[mirror_qemu.git] / target-mips / machine.c

#include "hw/hw.h"

#include "cpu.h"

/* FPU state */

static int get_fpr(QEMUFile *f, void *pv, size_t size)
{
    fpr_t *v = pv;
    qemu_get_be64s(f, &v->d);
    return 0;
}

static void put_fpr(QEMUFile *f, void *pv, size_t size)
{
    fpr_t *v = pv;
    qemu_put_be64s(f, &v->d);
}

const VMStateInfo vmstate_info_fpr = {
    .name = "fpr",
    .get  = get_fpr,
    .put  = put_fpr,
};

#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                     \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)

#define VMSTATE_FPR_ARRAY(_f, _s, _n)                           \
    VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)

static VMStateField vmstate_fpu_fields[] = {
    VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
    VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext),
    VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext),
    VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext),
    VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
    VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
    VMSTATE_END_OF_LIST()
};

const VMStateDescription vmstate_fpu = {
    .name = "cpu/fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_fpu_fields
};

const VMStateDescription vmstate_inactive_fpu = {
    .name = "cpu/inactive_fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_fpu_fields
};

/* TC state */

static VMStateField vmstate_tc_fields[] = {
    VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
    VMSTATE_UINTTL(PC, TCState),
    VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL(DSPControl, TCState),
    VMSTATE_INT32(CP0_TCStatus, TCState),
    VMSTATE_INT32(CP0_TCBind, TCState),
    VMSTATE_UINTTL(CP0_TCHalt, TCState),
    VMSTATE_UINTTL(CP0_TCContext, TCState),
    VMSTATE_UINTTL(CP0_TCSchedule, TCState),
    VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
    VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
    VMSTATE_UINTTL(CP0_UserLocal, TCState),
    VMSTATE_END_OF_LIST()
};

const VMStateDescription vmstate_tc = {
    .name = "cpu/tc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_tc_fields
};

const VMStateDescription vmstate_inactive_tc = {
    .name = "cpu/inactive_tc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_tc_fields
};

/* MVP state */

const VMStateDescription vmstate_mvp = {
    .name = "cpu/mvp",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
        VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
        VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
        VMSTATE_END_OF_LIST()
    }
};

/* TLB state */

static int get_tlb(QEMUFile *f, void *pv, size_t size)
{
    r4k_tlb_t *v = pv;
    uint16_t flags;

    qemu_get_betls(f, &v->VPN);
    qemu_get_be32s(f, &v->PageMask);
    qemu_get_8s(f, &v->ASID);
    qemu_get_be16s(f, &flags);
    v->G = (flags >> 10) & 1;
    v->C0 = (flags >> 7) & 3;
    v->C1 = (flags >> 4) & 3;
    v->V0 = (flags >> 3) & 1;
    v->V1 = (flags >> 2) & 1;
    v->D0 = (flags >> 1) & 1;
    v->D1 = (flags >> 0) & 1;
    v->EHINV = (flags >> 15) & 1;
    v->RI1 = (flags >> 14) & 1;
    v->RI0 = (flags >> 13) & 1;
    v->XI1 = (flags >> 12) & 1;
    v->XI0 = (flags >> 11) & 1;
    qemu_get_betls(f, &v->PFN[0]);
    qemu_get_betls(f, &v->PFN[1]);

    return 0;
}

static void put_tlb(QEMUFile *f, void *pv, size_t size)
{
    r4k_tlb_t *v = pv;

    uint16_t flags = ((v->EHINV << 15) |
                      (v->RI1 << 14) |
                      (v->RI0 << 13) |
                      (v->XI1 << 12) |
                      (v->XI0 << 11) |
                      (v->G << 10) |
                      (v->C0 << 7) |
                      (v->C1 << 4) |
                      (v->V0 << 3) |
                      (v->V1 << 2) |
                      (v->D0 << 1) |
                      (v->D1 << 0));

    qemu_put_betls(f, &v->VPN);
    qemu_put_be32s(f, &v->PageMask);
    qemu_put_8s(f, &v->ASID);
    qemu_put_be16s(f, &flags);
    qemu_put_betls(f, &v->PFN[0]);
    qemu_put_betls(f, &v->PFN[1]);
}

const VMStateInfo vmstate_info_tlb = {
    .name = "tlb_entry",
    .get  = get_tlb,
    .put  = put_tlb,
};

#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v)                     \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)

#define VMSTATE_TLB_ARRAY(_f, _s, _n)                           \
    VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)

const VMStateDescription vmstate_tlb = {
    .name = "cpu/tlb",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
        VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
        VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
        VMSTATE_END_OF_LIST()
    }
};

/* MIPS CPU state */

const VMStateDescription vmstate_mips_cpu = {
    .name = "cpu",
    .version_id = 5,
    .minimum_version_id = 5,
    .fields = (VMStateField[]) {
        /* Active TC */
        VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),

        /* Active FPU */
        VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
                       CPUMIPSFPUContext),

        /* MVP */
        VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
                               CPUMIPSMVPContext),

        /* TLB */
        VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
                               CPUMIPSTLBContext),

        /* CPU metastate */
        VMSTATE_UINT32(env.current_tc, MIPSCPU),
        VMSTATE_UINT32(env.current_fpu, MIPSCPU),
        VMSTATE_INT32(env.error_code, MIPSCPU),
        VMSTATE_UINT32(env.hflags, MIPSCPU),
        VMSTATE_UINTTL(env.btarget, MIPSCPU),
        VMSTATE_UINTTL(env.bcond, MIPSCPU),

        /* Remaining CP0 registers */
        VMSTATE_INT32(env.CP0_Index, MIPSCPU),
        VMSTATE_INT32(env.CP0_Random, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EntryLo0, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EntryLo1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
        VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
        VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
        VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
        VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
        VMSTATE_INT32(env.CP0_Count, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
        VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
        VMSTATE_INT32(env.CP0_Status, MIPSCPU),
        VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
        VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
        VMSTATE_INT32(env.CP0_EBase, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
        VMSTATE_UINTTL(env.lladdr, MIPSCPU),
        VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
        VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
        VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
        VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
        VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
        VMSTATE_INT32(env.CP0_TagLo, MIPSCPU),
        VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
        VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
        VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
        VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),

        /* Inactive TC */
        VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
                             vmstate_inactive_tc, TCState),
        VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
                             vmstate_inactive_fpu, CPUMIPSFPUContext),

        VMSTATE_END_OF_LIST()
    },
};
Commit	Line	Data
8dd3dca3	1	#include "hw/hw.h"
8dd3dca3	2
2b41f10e	3	#include "cpu.h"
33a84765	4
04cd7962 LA	5	/* FPU state */
	6
	7	static int get_fpr(QEMUFile f, void pv, size_t size)
33a84765	8	{
04cd7962 LA	9	fpr_t *v = pv;
	10	qemu_get_be64s(f, &v->d);
	11	return 0;
33a84765 TS	12	}
33a84765 TS	13
04cd7962	14	static void put_fpr(QEMUFile f, void pv, size_t size)
33a84765	15	{
04cd7962 LA	16	fpr_t *v = pv;
04cd7962 LA	17	qemu_put_be64s(f, &v->d);
33a84765 TS	18	}
33a84765 TS	19
04cd7962 LA	20	const VMStateInfo vmstate_info_fpr = {
	21	.name = "fpr",
	22	.get = get_fpr,
	23	.put = put_fpr,
	24	};
	25
	26	#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
	27	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
	28
	29	#define VMSTATE_FPR_ARRAY(_f, _s, _n) \
	30	VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
	31
	32	static VMStateField vmstate_fpu_fields[] = {
	33	VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
	34	VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext),
	35	VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext),
	36	VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext),
	37	VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
	38	VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
	39	VMSTATE_END_OF_LIST()
	40	};
	41
	42	const VMStateDescription vmstate_fpu = {
	43	.name = "cpu/fpu",
	44	.version_id = 1,
	45	.minimum_version_id = 1,
	46	.fields = vmstate_fpu_fields
	47	};
	48
	49	const VMStateDescription vmstate_inactive_fpu = {
	50	.name = "cpu/inactive_fpu",
	51	.version_id = 1,
	52	.minimum_version_id = 1,
	53	.fields = vmstate_fpu_fields
	54	};
33a84765	55
04cd7962 LA	56	/* TC state */
	57
	58	static VMStateField vmstate_tc_fields[] = {
	59	VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
	60	VMSTATE_UINTTL(PC, TCState),
	61	VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
	62	VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
	63	VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
	64	VMSTATE_UINTTL(DSPControl, TCState),
	65	VMSTATE_INT32(CP0_TCStatus, TCState),
	66	VMSTATE_INT32(CP0_TCBind, TCState),
	67	VMSTATE_UINTTL(CP0_TCHalt, TCState),
	68	VMSTATE_UINTTL(CP0_TCContext, TCState),
	69	VMSTATE_UINTTL(CP0_TCSchedule, TCState),
	70	VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
	71	VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
	72	VMSTATE_UINTTL(CP0_UserLocal, TCState),
	73	VMSTATE_END_OF_LIST()
	74	};
	75
	76	const VMStateDescription vmstate_tc = {
	77	.name = "cpu/tc",
	78	.version_id = 1,
	79	.minimum_version_id = 1,
	80	.fields = vmstate_tc_fields
	81	};
	82
	83	const VMStateDescription vmstate_inactive_tc = {
	84	.name = "cpu/inactive_tc",
	85	.version_id = 1,
	86	.minimum_version_id = 1,
	87	.fields = vmstate_tc_fields
	88	};
	89
	90	/* MVP state */
	91
	92	const VMStateDescription vmstate_mvp = {
	93	.name = "cpu/mvp",
	94	.version_id = 1,
	95	.minimum_version_id = 1,
	96	.fields = (VMStateField[]) {
	97	VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
	98	VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
	99	VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
	100	VMSTATE_END_OF_LIST()
460c81f1	101	}
04cd7962	102	};
33a84765	103
04cd7962	104	/* TLB state */
33a84765	105
04cd7962	106	static int get_tlb(QEMUFile f, void pv, size_t size)
33a84765	107	{
04cd7962 LA	108	r4k_tlb_t *v = pv;
	109	uint16_t flags;
	110
	111	qemu_get_betls(f, &v->VPN);
	112	qemu_get_be32s(f, &v->PageMask);
	113	qemu_get_8s(f, &v->ASID);
	114	qemu_get_be16s(f, &flags);
	115	v->G = (flags >> 10) & 1;
	116	v->C0 = (flags >> 7) & 3;
	117	v->C1 = (flags >> 4) & 3;
	118	v->V0 = (flags >> 3) & 1;
	119	v->V1 = (flags >> 2) & 1;
	120	v->D0 = (flags >> 1) & 1;
	121	v->D1 = (flags >> 0) & 1;
	122	v->EHINV = (flags >> 15) & 1;
	123	v->RI1 = (flags >> 14) & 1;
	124	v->RI0 = (flags >> 13) & 1;
	125	v->XI1 = (flags >> 12) & 1;
	126	v->XI0 = (flags >> 11) & 1;
	127	qemu_get_betls(f, &v->PFN[0]);
	128	qemu_get_betls(f, &v->PFN[1]);
	129
	130	return 0;
33a84765 TS	131	}
33a84765 TS	132
04cd7962	133	static void put_tlb(QEMUFile f, void pv, size_t size)
33a84765	134	{
04cd7962 LA	135	r4k_tlb_t *v = pv;
	136
	137	uint16_t flags = ((v->EHINV << 15) \|
	138	(v->RI1 << 14) \|
	139	(v->RI0 << 13) \|
	140	(v->XI1 << 12) \|
	141	(v->XI0 << 11) \|
	142	(v->G << 10) \|
	143	(v->C0 << 7) \|
	144	(v->C1 << 4) \|
	145	(v->V0 << 3) \|
	146	(v->V1 << 2) \|
	147	(v->D0 << 1) \|
	148	(v->D1 << 0));
	149
	150	qemu_put_betls(f, &v->VPN);
	151	qemu_put_be32s(f, &v->PageMask);
	152	qemu_put_8s(f, &v->ASID);
	153	qemu_put_be16s(f, &flags);
	154	qemu_put_betls(f, &v->PFN[0]);
	155	qemu_put_betls(f, &v->PFN[1]);
8dd3dca3 AJ	156	}
8dd3dca3 AJ	157
04cd7962 LA	158	const VMStateInfo vmstate_info_tlb = {
	159	.name = "tlb_entry",
	160	.get = get_tlb,
	161	.put = put_tlb,
	162	};
33a84765	163
04cd7962 LA	164	#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
04cd7962 LA	165	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
33a84765	166
04cd7962 LA	167	#define VMSTATE_TLB_ARRAY(_f, _s, _n) \
04cd7962 LA	168	VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
33a84765	169
04cd7962 LA	170	const VMStateDescription vmstate_tlb = {
	171	.name = "cpu/tlb",
	172	.version_id = 1,
	173	.minimum_version_id = 1,
	174	.fields = (VMStateField[]) {
	175	VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
	176	VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
	177	VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
	178	VMSTATE_END_OF_LIST()
460c81f1	179	}
04cd7962	180	};
33a84765	181
04cd7962	182	/* MIPS CPU state */
33a84765	183
04cd7962 LA	184	const VMStateDescription vmstate_mips_cpu = {
	185	.name = "cpu",
	186	.version_id = 5,
	187	.minimum_version_id = 5,
	188	.fields = (VMStateField[]) {
	189	/* Active TC */
	190	VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
	191
	192	/* Active FPU */
	193	VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
	194	CPUMIPSFPUContext),
	195
	196	/* MVP */
	197	VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
	198	CPUMIPSMVPContext),
	199
	200	/* TLB */
	201	VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
	202	CPUMIPSTLBContext),
	203
	204	/* CPU metastate */
	205	VMSTATE_UINT32(env.current_tc, MIPSCPU),
	206	VMSTATE_UINT32(env.current_fpu, MIPSCPU),
	207	VMSTATE_INT32(env.error_code, MIPSCPU),
	208	VMSTATE_UINT32(env.hflags, MIPSCPU),
	209	VMSTATE_UINTTL(env.btarget, MIPSCPU),
	210	VMSTATE_UINTTL(env.bcond, MIPSCPU),
	211
	212	/* Remaining CP0 registers */
	213	VMSTATE_INT32(env.CP0_Index, MIPSCPU),
	214	VMSTATE_INT32(env.CP0_Random, MIPSCPU),
	215	VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
	216	VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
	217	VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
	218	VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
	219	VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
	220	VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
	221	VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
	222	VMSTATE_UINTTL(env.CP0_EntryLo0, MIPSCPU),
	223	VMSTATE_UINTTL(env.CP0_EntryLo1, MIPSCPU),
	224	VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
	225	VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
	226	VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
	227	VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
	228	VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
	229	VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
	230	VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
	231	VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
	232	VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
	233	VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
	234	VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
	235	VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
	236	VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
	237	VMSTATE_INT32(env.CP0_Count, MIPSCPU),
	238	VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
	239	VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
	240	VMSTATE_INT32(env.CP0_Status, MIPSCPU),
	241	VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
	242	VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
	243	VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
	244	VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
	245	VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
	246	VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
	247	VMSTATE_INT32(env.CP0_EBase, MIPSCPU),
248	VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
249	VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
250	VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
251	VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
252	VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
253	VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
254	VMSTATE_UINTTL(env.lladdr, MIPSCPU),
255	VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
256	VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
257	VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
258	VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
259	VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
260	VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
261	VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
262	VMSTATE_INT32(env.CP0_TagLo, MIPSCPU),
263	VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
264	VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
265	VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
266	VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
267	VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
268	VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
269
270	/* Inactive TC */
271	VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
272	vmstate_inactive_tc, TCState),
273	VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
274	vmstate_inactive_fpu, CPUMIPSFPUContext),
275
276	VMSTATE_END_OF_LIST()
277	},
278	};