[mirror_qemu.git] / target-mips / machine.c

#include "hw/hw.h"

#include "cpu.h"

static int cpu_post_load(void *opaque, int version_id)
{
    MIPSCPU *cpu = opaque;
    CPUMIPSState *env = &cpu->env;

    restore_fp_status(env);
    restore_msa_fp_status(env);
    compute_hflags(env);

    return 0;
}

/* FPU state */

static int get_fpr(QEMUFile *f, void *pv, size_t size)
{
    int i;
    fpr_t *v = pv;
    /* Restore entire MSA vector register */
    for (i = 0; i < MSA_WRLEN/64; i++) {
        qemu_get_sbe64s(f, &v->wr.d[i]);
    }
    return 0;
}

static void put_fpr(QEMUFile *f, void *pv, size_t size)
{
    int i;
    fpr_t *v = pv;
    /* Save entire MSA vector register */
    for (i = 0; i < MSA_WRLEN/64; i++) {
        qemu_put_sbe64s(f, &v->wr.d[i]);
    }
}

const VMStateInfo vmstate_info_fpr = {
    .name = "fpr",
    .get  = get_fpr,
    .put  = put_fpr,
};

#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                     \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)

#define VMSTATE_FPR_ARRAY(_f, _s, _n)                           \
    VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)

static VMStateField vmstate_fpu_fields[] = {
    VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
    VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
    VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
    VMSTATE_END_OF_LIST()
};

const VMStateDescription vmstate_fpu = {
    .name = "cpu/fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_fpu_fields
};

const VMStateDescription vmstate_inactive_fpu = {
    .name = "cpu/inactive_fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_fpu_fields
};

/* TC state */

static VMStateField vmstate_tc_fields[] = {
    VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
    VMSTATE_UINTTL(PC, TCState),
    VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
    VMSTATE_UINTTL(DSPControl, TCState),
    VMSTATE_INT32(CP0_TCStatus, TCState),
    VMSTATE_INT32(CP0_TCBind, TCState),
    VMSTATE_UINTTL(CP0_TCHalt, TCState),
    VMSTATE_UINTTL(CP0_TCContext, TCState),
    VMSTATE_UINTTL(CP0_TCSchedule, TCState),
    VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
    VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
    VMSTATE_UINTTL(CP0_UserLocal, TCState),
    VMSTATE_INT32(msacsr, TCState),
    VMSTATE_END_OF_LIST()
};

const VMStateDescription vmstate_tc = {
    .name = "cpu/tc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_tc_fields
};

const VMStateDescription vmstate_inactive_tc = {
    .name = "cpu/inactive_tc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = vmstate_tc_fields
};

/* MVP state */

const VMStateDescription vmstate_mvp = {
    .name = "cpu/mvp",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
        VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
        VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
        VMSTATE_END_OF_LIST()
    }
};

/* TLB state */

static int get_tlb(QEMUFile *f, void *pv, size_t size)
{
    r4k_tlb_t *v = pv;
    uint16_t flags;

    qemu_get_betls(f, &v->VPN);
    qemu_get_be32s(f, &v->PageMask);
    qemu_get_8s(f, &v->ASID);
    qemu_get_be16s(f, &flags);
    v->G = (flags >> 10) & 1;
    v->C0 = (flags >> 7) & 3;
    v->C1 = (flags >> 4) & 3;
    v->V0 = (flags >> 3) & 1;
    v->V1 = (flags >> 2) & 1;
    v->D0 = (flags >> 1) & 1;
    v->D1 = (flags >> 0) & 1;
    v->EHINV = (flags >> 15) & 1;
    v->RI1 = (flags >> 14) & 1;
    v->RI0 = (flags >> 13) & 1;
    v->XI1 = (flags >> 12) & 1;
    v->XI0 = (flags >> 11) & 1;
    qemu_get_betls(f, &v->PFN[0]);
    qemu_get_betls(f, &v->PFN[1]);

    return 0;
}

static void put_tlb(QEMUFile *f, void *pv, size_t size)
{
    r4k_tlb_t *v = pv;

    uint16_t flags = ((v->EHINV << 15) |
                      (v->RI1 << 14) |
                      (v->RI0 << 13) |
                      (v->XI1 << 12) |
                      (v->XI0 << 11) |
                      (v->G << 10) |
                      (v->C0 << 7) |
                      (v->C1 << 4) |
                      (v->V0 << 3) |
                      (v->V1 << 2) |
                      (v->D0 << 1) |
                      (v->D1 << 0));

    qemu_put_betls(f, &v->VPN);
    qemu_put_be32s(f, &v->PageMask);
    qemu_put_8s(f, &v->ASID);
    qemu_put_be16s(f, &flags);
    qemu_put_betls(f, &v->PFN[0]);
    qemu_put_betls(f, &v->PFN[1]);
}

const VMStateInfo vmstate_info_tlb = {
    .name = "tlb_entry",
    .get  = get_tlb,
    .put  = put_tlb,
};

#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v)                     \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)

#define VMSTATE_TLB_ARRAY(_f, _s, _n)                           \
    VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)

const VMStateDescription vmstate_tlb = {
    .name = "cpu/tlb",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
        VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
        VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
        VMSTATE_END_OF_LIST()
    }
};

/* MIPS CPU state */

const VMStateDescription vmstate_mips_cpu = {
    .name = "cpu",
    .version_id = 6,
    .minimum_version_id = 6,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        /* Active TC */
        VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),

        /* Active FPU */
        VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
                       CPUMIPSFPUContext),

        /* MVP */
        VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
                               CPUMIPSMVPContext),

        /* TLB */
        VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
                               CPUMIPSTLBContext),

        /* CPU metastate */
        VMSTATE_UINT32(env.current_tc, MIPSCPU),
        VMSTATE_UINT32(env.current_fpu, MIPSCPU),
        VMSTATE_INT32(env.error_code, MIPSCPU),
        VMSTATE_UINTTL(env.btarget, MIPSCPU),
        VMSTATE_UINTTL(env.bcond, MIPSCPU),

        /* Remaining CP0 registers */
        VMSTATE_INT32(env.CP0_Index, MIPSCPU),
        VMSTATE_INT32(env.CP0_Random, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
        VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EntryLo0, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EntryLo1, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
        VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
        VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
        VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
        VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
        VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
        VMSTATE_INT32(env.CP0_Count, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
        VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
        VMSTATE_INT32(env.CP0_Status, MIPSCPU),
        VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
        VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
        VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
        VMSTATE_INT32(env.CP0_EBase, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
        VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
        VMSTATE_UINTTL(env.lladdr, MIPSCPU),
        VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
        VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
        VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
        VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
        VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
        VMSTATE_INT32(env.CP0_TagLo, MIPSCPU),
        VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
        VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
        VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
        VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
        VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
        VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),

        /* Inactive TC */
        VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
                             vmstate_inactive_tc, TCState),
        VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
                             vmstate_inactive_fpu, CPUMIPSFPUContext),

        VMSTATE_END_OF_LIST()
    },
};
Commit	Line	Data
8dd3dca3	1	#include "hw/hw.h"
8dd3dca3	2
2b41f10e	3	#include "cpu.h"
33a84765	4
64451111 LA	5	static int cpu_post_load(void *opaque, int version_id)
	6	{
	7	MIPSCPU *cpu = opaque;
	8	CPUMIPSState *env = &cpu->env;
	9
	10	restore_fp_status(env);
	11	restore_msa_fp_status(env);
	12	compute_hflags(env);
	13
	14	return 0;
	15	}
	16
04cd7962 LA	17	/* FPU state */
	18
	19	static int get_fpr(QEMUFile f, void pv, size_t size)
33a84765	20	{
64451111	21	int i;
04cd7962	22	fpr_t *v = pv;
64451111 LA	23	/* Restore entire MSA vector register */
	24	for (i = 0; i < MSA_WRLEN/64; i++) {
	25	qemu_get_sbe64s(f, &v->wr.d[i]);
	26	}
04cd7962	27	return 0;
33a84765 TS	28	}
33a84765 TS	29
04cd7962	30	static void put_fpr(QEMUFile f, void pv, size_t size)
33a84765	31	{
64451111	32	int i;
04cd7962	33	fpr_t *v = pv;
64451111 LA	34	/* Save entire MSA vector register */
	35	for (i = 0; i < MSA_WRLEN/64; i++) {
	36	qemu_put_sbe64s(f, &v->wr.d[i]);
	37	}
33a84765 TS	38	}
33a84765 TS	39
04cd7962 LA	40	const VMStateInfo vmstate_info_fpr = {
	41	.name = "fpr",
	42	.get = get_fpr,
	43	.put = put_fpr,
	44	};
	45
	46	#define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \
	47	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
	48
	49	#define VMSTATE_FPR_ARRAY(_f, _s, _n) \
	50	VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
	51
	52	static VMStateField vmstate_fpu_fields[] = {
	53	VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
04cd7962 LA	54	VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
	55	VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
	56	VMSTATE_END_OF_LIST()
	57	};
	58
	59	const VMStateDescription vmstate_fpu = {
	60	.name = "cpu/fpu",
	61	.version_id = 1,
	62	.minimum_version_id = 1,
	63	.fields = vmstate_fpu_fields
	64	};
	65
	66	const VMStateDescription vmstate_inactive_fpu = {
	67	.name = "cpu/inactive_fpu",
	68	.version_id = 1,
	69	.minimum_version_id = 1,
	70	.fields = vmstate_fpu_fields
	71	};
33a84765	72
04cd7962 LA	73	/* TC state */
	74
	75	static VMStateField vmstate_tc_fields[] = {
	76	VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
	77	VMSTATE_UINTTL(PC, TCState),
	78	VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
	79	VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
	80	VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
	81	VMSTATE_UINTTL(DSPControl, TCState),
	82	VMSTATE_INT32(CP0_TCStatus, TCState),
	83	VMSTATE_INT32(CP0_TCBind, TCState),
	84	VMSTATE_UINTTL(CP0_TCHalt, TCState),
	85	VMSTATE_UINTTL(CP0_TCContext, TCState),
	86	VMSTATE_UINTTL(CP0_TCSchedule, TCState),
	87	VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
	88	VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
	89	VMSTATE_UINTTL(CP0_UserLocal, TCState),
64451111	90	VMSTATE_INT32(msacsr, TCState),
04cd7962 LA	91	VMSTATE_END_OF_LIST()
	92	};
	93
	94	const VMStateDescription vmstate_tc = {
	95	.name = "cpu/tc",
	96	.version_id = 1,
	97	.minimum_version_id = 1,
	98	.fields = vmstate_tc_fields
	99	};
	100
	101	const VMStateDescription vmstate_inactive_tc = {
	102	.name = "cpu/inactive_tc",
	103	.version_id = 1,
	104	.minimum_version_id = 1,
	105	.fields = vmstate_tc_fields
	106	};
	107
	108	/* MVP state */
	109
	110	const VMStateDescription vmstate_mvp = {
	111	.name = "cpu/mvp",
	112	.version_id = 1,
	113	.minimum_version_id = 1,
	114	.fields = (VMStateField[]) {
	115	VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
	116	VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
	117	VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
	118	VMSTATE_END_OF_LIST()
460c81f1	119	}
04cd7962	120	};
33a84765	121
04cd7962	122	/* TLB state */
33a84765	123
04cd7962	124	static int get_tlb(QEMUFile f, void pv, size_t size)
33a84765	125	{
04cd7962 LA	126	r4k_tlb_t *v = pv;
	127	uint16_t flags;
	128
	129	qemu_get_betls(f, &v->VPN);
	130	qemu_get_be32s(f, &v->PageMask);
	131	qemu_get_8s(f, &v->ASID);
	132	qemu_get_be16s(f, &flags);
	133	v->G = (flags >> 10) & 1;
	134	v->C0 = (flags >> 7) & 3;
	135	v->C1 = (flags >> 4) & 3;
	136	v->V0 = (flags >> 3) & 1;
	137	v->V1 = (flags >> 2) & 1;
	138	v->D0 = (flags >> 1) & 1;
	139	v->D1 = (flags >> 0) & 1;
	140	v->EHINV = (flags >> 15) & 1;
	141	v->RI1 = (flags >> 14) & 1;
	142	v->RI0 = (flags >> 13) & 1;
	143	v->XI1 = (flags >> 12) & 1;
	144	v->XI0 = (flags >> 11) & 1;
	145	qemu_get_betls(f, &v->PFN[0]);
	146	qemu_get_betls(f, &v->PFN[1]);
	147
	148	return 0;
33a84765 TS	149	}
33a84765 TS	150
04cd7962	151	static void put_tlb(QEMUFile f, void pv, size_t size)
33a84765	152	{
04cd7962 LA	153	r4k_tlb_t *v = pv;
	154
	155	uint16_t flags = ((v->EHINV << 15) \|
	156	(v->RI1 << 14) \|
	157	(v->RI0 << 13) \|
	158	(v->XI1 << 12) \|
	159	(v->XI0 << 11) \|
	160	(v->G << 10) \|
	161	(v->C0 << 7) \|
	162	(v->C1 << 4) \|
	163	(v->V0 << 3) \|
	164	(v->V1 << 2) \|
	165	(v->D0 << 1) \|
	166	(v->D1 << 0));
	167
	168	qemu_put_betls(f, &v->VPN);
	169	qemu_put_be32s(f, &v->PageMask);
	170	qemu_put_8s(f, &v->ASID);
	171	qemu_put_be16s(f, &flags);
	172	qemu_put_betls(f, &v->PFN[0]);
	173	qemu_put_betls(f, &v->PFN[1]);
8dd3dca3 AJ	174	}
8dd3dca3 AJ	175
04cd7962 LA	176	const VMStateInfo vmstate_info_tlb = {
	177	.name = "tlb_entry",
	178	.get = get_tlb,
	179	.put = put_tlb,
	180	};
33a84765	181
04cd7962 LA	182	#define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \
04cd7962 LA	183	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
33a84765	184
04cd7962 LA	185	#define VMSTATE_TLB_ARRAY(_f, _s, _n) \
04cd7962 LA	186	VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
33a84765	187
04cd7962 LA	188	const VMStateDescription vmstate_tlb = {
	189	.name = "cpu/tlb",
	190	.version_id = 1,
	191	.minimum_version_id = 1,
	192	.fields = (VMStateField[]) {
	193	VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
	194	VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
	195	VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
	196	VMSTATE_END_OF_LIST()
460c81f1	197	}
04cd7962	198	};
33a84765	199
04cd7962	200	/* MIPS CPU state */
33a84765	201
04cd7962 LA	202	const VMStateDescription vmstate_mips_cpu = {
04cd7962 LA	203	.name = "cpu",
64451111 LA	204	.version_id = 6,
	205	.minimum_version_id = 6,
	206	.post_load = cpu_post_load,
04cd7962 LA	207	.fields = (VMStateField[]) {
	208	/* Active TC */
	209	VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
	210
	211	/* Active FPU */
	212	VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
	213	CPUMIPSFPUContext),
	214
	215	/* MVP */
	216	VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
	217	CPUMIPSMVPContext),
	218
	219	/* TLB */
	220	VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
	221	CPUMIPSTLBContext),
	222
	223	/* CPU metastate */
	224	VMSTATE_UINT32(env.current_tc, MIPSCPU),
	225	VMSTATE_UINT32(env.current_fpu, MIPSCPU),
	226	VMSTATE_INT32(env.error_code, MIPSCPU),
04cd7962 LA	227	VMSTATE_UINTTL(env.btarget, MIPSCPU),
	228	VMSTATE_UINTTL(env.bcond, MIPSCPU),
	229
	230	/* Remaining CP0 registers */
	231	VMSTATE_INT32(env.CP0_Index, MIPSCPU),
	232	VMSTATE_INT32(env.CP0_Random, MIPSCPU),
	233	VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
	234	VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
	235	VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
	236	VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
	237	VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
	238	VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
	239	VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
	240	VMSTATE_UINTTL(env.CP0_EntryLo0, MIPSCPU),
	241	VMSTATE_UINTTL(env.CP0_EntryLo1, MIPSCPU),
	242	VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
	243	VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
	244	VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
	245	VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
	246	VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
	247	VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
	248	VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
	249	VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
	250	VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
	251	VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
	252	VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
	253	VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
	254	VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
	255	VMSTATE_INT32(env.CP0_Count, MIPSCPU),
	256	VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
	257	VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
	258	VMSTATE_INT32(env.CP0_Status, MIPSCPU),
	259	VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
	260	VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
	261	VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
	262	VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
	263	VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
	264	VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
	265	VMSTATE_INT32(env.CP0_EBase, MIPSCPU),
	266	VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
	267	VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
	268	VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
	269	VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
	270	VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
	271	VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
	272	VMSTATE_UINTTL(env.lladdr, MIPSCPU),
	273	VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
	274	VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
	275	VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
	276	VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
	277	VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
	278	VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
	279	VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
	280	VMSTATE_INT32(env.CP0_TagLo, MIPSCPU),
	281	VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
	282	VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
	283	VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
	284	VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
	285	VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
	286	VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
	287
	288	/* Inactive TC */
	289	VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
	290	vmstate_inactive_tc, TCState),
291	VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
292	vmstate_inactive_fpu, CPUMIPSFPUContext),
293
294	VMSTATE_END_OF_LIST()
295	},
296	};