projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 6af0bf9c FB |
1 | #if !defined (__QEMU_MIPS_DEFS_H__) |
| 2 | #define __QEMU_MIPS_DEFS_H__ | |
| 3 | ||
| 6af0bf9c FB |
4 | /* If we want to use host float regs... */ |
| 5 | //#define USE_HOST_FLOAT_REGS | |
| 6 | ||
| 6af0bf9c FB |
7 | /* real pages are variable size... */ |
| 8 | #define TARGET_PAGE_BITS 12 | |
| 814b9a47 | 9 | #define MIPS_TLB_MAX 128 |
| 6af0bf9c | 10 | |
| 540635ba | 11 | #if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64) |
| c570fd16 TS |
12 | #define TARGET_LONG_BITS 64 |
| 13 | #else | |
| 14 | #define TARGET_LONG_BITS 32 | |
| 15 | #endif | |
| 16 | ||
| e189e748 TS |
17 | /* Masks used to mark instructions to indicate which ISA level they |
| 18 | were introduced in. */ | |
| 19 | #define ISA_MIPS1 0x00000001 | |
| 20 | #define ISA_MIPS2 0x00000002 | |
| 21 | #define ISA_MIPS3 0x00000004 | |
| 22 | #define ISA_MIPS4 0x00000008 | |
| 23 | #define ISA_MIPS5 0x00000010 | |
| 24 | #define ISA_MIPS32 0x00000020 | |
| 25 | #define ISA_MIPS32R2 0x00000040 | |
| 26 | #define ISA_MIPS64 0x00000080 | |
| 27 | #define ISA_MIPS64R2 0x00000100 | |
| 28 | ||
| 29 | /* MIPS ASE */ | |
| 30 | #define ASE_MIPS16 0x00001000 | |
| 31 | #define ASE_MIPS3D 0x00002000 | |
| 32 | #define ASE_MDMX 0x00004000 | |
| 33 | #define ASE_DSP 0x00008000 | |
| 34 | #define ASE_DSPR2 0x00010000 | |
| 35 | ||
| 36 | /* Chip specific instructions. */ | |
| 37 | /* Currently void */ | |
| 38 | ||
| 39 | /* MIPS CPU defines. */ | |
| 40 | #define CPU_MIPS1 (ISA_MIPS1) | |
| 41 | #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) | |
| 42 | #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) | |
| 43 | #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) | |
| 44 | #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) | |
| 45 | ||
| 46 | #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) | |
| 47 | #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) | |
| 48 | ||
| 49 | #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) | |
| 50 | #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) | |
| 51 | ||
| 19221bda TS |
52 | /* Strictly follow the architecture standard: |
| 53 | - Disallow "special" instruction handling for PMON/SPIM. | |
| 54 | Note that we still maintain Count/Compare to match the host clock. */ | |
| b48cfdff TS |
55 | //#define MIPS_STRICT_STANDARD 1 |
| 56 | ||
| 6af0bf9c | 57 | #endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |