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Commit | Line | Data |
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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation micro-operations for qemu. | |
3 | * | |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer | |
6ea83fed | 5 | * Copyright (c) 2006 Marius Groeger (FPU operations) |
6af0bf9c FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include "config.h" | |
23 | #include "exec.h" | |
24 | ||
1b351e52 FB |
25 | #ifndef CALL_FROM_TB0 |
26 | #define CALL_FROM_TB0(func) func(); | |
27 | #endif | |
28 | #ifndef CALL_FROM_TB1 | |
29 | #define CALL_FROM_TB1(func, arg0) func(arg0); | |
30 | #endif | |
31 | #ifndef CALL_FROM_TB1_CONST16 | |
32 | #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0); | |
33 | #endif | |
34 | #ifndef CALL_FROM_TB2 | |
35 | #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1); | |
36 | #endif | |
37 | #ifndef CALL_FROM_TB2_CONST16 | |
38 | #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \ | |
39 | CALL_FROM_TB2(func, arg0, arg1); | |
40 | #endif | |
41 | #ifndef CALL_FROM_TB3 | |
42 | #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2); | |
43 | #endif | |
44 | #ifndef CALL_FROM_TB4 | |
45 | #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \ | |
46 | func(arg0, arg1, arg2, arg3); | |
47 | #endif | |
48 | ||
6af0bf9c FB |
49 | #define REG 1 |
50 | #include "op_template.c" | |
51 | #undef REG | |
52 | #define REG 2 | |
53 | #include "op_template.c" | |
54 | #undef REG | |
55 | #define REG 3 | |
56 | #include "op_template.c" | |
57 | #undef REG | |
58 | #define REG 4 | |
59 | #include "op_template.c" | |
60 | #undef REG | |
61 | #define REG 5 | |
62 | #include "op_template.c" | |
63 | #undef REG | |
64 | #define REG 6 | |
65 | #include "op_template.c" | |
66 | #undef REG | |
67 | #define REG 7 | |
68 | #include "op_template.c" | |
69 | #undef REG | |
70 | #define REG 8 | |
71 | #include "op_template.c" | |
72 | #undef REG | |
73 | #define REG 9 | |
74 | #include "op_template.c" | |
75 | #undef REG | |
76 | #define REG 10 | |
77 | #include "op_template.c" | |
78 | #undef REG | |
79 | #define REG 11 | |
80 | #include "op_template.c" | |
81 | #undef REG | |
82 | #define REG 12 | |
83 | #include "op_template.c" | |
84 | #undef REG | |
85 | #define REG 13 | |
86 | #include "op_template.c" | |
87 | #undef REG | |
88 | #define REG 14 | |
89 | #include "op_template.c" | |
90 | #undef REG | |
91 | #define REG 15 | |
92 | #include "op_template.c" | |
93 | #undef REG | |
94 | #define REG 16 | |
95 | #include "op_template.c" | |
96 | #undef REG | |
97 | #define REG 17 | |
98 | #include "op_template.c" | |
99 | #undef REG | |
100 | #define REG 18 | |
101 | #include "op_template.c" | |
102 | #undef REG | |
103 | #define REG 19 | |
104 | #include "op_template.c" | |
105 | #undef REG | |
106 | #define REG 20 | |
107 | #include "op_template.c" | |
108 | #undef REG | |
109 | #define REG 21 | |
110 | #include "op_template.c" | |
111 | #undef REG | |
112 | #define REG 22 | |
113 | #include "op_template.c" | |
114 | #undef REG | |
115 | #define REG 23 | |
116 | #include "op_template.c" | |
117 | #undef REG | |
118 | #define REG 24 | |
119 | #include "op_template.c" | |
120 | #undef REG | |
121 | #define REG 25 | |
122 | #include "op_template.c" | |
123 | #undef REG | |
124 | #define REG 26 | |
125 | #include "op_template.c" | |
126 | #undef REG | |
127 | #define REG 27 | |
128 | #include "op_template.c" | |
129 | #undef REG | |
130 | #define REG 28 | |
131 | #include "op_template.c" | |
132 | #undef REG | |
133 | #define REG 29 | |
134 | #include "op_template.c" | |
135 | #undef REG | |
136 | #define REG 30 | |
137 | #include "op_template.c" | |
138 | #undef REG | |
139 | #define REG 31 | |
140 | #include "op_template.c" | |
141 | #undef REG | |
142 | ||
c570fd16 | 143 | #define TN |
6af0bf9c FB |
144 | #include "op_template.c" |
145 | #undef TN | |
146 | ||
6ea83fed FB |
147 | #define SFREG 0 |
148 | #define DFREG 0 | |
149 | #include "fop_template.c" | |
150 | #undef SFREG | |
151 | #undef DFREG | |
152 | #define SFREG 1 | |
153 | #include "fop_template.c" | |
154 | #undef SFREG | |
155 | #define SFREG 2 | |
156 | #define DFREG 2 | |
157 | #include "fop_template.c" | |
158 | #undef SFREG | |
159 | #undef DFREG | |
160 | #define SFREG 3 | |
161 | #include "fop_template.c" | |
162 | #undef SFREG | |
163 | #define SFREG 4 | |
164 | #define DFREG 4 | |
165 | #include "fop_template.c" | |
166 | #undef SFREG | |
167 | #undef DFREG | |
168 | #define SFREG 5 | |
169 | #include "fop_template.c" | |
170 | #undef SFREG | |
171 | #define SFREG 6 | |
172 | #define DFREG 6 | |
173 | #include "fop_template.c" | |
174 | #undef SFREG | |
175 | #undef DFREG | |
176 | #define SFREG 7 | |
177 | #include "fop_template.c" | |
178 | #undef SFREG | |
179 | #define SFREG 8 | |
180 | #define DFREG 8 | |
181 | #include "fop_template.c" | |
182 | #undef SFREG | |
183 | #undef DFREG | |
184 | #define SFREG 9 | |
185 | #include "fop_template.c" | |
186 | #undef SFREG | |
187 | #define SFREG 10 | |
188 | #define DFREG 10 | |
189 | #include "fop_template.c" | |
190 | #undef SFREG | |
191 | #undef DFREG | |
192 | #define SFREG 11 | |
193 | #include "fop_template.c" | |
194 | #undef SFREG | |
195 | #define SFREG 12 | |
196 | #define DFREG 12 | |
197 | #include "fop_template.c" | |
198 | #undef SFREG | |
199 | #undef DFREG | |
200 | #define SFREG 13 | |
201 | #include "fop_template.c" | |
202 | #undef SFREG | |
203 | #define SFREG 14 | |
204 | #define DFREG 14 | |
205 | #include "fop_template.c" | |
206 | #undef SFREG | |
207 | #undef DFREG | |
208 | #define SFREG 15 | |
209 | #include "fop_template.c" | |
210 | #undef SFREG | |
211 | #define SFREG 16 | |
212 | #define DFREG 16 | |
213 | #include "fop_template.c" | |
214 | #undef SFREG | |
215 | #undef DFREG | |
216 | #define SFREG 17 | |
217 | #include "fop_template.c" | |
218 | #undef SFREG | |
219 | #define SFREG 18 | |
220 | #define DFREG 18 | |
221 | #include "fop_template.c" | |
222 | #undef SFREG | |
223 | #undef DFREG | |
224 | #define SFREG 19 | |
225 | #include "fop_template.c" | |
226 | #undef SFREG | |
227 | #define SFREG 20 | |
228 | #define DFREG 20 | |
229 | #include "fop_template.c" | |
230 | #undef SFREG | |
231 | #undef DFREG | |
232 | #define SFREG 21 | |
233 | #include "fop_template.c" | |
234 | #undef SFREG | |
235 | #define SFREG 22 | |
236 | #define DFREG 22 | |
237 | #include "fop_template.c" | |
238 | #undef SFREG | |
239 | #undef DFREG | |
240 | #define SFREG 23 | |
241 | #include "fop_template.c" | |
242 | #undef SFREG | |
243 | #define SFREG 24 | |
244 | #define DFREG 24 | |
245 | #include "fop_template.c" | |
246 | #undef SFREG | |
247 | #undef DFREG | |
248 | #define SFREG 25 | |
249 | #include "fop_template.c" | |
250 | #undef SFREG | |
251 | #define SFREG 26 | |
252 | #define DFREG 26 | |
253 | #include "fop_template.c" | |
254 | #undef SFREG | |
255 | #undef DFREG | |
256 | #define SFREG 27 | |
257 | #include "fop_template.c" | |
258 | #undef SFREG | |
259 | #define SFREG 28 | |
260 | #define DFREG 28 | |
261 | #include "fop_template.c" | |
262 | #undef SFREG | |
263 | #undef DFREG | |
264 | #define SFREG 29 | |
265 | #include "fop_template.c" | |
266 | #undef SFREG | |
267 | #define SFREG 30 | |
268 | #define DFREG 30 | |
269 | #include "fop_template.c" | |
270 | #undef SFREG | |
271 | #undef DFREG | |
272 | #define SFREG 31 | |
273 | #include "fop_template.c" | |
274 | #undef SFREG | |
275 | ||
276 | #define FTN | |
277 | #include "fop_template.c" | |
278 | #undef FTN | |
279 | ||
6af0bf9c FB |
280 | void op_dup_T0 (void) |
281 | { | |
282 | T2 = T0; | |
283 | RETURN(); | |
284 | } | |
285 | ||
286 | void op_load_HI (void) | |
287 | { | |
288 | T0 = env->HI; | |
289 | RETURN(); | |
290 | } | |
291 | ||
292 | void op_store_HI (void) | |
293 | { | |
294 | env->HI = T0; | |
295 | RETURN(); | |
296 | } | |
297 | ||
298 | void op_load_LO (void) | |
299 | { | |
300 | T0 = env->LO; | |
301 | RETURN(); | |
302 | } | |
303 | ||
304 | void op_store_LO (void) | |
305 | { | |
306 | env->LO = T0; | |
307 | RETURN(); | |
308 | } | |
309 | ||
310 | /* Load and store */ | |
311 | #define MEMSUFFIX _raw | |
312 | #include "op_mem.c" | |
313 | #undef MEMSUFFIX | |
314 | #if !defined(CONFIG_USER_ONLY) | |
315 | #define MEMSUFFIX _user | |
316 | #include "op_mem.c" | |
317 | #undef MEMSUFFIX | |
318 | ||
319 | #define MEMSUFFIX _kernel | |
320 | #include "op_mem.c" | |
321 | #undef MEMSUFFIX | |
322 | #endif | |
323 | ||
324 | /* Arithmetic */ | |
325 | void op_add (void) | |
326 | { | |
5dc4b744 | 327 | T0 = (int32_t)((int32_t)T0 + (int32_t)T1); |
6af0bf9c FB |
328 | RETURN(); |
329 | } | |
330 | ||
331 | void op_addo (void) | |
332 | { | |
333 | target_ulong tmp; | |
334 | ||
c570fd16 TS |
335 | tmp = (int32_t)T0; |
336 | T0 = (int32_t)T0 + (int32_t)T1; | |
76e050c2 | 337 | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { |
c570fd16 | 338 | /* operands of same sign, result different sign */ |
1579a72e | 339 | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
6af0bf9c | 340 | } |
5dc4b744 | 341 | T0 = (int32_t)T0; |
6af0bf9c FB |
342 | RETURN(); |
343 | } | |
344 | ||
345 | void op_sub (void) | |
346 | { | |
5dc4b744 | 347 | T0 = (int32_t)((int32_t)T0 - (int32_t)T1); |
6af0bf9c FB |
348 | RETURN(); |
349 | } | |
350 | ||
351 | void op_subo (void) | |
352 | { | |
353 | target_ulong tmp; | |
354 | ||
c570fd16 | 355 | tmp = (int32_t)T0; |
6af0bf9c | 356 | T0 = (int32_t)T0 - (int32_t)T1; |
76e050c2 | 357 | if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { |
c570fd16 | 358 | /* operands of different sign, first operand and result different sign */ |
1579a72e | 359 | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
6af0bf9c | 360 | } |
5dc4b744 | 361 | T0 = (int32_t)T0; |
6af0bf9c FB |
362 | RETURN(); |
363 | } | |
364 | ||
365 | void op_mul (void) | |
366 | { | |
5dc4b744 | 367 | T0 = (int32_t)((int32_t)T0 * (int32_t)T1); |
6af0bf9c FB |
368 | RETURN(); |
369 | } | |
370 | ||
371 | void op_div (void) | |
372 | { | |
373 | if (T1 != 0) { | |
5dc4b744 TS |
374 | env->LO = (int32_t)((int32_t)T0 / (int32_t)T1); |
375 | env->HI = (int32_t)((int32_t)T0 % (int32_t)T1); | |
6af0bf9c FB |
376 | } |
377 | RETURN(); | |
378 | } | |
379 | ||
380 | void op_divu (void) | |
c570fd16 TS |
381 | { |
382 | if (T1 != 0) { | |
5dc4b744 TS |
383 | env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1); |
384 | env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1); | |
c570fd16 TS |
385 | } |
386 | RETURN(); | |
387 | } | |
388 | ||
60aa19ab | 389 | #ifdef TARGET_MIPS64 |
c570fd16 TS |
390 | /* Arithmetic */ |
391 | void op_dadd (void) | |
392 | { | |
393 | T0 += T1; | |
394 | RETURN(); | |
395 | } | |
396 | ||
397 | void op_daddo (void) | |
398 | { | |
399 | target_long tmp; | |
400 | ||
401 | tmp = T0; | |
402 | T0 += T1; | |
403 | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) { | |
404 | /* operands of same sign, result different sign */ | |
1579a72e | 405 | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
c570fd16 TS |
406 | } |
407 | RETURN(); | |
408 | } | |
409 | ||
410 | void op_dsub (void) | |
411 | { | |
412 | T0 -= T1; | |
413 | RETURN(); | |
414 | } | |
415 | ||
416 | void op_dsubo (void) | |
417 | { | |
418 | target_long tmp; | |
419 | ||
420 | tmp = T0; | |
421 | T0 = (int64_t)T0 - (int64_t)T1; | |
422 | if (((tmp ^ T1) & (tmp ^ T0)) >> 63) { | |
423 | /* operands of different sign, first operand and result different sign */ | |
1579a72e | 424 | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
c570fd16 TS |
425 | } |
426 | RETURN(); | |
427 | } | |
428 | ||
429 | void op_dmul (void) | |
430 | { | |
431 | T0 = (int64_t)T0 * (int64_t)T1; | |
432 | RETURN(); | |
433 | } | |
434 | ||
435 | #if TARGET_LONG_BITS > HOST_LONG_BITS | |
436 | /* Those might call libgcc functions. */ | |
437 | void op_ddiv (void) | |
438 | { | |
439 | do_ddiv(); | |
440 | RETURN(); | |
441 | } | |
442 | ||
443 | void op_ddivu (void) | |
444 | { | |
445 | do_ddivu(); | |
446 | RETURN(); | |
447 | } | |
448 | #else | |
449 | void op_ddiv (void) | |
450 | { | |
451 | if (T1 != 0) { | |
452 | env->LO = (int64_t)T0 / (int64_t)T1; | |
453 | env->HI = (int64_t)T0 % (int64_t)T1; | |
454 | } | |
455 | RETURN(); | |
456 | } | |
457 | ||
458 | void op_ddivu (void) | |
6af0bf9c FB |
459 | { |
460 | if (T1 != 0) { | |
461 | env->LO = T0 / T1; | |
462 | env->HI = T0 % T1; | |
463 | } | |
464 | RETURN(); | |
465 | } | |
c570fd16 | 466 | #endif |
60aa19ab | 467 | #endif /* TARGET_MIPS64 */ |
6af0bf9c FB |
468 | |
469 | /* Logical */ | |
470 | void op_and (void) | |
471 | { | |
472 | T0 &= T1; | |
473 | RETURN(); | |
474 | } | |
475 | ||
476 | void op_nor (void) | |
477 | { | |
478 | T0 = ~(T0 | T1); | |
479 | RETURN(); | |
480 | } | |
481 | ||
482 | void op_or (void) | |
483 | { | |
484 | T0 |= T1; | |
485 | RETURN(); | |
486 | } | |
487 | ||
488 | void op_xor (void) | |
489 | { | |
490 | T0 ^= T1; | |
491 | RETURN(); | |
492 | } | |
493 | ||
494 | void op_sll (void) | |
495 | { | |
5a63bcb2 | 496 | T0 = (int32_t)((uint32_t)T0 << T1); |
6af0bf9c FB |
497 | RETURN(); |
498 | } | |
499 | ||
500 | void op_sra (void) | |
501 | { | |
5a63bcb2 | 502 | T0 = (int32_t)((int32_t)T0 >> T1); |
6af0bf9c FB |
503 | RETURN(); |
504 | } | |
505 | ||
506 | void op_srl (void) | |
507 | { | |
5a63bcb2 | 508 | T0 = (int32_t)((uint32_t)T0 >> T1); |
6af0bf9c FB |
509 | RETURN(); |
510 | } | |
511 | ||
7a387fff TS |
512 | void op_rotr (void) |
513 | { | |
514 | target_ulong tmp; | |
515 | ||
516 | if (T1) { | |
5a63bcb2 TS |
517 | tmp = (int32_t)((uint32_t)T0 << (0x20 - T1)); |
518 | T0 = (int32_t)((uint32_t)T0 >> T1) | tmp; | |
519 | } | |
7a387fff TS |
520 | RETURN(); |
521 | } | |
522 | ||
6af0bf9c FB |
523 | void op_sllv (void) |
524 | { | |
5dc4b744 | 525 | T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F)); |
6af0bf9c FB |
526 | RETURN(); |
527 | } | |
528 | ||
529 | void op_srav (void) | |
530 | { | |
5dc4b744 | 531 | T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F)); |
6af0bf9c FB |
532 | RETURN(); |
533 | } | |
534 | ||
535 | void op_srlv (void) | |
536 | { | |
5dc4b744 | 537 | T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F)); |
6af0bf9c FB |
538 | RETURN(); |
539 | } | |
540 | ||
7a387fff TS |
541 | void op_rotrv (void) |
542 | { | |
543 | target_ulong tmp; | |
544 | ||
545 | T0 &= 0x1F; | |
546 | if (T0) { | |
5dc4b744 TS |
547 | tmp = (int32_t)((uint32_t)T1 << (0x20 - T0)); |
548 | T0 = (int32_t)((uint32_t)T1 >> T0) | tmp; | |
7a387fff TS |
549 | } else |
550 | T0 = T1; | |
551 | RETURN(); | |
552 | } | |
553 | ||
6af0bf9c FB |
554 | void op_clo (void) |
555 | { | |
556 | int n; | |
557 | ||
c570fd16 | 558 | if (T0 == ~((target_ulong)0)) { |
6af0bf9c FB |
559 | T0 = 32; |
560 | } else { | |
561 | for (n = 0; n < 32; n++) { | |
562 | if (!(T0 & (1 << 31))) | |
563 | break; | |
564 | T0 = T0 << 1; | |
565 | } | |
566 | T0 = n; | |
567 | } | |
568 | RETURN(); | |
569 | } | |
570 | ||
571 | void op_clz (void) | |
572 | { | |
573 | int n; | |
574 | ||
575 | if (T0 == 0) { | |
576 | T0 = 32; | |
577 | } else { | |
578 | for (n = 0; n < 32; n++) { | |
579 | if (T0 & (1 << 31)) | |
580 | break; | |
581 | T0 = T0 << 1; | |
582 | } | |
583 | T0 = n; | |
584 | } | |
585 | RETURN(); | |
586 | } | |
587 | ||
60aa19ab | 588 | #ifdef TARGET_MIPS64 |
c570fd16 TS |
589 | |
590 | #if TARGET_LONG_BITS > HOST_LONG_BITS | |
591 | /* Those might call libgcc functions. */ | |
592 | void op_dsll (void) | |
6af0bf9c | 593 | { |
c570fd16 TS |
594 | CALL_FROM_TB0(do_dsll); |
595 | RETURN(); | |
6af0bf9c FB |
596 | } |
597 | ||
c570fd16 | 598 | void op_dsll32 (void) |
6af0bf9c | 599 | { |
c570fd16 TS |
600 | CALL_FROM_TB0(do_dsll32); |
601 | RETURN(); | |
6af0bf9c FB |
602 | } |
603 | ||
c570fd16 | 604 | void op_dsra (void) |
6af0bf9c | 605 | { |
c570fd16 | 606 | CALL_FROM_TB0(do_dsra); |
6af0bf9c FB |
607 | RETURN(); |
608 | } | |
609 | ||
c570fd16 | 610 | void op_dsra32 (void) |
6af0bf9c | 611 | { |
c570fd16 | 612 | CALL_FROM_TB0(do_dsra32); |
6af0bf9c FB |
613 | RETURN(); |
614 | } | |
615 | ||
c570fd16 | 616 | void op_dsrl (void) |
6af0bf9c | 617 | { |
c570fd16 TS |
618 | CALL_FROM_TB0(do_dsrl); |
619 | RETURN(); | |
620 | } | |
6af0bf9c | 621 | |
c570fd16 TS |
622 | void op_dsrl32 (void) |
623 | { | |
624 | CALL_FROM_TB0(do_dsrl32); | |
6af0bf9c FB |
625 | RETURN(); |
626 | } | |
627 | ||
c570fd16 | 628 | void op_drotr (void) |
6af0bf9c | 629 | { |
c570fd16 TS |
630 | CALL_FROM_TB0(do_drotr); |
631 | RETURN(); | |
632 | } | |
6af0bf9c | 633 | |
c570fd16 TS |
634 | void op_drotr32 (void) |
635 | { | |
636 | CALL_FROM_TB0(do_drotr32); | |
6af0bf9c FB |
637 | RETURN(); |
638 | } | |
639 | ||
c570fd16 | 640 | void op_dsllv (void) |
6af0bf9c | 641 | { |
c570fd16 TS |
642 | CALL_FROM_TB0(do_dsllv); |
643 | RETURN(); | |
644 | } | |
6af0bf9c | 645 | |
c570fd16 TS |
646 | void op_dsrav (void) |
647 | { | |
648 | CALL_FROM_TB0(do_dsrav); | |
6af0bf9c FB |
649 | RETURN(); |
650 | } | |
651 | ||
c570fd16 | 652 | void op_dsrlv (void) |
6af0bf9c | 653 | { |
c570fd16 TS |
654 | CALL_FROM_TB0(do_dsrlv); |
655 | RETURN(); | |
656 | } | |
6af0bf9c | 657 | |
c570fd16 TS |
658 | void op_drotrv (void) |
659 | { | |
660 | CALL_FROM_TB0(do_drotrv); | |
6af0bf9c FB |
661 | RETURN(); |
662 | } | |
c570fd16 TS |
663 | |
664 | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
665 | ||
666 | void op_dsll (void) | |
667 | { | |
668 | T0 = T0 << T1; | |
669 | RETURN(); | |
670 | } | |
671 | ||
672 | void op_dsll32 (void) | |
673 | { | |
674 | T0 = T0 << (T1 + 32); | |
675 | RETURN(); | |
676 | } | |
677 | ||
678 | void op_dsra (void) | |
679 | { | |
680 | T0 = (int64_t)T0 >> T1; | |
681 | RETURN(); | |
682 | } | |
683 | ||
684 | void op_dsra32 (void) | |
685 | { | |
686 | T0 = (int64_t)T0 >> (T1 + 32); | |
687 | RETURN(); | |
688 | } | |
689 | ||
690 | void op_dsrl (void) | |
691 | { | |
692 | T0 = T0 >> T1; | |
693 | RETURN(); | |
694 | } | |
695 | ||
696 | void op_dsrl32 (void) | |
697 | { | |
698 | T0 = T0 >> (T1 + 32); | |
699 | RETURN(); | |
700 | } | |
701 | ||
702 | void op_drotr (void) | |
703 | { | |
704 | target_ulong tmp; | |
705 | ||
706 | if (T1) { | |
707 | tmp = T0 << (0x40 - T1); | |
708 | T0 = (T0 >> T1) | tmp; | |
5a63bcb2 | 709 | } |
c570fd16 TS |
710 | RETURN(); |
711 | } | |
712 | ||
713 | void op_drotr32 (void) | |
714 | { | |
715 | target_ulong tmp; | |
716 | ||
717 | if (T1) { | |
718 | tmp = T0 << (0x40 - (32 + T1)); | |
719 | T0 = (T0 >> (32 + T1)) | tmp; | |
5a63bcb2 | 720 | } |
c570fd16 TS |
721 | RETURN(); |
722 | } | |
723 | ||
724 | void op_dsllv (void) | |
725 | { | |
726 | T0 = T1 << (T0 & 0x3F); | |
727 | RETURN(); | |
728 | } | |
729 | ||
730 | void op_dsrav (void) | |
731 | { | |
732 | T0 = (int64_t)T1 >> (T0 & 0x3F); | |
733 | RETURN(); | |
734 | } | |
735 | ||
736 | void op_dsrlv (void) | |
737 | { | |
738 | T0 = T1 >> (T0 & 0x3F); | |
739 | RETURN(); | |
740 | } | |
741 | ||
742 | void op_drotrv (void) | |
743 | { | |
744 | target_ulong tmp; | |
745 | ||
746 | T0 &= 0x3F; | |
747 | if (T0) { | |
748 | tmp = T1 << (0x40 - T0); | |
749 | T0 = (T1 >> T0) | tmp; | |
750 | } else | |
751 | T0 = T1; | |
752 | RETURN(); | |
753 | } | |
754 | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
755 | ||
756 | void op_dclo (void) | |
757 | { | |
758 | int n; | |
759 | ||
760 | if (T0 == ~((target_ulong)0)) { | |
761 | T0 = 64; | |
762 | } else { | |
763 | for (n = 0; n < 64; n++) { | |
764 | if (!(T0 & (1ULL << 63))) | |
765 | break; | |
766 | T0 = T0 << 1; | |
767 | } | |
768 | T0 = n; | |
769 | } | |
770 | RETURN(); | |
771 | } | |
772 | ||
773 | void op_dclz (void) | |
774 | { | |
775 | int n; | |
776 | ||
777 | if (T0 == 0) { | |
778 | T0 = 64; | |
779 | } else { | |
780 | for (n = 0; n < 64; n++) { | |
781 | if (T0 & (1ULL << 63)) | |
782 | break; | |
783 | T0 = T0 << 1; | |
784 | } | |
785 | T0 = n; | |
786 | } | |
787 | RETURN(); | |
788 | } | |
789 | #endif | |
790 | ||
791 | /* 64 bits arithmetic */ | |
792 | #if TARGET_LONG_BITS > HOST_LONG_BITS | |
6af0bf9c FB |
793 | void op_mult (void) |
794 | { | |
795 | CALL_FROM_TB0(do_mult); | |
796 | RETURN(); | |
797 | } | |
798 | ||
799 | void op_multu (void) | |
800 | { | |
801 | CALL_FROM_TB0(do_multu); | |
802 | RETURN(); | |
803 | } | |
804 | ||
805 | void op_madd (void) | |
806 | { | |
807 | CALL_FROM_TB0(do_madd); | |
808 | RETURN(); | |
809 | } | |
810 | ||
811 | void op_maddu (void) | |
812 | { | |
813 | CALL_FROM_TB0(do_maddu); | |
814 | RETURN(); | |
815 | } | |
816 | ||
817 | void op_msub (void) | |
818 | { | |
819 | CALL_FROM_TB0(do_msub); | |
820 | RETURN(); | |
821 | } | |
822 | ||
823 | void op_msubu (void) | |
824 | { | |
825 | CALL_FROM_TB0(do_msubu); | |
826 | RETURN(); | |
827 | } | |
c570fd16 TS |
828 | |
829 | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
830 | ||
831 | static inline uint64_t get_HILO (void) | |
832 | { | |
833 | return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO); | |
834 | } | |
835 | ||
836 | static inline void set_HILO (uint64_t HILO) | |
837 | { | |
5dc4b744 TS |
838 | env->LO = (int32_t)(HILO & 0xFFFFFFFF); |
839 | env->HI = (int32_t)(HILO >> 32); | |
c570fd16 TS |
840 | } |
841 | ||
842 | void op_mult (void) | |
843 | { | |
844 | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); | |
845 | RETURN(); | |
846 | } | |
847 | ||
848 | void op_multu (void) | |
849 | { | |
850 | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); | |
851 | RETURN(); | |
852 | } | |
853 | ||
854 | void op_madd (void) | |
855 | { | |
856 | int64_t tmp; | |
857 | ||
858 | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); | |
859 | set_HILO((int64_t)get_HILO() + tmp); | |
860 | RETURN(); | |
861 | } | |
862 | ||
863 | void op_maddu (void) | |
864 | { | |
865 | uint64_t tmp; | |
866 | ||
867 | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); | |
868 | set_HILO(get_HILO() + tmp); | |
869 | RETURN(); | |
870 | } | |
871 | ||
872 | void op_msub (void) | |
873 | { | |
874 | int64_t tmp; | |
875 | ||
876 | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); | |
877 | set_HILO((int64_t)get_HILO() - tmp); | |
878 | RETURN(); | |
879 | } | |
880 | ||
881 | void op_msubu (void) | |
882 | { | |
883 | uint64_t tmp; | |
884 | ||
885 | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); | |
886 | set_HILO(get_HILO() - tmp); | |
887 | RETURN(); | |
888 | } | |
889 | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
890 | ||
60aa19ab | 891 | #ifdef TARGET_MIPS64 |
c570fd16 TS |
892 | void op_dmult (void) |
893 | { | |
894 | CALL_FROM_TB0(do_dmult); | |
895 | RETURN(); | |
896 | } | |
897 | ||
898 | void op_dmultu (void) | |
899 | { | |
900 | CALL_FROM_TB0(do_dmultu); | |
901 | RETURN(); | |
902 | } | |
6af0bf9c FB |
903 | #endif |
904 | ||
905 | /* Conditional moves */ | |
906 | void op_movn (void) | |
907 | { | |
908 | if (T1 != 0) | |
909 | env->gpr[PARAM1] = T0; | |
910 | RETURN(); | |
911 | } | |
912 | ||
913 | void op_movz (void) | |
914 | { | |
915 | if (T1 == 0) | |
916 | env->gpr[PARAM1] = T0; | |
917 | RETURN(); | |
918 | } | |
919 | ||
7a387fff TS |
920 | void op_movf (void) |
921 | { | |
922 | if (!(env->fcr31 & PARAM1)) | |
923 | env->gpr[PARAM2] = env->gpr[PARAM3]; | |
924 | RETURN(); | |
925 | } | |
926 | ||
927 | void op_movt (void) | |
928 | { | |
929 | if (env->fcr31 & PARAM1) | |
930 | env->gpr[PARAM2] = env->gpr[PARAM3]; | |
931 | RETURN(); | |
932 | } | |
933 | ||
6af0bf9c FB |
934 | /* Tests */ |
935 | #define OP_COND(name, cond) \ | |
936 | void glue(op_, name) (void) \ | |
937 | { \ | |
938 | if (cond) { \ | |
939 | T0 = 1; \ | |
940 | } else { \ | |
941 | T0 = 0; \ | |
942 | } \ | |
943 | RETURN(); \ | |
944 | } | |
945 | ||
946 | OP_COND(eq, T0 == T1); | |
947 | OP_COND(ne, T0 != T1); | |
948 | OP_COND(ge, (int32_t)T0 >= (int32_t)T1); | |
949 | OP_COND(geu, T0 >= T1); | |
950 | OP_COND(lt, (int32_t)T0 < (int32_t)T1); | |
951 | OP_COND(ltu, T0 < T1); | |
952 | OP_COND(gez, (int32_t)T0 >= 0); | |
953 | OP_COND(gtz, (int32_t)T0 > 0); | |
954 | OP_COND(lez, (int32_t)T0 <= 0); | |
955 | OP_COND(ltz, (int32_t)T0 < 0); | |
956 | ||
7a387fff | 957 | /* Branches */ |
6af0bf9c | 958 | //#undef USE_DIRECT_JUMP |
c53be334 FB |
959 | |
960 | void OPPROTO op_goto_tb0(void) | |
961 | { | |
962 | GOTO_TB(op_goto_tb0, PARAM1, 0); | |
7a387fff | 963 | RETURN(); |
c53be334 FB |
964 | } |
965 | ||
966 | void OPPROTO op_goto_tb1(void) | |
967 | { | |
968 | GOTO_TB(op_goto_tb1, PARAM1, 1); | |
7a387fff | 969 | RETURN(); |
c53be334 | 970 | } |
6af0bf9c FB |
971 | |
972 | /* Branch to register */ | |
973 | void op_save_breg_target (void) | |
974 | { | |
975 | env->btarget = T2; | |
7a387fff | 976 | RETURN(); |
6af0bf9c FB |
977 | } |
978 | ||
979 | void op_restore_breg_target (void) | |
980 | { | |
981 | T2 = env->btarget; | |
7a387fff | 982 | RETURN(); |
6af0bf9c FB |
983 | } |
984 | ||
985 | void op_breg (void) | |
986 | { | |
987 | env->PC = T2; | |
988 | RETURN(); | |
989 | } | |
990 | ||
6af0bf9c FB |
991 | void op_save_btarget (void) |
992 | { | |
993 | env->btarget = PARAM1; | |
994 | RETURN(); | |
995 | } | |
996 | ||
997 | /* Conditional branch */ | |
998 | void op_set_bcond (void) | |
999 | { | |
1000 | T2 = T0; | |
1001 | RETURN(); | |
1002 | } | |
1003 | ||
1004 | void op_save_bcond (void) | |
1005 | { | |
1006 | env->bcond = T2; | |
1007 | RETURN(); | |
1008 | } | |
1009 | ||
1010 | void op_restore_bcond (void) | |
1011 | { | |
1012 | T2 = env->bcond; | |
1013 | RETURN(); | |
1014 | } | |
1015 | ||
c53be334 | 1016 | void op_jnz_T2 (void) |
6af0bf9c | 1017 | { |
c53be334 FB |
1018 | if (T2) |
1019 | GOTO_LABEL_PARAM(1); | |
6af0bf9c FB |
1020 | RETURN(); |
1021 | } | |
1022 | ||
1023 | /* CP0 functions */ | |
873eb012 | 1024 | void op_mfc0_index (void) |
6af0bf9c | 1025 | { |
9c2149c8 | 1026 | T0 = env->CP0_Index; |
873eb012 TS |
1027 | RETURN(); |
1028 | } | |
1029 | ||
1030 | void op_mfc0_random (void) | |
1031 | { | |
1032 | CALL_FROM_TB0(do_mfc0_random); | |
1033 | RETURN(); | |
1034 | } | |
1035 | ||
1036 | void op_mfc0_entrylo0 (void) | |
1037 | { | |
9c2149c8 | 1038 | T0 = (int32_t)env->CP0_EntryLo0; |
873eb012 TS |
1039 | RETURN(); |
1040 | } | |
1041 | ||
1042 | void op_mfc0_entrylo1 (void) | |
1043 | { | |
9c2149c8 | 1044 | T0 = (int32_t)env->CP0_EntryLo1; |
873eb012 TS |
1045 | RETURN(); |
1046 | } | |
1047 | ||
1048 | void op_mfc0_context (void) | |
1049 | { | |
9c2149c8 | 1050 | T0 = (int32_t)env->CP0_Context; |
873eb012 TS |
1051 | RETURN(); |
1052 | } | |
1053 | ||
1054 | void op_mfc0_pagemask (void) | |
1055 | { | |
9c2149c8 | 1056 | T0 = env->CP0_PageMask; |
873eb012 TS |
1057 | RETURN(); |
1058 | } | |
1059 | ||
7a387fff TS |
1060 | void op_mfc0_pagegrain (void) |
1061 | { | |
9c2149c8 | 1062 | T0 = env->CP0_PageGrain; |
7a387fff TS |
1063 | RETURN(); |
1064 | } | |
1065 | ||
873eb012 TS |
1066 | void op_mfc0_wired (void) |
1067 | { | |
9c2149c8 | 1068 | T0 = env->CP0_Wired; |
873eb012 TS |
1069 | RETURN(); |
1070 | } | |
1071 | ||
7a387fff TS |
1072 | void op_mfc0_hwrena (void) |
1073 | { | |
9c2149c8 | 1074 | T0 = env->CP0_HWREna; |
7a387fff TS |
1075 | RETURN(); |
1076 | } | |
1077 | ||
873eb012 TS |
1078 | void op_mfc0_badvaddr (void) |
1079 | { | |
9c2149c8 | 1080 | T0 = (int32_t)env->CP0_BadVAddr; |
873eb012 TS |
1081 | RETURN(); |
1082 | } | |
1083 | ||
1084 | void op_mfc0_count (void) | |
1085 | { | |
1086 | CALL_FROM_TB0(do_mfc0_count); | |
1087 | RETURN(); | |
1088 | } | |
1089 | ||
1090 | void op_mfc0_entryhi (void) | |
1091 | { | |
9c2149c8 | 1092 | T0 = (int32_t)env->CP0_EntryHi; |
873eb012 TS |
1093 | RETURN(); |
1094 | } | |
1095 | ||
1096 | void op_mfc0_compare (void) | |
1097 | { | |
9c2149c8 | 1098 | T0 = env->CP0_Compare; |
873eb012 TS |
1099 | RETURN(); |
1100 | } | |
1101 | ||
1102 | void op_mfc0_status (void) | |
1103 | { | |
9c2149c8 | 1104 | T0 = env->CP0_Status; |
873eb012 TS |
1105 | RETURN(); |
1106 | } | |
1107 | ||
7a387fff TS |
1108 | void op_mfc0_intctl (void) |
1109 | { | |
9c2149c8 | 1110 | T0 = env->CP0_IntCtl; |
7a387fff TS |
1111 | RETURN(); |
1112 | } | |
1113 | ||
1114 | void op_mfc0_srsctl (void) | |
1115 | { | |
9c2149c8 TS |
1116 | T0 = env->CP0_SRSCtl; |
1117 | RETURN(); | |
1118 | } | |
1119 | ||
1120 | void op_mfc0_srsmap (void) | |
1121 | { | |
1122 | T0 = env->CP0_SRSMap; | |
7a387fff TS |
1123 | RETURN(); |
1124 | } | |
1125 | ||
873eb012 TS |
1126 | void op_mfc0_cause (void) |
1127 | { | |
9c2149c8 | 1128 | T0 = env->CP0_Cause; |
873eb012 TS |
1129 | RETURN(); |
1130 | } | |
1131 | ||
1132 | void op_mfc0_epc (void) | |
1133 | { | |
9c2149c8 | 1134 | T0 = (int32_t)env->CP0_EPC; |
873eb012 TS |
1135 | RETURN(); |
1136 | } | |
1137 | ||
1138 | void op_mfc0_prid (void) | |
1139 | { | |
9c2149c8 | 1140 | T0 = env->CP0_PRid; |
873eb012 TS |
1141 | RETURN(); |
1142 | } | |
1143 | ||
7a387fff TS |
1144 | void op_mfc0_ebase (void) |
1145 | { | |
b29a0341 | 1146 | T0 = env->CP0_EBase; |
7a387fff TS |
1147 | RETURN(); |
1148 | } | |
1149 | ||
873eb012 TS |
1150 | void op_mfc0_config0 (void) |
1151 | { | |
9c2149c8 | 1152 | T0 = env->CP0_Config0; |
873eb012 TS |
1153 | RETURN(); |
1154 | } | |
1155 | ||
1156 | void op_mfc0_config1 (void) | |
1157 | { | |
9c2149c8 | 1158 | T0 = env->CP0_Config1; |
873eb012 TS |
1159 | RETURN(); |
1160 | } | |
1161 | ||
7a387fff TS |
1162 | void op_mfc0_config2 (void) |
1163 | { | |
9c2149c8 | 1164 | T0 = env->CP0_Config2; |
7a387fff TS |
1165 | RETURN(); |
1166 | } | |
1167 | ||
1168 | void op_mfc0_config3 (void) | |
1169 | { | |
9c2149c8 | 1170 | T0 = env->CP0_Config3; |
7a387fff TS |
1171 | RETURN(); |
1172 | } | |
1173 | ||
e397ee33 TS |
1174 | void op_mfc0_config6 (void) |
1175 | { | |
1176 | T0 = env->CP0_Config6; | |
1177 | RETURN(); | |
1178 | } | |
1179 | ||
1180 | void op_mfc0_config7 (void) | |
1181 | { | |
1182 | T0 = env->CP0_Config7; | |
1183 | RETURN(); | |
1184 | } | |
1185 | ||
873eb012 TS |
1186 | void op_mfc0_lladdr (void) |
1187 | { | |
9c2149c8 | 1188 | T0 = (int32_t)env->CP0_LLAddr >> 4; |
873eb012 TS |
1189 | RETURN(); |
1190 | } | |
1191 | ||
7a387fff | 1192 | void op_mfc0_watchlo0 (void) |
873eb012 | 1193 | { |
5dc4b744 | 1194 | T0 = (int32_t)env->CP0_WatchLo; |
873eb012 TS |
1195 | RETURN(); |
1196 | } | |
1197 | ||
7a387fff | 1198 | void op_mfc0_watchhi0 (void) |
873eb012 | 1199 | { |
9c2149c8 | 1200 | T0 = env->CP0_WatchHi; |
873eb012 TS |
1201 | RETURN(); |
1202 | } | |
1203 | ||
7a387fff TS |
1204 | void op_mfc0_xcontext (void) |
1205 | { | |
9c2149c8 | 1206 | T0 = (int32_t)env->CP0_XContext; |
7a387fff TS |
1207 | RETURN(); |
1208 | } | |
1209 | ||
1210 | void op_mfc0_framemask (void) | |
1211 | { | |
1212 | T0 = env->CP0_Framemask; | |
1213 | RETURN(); | |
1214 | } | |
1215 | ||
873eb012 TS |
1216 | void op_mfc0_debug (void) |
1217 | { | |
9c2149c8 | 1218 | T0 = env->CP0_Debug; |
873eb012 TS |
1219 | if (env->hflags & MIPS_HFLAG_DM) |
1220 | T0 |= 1 << CP0DB_DM; | |
1221 | RETURN(); | |
1222 | } | |
1223 | ||
1224 | void op_mfc0_depc (void) | |
1225 | { | |
9c2149c8 | 1226 | T0 = (int32_t)env->CP0_DEPC; |
873eb012 TS |
1227 | RETURN(); |
1228 | } | |
1229 | ||
7a387fff TS |
1230 | void op_mfc0_performance0 (void) |
1231 | { | |
9c2149c8 | 1232 | T0 = env->CP0_Performance0; |
7a387fff TS |
1233 | RETURN(); |
1234 | } | |
1235 | ||
873eb012 TS |
1236 | void op_mfc0_taglo (void) |
1237 | { | |
9c2149c8 | 1238 | T0 = env->CP0_TagLo; |
873eb012 TS |
1239 | RETURN(); |
1240 | } | |
1241 | ||
1242 | void op_mfc0_datalo (void) | |
1243 | { | |
9c2149c8 | 1244 | T0 = env->CP0_DataLo; |
873eb012 TS |
1245 | RETURN(); |
1246 | } | |
1247 | ||
7a387fff TS |
1248 | void op_mfc0_taghi (void) |
1249 | { | |
9c2149c8 | 1250 | T0 = env->CP0_TagHi; |
7a387fff TS |
1251 | RETURN(); |
1252 | } | |
1253 | ||
1254 | void op_mfc0_datahi (void) | |
1255 | { | |
9c2149c8 | 1256 | T0 = env->CP0_DataHi; |
7a387fff TS |
1257 | RETURN(); |
1258 | } | |
1259 | ||
873eb012 TS |
1260 | void op_mfc0_errorepc (void) |
1261 | { | |
9c2149c8 | 1262 | T0 = (int32_t)env->CP0_ErrorEPC; |
873eb012 TS |
1263 | RETURN(); |
1264 | } | |
1265 | ||
1266 | void op_mfc0_desave (void) | |
1267 | { | |
9c2149c8 | 1268 | T0 = env->CP0_DESAVE; |
6af0bf9c FB |
1269 | RETURN(); |
1270 | } | |
1271 | ||
8c0fdd85 | 1272 | void op_mtc0_index (void) |
6af0bf9c | 1273 | { |
9c2149c8 | 1274 | env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1)); |
8c0fdd85 TS |
1275 | RETURN(); |
1276 | } | |
1277 | ||
1278 | void op_mtc0_entrylo0 (void) | |
1279 | { | |
7a387fff TS |
1280 | /* Large physaddr not implemented */ |
1281 | /* 1k pages not implemented */ | |
9c2149c8 | 1282 | env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF; |
8c0fdd85 TS |
1283 | RETURN(); |
1284 | } | |
1285 | ||
1286 | void op_mtc0_entrylo1 (void) | |
1287 | { | |
7a387fff TS |
1288 | /* Large physaddr not implemented */ |
1289 | /* 1k pages not implemented */ | |
9c2149c8 | 1290 | env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF; |
8c0fdd85 TS |
1291 | RETURN(); |
1292 | } | |
1293 | ||
1294 | void op_mtc0_context (void) | |
1295 | { | |
534ce69f | 1296 | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
8c0fdd85 TS |
1297 | RETURN(); |
1298 | } | |
1299 | ||
1300 | void op_mtc0_pagemask (void) | |
1301 | { | |
7a387fff TS |
1302 | /* 1k pages not implemented */ |
1303 | env->CP0_PageMask = T0 & 0x1FFFE000; | |
1304 | RETURN(); | |
1305 | } | |
1306 | ||
1307 | void op_mtc0_pagegrain (void) | |
1308 | { | |
1309 | /* SmartMIPS not implemented */ | |
1310 | /* Large physaddr not implemented */ | |
1311 | /* 1k pages not implemented */ | |
1312 | env->CP0_PageGrain = 0; | |
8c0fdd85 TS |
1313 | RETURN(); |
1314 | } | |
1315 | ||
1316 | void op_mtc0_wired (void) | |
1317 | { | |
7a387fff TS |
1318 | env->CP0_Wired = T0 & (MIPS_TLB_NB - 1); |
1319 | RETURN(); | |
1320 | } | |
1321 | ||
1322 | void op_mtc0_hwrena (void) | |
1323 | { | |
1324 | env->CP0_HWREna = T0 & 0x0000000F; | |
8c0fdd85 TS |
1325 | RETURN(); |
1326 | } | |
1327 | ||
1328 | void op_mtc0_count (void) | |
1329 | { | |
1330 | CALL_FROM_TB2(cpu_mips_store_count, env, T0); | |
1331 | RETURN(); | |
1332 | } | |
1333 | ||
1334 | void op_mtc0_entryhi (void) | |
1335 | { | |
0feef828 | 1336 | target_ulong old, val; |
8c0fdd85 | 1337 | |
7a387fff TS |
1338 | /* 1k pages not implemented */ |
1339 | /* Ignore MIPS64 TLB for now */ | |
925fd0f2 | 1340 | val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00; |
8c0fdd85 TS |
1341 | old = env->CP0_EntryHi; |
1342 | env->CP0_EntryHi = val; | |
1343 | /* If the ASID changes, flush qemu's TLB. */ | |
1344 | if ((old & 0xFF) != (val & 0xFF)) | |
1345 | CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1); | |
1346 | RETURN(); | |
1347 | } | |
1348 | ||
1349 | void op_mtc0_compare (void) | |
1350 | { | |
1351 | CALL_FROM_TB2(cpu_mips_store_compare, env, T0); | |
1352 | RETURN(); | |
1353 | } | |
1354 | ||
1355 | void op_mtc0_status (void) | |
1356 | { | |
4de9b249 | 1357 | uint32_t val, old; |
8c0fdd85 | 1358 | |
24c7b0e3 TS |
1359 | /* No 64bit FPU, no reverse endianness, no MDMX/DSP, no 64bit ops, |
1360 | no 64bit addressing implemented. */ | |
1361 | val = (int32_t)T0 & 0xF878FF17; | |
8c0fdd85 | 1362 | old = env->CP0_Status; |
f41c52f1 TS |
1363 | if (!(val & (1 << CP0St_EXL)) && |
1364 | !(val & (1 << CP0St_ERL)) && | |
1365 | !(env->hflags & MIPS_HFLAG_DM) && | |
1366 | (val & (1 << CP0St_UM))) | |
1367 | env->hflags |= MIPS_HFLAG_UM; | |
16c00cb2 | 1368 | env->CP0_Status = (env->CP0_Status & ~0xF878FF17) | val; |
f41c52f1 TS |
1369 | if (loglevel & CPU_LOG_EXEC) |
1370 | CALL_FROM_TB2(do_mtc0_status_debug, old, val); | |
4de9b249 | 1371 | CALL_FROM_TB1(cpu_mips_update_irq, env); |
8c0fdd85 TS |
1372 | RETURN(); |
1373 | } | |
1374 | ||
7a387fff TS |
1375 | void op_mtc0_intctl (void) |
1376 | { | |
c090a8f4 TS |
1377 | /* vectored interrupts not implemented, timer on int 7, |
1378 | no performance counters. */ | |
1379 | env->CP0_IntCtl |= T0 & 0x000002e0; | |
7a387fff TS |
1380 | RETURN(); |
1381 | } | |
1382 | ||
1383 | void op_mtc0_srsctl (void) | |
1384 | { | |
1385 | /* shadow registers not implemented */ | |
1386 | env->CP0_SRSCtl = 0; | |
1387 | RETURN(); | |
1388 | } | |
1389 | ||
9c2149c8 TS |
1390 | void op_mtc0_srsmap (void) |
1391 | { | |
1392 | /* shadow registers not implemented */ | |
1393 | env->CP0_SRSMap = 0; | |
1394 | RETURN(); | |
1395 | } | |
1396 | ||
8c0fdd85 TS |
1397 | void op_mtc0_cause (void) |
1398 | { | |
39d51eb8 TS |
1399 | uint32_t mask = 0x00C00300; |
1400 | ||
1401 | if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) | |
1402 | mask |= 1 << CP0Ca_DC; | |
1403 | ||
e58c8ba5 | 1404 | env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); |
8c0fdd85 | 1405 | |
4de9b249 TS |
1406 | /* Handle the software interrupt as an hardware one, as they |
1407 | are very similar */ | |
1408 | if (T0 & CP0Ca_IP_mask) { | |
1409 | CALL_FROM_TB1(cpu_mips_update_irq, env); | |
8c0fdd85 | 1410 | } |
8c0fdd85 TS |
1411 | RETURN(); |
1412 | } | |
1413 | ||
1414 | void op_mtc0_epc (void) | |
1415 | { | |
9c2149c8 | 1416 | env->CP0_EPC = (int32_t)T0; |
8c0fdd85 TS |
1417 | RETURN(); |
1418 | } | |
1419 | ||
7a387fff TS |
1420 | void op_mtc0_ebase (void) |
1421 | { | |
1422 | /* vectored interrupts not implemented */ | |
1423 | /* Multi-CPU not implemented */ | |
b29a0341 | 1424 | env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
7a387fff TS |
1425 | RETURN(); |
1426 | } | |
1427 | ||
8c0fdd85 TS |
1428 | void op_mtc0_config0 (void) |
1429 | { | |
1430 | #if defined(MIPS_USES_R4K_TLB) | |
7a387fff TS |
1431 | /* Fixed mapping MMU not implemented */ |
1432 | env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001); | |
8c0fdd85 | 1433 | #else |
7a387fff | 1434 | env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001); |
8c0fdd85 TS |
1435 | #endif |
1436 | RETURN(); | |
1437 | } | |
1438 | ||
7a387fff TS |
1439 | void op_mtc0_config2 (void) |
1440 | { | |
1441 | /* tertiary/secondary caches not implemented */ | |
1442 | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); | |
1443 | RETURN(); | |
1444 | } | |
1445 | ||
1446 | void op_mtc0_watchlo0 (void) | |
8c0fdd85 | 1447 | { |
4e7a4a4e TS |
1448 | /* Watch exceptions for instructions, data loads, data stores |
1449 | not implemented. */ | |
1450 | env->CP0_WatchLo = (int32_t)(T0 & ~0x7); | |
8c0fdd85 TS |
1451 | RETURN(); |
1452 | } | |
1453 | ||
7a387fff | 1454 | void op_mtc0_watchhi0 (void) |
8c0fdd85 | 1455 | { |
4e7a4a4e TS |
1456 | env->CP0_WatchHi = (T0 & 0x40FF0FF8); |
1457 | env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7); | |
8c0fdd85 TS |
1458 | RETURN(); |
1459 | } | |
1460 | ||
7a387fff TS |
1461 | void op_mtc0_framemask (void) |
1462 | { | |
1463 | env->CP0_Framemask = T0; /* XXX */ | |
1464 | RETURN(); | |
1465 | } | |
1466 | ||
8c0fdd85 TS |
1467 | void op_mtc0_debug (void) |
1468 | { | |
1469 | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); | |
1470 | if (T0 & (1 << CP0DB_DM)) | |
1471 | env->hflags |= MIPS_HFLAG_DM; | |
1472 | else | |
1473 | env->hflags &= ~MIPS_HFLAG_DM; | |
1474 | RETURN(); | |
1475 | } | |
1476 | ||
1477 | void op_mtc0_depc (void) | |
1478 | { | |
9c2149c8 | 1479 | env->CP0_DEPC = (int32_t)T0; |
8c0fdd85 TS |
1480 | RETURN(); |
1481 | } | |
1482 | ||
7a387fff TS |
1483 | void op_mtc0_performance0 (void) |
1484 | { | |
1485 | env->CP0_Performance0 = T0; /* XXX */ | |
1486 | RETURN(); | |
1487 | } | |
1488 | ||
8c0fdd85 TS |
1489 | void op_mtc0_taglo (void) |
1490 | { | |
9c2149c8 | 1491 | env->CP0_TagLo = T0 & 0xFFFFFCF6; |
8c0fdd85 TS |
1492 | RETURN(); |
1493 | } | |
1494 | ||
7a387fff TS |
1495 | void op_mtc0_datalo (void) |
1496 | { | |
1497 | env->CP0_DataLo = T0; /* XXX */ | |
1498 | RETURN(); | |
1499 | } | |
1500 | ||
1501 | void op_mtc0_taghi (void) | |
1502 | { | |
1503 | env->CP0_TagHi = T0; /* XXX */ | |
1504 | RETURN(); | |
1505 | } | |
1506 | ||
1507 | void op_mtc0_datahi (void) | |
1508 | { | |
1509 | env->CP0_DataHi = T0; /* XXX */ | |
1510 | RETURN(); | |
1511 | } | |
1512 | ||
8c0fdd85 TS |
1513 | void op_mtc0_errorepc (void) |
1514 | { | |
9c2149c8 | 1515 | env->CP0_ErrorEPC = (int32_t)T0; |
8c0fdd85 TS |
1516 | RETURN(); |
1517 | } | |
1518 | ||
1519 | void op_mtc0_desave (void) | |
1520 | { | |
1521 | env->CP0_DESAVE = T0; | |
6af0bf9c FB |
1522 | RETURN(); |
1523 | } | |
1524 | ||
534ce69f | 1525 | #ifdef TARGET_MIPS64 |
9c2149c8 TS |
1526 | void op_dmfc0_entrylo0 (void) |
1527 | { | |
1528 | T0 = env->CP0_EntryLo0; | |
1529 | RETURN(); | |
1530 | } | |
1531 | ||
1532 | void op_dmfc0_entrylo1 (void) | |
1533 | { | |
1534 | T0 = env->CP0_EntryLo1; | |
1535 | RETURN(); | |
1536 | } | |
1537 | ||
1538 | void op_dmfc0_context (void) | |
1539 | { | |
1540 | T0 = env->CP0_Context; | |
1541 | RETURN(); | |
1542 | } | |
1543 | ||
1544 | void op_dmfc0_badvaddr (void) | |
1545 | { | |
1546 | T0 = env->CP0_BadVAddr; | |
1547 | RETURN(); | |
1548 | } | |
1549 | ||
1550 | void op_dmfc0_entryhi (void) | |
1551 | { | |
1552 | T0 = env->CP0_EntryHi; | |
1553 | RETURN(); | |
1554 | } | |
1555 | ||
1556 | void op_dmfc0_epc (void) | |
1557 | { | |
1558 | T0 = env->CP0_EPC; | |
1559 | RETURN(); | |
1560 | } | |
1561 | ||
9c2149c8 TS |
1562 | void op_dmfc0_lladdr (void) |
1563 | { | |
1564 | T0 = env->CP0_LLAddr >> 4; | |
1565 | RETURN(); | |
1566 | } | |
1567 | ||
1568 | void op_dmfc0_watchlo0 (void) | |
1569 | { | |
1570 | T0 = env->CP0_WatchLo; | |
1571 | RETURN(); | |
1572 | } | |
1573 | ||
1574 | void op_dmfc0_xcontext (void) | |
1575 | { | |
1576 | T0 = env->CP0_XContext; | |
1577 | RETURN(); | |
1578 | } | |
1579 | ||
1580 | void op_dmfc0_depc (void) | |
1581 | { | |
1582 | T0 = env->CP0_DEPC; | |
1583 | RETURN(); | |
1584 | } | |
1585 | ||
1586 | void op_dmfc0_errorepc (void) | |
1587 | { | |
1588 | T0 = env->CP0_ErrorEPC; | |
1589 | RETURN(); | |
1590 | } | |
1591 | ||
1592 | void op_dmtc0_entrylo0 (void) | |
1593 | { | |
1594 | /* Large physaddr not implemented */ | |
1595 | /* 1k pages not implemented */ | |
1596 | env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; | |
1597 | RETURN(); | |
1598 | } | |
1599 | ||
1600 | void op_dmtc0_entrylo1 (void) | |
1601 | { | |
1602 | /* Large physaddr not implemented */ | |
1603 | /* 1k pages not implemented */ | |
1604 | env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; | |
1605 | RETURN(); | |
1606 | } | |
1607 | ||
1608 | void op_dmtc0_context (void) | |
1609 | { | |
534ce69f | 1610 | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
9c2149c8 TS |
1611 | RETURN(); |
1612 | } | |
1613 | ||
1614 | void op_dmtc0_epc (void) | |
1615 | { | |
1616 | env->CP0_EPC = T0; | |
1617 | RETURN(); | |
1618 | } | |
1619 | ||
9c2149c8 TS |
1620 | void op_dmtc0_watchlo0 (void) |
1621 | { | |
4e7a4a4e TS |
1622 | /* Watch exceptions for instructions, data loads, data stores |
1623 | not implemented. */ | |
1624 | env->CP0_WatchLo = T0 & ~0x7; | |
9c2149c8 TS |
1625 | RETURN(); |
1626 | } | |
1627 | ||
1628 | void op_dmtc0_xcontext (void) | |
1629 | { | |
534ce69f | 1630 | env->CP0_XContext = (env->CP0_XContext & 0xffffffff) | (T0 & ~0xffffffff); |
9c2149c8 TS |
1631 | RETURN(); |
1632 | } | |
1633 | ||
1634 | void op_dmtc0_depc (void) | |
1635 | { | |
1636 | env->CP0_DEPC = T0; | |
1637 | RETURN(); | |
1638 | } | |
1639 | ||
1640 | void op_dmtc0_errorepc (void) | |
1641 | { | |
1642 | env->CP0_ErrorEPC = T0; | |
1643 | RETURN(); | |
1644 | } | |
534ce69f | 1645 | #endif /* TARGET_MIPS64 */ |
9c2149c8 | 1646 | |
6ea83fed FB |
1647 | #if 0 |
1648 | # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env) | |
1649 | #else | |
1650 | # define DEBUG_FPU_STATE() do { } while(0) | |
1651 | #endif | |
1652 | ||
24c7b0e3 TS |
1653 | void op_cp0_enabled(void) |
1654 | { | |
1655 | if (!(env->CP0_Status & (1 << CP0St_CU0)) && | |
1656 | (env->hflags & MIPS_HFLAG_UM)) { | |
1579a72e | 1657 | CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 0); |
24c7b0e3 TS |
1658 | } |
1659 | RETURN(); | |
1660 | } | |
1661 | ||
6ea83fed FB |
1662 | void op_cp1_enabled(void) |
1663 | { | |
1664 | if (!(env->CP0_Status & (1 << CP0St_CU1))) { | |
1579a72e | 1665 | CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1); |
6ea83fed FB |
1666 | } |
1667 | RETURN(); | |
1668 | } | |
1669 | ||
1670 | /* CP1 functions */ | |
1671 | void op_cfc1 (void) | |
1672 | { | |
1673 | if (T1 == 0) { | |
1674 | T0 = env->fcr0; | |
1675 | } | |
1676 | else { | |
1677 | /* fetch fcr31, masking unused bits */ | |
1678 | T0 = env->fcr31 & 0x0183FFFF; | |
1679 | } | |
1680 | DEBUG_FPU_STATE(); | |
1681 | RETURN(); | |
1682 | } | |
1683 | ||
1684 | /* convert MIPS rounding mode in FCR31 to IEEE library */ | |
1685 | unsigned int ieee_rm[] = { | |
1686 | float_round_nearest_even, | |
1687 | float_round_to_zero, | |
1688 | float_round_up, | |
1689 | float_round_down | |
1690 | }; | |
1691 | ||
1692 | #define RESTORE_ROUNDING_MODE \ | |
1693 | set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status) | |
1694 | ||
1695 | void op_ctc1 (void) | |
1696 | { | |
1697 | if (T1 == 0) { | |
1698 | /* XXX should this throw an exception? | |
1699 | * don't write to FCR0. | |
1700 | * env->fcr0 = T0; | |
1701 | */ | |
1702 | } | |
1703 | else { | |
1704 | /* store new fcr31, masking unused bits */ | |
1705 | env->fcr31 = T0 & 0x0183FFFF; | |
1706 | ||
1707 | /* set rounding mode */ | |
1708 | RESTORE_ROUNDING_MODE; | |
1709 | ||
1710 | #ifndef CONFIG_SOFTFLOAT | |
1711 | /* no floating point exception for native float */ | |
1712 | SET_FP_ENABLE(env->fcr31, 0); | |
1713 | #endif | |
1714 | } | |
1715 | DEBUG_FPU_STATE(); | |
1716 | RETURN(); | |
1717 | } | |
1718 | ||
1719 | void op_mfc1 (void) | |
1720 | { | |
1721 | T0 = WT0; | |
1722 | DEBUG_FPU_STATE(); | |
1723 | RETURN(); | |
1724 | } | |
1725 | ||
1726 | void op_mtc1 (void) | |
1727 | { | |
1728 | WT0 = T0; | |
1729 | DEBUG_FPU_STATE(); | |
1730 | RETURN(); | |
1731 | } | |
1732 | ||
1733 | /* Float support. | |
1734 | Single precition routines have a "s" suffix, double precision a | |
1735 | "d" suffix. */ | |
1736 | ||
1737 | #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) | |
1738 | ||
dd016883 FB |
1739 | FLOAT_OP(cvtd, s) |
1740 | { | |
00a709c7 | 1741 | FDT2 = float32_to_float64(FST0, &env->fp_status); |
dd016883 FB |
1742 | DEBUG_FPU_STATE(); |
1743 | RETURN(); | |
1744 | } | |
6ea83fed FB |
1745 | FLOAT_OP(cvtd, w) |
1746 | { | |
1747 | FDT2 = int32_to_float64(WT0, &env->fp_status); | |
1748 | DEBUG_FPU_STATE(); | |
1749 | RETURN(); | |
1750 | } | |
dd016883 FB |
1751 | FLOAT_OP(cvts, d) |
1752 | { | |
417f38f0 | 1753 | FST2 = float64_to_float32(FDT0, &env->fp_status); |
dd016883 FB |
1754 | DEBUG_FPU_STATE(); |
1755 | RETURN(); | |
1756 | } | |
6ea83fed FB |
1757 | FLOAT_OP(cvts, w) |
1758 | { | |
1759 | FST2 = int32_to_float32(WT0, &env->fp_status); | |
1760 | DEBUG_FPU_STATE(); | |
1761 | RETURN(); | |
1762 | } | |
1763 | FLOAT_OP(cvtw, s) | |
1764 | { | |
1765 | WT2 = float32_to_int32(FST0, &env->fp_status); | |
1766 | DEBUG_FPU_STATE(); | |
1767 | RETURN(); | |
1768 | } | |
1769 | FLOAT_OP(cvtw, d) | |
1770 | { | |
1771 | WT2 = float64_to_int32(FDT0, &env->fp_status); | |
1772 | DEBUG_FPU_STATE(); | |
1773 | RETURN(); | |
1774 | } | |
1775 | ||
1776 | FLOAT_OP(roundw, d) | |
1777 | { | |
1778 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); | |
1779 | WT2 = float64_round_to_int(FDT0, &env->fp_status); | |
1780 | RESTORE_ROUNDING_MODE; | |
1781 | ||
1782 | DEBUG_FPU_STATE(); | |
1783 | RETURN(); | |
1784 | } | |
1785 | FLOAT_OP(roundw, s) | |
1786 | { | |
1787 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); | |
1788 | WT2 = float32_round_to_int(FST0, &env->fp_status); | |
1789 | RESTORE_ROUNDING_MODE; | |
1790 | DEBUG_FPU_STATE(); | |
1791 | RETURN(); | |
1792 | } | |
1793 | ||
1794 | FLOAT_OP(truncw, d) | |
1795 | { | |
1796 | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status); | |
1797 | DEBUG_FPU_STATE(); | |
1798 | RETURN(); | |
1799 | } | |
1800 | FLOAT_OP(truncw, s) | |
1801 | { | |
1802 | WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status); | |
1803 | DEBUG_FPU_STATE(); | |
1804 | RETURN(); | |
1805 | } | |
1806 | ||
1807 | FLOAT_OP(ceilw, d) | |
1808 | { | |
1809 | set_float_rounding_mode(float_round_up, &env->fp_status); | |
1810 | WT2 = float64_round_to_int(FDT0, &env->fp_status); | |
1811 | RESTORE_ROUNDING_MODE; | |
1812 | ||
1813 | DEBUG_FPU_STATE(); | |
1814 | RETURN(); | |
1815 | } | |
1816 | FLOAT_OP(ceilw, s) | |
1817 | { | |
1818 | set_float_rounding_mode(float_round_up, &env->fp_status); | |
1819 | WT2 = float32_round_to_int(FST0, &env->fp_status); | |
1820 | RESTORE_ROUNDING_MODE; | |
1821 | DEBUG_FPU_STATE(); | |
1822 | RETURN(); | |
1823 | } | |
1824 | ||
1825 | FLOAT_OP(floorw, d) | |
1826 | { | |
1827 | set_float_rounding_mode(float_round_down, &env->fp_status); | |
1828 | WT2 = float64_round_to_int(FDT0, &env->fp_status); | |
1829 | RESTORE_ROUNDING_MODE; | |
1830 | ||
1831 | DEBUG_FPU_STATE(); | |
1832 | RETURN(); | |
1833 | } | |
1834 | FLOAT_OP(floorw, s) | |
1835 | { | |
1836 | set_float_rounding_mode(float_round_down, &env->fp_status); | |
1837 | WT2 = float32_round_to_int(FST0, &env->fp_status); | |
1838 | RESTORE_ROUNDING_MODE; | |
1839 | DEBUG_FPU_STATE(); | |
1840 | RETURN(); | |
1841 | } | |
1842 | ||
1843 | /* binary operations */ | |
1844 | #define FLOAT_BINOP(name) \ | |
1845 | FLOAT_OP(name, d) \ | |
1846 | { \ | |
1847 | FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \ | |
1848 | DEBUG_FPU_STATE(); \ | |
1849 | } \ | |
1850 | FLOAT_OP(name, s) \ | |
1851 | { \ | |
1852 | FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ | |
1853 | DEBUG_FPU_STATE(); \ | |
1854 | } | |
1855 | FLOAT_BINOP(add) | |
1856 | FLOAT_BINOP(sub) | |
1857 | FLOAT_BINOP(mul) | |
1858 | FLOAT_BINOP(div) | |
1859 | #undef FLOAT_BINOP | |
1860 | ||
1861 | /* unary operations, modifying fp status */ | |
1862 | #define FLOAT_UNOP(name) \ | |
1863 | FLOAT_OP(name, d) \ | |
1864 | { \ | |
1865 | FDT2 = float64_ ## name(FDT0, &env->fp_status); \ | |
1866 | DEBUG_FPU_STATE(); \ | |
1867 | } \ | |
1868 | FLOAT_OP(name, s) \ | |
1869 | { \ | |
1870 | FST2 = float32_ ## name(FST0, &env->fp_status); \ | |
1871 | DEBUG_FPU_STATE(); \ | |
1872 | } | |
1873 | FLOAT_UNOP(sqrt) | |
1874 | #undef FLOAT_UNOP | |
1875 | ||
1876 | /* unary operations, not modifying fp status */ | |
1877 | #define FLOAT_UNOP(name) \ | |
1878 | FLOAT_OP(name, d) \ | |
1879 | { \ | |
1880 | FDT2 = float64_ ## name(FDT0); \ | |
1881 | DEBUG_FPU_STATE(); \ | |
1882 | } \ | |
1883 | FLOAT_OP(name, s) \ | |
1884 | { \ | |
1885 | FST2 = float32_ ## name(FST0); \ | |
1886 | DEBUG_FPU_STATE(); \ | |
1887 | } | |
1888 | FLOAT_UNOP(abs) | |
1889 | FLOAT_UNOP(chs) | |
1890 | #undef FLOAT_UNOP | |
1891 | ||
1892 | FLOAT_OP(mov, d) | |
1893 | { | |
1894 | FDT2 = FDT0; | |
1895 | DEBUG_FPU_STATE(); | |
1896 | RETURN(); | |
1897 | } | |
1898 | FLOAT_OP(mov, s) | |
1899 | { | |
1900 | FST2 = FST0; | |
1901 | DEBUG_FPU_STATE(); | |
1902 | RETURN(); | |
1903 | } | |
1904 | ||
1905 | #ifdef CONFIG_SOFTFLOAT | |
1906 | #define clear_invalid() do { \ | |
1907 | int flags = get_float_exception_flags(&env->fp_status); \ | |
1908 | flags &= ~float_flag_invalid; \ | |
1909 | set_float_exception_flags(flags, &env->fp_status); \ | |
1910 | } while(0) | |
1911 | #else | |
1912 | #define clear_invalid() do { } while(0) | |
1913 | #endif | |
1914 | ||
1915 | extern void dump_fpu_s(CPUState *env); | |
1916 | ||
1917 | #define FOP_COND(fmt, op, sig, cond) \ | |
1918 | void op_cmp_ ## fmt ## _ ## op (void) \ | |
1919 | { \ | |
1920 | if (cond) \ | |
1921 | SET_FP_COND(env->fcr31); \ | |
1922 | else \ | |
1923 | CLEAR_FP_COND(env->fcr31); \ | |
1924 | if (!sig) \ | |
1925 | clear_invalid(); \ | |
1926 | /*CALL_FROM_TB1(dump_fpu_s, env);*/ \ | |
1927 | DEBUG_FPU_STATE(); \ | |
1928 | RETURN(); \ | |
1929 | } | |
1930 | ||
569f5d66 | 1931 | int float64_is_unordered(float64 a, float64 b STATUS_PARAM) |
6ea83fed | 1932 | { |
6ea83fed FB |
1933 | if (float64_is_nan(a) || float64_is_nan(b)) { |
1934 | float_raise(float_flag_invalid, status); | |
1935 | return 1; | |
1936 | } | |
1937 | else { | |
1938 | return 0; | |
1939 | } | |
1940 | } | |
1941 | ||
1942 | FOP_COND(d, f, 0, 0) | |
1943 | FOP_COND(d, un, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status)) | |
1944 | FOP_COND(d, eq, 0, float64_eq(FDT0, FDT1, &env->fp_status)) | |
1945 | FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status)) | |
1946 | FOP_COND(d, olt, 0, float64_lt(FDT0, FDT1, &env->fp_status)) | |
1947 | FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status)) | |
1948 | FOP_COND(d, ole, 0, float64_le(FDT0, FDT1, &env->fp_status)) | |
1949 | FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status)) | |
1950 | /* NOTE: the comma operator will make "cond" to eval to false, | |
1951 | * but float*_is_unordered() is still called | |
1952 | */ | |
1953 | FOP_COND(d, sf, 1, (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0)) | |
1954 | FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status)) | |
1955 | FOP_COND(d, seq, 1, float64_eq(FDT0, FDT1, &env->fp_status)) | |
1956 | FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status)) | |
1957 | FOP_COND(d, lt, 1, float64_lt(FDT0, FDT1, &env->fp_status)) | |
1958 | FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status)) | |
1959 | FOP_COND(d, le, 1, float64_le(FDT0, FDT1, &env->fp_status)) | |
1960 | FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status)) | |
1961 | ||
1962 | flag float32_is_unordered(float32 a, float32 b STATUS_PARAM) | |
1963 | { | |
1964 | extern flag float32_is_nan( float32 a ); | |
1965 | if (float32_is_nan(a) || float32_is_nan(b)) { | |
1966 | float_raise(float_flag_invalid, status); | |
1967 | return 1; | |
1968 | } | |
1969 | else { | |
1970 | return 0; | |
1971 | } | |
1972 | } | |
1973 | ||
1974 | /* NOTE: the comma operator will make "cond" to eval to false, | |
1975 | * but float*_is_unordered() is still called | |
1976 | */ | |
1977 | FOP_COND(s, f, 0, 0) | |
1978 | FOP_COND(s, un, 0, float32_is_unordered(FST1, FST0, &env->fp_status)) | |
1979 | FOP_COND(s, eq, 0, float32_eq(FST0, FST1, &env->fp_status)) | |
1980 | FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status)) | |
1981 | FOP_COND(s, olt, 0, float32_lt(FST0, FST1, &env->fp_status)) | |
1982 | FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status)) | |
1983 | FOP_COND(s, ole, 0, float32_le(FST0, FST1, &env->fp_status)) | |
1984 | FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status)) | |
1985 | /* NOTE: the comma operator will make "cond" to eval to false, | |
1986 | * but float*_is_unordered() is still called | |
1987 | */ | |
1988 | FOP_COND(s, sf, 1, (float32_is_unordered(FST0, FST1, &env->fp_status), 0)) | |
1989 | FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status)) | |
1990 | FOP_COND(s, seq, 1, float32_eq(FST0, FST1, &env->fp_status)) | |
1991 | FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status)) | |
1992 | FOP_COND(s, lt, 1, float32_lt(FST0, FST1, &env->fp_status)) | |
1993 | FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status)) | |
1994 | FOP_COND(s, le, 1, float32_le(FST0, FST1, &env->fp_status)) | |
1995 | FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status)) | |
1996 | ||
1997 | void op_bc1f (void) | |
1998 | { | |
1999 | T0 = ! IS_FP_COND_SET(env->fcr31); | |
2000 | DEBUG_FPU_STATE(); | |
2001 | RETURN(); | |
2002 | } | |
2003 | ||
2004 | void op_bc1t (void) | |
2005 | { | |
2006 | T0 = IS_FP_COND_SET(env->fcr31); | |
2007 | DEBUG_FPU_STATE(); | |
2008 | RETURN(); | |
2009 | } | |
6ea83fed | 2010 | |
6af0bf9c FB |
2011 | #if defined(MIPS_USES_R4K_TLB) |
2012 | void op_tlbwi (void) | |
2013 | { | |
2014 | CALL_FROM_TB0(do_tlbwi); | |
2015 | RETURN(); | |
2016 | } | |
2017 | ||
2018 | void op_tlbwr (void) | |
2019 | { | |
2020 | CALL_FROM_TB0(do_tlbwr); | |
2021 | RETURN(); | |
2022 | } | |
2023 | ||
2024 | void op_tlbp (void) | |
2025 | { | |
2026 | CALL_FROM_TB0(do_tlbp); | |
2027 | RETURN(); | |
2028 | } | |
2029 | ||
2030 | void op_tlbr (void) | |
2031 | { | |
2032 | CALL_FROM_TB0(do_tlbr); | |
2033 | RETURN(); | |
2034 | } | |
2035 | #endif | |
2036 | ||
2037 | /* Specials */ | |
6f5b89a0 TS |
2038 | #if defined (CONFIG_USER_ONLY) |
2039 | void op_tls_value (void) | |
2040 | { | |
2041 | T0 = env->tls_value; | |
2042 | } | |
2043 | #endif | |
2044 | ||
6af0bf9c FB |
2045 | void op_pmon (void) |
2046 | { | |
2047 | CALL_FROM_TB1(do_pmon, PARAM1); | |
7a387fff TS |
2048 | RETURN(); |
2049 | } | |
2050 | ||
2051 | void op_di (void) | |
2052 | { | |
7a387fff | 2053 | T0 = env->CP0_Status; |
4de9b249 TS |
2054 | env->CP0_Status = T0 & ~(1 << CP0St_IE); |
2055 | CALL_FROM_TB1(cpu_mips_update_irq, env); | |
7a387fff TS |
2056 | RETURN(); |
2057 | } | |
2058 | ||
2059 | void op_ei (void) | |
2060 | { | |
7a387fff | 2061 | T0 = env->CP0_Status; |
4de9b249 TS |
2062 | env->CP0_Status = T0 | (1 << CP0St_IE); |
2063 | CALL_FROM_TB1(cpu_mips_update_irq, env); | |
7a387fff | 2064 | RETURN(); |
6af0bf9c FB |
2065 | } |
2066 | ||
2067 | void op_trap (void) | |
2068 | { | |
2069 | if (T0) { | |
1579a72e | 2070 | CALL_FROM_TB1(do_raise_exception, EXCP_TRAP); |
6af0bf9c FB |
2071 | } |
2072 | RETURN(); | |
2073 | } | |
2074 | ||
4ad40f36 FB |
2075 | void op_debug (void) |
2076 | { | |
7a387fff TS |
2077 | CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
2078 | RETURN(); | |
4ad40f36 FB |
2079 | } |
2080 | ||
6af0bf9c FB |
2081 | void op_set_lladdr (void) |
2082 | { | |
2083 | env->CP0_LLAddr = T2; | |
7a387fff | 2084 | RETURN(); |
6af0bf9c FB |
2085 | } |
2086 | ||
f41c52f1 TS |
2087 | void debug_pre_eret (void); |
2088 | void debug_post_eret (void); | |
6af0bf9c FB |
2089 | void op_eret (void) |
2090 | { | |
f41c52f1 TS |
2091 | if (loglevel & CPU_LOG_EXEC) |
2092 | CALL_FROM_TB0(debug_pre_eret); | |
24c7b0e3 | 2093 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
6af0bf9c | 2094 | env->PC = env->CP0_ErrorEPC; |
24c7b0e3 | 2095 | env->CP0_Status &= ~(1 << CP0St_ERL); |
51e11d9e | 2096 | } else { |
6af0bf9c | 2097 | env->PC = env->CP0_EPC; |
24c7b0e3 | 2098 | env->CP0_Status &= ~(1 << CP0St_EXL); |
51e11d9e | 2099 | } |
24c7b0e3 TS |
2100 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
2101 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
2102 | !(env->hflags & MIPS_HFLAG_DM) && | |
2103 | (env->CP0_Status & (1 << CP0St_UM))) | |
2104 | env->hflags |= MIPS_HFLAG_UM; | |
f41c52f1 TS |
2105 | if (loglevel & CPU_LOG_EXEC) |
2106 | CALL_FROM_TB0(debug_post_eret); | |
6af0bf9c | 2107 | env->CP0_LLAddr = 1; |
7a387fff | 2108 | RETURN(); |
6af0bf9c FB |
2109 | } |
2110 | ||
2111 | void op_deret (void) | |
2112 | { | |
f41c52f1 TS |
2113 | if (loglevel & CPU_LOG_EXEC) |
2114 | CALL_FROM_TB0(debug_pre_eret); | |
6af0bf9c | 2115 | env->PC = env->CP0_DEPC; |
24c7b0e3 TS |
2116 | env->hflags |= MIPS_HFLAG_DM; |
2117 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && | |
2118 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
2119 | !(env->hflags & MIPS_HFLAG_DM) && | |
2120 | (env->CP0_Status & (1 << CP0St_UM))) | |
2121 | env->hflags |= MIPS_HFLAG_UM; | |
f41c52f1 TS |
2122 | if (loglevel & CPU_LOG_EXEC) |
2123 | CALL_FROM_TB0(debug_post_eret); | |
24c7b0e3 | 2124 | env->CP0_LLAddr = 1; |
7a387fff TS |
2125 | RETURN(); |
2126 | } | |
2127 | ||
2128 | void op_rdhwr_cpunum(void) | |
2129 | { | |
1579a72e | 2130 | if (!(env->hflags & MIPS_HFLAG_UM) || |
97428a4d | 2131 | (env->CP0_HWREna & (1 << 0)) || |
1579a72e TS |
2132 | (env->CP0_Status & (1 << CP0St_CU0))) |
2133 | T0 = env->CP0_EBase & 0x3ff; | |
7a387fff | 2134 | else |
1579a72e | 2135 | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
7a387fff TS |
2136 | RETURN(); |
2137 | } | |
2138 | ||
2139 | void op_rdhwr_synci_step(void) | |
2140 | { | |
1579a72e | 2141 | if (!(env->hflags & MIPS_HFLAG_UM) || |
97428a4d | 2142 | (env->CP0_HWREna & (1 << 1)) || |
1579a72e TS |
2143 | (env->CP0_Status & (1 << CP0St_CU0))) |
2144 | T0 = env->SYNCI_Step; | |
7a387fff | 2145 | else |
1579a72e | 2146 | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
7a387fff TS |
2147 | RETURN(); |
2148 | } | |
2149 | ||
2150 | void op_rdhwr_cc(void) | |
2151 | { | |
1579a72e | 2152 | if (!(env->hflags & MIPS_HFLAG_UM) || |
97428a4d | 2153 | (env->CP0_HWREna & (1 << 2)) || |
1579a72e TS |
2154 | (env->CP0_Status & (1 << CP0St_CU0))) |
2155 | T0 = env->CP0_Count; | |
7a387fff | 2156 | else |
1579a72e | 2157 | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
7a387fff TS |
2158 | RETURN(); |
2159 | } | |
2160 | ||
2161 | void op_rdhwr_ccres(void) | |
2162 | { | |
1579a72e | 2163 | if (!(env->hflags & MIPS_HFLAG_UM) || |
97428a4d | 2164 | (env->CP0_HWREna & (1 << 3)) || |
1579a72e TS |
2165 | (env->CP0_Status & (1 << CP0St_CU0))) |
2166 | T0 = env->CCRes; | |
7a387fff | 2167 | else |
1579a72e TS |
2168 | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
2169 | RETURN(); | |
2170 | } | |
2171 | ||
6af0bf9c FB |
2172 | void op_save_state (void) |
2173 | { | |
2174 | env->hflags = PARAM1; | |
2175 | RETURN(); | |
2176 | } | |
2177 | ||
2178 | void op_save_pc (void) | |
2179 | { | |
2180 | env->PC = PARAM1; | |
2181 | RETURN(); | |
2182 | } | |
2183 | ||
16c00cb2 TS |
2184 | void op_interrupt_restart (void) |
2185 | { | |
2186 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && | |
2187 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
2188 | !(env->hflags & MIPS_HFLAG_DM) && | |
2189 | (env->CP0_Status & (1 << CP0St_IE)) && | |
2190 | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { | |
2191 | env->CP0_Cause &= ~(0x1f << CP0Ca_EC); | |
2192 | CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT); | |
2193 | } | |
2194 | RETURN(); | |
2195 | } | |
2196 | ||
6af0bf9c FB |
2197 | void op_raise_exception (void) |
2198 | { | |
2199 | CALL_FROM_TB1(do_raise_exception, PARAM1); | |
2200 | RETURN(); | |
2201 | } | |
2202 | ||
2203 | void op_raise_exception_err (void) | |
2204 | { | |
2205 | CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); | |
2206 | RETURN(); | |
2207 | } | |
2208 | ||
2209 | void op_exit_tb (void) | |
2210 | { | |
2211 | EXIT_TB(); | |
7a387fff | 2212 | RETURN(); |
6af0bf9c FB |
2213 | } |
2214 | ||
4ad40f36 FB |
2215 | void op_wait (void) |
2216 | { | |
2217 | env->halted = 1; | |
2218 | CALL_FROM_TB1(do_raise_exception, EXCP_HLT); | |
7a387fff TS |
2219 | RETURN(); |
2220 | } | |
2221 | ||
2222 | /* Bitfield operations. */ | |
2223 | void op_ext(void) | |
2224 | { | |
2225 | unsigned int pos = PARAM1; | |
2226 | unsigned int size = PARAM2; | |
2227 | ||
f757d6ff | 2228 | T0 = ((uint32_t)T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0); |
7a387fff TS |
2229 | RETURN(); |
2230 | } | |
2231 | ||
2232 | void op_ins(void) | |
2233 | { | |
2234 | unsigned int pos = PARAM1; | |
2235 | unsigned int size = PARAM2; | |
f757d6ff | 2236 | target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
7a387fff | 2237 | |
c570fd16 | 2238 | T0 = (T2 & ~mask) | (((uint32_t)T1 << pos) & mask); |
7a387fff TS |
2239 | RETURN(); |
2240 | } | |
2241 | ||
2242 | void op_wsbh(void) | |
2243 | { | |
2244 | T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF); | |
2245 | RETURN(); | |
2246 | } | |
2247 | ||
60aa19ab | 2248 | #ifdef TARGET_MIPS64 |
c570fd16 TS |
2249 | void op_dext(void) |
2250 | { | |
2251 | unsigned int pos = PARAM1; | |
2252 | unsigned int size = PARAM2; | |
2253 | ||
f757d6ff | 2254 | T0 = (T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0); |
c570fd16 TS |
2255 | RETURN(); |
2256 | } | |
2257 | ||
2258 | void op_dins(void) | |
2259 | { | |
2260 | unsigned int pos = PARAM1; | |
2261 | unsigned int size = PARAM2; | |
f757d6ff | 2262 | target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
c570fd16 TS |
2263 | |
2264 | T0 = (T2 & ~mask) | ((T1 << pos) & mask); | |
2265 | RETURN(); | |
2266 | } | |
2267 | ||
7a387fff TS |
2268 | void op_dsbh(void) |
2269 | { | |
2270 | T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); | |
2271 | RETURN(); | |
2272 | } | |
2273 | ||
2274 | void op_dshd(void) | |
2275 | { | |
2276 | T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); | |
2277 | RETURN(); | |
2278 | } | |
c570fd16 | 2279 | #endif |
7a387fff TS |
2280 | |
2281 | void op_seb(void) | |
2282 | { | |
2283 | T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; | |
2284 | RETURN(); | |
2285 | } | |
2286 | ||
2287 | void op_seh(void) | |
2288 | { | |
2289 | T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; | |
2290 | RETURN(); | |
4ad40f36 | 2291 | } |