]>
Commit | Line | Data |
---|---|---|
6af0bf9c FB |
1 | /* |
2 | * MIPS emulation micro-operations for qemu. | |
3 | * | |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer | |
6ea83fed | 5 | * Copyright (c) 2006 Marius Groeger (FPU operations) |
6af0bf9c FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include "config.h" | |
23 | #include "exec.h" | |
24 | ||
1b351e52 FB |
25 | #ifndef CALL_FROM_TB0 |
26 | #define CALL_FROM_TB0(func) func(); | |
27 | #endif | |
28 | #ifndef CALL_FROM_TB1 | |
29 | #define CALL_FROM_TB1(func, arg0) func(arg0); | |
30 | #endif | |
31 | #ifndef CALL_FROM_TB1_CONST16 | |
32 | #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0); | |
33 | #endif | |
34 | #ifndef CALL_FROM_TB2 | |
35 | #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1); | |
36 | #endif | |
37 | #ifndef CALL_FROM_TB2_CONST16 | |
38 | #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \ | |
39 | CALL_FROM_TB2(func, arg0, arg1); | |
40 | #endif | |
41 | #ifndef CALL_FROM_TB3 | |
42 | #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2); | |
43 | #endif | |
44 | #ifndef CALL_FROM_TB4 | |
45 | #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \ | |
46 | func(arg0, arg1, arg2, arg3); | |
47 | #endif | |
48 | ||
6af0bf9c FB |
49 | #define REG 1 |
50 | #include "op_template.c" | |
51 | #undef REG | |
52 | #define REG 2 | |
53 | #include "op_template.c" | |
54 | #undef REG | |
55 | #define REG 3 | |
56 | #include "op_template.c" | |
57 | #undef REG | |
58 | #define REG 4 | |
59 | #include "op_template.c" | |
60 | #undef REG | |
61 | #define REG 5 | |
62 | #include "op_template.c" | |
63 | #undef REG | |
64 | #define REG 6 | |
65 | #include "op_template.c" | |
66 | #undef REG | |
67 | #define REG 7 | |
68 | #include "op_template.c" | |
69 | #undef REG | |
70 | #define REG 8 | |
71 | #include "op_template.c" | |
72 | #undef REG | |
73 | #define REG 9 | |
74 | #include "op_template.c" | |
75 | #undef REG | |
76 | #define REG 10 | |
77 | #include "op_template.c" | |
78 | #undef REG | |
79 | #define REG 11 | |
80 | #include "op_template.c" | |
81 | #undef REG | |
82 | #define REG 12 | |
83 | #include "op_template.c" | |
84 | #undef REG | |
85 | #define REG 13 | |
86 | #include "op_template.c" | |
87 | #undef REG | |
88 | #define REG 14 | |
89 | #include "op_template.c" | |
90 | #undef REG | |
91 | #define REG 15 | |
92 | #include "op_template.c" | |
93 | #undef REG | |
94 | #define REG 16 | |
95 | #include "op_template.c" | |
96 | #undef REG | |
97 | #define REG 17 | |
98 | #include "op_template.c" | |
99 | #undef REG | |
100 | #define REG 18 | |
101 | #include "op_template.c" | |
102 | #undef REG | |
103 | #define REG 19 | |
104 | #include "op_template.c" | |
105 | #undef REG | |
106 | #define REG 20 | |
107 | #include "op_template.c" | |
108 | #undef REG | |
109 | #define REG 21 | |
110 | #include "op_template.c" | |
111 | #undef REG | |
112 | #define REG 22 | |
113 | #include "op_template.c" | |
114 | #undef REG | |
115 | #define REG 23 | |
116 | #include "op_template.c" | |
117 | #undef REG | |
118 | #define REG 24 | |
119 | #include "op_template.c" | |
120 | #undef REG | |
121 | #define REG 25 | |
122 | #include "op_template.c" | |
123 | #undef REG | |
124 | #define REG 26 | |
125 | #include "op_template.c" | |
126 | #undef REG | |
127 | #define REG 27 | |
128 | #include "op_template.c" | |
129 | #undef REG | |
130 | #define REG 28 | |
131 | #include "op_template.c" | |
132 | #undef REG | |
133 | #define REG 29 | |
134 | #include "op_template.c" | |
135 | #undef REG | |
136 | #define REG 30 | |
137 | #include "op_template.c" | |
138 | #undef REG | |
139 | #define REG 31 | |
140 | #include "op_template.c" | |
141 | #undef REG | |
142 | ||
c570fd16 | 143 | #define TN |
6af0bf9c FB |
144 | #include "op_template.c" |
145 | #undef TN | |
146 | ||
6ea83fed FB |
147 | #define SFREG 0 |
148 | #define DFREG 0 | |
149 | #include "fop_template.c" | |
150 | #undef SFREG | |
151 | #undef DFREG | |
152 | #define SFREG 1 | |
153 | #include "fop_template.c" | |
154 | #undef SFREG | |
155 | #define SFREG 2 | |
156 | #define DFREG 2 | |
157 | #include "fop_template.c" | |
158 | #undef SFREG | |
159 | #undef DFREG | |
160 | #define SFREG 3 | |
161 | #include "fop_template.c" | |
162 | #undef SFREG | |
163 | #define SFREG 4 | |
164 | #define DFREG 4 | |
165 | #include "fop_template.c" | |
166 | #undef SFREG | |
167 | #undef DFREG | |
168 | #define SFREG 5 | |
169 | #include "fop_template.c" | |
170 | #undef SFREG | |
171 | #define SFREG 6 | |
172 | #define DFREG 6 | |
173 | #include "fop_template.c" | |
174 | #undef SFREG | |
175 | #undef DFREG | |
176 | #define SFREG 7 | |
177 | #include "fop_template.c" | |
178 | #undef SFREG | |
179 | #define SFREG 8 | |
180 | #define DFREG 8 | |
181 | #include "fop_template.c" | |
182 | #undef SFREG | |
183 | #undef DFREG | |
184 | #define SFREG 9 | |
185 | #include "fop_template.c" | |
186 | #undef SFREG | |
187 | #define SFREG 10 | |
188 | #define DFREG 10 | |
189 | #include "fop_template.c" | |
190 | #undef SFREG | |
191 | #undef DFREG | |
192 | #define SFREG 11 | |
193 | #include "fop_template.c" | |
194 | #undef SFREG | |
195 | #define SFREG 12 | |
196 | #define DFREG 12 | |
197 | #include "fop_template.c" | |
198 | #undef SFREG | |
199 | #undef DFREG | |
200 | #define SFREG 13 | |
201 | #include "fop_template.c" | |
202 | #undef SFREG | |
203 | #define SFREG 14 | |
204 | #define DFREG 14 | |
205 | #include "fop_template.c" | |
206 | #undef SFREG | |
207 | #undef DFREG | |
208 | #define SFREG 15 | |
209 | #include "fop_template.c" | |
210 | #undef SFREG | |
211 | #define SFREG 16 | |
212 | #define DFREG 16 | |
213 | #include "fop_template.c" | |
214 | #undef SFREG | |
215 | #undef DFREG | |
216 | #define SFREG 17 | |
217 | #include "fop_template.c" | |
218 | #undef SFREG | |
219 | #define SFREG 18 | |
220 | #define DFREG 18 | |
221 | #include "fop_template.c" | |
222 | #undef SFREG | |
223 | #undef DFREG | |
224 | #define SFREG 19 | |
225 | #include "fop_template.c" | |
226 | #undef SFREG | |
227 | #define SFREG 20 | |
228 | #define DFREG 20 | |
229 | #include "fop_template.c" | |
230 | #undef SFREG | |
231 | #undef DFREG | |
232 | #define SFREG 21 | |
233 | #include "fop_template.c" | |
234 | #undef SFREG | |
235 | #define SFREG 22 | |
236 | #define DFREG 22 | |
237 | #include "fop_template.c" | |
238 | #undef SFREG | |
239 | #undef DFREG | |
240 | #define SFREG 23 | |
241 | #include "fop_template.c" | |
242 | #undef SFREG | |
243 | #define SFREG 24 | |
244 | #define DFREG 24 | |
245 | #include "fop_template.c" | |
246 | #undef SFREG | |
247 | #undef DFREG | |
248 | #define SFREG 25 | |
249 | #include "fop_template.c" | |
250 | #undef SFREG | |
251 | #define SFREG 26 | |
252 | #define DFREG 26 | |
253 | #include "fop_template.c" | |
254 | #undef SFREG | |
255 | #undef DFREG | |
256 | #define SFREG 27 | |
257 | #include "fop_template.c" | |
258 | #undef SFREG | |
259 | #define SFREG 28 | |
260 | #define DFREG 28 | |
261 | #include "fop_template.c" | |
262 | #undef SFREG | |
263 | #undef DFREG | |
264 | #define SFREG 29 | |
265 | #include "fop_template.c" | |
266 | #undef SFREG | |
267 | #define SFREG 30 | |
268 | #define DFREG 30 | |
269 | #include "fop_template.c" | |
270 | #undef SFREG | |
271 | #undef DFREG | |
272 | #define SFREG 31 | |
273 | #include "fop_template.c" | |
274 | #undef SFREG | |
275 | ||
276 | #define FTN | |
277 | #include "fop_template.c" | |
278 | #undef FTN | |
279 | ||
6af0bf9c FB |
280 | void op_dup_T0 (void) |
281 | { | |
282 | T2 = T0; | |
283 | RETURN(); | |
284 | } | |
285 | ||
286 | void op_load_HI (void) | |
287 | { | |
288 | T0 = env->HI; | |
289 | RETURN(); | |
290 | } | |
291 | ||
292 | void op_store_HI (void) | |
293 | { | |
294 | env->HI = T0; | |
295 | RETURN(); | |
296 | } | |
297 | ||
298 | void op_load_LO (void) | |
299 | { | |
300 | T0 = env->LO; | |
301 | RETURN(); | |
302 | } | |
303 | ||
304 | void op_store_LO (void) | |
305 | { | |
306 | env->LO = T0; | |
307 | RETURN(); | |
308 | } | |
309 | ||
310 | /* Load and store */ | |
311 | #define MEMSUFFIX _raw | |
312 | #include "op_mem.c" | |
313 | #undef MEMSUFFIX | |
314 | #if !defined(CONFIG_USER_ONLY) | |
315 | #define MEMSUFFIX _user | |
316 | #include "op_mem.c" | |
317 | #undef MEMSUFFIX | |
318 | ||
319 | #define MEMSUFFIX _kernel | |
320 | #include "op_mem.c" | |
321 | #undef MEMSUFFIX | |
322 | #endif | |
323 | ||
324 | /* Arithmetic */ | |
325 | void op_add (void) | |
326 | { | |
5dc4b744 | 327 | T0 = (int32_t)((int32_t)T0 + (int32_t)T1); |
6af0bf9c FB |
328 | RETURN(); |
329 | } | |
330 | ||
331 | void op_addo (void) | |
332 | { | |
333 | target_ulong tmp; | |
334 | ||
c570fd16 TS |
335 | tmp = (int32_t)T0; |
336 | T0 = (int32_t)T0 + (int32_t)T1; | |
76e050c2 | 337 | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { |
c570fd16 | 338 | /* operands of same sign, result different sign */ |
4ad40f36 | 339 | CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); |
6af0bf9c | 340 | } |
5dc4b744 | 341 | T0 = (int32_t)T0; |
6af0bf9c FB |
342 | RETURN(); |
343 | } | |
344 | ||
345 | void op_sub (void) | |
346 | { | |
5dc4b744 | 347 | T0 = (int32_t)((int32_t)T0 - (int32_t)T1); |
6af0bf9c FB |
348 | RETURN(); |
349 | } | |
350 | ||
351 | void op_subo (void) | |
352 | { | |
353 | target_ulong tmp; | |
354 | ||
c570fd16 | 355 | tmp = (int32_t)T0; |
6af0bf9c | 356 | T0 = (int32_t)T0 - (int32_t)T1; |
76e050c2 | 357 | if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { |
c570fd16 | 358 | /* operands of different sign, first operand and result different sign */ |
4ad40f36 | 359 | CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); |
6af0bf9c | 360 | } |
5dc4b744 | 361 | T0 = (int32_t)T0; |
6af0bf9c FB |
362 | RETURN(); |
363 | } | |
364 | ||
365 | void op_mul (void) | |
366 | { | |
5dc4b744 | 367 | T0 = (int32_t)((int32_t)T0 * (int32_t)T1); |
6af0bf9c FB |
368 | RETURN(); |
369 | } | |
370 | ||
371 | void op_div (void) | |
372 | { | |
373 | if (T1 != 0) { | |
5dc4b744 TS |
374 | env->LO = (int32_t)((int32_t)T0 / (int32_t)T1); |
375 | env->HI = (int32_t)((int32_t)T0 % (int32_t)T1); | |
6af0bf9c FB |
376 | } |
377 | RETURN(); | |
378 | } | |
379 | ||
380 | void op_divu (void) | |
c570fd16 TS |
381 | { |
382 | if (T1 != 0) { | |
5dc4b744 TS |
383 | env->LO = (int32_t)((uint32_t)T0 / (uint32_t)T1); |
384 | env->HI = (int32_t)((uint32_t)T0 % (uint32_t)T1); | |
c570fd16 TS |
385 | } |
386 | RETURN(); | |
387 | } | |
388 | ||
389 | #ifdef MIPS_HAS_MIPS64 | |
390 | /* Arithmetic */ | |
391 | void op_dadd (void) | |
392 | { | |
393 | T0 += T1; | |
394 | RETURN(); | |
395 | } | |
396 | ||
397 | void op_daddo (void) | |
398 | { | |
399 | target_long tmp; | |
400 | ||
401 | tmp = T0; | |
402 | T0 += T1; | |
403 | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) { | |
404 | /* operands of same sign, result different sign */ | |
405 | CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); | |
406 | } | |
407 | RETURN(); | |
408 | } | |
409 | ||
410 | void op_dsub (void) | |
411 | { | |
412 | T0 -= T1; | |
413 | RETURN(); | |
414 | } | |
415 | ||
416 | void op_dsubo (void) | |
417 | { | |
418 | target_long tmp; | |
419 | ||
420 | tmp = T0; | |
421 | T0 = (int64_t)T0 - (int64_t)T1; | |
422 | if (((tmp ^ T1) & (tmp ^ T0)) >> 63) { | |
423 | /* operands of different sign, first operand and result different sign */ | |
424 | CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW); | |
425 | } | |
426 | RETURN(); | |
427 | } | |
428 | ||
429 | void op_dmul (void) | |
430 | { | |
431 | T0 = (int64_t)T0 * (int64_t)T1; | |
432 | RETURN(); | |
433 | } | |
434 | ||
435 | #if TARGET_LONG_BITS > HOST_LONG_BITS | |
436 | /* Those might call libgcc functions. */ | |
437 | void op_ddiv (void) | |
438 | { | |
439 | do_ddiv(); | |
440 | RETURN(); | |
441 | } | |
442 | ||
443 | void op_ddivu (void) | |
444 | { | |
445 | do_ddivu(); | |
446 | RETURN(); | |
447 | } | |
448 | #else | |
449 | void op_ddiv (void) | |
450 | { | |
451 | if (T1 != 0) { | |
452 | env->LO = (int64_t)T0 / (int64_t)T1; | |
453 | env->HI = (int64_t)T0 % (int64_t)T1; | |
454 | } | |
455 | RETURN(); | |
456 | } | |
457 | ||
458 | void op_ddivu (void) | |
6af0bf9c FB |
459 | { |
460 | if (T1 != 0) { | |
461 | env->LO = T0 / T1; | |
462 | env->HI = T0 % T1; | |
463 | } | |
464 | RETURN(); | |
465 | } | |
c570fd16 TS |
466 | #endif |
467 | #endif /* MIPS_HAS_MIPS64 */ | |
6af0bf9c FB |
468 | |
469 | /* Logical */ | |
470 | void op_and (void) | |
471 | { | |
472 | T0 &= T1; | |
473 | RETURN(); | |
474 | } | |
475 | ||
476 | void op_nor (void) | |
477 | { | |
478 | T0 = ~(T0 | T1); | |
479 | RETURN(); | |
480 | } | |
481 | ||
482 | void op_or (void) | |
483 | { | |
484 | T0 |= T1; | |
485 | RETURN(); | |
486 | } | |
487 | ||
488 | void op_xor (void) | |
489 | { | |
490 | T0 ^= T1; | |
491 | RETURN(); | |
492 | } | |
493 | ||
494 | void op_sll (void) | |
495 | { | |
5dc4b744 | 496 | T0 = (int32_t)((uint32_t)T0 << (uint32_t)T1); |
6af0bf9c FB |
497 | RETURN(); |
498 | } | |
499 | ||
500 | void op_sra (void) | |
501 | { | |
5dc4b744 | 502 | T0 = (int32_t)((int32_t)T0 >> (uint32_t)T1); |
6af0bf9c FB |
503 | RETURN(); |
504 | } | |
505 | ||
506 | void op_srl (void) | |
507 | { | |
5dc4b744 | 508 | T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1); |
6af0bf9c FB |
509 | RETURN(); |
510 | } | |
511 | ||
7a387fff TS |
512 | void op_rotr (void) |
513 | { | |
514 | target_ulong tmp; | |
515 | ||
516 | if (T1) { | |
5dc4b744 TS |
517 | tmp = (int32_t)((uint32_t)T0 << (0x20 - (uint32_t)T1)); |
518 | T0 = (int32_t)((uint32_t)T0 >> (uint32_t)T1) | tmp; | |
7a387fff TS |
519 | } else |
520 | T0 = T1; | |
521 | RETURN(); | |
522 | } | |
523 | ||
6af0bf9c FB |
524 | void op_sllv (void) |
525 | { | |
5dc4b744 | 526 | T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F)); |
6af0bf9c FB |
527 | RETURN(); |
528 | } | |
529 | ||
530 | void op_srav (void) | |
531 | { | |
5dc4b744 | 532 | T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F)); |
6af0bf9c FB |
533 | RETURN(); |
534 | } | |
535 | ||
536 | void op_srlv (void) | |
537 | { | |
5dc4b744 | 538 | T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F)); |
6af0bf9c FB |
539 | RETURN(); |
540 | } | |
541 | ||
7a387fff TS |
542 | void op_rotrv (void) |
543 | { | |
544 | target_ulong tmp; | |
545 | ||
546 | T0 &= 0x1F; | |
547 | if (T0) { | |
5dc4b744 TS |
548 | tmp = (int32_t)((uint32_t)T1 << (0x20 - T0)); |
549 | T0 = (int32_t)((uint32_t)T1 >> T0) | tmp; | |
7a387fff TS |
550 | } else |
551 | T0 = T1; | |
552 | RETURN(); | |
553 | } | |
554 | ||
6af0bf9c FB |
555 | void op_clo (void) |
556 | { | |
557 | int n; | |
558 | ||
c570fd16 | 559 | if (T0 == ~((target_ulong)0)) { |
6af0bf9c FB |
560 | T0 = 32; |
561 | } else { | |
562 | for (n = 0; n < 32; n++) { | |
563 | if (!(T0 & (1 << 31))) | |
564 | break; | |
565 | T0 = T0 << 1; | |
566 | } | |
567 | T0 = n; | |
568 | } | |
569 | RETURN(); | |
570 | } | |
571 | ||
572 | void op_clz (void) | |
573 | { | |
574 | int n; | |
575 | ||
576 | if (T0 == 0) { | |
577 | T0 = 32; | |
578 | } else { | |
579 | for (n = 0; n < 32; n++) { | |
580 | if (T0 & (1 << 31)) | |
581 | break; | |
582 | T0 = T0 << 1; | |
583 | } | |
584 | T0 = n; | |
585 | } | |
586 | RETURN(); | |
587 | } | |
588 | ||
c570fd16 TS |
589 | #ifdef MIPS_HAS_MIPS64 |
590 | ||
591 | #if TARGET_LONG_BITS > HOST_LONG_BITS | |
592 | /* Those might call libgcc functions. */ | |
593 | void op_dsll (void) | |
6af0bf9c | 594 | { |
c570fd16 TS |
595 | CALL_FROM_TB0(do_dsll); |
596 | RETURN(); | |
6af0bf9c FB |
597 | } |
598 | ||
c570fd16 | 599 | void op_dsll32 (void) |
6af0bf9c | 600 | { |
c570fd16 TS |
601 | CALL_FROM_TB0(do_dsll32); |
602 | RETURN(); | |
6af0bf9c FB |
603 | } |
604 | ||
c570fd16 | 605 | void op_dsra (void) |
6af0bf9c | 606 | { |
c570fd16 | 607 | CALL_FROM_TB0(do_dsra); |
6af0bf9c FB |
608 | RETURN(); |
609 | } | |
610 | ||
c570fd16 | 611 | void op_dsra32 (void) |
6af0bf9c | 612 | { |
c570fd16 | 613 | CALL_FROM_TB0(do_dsra32); |
6af0bf9c FB |
614 | RETURN(); |
615 | } | |
616 | ||
c570fd16 | 617 | void op_dsrl (void) |
6af0bf9c | 618 | { |
c570fd16 TS |
619 | CALL_FROM_TB0(do_dsrl); |
620 | RETURN(); | |
621 | } | |
6af0bf9c | 622 | |
c570fd16 TS |
623 | void op_dsrl32 (void) |
624 | { | |
625 | CALL_FROM_TB0(do_dsrl32); | |
6af0bf9c FB |
626 | RETURN(); |
627 | } | |
628 | ||
c570fd16 | 629 | void op_drotr (void) |
6af0bf9c | 630 | { |
c570fd16 TS |
631 | CALL_FROM_TB0(do_drotr); |
632 | RETURN(); | |
633 | } | |
6af0bf9c | 634 | |
c570fd16 TS |
635 | void op_drotr32 (void) |
636 | { | |
637 | CALL_FROM_TB0(do_drotr32); | |
6af0bf9c FB |
638 | RETURN(); |
639 | } | |
640 | ||
c570fd16 | 641 | void op_dsllv (void) |
6af0bf9c | 642 | { |
c570fd16 TS |
643 | CALL_FROM_TB0(do_dsllv); |
644 | RETURN(); | |
645 | } | |
6af0bf9c | 646 | |
c570fd16 TS |
647 | void op_dsrav (void) |
648 | { | |
649 | CALL_FROM_TB0(do_dsrav); | |
6af0bf9c FB |
650 | RETURN(); |
651 | } | |
652 | ||
c570fd16 | 653 | void op_dsrlv (void) |
6af0bf9c | 654 | { |
c570fd16 TS |
655 | CALL_FROM_TB0(do_dsrlv); |
656 | RETURN(); | |
657 | } | |
6af0bf9c | 658 | |
c570fd16 TS |
659 | void op_drotrv (void) |
660 | { | |
661 | CALL_FROM_TB0(do_drotrv); | |
6af0bf9c FB |
662 | RETURN(); |
663 | } | |
c570fd16 TS |
664 | |
665 | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
666 | ||
667 | void op_dsll (void) | |
668 | { | |
669 | T0 = T0 << T1; | |
670 | RETURN(); | |
671 | } | |
672 | ||
673 | void op_dsll32 (void) | |
674 | { | |
675 | T0 = T0 << (T1 + 32); | |
676 | RETURN(); | |
677 | } | |
678 | ||
679 | void op_dsra (void) | |
680 | { | |
681 | T0 = (int64_t)T0 >> T1; | |
682 | RETURN(); | |
683 | } | |
684 | ||
685 | void op_dsra32 (void) | |
686 | { | |
687 | T0 = (int64_t)T0 >> (T1 + 32); | |
688 | RETURN(); | |
689 | } | |
690 | ||
691 | void op_dsrl (void) | |
692 | { | |
693 | T0 = T0 >> T1; | |
694 | RETURN(); | |
695 | } | |
696 | ||
697 | void op_dsrl32 (void) | |
698 | { | |
699 | T0 = T0 >> (T1 + 32); | |
700 | RETURN(); | |
701 | } | |
702 | ||
703 | void op_drotr (void) | |
704 | { | |
705 | target_ulong tmp; | |
706 | ||
707 | if (T1) { | |
708 | tmp = T0 << (0x40 - T1); | |
709 | T0 = (T0 >> T1) | tmp; | |
710 | } else | |
711 | T0 = T1; | |
712 | RETURN(); | |
713 | } | |
714 | ||
715 | void op_drotr32 (void) | |
716 | { | |
717 | target_ulong tmp; | |
718 | ||
719 | if (T1) { | |
720 | tmp = T0 << (0x40 - (32 + T1)); | |
721 | T0 = (T0 >> (32 + T1)) | tmp; | |
722 | } else | |
723 | T0 = T1; | |
724 | RETURN(); | |
725 | } | |
726 | ||
727 | void op_dsllv (void) | |
728 | { | |
729 | T0 = T1 << (T0 & 0x3F); | |
730 | RETURN(); | |
731 | } | |
732 | ||
733 | void op_dsrav (void) | |
734 | { | |
735 | T0 = (int64_t)T1 >> (T0 & 0x3F); | |
736 | RETURN(); | |
737 | } | |
738 | ||
739 | void op_dsrlv (void) | |
740 | { | |
741 | T0 = T1 >> (T0 & 0x3F); | |
742 | RETURN(); | |
743 | } | |
744 | ||
745 | void op_drotrv (void) | |
746 | { | |
747 | target_ulong tmp; | |
748 | ||
749 | T0 &= 0x3F; | |
750 | if (T0) { | |
751 | tmp = T1 << (0x40 - T0); | |
752 | T0 = (T1 >> T0) | tmp; | |
753 | } else | |
754 | T0 = T1; | |
755 | RETURN(); | |
756 | } | |
757 | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
758 | ||
759 | void op_dclo (void) | |
760 | { | |
761 | int n; | |
762 | ||
763 | if (T0 == ~((target_ulong)0)) { | |
764 | T0 = 64; | |
765 | } else { | |
766 | for (n = 0; n < 64; n++) { | |
767 | if (!(T0 & (1ULL << 63))) | |
768 | break; | |
769 | T0 = T0 << 1; | |
770 | } | |
771 | T0 = n; | |
772 | } | |
773 | RETURN(); | |
774 | } | |
775 | ||
776 | void op_dclz (void) | |
777 | { | |
778 | int n; | |
779 | ||
780 | if (T0 == 0) { | |
781 | T0 = 64; | |
782 | } else { | |
783 | for (n = 0; n < 64; n++) { | |
784 | if (T0 & (1ULL << 63)) | |
785 | break; | |
786 | T0 = T0 << 1; | |
787 | } | |
788 | T0 = n; | |
789 | } | |
790 | RETURN(); | |
791 | } | |
792 | #endif | |
793 | ||
794 | /* 64 bits arithmetic */ | |
795 | #if TARGET_LONG_BITS > HOST_LONG_BITS | |
6af0bf9c FB |
796 | void op_mult (void) |
797 | { | |
798 | CALL_FROM_TB0(do_mult); | |
799 | RETURN(); | |
800 | } | |
801 | ||
802 | void op_multu (void) | |
803 | { | |
804 | CALL_FROM_TB0(do_multu); | |
805 | RETURN(); | |
806 | } | |
807 | ||
808 | void op_madd (void) | |
809 | { | |
810 | CALL_FROM_TB0(do_madd); | |
811 | RETURN(); | |
812 | } | |
813 | ||
814 | void op_maddu (void) | |
815 | { | |
816 | CALL_FROM_TB0(do_maddu); | |
817 | RETURN(); | |
818 | } | |
819 | ||
820 | void op_msub (void) | |
821 | { | |
822 | CALL_FROM_TB0(do_msub); | |
823 | RETURN(); | |
824 | } | |
825 | ||
826 | void op_msubu (void) | |
827 | { | |
828 | CALL_FROM_TB0(do_msubu); | |
829 | RETURN(); | |
830 | } | |
c570fd16 TS |
831 | |
832 | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
833 | ||
834 | static inline uint64_t get_HILO (void) | |
835 | { | |
836 | return ((uint64_t)env->HI << 32) | ((uint64_t)(uint32_t)env->LO); | |
837 | } | |
838 | ||
839 | static inline void set_HILO (uint64_t HILO) | |
840 | { | |
5dc4b744 TS |
841 | env->LO = (int32_t)(HILO & 0xFFFFFFFF); |
842 | env->HI = (int32_t)(HILO >> 32); | |
c570fd16 TS |
843 | } |
844 | ||
845 | void op_mult (void) | |
846 | { | |
847 | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); | |
848 | RETURN(); | |
849 | } | |
850 | ||
851 | void op_multu (void) | |
852 | { | |
853 | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); | |
854 | RETURN(); | |
855 | } | |
856 | ||
857 | void op_madd (void) | |
858 | { | |
859 | int64_t tmp; | |
860 | ||
861 | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); | |
862 | set_HILO((int64_t)get_HILO() + tmp); | |
863 | RETURN(); | |
864 | } | |
865 | ||
866 | void op_maddu (void) | |
867 | { | |
868 | uint64_t tmp; | |
869 | ||
870 | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); | |
871 | set_HILO(get_HILO() + tmp); | |
872 | RETURN(); | |
873 | } | |
874 | ||
875 | void op_msub (void) | |
876 | { | |
877 | int64_t tmp; | |
878 | ||
879 | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); | |
880 | set_HILO((int64_t)get_HILO() - tmp); | |
881 | RETURN(); | |
882 | } | |
883 | ||
884 | void op_msubu (void) | |
885 | { | |
886 | uint64_t tmp; | |
887 | ||
888 | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); | |
889 | set_HILO(get_HILO() - tmp); | |
890 | RETURN(); | |
891 | } | |
892 | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
893 | ||
894 | #ifdef MIPS_HAS_MIPS64 | |
895 | void op_dmult (void) | |
896 | { | |
897 | CALL_FROM_TB0(do_dmult); | |
898 | RETURN(); | |
899 | } | |
900 | ||
901 | void op_dmultu (void) | |
902 | { | |
903 | CALL_FROM_TB0(do_dmultu); | |
904 | RETURN(); | |
905 | } | |
6af0bf9c FB |
906 | #endif |
907 | ||
908 | /* Conditional moves */ | |
909 | void op_movn (void) | |
910 | { | |
911 | if (T1 != 0) | |
912 | env->gpr[PARAM1] = T0; | |
913 | RETURN(); | |
914 | } | |
915 | ||
916 | void op_movz (void) | |
917 | { | |
918 | if (T1 == 0) | |
919 | env->gpr[PARAM1] = T0; | |
920 | RETURN(); | |
921 | } | |
922 | ||
7a387fff TS |
923 | void op_movf (void) |
924 | { | |
925 | if (!(env->fcr31 & PARAM1)) | |
926 | env->gpr[PARAM2] = env->gpr[PARAM3]; | |
927 | RETURN(); | |
928 | } | |
929 | ||
930 | void op_movt (void) | |
931 | { | |
932 | if (env->fcr31 & PARAM1) | |
933 | env->gpr[PARAM2] = env->gpr[PARAM3]; | |
934 | RETURN(); | |
935 | } | |
936 | ||
6af0bf9c FB |
937 | /* Tests */ |
938 | #define OP_COND(name, cond) \ | |
939 | void glue(op_, name) (void) \ | |
940 | { \ | |
941 | if (cond) { \ | |
942 | T0 = 1; \ | |
943 | } else { \ | |
944 | T0 = 0; \ | |
945 | } \ | |
946 | RETURN(); \ | |
947 | } | |
948 | ||
949 | OP_COND(eq, T0 == T1); | |
950 | OP_COND(ne, T0 != T1); | |
951 | OP_COND(ge, (int32_t)T0 >= (int32_t)T1); | |
952 | OP_COND(geu, T0 >= T1); | |
953 | OP_COND(lt, (int32_t)T0 < (int32_t)T1); | |
954 | OP_COND(ltu, T0 < T1); | |
955 | OP_COND(gez, (int32_t)T0 >= 0); | |
956 | OP_COND(gtz, (int32_t)T0 > 0); | |
957 | OP_COND(lez, (int32_t)T0 <= 0); | |
958 | OP_COND(ltz, (int32_t)T0 < 0); | |
959 | ||
7a387fff | 960 | /* Branches */ |
6af0bf9c | 961 | //#undef USE_DIRECT_JUMP |
c53be334 FB |
962 | |
963 | void OPPROTO op_goto_tb0(void) | |
964 | { | |
965 | GOTO_TB(op_goto_tb0, PARAM1, 0); | |
7a387fff | 966 | RETURN(); |
c53be334 FB |
967 | } |
968 | ||
969 | void OPPROTO op_goto_tb1(void) | |
970 | { | |
971 | GOTO_TB(op_goto_tb1, PARAM1, 1); | |
7a387fff | 972 | RETURN(); |
c53be334 | 973 | } |
6af0bf9c FB |
974 | |
975 | /* Branch to register */ | |
976 | void op_save_breg_target (void) | |
977 | { | |
978 | env->btarget = T2; | |
7a387fff | 979 | RETURN(); |
6af0bf9c FB |
980 | } |
981 | ||
982 | void op_restore_breg_target (void) | |
983 | { | |
984 | T2 = env->btarget; | |
7a387fff | 985 | RETURN(); |
6af0bf9c FB |
986 | } |
987 | ||
988 | void op_breg (void) | |
989 | { | |
990 | env->PC = T2; | |
991 | RETURN(); | |
992 | } | |
993 | ||
6af0bf9c FB |
994 | void op_save_btarget (void) |
995 | { | |
996 | env->btarget = PARAM1; | |
997 | RETURN(); | |
998 | } | |
999 | ||
1000 | /* Conditional branch */ | |
1001 | void op_set_bcond (void) | |
1002 | { | |
1003 | T2 = T0; | |
1004 | RETURN(); | |
1005 | } | |
1006 | ||
1007 | void op_save_bcond (void) | |
1008 | { | |
1009 | env->bcond = T2; | |
1010 | RETURN(); | |
1011 | } | |
1012 | ||
1013 | void op_restore_bcond (void) | |
1014 | { | |
1015 | T2 = env->bcond; | |
1016 | RETURN(); | |
1017 | } | |
1018 | ||
c53be334 | 1019 | void op_jnz_T2 (void) |
6af0bf9c | 1020 | { |
c53be334 FB |
1021 | if (T2) |
1022 | GOTO_LABEL_PARAM(1); | |
6af0bf9c FB |
1023 | RETURN(); |
1024 | } | |
1025 | ||
1026 | /* CP0 functions */ | |
873eb012 | 1027 | void op_mfc0_index (void) |
6af0bf9c | 1028 | { |
9c2149c8 | 1029 | T0 = env->CP0_Index; |
873eb012 TS |
1030 | RETURN(); |
1031 | } | |
1032 | ||
1033 | void op_mfc0_random (void) | |
1034 | { | |
1035 | CALL_FROM_TB0(do_mfc0_random); | |
1036 | RETURN(); | |
1037 | } | |
1038 | ||
1039 | void op_mfc0_entrylo0 (void) | |
1040 | { | |
9c2149c8 | 1041 | T0 = (int32_t)env->CP0_EntryLo0; |
873eb012 TS |
1042 | RETURN(); |
1043 | } | |
1044 | ||
1045 | void op_mfc0_entrylo1 (void) | |
1046 | { | |
9c2149c8 | 1047 | T0 = (int32_t)env->CP0_EntryLo1; |
873eb012 TS |
1048 | RETURN(); |
1049 | } | |
1050 | ||
1051 | void op_mfc0_context (void) | |
1052 | { | |
9c2149c8 | 1053 | T0 = (int32_t)env->CP0_Context; |
873eb012 TS |
1054 | RETURN(); |
1055 | } | |
1056 | ||
1057 | void op_mfc0_pagemask (void) | |
1058 | { | |
9c2149c8 | 1059 | T0 = env->CP0_PageMask; |
873eb012 TS |
1060 | RETURN(); |
1061 | } | |
1062 | ||
7a387fff TS |
1063 | void op_mfc0_pagegrain (void) |
1064 | { | |
9c2149c8 | 1065 | T0 = env->CP0_PageGrain; |
7a387fff TS |
1066 | RETURN(); |
1067 | } | |
1068 | ||
873eb012 TS |
1069 | void op_mfc0_wired (void) |
1070 | { | |
9c2149c8 | 1071 | T0 = env->CP0_Wired; |
873eb012 TS |
1072 | RETURN(); |
1073 | } | |
1074 | ||
7a387fff TS |
1075 | void op_mfc0_hwrena (void) |
1076 | { | |
9c2149c8 | 1077 | T0 = env->CP0_HWREna; |
7a387fff TS |
1078 | RETURN(); |
1079 | } | |
1080 | ||
873eb012 TS |
1081 | void op_mfc0_badvaddr (void) |
1082 | { | |
9c2149c8 | 1083 | T0 = (int32_t)env->CP0_BadVAddr; |
873eb012 TS |
1084 | RETURN(); |
1085 | } | |
1086 | ||
1087 | void op_mfc0_count (void) | |
1088 | { | |
1089 | CALL_FROM_TB0(do_mfc0_count); | |
1090 | RETURN(); | |
1091 | } | |
1092 | ||
1093 | void op_mfc0_entryhi (void) | |
1094 | { | |
9c2149c8 | 1095 | T0 = (int32_t)env->CP0_EntryHi; |
873eb012 TS |
1096 | RETURN(); |
1097 | } | |
1098 | ||
1099 | void op_mfc0_compare (void) | |
1100 | { | |
9c2149c8 | 1101 | T0 = env->CP0_Compare; |
873eb012 TS |
1102 | RETURN(); |
1103 | } | |
1104 | ||
1105 | void op_mfc0_status (void) | |
1106 | { | |
9c2149c8 | 1107 | T0 = env->CP0_Status; |
873eb012 TS |
1108 | if (env->hflags & MIPS_HFLAG_UM) |
1109 | T0 |= (1 << CP0St_UM); | |
1110 | if (env->hflags & MIPS_HFLAG_ERL) | |
1111 | T0 |= (1 << CP0St_ERL); | |
1112 | if (env->hflags & MIPS_HFLAG_EXL) | |
1113 | T0 |= (1 << CP0St_EXL); | |
1114 | RETURN(); | |
1115 | } | |
1116 | ||
7a387fff TS |
1117 | void op_mfc0_intctl (void) |
1118 | { | |
9c2149c8 | 1119 | T0 = env->CP0_IntCtl; |
7a387fff TS |
1120 | RETURN(); |
1121 | } | |
1122 | ||
1123 | void op_mfc0_srsctl (void) | |
1124 | { | |
9c2149c8 TS |
1125 | T0 = env->CP0_SRSCtl; |
1126 | RETURN(); | |
1127 | } | |
1128 | ||
1129 | void op_mfc0_srsmap (void) | |
1130 | { | |
1131 | T0 = env->CP0_SRSMap; | |
7a387fff TS |
1132 | RETURN(); |
1133 | } | |
1134 | ||
873eb012 TS |
1135 | void op_mfc0_cause (void) |
1136 | { | |
9c2149c8 | 1137 | T0 = env->CP0_Cause; |
873eb012 TS |
1138 | RETURN(); |
1139 | } | |
1140 | ||
1141 | void op_mfc0_epc (void) | |
1142 | { | |
9c2149c8 | 1143 | T0 = (int32_t)env->CP0_EPC; |
873eb012 TS |
1144 | RETURN(); |
1145 | } | |
1146 | ||
1147 | void op_mfc0_prid (void) | |
1148 | { | |
9c2149c8 | 1149 | T0 = env->CP0_PRid; |
873eb012 TS |
1150 | RETURN(); |
1151 | } | |
1152 | ||
7a387fff TS |
1153 | void op_mfc0_ebase (void) |
1154 | { | |
b29a0341 | 1155 | T0 = env->CP0_EBase; |
7a387fff TS |
1156 | RETURN(); |
1157 | } | |
1158 | ||
873eb012 TS |
1159 | void op_mfc0_config0 (void) |
1160 | { | |
9c2149c8 | 1161 | T0 = env->CP0_Config0; |
873eb012 TS |
1162 | RETURN(); |
1163 | } | |
1164 | ||
1165 | void op_mfc0_config1 (void) | |
1166 | { | |
9c2149c8 | 1167 | T0 = env->CP0_Config1; |
873eb012 TS |
1168 | RETURN(); |
1169 | } | |
1170 | ||
7a387fff TS |
1171 | void op_mfc0_config2 (void) |
1172 | { | |
9c2149c8 | 1173 | T0 = env->CP0_Config2; |
7a387fff TS |
1174 | RETURN(); |
1175 | } | |
1176 | ||
1177 | void op_mfc0_config3 (void) | |
1178 | { | |
9c2149c8 | 1179 | T0 = env->CP0_Config3; |
7a387fff TS |
1180 | RETURN(); |
1181 | } | |
1182 | ||
873eb012 TS |
1183 | void op_mfc0_lladdr (void) |
1184 | { | |
9c2149c8 | 1185 | T0 = (int32_t)env->CP0_LLAddr >> 4; |
873eb012 TS |
1186 | RETURN(); |
1187 | } | |
1188 | ||
7a387fff | 1189 | void op_mfc0_watchlo0 (void) |
873eb012 | 1190 | { |
5dc4b744 | 1191 | T0 = (int32_t)env->CP0_WatchLo; |
873eb012 TS |
1192 | RETURN(); |
1193 | } | |
1194 | ||
7a387fff | 1195 | void op_mfc0_watchhi0 (void) |
873eb012 | 1196 | { |
9c2149c8 | 1197 | T0 = env->CP0_WatchHi; |
873eb012 TS |
1198 | RETURN(); |
1199 | } | |
1200 | ||
7a387fff TS |
1201 | void op_mfc0_xcontext (void) |
1202 | { | |
9c2149c8 | 1203 | T0 = (int32_t)env->CP0_XContext; |
7a387fff TS |
1204 | RETURN(); |
1205 | } | |
1206 | ||
1207 | void op_mfc0_framemask (void) | |
1208 | { | |
1209 | T0 = env->CP0_Framemask; | |
1210 | RETURN(); | |
1211 | } | |
1212 | ||
873eb012 TS |
1213 | void op_mfc0_debug (void) |
1214 | { | |
9c2149c8 | 1215 | T0 = env->CP0_Debug; |
873eb012 TS |
1216 | if (env->hflags & MIPS_HFLAG_DM) |
1217 | T0 |= 1 << CP0DB_DM; | |
1218 | RETURN(); | |
1219 | } | |
1220 | ||
1221 | void op_mfc0_depc (void) | |
1222 | { | |
9c2149c8 | 1223 | T0 = (int32_t)env->CP0_DEPC; |
873eb012 TS |
1224 | RETURN(); |
1225 | } | |
1226 | ||
7a387fff TS |
1227 | void op_mfc0_performance0 (void) |
1228 | { | |
9c2149c8 | 1229 | T0 = env->CP0_Performance0; |
7a387fff TS |
1230 | RETURN(); |
1231 | } | |
1232 | ||
873eb012 TS |
1233 | void op_mfc0_taglo (void) |
1234 | { | |
9c2149c8 | 1235 | T0 = env->CP0_TagLo; |
873eb012 TS |
1236 | RETURN(); |
1237 | } | |
1238 | ||
1239 | void op_mfc0_datalo (void) | |
1240 | { | |
9c2149c8 | 1241 | T0 = env->CP0_DataLo; |
873eb012 TS |
1242 | RETURN(); |
1243 | } | |
1244 | ||
7a387fff TS |
1245 | void op_mfc0_taghi (void) |
1246 | { | |
9c2149c8 | 1247 | T0 = env->CP0_TagHi; |
7a387fff TS |
1248 | RETURN(); |
1249 | } | |
1250 | ||
1251 | void op_mfc0_datahi (void) | |
1252 | { | |
9c2149c8 | 1253 | T0 = env->CP0_DataHi; |
7a387fff TS |
1254 | RETURN(); |
1255 | } | |
1256 | ||
873eb012 TS |
1257 | void op_mfc0_errorepc (void) |
1258 | { | |
9c2149c8 | 1259 | T0 = (int32_t)env->CP0_ErrorEPC; |
873eb012 TS |
1260 | RETURN(); |
1261 | } | |
1262 | ||
1263 | void op_mfc0_desave (void) | |
1264 | { | |
9c2149c8 | 1265 | T0 = env->CP0_DESAVE; |
6af0bf9c FB |
1266 | RETURN(); |
1267 | } | |
1268 | ||
8c0fdd85 | 1269 | void op_mtc0_index (void) |
6af0bf9c | 1270 | { |
9c2149c8 | 1271 | env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1)); |
8c0fdd85 TS |
1272 | RETURN(); |
1273 | } | |
1274 | ||
1275 | void op_mtc0_entrylo0 (void) | |
1276 | { | |
7a387fff TS |
1277 | /* Large physaddr not implemented */ |
1278 | /* 1k pages not implemented */ | |
9c2149c8 | 1279 | env->CP0_EntryLo0 = (int32_t)T0 & 0x3FFFFFFF; |
8c0fdd85 TS |
1280 | RETURN(); |
1281 | } | |
1282 | ||
1283 | void op_mtc0_entrylo1 (void) | |
1284 | { | |
7a387fff TS |
1285 | /* Large physaddr not implemented */ |
1286 | /* 1k pages not implemented */ | |
9c2149c8 | 1287 | env->CP0_EntryLo1 = (int32_t)T0 & 0x3FFFFFFF; |
8c0fdd85 TS |
1288 | RETURN(); |
1289 | } | |
1290 | ||
1291 | void op_mtc0_context (void) | |
1292 | { | |
7a387fff | 1293 | env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0); |
8c0fdd85 TS |
1294 | RETURN(); |
1295 | } | |
1296 | ||
1297 | void op_mtc0_pagemask (void) | |
1298 | { | |
7a387fff TS |
1299 | /* 1k pages not implemented */ |
1300 | env->CP0_PageMask = T0 & 0x1FFFE000; | |
1301 | RETURN(); | |
1302 | } | |
1303 | ||
1304 | void op_mtc0_pagegrain (void) | |
1305 | { | |
1306 | /* SmartMIPS not implemented */ | |
1307 | /* Large physaddr not implemented */ | |
1308 | /* 1k pages not implemented */ | |
1309 | env->CP0_PageGrain = 0; | |
8c0fdd85 TS |
1310 | RETURN(); |
1311 | } | |
1312 | ||
1313 | void op_mtc0_wired (void) | |
1314 | { | |
7a387fff TS |
1315 | env->CP0_Wired = T0 & (MIPS_TLB_NB - 1); |
1316 | RETURN(); | |
1317 | } | |
1318 | ||
1319 | void op_mtc0_hwrena (void) | |
1320 | { | |
1321 | env->CP0_HWREna = T0 & 0x0000000F; | |
8c0fdd85 TS |
1322 | RETURN(); |
1323 | } | |
1324 | ||
1325 | void op_mtc0_count (void) | |
1326 | { | |
1327 | CALL_FROM_TB2(cpu_mips_store_count, env, T0); | |
1328 | RETURN(); | |
1329 | } | |
1330 | ||
1331 | void op_mtc0_entryhi (void) | |
1332 | { | |
0feef828 | 1333 | target_ulong old, val; |
8c0fdd85 | 1334 | |
7a387fff TS |
1335 | /* 1k pages not implemented */ |
1336 | /* Ignore MIPS64 TLB for now */ | |
925fd0f2 | 1337 | val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00; |
8c0fdd85 TS |
1338 | old = env->CP0_EntryHi; |
1339 | env->CP0_EntryHi = val; | |
1340 | /* If the ASID changes, flush qemu's TLB. */ | |
1341 | if ((old & 0xFF) != (val & 0xFF)) | |
1342 | CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1); | |
1343 | RETURN(); | |
1344 | } | |
1345 | ||
1346 | void op_mtc0_compare (void) | |
1347 | { | |
1348 | CALL_FROM_TB2(cpu_mips_store_compare, env, T0); | |
1349 | RETURN(); | |
1350 | } | |
1351 | ||
1352 | void op_mtc0_status (void) | |
1353 | { | |
4de9b249 | 1354 | uint32_t val, old; |
8c0fdd85 | 1355 | |
9c2149c8 | 1356 | val = (int32_t)T0 & 0xFA78FF01; |
8c0fdd85 TS |
1357 | old = env->CP0_Status; |
1358 | if (T0 & (1 << CP0St_UM)) | |
1359 | env->hflags |= MIPS_HFLAG_UM; | |
1360 | else | |
1361 | env->hflags &= ~MIPS_HFLAG_UM; | |
1362 | if (T0 & (1 << CP0St_ERL)) | |
1363 | env->hflags |= MIPS_HFLAG_ERL; | |
1364 | else | |
1365 | env->hflags &= ~MIPS_HFLAG_ERL; | |
1366 | if (T0 & (1 << CP0St_EXL)) | |
1367 | env->hflags |= MIPS_HFLAG_EXL; | |
1368 | else | |
1369 | env->hflags &= ~MIPS_HFLAG_EXL; | |
1370 | env->CP0_Status = val; | |
8c0fdd85 TS |
1371 | if (loglevel & CPU_LOG_TB_IN_ASM) |
1372 | CALL_FROM_TB2(do_mtc0_status_debug, old, val); | |
4de9b249 | 1373 | CALL_FROM_TB1(cpu_mips_update_irq, env); |
8c0fdd85 TS |
1374 | RETURN(); |
1375 | } | |
1376 | ||
7a387fff TS |
1377 | void op_mtc0_intctl (void) |
1378 | { | |
1379 | /* vectored interrupts not implemented */ | |
1380 | env->CP0_IntCtl = 0; | |
1381 | RETURN(); | |
1382 | } | |
1383 | ||
1384 | void op_mtc0_srsctl (void) | |
1385 | { | |
1386 | /* shadow registers not implemented */ | |
1387 | env->CP0_SRSCtl = 0; | |
1388 | RETURN(); | |
1389 | } | |
1390 | ||
9c2149c8 TS |
1391 | void op_mtc0_srsmap (void) |
1392 | { | |
1393 | /* shadow registers not implemented */ | |
1394 | env->CP0_SRSMap = 0; | |
1395 | RETURN(); | |
1396 | } | |
1397 | ||
8c0fdd85 TS |
1398 | void op_mtc0_cause (void) |
1399 | { | |
39d51eb8 TS |
1400 | uint32_t mask = 0x00C00300; |
1401 | ||
1402 | if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) | |
1403 | mask |= 1 << CP0Ca_DC; | |
1404 | ||
1405 | env->CP0_Cause = (env->CP0_Cause & 0xFCC0FF7C) | (T0 & mask); | |
8c0fdd85 | 1406 | |
4de9b249 TS |
1407 | /* Handle the software interrupt as an hardware one, as they |
1408 | are very similar */ | |
1409 | if (T0 & CP0Ca_IP_mask) { | |
1410 | CALL_FROM_TB1(cpu_mips_update_irq, env); | |
8c0fdd85 | 1411 | } |
8c0fdd85 TS |
1412 | RETURN(); |
1413 | } | |
1414 | ||
1415 | void op_mtc0_epc (void) | |
1416 | { | |
9c2149c8 | 1417 | env->CP0_EPC = (int32_t)T0; |
8c0fdd85 TS |
1418 | RETURN(); |
1419 | } | |
1420 | ||
7a387fff TS |
1421 | void op_mtc0_ebase (void) |
1422 | { | |
1423 | /* vectored interrupts not implemented */ | |
1424 | /* Multi-CPU not implemented */ | |
b29a0341 | 1425 | env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
7a387fff TS |
1426 | RETURN(); |
1427 | } | |
1428 | ||
8c0fdd85 TS |
1429 | void op_mtc0_config0 (void) |
1430 | { | |
1431 | #if defined(MIPS_USES_R4K_TLB) | |
7a387fff TS |
1432 | /* Fixed mapping MMU not implemented */ |
1433 | env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001); | |
8c0fdd85 | 1434 | #else |
7a387fff | 1435 | env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001); |
8c0fdd85 TS |
1436 | #endif |
1437 | RETURN(); | |
1438 | } | |
1439 | ||
7a387fff TS |
1440 | void op_mtc0_config2 (void) |
1441 | { | |
1442 | /* tertiary/secondary caches not implemented */ | |
1443 | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); | |
1444 | RETURN(); | |
1445 | } | |
1446 | ||
1447 | void op_mtc0_watchlo0 (void) | |
8c0fdd85 | 1448 | { |
9c2149c8 | 1449 | env->CP0_WatchLo = (int32_t)T0; |
8c0fdd85 TS |
1450 | RETURN(); |
1451 | } | |
1452 | ||
7a387fff | 1453 | void op_mtc0_watchhi0 (void) |
8c0fdd85 TS |
1454 | { |
1455 | env->CP0_WatchHi = T0 & 0x40FF0FF8; | |
1456 | RETURN(); | |
1457 | } | |
1458 | ||
7a387fff TS |
1459 | void op_mtc0_xcontext (void) |
1460 | { | |
9c2149c8 | 1461 | env->CP0_XContext = (int32_t)T0; /* XXX */ |
7a387fff TS |
1462 | RETURN(); |
1463 | } | |
1464 | ||
1465 | void op_mtc0_framemask (void) | |
1466 | { | |
1467 | env->CP0_Framemask = T0; /* XXX */ | |
1468 | RETURN(); | |
1469 | } | |
1470 | ||
8c0fdd85 TS |
1471 | void op_mtc0_debug (void) |
1472 | { | |
1473 | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); | |
1474 | if (T0 & (1 << CP0DB_DM)) | |
1475 | env->hflags |= MIPS_HFLAG_DM; | |
1476 | else | |
1477 | env->hflags &= ~MIPS_HFLAG_DM; | |
1478 | RETURN(); | |
1479 | } | |
1480 | ||
1481 | void op_mtc0_depc (void) | |
1482 | { | |
9c2149c8 | 1483 | env->CP0_DEPC = (int32_t)T0; |
8c0fdd85 TS |
1484 | RETURN(); |
1485 | } | |
1486 | ||
7a387fff TS |
1487 | void op_mtc0_performance0 (void) |
1488 | { | |
1489 | env->CP0_Performance0 = T0; /* XXX */ | |
1490 | RETURN(); | |
1491 | } | |
1492 | ||
8c0fdd85 TS |
1493 | void op_mtc0_taglo (void) |
1494 | { | |
9c2149c8 | 1495 | env->CP0_TagLo = T0 & 0xFFFFFCF6; |
8c0fdd85 TS |
1496 | RETURN(); |
1497 | } | |
1498 | ||
7a387fff TS |
1499 | void op_mtc0_datalo (void) |
1500 | { | |
1501 | env->CP0_DataLo = T0; /* XXX */ | |
1502 | RETURN(); | |
1503 | } | |
1504 | ||
1505 | void op_mtc0_taghi (void) | |
1506 | { | |
1507 | env->CP0_TagHi = T0; /* XXX */ | |
1508 | RETURN(); | |
1509 | } | |
1510 | ||
1511 | void op_mtc0_datahi (void) | |
1512 | { | |
1513 | env->CP0_DataHi = T0; /* XXX */ | |
1514 | RETURN(); | |
1515 | } | |
1516 | ||
8c0fdd85 TS |
1517 | void op_mtc0_errorepc (void) |
1518 | { | |
9c2149c8 | 1519 | env->CP0_ErrorEPC = (int32_t)T0; |
8c0fdd85 TS |
1520 | RETURN(); |
1521 | } | |
1522 | ||
1523 | void op_mtc0_desave (void) | |
1524 | { | |
1525 | env->CP0_DESAVE = T0; | |
6af0bf9c FB |
1526 | RETURN(); |
1527 | } | |
1528 | ||
9c2149c8 TS |
1529 | void op_dmfc0_entrylo0 (void) |
1530 | { | |
1531 | T0 = env->CP0_EntryLo0; | |
1532 | RETURN(); | |
1533 | } | |
1534 | ||
1535 | void op_dmfc0_entrylo1 (void) | |
1536 | { | |
1537 | T0 = env->CP0_EntryLo1; | |
1538 | RETURN(); | |
1539 | } | |
1540 | ||
1541 | void op_dmfc0_context (void) | |
1542 | { | |
1543 | T0 = env->CP0_Context; | |
1544 | RETURN(); | |
1545 | } | |
1546 | ||
1547 | void op_dmfc0_badvaddr (void) | |
1548 | { | |
1549 | T0 = env->CP0_BadVAddr; | |
1550 | RETURN(); | |
1551 | } | |
1552 | ||
1553 | void op_dmfc0_entryhi (void) | |
1554 | { | |
1555 | T0 = env->CP0_EntryHi; | |
1556 | RETURN(); | |
1557 | } | |
1558 | ||
1559 | void op_dmfc0_epc (void) | |
1560 | { | |
1561 | T0 = env->CP0_EPC; | |
1562 | RETURN(); | |
1563 | } | |
1564 | ||
9c2149c8 TS |
1565 | void op_dmfc0_lladdr (void) |
1566 | { | |
1567 | T0 = env->CP0_LLAddr >> 4; | |
1568 | RETURN(); | |
1569 | } | |
1570 | ||
1571 | void op_dmfc0_watchlo0 (void) | |
1572 | { | |
1573 | T0 = env->CP0_WatchLo; | |
1574 | RETURN(); | |
1575 | } | |
1576 | ||
1577 | void op_dmfc0_xcontext (void) | |
1578 | { | |
1579 | T0 = env->CP0_XContext; | |
1580 | RETURN(); | |
1581 | } | |
1582 | ||
1583 | void op_dmfc0_depc (void) | |
1584 | { | |
1585 | T0 = env->CP0_DEPC; | |
1586 | RETURN(); | |
1587 | } | |
1588 | ||
1589 | void op_dmfc0_errorepc (void) | |
1590 | { | |
1591 | T0 = env->CP0_ErrorEPC; | |
1592 | RETURN(); | |
1593 | } | |
1594 | ||
1595 | void op_dmtc0_entrylo0 (void) | |
1596 | { | |
1597 | /* Large physaddr not implemented */ | |
1598 | /* 1k pages not implemented */ | |
1599 | env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; | |
1600 | RETURN(); | |
1601 | } | |
1602 | ||
1603 | void op_dmtc0_entrylo1 (void) | |
1604 | { | |
1605 | /* Large physaddr not implemented */ | |
1606 | /* 1k pages not implemented */ | |
1607 | env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; | |
1608 | RETURN(); | |
1609 | } | |
1610 | ||
1611 | void op_dmtc0_context (void) | |
1612 | { | |
1613 | env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0); | |
1614 | RETURN(); | |
1615 | } | |
1616 | ||
1617 | void op_dmtc0_epc (void) | |
1618 | { | |
1619 | env->CP0_EPC = T0; | |
1620 | RETURN(); | |
1621 | } | |
1622 | ||
9c2149c8 TS |
1623 | void op_dmtc0_watchlo0 (void) |
1624 | { | |
1625 | env->CP0_WatchLo = T0; | |
1626 | RETURN(); | |
1627 | } | |
1628 | ||
1629 | void op_dmtc0_xcontext (void) | |
1630 | { | |
1631 | env->CP0_XContext = T0; /* XXX */ | |
1632 | RETURN(); | |
1633 | } | |
1634 | ||
1635 | void op_dmtc0_depc (void) | |
1636 | { | |
1637 | env->CP0_DEPC = T0; | |
1638 | RETURN(); | |
1639 | } | |
1640 | ||
1641 | void op_dmtc0_errorepc (void) | |
1642 | { | |
1643 | env->CP0_ErrorEPC = T0; | |
1644 | RETURN(); | |
1645 | } | |
1646 | ||
6ea83fed FB |
1647 | #if 0 |
1648 | # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env) | |
1649 | #else | |
1650 | # define DEBUG_FPU_STATE() do { } while(0) | |
1651 | #endif | |
1652 | ||
1653 | void op_cp1_enabled(void) | |
1654 | { | |
1655 | if (!(env->CP0_Status & (1 << CP0St_CU1))) { | |
1656 | CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1); | |
1657 | } | |
1658 | RETURN(); | |
1659 | } | |
1660 | ||
1661 | /* CP1 functions */ | |
1662 | void op_cfc1 (void) | |
1663 | { | |
1664 | if (T1 == 0) { | |
1665 | T0 = env->fcr0; | |
1666 | } | |
1667 | else { | |
1668 | /* fetch fcr31, masking unused bits */ | |
1669 | T0 = env->fcr31 & 0x0183FFFF; | |
1670 | } | |
1671 | DEBUG_FPU_STATE(); | |
1672 | RETURN(); | |
1673 | } | |
1674 | ||
1675 | /* convert MIPS rounding mode in FCR31 to IEEE library */ | |
1676 | unsigned int ieee_rm[] = { | |
1677 | float_round_nearest_even, | |
1678 | float_round_to_zero, | |
1679 | float_round_up, | |
1680 | float_round_down | |
1681 | }; | |
1682 | ||
1683 | #define RESTORE_ROUNDING_MODE \ | |
1684 | set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status) | |
1685 | ||
1686 | void op_ctc1 (void) | |
1687 | { | |
1688 | if (T1 == 0) { | |
1689 | /* XXX should this throw an exception? | |
1690 | * don't write to FCR0. | |
1691 | * env->fcr0 = T0; | |
1692 | */ | |
1693 | } | |
1694 | else { | |
1695 | /* store new fcr31, masking unused bits */ | |
1696 | env->fcr31 = T0 & 0x0183FFFF; | |
1697 | ||
1698 | /* set rounding mode */ | |
1699 | RESTORE_ROUNDING_MODE; | |
1700 | ||
1701 | #ifndef CONFIG_SOFTFLOAT | |
1702 | /* no floating point exception for native float */ | |
1703 | SET_FP_ENABLE(env->fcr31, 0); | |
1704 | #endif | |
1705 | } | |
1706 | DEBUG_FPU_STATE(); | |
1707 | RETURN(); | |
1708 | } | |
1709 | ||
1710 | void op_mfc1 (void) | |
1711 | { | |
1712 | T0 = WT0; | |
1713 | DEBUG_FPU_STATE(); | |
1714 | RETURN(); | |
1715 | } | |
1716 | ||
1717 | void op_mtc1 (void) | |
1718 | { | |
1719 | WT0 = T0; | |
1720 | DEBUG_FPU_STATE(); | |
1721 | RETURN(); | |
1722 | } | |
1723 | ||
1724 | /* Float support. | |
1725 | Single precition routines have a "s" suffix, double precision a | |
1726 | "d" suffix. */ | |
1727 | ||
1728 | #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) | |
1729 | ||
dd016883 FB |
1730 | FLOAT_OP(cvtd, s) |
1731 | { | |
00a709c7 | 1732 | FDT2 = float32_to_float64(FST0, &env->fp_status); |
dd016883 FB |
1733 | DEBUG_FPU_STATE(); |
1734 | RETURN(); | |
1735 | } | |
6ea83fed FB |
1736 | FLOAT_OP(cvtd, w) |
1737 | { | |
1738 | FDT2 = int32_to_float64(WT0, &env->fp_status); | |
1739 | DEBUG_FPU_STATE(); | |
1740 | RETURN(); | |
1741 | } | |
dd016883 FB |
1742 | FLOAT_OP(cvts, d) |
1743 | { | |
417f38f0 | 1744 | FST2 = float64_to_float32(FDT0, &env->fp_status); |
dd016883 FB |
1745 | DEBUG_FPU_STATE(); |
1746 | RETURN(); | |
1747 | } | |
6ea83fed FB |
1748 | FLOAT_OP(cvts, w) |
1749 | { | |
1750 | FST2 = int32_to_float32(WT0, &env->fp_status); | |
1751 | DEBUG_FPU_STATE(); | |
1752 | RETURN(); | |
1753 | } | |
1754 | FLOAT_OP(cvtw, s) | |
1755 | { | |
1756 | WT2 = float32_to_int32(FST0, &env->fp_status); | |
1757 | DEBUG_FPU_STATE(); | |
1758 | RETURN(); | |
1759 | } | |
1760 | FLOAT_OP(cvtw, d) | |
1761 | { | |
1762 | WT2 = float64_to_int32(FDT0, &env->fp_status); | |
1763 | DEBUG_FPU_STATE(); | |
1764 | RETURN(); | |
1765 | } | |
1766 | ||
1767 | FLOAT_OP(roundw, d) | |
1768 | { | |
1769 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); | |
1770 | WT2 = float64_round_to_int(FDT0, &env->fp_status); | |
1771 | RESTORE_ROUNDING_MODE; | |
1772 | ||
1773 | DEBUG_FPU_STATE(); | |
1774 | RETURN(); | |
1775 | } | |
1776 | FLOAT_OP(roundw, s) | |
1777 | { | |
1778 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); | |
1779 | WT2 = float32_round_to_int(FST0, &env->fp_status); | |
1780 | RESTORE_ROUNDING_MODE; | |
1781 | DEBUG_FPU_STATE(); | |
1782 | RETURN(); | |
1783 | } | |
1784 | ||
1785 | FLOAT_OP(truncw, d) | |
1786 | { | |
1787 | WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status); | |
1788 | DEBUG_FPU_STATE(); | |
1789 | RETURN(); | |
1790 | } | |
1791 | FLOAT_OP(truncw, s) | |
1792 | { | |
1793 | WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status); | |
1794 | DEBUG_FPU_STATE(); | |
1795 | RETURN(); | |
1796 | } | |
1797 | ||
1798 | FLOAT_OP(ceilw, d) | |
1799 | { | |
1800 | set_float_rounding_mode(float_round_up, &env->fp_status); | |
1801 | WT2 = float64_round_to_int(FDT0, &env->fp_status); | |
1802 | RESTORE_ROUNDING_MODE; | |
1803 | ||
1804 | DEBUG_FPU_STATE(); | |
1805 | RETURN(); | |
1806 | } | |
1807 | FLOAT_OP(ceilw, s) | |
1808 | { | |
1809 | set_float_rounding_mode(float_round_up, &env->fp_status); | |
1810 | WT2 = float32_round_to_int(FST0, &env->fp_status); | |
1811 | RESTORE_ROUNDING_MODE; | |
1812 | DEBUG_FPU_STATE(); | |
1813 | RETURN(); | |
1814 | } | |
1815 | ||
1816 | FLOAT_OP(floorw, d) | |
1817 | { | |
1818 | set_float_rounding_mode(float_round_down, &env->fp_status); | |
1819 | WT2 = float64_round_to_int(FDT0, &env->fp_status); | |
1820 | RESTORE_ROUNDING_MODE; | |
1821 | ||
1822 | DEBUG_FPU_STATE(); | |
1823 | RETURN(); | |
1824 | } | |
1825 | FLOAT_OP(floorw, s) | |
1826 | { | |
1827 | set_float_rounding_mode(float_round_down, &env->fp_status); | |
1828 | WT2 = float32_round_to_int(FST0, &env->fp_status); | |
1829 | RESTORE_ROUNDING_MODE; | |
1830 | DEBUG_FPU_STATE(); | |
1831 | RETURN(); | |
1832 | } | |
1833 | ||
1834 | /* binary operations */ | |
1835 | #define FLOAT_BINOP(name) \ | |
1836 | FLOAT_OP(name, d) \ | |
1837 | { \ | |
1838 | FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \ | |
1839 | DEBUG_FPU_STATE(); \ | |
1840 | } \ | |
1841 | FLOAT_OP(name, s) \ | |
1842 | { \ | |
1843 | FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \ | |
1844 | DEBUG_FPU_STATE(); \ | |
1845 | } | |
1846 | FLOAT_BINOP(add) | |
1847 | FLOAT_BINOP(sub) | |
1848 | FLOAT_BINOP(mul) | |
1849 | FLOAT_BINOP(div) | |
1850 | #undef FLOAT_BINOP | |
1851 | ||
1852 | /* unary operations, modifying fp status */ | |
1853 | #define FLOAT_UNOP(name) \ | |
1854 | FLOAT_OP(name, d) \ | |
1855 | { \ | |
1856 | FDT2 = float64_ ## name(FDT0, &env->fp_status); \ | |
1857 | DEBUG_FPU_STATE(); \ | |
1858 | } \ | |
1859 | FLOAT_OP(name, s) \ | |
1860 | { \ | |
1861 | FST2 = float32_ ## name(FST0, &env->fp_status); \ | |
1862 | DEBUG_FPU_STATE(); \ | |
1863 | } | |
1864 | FLOAT_UNOP(sqrt) | |
1865 | #undef FLOAT_UNOP | |
1866 | ||
1867 | /* unary operations, not modifying fp status */ | |
1868 | #define FLOAT_UNOP(name) \ | |
1869 | FLOAT_OP(name, d) \ | |
1870 | { \ | |
1871 | FDT2 = float64_ ## name(FDT0); \ | |
1872 | DEBUG_FPU_STATE(); \ | |
1873 | } \ | |
1874 | FLOAT_OP(name, s) \ | |
1875 | { \ | |
1876 | FST2 = float32_ ## name(FST0); \ | |
1877 | DEBUG_FPU_STATE(); \ | |
1878 | } | |
1879 | FLOAT_UNOP(abs) | |
1880 | FLOAT_UNOP(chs) | |
1881 | #undef FLOAT_UNOP | |
1882 | ||
1883 | FLOAT_OP(mov, d) | |
1884 | { | |
1885 | FDT2 = FDT0; | |
1886 | DEBUG_FPU_STATE(); | |
1887 | RETURN(); | |
1888 | } | |
1889 | FLOAT_OP(mov, s) | |
1890 | { | |
1891 | FST2 = FST0; | |
1892 | DEBUG_FPU_STATE(); | |
1893 | RETURN(); | |
1894 | } | |
1895 | ||
1896 | #ifdef CONFIG_SOFTFLOAT | |
1897 | #define clear_invalid() do { \ | |
1898 | int flags = get_float_exception_flags(&env->fp_status); \ | |
1899 | flags &= ~float_flag_invalid; \ | |
1900 | set_float_exception_flags(flags, &env->fp_status); \ | |
1901 | } while(0) | |
1902 | #else | |
1903 | #define clear_invalid() do { } while(0) | |
1904 | #endif | |
1905 | ||
1906 | extern void dump_fpu_s(CPUState *env); | |
1907 | ||
1908 | #define FOP_COND(fmt, op, sig, cond) \ | |
1909 | void op_cmp_ ## fmt ## _ ## op (void) \ | |
1910 | { \ | |
1911 | if (cond) \ | |
1912 | SET_FP_COND(env->fcr31); \ | |
1913 | else \ | |
1914 | CLEAR_FP_COND(env->fcr31); \ | |
1915 | if (!sig) \ | |
1916 | clear_invalid(); \ | |
1917 | /*CALL_FROM_TB1(dump_fpu_s, env);*/ \ | |
1918 | DEBUG_FPU_STATE(); \ | |
1919 | RETURN(); \ | |
1920 | } | |
1921 | ||
569f5d66 | 1922 | int float64_is_unordered(float64 a, float64 b STATUS_PARAM) |
6ea83fed | 1923 | { |
6ea83fed FB |
1924 | if (float64_is_nan(a) || float64_is_nan(b)) { |
1925 | float_raise(float_flag_invalid, status); | |
1926 | return 1; | |
1927 | } | |
1928 | else { | |
1929 | return 0; | |
1930 | } | |
1931 | } | |
1932 | ||
1933 | FOP_COND(d, f, 0, 0) | |
1934 | FOP_COND(d, un, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status)) | |
1935 | FOP_COND(d, eq, 0, float64_eq(FDT0, FDT1, &env->fp_status)) | |
1936 | FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status)) | |
1937 | FOP_COND(d, olt, 0, float64_lt(FDT0, FDT1, &env->fp_status)) | |
1938 | FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status)) | |
1939 | FOP_COND(d, ole, 0, float64_le(FDT0, FDT1, &env->fp_status)) | |
1940 | FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status)) | |
1941 | /* NOTE: the comma operator will make "cond" to eval to false, | |
1942 | * but float*_is_unordered() is still called | |
1943 | */ | |
1944 | FOP_COND(d, sf, 1, (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0)) | |
1945 | FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status)) | |
1946 | FOP_COND(d, seq, 1, float64_eq(FDT0, FDT1, &env->fp_status)) | |
1947 | FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status)) | |
1948 | FOP_COND(d, lt, 1, float64_lt(FDT0, FDT1, &env->fp_status)) | |
1949 | FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status)) | |
1950 | FOP_COND(d, le, 1, float64_le(FDT0, FDT1, &env->fp_status)) | |
1951 | FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status)) | |
1952 | ||
1953 | flag float32_is_unordered(float32 a, float32 b STATUS_PARAM) | |
1954 | { | |
1955 | extern flag float32_is_nan( float32 a ); | |
1956 | if (float32_is_nan(a) || float32_is_nan(b)) { | |
1957 | float_raise(float_flag_invalid, status); | |
1958 | return 1; | |
1959 | } | |
1960 | else { | |
1961 | return 0; | |
1962 | } | |
1963 | } | |
1964 | ||
1965 | /* NOTE: the comma operator will make "cond" to eval to false, | |
1966 | * but float*_is_unordered() is still called | |
1967 | */ | |
1968 | FOP_COND(s, f, 0, 0) | |
1969 | FOP_COND(s, un, 0, float32_is_unordered(FST1, FST0, &env->fp_status)) | |
1970 | FOP_COND(s, eq, 0, float32_eq(FST0, FST1, &env->fp_status)) | |
1971 | FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status)) | |
1972 | FOP_COND(s, olt, 0, float32_lt(FST0, FST1, &env->fp_status)) | |
1973 | FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status)) | |
1974 | FOP_COND(s, ole, 0, float32_le(FST0, FST1, &env->fp_status)) | |
1975 | FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status)) | |
1976 | /* NOTE: the comma operator will make "cond" to eval to false, | |
1977 | * but float*_is_unordered() is still called | |
1978 | */ | |
1979 | FOP_COND(s, sf, 1, (float32_is_unordered(FST0, FST1, &env->fp_status), 0)) | |
1980 | FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status)) | |
1981 | FOP_COND(s, seq, 1, float32_eq(FST0, FST1, &env->fp_status)) | |
1982 | FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status)) | |
1983 | FOP_COND(s, lt, 1, float32_lt(FST0, FST1, &env->fp_status)) | |
1984 | FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status)) | |
1985 | FOP_COND(s, le, 1, float32_le(FST0, FST1, &env->fp_status)) | |
1986 | FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status)) | |
1987 | ||
1988 | void op_bc1f (void) | |
1989 | { | |
1990 | T0 = ! IS_FP_COND_SET(env->fcr31); | |
1991 | DEBUG_FPU_STATE(); | |
1992 | RETURN(); | |
1993 | } | |
1994 | ||
1995 | void op_bc1t (void) | |
1996 | { | |
1997 | T0 = IS_FP_COND_SET(env->fcr31); | |
1998 | DEBUG_FPU_STATE(); | |
1999 | RETURN(); | |
2000 | } | |
6ea83fed | 2001 | |
6af0bf9c FB |
2002 | #if defined(MIPS_USES_R4K_TLB) |
2003 | void op_tlbwi (void) | |
2004 | { | |
2005 | CALL_FROM_TB0(do_tlbwi); | |
2006 | RETURN(); | |
2007 | } | |
2008 | ||
2009 | void op_tlbwr (void) | |
2010 | { | |
2011 | CALL_FROM_TB0(do_tlbwr); | |
2012 | RETURN(); | |
2013 | } | |
2014 | ||
2015 | void op_tlbp (void) | |
2016 | { | |
2017 | CALL_FROM_TB0(do_tlbp); | |
2018 | RETURN(); | |
2019 | } | |
2020 | ||
2021 | void op_tlbr (void) | |
2022 | { | |
2023 | CALL_FROM_TB0(do_tlbr); | |
2024 | RETURN(); | |
2025 | } | |
2026 | #endif | |
2027 | ||
2028 | /* Specials */ | |
6f5b89a0 TS |
2029 | #if defined (CONFIG_USER_ONLY) |
2030 | void op_tls_value (void) | |
2031 | { | |
2032 | T0 = env->tls_value; | |
2033 | } | |
2034 | #endif | |
2035 | ||
6af0bf9c FB |
2036 | void op_pmon (void) |
2037 | { | |
2038 | CALL_FROM_TB1(do_pmon, PARAM1); | |
7a387fff TS |
2039 | RETURN(); |
2040 | } | |
2041 | ||
2042 | void op_di (void) | |
2043 | { | |
7a387fff | 2044 | T0 = env->CP0_Status; |
4de9b249 TS |
2045 | env->CP0_Status = T0 & ~(1 << CP0St_IE); |
2046 | CALL_FROM_TB1(cpu_mips_update_irq, env); | |
7a387fff TS |
2047 | RETURN(); |
2048 | } | |
2049 | ||
2050 | void op_ei (void) | |
2051 | { | |
7a387fff | 2052 | T0 = env->CP0_Status; |
4de9b249 TS |
2053 | env->CP0_Status = T0 | (1 << CP0St_IE); |
2054 | CALL_FROM_TB1(cpu_mips_update_irq, env); | |
7a387fff | 2055 | RETURN(); |
6af0bf9c FB |
2056 | } |
2057 | ||
2058 | void op_trap (void) | |
2059 | { | |
2060 | if (T0) { | |
4ad40f36 | 2061 | CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP); |
6af0bf9c FB |
2062 | } |
2063 | RETURN(); | |
2064 | } | |
2065 | ||
4ad40f36 FB |
2066 | void op_debug (void) |
2067 | { | |
7a387fff TS |
2068 | CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
2069 | RETURN(); | |
4ad40f36 FB |
2070 | } |
2071 | ||
6af0bf9c FB |
2072 | void op_set_lladdr (void) |
2073 | { | |
2074 | env->CP0_LLAddr = T2; | |
7a387fff | 2075 | RETURN(); |
6af0bf9c FB |
2076 | } |
2077 | ||
2078 | void debug_eret (void); | |
2079 | void op_eret (void) | |
2080 | { | |
2081 | CALL_FROM_TB0(debug_eret); | |
51e11d9e | 2082 | if (env->hflags & MIPS_HFLAG_ERL) { |
6af0bf9c | 2083 | env->PC = env->CP0_ErrorEPC; |
51e11d9e | 2084 | env->hflags &= ~MIPS_HFLAG_ERL; |
3e382bc8 | 2085 | env->CP0_Status &= ~(1 << CP0St_ERL); |
51e11d9e | 2086 | } else { |
6af0bf9c | 2087 | env->PC = env->CP0_EPC; |
51e11d9e | 2088 | env->hflags &= ~MIPS_HFLAG_EXL; |
3e382bc8 | 2089 | env->CP0_Status &= ~(1 << CP0St_EXL); |
51e11d9e | 2090 | } |
6af0bf9c | 2091 | env->CP0_LLAddr = 1; |
7a387fff | 2092 | RETURN(); |
6af0bf9c FB |
2093 | } |
2094 | ||
2095 | void op_deret (void) | |
2096 | { | |
2097 | CALL_FROM_TB0(debug_eret); | |
2098 | env->PC = env->CP0_DEPC; | |
7a387fff TS |
2099 | RETURN(); |
2100 | } | |
2101 | ||
2102 | void op_rdhwr_cpunum(void) | |
2103 | { | |
2104 | if (env->CP0_HWREna & (1 << 0)) | |
2105 | T0 = env->CP0_EBase & 0x2ff; | |
2106 | else | |
2107 | CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); | |
2108 | RETURN(); | |
2109 | } | |
2110 | ||
2111 | void op_rdhwr_synci_step(void) | |
2112 | { | |
2113 | if (env->CP0_HWREna & (1 << 1)) | |
2114 | T0 = env->SYNCI_Step; | |
2115 | else | |
2116 | CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); | |
2117 | RETURN(); | |
2118 | } | |
2119 | ||
2120 | void op_rdhwr_cc(void) | |
2121 | { | |
2122 | if (env->CP0_HWREna & (1 << 2)) | |
2123 | T0 = env->CP0_Count; | |
2124 | else | |
2125 | CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); | |
2126 | RETURN(); | |
2127 | } | |
2128 | ||
2129 | void op_rdhwr_ccres(void) | |
2130 | { | |
2131 | if (env->CP0_HWREna & (1 << 3)) | |
2132 | T0 = env->CCRes; | |
2133 | else | |
2134 | CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI); | |
2135 | RETURN(); | |
6af0bf9c FB |
2136 | } |
2137 | ||
2138 | void op_save_state (void) | |
2139 | { | |
2140 | env->hflags = PARAM1; | |
2141 | RETURN(); | |
2142 | } | |
2143 | ||
2144 | void op_save_pc (void) | |
2145 | { | |
2146 | env->PC = PARAM1; | |
2147 | RETURN(); | |
2148 | } | |
2149 | ||
2150 | void op_raise_exception (void) | |
2151 | { | |
2152 | CALL_FROM_TB1(do_raise_exception, PARAM1); | |
2153 | RETURN(); | |
2154 | } | |
2155 | ||
2156 | void op_raise_exception_err (void) | |
2157 | { | |
2158 | CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); | |
2159 | RETURN(); | |
2160 | } | |
2161 | ||
2162 | void op_exit_tb (void) | |
2163 | { | |
2164 | EXIT_TB(); | |
7a387fff | 2165 | RETURN(); |
6af0bf9c FB |
2166 | } |
2167 | ||
4ad40f36 FB |
2168 | void op_wait (void) |
2169 | { | |
2170 | env->halted = 1; | |
2171 | CALL_FROM_TB1(do_raise_exception, EXCP_HLT); | |
7a387fff TS |
2172 | RETURN(); |
2173 | } | |
2174 | ||
2175 | /* Bitfield operations. */ | |
2176 | void op_ext(void) | |
2177 | { | |
2178 | unsigned int pos = PARAM1; | |
2179 | unsigned int size = PARAM2; | |
2180 | ||
c570fd16 | 2181 | T0 = ((uint32_t)T1 >> pos) & ((1 << size) - 1); |
7a387fff TS |
2182 | RETURN(); |
2183 | } | |
2184 | ||
2185 | void op_ins(void) | |
2186 | { | |
2187 | unsigned int pos = PARAM1; | |
2188 | unsigned int size = PARAM2; | |
2189 | target_ulong mask = ((1 << size) - 1) << pos; | |
2190 | ||
c570fd16 | 2191 | T0 = (T2 & ~mask) | (((uint32_t)T1 << pos) & mask); |
7a387fff TS |
2192 | RETURN(); |
2193 | } | |
2194 | ||
2195 | void op_wsbh(void) | |
2196 | { | |
2197 | T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF); | |
2198 | RETURN(); | |
2199 | } | |
2200 | ||
c570fd16 TS |
2201 | #ifdef MIPS_HAS_MIPS64 |
2202 | void op_dext(void) | |
2203 | { | |
2204 | unsigned int pos = PARAM1; | |
2205 | unsigned int size = PARAM2; | |
2206 | ||
2207 | T0 = (T1 >> pos) & ((1 << size) - 1); | |
2208 | RETURN(); | |
2209 | } | |
2210 | ||
2211 | void op_dins(void) | |
2212 | { | |
2213 | unsigned int pos = PARAM1; | |
2214 | unsigned int size = PARAM2; | |
2215 | target_ulong mask = ((1 << size) - 1) << pos; | |
2216 | ||
2217 | T0 = (T2 & ~mask) | ((T1 << pos) & mask); | |
2218 | RETURN(); | |
2219 | } | |
2220 | ||
7a387fff TS |
2221 | void op_dsbh(void) |
2222 | { | |
2223 | T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); | |
2224 | RETURN(); | |
2225 | } | |
2226 | ||
2227 | void op_dshd(void) | |
2228 | { | |
2229 | T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); | |
2230 | RETURN(); | |
2231 | } | |
c570fd16 | 2232 | #endif |
7a387fff TS |
2233 | |
2234 | void op_seb(void) | |
2235 | { | |
2236 | T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; | |
2237 | RETURN(); | |
2238 | } | |
2239 | ||
2240 | void op_seh(void) | |
2241 | { | |
2242 | T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; | |
2243 | RETURN(); | |
4ad40f36 | 2244 | } |