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Commit | Line | Data |
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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
fad6cb1a | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
6af0bf9c | 19 | */ |
2d0e944d | 20 | #include <stdlib.h> |
6af0bf9c FB |
21 | #include "exec.h" |
22 | ||
05f778c8 TS |
23 | #include "host-utils.h" |
24 | ||
a7812ae4 | 25 | #include "helper.h" |
6af0bf9c FB |
26 | /*****************************************************************************/ |
27 | /* Exceptions processing helpers */ | |
6af0bf9c | 28 | |
6af0bf9c FB |
29 | void do_raise_exception_err (uint32_t exception, int error_code) |
30 | { | |
31 | #if 1 | |
93fcfe39 AL |
32 | if (exception < 0x100) |
33 | qemu_log("%s: %d %d\n", __func__, exception, error_code); | |
6af0bf9c FB |
34 | #endif |
35 | env->exception_index = exception; | |
36 | env->error_code = error_code; | |
6af0bf9c FB |
37 | cpu_loop_exit(); |
38 | } | |
39 | ||
6af0bf9c FB |
40 | void do_raise_exception (uint32_t exception) |
41 | { | |
42 | do_raise_exception_err(exception, 0); | |
43 | } | |
44 | ||
48d38ca5 TS |
45 | void do_interrupt_restart (void) |
46 | { | |
47 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && | |
48 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
49 | !(env->hflags & MIPS_HFLAG_DM) && | |
50 | (env->CP0_Status & (1 << CP0St_IE)) && | |
51 | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { | |
52 | env->CP0_Cause &= ~(0x1f << CP0Ca_EC); | |
53 | do_raise_exception(EXCP_EXT_INTERRUPT); | |
54 | } | |
55 | } | |
56 | ||
f9480ffc TS |
57 | #if !defined(CONFIG_USER_ONLY) |
58 | static void do_restore_state (void *pc_ptr) | |
4ad40f36 | 59 | { |
a607922c FB |
60 | TranslationBlock *tb; |
61 | unsigned long pc = (unsigned long) pc_ptr; | |
62 | ||
63 | tb = tb_find_pc (pc); | |
64 | if (tb) { | |
65 | cpu_restore_state (tb, env, pc, NULL); | |
66 | } | |
4ad40f36 | 67 | } |
f9480ffc | 68 | #endif |
4ad40f36 | 69 | |
be24bb4f | 70 | target_ulong do_clo (target_ulong t0) |
30898801 | 71 | { |
be24bb4f | 72 | return clo32(t0); |
30898801 TS |
73 | } |
74 | ||
be24bb4f | 75 | target_ulong do_clz (target_ulong t0) |
30898801 | 76 | { |
be24bb4f | 77 | return clz32(t0); |
30898801 TS |
78 | } |
79 | ||
d26bc211 | 80 | #if defined(TARGET_MIPS64) |
be24bb4f | 81 | target_ulong do_dclo (target_ulong t0) |
05f778c8 | 82 | { |
be24bb4f | 83 | return clo64(t0); |
05f778c8 TS |
84 | } |
85 | ||
be24bb4f | 86 | target_ulong do_dclz (target_ulong t0) |
05f778c8 | 87 | { |
be24bb4f | 88 | return clz64(t0); |
05f778c8 | 89 | } |
d26bc211 | 90 | #endif /* TARGET_MIPS64 */ |
c570fd16 | 91 | |
6af0bf9c | 92 | /* 64 bits arithmetic for 32 bits hosts */ |
c904ef0e | 93 | static inline uint64_t get_HILO (void) |
6af0bf9c | 94 | { |
b5dc7732 | 95 | return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; |
6af0bf9c FB |
96 | } |
97 | ||
c904ef0e | 98 | static inline void set_HILO (uint64_t HILO) |
6af0bf9c | 99 | { |
b5dc7732 TS |
100 | env->active_tc.LO[0] = (int32_t)HILO; |
101 | env->active_tc.HI[0] = (int32_t)(HILO >> 32); | |
6af0bf9c FB |
102 | } |
103 | ||
c904ef0e | 104 | static inline void set_HIT0_LO (target_ulong t0, uint64_t HILO) |
e9c71dd1 | 105 | { |
b5dc7732 TS |
106 | env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
107 | t0 = env->active_tc.HI[0] = (int32_t)(HILO >> 32); | |
e9c71dd1 TS |
108 | } |
109 | ||
c904ef0e | 110 | static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO) |
e9c71dd1 | 111 | { |
b5dc7732 TS |
112 | t0 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
113 | env->active_tc.HI[0] = (int32_t)(HILO >> 32); | |
e9c71dd1 TS |
114 | } |
115 | ||
92af06d2 | 116 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
be24bb4f | 117 | void do_madd (target_ulong t0, target_ulong t1) |
6af0bf9c FB |
118 | { |
119 | int64_t tmp; | |
120 | ||
be24bb4f | 121 | tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1); |
6af0bf9c FB |
122 | set_HILO((int64_t)get_HILO() + tmp); |
123 | } | |
124 | ||
be24bb4f | 125 | void do_maddu (target_ulong t0, target_ulong t1) |
6af0bf9c FB |
126 | { |
127 | uint64_t tmp; | |
128 | ||
be24bb4f | 129 | tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1); |
6af0bf9c FB |
130 | set_HILO(get_HILO() + tmp); |
131 | } | |
132 | ||
be24bb4f | 133 | void do_msub (target_ulong t0, target_ulong t1) |
6af0bf9c FB |
134 | { |
135 | int64_t tmp; | |
136 | ||
be24bb4f | 137 | tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1); |
6af0bf9c FB |
138 | set_HILO((int64_t)get_HILO() - tmp); |
139 | } | |
140 | ||
be24bb4f | 141 | void do_msubu (target_ulong t0, target_ulong t1) |
6af0bf9c FB |
142 | { |
143 | uint64_t tmp; | |
144 | ||
be24bb4f | 145 | tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1); |
6af0bf9c FB |
146 | set_HILO(get_HILO() - tmp); |
147 | } | |
92af06d2 | 148 | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
e9c71dd1 TS |
149 | |
150 | /* Multiplication variants of the vr54xx. */ | |
be24bb4f | 151 | target_ulong do_muls (target_ulong t0, target_ulong t1) |
e9c71dd1 | 152 | { |
be24bb4f TS |
153 | set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); |
154 | ||
155 | return t0; | |
e9c71dd1 TS |
156 | } |
157 | ||
be24bb4f | 158 | target_ulong do_mulsu (target_ulong t0, target_ulong t1) |
e9c71dd1 | 159 | { |
be24bb4f TS |
160 | set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); |
161 | ||
162 | return t0; | |
e9c71dd1 TS |
163 | } |
164 | ||
be24bb4f | 165 | target_ulong do_macc (target_ulong t0, target_ulong t1) |
e9c71dd1 | 166 | { |
be24bb4f TS |
167 | set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); |
168 | ||
169 | return t0; | |
e9c71dd1 TS |
170 | } |
171 | ||
be24bb4f | 172 | target_ulong do_macchi (target_ulong t0, target_ulong t1) |
e9c71dd1 | 173 | { |
be24bb4f TS |
174 | set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); |
175 | ||
176 | return t0; | |
e9c71dd1 TS |
177 | } |
178 | ||
be24bb4f | 179 | target_ulong do_maccu (target_ulong t0, target_ulong t1) |
e9c71dd1 | 180 | { |
be24bb4f TS |
181 | set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); |
182 | ||
183 | return t0; | |
e9c71dd1 TS |
184 | } |
185 | ||
be24bb4f | 186 | target_ulong do_macchiu (target_ulong t0, target_ulong t1) |
e9c71dd1 | 187 | { |
be24bb4f TS |
188 | set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); |
189 | ||
190 | return t0; | |
e9c71dd1 TS |
191 | } |
192 | ||
be24bb4f | 193 | target_ulong do_msac (target_ulong t0, target_ulong t1) |
e9c71dd1 | 194 | { |
be24bb4f TS |
195 | set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); |
196 | ||
197 | return t0; | |
e9c71dd1 TS |
198 | } |
199 | ||
be24bb4f | 200 | target_ulong do_msachi (target_ulong t0, target_ulong t1) |
e9c71dd1 | 201 | { |
be24bb4f TS |
202 | set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); |
203 | ||
204 | return t0; | |
e9c71dd1 TS |
205 | } |
206 | ||
be24bb4f | 207 | target_ulong do_msacu (target_ulong t0, target_ulong t1) |
e9c71dd1 | 208 | { |
be24bb4f TS |
209 | set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); |
210 | ||
211 | return t0; | |
e9c71dd1 TS |
212 | } |
213 | ||
be24bb4f | 214 | target_ulong do_msachiu (target_ulong t0, target_ulong t1) |
e9c71dd1 | 215 | { |
be24bb4f TS |
216 | set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); |
217 | ||
218 | return t0; | |
e9c71dd1 TS |
219 | } |
220 | ||
be24bb4f | 221 | target_ulong do_mulhi (target_ulong t0, target_ulong t1) |
e9c71dd1 | 222 | { |
be24bb4f TS |
223 | set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1); |
224 | ||
225 | return t0; | |
e9c71dd1 TS |
226 | } |
227 | ||
be24bb4f | 228 | target_ulong do_mulhiu (target_ulong t0, target_ulong t1) |
e9c71dd1 | 229 | { |
be24bb4f TS |
230 | set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1); |
231 | ||
232 | return t0; | |
e9c71dd1 TS |
233 | } |
234 | ||
be24bb4f | 235 | target_ulong do_mulshi (target_ulong t0, target_ulong t1) |
e9c71dd1 | 236 | { |
be24bb4f TS |
237 | set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1)); |
238 | ||
239 | return t0; | |
e9c71dd1 TS |
240 | } |
241 | ||
be24bb4f | 242 | target_ulong do_mulshiu (target_ulong t0, target_ulong t1) |
e9c71dd1 | 243 | { |
be24bb4f TS |
244 | set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1)); |
245 | ||
246 | return t0; | |
e9c71dd1 | 247 | } |
6af0bf9c | 248 | |
214c465f | 249 | #ifdef TARGET_MIPS64 |
be24bb4f | 250 | void do_dmult (target_ulong t0, target_ulong t1) |
214c465f | 251 | { |
b5dc7732 | 252 | muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1); |
214c465f TS |
253 | } |
254 | ||
be24bb4f | 255 | void do_dmultu (target_ulong t0, target_ulong t1) |
214c465f | 256 | { |
b5dc7732 | 257 | mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1); |
214c465f TS |
258 | } |
259 | #endif | |
260 | ||
c8c2227e TS |
261 | #ifdef TARGET_WORDS_BIGENDIAN |
262 | #define GET_LMASK(v) ((v) & 3) | |
263 | #define GET_OFFSET(addr, offset) (addr + (offset)) | |
264 | #else | |
265 | #define GET_LMASK(v) (((v) & 3) ^ 3) | |
266 | #define GET_OFFSET(addr, offset) (addr - (offset)) | |
267 | #endif | |
268 | ||
be24bb4f | 269 | target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx) |
c8c2227e TS |
270 | { |
271 | target_ulong tmp; | |
272 | ||
273 | #ifdef CONFIG_USER_ONLY | |
274 | #define ldfun ldub_raw | |
275 | #else | |
276 | int (*ldfun)(target_ulong); | |
277 | ||
278 | switch (mem_idx) | |
279 | { | |
280 | case 0: ldfun = ldub_kernel; break; | |
281 | case 1: ldfun = ldub_super; break; | |
282 | default: | |
283 | case 2: ldfun = ldub_user; break; | |
284 | } | |
285 | #endif | |
be24bb4f TS |
286 | tmp = ldfun(t0); |
287 | t1 = (t1 & 0x00FFFFFF) | (tmp << 24); | |
c8c2227e | 288 | |
be24bb4f TS |
289 | if (GET_LMASK(t0) <= 2) { |
290 | tmp = ldfun(GET_OFFSET(t0, 1)); | |
291 | t1 = (t1 & 0xFF00FFFF) | (tmp << 16); | |
c8c2227e TS |
292 | } |
293 | ||
be24bb4f TS |
294 | if (GET_LMASK(t0) <= 1) { |
295 | tmp = ldfun(GET_OFFSET(t0, 2)); | |
296 | t1 = (t1 & 0xFFFF00FF) | (tmp << 8); | |
c8c2227e TS |
297 | } |
298 | ||
be24bb4f TS |
299 | if (GET_LMASK(t0) == 0) { |
300 | tmp = ldfun(GET_OFFSET(t0, 3)); | |
301 | t1 = (t1 & 0xFFFFFF00) | tmp; | |
c8c2227e | 302 | } |
be24bb4f | 303 | return (int32_t)t1; |
c8c2227e TS |
304 | } |
305 | ||
be24bb4f | 306 | target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx) |
c8c2227e TS |
307 | { |
308 | target_ulong tmp; | |
309 | ||
310 | #ifdef CONFIG_USER_ONLY | |
311 | #define ldfun ldub_raw | |
312 | #else | |
313 | int (*ldfun)(target_ulong); | |
314 | ||
315 | switch (mem_idx) | |
316 | { | |
317 | case 0: ldfun = ldub_kernel; break; | |
318 | case 1: ldfun = ldub_super; break; | |
319 | default: | |
320 | case 2: ldfun = ldub_user; break; | |
321 | } | |
322 | #endif | |
be24bb4f TS |
323 | tmp = ldfun(t0); |
324 | t1 = (t1 & 0xFFFFFF00) | tmp; | |
c8c2227e | 325 | |
be24bb4f TS |
326 | if (GET_LMASK(t0) >= 1) { |
327 | tmp = ldfun(GET_OFFSET(t0, -1)); | |
328 | t1 = (t1 & 0xFFFF00FF) | (tmp << 8); | |
c8c2227e TS |
329 | } |
330 | ||
be24bb4f TS |
331 | if (GET_LMASK(t0) >= 2) { |
332 | tmp = ldfun(GET_OFFSET(t0, -2)); | |
333 | t1 = (t1 & 0xFF00FFFF) | (tmp << 16); | |
c8c2227e TS |
334 | } |
335 | ||
be24bb4f TS |
336 | if (GET_LMASK(t0) == 3) { |
337 | tmp = ldfun(GET_OFFSET(t0, -3)); | |
338 | t1 = (t1 & 0x00FFFFFF) | (tmp << 24); | |
c8c2227e | 339 | } |
be24bb4f | 340 | return (int32_t)t1; |
c8c2227e TS |
341 | } |
342 | ||
be24bb4f | 343 | void do_swl(target_ulong t0, target_ulong t1, int mem_idx) |
c8c2227e TS |
344 | { |
345 | #ifdef CONFIG_USER_ONLY | |
346 | #define stfun stb_raw | |
347 | #else | |
348 | void (*stfun)(target_ulong, int); | |
349 | ||
350 | switch (mem_idx) | |
351 | { | |
352 | case 0: stfun = stb_kernel; break; | |
353 | case 1: stfun = stb_super; break; | |
354 | default: | |
355 | case 2: stfun = stb_user; break; | |
356 | } | |
357 | #endif | |
be24bb4f | 358 | stfun(t0, (uint8_t)(t1 >> 24)); |
c8c2227e | 359 | |
be24bb4f TS |
360 | if (GET_LMASK(t0) <= 2) |
361 | stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16)); | |
c8c2227e | 362 | |
be24bb4f TS |
363 | if (GET_LMASK(t0) <= 1) |
364 | stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8)); | |
c8c2227e | 365 | |
be24bb4f TS |
366 | if (GET_LMASK(t0) == 0) |
367 | stfun(GET_OFFSET(t0, 3), (uint8_t)t1); | |
c8c2227e TS |
368 | } |
369 | ||
be24bb4f | 370 | void do_swr(target_ulong t0, target_ulong t1, int mem_idx) |
c8c2227e TS |
371 | { |
372 | #ifdef CONFIG_USER_ONLY | |
373 | #define stfun stb_raw | |
374 | #else | |
375 | void (*stfun)(target_ulong, int); | |
376 | ||
377 | switch (mem_idx) | |
378 | { | |
379 | case 0: stfun = stb_kernel; break; | |
380 | case 1: stfun = stb_super; break; | |
381 | default: | |
382 | case 2: stfun = stb_user; break; | |
383 | } | |
384 | #endif | |
be24bb4f | 385 | stfun(t0, (uint8_t)t1); |
c8c2227e | 386 | |
be24bb4f TS |
387 | if (GET_LMASK(t0) >= 1) |
388 | stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8)); | |
c8c2227e | 389 | |
be24bb4f TS |
390 | if (GET_LMASK(t0) >= 2) |
391 | stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16)); | |
c8c2227e | 392 | |
be24bb4f TS |
393 | if (GET_LMASK(t0) == 3) |
394 | stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24)); | |
c8c2227e TS |
395 | } |
396 | ||
397 | #if defined(TARGET_MIPS64) | |
398 | /* "half" load and stores. We must do the memory access inline, | |
399 | or fault handling won't work. */ | |
400 | ||
401 | #ifdef TARGET_WORDS_BIGENDIAN | |
402 | #define GET_LMASK64(v) ((v) & 7) | |
403 | #else | |
404 | #define GET_LMASK64(v) (((v) & 7) ^ 7) | |
405 | #endif | |
406 | ||
be24bb4f | 407 | target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx) |
c8c2227e TS |
408 | { |
409 | uint64_t tmp; | |
410 | ||
411 | #ifdef CONFIG_USER_ONLY | |
412 | #define ldfun ldub_raw | |
413 | #else | |
be24bb4f | 414 | int (*ldfun)(target_ulong); |
c8c2227e TS |
415 | |
416 | switch (mem_idx) | |
417 | { | |
418 | case 0: ldfun = ldub_kernel; break; | |
419 | case 1: ldfun = ldub_super; break; | |
420 | default: | |
421 | case 2: ldfun = ldub_user; break; | |
422 | } | |
423 | #endif | |
be24bb4f TS |
424 | tmp = ldfun(t0); |
425 | t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); | |
c8c2227e | 426 | |
be24bb4f TS |
427 | if (GET_LMASK64(t0) <= 6) { |
428 | tmp = ldfun(GET_OFFSET(t0, 1)); | |
429 | t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); | |
c8c2227e TS |
430 | } |
431 | ||
be24bb4f TS |
432 | if (GET_LMASK64(t0) <= 5) { |
433 | tmp = ldfun(GET_OFFSET(t0, 2)); | |
434 | t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); | |
c8c2227e TS |
435 | } |
436 | ||
be24bb4f TS |
437 | if (GET_LMASK64(t0) <= 4) { |
438 | tmp = ldfun(GET_OFFSET(t0, 3)); | |
439 | t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); | |
c8c2227e TS |
440 | } |
441 | ||
be24bb4f TS |
442 | if (GET_LMASK64(t0) <= 3) { |
443 | tmp = ldfun(GET_OFFSET(t0, 4)); | |
444 | t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); | |
c8c2227e TS |
445 | } |
446 | ||
be24bb4f TS |
447 | if (GET_LMASK64(t0) <= 2) { |
448 | tmp = ldfun(GET_OFFSET(t0, 5)); | |
449 | t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); | |
c8c2227e TS |
450 | } |
451 | ||
be24bb4f TS |
452 | if (GET_LMASK64(t0) <= 1) { |
453 | tmp = ldfun(GET_OFFSET(t0, 6)); | |
454 | t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); | |
c8c2227e TS |
455 | } |
456 | ||
be24bb4f TS |
457 | if (GET_LMASK64(t0) == 0) { |
458 | tmp = ldfun(GET_OFFSET(t0, 7)); | |
459 | t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; | |
c8c2227e | 460 | } |
be24bb4f TS |
461 | |
462 | return t1; | |
c8c2227e TS |
463 | } |
464 | ||
be24bb4f | 465 | target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx) |
c8c2227e TS |
466 | { |
467 | uint64_t tmp; | |
468 | ||
469 | #ifdef CONFIG_USER_ONLY | |
470 | #define ldfun ldub_raw | |
471 | #else | |
be24bb4f | 472 | int (*ldfun)(target_ulong); |
c8c2227e TS |
473 | |
474 | switch (mem_idx) | |
475 | { | |
476 | case 0: ldfun = ldub_kernel; break; | |
477 | case 1: ldfun = ldub_super; break; | |
478 | default: | |
479 | case 2: ldfun = ldub_user; break; | |
480 | } | |
481 | #endif | |
be24bb4f TS |
482 | tmp = ldfun(t0); |
483 | t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; | |
c8c2227e | 484 | |
be24bb4f TS |
485 | if (GET_LMASK64(t0) >= 1) { |
486 | tmp = ldfun(GET_OFFSET(t0, -1)); | |
487 | t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); | |
c8c2227e TS |
488 | } |
489 | ||
be24bb4f TS |
490 | if (GET_LMASK64(t0) >= 2) { |
491 | tmp = ldfun(GET_OFFSET(t0, -2)); | |
492 | t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); | |
c8c2227e TS |
493 | } |
494 | ||
be24bb4f TS |
495 | if (GET_LMASK64(t0) >= 3) { |
496 | tmp = ldfun(GET_OFFSET(t0, -3)); | |
497 | t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); | |
c8c2227e TS |
498 | } |
499 | ||
be24bb4f TS |
500 | if (GET_LMASK64(t0) >= 4) { |
501 | tmp = ldfun(GET_OFFSET(t0, -4)); | |
502 | t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); | |
c8c2227e TS |
503 | } |
504 | ||
be24bb4f TS |
505 | if (GET_LMASK64(t0) >= 5) { |
506 | tmp = ldfun(GET_OFFSET(t0, -5)); | |
507 | t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); | |
c8c2227e TS |
508 | } |
509 | ||
be24bb4f TS |
510 | if (GET_LMASK64(t0) >= 6) { |
511 | tmp = ldfun(GET_OFFSET(t0, -6)); | |
512 | t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); | |
c8c2227e TS |
513 | } |
514 | ||
be24bb4f TS |
515 | if (GET_LMASK64(t0) == 7) { |
516 | tmp = ldfun(GET_OFFSET(t0, -7)); | |
517 | t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); | |
c8c2227e | 518 | } |
be24bb4f TS |
519 | |
520 | return t1; | |
c8c2227e TS |
521 | } |
522 | ||
be24bb4f | 523 | void do_sdl(target_ulong t0, target_ulong t1, int mem_idx) |
c8c2227e TS |
524 | { |
525 | #ifdef CONFIG_USER_ONLY | |
526 | #define stfun stb_raw | |
527 | #else | |
528 | void (*stfun)(target_ulong, int); | |
529 | ||
530 | switch (mem_idx) | |
531 | { | |
532 | case 0: stfun = stb_kernel; break; | |
533 | case 1: stfun = stb_super; break; | |
534 | default: | |
535 | case 2: stfun = stb_user; break; | |
536 | } | |
537 | #endif | |
be24bb4f | 538 | stfun(t0, (uint8_t)(t1 >> 56)); |
c8c2227e | 539 | |
be24bb4f TS |
540 | if (GET_LMASK64(t0) <= 6) |
541 | stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48)); | |
c8c2227e | 542 | |
be24bb4f TS |
543 | if (GET_LMASK64(t0) <= 5) |
544 | stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40)); | |
c8c2227e | 545 | |
be24bb4f TS |
546 | if (GET_LMASK64(t0) <= 4) |
547 | stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32)); | |
c8c2227e | 548 | |
be24bb4f TS |
549 | if (GET_LMASK64(t0) <= 3) |
550 | stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24)); | |
c8c2227e | 551 | |
be24bb4f TS |
552 | if (GET_LMASK64(t0) <= 2) |
553 | stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16)); | |
c8c2227e | 554 | |
be24bb4f TS |
555 | if (GET_LMASK64(t0) <= 1) |
556 | stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8)); | |
c8c2227e | 557 | |
be24bb4f TS |
558 | if (GET_LMASK64(t0) <= 0) |
559 | stfun(GET_OFFSET(t0, 7), (uint8_t)t1); | |
c8c2227e TS |
560 | } |
561 | ||
be24bb4f | 562 | void do_sdr(target_ulong t0, target_ulong t1, int mem_idx) |
c8c2227e TS |
563 | { |
564 | #ifdef CONFIG_USER_ONLY | |
565 | #define stfun stb_raw | |
566 | #else | |
567 | void (*stfun)(target_ulong, int); | |
568 | ||
569 | switch (mem_idx) | |
570 | { | |
571 | case 0: stfun = stb_kernel; break; | |
572 | case 1: stfun = stb_super; break; | |
573 | default: | |
574 | case 2: stfun = stb_user; break; | |
575 | } | |
576 | #endif | |
be24bb4f | 577 | stfun(t0, (uint8_t)t1); |
c8c2227e | 578 | |
be24bb4f TS |
579 | if (GET_LMASK64(t0) >= 1) |
580 | stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8)); | |
c8c2227e | 581 | |
be24bb4f TS |
582 | if (GET_LMASK64(t0) >= 2) |
583 | stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16)); | |
c8c2227e | 584 | |
be24bb4f TS |
585 | if (GET_LMASK64(t0) >= 3) |
586 | stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24)); | |
c8c2227e | 587 | |
be24bb4f TS |
588 | if (GET_LMASK64(t0) >= 4) |
589 | stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32)); | |
c8c2227e | 590 | |
be24bb4f TS |
591 | if (GET_LMASK64(t0) >= 5) |
592 | stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40)); | |
c8c2227e | 593 | |
be24bb4f TS |
594 | if (GET_LMASK64(t0) >= 6) |
595 | stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48)); | |
c8c2227e | 596 | |
be24bb4f TS |
597 | if (GET_LMASK64(t0) == 7) |
598 | stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56)); | |
c8c2227e TS |
599 | } |
600 | #endif /* TARGET_MIPS64 */ | |
601 | ||
0eaef5aa | 602 | #ifndef CONFIG_USER_ONLY |
6af0bf9c | 603 | /* CP0 helpers */ |
1a3fd9c3 | 604 | target_ulong do_mfc0_mvpcontrol (void) |
f1aa6320 | 605 | { |
be24bb4f | 606 | return env->mvp->CP0_MVPControl; |
f1aa6320 TS |
607 | } |
608 | ||
1a3fd9c3 | 609 | target_ulong do_mfc0_mvpconf0 (void) |
f1aa6320 | 610 | { |
be24bb4f | 611 | return env->mvp->CP0_MVPConf0; |
f1aa6320 TS |
612 | } |
613 | ||
1a3fd9c3 | 614 | target_ulong do_mfc0_mvpconf1 (void) |
f1aa6320 | 615 | { |
be24bb4f | 616 | return env->mvp->CP0_MVPConf1; |
f1aa6320 TS |
617 | } |
618 | ||
1a3fd9c3 | 619 | target_ulong do_mfc0_random (void) |
6af0bf9c | 620 | { |
be24bb4f | 621 | return (int32_t)cpu_mips_get_random(env); |
873eb012 | 622 | } |
6af0bf9c | 623 | |
1a3fd9c3 | 624 | target_ulong do_mfc0_tcstatus (void) |
f1aa6320 | 625 | { |
b5dc7732 | 626 | return env->active_tc.CP0_TCStatus; |
f1aa6320 TS |
627 | } |
628 | ||
1a3fd9c3 | 629 | target_ulong do_mftc0_tcstatus(void) |
f1aa6320 TS |
630 | { |
631 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
632 | ||
b5dc7732 TS |
633 | if (other_tc == env->current_tc) |
634 | return env->active_tc.CP0_TCStatus; | |
635 | else | |
636 | return env->tcs[other_tc].CP0_TCStatus; | |
f1aa6320 TS |
637 | } |
638 | ||
1a3fd9c3 | 639 | target_ulong do_mfc0_tcbind (void) |
f1aa6320 | 640 | { |
b5dc7732 | 641 | return env->active_tc.CP0_TCBind; |
f1aa6320 TS |
642 | } |
643 | ||
1a3fd9c3 | 644 | target_ulong do_mftc0_tcbind(void) |
f1aa6320 TS |
645 | { |
646 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
647 | ||
b5dc7732 TS |
648 | if (other_tc == env->current_tc) |
649 | return env->active_tc.CP0_TCBind; | |
650 | else | |
651 | return env->tcs[other_tc].CP0_TCBind; | |
f1aa6320 TS |
652 | } |
653 | ||
1a3fd9c3 | 654 | target_ulong do_mfc0_tcrestart (void) |
f1aa6320 | 655 | { |
b5dc7732 | 656 | return env->active_tc.PC; |
f1aa6320 TS |
657 | } |
658 | ||
1a3fd9c3 | 659 | target_ulong do_mftc0_tcrestart(void) |
f1aa6320 TS |
660 | { |
661 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
662 | ||
b5dc7732 TS |
663 | if (other_tc == env->current_tc) |
664 | return env->active_tc.PC; | |
665 | else | |
666 | return env->tcs[other_tc].PC; | |
f1aa6320 TS |
667 | } |
668 | ||
1a3fd9c3 | 669 | target_ulong do_mfc0_tchalt (void) |
f1aa6320 | 670 | { |
b5dc7732 | 671 | return env->active_tc.CP0_TCHalt; |
f1aa6320 TS |
672 | } |
673 | ||
1a3fd9c3 | 674 | target_ulong do_mftc0_tchalt(void) |
f1aa6320 TS |
675 | { |
676 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
677 | ||
b5dc7732 TS |
678 | if (other_tc == env->current_tc) |
679 | return env->active_tc.CP0_TCHalt; | |
680 | else | |
681 | return env->tcs[other_tc].CP0_TCHalt; | |
f1aa6320 TS |
682 | } |
683 | ||
1a3fd9c3 | 684 | target_ulong do_mfc0_tccontext (void) |
f1aa6320 | 685 | { |
b5dc7732 | 686 | return env->active_tc.CP0_TCContext; |
f1aa6320 TS |
687 | } |
688 | ||
1a3fd9c3 | 689 | target_ulong do_mftc0_tccontext(void) |
f1aa6320 TS |
690 | { |
691 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
692 | ||
b5dc7732 TS |
693 | if (other_tc == env->current_tc) |
694 | return env->active_tc.CP0_TCContext; | |
695 | else | |
696 | return env->tcs[other_tc].CP0_TCContext; | |
f1aa6320 TS |
697 | } |
698 | ||
1a3fd9c3 | 699 | target_ulong do_mfc0_tcschedule (void) |
f1aa6320 | 700 | { |
b5dc7732 | 701 | return env->active_tc.CP0_TCSchedule; |
f1aa6320 TS |
702 | } |
703 | ||
1a3fd9c3 | 704 | target_ulong do_mftc0_tcschedule(void) |
f1aa6320 TS |
705 | { |
706 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
707 | ||
b5dc7732 TS |
708 | if (other_tc == env->current_tc) |
709 | return env->active_tc.CP0_TCSchedule; | |
710 | else | |
711 | return env->tcs[other_tc].CP0_TCSchedule; | |
f1aa6320 TS |
712 | } |
713 | ||
1a3fd9c3 | 714 | target_ulong do_mfc0_tcschefback (void) |
f1aa6320 | 715 | { |
b5dc7732 | 716 | return env->active_tc.CP0_TCScheFBack; |
f1aa6320 TS |
717 | } |
718 | ||
1a3fd9c3 | 719 | target_ulong do_mftc0_tcschefback(void) |
f1aa6320 TS |
720 | { |
721 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
722 | ||
b5dc7732 TS |
723 | if (other_tc == env->current_tc) |
724 | return env->active_tc.CP0_TCScheFBack; | |
725 | else | |
726 | return env->tcs[other_tc].CP0_TCScheFBack; | |
f1aa6320 TS |
727 | } |
728 | ||
1a3fd9c3 | 729 | target_ulong do_mfc0_count (void) |
873eb012 | 730 | { |
be24bb4f | 731 | return (int32_t)cpu_mips_get_count(env); |
6af0bf9c FB |
732 | } |
733 | ||
1a3fd9c3 | 734 | target_ulong do_mftc0_entryhi(void) |
f1aa6320 TS |
735 | { |
736 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 | 737 | int32_t tcstatus; |
f1aa6320 | 738 | |
b5dc7732 TS |
739 | if (other_tc == env->current_tc) |
740 | tcstatus = env->active_tc.CP0_TCStatus; | |
741 | else | |
742 | tcstatus = env->tcs[other_tc].CP0_TCStatus; | |
743 | ||
744 | return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff); | |
f1aa6320 TS |
745 | } |
746 | ||
1a3fd9c3 | 747 | target_ulong do_mftc0_status(void) |
f1aa6320 TS |
748 | { |
749 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1a3fd9c3 | 750 | target_ulong t0; |
b5dc7732 TS |
751 | int32_t tcstatus; |
752 | ||
753 | if (other_tc == env->current_tc) | |
754 | tcstatus = env->active_tc.CP0_TCStatus; | |
755 | else | |
756 | tcstatus = env->tcs[other_tc].CP0_TCStatus; | |
f1aa6320 | 757 | |
be24bb4f TS |
758 | t0 = env->CP0_Status & ~0xf1000018; |
759 | t0 |= tcstatus & (0xf << CP0TCSt_TCU0); | |
760 | t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX); | |
761 | t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); | |
762 | ||
763 | return t0; | |
f1aa6320 TS |
764 | } |
765 | ||
1a3fd9c3 | 766 | target_ulong do_mfc0_lladdr (void) |
f1aa6320 | 767 | { |
be24bb4f | 768 | return (int32_t)env->CP0_LLAddr >> 4; |
f1aa6320 TS |
769 | } |
770 | ||
1a3fd9c3 | 771 | target_ulong do_mfc0_watchlo (uint32_t sel) |
f1aa6320 | 772 | { |
be24bb4f | 773 | return (int32_t)env->CP0_WatchLo[sel]; |
f1aa6320 TS |
774 | } |
775 | ||
1a3fd9c3 | 776 | target_ulong do_mfc0_watchhi (uint32_t sel) |
f1aa6320 | 777 | { |
be24bb4f | 778 | return env->CP0_WatchHi[sel]; |
f1aa6320 TS |
779 | } |
780 | ||
1a3fd9c3 | 781 | target_ulong do_mfc0_debug (void) |
f1aa6320 | 782 | { |
1a3fd9c3 | 783 | target_ulong t0 = env->CP0_Debug; |
f1aa6320 | 784 | if (env->hflags & MIPS_HFLAG_DM) |
be24bb4f TS |
785 | t0 |= 1 << CP0DB_DM; |
786 | ||
787 | return t0; | |
f1aa6320 TS |
788 | } |
789 | ||
1a3fd9c3 | 790 | target_ulong do_mftc0_debug(void) |
f1aa6320 TS |
791 | { |
792 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 TS |
793 | int32_t tcstatus; |
794 | ||
795 | if (other_tc == env->current_tc) | |
796 | tcstatus = env->active_tc.CP0_Debug_tcstatus; | |
797 | else | |
798 | tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus; | |
f1aa6320 TS |
799 | |
800 | /* XXX: Might be wrong, check with EJTAG spec. */ | |
be24bb4f | 801 | return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
b5dc7732 | 802 | (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
f1aa6320 TS |
803 | } |
804 | ||
805 | #if defined(TARGET_MIPS64) | |
1a3fd9c3 | 806 | target_ulong do_dmfc0_tcrestart (void) |
f1aa6320 | 807 | { |
b5dc7732 | 808 | return env->active_tc.PC; |
f1aa6320 TS |
809 | } |
810 | ||
1a3fd9c3 | 811 | target_ulong do_dmfc0_tchalt (void) |
f1aa6320 | 812 | { |
b5dc7732 | 813 | return env->active_tc.CP0_TCHalt; |
f1aa6320 TS |
814 | } |
815 | ||
1a3fd9c3 | 816 | target_ulong do_dmfc0_tccontext (void) |
f1aa6320 | 817 | { |
b5dc7732 | 818 | return env->active_tc.CP0_TCContext; |
f1aa6320 TS |
819 | } |
820 | ||
1a3fd9c3 | 821 | target_ulong do_dmfc0_tcschedule (void) |
f1aa6320 | 822 | { |
b5dc7732 | 823 | return env->active_tc.CP0_TCSchedule; |
f1aa6320 TS |
824 | } |
825 | ||
1a3fd9c3 | 826 | target_ulong do_dmfc0_tcschefback (void) |
f1aa6320 | 827 | { |
b5dc7732 | 828 | return env->active_tc.CP0_TCScheFBack; |
f1aa6320 TS |
829 | } |
830 | ||
1a3fd9c3 | 831 | target_ulong do_dmfc0_lladdr (void) |
f1aa6320 | 832 | { |
be24bb4f | 833 | return env->CP0_LLAddr >> 4; |
f1aa6320 TS |
834 | } |
835 | ||
1a3fd9c3 | 836 | target_ulong do_dmfc0_watchlo (uint32_t sel) |
f1aa6320 | 837 | { |
be24bb4f | 838 | return env->CP0_WatchLo[sel]; |
f1aa6320 TS |
839 | } |
840 | #endif /* TARGET_MIPS64 */ | |
841 | ||
be24bb4f | 842 | void do_mtc0_index (target_ulong t0) |
f1aa6320 TS |
843 | { |
844 | int num = 1; | |
845 | unsigned int tmp = env->tlb->nb_tlb; | |
846 | ||
847 | do { | |
848 | tmp >>= 1; | |
849 | num <<= 1; | |
850 | } while (tmp); | |
be24bb4f | 851 | env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1)); |
f1aa6320 TS |
852 | } |
853 | ||
be24bb4f | 854 | void do_mtc0_mvpcontrol (target_ulong t0) |
f1aa6320 TS |
855 | { |
856 | uint32_t mask = 0; | |
857 | uint32_t newval; | |
858 | ||
859 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) | |
860 | mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | | |
861 | (1 << CP0MVPCo_EVP); | |
862 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
863 | mask |= (1 << CP0MVPCo_STLB); | |
be24bb4f | 864 | newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask); |
f1aa6320 TS |
865 | |
866 | // TODO: Enable/disable shared TLB, enable/disable VPEs. | |
867 | ||
868 | env->mvp->CP0_MVPControl = newval; | |
869 | } | |
870 | ||
be24bb4f | 871 | void do_mtc0_vpecontrol (target_ulong t0) |
f1aa6320 TS |
872 | { |
873 | uint32_t mask; | |
874 | uint32_t newval; | |
875 | ||
876 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | | |
877 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); | |
be24bb4f | 878 | newval = (env->CP0_VPEControl & ~mask) | (t0 & mask); |
f1aa6320 TS |
879 | |
880 | /* Yield scheduler intercept not implemented. */ | |
881 | /* Gating storage scheduler intercept not implemented. */ | |
882 | ||
883 | // TODO: Enable/disable TCs. | |
884 | ||
885 | env->CP0_VPEControl = newval; | |
886 | } | |
887 | ||
be24bb4f | 888 | void do_mtc0_vpeconf0 (target_ulong t0) |
f1aa6320 TS |
889 | { |
890 | uint32_t mask = 0; | |
891 | uint32_t newval; | |
892 | ||
893 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { | |
894 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) | |
895 | mask |= (0xff << CP0VPEC0_XTC); | |
896 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); | |
897 | } | |
be24bb4f | 898 | newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask); |
f1aa6320 TS |
899 | |
900 | // TODO: TC exclusive handling due to ERL/EXL. | |
901 | ||
902 | env->CP0_VPEConf0 = newval; | |
903 | } | |
904 | ||
be24bb4f | 905 | void do_mtc0_vpeconf1 (target_ulong t0) |
f1aa6320 TS |
906 | { |
907 | uint32_t mask = 0; | |
908 | uint32_t newval; | |
909 | ||
910 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
911 | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | | |
912 | (0xff << CP0VPEC1_NCP1); | |
be24bb4f | 913 | newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask); |
f1aa6320 TS |
914 | |
915 | /* UDI not implemented. */ | |
916 | /* CP2 not implemented. */ | |
917 | ||
918 | // TODO: Handle FPU (CP1) binding. | |
919 | ||
920 | env->CP0_VPEConf1 = newval; | |
921 | } | |
922 | ||
be24bb4f | 923 | void do_mtc0_yqmask (target_ulong t0) |
f1aa6320 TS |
924 | { |
925 | /* Yield qualifier inputs not implemented. */ | |
926 | env->CP0_YQMask = 0x00000000; | |
927 | } | |
928 | ||
be24bb4f | 929 | void do_mtc0_vpeopt (target_ulong t0) |
f1aa6320 | 930 | { |
be24bb4f | 931 | env->CP0_VPEOpt = t0 & 0x0000ffff; |
f1aa6320 TS |
932 | } |
933 | ||
be24bb4f | 934 | void do_mtc0_entrylo0 (target_ulong t0) |
f1aa6320 TS |
935 | { |
936 | /* Large physaddr (PABITS) not implemented */ | |
937 | /* 1k pages not implemented */ | |
be24bb4f | 938 | env->CP0_EntryLo0 = t0 & 0x3FFFFFFF; |
f1aa6320 TS |
939 | } |
940 | ||
be24bb4f | 941 | void do_mtc0_tcstatus (target_ulong t0) |
f1aa6320 TS |
942 | { |
943 | uint32_t mask = env->CP0_TCStatus_rw_bitmask; | |
944 | uint32_t newval; | |
945 | ||
b5dc7732 | 946 | newval = (env->active_tc.CP0_TCStatus & ~mask) | (t0 & mask); |
f1aa6320 TS |
947 | |
948 | // TODO: Sync with CP0_Status. | |
949 | ||
b5dc7732 | 950 | env->active_tc.CP0_TCStatus = newval; |
f1aa6320 TS |
951 | } |
952 | ||
be24bb4f | 953 | void do_mttc0_tcstatus (target_ulong t0) |
f1aa6320 TS |
954 | { |
955 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
956 | ||
957 | // TODO: Sync with CP0_Status. | |
958 | ||
b5dc7732 TS |
959 | if (other_tc == env->current_tc) |
960 | env->active_tc.CP0_TCStatus = t0; | |
961 | else | |
962 | env->tcs[other_tc].CP0_TCStatus = t0; | |
f1aa6320 TS |
963 | } |
964 | ||
be24bb4f | 965 | void do_mtc0_tcbind (target_ulong t0) |
f1aa6320 TS |
966 | { |
967 | uint32_t mask = (1 << CP0TCBd_TBE); | |
968 | uint32_t newval; | |
969 | ||
970 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
971 | mask |= (1 << CP0TCBd_CurVPE); | |
b5dc7732 TS |
972 | newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask); |
973 | env->active_tc.CP0_TCBind = newval; | |
f1aa6320 TS |
974 | } |
975 | ||
be24bb4f | 976 | void do_mttc0_tcbind (target_ulong t0) |
f1aa6320 TS |
977 | { |
978 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
979 | uint32_t mask = (1 << CP0TCBd_TBE); | |
980 | uint32_t newval; | |
981 | ||
982 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) | |
983 | mask |= (1 << CP0TCBd_CurVPE); | |
b5dc7732 TS |
984 | if (other_tc == env->current_tc) { |
985 | newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask); | |
986 | env->active_tc.CP0_TCBind = newval; | |
987 | } else { | |
988 | newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (t0 & mask); | |
989 | env->tcs[other_tc].CP0_TCBind = newval; | |
990 | } | |
f1aa6320 TS |
991 | } |
992 | ||
be24bb4f | 993 | void do_mtc0_tcrestart (target_ulong t0) |
f1aa6320 | 994 | { |
b5dc7732 TS |
995 | env->active_tc.PC = t0; |
996 | env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); | |
f1aa6320 TS |
997 | env->CP0_LLAddr = 0ULL; |
998 | /* MIPS16 not implemented. */ | |
999 | } | |
1000 | ||
be24bb4f | 1001 | void do_mttc0_tcrestart (target_ulong t0) |
f1aa6320 TS |
1002 | { |
1003 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1004 | ||
b5dc7732 TS |
1005 | if (other_tc == env->current_tc) { |
1006 | env->active_tc.PC = t0; | |
1007 | env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); | |
1008 | env->CP0_LLAddr = 0ULL; | |
1009 | /* MIPS16 not implemented. */ | |
1010 | } else { | |
1011 | env->tcs[other_tc].PC = t0; | |
1012 | env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); | |
1013 | env->CP0_LLAddr = 0ULL; | |
1014 | /* MIPS16 not implemented. */ | |
1015 | } | |
f1aa6320 TS |
1016 | } |
1017 | ||
be24bb4f | 1018 | void do_mtc0_tchalt (target_ulong t0) |
f1aa6320 | 1019 | { |
b5dc7732 | 1020 | env->active_tc.CP0_TCHalt = t0 & 0x1; |
f1aa6320 TS |
1021 | |
1022 | // TODO: Halt TC / Restart (if allocated+active) TC. | |
1023 | } | |
1024 | ||
be24bb4f | 1025 | void do_mttc0_tchalt (target_ulong t0) |
f1aa6320 TS |
1026 | { |
1027 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1028 | ||
1029 | // TODO: Halt TC / Restart (if allocated+active) TC. | |
1030 | ||
b5dc7732 TS |
1031 | if (other_tc == env->current_tc) |
1032 | env->active_tc.CP0_TCHalt = t0; | |
1033 | else | |
1034 | env->tcs[other_tc].CP0_TCHalt = t0; | |
f1aa6320 TS |
1035 | } |
1036 | ||
be24bb4f | 1037 | void do_mtc0_tccontext (target_ulong t0) |
f1aa6320 | 1038 | { |
b5dc7732 | 1039 | env->active_tc.CP0_TCContext = t0; |
f1aa6320 TS |
1040 | } |
1041 | ||
be24bb4f | 1042 | void do_mttc0_tccontext (target_ulong t0) |
f1aa6320 TS |
1043 | { |
1044 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1045 | ||
b5dc7732 TS |
1046 | if (other_tc == env->current_tc) |
1047 | env->active_tc.CP0_TCContext = t0; | |
1048 | else | |
1049 | env->tcs[other_tc].CP0_TCContext = t0; | |
f1aa6320 TS |
1050 | } |
1051 | ||
be24bb4f | 1052 | void do_mtc0_tcschedule (target_ulong t0) |
f1aa6320 | 1053 | { |
b5dc7732 | 1054 | env->active_tc.CP0_TCSchedule = t0; |
f1aa6320 TS |
1055 | } |
1056 | ||
be24bb4f | 1057 | void do_mttc0_tcschedule (target_ulong t0) |
f1aa6320 TS |
1058 | { |
1059 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1060 | ||
b5dc7732 TS |
1061 | if (other_tc == env->current_tc) |
1062 | env->active_tc.CP0_TCSchedule = t0; | |
1063 | else | |
1064 | env->tcs[other_tc].CP0_TCSchedule = t0; | |
f1aa6320 TS |
1065 | } |
1066 | ||
be24bb4f | 1067 | void do_mtc0_tcschefback (target_ulong t0) |
f1aa6320 | 1068 | { |
b5dc7732 | 1069 | env->active_tc.CP0_TCScheFBack = t0; |
f1aa6320 TS |
1070 | } |
1071 | ||
be24bb4f | 1072 | void do_mttc0_tcschefback (target_ulong t0) |
f1aa6320 TS |
1073 | { |
1074 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1075 | ||
b5dc7732 TS |
1076 | if (other_tc == env->current_tc) |
1077 | env->active_tc.CP0_TCScheFBack = t0; | |
1078 | else | |
1079 | env->tcs[other_tc].CP0_TCScheFBack = t0; | |
f1aa6320 TS |
1080 | } |
1081 | ||
be24bb4f | 1082 | void do_mtc0_entrylo1 (target_ulong t0) |
f1aa6320 TS |
1083 | { |
1084 | /* Large physaddr (PABITS) not implemented */ | |
1085 | /* 1k pages not implemented */ | |
be24bb4f | 1086 | env->CP0_EntryLo1 = t0 & 0x3FFFFFFF; |
f1aa6320 TS |
1087 | } |
1088 | ||
be24bb4f | 1089 | void do_mtc0_context (target_ulong t0) |
f1aa6320 | 1090 | { |
be24bb4f | 1091 | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF); |
f1aa6320 TS |
1092 | } |
1093 | ||
be24bb4f | 1094 | void do_mtc0_pagemask (target_ulong t0) |
f1aa6320 TS |
1095 | { |
1096 | /* 1k pages not implemented */ | |
be24bb4f | 1097 | env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
f1aa6320 TS |
1098 | } |
1099 | ||
be24bb4f | 1100 | void do_mtc0_pagegrain (target_ulong t0) |
f1aa6320 TS |
1101 | { |
1102 | /* SmartMIPS not implemented */ | |
1103 | /* Large physaddr (PABITS) not implemented */ | |
1104 | /* 1k pages not implemented */ | |
1105 | env->CP0_PageGrain = 0; | |
1106 | } | |
1107 | ||
be24bb4f | 1108 | void do_mtc0_wired (target_ulong t0) |
f1aa6320 | 1109 | { |
be24bb4f | 1110 | env->CP0_Wired = t0 % env->tlb->nb_tlb; |
f1aa6320 TS |
1111 | } |
1112 | ||
be24bb4f | 1113 | void do_mtc0_srsconf0 (target_ulong t0) |
f1aa6320 | 1114 | { |
be24bb4f | 1115 | env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask; |
f1aa6320 TS |
1116 | } |
1117 | ||
be24bb4f | 1118 | void do_mtc0_srsconf1 (target_ulong t0) |
f1aa6320 | 1119 | { |
be24bb4f | 1120 | env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask; |
f1aa6320 TS |
1121 | } |
1122 | ||
be24bb4f | 1123 | void do_mtc0_srsconf2 (target_ulong t0) |
f1aa6320 | 1124 | { |
be24bb4f | 1125 | env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask; |
f1aa6320 TS |
1126 | } |
1127 | ||
be24bb4f | 1128 | void do_mtc0_srsconf3 (target_ulong t0) |
f1aa6320 | 1129 | { |
be24bb4f | 1130 | env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask; |
f1aa6320 TS |
1131 | } |
1132 | ||
be24bb4f | 1133 | void do_mtc0_srsconf4 (target_ulong t0) |
f1aa6320 | 1134 | { |
be24bb4f | 1135 | env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask; |
f1aa6320 TS |
1136 | } |
1137 | ||
be24bb4f | 1138 | void do_mtc0_hwrena (target_ulong t0) |
f1aa6320 | 1139 | { |
be24bb4f | 1140 | env->CP0_HWREna = t0 & 0x0000000F; |
f1aa6320 TS |
1141 | } |
1142 | ||
be24bb4f | 1143 | void do_mtc0_count (target_ulong t0) |
f1aa6320 | 1144 | { |
be24bb4f | 1145 | cpu_mips_store_count(env, t0); |
f1aa6320 TS |
1146 | } |
1147 | ||
be24bb4f | 1148 | void do_mtc0_entryhi (target_ulong t0) |
f1aa6320 TS |
1149 | { |
1150 | target_ulong old, val; | |
1151 | ||
1152 | /* 1k pages not implemented */ | |
be24bb4f | 1153 | val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
f1aa6320 TS |
1154 | #if defined(TARGET_MIPS64) |
1155 | val &= env->SEGMask; | |
1156 | #endif | |
1157 | old = env->CP0_EntryHi; | |
1158 | env->CP0_EntryHi = val; | |
1159 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { | |
b5dc7732 TS |
1160 | uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff; |
1161 | env->active_tc.CP0_TCStatus = tcst | (val & 0xff); | |
f1aa6320 TS |
1162 | } |
1163 | /* If the ASID changes, flush qemu's TLB. */ | |
1164 | if ((old & 0xFF) != (val & 0xFF)) | |
1165 | cpu_mips_tlb_flush(env, 1); | |
1166 | } | |
1167 | ||
be24bb4f | 1168 | void do_mttc0_entryhi(target_ulong t0) |
f1aa6320 TS |
1169 | { |
1170 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 | 1171 | int32_t tcstatus; |
f1aa6320 | 1172 | |
be24bb4f | 1173 | env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff); |
b5dc7732 TS |
1174 | if (other_tc == env->current_tc) { |
1175 | tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (t0 & 0xff); | |
1176 | env->active_tc.CP0_TCStatus = tcstatus; | |
1177 | } else { | |
1178 | tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (t0 & 0xff); | |
1179 | env->tcs[other_tc].CP0_TCStatus = tcstatus; | |
1180 | } | |
f1aa6320 TS |
1181 | } |
1182 | ||
be24bb4f | 1183 | void do_mtc0_compare (target_ulong t0) |
f1aa6320 | 1184 | { |
be24bb4f | 1185 | cpu_mips_store_compare(env, t0); |
f1aa6320 TS |
1186 | } |
1187 | ||
be24bb4f | 1188 | void do_mtc0_status (target_ulong t0) |
f1aa6320 TS |
1189 | { |
1190 | uint32_t val, old; | |
1191 | uint32_t mask = env->CP0_Status_rw_bitmask; | |
1192 | ||
be24bb4f | 1193 | val = t0 & mask; |
f1aa6320 TS |
1194 | old = env->CP0_Status; |
1195 | env->CP0_Status = (env->CP0_Status & ~mask) | val; | |
1196 | compute_hflags(env); | |
8fec2b8c | 1197 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) |
f1aa6320 TS |
1198 | do_mtc0_status_debug(old, val); |
1199 | cpu_mips_update_irq(env); | |
1200 | } | |
1201 | ||
be24bb4f | 1202 | void do_mttc0_status(target_ulong t0) |
f1aa6320 TS |
1203 | { |
1204 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 | 1205 | int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus; |
f1aa6320 | 1206 | |
be24bb4f TS |
1207 | env->CP0_Status = t0 & ~0xf1000018; |
1208 | tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0)); | |
1209 | tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); | |
1210 | tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); | |
b5dc7732 TS |
1211 | if (other_tc == env->current_tc) |
1212 | env->active_tc.CP0_TCStatus = tcstatus; | |
1213 | else | |
1214 | env->tcs[other_tc].CP0_TCStatus = tcstatus; | |
f1aa6320 TS |
1215 | } |
1216 | ||
be24bb4f | 1217 | void do_mtc0_intctl (target_ulong t0) |
f1aa6320 TS |
1218 | { |
1219 | /* vectored interrupts not implemented, no performance counters. */ | |
be24bb4f | 1220 | env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0); |
f1aa6320 TS |
1221 | } |
1222 | ||
be24bb4f | 1223 | void do_mtc0_srsctl (target_ulong t0) |
f1aa6320 TS |
1224 | { |
1225 | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); | |
be24bb4f | 1226 | env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask); |
f1aa6320 TS |
1227 | } |
1228 | ||
be24bb4f | 1229 | void do_mtc0_cause (target_ulong t0) |
f1aa6320 TS |
1230 | { |
1231 | uint32_t mask = 0x00C00300; | |
1232 | uint32_t old = env->CP0_Cause; | |
1233 | ||
1234 | if (env->insn_flags & ISA_MIPS32R2) | |
1235 | mask |= 1 << CP0Ca_DC; | |
1236 | ||
be24bb4f | 1237 | env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask); |
f1aa6320 TS |
1238 | |
1239 | if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { | |
1240 | if (env->CP0_Cause & (1 << CP0Ca_DC)) | |
1241 | cpu_mips_stop_count(env); | |
1242 | else | |
1243 | cpu_mips_start_count(env); | |
1244 | } | |
1245 | ||
1246 | /* Handle the software interrupt as an hardware one, as they | |
1247 | are very similar */ | |
be24bb4f | 1248 | if (t0 & CP0Ca_IP_mask) { |
f1aa6320 TS |
1249 | cpu_mips_update_irq(env); |
1250 | } | |
1251 | } | |
1252 | ||
be24bb4f | 1253 | void do_mtc0_ebase (target_ulong t0) |
f1aa6320 TS |
1254 | { |
1255 | /* vectored interrupts not implemented */ | |
1256 | /* Multi-CPU not implemented */ | |
be24bb4f | 1257 | env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000); |
f1aa6320 TS |
1258 | } |
1259 | ||
be24bb4f | 1260 | void do_mtc0_config0 (target_ulong t0) |
f1aa6320 | 1261 | { |
be24bb4f | 1262 | env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007); |
f1aa6320 TS |
1263 | } |
1264 | ||
be24bb4f | 1265 | void do_mtc0_config2 (target_ulong t0) |
f1aa6320 TS |
1266 | { |
1267 | /* tertiary/secondary caches not implemented */ | |
1268 | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); | |
1269 | } | |
1270 | ||
be24bb4f | 1271 | void do_mtc0_watchlo (target_ulong t0, uint32_t sel) |
f1aa6320 TS |
1272 | { |
1273 | /* Watch exceptions for instructions, data loads, data stores | |
1274 | not implemented. */ | |
be24bb4f | 1275 | env->CP0_WatchLo[sel] = (t0 & ~0x7); |
f1aa6320 TS |
1276 | } |
1277 | ||
be24bb4f | 1278 | void do_mtc0_watchhi (target_ulong t0, uint32_t sel) |
f1aa6320 | 1279 | { |
be24bb4f TS |
1280 | env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8); |
1281 | env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7); | |
f1aa6320 TS |
1282 | } |
1283 | ||
be24bb4f | 1284 | void do_mtc0_xcontext (target_ulong t0) |
f1aa6320 TS |
1285 | { |
1286 | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; | |
be24bb4f | 1287 | env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask); |
f1aa6320 TS |
1288 | } |
1289 | ||
be24bb4f | 1290 | void do_mtc0_framemask (target_ulong t0) |
f1aa6320 | 1291 | { |
be24bb4f | 1292 | env->CP0_Framemask = t0; /* XXX */ |
f1aa6320 TS |
1293 | } |
1294 | ||
be24bb4f | 1295 | void do_mtc0_debug (target_ulong t0) |
f1aa6320 | 1296 | { |
be24bb4f TS |
1297 | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120); |
1298 | if (t0 & (1 << CP0DB_DM)) | |
f1aa6320 TS |
1299 | env->hflags |= MIPS_HFLAG_DM; |
1300 | else | |
1301 | env->hflags &= ~MIPS_HFLAG_DM; | |
1302 | } | |
1303 | ||
be24bb4f | 1304 | void do_mttc0_debug(target_ulong t0) |
f1aa6320 TS |
1305 | { |
1306 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
b5dc7732 | 1307 | uint32_t val = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
f1aa6320 TS |
1308 | |
1309 | /* XXX: Might be wrong, check with EJTAG spec. */ | |
b5dc7732 TS |
1310 | if (other_tc == env->current_tc) |
1311 | env->active_tc.CP0_Debug_tcstatus = val; | |
1312 | else | |
1313 | env->tcs[other_tc].CP0_Debug_tcstatus = val; | |
f1aa6320 | 1314 | env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
be24bb4f | 1315 | (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
f1aa6320 TS |
1316 | } |
1317 | ||
be24bb4f | 1318 | void do_mtc0_performance0 (target_ulong t0) |
f1aa6320 | 1319 | { |
be24bb4f | 1320 | env->CP0_Performance0 = t0 & 0x000007ff; |
f1aa6320 TS |
1321 | } |
1322 | ||
be24bb4f | 1323 | void do_mtc0_taglo (target_ulong t0) |
f1aa6320 | 1324 | { |
be24bb4f | 1325 | env->CP0_TagLo = t0 & 0xFFFFFCF6; |
f1aa6320 TS |
1326 | } |
1327 | ||
be24bb4f | 1328 | void do_mtc0_datalo (target_ulong t0) |
f1aa6320 | 1329 | { |
be24bb4f | 1330 | env->CP0_DataLo = t0; /* XXX */ |
f1aa6320 TS |
1331 | } |
1332 | ||
be24bb4f | 1333 | void do_mtc0_taghi (target_ulong t0) |
f1aa6320 | 1334 | { |
be24bb4f | 1335 | env->CP0_TagHi = t0; /* XXX */ |
f1aa6320 TS |
1336 | } |
1337 | ||
be24bb4f | 1338 | void do_mtc0_datahi (target_ulong t0) |
f1aa6320 | 1339 | { |
be24bb4f | 1340 | env->CP0_DataHi = t0; /* XXX */ |
f1aa6320 TS |
1341 | } |
1342 | ||
8c0fdd85 | 1343 | void do_mtc0_status_debug(uint32_t old, uint32_t val) |
6af0bf9c | 1344 | { |
93fcfe39 | 1345 | qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x", |
f41c52f1 TS |
1346 | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
1347 | val, val & env->CP0_Cause & CP0Ca_IP_mask, | |
1348 | env->CP0_Cause); | |
623a930e | 1349 | switch (env->hflags & MIPS_HFLAG_KSU) { |
93fcfe39 AL |
1350 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
1351 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; | |
1352 | case MIPS_HFLAG_KM: qemu_log("\n"); break; | |
623a930e TS |
1353 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
1354 | } | |
8c0fdd85 TS |
1355 | } |
1356 | ||
1357 | void do_mtc0_status_irqraise_debug(void) | |
1358 | { | |
93fcfe39 | 1359 | qemu_log("Raise pending IRQs\n"); |
6af0bf9c | 1360 | } |
f1aa6320 TS |
1361 | |
1362 | /* MIPS MT functions */ | |
add69063 | 1363 | target_ulong do_mftgpr(uint32_t sel) |
f1aa6320 TS |
1364 | { |
1365 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1366 | ||
b5dc7732 TS |
1367 | if (other_tc == env->current_tc) |
1368 | return env->active_tc.gpr[sel]; | |
1369 | else | |
1370 | return env->tcs[other_tc].gpr[sel]; | |
f1aa6320 TS |
1371 | } |
1372 | ||
add69063 | 1373 | target_ulong do_mftlo(uint32_t sel) |
f1aa6320 TS |
1374 | { |
1375 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1376 | ||
b5dc7732 TS |
1377 | if (other_tc == env->current_tc) |
1378 | return env->active_tc.LO[sel]; | |
1379 | else | |
1380 | return env->tcs[other_tc].LO[sel]; | |
f1aa6320 TS |
1381 | } |
1382 | ||
add69063 | 1383 | target_ulong do_mfthi(uint32_t sel) |
f1aa6320 TS |
1384 | { |
1385 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1386 | ||
b5dc7732 TS |
1387 | if (other_tc == env->current_tc) |
1388 | return env->active_tc.HI[sel]; | |
1389 | else | |
1390 | return env->tcs[other_tc].HI[sel]; | |
f1aa6320 TS |
1391 | } |
1392 | ||
add69063 | 1393 | target_ulong do_mftacx(uint32_t sel) |
f1aa6320 TS |
1394 | { |
1395 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1396 | ||
b5dc7732 TS |
1397 | if (other_tc == env->current_tc) |
1398 | return env->active_tc.ACX[sel]; | |
1399 | else | |
1400 | return env->tcs[other_tc].ACX[sel]; | |
f1aa6320 TS |
1401 | } |
1402 | ||
add69063 | 1403 | target_ulong do_mftdsp(void) |
f1aa6320 TS |
1404 | { |
1405 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1406 | ||
b5dc7732 TS |
1407 | if (other_tc == env->current_tc) |
1408 | return env->active_tc.DSPControl; | |
1409 | else | |
1410 | return env->tcs[other_tc].DSPControl; | |
f1aa6320 | 1411 | } |
6af0bf9c | 1412 | |
be24bb4f | 1413 | void do_mttgpr(target_ulong t0, uint32_t sel) |
f1aa6320 TS |
1414 | { |
1415 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1416 | ||
b5dc7732 TS |
1417 | if (other_tc == env->current_tc) |
1418 | env->active_tc.gpr[sel] = t0; | |
1419 | else | |
1420 | env->tcs[other_tc].gpr[sel] = t0; | |
f1aa6320 TS |
1421 | } |
1422 | ||
be24bb4f | 1423 | void do_mttlo(target_ulong t0, uint32_t sel) |
f1aa6320 TS |
1424 | { |
1425 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1426 | ||
b5dc7732 TS |
1427 | if (other_tc == env->current_tc) |
1428 | env->active_tc.LO[sel] = t0; | |
1429 | else | |
1430 | env->tcs[other_tc].LO[sel] = t0; | |
f1aa6320 TS |
1431 | } |
1432 | ||
be24bb4f | 1433 | void do_mtthi(target_ulong t0, uint32_t sel) |
f1aa6320 TS |
1434 | { |
1435 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1436 | ||
b5dc7732 TS |
1437 | if (other_tc == env->current_tc) |
1438 | env->active_tc.HI[sel] = t0; | |
1439 | else | |
1440 | env->tcs[other_tc].HI[sel] = t0; | |
f1aa6320 TS |
1441 | } |
1442 | ||
be24bb4f | 1443 | void do_mttacx(target_ulong t0, uint32_t sel) |
f1aa6320 TS |
1444 | { |
1445 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1446 | ||
b5dc7732 TS |
1447 | if (other_tc == env->current_tc) |
1448 | env->active_tc.ACX[sel] = t0; | |
1449 | else | |
1450 | env->tcs[other_tc].ACX[sel] = t0; | |
f1aa6320 TS |
1451 | } |
1452 | ||
be24bb4f | 1453 | void do_mttdsp(target_ulong t0) |
f1aa6320 TS |
1454 | { |
1455 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
1456 | ||
b5dc7732 TS |
1457 | if (other_tc == env->current_tc) |
1458 | env->active_tc.DSPControl = t0; | |
1459 | else | |
1460 | env->tcs[other_tc].DSPControl = t0; | |
f1aa6320 TS |
1461 | } |
1462 | ||
1463 | /* MIPS MT functions */ | |
be24bb4f | 1464 | target_ulong do_dmt(target_ulong t0) |
f1aa6320 TS |
1465 | { |
1466 | // TODO | |
be24bb4f TS |
1467 | t0 = 0; |
1468 | // rt = t0 | |
1469 | ||
1470 | return t0; | |
f1aa6320 TS |
1471 | } |
1472 | ||
be24bb4f | 1473 | target_ulong do_emt(target_ulong t0) |
f1aa6320 TS |
1474 | { |
1475 | // TODO | |
be24bb4f TS |
1476 | t0 = 0; |
1477 | // rt = t0 | |
1478 | ||
1479 | return t0; | |
f1aa6320 TS |
1480 | } |
1481 | ||
be24bb4f | 1482 | target_ulong do_dvpe(target_ulong t0) |
f1aa6320 TS |
1483 | { |
1484 | // TODO | |
be24bb4f TS |
1485 | t0 = 0; |
1486 | // rt = t0 | |
1487 | ||
1488 | return t0; | |
f1aa6320 TS |
1489 | } |
1490 | ||
be24bb4f | 1491 | target_ulong do_evpe(target_ulong t0) |
f1aa6320 TS |
1492 | { |
1493 | // TODO | |
be24bb4f TS |
1494 | t0 = 0; |
1495 | // rt = t0 | |
1496 | ||
1497 | return t0; | |
f1aa6320 | 1498 | } |
f9480ffc | 1499 | #endif /* !CONFIG_USER_ONLY */ |
f1aa6320 | 1500 | |
6c5c1e20 | 1501 | void do_fork(target_ulong t0, target_ulong t1) |
f1aa6320 | 1502 | { |
be24bb4f TS |
1503 | // t0 = rt, t1 = rs |
1504 | t0 = 0; | |
f1aa6320 TS |
1505 | // TODO: store to TC register |
1506 | } | |
1507 | ||
be24bb4f | 1508 | target_ulong do_yield(target_ulong t0) |
f1aa6320 | 1509 | { |
be24bb4f | 1510 | if (t0 < 0) { |
f1aa6320 | 1511 | /* No scheduling policy implemented. */ |
be24bb4f | 1512 | if (t0 != -2) { |
f1aa6320 | 1513 | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
b5dc7732 | 1514 | env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { |
f1aa6320 TS |
1515 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
1516 | env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; | |
1517 | do_raise_exception(EXCP_THREAD); | |
1518 | } | |
1519 | } | |
be24bb4f | 1520 | } else if (t0 == 0) { |
6958549d | 1521 | if (0 /* TODO: TC underflow */) { |
f1aa6320 TS |
1522 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
1523 | do_raise_exception(EXCP_THREAD); | |
1524 | } else { | |
1525 | // TODO: Deallocate TC | |
1526 | } | |
be24bb4f | 1527 | } else if (t0 > 0) { |
f1aa6320 TS |
1528 | /* Yield qualifier inputs not implemented. */ |
1529 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); | |
1530 | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; | |
1531 | do_raise_exception(EXCP_THREAD); | |
1532 | } | |
be24bb4f | 1533 | return env->CP0_YQMask; |
f1aa6320 TS |
1534 | } |
1535 | ||
f1aa6320 | 1536 | #ifndef CONFIG_USER_ONLY |
6af0bf9c | 1537 | /* TLB management */ |
814b9a47 TS |
1538 | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
1539 | { | |
1540 | /* Flush qemu's TLB and discard all shadowed entries. */ | |
1541 | tlb_flush (env, flush_global); | |
ead9360e | 1542 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
814b9a47 TS |
1543 | } |
1544 | ||
29929e34 | 1545 | static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
814b9a47 TS |
1546 | { |
1547 | /* Discard entries from env->tlb[first] onwards. */ | |
ead9360e TS |
1548 | while (env->tlb->tlb_in_use > first) { |
1549 | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); | |
814b9a47 TS |
1550 | } |
1551 | } | |
1552 | ||
29929e34 | 1553 | static void r4k_fill_tlb (int idx) |
6af0bf9c | 1554 | { |
29929e34 | 1555 | r4k_tlb_t *tlb; |
6af0bf9c FB |
1556 | |
1557 | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ | |
ead9360e | 1558 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 1559 | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
d26bc211 | 1560 | #if defined(TARGET_MIPS64) |
e034e2c3 | 1561 | tlb->VPN &= env->SEGMask; |
100ce988 | 1562 | #endif |
98c1b82b | 1563 | tlb->ASID = env->CP0_EntryHi & 0xFF; |
3b1c8be4 | 1564 | tlb->PageMask = env->CP0_PageMask; |
6af0bf9c | 1565 | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
98c1b82b PB |
1566 | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
1567 | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; | |
1568 | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; | |
6af0bf9c | 1569 | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
98c1b82b PB |
1570 | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
1571 | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; | |
1572 | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; | |
6af0bf9c FB |
1573 | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
1574 | } | |
1575 | ||
29929e34 | 1576 | void r4k_do_tlbwi (void) |
6af0bf9c | 1577 | { |
bbc0d79c AJ |
1578 | int idx; |
1579 | ||
1580 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; | |
1581 | ||
814b9a47 TS |
1582 | /* Discard cached TLB entries. We could avoid doing this if the |
1583 | tlbwi is just upgrading access permissions on the current entry; | |
1584 | that might be a further win. */ | |
ead9360e | 1585 | r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
814b9a47 | 1586 | |
bbc0d79c AJ |
1587 | r4k_invalidate_tlb(env, idx, 0); |
1588 | r4k_fill_tlb(idx); | |
6af0bf9c FB |
1589 | } |
1590 | ||
29929e34 | 1591 | void r4k_do_tlbwr (void) |
6af0bf9c FB |
1592 | { |
1593 | int r = cpu_mips_get_random(env); | |
1594 | ||
29929e34 TS |
1595 | r4k_invalidate_tlb(env, r, 1); |
1596 | r4k_fill_tlb(r); | |
6af0bf9c FB |
1597 | } |
1598 | ||
29929e34 | 1599 | void r4k_do_tlbp (void) |
6af0bf9c | 1600 | { |
29929e34 | 1601 | r4k_tlb_t *tlb; |
f2e9ebef | 1602 | target_ulong mask; |
6af0bf9c | 1603 | target_ulong tag; |
f2e9ebef | 1604 | target_ulong VPN; |
6af0bf9c FB |
1605 | uint8_t ASID; |
1606 | int i; | |
1607 | ||
3d9fb9fe | 1608 | ASID = env->CP0_EntryHi & 0xFF; |
ead9360e TS |
1609 | for (i = 0; i < env->tlb->nb_tlb; i++) { |
1610 | tlb = &env->tlb->mmu.r4k.tlb[i]; | |
f2e9ebef TS |
1611 | /* 1k pages are not supported. */ |
1612 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
1613 | tag = env->CP0_EntryHi & ~mask; | |
1614 | VPN = tlb->VPN & ~mask; | |
6af0bf9c | 1615 | /* Check ASID, virtual page number & size */ |
f2e9ebef | 1616 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
6af0bf9c | 1617 | /* TLB match */ |
9c2149c8 | 1618 | env->CP0_Index = i; |
6af0bf9c FB |
1619 | break; |
1620 | } | |
1621 | } | |
ead9360e | 1622 | if (i == env->tlb->nb_tlb) { |
814b9a47 | 1623 | /* No match. Discard any shadow entries, if any of them match. */ |
ead9360e | 1624 | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { |
6958549d AJ |
1625 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
1626 | /* 1k pages are not supported. */ | |
1627 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); | |
1628 | tag = env->CP0_EntryHi & ~mask; | |
1629 | VPN = tlb->VPN & ~mask; | |
1630 | /* Check ASID, virtual page number & size */ | |
1631 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { | |
29929e34 | 1632 | r4k_mips_tlb_flush_extra (env, i); |
6958549d AJ |
1633 | break; |
1634 | } | |
1635 | } | |
814b9a47 | 1636 | |
9c2149c8 | 1637 | env->CP0_Index |= 0x80000000; |
6af0bf9c FB |
1638 | } |
1639 | } | |
1640 | ||
29929e34 | 1641 | void r4k_do_tlbr (void) |
6af0bf9c | 1642 | { |
29929e34 | 1643 | r4k_tlb_t *tlb; |
09c56b84 | 1644 | uint8_t ASID; |
bbc0d79c | 1645 | int idx; |
6af0bf9c | 1646 | |
09c56b84 | 1647 | ASID = env->CP0_EntryHi & 0xFF; |
bbc0d79c AJ |
1648 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
1649 | tlb = &env->tlb->mmu.r4k.tlb[idx]; | |
4ad40f36 FB |
1650 | |
1651 | /* If this will change the current ASID, flush qemu's TLB. */ | |
814b9a47 TS |
1652 | if (ASID != tlb->ASID) |
1653 | cpu_mips_tlb_flush (env, 1); | |
1654 | ||
ead9360e | 1655 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
4ad40f36 | 1656 | |
6af0bf9c | 1657 | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
3b1c8be4 | 1658 | env->CP0_PageMask = tlb->PageMask; |
7495fd0f TS |
1659 | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
1660 | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); | |
1661 | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | | |
1662 | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); | |
6af0bf9c | 1663 | } |
6af0bf9c | 1664 | |
a7812ae4 PB |
1665 | void do_tlbwi(void) |
1666 | { | |
1667 | env->tlb->do_tlbwi(); | |
1668 | } | |
1669 | ||
1670 | void do_tlbwr(void) | |
1671 | { | |
1672 | env->tlb->do_tlbwr(); | |
1673 | } | |
1674 | ||
1675 | void do_tlbp(void) | |
1676 | { | |
1677 | env->tlb->do_tlbp(); | |
1678 | } | |
1679 | ||
1680 | void do_tlbr(void) | |
1681 | { | |
1682 | env->tlb->do_tlbr(); | |
1683 | } | |
1684 | ||
2b0233ab | 1685 | /* Specials */ |
2796188e | 1686 | target_ulong do_di (void) |
2b0233ab | 1687 | { |
2796188e TS |
1688 | target_ulong t0 = env->CP0_Status; |
1689 | ||
be24bb4f | 1690 | env->CP0_Status = t0 & ~(1 << CP0St_IE); |
2b0233ab | 1691 | cpu_mips_update_irq(env); |
be24bb4f TS |
1692 | |
1693 | return t0; | |
2b0233ab TS |
1694 | } |
1695 | ||
2796188e | 1696 | target_ulong do_ei (void) |
2b0233ab | 1697 | { |
2796188e TS |
1698 | target_ulong t0 = env->CP0_Status; |
1699 | ||
be24bb4f | 1700 | env->CP0_Status = t0 | (1 << CP0St_IE); |
2b0233ab | 1701 | cpu_mips_update_irq(env); |
be24bb4f TS |
1702 | |
1703 | return t0; | |
2b0233ab TS |
1704 | } |
1705 | ||
cd5158ea | 1706 | static void debug_pre_eret (void) |
6af0bf9c | 1707 | { |
8fec2b8c | 1708 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
93fcfe39 AL |
1709 | qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1710 | env->active_tc.PC, env->CP0_EPC); | |
1711 | if (env->CP0_Status & (1 << CP0St_ERL)) | |
1712 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); | |
1713 | if (env->hflags & MIPS_HFLAG_DM) | |
1714 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); | |
1715 | qemu_log("\n"); | |
1716 | } | |
f41c52f1 TS |
1717 | } |
1718 | ||
cd5158ea | 1719 | static void debug_post_eret (void) |
f41c52f1 | 1720 | { |
8fec2b8c | 1721 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
93fcfe39 AL |
1722 | qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
1723 | env->active_tc.PC, env->CP0_EPC); | |
1724 | if (env->CP0_Status & (1 << CP0St_ERL)) | |
1725 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); | |
1726 | if (env->hflags & MIPS_HFLAG_DM) | |
1727 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); | |
1728 | switch (env->hflags & MIPS_HFLAG_KSU) { | |
1729 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; | |
1730 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; | |
1731 | case MIPS_HFLAG_KM: qemu_log("\n"); break; | |
1732 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; | |
1733 | } | |
623a930e | 1734 | } |
6af0bf9c FB |
1735 | } |
1736 | ||
6c5c1e20 | 1737 | void do_eret (void) |
2b0233ab | 1738 | { |
93fcfe39 | 1739 | debug_pre_eret(); |
2b0233ab | 1740 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
b5dc7732 | 1741 | env->active_tc.PC = env->CP0_ErrorEPC; |
2b0233ab TS |
1742 | env->CP0_Status &= ~(1 << CP0St_ERL); |
1743 | } else { | |
b5dc7732 | 1744 | env->active_tc.PC = env->CP0_EPC; |
2b0233ab TS |
1745 | env->CP0_Status &= ~(1 << CP0St_EXL); |
1746 | } | |
1747 | compute_hflags(env); | |
93fcfe39 | 1748 | debug_post_eret(); |
2b0233ab TS |
1749 | env->CP0_LLAddr = 1; |
1750 | } | |
1751 | ||
6c5c1e20 | 1752 | void do_deret (void) |
2b0233ab | 1753 | { |
93fcfe39 | 1754 | debug_pre_eret(); |
b5dc7732 | 1755 | env->active_tc.PC = env->CP0_DEPC; |
2b0233ab TS |
1756 | env->hflags &= MIPS_HFLAG_DM; |
1757 | compute_hflags(env); | |
93fcfe39 | 1758 | debug_post_eret(); |
2b0233ab TS |
1759 | env->CP0_LLAddr = 1; |
1760 | } | |
0eaef5aa | 1761 | #endif /* !CONFIG_USER_ONLY */ |
2b0233ab | 1762 | |
2796188e | 1763 | target_ulong do_rdhwr_cpunum(void) |
2b0233ab TS |
1764 | { |
1765 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
1766 | (env->CP0_HWREna & (1 << 0))) | |
2796188e | 1767 | return env->CP0_EBase & 0x3ff; |
2b0233ab TS |
1768 | else |
1769 | do_raise_exception(EXCP_RI); | |
be24bb4f | 1770 | |
2796188e | 1771 | return 0; |
2b0233ab TS |
1772 | } |
1773 | ||
2796188e | 1774 | target_ulong do_rdhwr_synci_step(void) |
2b0233ab TS |
1775 | { |
1776 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
1777 | (env->CP0_HWREna & (1 << 1))) | |
2796188e | 1778 | return env->SYNCI_Step; |
2b0233ab TS |
1779 | else |
1780 | do_raise_exception(EXCP_RI); | |
be24bb4f | 1781 | |
2796188e | 1782 | return 0; |
2b0233ab TS |
1783 | } |
1784 | ||
2796188e | 1785 | target_ulong do_rdhwr_cc(void) |
2b0233ab TS |
1786 | { |
1787 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
1788 | (env->CP0_HWREna & (1 << 2))) | |
2796188e | 1789 | return env->CP0_Count; |
2b0233ab TS |
1790 | else |
1791 | do_raise_exception(EXCP_RI); | |
be24bb4f | 1792 | |
2796188e | 1793 | return 0; |
2b0233ab TS |
1794 | } |
1795 | ||
2796188e | 1796 | target_ulong do_rdhwr_ccres(void) |
2b0233ab TS |
1797 | { |
1798 | if ((env->hflags & MIPS_HFLAG_CP0) || | |
1799 | (env->CP0_HWREna & (1 << 3))) | |
2796188e | 1800 | return env->CCRes; |
2b0233ab TS |
1801 | else |
1802 | do_raise_exception(EXCP_RI); | |
be24bb4f | 1803 | |
2796188e | 1804 | return 0; |
2b0233ab TS |
1805 | } |
1806 | ||
6af0bf9c FB |
1807 | void do_pmon (int function) |
1808 | { | |
1809 | function /= 2; | |
1810 | switch (function) { | |
1811 | case 2: /* TODO: char inbyte(int waitflag); */ | |
b5dc7732 TS |
1812 | if (env->active_tc.gpr[4] == 0) |
1813 | env->active_tc.gpr[2] = -1; | |
6af0bf9c FB |
1814 | /* Fall through */ |
1815 | case 11: /* TODO: char inbyte (void); */ | |
b5dc7732 | 1816 | env->active_tc.gpr[2] = -1; |
6af0bf9c FB |
1817 | break; |
1818 | case 3: | |
1819 | case 12: | |
b5dc7732 | 1820 | printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); |
6af0bf9c FB |
1821 | break; |
1822 | case 17: | |
1823 | break; | |
1824 | case 158: | |
1825 | { | |
b5dc7732 | 1826 | unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4]; |
6af0bf9c FB |
1827 | printf("%s", fmt); |
1828 | } | |
1829 | break; | |
1830 | } | |
1831 | } | |
e37e863f | 1832 | |
08ba7963 TS |
1833 | void do_wait (void) |
1834 | { | |
1835 | env->halted = 1; | |
1836 | do_raise_exception(EXCP_HLT); | |
1837 | } | |
1838 | ||
5fafdf24 | 1839 | #if !defined(CONFIG_USER_ONLY) |
e37e863f | 1840 | |
4ad40f36 FB |
1841 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
1842 | ||
e37e863f | 1843 | #define MMUSUFFIX _mmu |
4ad40f36 | 1844 | #define ALIGNED_ONLY |
e37e863f FB |
1845 | |
1846 | #define SHIFT 0 | |
1847 | #include "softmmu_template.h" | |
1848 | ||
1849 | #define SHIFT 1 | |
1850 | #include "softmmu_template.h" | |
1851 | ||
1852 | #define SHIFT 2 | |
1853 | #include "softmmu_template.h" | |
1854 | ||
1855 | #define SHIFT 3 | |
1856 | #include "softmmu_template.h" | |
1857 | ||
4ad40f36 FB |
1858 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
1859 | { | |
1860 | env->CP0_BadVAddr = addr; | |
1861 | do_restore_state (retaddr); | |
1862 | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); | |
1863 | } | |
1864 | ||
6ebbf390 | 1865 | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
e37e863f FB |
1866 | { |
1867 | TranslationBlock *tb; | |
1868 | CPUState *saved_env; | |
1869 | unsigned long pc; | |
1870 | int ret; | |
1871 | ||
1872 | /* XXX: hack to restore env in all cases, even if not called from | |
1873 | generated code */ | |
1874 | saved_env = env; | |
1875 | env = cpu_single_env; | |
6ebbf390 | 1876 | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); |
e37e863f FB |
1877 | if (ret) { |
1878 | if (retaddr) { | |
1879 | /* now we have a real cpu fault */ | |
1880 | pc = (unsigned long)retaddr; | |
1881 | tb = tb_find_pc(pc); | |
1882 | if (tb) { | |
1883 | /* the PC is inside the translated code. It means that we have | |
1884 | a virtual CPU fault */ | |
1885 | cpu_restore_state(tb, env, pc, NULL); | |
1886 | } | |
1887 | } | |
1888 | do_raise_exception_err(env->exception_index, env->error_code); | |
1889 | } | |
1890 | env = saved_env; | |
1891 | } | |
1892 | ||
647de6ca | 1893 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
e18231a3 | 1894 | int unused, int size) |
647de6ca TS |
1895 | { |
1896 | if (is_exec) | |
1897 | do_raise_exception(EXCP_IBE); | |
1898 | else | |
1899 | do_raise_exception(EXCP_DBE); | |
1900 | } | |
f1aa6320 | 1901 | #endif /* !CONFIG_USER_ONLY */ |
fd4a04eb TS |
1902 | |
1903 | /* Complex FPU operations which may need stack space. */ | |
1904 | ||
f090c9d4 PB |
1905 | #define FLOAT_ONE32 make_float32(0x3f8 << 20) |
1906 | #define FLOAT_ONE64 make_float64(0x3ffULL << 52) | |
1907 | #define FLOAT_TWO32 make_float32(1 << 30) | |
1908 | #define FLOAT_TWO64 make_float64(1ULL << 62) | |
54454097 TS |
1909 | #define FLOAT_QNAN32 0x7fbfffff |
1910 | #define FLOAT_QNAN64 0x7ff7ffffffffffffULL | |
1911 | #define FLOAT_SNAN32 0x7fffffff | |
1912 | #define FLOAT_SNAN64 0x7fffffffffffffffULL | |
8dfdb87c | 1913 | |
fd4a04eb TS |
1914 | /* convert MIPS rounding mode in FCR31 to IEEE library */ |
1915 | unsigned int ieee_rm[] = { | |
1916 | float_round_nearest_even, | |
1917 | float_round_to_zero, | |
1918 | float_round_up, | |
1919 | float_round_down | |
1920 | }; | |
1921 | ||
1922 | #define RESTORE_ROUNDING_MODE \ | |
f01be154 | 1923 | set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status) |
fd4a04eb | 1924 | |
6c5c1e20 | 1925 | target_ulong do_cfc1 (uint32_t reg) |
fd4a04eb | 1926 | { |
6c5c1e20 TS |
1927 | target_ulong t0; |
1928 | ||
ead9360e TS |
1929 | switch (reg) { |
1930 | case 0: | |
f01be154 | 1931 | t0 = (int32_t)env->active_fpu.fcr0; |
ead9360e TS |
1932 | break; |
1933 | case 25: | |
f01be154 | 1934 | t0 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); |
ead9360e TS |
1935 | break; |
1936 | case 26: | |
f01be154 | 1937 | t0 = env->active_fpu.fcr31 & 0x0003f07c; |
ead9360e TS |
1938 | break; |
1939 | case 28: | |
f01be154 | 1940 | t0 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); |
ead9360e TS |
1941 | break; |
1942 | default: | |
f01be154 | 1943 | t0 = (int32_t)env->active_fpu.fcr31; |
ead9360e TS |
1944 | break; |
1945 | } | |
be24bb4f TS |
1946 | |
1947 | return t0; | |
ead9360e TS |
1948 | } |
1949 | ||
be24bb4f | 1950 | void do_ctc1 (target_ulong t0, uint32_t reg) |
ead9360e TS |
1951 | { |
1952 | switch(reg) { | |
fd4a04eb | 1953 | case 25: |
be24bb4f | 1954 | if (t0 & 0xffffff00) |
fd4a04eb | 1955 | return; |
f01be154 | 1956 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) | |
be24bb4f | 1957 | ((t0 & 0x1) << 23); |
fd4a04eb TS |
1958 | break; |
1959 | case 26: | |
be24bb4f | 1960 | if (t0 & 0x007c0000) |
fd4a04eb | 1961 | return; |
f01be154 | 1962 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c); |
fd4a04eb TS |
1963 | break; |
1964 | case 28: | |
be24bb4f | 1965 | if (t0 & 0x007c0000) |
fd4a04eb | 1966 | return; |
f01be154 | 1967 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (t0 & 0x00000f83) | |
be24bb4f | 1968 | ((t0 & 0x4) << 22); |
fd4a04eb TS |
1969 | break; |
1970 | case 31: | |
be24bb4f | 1971 | if (t0 & 0x007c0000) |
fd4a04eb | 1972 | return; |
f01be154 | 1973 | env->active_fpu.fcr31 = t0; |
fd4a04eb TS |
1974 | break; |
1975 | default: | |
1976 | return; | |
1977 | } | |
1978 | /* set rounding mode */ | |
1979 | RESTORE_ROUNDING_MODE; | |
f01be154 TS |
1980 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
1981 | if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) | |
fd4a04eb TS |
1982 | do_raise_exception(EXCP_FPE); |
1983 | } | |
1984 | ||
c904ef0e | 1985 | static inline char ieee_ex_to_mips(char xcpt) |
fd4a04eb TS |
1986 | { |
1987 | return (xcpt & float_flag_inexact) >> 5 | | |
1988 | (xcpt & float_flag_underflow) >> 3 | | |
1989 | (xcpt & float_flag_overflow) >> 1 | | |
1990 | (xcpt & float_flag_divbyzero) << 1 | | |
1991 | (xcpt & float_flag_invalid) << 4; | |
1992 | } | |
1993 | ||
c904ef0e | 1994 | static inline char mips_ex_to_ieee(char xcpt) |
fd4a04eb TS |
1995 | { |
1996 | return (xcpt & FP_INEXACT) << 5 | | |
1997 | (xcpt & FP_UNDERFLOW) << 3 | | |
1998 | (xcpt & FP_OVERFLOW) << 1 | | |
1999 | (xcpt & FP_DIV0) >> 1 | | |
2000 | (xcpt & FP_INVALID) >> 4; | |
2001 | } | |
2002 | ||
c904ef0e | 2003 | static inline void update_fcr31(void) |
fd4a04eb | 2004 | { |
f01be154 | 2005 | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); |
fd4a04eb | 2006 | |
f01be154 TS |
2007 | SET_FP_CAUSE(env->active_fpu.fcr31, tmp); |
2008 | if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) | |
fd4a04eb TS |
2009 | do_raise_exception(EXCP_FPE); |
2010 | else | |
f01be154 | 2011 | UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); |
fd4a04eb TS |
2012 | } |
2013 | ||
a16336e4 TS |
2014 | /* Float support. |
2015 | Single precition routines have a "s" suffix, double precision a | |
2016 | "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", | |
2017 | paired single lower "pl", paired single upper "pu". */ | |
2018 | ||
a16336e4 | 2019 | /* unary operations, modifying fp status */ |
b6d96bed TS |
2020 | uint64_t do_float_sqrt_d(uint64_t fdt0) |
2021 | { | |
f01be154 | 2022 | return float64_sqrt(fdt0, &env->active_fpu.fp_status); |
b6d96bed TS |
2023 | } |
2024 | ||
2025 | uint32_t do_float_sqrt_s(uint32_t fst0) | |
2026 | { | |
f01be154 | 2027 | return float32_sqrt(fst0, &env->active_fpu.fp_status); |
b6d96bed | 2028 | } |
a16336e4 | 2029 | |
b6d96bed | 2030 | uint64_t do_float_cvtd_s(uint32_t fst0) |
fd4a04eb | 2031 | { |
b6d96bed TS |
2032 | uint64_t fdt2; |
2033 | ||
f01be154 TS |
2034 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2035 | fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2036 | update_fcr31(); |
b6d96bed | 2037 | return fdt2; |
fd4a04eb | 2038 | } |
b6d96bed TS |
2039 | |
2040 | uint64_t do_float_cvtd_w(uint32_t wt0) | |
fd4a04eb | 2041 | { |
b6d96bed TS |
2042 | uint64_t fdt2; |
2043 | ||
f01be154 TS |
2044 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2045 | fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2046 | update_fcr31(); |
b6d96bed | 2047 | return fdt2; |
fd4a04eb | 2048 | } |
b6d96bed TS |
2049 | |
2050 | uint64_t do_float_cvtd_l(uint64_t dt0) | |
fd4a04eb | 2051 | { |
b6d96bed TS |
2052 | uint64_t fdt2; |
2053 | ||
f01be154 TS |
2054 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2055 | fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2056 | update_fcr31(); |
b6d96bed | 2057 | return fdt2; |
fd4a04eb | 2058 | } |
b6d96bed TS |
2059 | |
2060 | uint64_t do_float_cvtl_d(uint64_t fdt0) | |
fd4a04eb | 2061 | { |
b6d96bed TS |
2062 | uint64_t dt2; |
2063 | ||
f01be154 TS |
2064 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2065 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2066 | update_fcr31(); |
f01be154 | 2067 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2068 | dt2 = FLOAT_SNAN64; |
2069 | return dt2; | |
fd4a04eb | 2070 | } |
b6d96bed TS |
2071 | |
2072 | uint64_t do_float_cvtl_s(uint32_t fst0) | |
fd4a04eb | 2073 | { |
b6d96bed TS |
2074 | uint64_t dt2; |
2075 | ||
f01be154 TS |
2076 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2077 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2078 | update_fcr31(); |
f01be154 | 2079 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2080 | dt2 = FLOAT_SNAN64; |
2081 | return dt2; | |
fd4a04eb TS |
2082 | } |
2083 | ||
b6d96bed | 2084 | uint64_t do_float_cvtps_pw(uint64_t dt0) |
fd4a04eb | 2085 | { |
b6d96bed TS |
2086 | uint32_t fst2; |
2087 | uint32_t fsth2; | |
2088 | ||
f01be154 TS |
2089 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2090 | fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); | |
2091 | fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); | |
fd4a04eb | 2092 | update_fcr31(); |
b6d96bed | 2093 | return ((uint64_t)fsth2 << 32) | fst2; |
fd4a04eb | 2094 | } |
b6d96bed TS |
2095 | |
2096 | uint64_t do_float_cvtpw_ps(uint64_t fdt0) | |
fd4a04eb | 2097 | { |
b6d96bed TS |
2098 | uint32_t wt2; |
2099 | uint32_t wth2; | |
2100 | ||
f01be154 TS |
2101 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2102 | wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); | |
2103 | wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); | |
fd4a04eb | 2104 | update_fcr31(); |
f01be154 | 2105 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { |
b6d96bed TS |
2106 | wt2 = FLOAT_SNAN32; |
2107 | wth2 = FLOAT_SNAN32; | |
2108 | } | |
2109 | return ((uint64_t)wth2 << 32) | wt2; | |
fd4a04eb | 2110 | } |
b6d96bed TS |
2111 | |
2112 | uint32_t do_float_cvts_d(uint64_t fdt0) | |
fd4a04eb | 2113 | { |
b6d96bed TS |
2114 | uint32_t fst2; |
2115 | ||
f01be154 TS |
2116 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2117 | fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2118 | update_fcr31(); |
b6d96bed | 2119 | return fst2; |
fd4a04eb | 2120 | } |
b6d96bed TS |
2121 | |
2122 | uint32_t do_float_cvts_w(uint32_t wt0) | |
fd4a04eb | 2123 | { |
b6d96bed TS |
2124 | uint32_t fst2; |
2125 | ||
f01be154 TS |
2126 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2127 | fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2128 | update_fcr31(); |
b6d96bed | 2129 | return fst2; |
fd4a04eb | 2130 | } |
b6d96bed TS |
2131 | |
2132 | uint32_t do_float_cvts_l(uint64_t dt0) | |
fd4a04eb | 2133 | { |
b6d96bed TS |
2134 | uint32_t fst2; |
2135 | ||
f01be154 TS |
2136 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2137 | fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2138 | update_fcr31(); |
b6d96bed | 2139 | return fst2; |
fd4a04eb | 2140 | } |
b6d96bed TS |
2141 | |
2142 | uint32_t do_float_cvts_pl(uint32_t wt0) | |
fd4a04eb | 2143 | { |
b6d96bed TS |
2144 | uint32_t wt2; |
2145 | ||
f01be154 | 2146 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
b6d96bed | 2147 | wt2 = wt0; |
fd4a04eb | 2148 | update_fcr31(); |
b6d96bed | 2149 | return wt2; |
fd4a04eb | 2150 | } |
b6d96bed TS |
2151 | |
2152 | uint32_t do_float_cvts_pu(uint32_t wth0) | |
fd4a04eb | 2153 | { |
b6d96bed TS |
2154 | uint32_t wt2; |
2155 | ||
f01be154 | 2156 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
b6d96bed | 2157 | wt2 = wth0; |
fd4a04eb | 2158 | update_fcr31(); |
b6d96bed | 2159 | return wt2; |
fd4a04eb | 2160 | } |
b6d96bed TS |
2161 | |
2162 | uint32_t do_float_cvtw_s(uint32_t fst0) | |
fd4a04eb | 2163 | { |
b6d96bed TS |
2164 | uint32_t wt2; |
2165 | ||
f01be154 TS |
2166 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2167 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb | 2168 | update_fcr31(); |
f01be154 | 2169 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2170 | wt2 = FLOAT_SNAN32; |
2171 | return wt2; | |
fd4a04eb | 2172 | } |
b6d96bed TS |
2173 | |
2174 | uint32_t do_float_cvtw_d(uint64_t fdt0) | |
fd4a04eb | 2175 | { |
b6d96bed TS |
2176 | uint32_t wt2; |
2177 | ||
f01be154 TS |
2178 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2179 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb | 2180 | update_fcr31(); |
f01be154 | 2181 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2182 | wt2 = FLOAT_SNAN32; |
2183 | return wt2; | |
fd4a04eb TS |
2184 | } |
2185 | ||
b6d96bed | 2186 | uint64_t do_float_roundl_d(uint64_t fdt0) |
fd4a04eb | 2187 | { |
b6d96bed TS |
2188 | uint64_t dt2; |
2189 | ||
f01be154 TS |
2190 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2191 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2192 | RESTORE_ROUNDING_MODE; |
2193 | update_fcr31(); | |
f01be154 | 2194 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2195 | dt2 = FLOAT_SNAN64; |
2196 | return dt2; | |
fd4a04eb | 2197 | } |
b6d96bed TS |
2198 | |
2199 | uint64_t do_float_roundl_s(uint32_t fst0) | |
fd4a04eb | 2200 | { |
b6d96bed TS |
2201 | uint64_t dt2; |
2202 | ||
f01be154 TS |
2203 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2204 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2205 | RESTORE_ROUNDING_MODE; |
2206 | update_fcr31(); | |
f01be154 | 2207 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2208 | dt2 = FLOAT_SNAN64; |
2209 | return dt2; | |
fd4a04eb | 2210 | } |
b6d96bed TS |
2211 | |
2212 | uint32_t do_float_roundw_d(uint64_t fdt0) | |
fd4a04eb | 2213 | { |
b6d96bed TS |
2214 | uint32_t wt2; |
2215 | ||
f01be154 TS |
2216 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2217 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2218 | RESTORE_ROUNDING_MODE; |
2219 | update_fcr31(); | |
f01be154 | 2220 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2221 | wt2 = FLOAT_SNAN32; |
2222 | return wt2; | |
fd4a04eb | 2223 | } |
b6d96bed TS |
2224 | |
2225 | uint32_t do_float_roundw_s(uint32_t fst0) | |
fd4a04eb | 2226 | { |
b6d96bed TS |
2227 | uint32_t wt2; |
2228 | ||
f01be154 TS |
2229 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
2230 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2231 | RESTORE_ROUNDING_MODE; |
2232 | update_fcr31(); | |
f01be154 | 2233 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2234 | wt2 = FLOAT_SNAN32; |
2235 | return wt2; | |
fd4a04eb TS |
2236 | } |
2237 | ||
b6d96bed | 2238 | uint64_t do_float_truncl_d(uint64_t fdt0) |
fd4a04eb | 2239 | { |
b6d96bed TS |
2240 | uint64_t dt2; |
2241 | ||
f01be154 | 2242 | dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); |
fd4a04eb | 2243 | update_fcr31(); |
f01be154 | 2244 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2245 | dt2 = FLOAT_SNAN64; |
2246 | return dt2; | |
fd4a04eb | 2247 | } |
b6d96bed TS |
2248 | |
2249 | uint64_t do_float_truncl_s(uint32_t fst0) | |
fd4a04eb | 2250 | { |
b6d96bed TS |
2251 | uint64_t dt2; |
2252 | ||
f01be154 | 2253 | dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); |
fd4a04eb | 2254 | update_fcr31(); |
f01be154 | 2255 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2256 | dt2 = FLOAT_SNAN64; |
2257 | return dt2; | |
fd4a04eb | 2258 | } |
b6d96bed TS |
2259 | |
2260 | uint32_t do_float_truncw_d(uint64_t fdt0) | |
fd4a04eb | 2261 | { |
b6d96bed TS |
2262 | uint32_t wt2; |
2263 | ||
f01be154 | 2264 | wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); |
fd4a04eb | 2265 | update_fcr31(); |
f01be154 | 2266 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2267 | wt2 = FLOAT_SNAN32; |
2268 | return wt2; | |
fd4a04eb | 2269 | } |
b6d96bed TS |
2270 | |
2271 | uint32_t do_float_truncw_s(uint32_t fst0) | |
fd4a04eb | 2272 | { |
b6d96bed TS |
2273 | uint32_t wt2; |
2274 | ||
f01be154 | 2275 | wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); |
fd4a04eb | 2276 | update_fcr31(); |
f01be154 | 2277 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2278 | wt2 = FLOAT_SNAN32; |
2279 | return wt2; | |
fd4a04eb TS |
2280 | } |
2281 | ||
b6d96bed | 2282 | uint64_t do_float_ceill_d(uint64_t fdt0) |
fd4a04eb | 2283 | { |
b6d96bed TS |
2284 | uint64_t dt2; |
2285 | ||
f01be154 TS |
2286 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2287 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2288 | RESTORE_ROUNDING_MODE; |
2289 | update_fcr31(); | |
f01be154 | 2290 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2291 | dt2 = FLOAT_SNAN64; |
2292 | return dt2; | |
fd4a04eb | 2293 | } |
b6d96bed TS |
2294 | |
2295 | uint64_t do_float_ceill_s(uint32_t fst0) | |
fd4a04eb | 2296 | { |
b6d96bed TS |
2297 | uint64_t dt2; |
2298 | ||
f01be154 TS |
2299 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2300 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2301 | RESTORE_ROUNDING_MODE; |
2302 | update_fcr31(); | |
f01be154 | 2303 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2304 | dt2 = FLOAT_SNAN64; |
2305 | return dt2; | |
fd4a04eb | 2306 | } |
b6d96bed TS |
2307 | |
2308 | uint32_t do_float_ceilw_d(uint64_t fdt0) | |
fd4a04eb | 2309 | { |
b6d96bed TS |
2310 | uint32_t wt2; |
2311 | ||
f01be154 TS |
2312 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2313 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2314 | RESTORE_ROUNDING_MODE; |
2315 | update_fcr31(); | |
f01be154 | 2316 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2317 | wt2 = FLOAT_SNAN32; |
2318 | return wt2; | |
fd4a04eb | 2319 | } |
b6d96bed TS |
2320 | |
2321 | uint32_t do_float_ceilw_s(uint32_t fst0) | |
fd4a04eb | 2322 | { |
b6d96bed TS |
2323 | uint32_t wt2; |
2324 | ||
f01be154 TS |
2325 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
2326 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2327 | RESTORE_ROUNDING_MODE; |
2328 | update_fcr31(); | |
f01be154 | 2329 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2330 | wt2 = FLOAT_SNAN32; |
2331 | return wt2; | |
fd4a04eb TS |
2332 | } |
2333 | ||
b6d96bed | 2334 | uint64_t do_float_floorl_d(uint64_t fdt0) |
fd4a04eb | 2335 | { |
b6d96bed TS |
2336 | uint64_t dt2; |
2337 | ||
f01be154 TS |
2338 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2339 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2340 | RESTORE_ROUNDING_MODE; |
2341 | update_fcr31(); | |
f01be154 | 2342 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2343 | dt2 = FLOAT_SNAN64; |
2344 | return dt2; | |
fd4a04eb | 2345 | } |
b6d96bed TS |
2346 | |
2347 | uint64_t do_float_floorl_s(uint32_t fst0) | |
fd4a04eb | 2348 | { |
b6d96bed TS |
2349 | uint64_t dt2; |
2350 | ||
f01be154 TS |
2351 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2352 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2353 | RESTORE_ROUNDING_MODE; |
2354 | update_fcr31(); | |
f01be154 | 2355 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2356 | dt2 = FLOAT_SNAN64; |
2357 | return dt2; | |
fd4a04eb | 2358 | } |
b6d96bed TS |
2359 | |
2360 | uint32_t do_float_floorw_d(uint64_t fdt0) | |
fd4a04eb | 2361 | { |
b6d96bed TS |
2362 | uint32_t wt2; |
2363 | ||
f01be154 TS |
2364 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2365 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2366 | RESTORE_ROUNDING_MODE; |
2367 | update_fcr31(); | |
f01be154 | 2368 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2369 | wt2 = FLOAT_SNAN32; |
2370 | return wt2; | |
fd4a04eb | 2371 | } |
b6d96bed TS |
2372 | |
2373 | uint32_t do_float_floorw_s(uint32_t fst0) | |
fd4a04eb | 2374 | { |
b6d96bed TS |
2375 | uint32_t wt2; |
2376 | ||
f01be154 TS |
2377 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
2378 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); | |
fd4a04eb TS |
2379 | RESTORE_ROUNDING_MODE; |
2380 | update_fcr31(); | |
f01be154 | 2381 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
b6d96bed TS |
2382 | wt2 = FLOAT_SNAN32; |
2383 | return wt2; | |
fd4a04eb TS |
2384 | } |
2385 | ||
a16336e4 | 2386 | /* unary operations, not modifying fp status */ |
b6d96bed TS |
2387 | #define FLOAT_UNOP(name) \ |
2388 | uint64_t do_float_ ## name ## _d(uint64_t fdt0) \ | |
2389 | { \ | |
2390 | return float64_ ## name(fdt0); \ | |
2391 | } \ | |
2392 | uint32_t do_float_ ## name ## _s(uint32_t fst0) \ | |
2393 | { \ | |
2394 | return float32_ ## name(fst0); \ | |
2395 | } \ | |
2396 | uint64_t do_float_ ## name ## _ps(uint64_t fdt0) \ | |
2397 | { \ | |
2398 | uint32_t wt0; \ | |
2399 | uint32_t wth0; \ | |
2400 | \ | |
2401 | wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ | |
2402 | wth0 = float32_ ## name(fdt0 >> 32); \ | |
2403 | return ((uint64_t)wth0 << 32) | wt0; \ | |
a16336e4 TS |
2404 | } |
2405 | FLOAT_UNOP(abs) | |
2406 | FLOAT_UNOP(chs) | |
2407 | #undef FLOAT_UNOP | |
2408 | ||
8dfdb87c | 2409 | /* MIPS specific unary operations */ |
b6d96bed | 2410 | uint64_t do_float_recip_d(uint64_t fdt0) |
8dfdb87c | 2411 | { |
b6d96bed TS |
2412 | uint64_t fdt2; |
2413 | ||
f01be154 TS |
2414 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2415 | fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); | |
8dfdb87c | 2416 | update_fcr31(); |
b6d96bed | 2417 | return fdt2; |
8dfdb87c | 2418 | } |
b6d96bed TS |
2419 | |
2420 | uint32_t do_float_recip_s(uint32_t fst0) | |
8dfdb87c | 2421 | { |
b6d96bed TS |
2422 | uint32_t fst2; |
2423 | ||
f01be154 TS |
2424 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2425 | fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); | |
8dfdb87c | 2426 | update_fcr31(); |
b6d96bed | 2427 | return fst2; |
57fa1fb3 | 2428 | } |
57fa1fb3 | 2429 | |
b6d96bed | 2430 | uint64_t do_float_rsqrt_d(uint64_t fdt0) |
8dfdb87c | 2431 | { |
b6d96bed TS |
2432 | uint64_t fdt2; |
2433 | ||
f01be154 TS |
2434 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2435 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); | |
2436 | fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); | |
8dfdb87c | 2437 | update_fcr31(); |
b6d96bed | 2438 | return fdt2; |
8dfdb87c | 2439 | } |
b6d96bed TS |
2440 | |
2441 | uint32_t do_float_rsqrt_s(uint32_t fst0) | |
8dfdb87c | 2442 | { |
b6d96bed TS |
2443 | uint32_t fst2; |
2444 | ||
f01be154 TS |
2445 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2446 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); | |
2447 | fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); | |
8dfdb87c | 2448 | update_fcr31(); |
b6d96bed | 2449 | return fst2; |
8dfdb87c TS |
2450 | } |
2451 | ||
b6d96bed | 2452 | uint64_t do_float_recip1_d(uint64_t fdt0) |
8dfdb87c | 2453 | { |
b6d96bed TS |
2454 | uint64_t fdt2; |
2455 | ||
f01be154 TS |
2456 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2457 | fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); | |
8dfdb87c | 2458 | update_fcr31(); |
b6d96bed | 2459 | return fdt2; |
8dfdb87c | 2460 | } |
b6d96bed TS |
2461 | |
2462 | uint32_t do_float_recip1_s(uint32_t fst0) | |
8dfdb87c | 2463 | { |
b6d96bed TS |
2464 | uint32_t fst2; |
2465 | ||
f01be154 TS |
2466 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2467 | fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); | |
8dfdb87c | 2468 | update_fcr31(); |
b6d96bed | 2469 | return fst2; |
8dfdb87c | 2470 | } |
b6d96bed TS |
2471 | |
2472 | uint64_t do_float_recip1_ps(uint64_t fdt0) | |
8dfdb87c | 2473 | { |
b6d96bed TS |
2474 | uint32_t fst2; |
2475 | uint32_t fsth2; | |
2476 | ||
f01be154 TS |
2477 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2478 | fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); | |
2479 | fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); | |
8dfdb87c | 2480 | update_fcr31(); |
b6d96bed | 2481 | return ((uint64_t)fsth2 << 32) | fst2; |
8dfdb87c TS |
2482 | } |
2483 | ||
b6d96bed | 2484 | uint64_t do_float_rsqrt1_d(uint64_t fdt0) |
8dfdb87c | 2485 | { |
b6d96bed TS |
2486 | uint64_t fdt2; |
2487 | ||
f01be154 TS |
2488 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2489 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); | |
2490 | fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); | |
8dfdb87c | 2491 | update_fcr31(); |
b6d96bed | 2492 | return fdt2; |
8dfdb87c | 2493 | } |
b6d96bed TS |
2494 | |
2495 | uint32_t do_float_rsqrt1_s(uint32_t fst0) | |
8dfdb87c | 2496 | { |
b6d96bed TS |
2497 | uint32_t fst2; |
2498 | ||
f01be154 TS |
2499 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2500 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); | |
2501 | fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); | |
8dfdb87c | 2502 | update_fcr31(); |
b6d96bed | 2503 | return fst2; |
8dfdb87c | 2504 | } |
b6d96bed TS |
2505 | |
2506 | uint64_t do_float_rsqrt1_ps(uint64_t fdt0) | |
8dfdb87c | 2507 | { |
b6d96bed TS |
2508 | uint32_t fst2; |
2509 | uint32_t fsth2; | |
2510 | ||
f01be154 TS |
2511 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2512 | fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); | |
2513 | fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); | |
2514 | fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); | |
2515 | fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); | |
8dfdb87c | 2516 | update_fcr31(); |
b6d96bed | 2517 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 | 2518 | } |
57fa1fb3 | 2519 | |
b6d96bed TS |
2520 | #define FLOAT_OP(name, p) void do_float_##name##_##p(void) |
2521 | ||
fd4a04eb | 2522 | /* binary operations */ |
b6d96bed TS |
2523 | #define FLOAT_BINOP(name) \ |
2524 | uint64_t do_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \ | |
2525 | { \ | |
2526 | uint64_t dt2; \ | |
2527 | \ | |
f01be154 TS |
2528 | set_float_exception_flags(0, &env->active_fpu.fp_status); \ |
2529 | dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ | |
ead9360e | 2530 | update_fcr31(); \ |
f01be154 | 2531 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ |
b6d96bed TS |
2532 | dt2 = FLOAT_QNAN64; \ |
2533 | return dt2; \ | |
2534 | } \ | |
2535 | \ | |
2536 | uint32_t do_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \ | |
2537 | { \ | |
2538 | uint32_t wt2; \ | |
2539 | \ | |
f01be154 TS |
2540 | set_float_exception_flags(0, &env->active_fpu.fp_status); \ |
2541 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ | |
ead9360e | 2542 | update_fcr31(); \ |
f01be154 | 2543 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ |
b6d96bed TS |
2544 | wt2 = FLOAT_QNAN32; \ |
2545 | return wt2; \ | |
2546 | } \ | |
2547 | \ | |
2548 | uint64_t do_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ | |
2549 | { \ | |
2550 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2551 | uint32_t fsth0 = fdt0 >> 32; \ | |
2552 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2553 | uint32_t fsth1 = fdt1 >> 32; \ | |
2554 | uint32_t wt2; \ | |
2555 | uint32_t wth2; \ | |
2556 | \ | |
f01be154 TS |
2557 | set_float_exception_flags(0, &env->active_fpu.fp_status); \ |
2558 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ | |
2559 | wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ | |
b6d96bed | 2560 | update_fcr31(); \ |
f01be154 | 2561 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \ |
b6d96bed TS |
2562 | wt2 = FLOAT_QNAN32; \ |
2563 | wth2 = FLOAT_QNAN32; \ | |
2564 | } \ | |
2565 | return ((uint64_t)wth2 << 32) | wt2; \ | |
fd4a04eb | 2566 | } |
b6d96bed | 2567 | |
fd4a04eb TS |
2568 | FLOAT_BINOP(add) |
2569 | FLOAT_BINOP(sub) | |
2570 | FLOAT_BINOP(mul) | |
2571 | FLOAT_BINOP(div) | |
2572 | #undef FLOAT_BINOP | |
2573 | ||
a16336e4 | 2574 | /* ternary operations */ |
b6d96bed TS |
2575 | #define FLOAT_TERNOP(name1, name2) \ |
2576 | uint64_t do_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ | |
2577 | uint64_t fdt2) \ | |
2578 | { \ | |
f01be154 TS |
2579 | fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
2580 | return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2581 | } \ |
2582 | \ | |
2583 | uint32_t do_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ | |
2584 | uint32_t fst2) \ | |
2585 | { \ | |
f01be154 TS |
2586 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2587 | return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2588 | } \ |
2589 | \ | |
2590 | uint64_t do_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ | |
2591 | uint64_t fdt2) \ | |
2592 | { \ | |
2593 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2594 | uint32_t fsth0 = fdt0 >> 32; \ | |
2595 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2596 | uint32_t fsth1 = fdt1 >> 32; \ | |
2597 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ | |
2598 | uint32_t fsth2 = fdt2 >> 32; \ | |
2599 | \ | |
f01be154 TS |
2600 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2601 | fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ | |
2602 | fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ | |
2603 | fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ | |
b6d96bed | 2604 | return ((uint64_t)fsth2 << 32) | fst2; \ |
a16336e4 | 2605 | } |
b6d96bed | 2606 | |
a16336e4 TS |
2607 | FLOAT_TERNOP(mul, add) |
2608 | FLOAT_TERNOP(mul, sub) | |
2609 | #undef FLOAT_TERNOP | |
2610 | ||
2611 | /* negated ternary operations */ | |
b6d96bed TS |
2612 | #define FLOAT_NTERNOP(name1, name2) \ |
2613 | uint64_t do_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ | |
2614 | uint64_t fdt2) \ | |
2615 | { \ | |
f01be154 TS |
2616 | fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
2617 | fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2618 | return float64_chs(fdt2); \ |
2619 | } \ | |
2620 | \ | |
2621 | uint32_t do_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ | |
2622 | uint32_t fst2) \ | |
2623 | { \ | |
f01be154 TS |
2624 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2625 | fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2626 | return float32_chs(fst2); \ |
2627 | } \ | |
2628 | \ | |
2629 | uint64_t do_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\ | |
2630 | uint64_t fdt2) \ | |
2631 | { \ | |
2632 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ | |
2633 | uint32_t fsth0 = fdt0 >> 32; \ | |
2634 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ | |
2635 | uint32_t fsth1 = fdt1 >> 32; \ | |
2636 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ | |
2637 | uint32_t fsth2 = fdt2 >> 32; \ | |
2638 | \ | |
f01be154 TS |
2639 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
2640 | fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ | |
2641 | fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ | |
2642 | fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ | |
b6d96bed TS |
2643 | fst2 = float32_chs(fst2); \ |
2644 | fsth2 = float32_chs(fsth2); \ | |
2645 | return ((uint64_t)fsth2 << 32) | fst2; \ | |
a16336e4 | 2646 | } |
b6d96bed | 2647 | |
a16336e4 TS |
2648 | FLOAT_NTERNOP(mul, add) |
2649 | FLOAT_NTERNOP(mul, sub) | |
2650 | #undef FLOAT_NTERNOP | |
2651 | ||
8dfdb87c | 2652 | /* MIPS specific binary operations */ |
b6d96bed | 2653 | uint64_t do_float_recip2_d(uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2654 | { |
f01be154 TS |
2655 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2656 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); | |
2657 | fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); | |
8dfdb87c | 2658 | update_fcr31(); |
b6d96bed | 2659 | return fdt2; |
8dfdb87c | 2660 | } |
b6d96bed TS |
2661 | |
2662 | uint32_t do_float_recip2_s(uint32_t fst0, uint32_t fst2) | |
8dfdb87c | 2663 | { |
f01be154 TS |
2664 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2665 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); | |
2666 | fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); | |
8dfdb87c | 2667 | update_fcr31(); |
b6d96bed | 2668 | return fst2; |
8dfdb87c | 2669 | } |
b6d96bed TS |
2670 | |
2671 | uint64_t do_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) | |
8dfdb87c | 2672 | { |
b6d96bed TS |
2673 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2674 | uint32_t fsth0 = fdt0 >> 32; | |
2675 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; | |
2676 | uint32_t fsth2 = fdt2 >> 32; | |
2677 | ||
f01be154 TS |
2678 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2679 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); | |
2680 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); | |
2681 | fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); | |
2682 | fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); | |
8dfdb87c | 2683 | update_fcr31(); |
b6d96bed | 2684 | return ((uint64_t)fsth2 << 32) | fst2; |
8dfdb87c TS |
2685 | } |
2686 | ||
b6d96bed | 2687 | uint64_t do_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2) |
8dfdb87c | 2688 | { |
f01be154 TS |
2689 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2690 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); | |
2691 | fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); | |
2692 | fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); | |
8dfdb87c | 2693 | update_fcr31(); |
b6d96bed | 2694 | return fdt2; |
8dfdb87c | 2695 | } |
b6d96bed TS |
2696 | |
2697 | uint32_t do_float_rsqrt2_s(uint32_t fst0, uint32_t fst2) | |
8dfdb87c | 2698 | { |
f01be154 TS |
2699 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2700 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); | |
2701 | fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); | |
2702 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); | |
8dfdb87c | 2703 | update_fcr31(); |
b6d96bed | 2704 | return fst2; |
8dfdb87c | 2705 | } |
b6d96bed TS |
2706 | |
2707 | uint64_t do_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) | |
8dfdb87c | 2708 | { |
b6d96bed TS |
2709 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2710 | uint32_t fsth0 = fdt0 >> 32; | |
2711 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; | |
2712 | uint32_t fsth2 = fdt2 >> 32; | |
2713 | ||
f01be154 TS |
2714 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2715 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); | |
2716 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); | |
2717 | fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); | |
2718 | fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); | |
2719 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); | |
2720 | fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); | |
8dfdb87c | 2721 | update_fcr31(); |
b6d96bed | 2722 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 | 2723 | } |
57fa1fb3 | 2724 | |
b6d96bed | 2725 | uint64_t do_float_addr_ps(uint64_t fdt0, uint64_t fdt1) |
fd4a04eb | 2726 | { |
b6d96bed TS |
2727 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2728 | uint32_t fsth0 = fdt0 >> 32; | |
2729 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; | |
2730 | uint32_t fsth1 = fdt1 >> 32; | |
2731 | uint32_t fst2; | |
2732 | uint32_t fsth2; | |
2733 | ||
f01be154 TS |
2734 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2735 | fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); | |
2736 | fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); | |
fd4a04eb | 2737 | update_fcr31(); |
b6d96bed | 2738 | return ((uint64_t)fsth2 << 32) | fst2; |
fd4a04eb TS |
2739 | } |
2740 | ||
b6d96bed | 2741 | uint64_t do_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) |
57fa1fb3 | 2742 | { |
b6d96bed TS |
2743 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
2744 | uint32_t fsth0 = fdt0 >> 32; | |
2745 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; | |
2746 | uint32_t fsth1 = fdt1 >> 32; | |
2747 | uint32_t fst2; | |
2748 | uint32_t fsth2; | |
2749 | ||
f01be154 TS |
2750 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
2751 | fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); | |
2752 | fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); | |
57fa1fb3 | 2753 | update_fcr31(); |
b6d96bed | 2754 | return ((uint64_t)fsth2 << 32) | fst2; |
57fa1fb3 TS |
2755 | } |
2756 | ||
8dfdb87c | 2757 | /* compare operations */ |
b6d96bed TS |
2758 | #define FOP_COND_D(op, cond) \ |
2759 | void do_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ | |
2760 | { \ | |
2761 | int c = cond; \ | |
2762 | update_fcr31(); \ | |
2763 | if (c) \ | |
f01be154 | 2764 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2765 | else \ |
f01be154 | 2766 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed TS |
2767 | } \ |
2768 | void do_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ | |
2769 | { \ | |
2770 | int c; \ | |
2771 | fdt0 = float64_abs(fdt0); \ | |
2772 | fdt1 = float64_abs(fdt1); \ | |
2773 | c = cond; \ | |
2774 | update_fcr31(); \ | |
2775 | if (c) \ | |
f01be154 | 2776 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2777 | else \ |
f01be154 | 2778 | CLEAR_FP_COND(cc, env->active_fpu); \ |
fd4a04eb TS |
2779 | } |
2780 | ||
cd5158ea | 2781 | static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
fd4a04eb TS |
2782 | { |
2783 | if (float64_is_signaling_nan(a) || | |
2784 | float64_is_signaling_nan(b) || | |
2785 | (sig && (float64_is_nan(a) || float64_is_nan(b)))) { | |
2786 | float_raise(float_flag_invalid, status); | |
2787 | return 1; | |
2788 | } else if (float64_is_nan(a) || float64_is_nan(b)) { | |
2789 | return 1; | |
2790 | } else { | |
2791 | return 0; | |
2792 | } | |
2793 | } | |
2794 | ||
2795 | /* NOTE: the comma operator will make "cond" to eval to false, | |
2796 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2797 | FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
2798 | FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)) | |
2799 | FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2800 | FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2801 | FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2802 | FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2803 | FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2804 | FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) | |
fd4a04eb TS |
2805 | /* NOTE: the comma operator will make "cond" to eval to false, |
2806 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2807 | FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
2808 | FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)) | |
2809 | FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2810 | FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2811 | FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2812 | FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2813 | FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) | |
2814 | FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) | |
b6d96bed TS |
2815 | |
2816 | #define FOP_COND_S(op, cond) \ | |
2817 | void do_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ | |
2818 | { \ | |
2819 | int c = cond; \ | |
2820 | update_fcr31(); \ | |
2821 | if (c) \ | |
f01be154 | 2822 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2823 | else \ |
f01be154 | 2824 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed TS |
2825 | } \ |
2826 | void do_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ | |
2827 | { \ | |
2828 | int c; \ | |
2829 | fst0 = float32_abs(fst0); \ | |
2830 | fst1 = float32_abs(fst1); \ | |
2831 | c = cond; \ | |
2832 | update_fcr31(); \ | |
2833 | if (c) \ | |
f01be154 | 2834 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2835 | else \ |
f01be154 | 2836 | CLEAR_FP_COND(cc, env->active_fpu); \ |
fd4a04eb TS |
2837 | } |
2838 | ||
cd5158ea | 2839 | static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM) |
fd4a04eb | 2840 | { |
fd4a04eb TS |
2841 | if (float32_is_signaling_nan(a) || |
2842 | float32_is_signaling_nan(b) || | |
2843 | (sig && (float32_is_nan(a) || float32_is_nan(b)))) { | |
2844 | float_raise(float_flag_invalid, status); | |
2845 | return 1; | |
2846 | } else if (float32_is_nan(a) || float32_is_nan(b)) { | |
2847 | return 1; | |
2848 | } else { | |
2849 | return 0; | |
2850 | } | |
2851 | } | |
2852 | ||
2853 | /* NOTE: the comma operator will make "cond" to eval to false, | |
2854 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2855 | FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0)) |
2856 | FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)) | |
2857 | FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
2858 | FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
2859 | FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
2860 | FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
2861 | FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) | |
2862 | FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) | |
fd4a04eb TS |
2863 | /* NOTE: the comma operator will make "cond" to eval to false, |
2864 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2865 | FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0)) |
2866 | FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)) | |
2867 | FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
2868 | FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) | |
2869 | FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
2870 | FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) | |
2871 | FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) | |
2872 | FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) | |
b6d96bed TS |
2873 | |
2874 | #define FOP_COND_PS(op, condl, condh) \ | |
2875 | void do_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ | |
2876 | { \ | |
2877 | uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ | |
2878 | uint32_t fsth0 = float32_abs(fdt0 >> 32); \ | |
2879 | uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ | |
2880 | uint32_t fsth1 = float32_abs(fdt1 >> 32); \ | |
2881 | int cl = condl; \ | |
2882 | int ch = condh; \ | |
2883 | \ | |
2884 | update_fcr31(); \ | |
2885 | if (cl) \ | |
f01be154 | 2886 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2887 | else \ |
f01be154 | 2888 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2889 | if (ch) \ |
f01be154 | 2890 | SET_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 2891 | else \ |
f01be154 | 2892 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed TS |
2893 | } \ |
2894 | void do_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ | |
2895 | { \ | |
2896 | uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ | |
2897 | uint32_t fsth0 = float32_abs(fdt0 >> 32); \ | |
2898 | uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ | |
2899 | uint32_t fsth1 = float32_abs(fdt1 >> 32); \ | |
2900 | int cl = condl; \ | |
2901 | int ch = condh; \ | |
2902 | \ | |
2903 | update_fcr31(); \ | |
2904 | if (cl) \ | |
f01be154 | 2905 | SET_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2906 | else \ |
f01be154 | 2907 | CLEAR_FP_COND(cc, env->active_fpu); \ |
b6d96bed | 2908 | if (ch) \ |
f01be154 | 2909 | SET_FP_COND(cc + 1, env->active_fpu); \ |
b6d96bed | 2910 | else \ |
f01be154 | 2911 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
fd4a04eb TS |
2912 | } |
2913 | ||
2914 | /* NOTE: the comma operator will make "cond" to eval to false, | |
2915 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2916 | FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0), |
2917 | (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0)) | |
2918 | FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), | |
2919 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)) | |
2920 | FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
2921 | !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2922 | FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
2923 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2924 | FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
2925 | !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2926 | FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
2927 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2928 | FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), | |
2929 | !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2930 | FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), | |
2931 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) | |
fd4a04eb TS |
2932 | /* NOTE: the comma operator will make "cond" to eval to false, |
2933 | * but float*_is_unordered() is still called. */ | |
f01be154 TS |
2934 | FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0), |
2935 | (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0)) | |
2936 | FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), | |
2937 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)) | |
2938 | FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
2939 | !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2940 | FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), | |
2941 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2942 | FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
2943 | !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2944 | FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), | |
2945 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2946 | FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), | |
2947 | !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) | |
2948 | FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), | |
2949 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |