[mirror_qemu.git] / target-mips / op_helper.c

/*
 *  MIPS emulation helpers for qemu.
 * 
 *  Copyright (c) 2004-2005 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdlib.h>
#include "exec.h"

#define GETPC() (__builtin_return_address(0))

/*****************************************************************************/
/* Exceptions processing helpers */
void cpu_loop_exit(void)
{
    longjmp(env->jmp_env, 1);
}

void do_raise_exception_err (uint32_t exception, int error_code)
{
#if 1
    if (logfile && exception < 0x100)
        fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
#endif
    env->exception_index = exception;
    env->error_code = error_code;
    T0 = 0;
    cpu_loop_exit();
}

void do_raise_exception (uint32_t exception)
{
    do_raise_exception_err(exception, 0);
}

void do_restore_state (void *pc_ptr)
{
  TranslationBlock *tb;
  unsigned long pc = (unsigned long) pc_ptr;

  tb = tb_find_pc (pc);
  cpu_restore_state (tb, env, pc, NULL);
}

void do_raise_exception_direct_err (uint32_t exception, int error_code)
{
    do_restore_state (GETPC ());
    do_raise_exception_err (exception, error_code);
}

void do_raise_exception_direct (uint32_t exception)
{
    do_raise_exception_direct_err (exception, 0);
}

#define MEMSUFFIX _raw
#include "op_helper_mem.c"
#undef MEMSUFFIX
#if !defined(CONFIG_USER_ONLY)
#define MEMSUFFIX _user
#include "op_helper_mem.c"
#undef MEMSUFFIX
#define MEMSUFFIX _kernel
#include "op_helper_mem.c"
#undef MEMSUFFIX
#endif

#ifdef TARGET_MIPS64
#if TARGET_LONG_BITS > HOST_LONG_BITS
/* Those might call libgcc functions.  */
void do_dsll (void)
{
    T0 = T0 << T1;
}

void do_dsll32 (void)
{
    T0 = T0 << (T1 + 32);
}

void do_dsra (void)
{
    T0 = (int64_t)T0 >> T1;
}

void do_dsra32 (void)
{
    T0 = (int64_t)T0 >> (T1 + 32);
}

void do_dsrl (void)
{
    T0 = T0 >> T1;
}

void do_dsrl32 (void)
{
    T0 = T0 >> (T1 + 32);
}

void do_drotr (void)
{
    target_ulong tmp;

    if (T1) {
       tmp = T0 << (0x40 - T1);
       T0 = (T0 >> T1) | tmp;
    }
}

void do_drotr32 (void)
{
    target_ulong tmp;

    if (T1) {
       tmp = T0 << (0x40 - (32 + T1));
       T0 = (T0 >> (32 + T1)) | tmp;
    }
}

void do_dsllv (void)
{
    T0 = T1 << (T0 & 0x3F);
}

void do_dsrav (void)
{
    T0 = (int64_t)T1 >> (T0 & 0x3F);
}

void do_dsrlv (void)
{
    T0 = T1 >> (T0 & 0x3F);
}

void do_drotrv (void)
{
    target_ulong tmp;

    T0 &= 0x3F;
    if (T0) {
       tmp = T1 << (0x40 - T0);
       T0 = (T1 >> T0) | tmp;
    } else
       T0 = T1;
}
#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
#endif /* TARGET_MIPS64 */

/* 64 bits arithmetic for 32 bits hosts */
#if TARGET_LONG_BITS > HOST_LONG_BITS
static inline uint64_t get_HILO (void)
{
    return (env->HI << 32) | (uint32_t)env->LO;
}

static inline void set_HILO (uint64_t HILO)
{
    env->LO = (int32_t)HILO;
    env->HI = (int32_t)(HILO >> 32);
}

void do_mult (void)
{
    set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
}

void do_multu (void)
{
    set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
}

void do_madd (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() + tmp);
}

void do_maddu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() + tmp);
}

void do_msub (void)
{
    int64_t tmp;

    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
    set_HILO((int64_t)get_HILO() - tmp);
}

void do_msubu (void)
{
    uint64_t tmp;

    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
    set_HILO(get_HILO() - tmp);
}
#endif

#if HOST_LONG_BITS < 64
void do_div (void)
{
    /* 64bit datatypes because we may see overflow/underflow. */
    if (T1 != 0) {
        env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
        env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
    }
}
#endif

#ifdef TARGET_MIPS64
void do_ddiv (void)
{
    if (T1 != 0) {
        lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
        env->LO = res.quot;
        env->HI = res.rem;
    }
}

void do_ddivu (void)
{
    if (T1 != 0) {
        /* XXX: lldivu? */
        lldiv_t res = lldiv(T0, T1);
        env->LO = (uint64_t)res.quot;
        env->HI = (uint64_t)res.rem;
    }
}
#endif

#if defined(CONFIG_USER_ONLY) 
void do_mfc0_random (void)
{
    cpu_abort(env, "mfc0 random\n");
}

void do_mfc0_count (void)
{
    cpu_abort(env, "mfc0 count\n");
}

void cpu_mips_store_count(CPUState *env, uint32_t value)
{
    cpu_abort(env, "mtc0 count\n");
}

void cpu_mips_store_compare(CPUState *env, uint32_t value)
{
    cpu_abort(env, "mtc0 compare\n");
}

void cpu_mips_update_irq(CPUState *env)
{
    cpu_abort(env, "mtc0 status / mtc0 cause\n");
}

void do_mtc0_status_debug(uint32_t old, uint32_t val)
{
    cpu_abort(env, "mtc0 status debug\n");
}

void do_mtc0_status_irqraise_debug (void)
{
    cpu_abort(env, "mtc0 status irqraise debug\n");
}

void cpu_mips_tlb_flush (CPUState *env, int flush_global)
{
    cpu_abort(env, "mips_tlb_flush\n");
}

#else

/* CP0 helpers */
void do_mfc0_random (void)
{
    T0 = (int32_t)cpu_mips_get_random(env);
}

void do_mfc0_count (void)
{
    T0 = (int32_t)cpu_mips_get_count(env);
}

void do_mtc0_status_debug(uint32_t old, uint32_t val)
{
    fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
            old, old & env->CP0_Cause & CP0Ca_IP_mask,
            val, val & env->CP0_Cause & CP0Ca_IP_mask,
            env->CP0_Cause);
    (env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
                                  : fputs("\n", logfile);
}

void do_mtc0_status_irqraise_debug(void)
{
    fprintf(logfile, "Raise pending IRQs\n");
}

void fpu_handle_exception(void)
{
#ifdef CONFIG_SOFTFLOAT
    int flags = get_float_exception_flags(&env->fp_status);
    unsigned int cpuflags = 0, enable, cause = 0;

    enable = GET_FP_ENABLE(env->fcr31);

    /* determine current flags */   
    if (flags & float_flag_invalid) {
        cpuflags |= FP_INVALID;
        cause |= FP_INVALID & enable;
    }
    if (flags & float_flag_divbyzero) {
        cpuflags |= FP_DIV0;    
        cause |= FP_DIV0 & enable;
    }
    if (flags & float_flag_overflow) {
        cpuflags |= FP_OVERFLOW;    
        cause |= FP_OVERFLOW & enable;
    }
    if (flags & float_flag_underflow) {
        cpuflags |= FP_UNDERFLOW;   
        cause |= FP_UNDERFLOW & enable;
    }
    if (flags & float_flag_inexact) {
        cpuflags |= FP_INEXACT; 
        cause |= FP_INEXACT & enable;
    }
    SET_FP_FLAGS(env->fcr31, cpuflags);
    SET_FP_CAUSE(env->fcr31, cause);
#else
    SET_FP_FLAGS(env->fcr31, 0);
    SET_FP_CAUSE(env->fcr31, 0);
#endif
}

/* TLB management */
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
{
    /* Flush qemu's TLB and discard all shadowed entries.  */
    tlb_flush (env, flush_global);
    env->tlb_in_use = env->nb_tlb;
}

static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
{
    /* Discard entries from env->tlb[first] onwards.  */
    while (env->tlb_in_use > first) {
        r4k_invalidate_tlb(env, --env->tlb_in_use, 0);
    }
}

static void r4k_fill_tlb (int idx)
{
    r4k_tlb_t *tlb;

    /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
    tlb = &env->mmu.r4k.tlb[idx];
    tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
#ifdef TARGET_MIPS64
    tlb->VPN &= 0xC00000FFFFFFFFFFULL;
#endif
    tlb->ASID = env->CP0_EntryHi & 0xFF;
    tlb->PageMask = env->CP0_PageMask;
    tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
    tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
    tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
    tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
    tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
    tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
    tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
    tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
    tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
}

void r4k_do_tlbwi (void)
{
    /* Discard cached TLB entries.  We could avoid doing this if the
       tlbwi is just upgrading access permissions on the current entry;
       that might be a further win.  */
    r4k_mips_tlb_flush_extra (env, env->nb_tlb);

    r4k_invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
    r4k_fill_tlb(env->CP0_Index % env->nb_tlb);
}

void r4k_do_tlbwr (void)
{
    int r = cpu_mips_get_random(env);

    r4k_invalidate_tlb(env, r, 1);
    r4k_fill_tlb(r);
}

void r4k_do_tlbp (void)
{
    r4k_tlb_t *tlb;
    target_ulong mask;
    target_ulong tag;
    target_ulong VPN;
    uint8_t ASID;
    int i;

    ASID = env->CP0_EntryHi & 0xFF;
    for (i = 0; i < env->nb_tlb; i++) {
        tlb = &env->mmu.r4k.tlb[i];
        /* 1k pages are not supported. */
        mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
        tag = env->CP0_EntryHi & ~mask;
        VPN = tlb->VPN & ~mask;
        /* Check ASID, virtual page number & size */
        if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
            /* TLB match */
            env->CP0_Index = i;
            break;
        }
    }
    if (i == env->nb_tlb) {
        /* No match.  Discard any shadow entries, if any of them match.  */
        for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
	    tlb = &env->mmu.r4k.tlb[i];
	    /* 1k pages are not supported. */
	    mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
	    tag = env->CP0_EntryHi & ~mask;
	    VPN = tlb->VPN & ~mask;
	    /* Check ASID, virtual page number & size */
	    if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
                r4k_mips_tlb_flush_extra (env, i);
	        break;
	    }
	}

        env->CP0_Index |= 0x80000000;
    }
}

void r4k_do_tlbr (void)
{
    r4k_tlb_t *tlb;
    uint8_t ASID;

    ASID = env->CP0_EntryHi & 0xFF;
    tlb = &env->mmu.r4k.tlb[env->CP0_Index % env->nb_tlb];

    /* If this will change the current ASID, flush qemu's TLB.  */
    if (ASID != tlb->ASID)
        cpu_mips_tlb_flush (env, 1);

    r4k_mips_tlb_flush_extra(env, env->nb_tlb);

    env->CP0_EntryHi = tlb->VPN | tlb->ASID;
    env->CP0_PageMask = tlb->PageMask;
    env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
                        (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
    env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
                        (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}

#endif /* !CONFIG_USER_ONLY */

void dump_ldst (const unsigned char *func)
{
    if (loglevel)
        fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
}

void dump_sc (void)
{
    if (loglevel) {
        fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
                T1, T0, env->CP0_LLAddr);
    }
}

void debug_pre_eret (void)
{
    fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
            env->PC, env->CP0_EPC);
    if (env->CP0_Status & (1 << CP0St_ERL))
        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
    if (env->hflags & MIPS_HFLAG_DM)
        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
    fputs("\n", logfile);
}

void debug_post_eret (void)
{
    fprintf(logfile, "  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
            env->PC, env->CP0_EPC);
    if (env->CP0_Status & (1 << CP0St_ERL))
        fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
    if (env->hflags & MIPS_HFLAG_DM)
        fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
    if (env->hflags & MIPS_HFLAG_UM)
        fputs(", UM\n", logfile);
    else
        fputs("\n", logfile);
}

void do_pmon (int function)
{
    function /= 2;
    switch (function) {
    case 2: /* TODO: char inbyte(int waitflag); */
        if (env->gpr[4] == 0)
            env->gpr[2] = -1;
        /* Fall through */
    case 11: /* TODO: char inbyte (void); */
        env->gpr[2] = -1;
        break;
    case 3:
    case 12:
        printf("%c", (char)(env->gpr[4] & 0xFF));
        break;
    case 17:
        break;
    case 158:
        {
            unsigned char *fmt = (void *)(unsigned long)env->gpr[4];
            printf("%s", fmt);
        }
        break;
    }
}

#if !defined(CONFIG_USER_ONLY) 

static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);

#define MMUSUFFIX _mmu
#define ALIGNED_ONLY

#define SHIFT 0
#include "softmmu_template.h"

#define SHIFT 1
#include "softmmu_template.h"

#define SHIFT 2
#include "softmmu_template.h"

#define SHIFT 3
#include "softmmu_template.h"

static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
{
    env->CP0_BadVAddr = addr;
    do_restore_state (retaddr);
    do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
}

void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
{
    TranslationBlock *tb;
    CPUState *saved_env;
    unsigned long pc;
    int ret;

    /* XXX: hack to restore env in all cases, even if not called from
       generated code */
    saved_env = env;
    env = cpu_single_env;
    ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
    if (ret) {
        if (retaddr) {
            /* now we have a real cpu fault */
            pc = (unsigned long)retaddr;
            tb = tb_find_pc(pc);
            if (tb) {
                /* the PC is inside the translated code. It means that we have
                   a virtual CPU fault */
                cpu_restore_state(tb, env, pc, NULL);
            }
        }
        do_raise_exception_err(env->exception_index, env->error_code);
    }
    env = saved_env;
}

#endif
Commit	Line	Data
6af0bf9c FB	1	/*
	2	* MIPS emulation helpers for qemu.
	3	*
	4	* Copyright (c) 2004-2005 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
2d0e944d	20	#include <stdlib.h>
6af0bf9c FB	21	#include "exec.h"
6af0bf9c FB	22
4ad40f36 FB	23	#define GETPC() (__builtin_return_address(0))
4ad40f36 FB	24
6af0bf9c FB	25	/*****************************************************************************/
	26	/* Exceptions processing helpers */
	27	void cpu_loop_exit(void)
	28	{
	29	longjmp(env->jmp_env, 1);
	30	}
	31
6af0bf9c FB	32	void do_raise_exception_err (uint32_t exception, int error_code)
	33	{
	34	#if 1
	35	if (logfile && exception < 0x100)
	36	fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
	37	#endif
	38	env->exception_index = exception;
	39	env->error_code = error_code;
	40	T0 = 0;
	41	cpu_loop_exit();
	42	}
	43
6af0bf9c FB	44	void do_raise_exception (uint32_t exception)
	45	{
	46	do_raise_exception_err(exception, 0);
	47	}
	48
4ad40f36 FB	49	void do_restore_state (void *pc_ptr)
	50	{
	51	TranslationBlock *tb;
	52	unsigned long pc = (unsigned long) pc_ptr;
	53
	54	tb = tb_find_pc (pc);
	55	cpu_restore_state (tb, env, pc, NULL);
	56	}
	57
e397ee33	58	void do_raise_exception_direct_err (uint32_t exception, int error_code)
4ad40f36 FB	59	{
4ad40f36 FB	60	do_restore_state (GETPC ());
e397ee33 TS	61	do_raise_exception_err (exception, error_code);
	62	}
	63
	64	void do_raise_exception_direct (uint32_t exception)
	65	{
	66	do_raise_exception_direct_err (exception, 0);
4ad40f36 FB	67	}
4ad40f36 FB	68
6af0bf9c FB	69	#define MEMSUFFIX _raw
	70	#include "op_helper_mem.c"
	71	#undef MEMSUFFIX
	72	#if !defined(CONFIG_USER_ONLY)
	73	#define MEMSUFFIX _user
	74	#include "op_helper_mem.c"
	75	#undef MEMSUFFIX
	76	#define MEMSUFFIX _kernel
	77	#include "op_helper_mem.c"
	78	#undef MEMSUFFIX
	79	#endif
	80
60aa19ab	81	#ifdef TARGET_MIPS64
c570fd16 TS	82	#if TARGET_LONG_BITS > HOST_LONG_BITS
	83	/* Those might call libgcc functions. */
	84	void do_dsll (void)
	85	{
	86	T0 = T0 << T1;
	87	}
	88
	89	void do_dsll32 (void)
	90	{
	91	T0 = T0 << (T1 + 32);
	92	}
	93
	94	void do_dsra (void)
	95	{
	96	T0 = (int64_t)T0 >> T1;
	97	}
	98
	99	void do_dsra32 (void)
	100	{
	101	T0 = (int64_t)T0 >> (T1 + 32);
	102	}
	103
	104	void do_dsrl (void)
	105	{
	106	T0 = T0 >> T1;
	107	}
	108
	109	void do_dsrl32 (void)
	110	{
	111	T0 = T0 >> (T1 + 32);
	112	}
	113
	114	void do_drotr (void)
	115	{
	116	target_ulong tmp;
	117
	118	if (T1) {
	119	tmp = T0 << (0x40 - T1);
	120	T0 = (T0 >> T1) \| tmp;
5a63bcb2	121	}
c570fd16 TS	122	}
	123
	124	void do_drotr32 (void)
	125	{
	126	target_ulong tmp;
	127
	128	if (T1) {
	129	tmp = T0 << (0x40 - (32 + T1));
	130	T0 = (T0 >> (32 + T1)) \| tmp;
5a63bcb2	131	}
c570fd16 TS	132	}
	133
	134	void do_dsllv (void)
	135	{
	136	T0 = T1 << (T0 & 0x3F);
	137	}
	138
	139	void do_dsrav (void)
	140	{
	141	T0 = (int64_t)T1 >> (T0 & 0x3F);
	142	}
	143
	144	void do_dsrlv (void)
	145	{
	146	T0 = T1 >> (T0 & 0x3F);
	147	}
	148
	149	void do_drotrv (void)
	150	{
	151	target_ulong tmp;
	152
	153	T0 &= 0x3F;
	154	if (T0) {
	155	tmp = T1 << (0x40 - T0);
	156	T0 = (T1 >> T0) \| tmp;
	157	} else
	158	T0 = T1;
	159	}
	160	#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
60aa19ab	161	#endif /* TARGET_MIPS64 */
c570fd16	162
6af0bf9c	163	/* 64 bits arithmetic for 32 bits hosts */
c570fd16	164	#if TARGET_LONG_BITS > HOST_LONG_BITS
6af0bf9c FB	165	static inline uint64_t get_HILO (void)
6af0bf9c FB	166	{
7495fd0f	167	return (env->HI << 32) \| (uint32_t)env->LO;
6af0bf9c FB	168	}
	169
	170	static inline void set_HILO (uint64_t HILO)
	171	{
7495fd0f	172	env->LO = (int32_t)HILO;
5dc4b744	173	env->HI = (int32_t)(HILO >> 32);
6af0bf9c FB	174	}
	175
	176	void do_mult (void)
	177	{
4ad40f36	178	set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c FB	179	}
	180
	181	void do_multu (void)
	182	{
c570fd16	183	set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c FB	184	}
	185
	186	void do_madd (void)
	187	{
	188	int64_t tmp;
	189
4ad40f36	190	tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c FB	191	set_HILO((int64_t)get_HILO() + tmp);
	192	}
	193
	194	void do_maddu (void)
	195	{
	196	uint64_t tmp;
	197
c570fd16	198	tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c FB	199	set_HILO(get_HILO() + tmp);
	200	}
	201
	202	void do_msub (void)
	203	{
	204	int64_t tmp;
	205
4ad40f36	206	tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
6af0bf9c FB	207	set_HILO((int64_t)get_HILO() - tmp);
	208	}
	209
	210	void do_msubu (void)
	211	{
	212	uint64_t tmp;
	213
c570fd16	214	tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
6af0bf9c FB	215	set_HILO(get_HILO() - tmp);
	216	}
	217	#endif
	218
80c27194 TS	219	#if HOST_LONG_BITS < 64
	220	void do_div (void)
	221	{
	222	/* 64bit datatypes because we may see overflow/underflow. */
	223	if (T1 != 0) {
	224	env->LO = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
	225	env->HI = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
	226	}
	227	}
	228	#endif
	229
60aa19ab	230	#ifdef TARGET_MIPS64
c570fd16 TS	231	void do_ddiv (void)
	232	{
	233	if (T1 != 0) {
2d0e944d TS	234	lldiv_t res = lldiv((int64_t)T0, (int64_t)T1);
	235	env->LO = res.quot;
	236	env->HI = res.rem;
c570fd16 TS	237	}
	238	}
	239
	240	void do_ddivu (void)
	241	{
	242	if (T1 != 0) {
2d0e944d TS	243	/* XXX: lldivu? */
	244	lldiv_t res = lldiv(T0, T1);
	245	env->LO = (uint64_t)res.quot;
	246	env->HI = (uint64_t)res.rem;
c570fd16 TS	247	}
	248	}
	249	#endif
	250
048f6b4d	251	#if defined(CONFIG_USER_ONLY)
873eb012	252	void do_mfc0_random (void)
048f6b4d	253	{
873eb012	254	cpu_abort(env, "mfc0 random\n");
048f6b4d	255	}
873eb012 TS	256
	257	void do_mfc0_count (void)
	258	{
	259	cpu_abort(env, "mfc0 count\n");
	260	}
	261
8c0fdd85	262	void cpu_mips_store_count(CPUState *env, uint32_t value)
048f6b4d	263	{
8c0fdd85 TS	264	cpu_abort(env, "mtc0 count\n");
	265	}
	266
	267	void cpu_mips_store_compare(CPUState *env, uint32_t value)
	268	{
	269	cpu_abort(env, "mtc0 compare\n");
	270	}
	271
4de9b249 TS	272	void cpu_mips_update_irq(CPUState *env)
	273	{
	274	cpu_abort(env, "mtc0 status / mtc0 cause\n");
	275	}
	276
8c0fdd85 TS	277	void do_mtc0_status_debug(uint32_t old, uint32_t val)
8c0fdd85 TS	278	{
7a387fff	279	cpu_abort(env, "mtc0 status debug\n");
8c0fdd85 TS	280	}
8c0fdd85 TS	281
7a387fff	282	void do_mtc0_status_irqraise_debug (void)
8c0fdd85	283	{
7a387fff	284	cpu_abort(env, "mtc0 status irqraise debug\n");
048f6b4d FB	285	}
048f6b4d FB	286
8c0fdd85 TS	287	void cpu_mips_tlb_flush (CPUState *env, int flush_global)
	288	{
	289	cpu_abort(env, "mips_tlb_flush\n");
	290	}
	291
048f6b4d FB	292	#else
048f6b4d FB	293
6af0bf9c	294	/* CP0 helpers */
873eb012	295	void do_mfc0_random (void)
6af0bf9c	296	{
5dc4b744	297	T0 = (int32_t)cpu_mips_get_random(env);
873eb012	298	}
6af0bf9c	299
873eb012 TS	300	void do_mfc0_count (void)
873eb012 TS	301	{
5dc4b744	302	T0 = (int32_t)cpu_mips_get_count(env);
6af0bf9c FB	303	}
6af0bf9c FB	304
8c0fdd85	305	void do_mtc0_status_debug(uint32_t old, uint32_t val)
6af0bf9c	306	{
f41c52f1 TS	307	fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
	308	old, old & env->CP0_Cause & CP0Ca_IP_mask,
	309	val, val & env->CP0_Cause & CP0Ca_IP_mask,
	310	env->CP0_Cause);
	311	(env->hflags & MIPS_HFLAG_UM) ? fputs(", UM\n", logfile)
	312	: fputs("\n", logfile);
8c0fdd85 TS	313	}
	314
	315	void do_mtc0_status_irqraise_debug(void)
	316	{
	317	fprintf(logfile, "Raise pending IRQs\n");
6af0bf9c FB	318	}
6af0bf9c FB	319
6ea83fed FB	320	void fpu_handle_exception(void)
	321	{
	322	#ifdef CONFIG_SOFTFLOAT
	323	int flags = get_float_exception_flags(&env->fp_status);
	324	unsigned int cpuflags = 0, enable, cause = 0;
	325
	326	enable = GET_FP_ENABLE(env->fcr31);
	327
	328	/* determine current flags */
	329	if (flags & float_flag_invalid) {
	330	cpuflags \|= FP_INVALID;
	331	cause \|= FP_INVALID & enable;
	332	}
	333	if (flags & float_flag_divbyzero) {
	334	cpuflags \|= FP_DIV0;
	335	cause \|= FP_DIV0 & enable;
	336	}
	337	if (flags & float_flag_overflow) {
	338	cpuflags \|= FP_OVERFLOW;
	339	cause \|= FP_OVERFLOW & enable;
	340	}
	341	if (flags & float_flag_underflow) {
	342	cpuflags \|= FP_UNDERFLOW;
	343	cause \|= FP_UNDERFLOW & enable;
	344	}
	345	if (flags & float_flag_inexact) {
	346	cpuflags \|= FP_INEXACT;
	347	cause \|= FP_INEXACT & enable;
	348	}
	349	SET_FP_FLAGS(env->fcr31, cpuflags);
	350	SET_FP_CAUSE(env->fcr31, cause);
	351	#else
	352	SET_FP_FLAGS(env->fcr31, 0);
	353	SET_FP_CAUSE(env->fcr31, 0);
	354	#endif
	355	}
6ea83fed	356
6af0bf9c	357	/* TLB management */
814b9a47 TS	358	void cpu_mips_tlb_flush (CPUState *env, int flush_global)
	359	{
	360	/* Flush qemu's TLB and discard all shadowed entries. */
	361	tlb_flush (env, flush_global);
fcb4a419	362	env->tlb_in_use = env->nb_tlb;
814b9a47 TS	363	}
814b9a47 TS	364
29929e34	365	static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
814b9a47 TS	366	{
	367	/* Discard entries from env->tlb[first] onwards. */
	368	while (env->tlb_in_use > first) {
29929e34	369	r4k_invalidate_tlb(env, --env->tlb_in_use, 0);
814b9a47 TS	370	}
	371	}
	372
29929e34	373	static void r4k_fill_tlb (int idx)
6af0bf9c	374	{
29929e34	375	r4k_tlb_t *tlb;
6af0bf9c FB	376
6af0bf9c FB	377	/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
29929e34	378	tlb = &env->mmu.r4k.tlb[idx];
f2e9ebef	379	tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
100ce988 TS	380	#ifdef TARGET_MIPS64
	381	tlb->VPN &= 0xC00000FFFFFFFFFFULL;
	382	#endif
98c1b82b	383	tlb->ASID = env->CP0_EntryHi & 0xFF;
3b1c8be4	384	tlb->PageMask = env->CP0_PageMask;
6af0bf9c	385	tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
98c1b82b PB	386	tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
	387	tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
	388	tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
6af0bf9c	389	tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
98c1b82b PB	390	tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
	391	tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
	392	tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
6af0bf9c FB	393	tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
	394	}
	395
29929e34	396	void r4k_do_tlbwi (void)
6af0bf9c	397	{
814b9a47 TS	398	/* Discard cached TLB entries. We could avoid doing this if the
	399	tlbwi is just upgrading access permissions on the current entry;
	400	that might be a further win. */
29929e34	401	r4k_mips_tlb_flush_extra (env, env->nb_tlb);
814b9a47	402
29929e34 TS	403	r4k_invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
29929e34 TS	404	r4k_fill_tlb(env->CP0_Index % env->nb_tlb);
6af0bf9c FB	405	}
6af0bf9c FB	406
29929e34	407	void r4k_do_tlbwr (void)
6af0bf9c FB	408	{
	409	int r = cpu_mips_get_random(env);
	410
29929e34 TS	411	r4k_invalidate_tlb(env, r, 1);
29929e34 TS	412	r4k_fill_tlb(r);
6af0bf9c FB	413	}
6af0bf9c FB	414
29929e34	415	void r4k_do_tlbp (void)
6af0bf9c	416	{
29929e34	417	r4k_tlb_t *tlb;
f2e9ebef	418	target_ulong mask;
6af0bf9c	419	target_ulong tag;
f2e9ebef	420	target_ulong VPN;
6af0bf9c FB	421	uint8_t ASID;
	422	int i;
	423
3d9fb9fe	424	ASID = env->CP0_EntryHi & 0xFF;
fcb4a419	425	for (i = 0; i < env->nb_tlb; i++) {
29929e34	426	tlb = &env->mmu.r4k.tlb[i];
f2e9ebef TS	427	/* 1k pages are not supported. */
	428	mask = tlb->PageMask \| ~(TARGET_PAGE_MASK << 1);
	429	tag = env->CP0_EntryHi & ~mask;
	430	VPN = tlb->VPN & ~mask;
6af0bf9c	431	/* Check ASID, virtual page number & size */
f2e9ebef	432	if ((tlb->G == 1 \|\| tlb->ASID == ASID) && VPN == tag) {
6af0bf9c	433	/* TLB match */
9c2149c8	434	env->CP0_Index = i;
6af0bf9c FB	435	break;
	436	}
	437	}
fcb4a419	438	if (i == env->nb_tlb) {
814b9a47	439	/* No match. Discard any shadow entries, if any of them match. */
fcb4a419	440	for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
29929e34	441	tlb = &env->mmu.r4k.tlb[i];
f2e9ebef TS	442	/* 1k pages are not supported. */
	443	mask = tlb->PageMask \| ~(TARGET_PAGE_MASK << 1);
	444	tag = env->CP0_EntryHi & ~mask;
	445	VPN = tlb->VPN & ~mask;
814b9a47	446	/* Check ASID, virtual page number & size */
f2e9ebef	447	if ((tlb->G == 1 \|\| tlb->ASID == ASID) && VPN == tag) {
29929e34	448	r4k_mips_tlb_flush_extra (env, i);
814b9a47 TS	449	break;
	450	}
	451	}
	452
9c2149c8	453	env->CP0_Index \|= 0x80000000;
6af0bf9c FB	454	}
	455	}
	456
29929e34	457	void r4k_do_tlbr (void)
6af0bf9c	458	{
29929e34	459	r4k_tlb_t *tlb;
09c56b84	460	uint8_t ASID;
6af0bf9c	461
09c56b84	462	ASID = env->CP0_EntryHi & 0xFF;
29929e34	463	tlb = &env->mmu.r4k.tlb[env->CP0_Index % env->nb_tlb];
4ad40f36 FB	464
4ad40f36 FB	465	/* If this will change the current ASID, flush qemu's TLB. */
814b9a47 TS	466	if (ASID != tlb->ASID)
	467	cpu_mips_tlb_flush (env, 1);
	468
29929e34	469	r4k_mips_tlb_flush_extra(env, env->nb_tlb);
4ad40f36	470
6af0bf9c	471	env->CP0_EntryHi = tlb->VPN \| tlb->ASID;
3b1c8be4	472	env->CP0_PageMask = tlb->PageMask;
7495fd0f TS	473	env->CP0_EntryLo0 = tlb->G \| (tlb->V0 << 1) \| (tlb->D0 << 2) \|
	474	(tlb->C0 << 3) \| (tlb->PFN[0] >> 6);
	475	env->CP0_EntryLo1 = tlb->G \| (tlb->V1 << 1) \| (tlb->D1 << 2) \|
	476	(tlb->C1 << 3) \| (tlb->PFN[1] >> 6);
6af0bf9c	477	}
6af0bf9c	478
048f6b4d FB	479	#endif /* !CONFIG_USER_ONLY */
048f6b4d FB	480
c570fd16	481	void dump_ldst (const unsigned char *func)
6af0bf9c FB	482	{
6af0bf9c FB	483	if (loglevel)
3594c774	484	fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
6af0bf9c FB	485	}
	486
	487	void dump_sc (void)
	488	{
	489	if (loglevel) {
3594c774	490	fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
6af0bf9c FB	491	T1, T0, env->CP0_LLAddr);
	492	}
	493	}
	494
f41c52f1	495	void debug_pre_eret (void)
6af0bf9c	496	{
f41c52f1 TS	497	fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
	498	env->PC, env->CP0_EPC);
	499	if (env->CP0_Status & (1 << CP0St_ERL))
	500	fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
	501	if (env->hflags & MIPS_HFLAG_DM)
	502	fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
	503	fputs("\n", logfile);
	504	}
	505
	506	void debug_post_eret (void)
	507	{
744e0915	508	fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
f41c52f1 TS	509	env->PC, env->CP0_EPC);
	510	if (env->CP0_Status & (1 << CP0St_ERL))
	511	fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
	512	if (env->hflags & MIPS_HFLAG_DM)
	513	fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
	514	if (env->hflags & MIPS_HFLAG_UM)
	515	fputs(", UM\n", logfile);
	516	else
24c7b0e3	517	fputs("\n", logfile);
6af0bf9c FB	518	}
6af0bf9c FB	519
6af0bf9c FB	520	void do_pmon (int function)
	521	{
	522	function /= 2;
	523	switch (function) {
	524	case 2: /* TODO: char inbyte(int waitflag); */
	525	if (env->gpr[4] == 0)
	526	env->gpr[2] = -1;
	527	/* Fall through */
	528	case 11: /* TODO: char inbyte (void); */
	529	env->gpr[2] = -1;
	530	break;
	531	case 3:
	532	case 12:
c570fd16	533	printf("%c", (char)(env->gpr[4] & 0xFF));
6af0bf9c FB	534	break;
	535	case 17:
	536	break;
	537	case 158:
	538	{
c570fd16	539	unsigned char fmt = (void )(unsigned long)env->gpr[4];
6af0bf9c FB	540	printf("%s", fmt);
	541	}
	542	break;
	543	}
	544	}
e37e863f FB	545
	546	#if !defined(CONFIG_USER_ONLY)
	547
4ad40f36 FB	548	static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
4ad40f36 FB	549
e37e863f	550	#define MMUSUFFIX _mmu
4ad40f36	551	#define ALIGNED_ONLY
e37e863f FB	552
	553	#define SHIFT 0
	554	#include "softmmu_template.h"
	555
	556	#define SHIFT 1
	557	#include "softmmu_template.h"
	558
	559	#define SHIFT 2
	560	#include "softmmu_template.h"
	561
	562	#define SHIFT 3
	563	#include "softmmu_template.h"
	564
4ad40f36 FB	565	static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
	566	{
	567	env->CP0_BadVAddr = addr;
	568	do_restore_state (retaddr);
	569	do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
	570	}
	571
e37e863f FB	572	void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
	573	{
	574	TranslationBlock *tb;
	575	CPUState *saved_env;
	576	unsigned long pc;
	577	int ret;
	578
	579	/* XXX: hack to restore env in all cases, even if not called from
	580	generated code */
	581	saved_env = env;
	582	env = cpu_single_env;
	583	ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
	584	if (ret) {
	585	if (retaddr) {
	586	/* now we have a real cpu fault */
	587	pc = (unsigned long)retaddr;
	588	tb = tb_find_pc(pc);
	589	if (tb) {
	590	/* the PC is inside the translated code. It means that we have
	591	a virtual CPU fault */
	592	cpu_restore_state(tb, env, pc, NULL);
	593	}
	594	}
	595	do_raise_exception_err(env->exception_index, env->error_code);
	596	}
	597	env = saved_env;
	598	}
	599
	600	#endif