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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
3 | * | |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
6af0bf9c FB |
20 | #include "exec.h" |
21 | ||
22 | #define MIPS_DEBUG_DISAS | |
23 | ||
4ad40f36 FB |
24 | #define GETPC() (__builtin_return_address(0)) |
25 | ||
6af0bf9c FB |
26 | /*****************************************************************************/ |
27 | /* Exceptions processing helpers */ | |
28 | void cpu_loop_exit(void) | |
29 | { | |
30 | longjmp(env->jmp_env, 1); | |
31 | } | |
32 | ||
6af0bf9c FB |
33 | void do_raise_exception_err (uint32_t exception, int error_code) |
34 | { | |
35 | #if 1 | |
36 | if (logfile && exception < 0x100) | |
37 | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code); | |
38 | #endif | |
39 | env->exception_index = exception; | |
40 | env->error_code = error_code; | |
41 | T0 = 0; | |
42 | cpu_loop_exit(); | |
43 | } | |
44 | ||
6af0bf9c FB |
45 | void do_raise_exception (uint32_t exception) |
46 | { | |
47 | do_raise_exception_err(exception, 0); | |
48 | } | |
49 | ||
4ad40f36 FB |
50 | void do_restore_state (void *pc_ptr) |
51 | { | |
52 | TranslationBlock *tb; | |
53 | unsigned long pc = (unsigned long) pc_ptr; | |
54 | ||
55 | tb = tb_find_pc (pc); | |
56 | cpu_restore_state (tb, env, pc, NULL); | |
57 | } | |
58 | ||
59 | void do_raise_exception_direct (uint32_t exception) | |
60 | { | |
61 | do_restore_state (GETPC ()); | |
62 | do_raise_exception_err (exception, 0); | |
63 | } | |
64 | ||
6af0bf9c FB |
65 | #define MEMSUFFIX _raw |
66 | #include "op_helper_mem.c" | |
67 | #undef MEMSUFFIX | |
68 | #if !defined(CONFIG_USER_ONLY) | |
69 | #define MEMSUFFIX _user | |
70 | #include "op_helper_mem.c" | |
71 | #undef MEMSUFFIX | |
72 | #define MEMSUFFIX _kernel | |
73 | #include "op_helper_mem.c" | |
74 | #undef MEMSUFFIX | |
75 | #endif | |
76 | ||
c570fd16 TS |
77 | #ifdef MIPS_HAS_MIPS64 |
78 | #if TARGET_LONG_BITS > HOST_LONG_BITS | |
79 | /* Those might call libgcc functions. */ | |
80 | void do_dsll (void) | |
81 | { | |
82 | T0 = T0 << T1; | |
83 | } | |
84 | ||
85 | void do_dsll32 (void) | |
86 | { | |
87 | T0 = T0 << (T1 + 32); | |
88 | } | |
89 | ||
90 | void do_dsra (void) | |
91 | { | |
92 | T0 = (int64_t)T0 >> T1; | |
93 | } | |
94 | ||
95 | void do_dsra32 (void) | |
96 | { | |
97 | T0 = (int64_t)T0 >> (T1 + 32); | |
98 | } | |
99 | ||
100 | void do_dsrl (void) | |
101 | { | |
102 | T0 = T0 >> T1; | |
103 | } | |
104 | ||
105 | void do_dsrl32 (void) | |
106 | { | |
107 | T0 = T0 >> (T1 + 32); | |
108 | } | |
109 | ||
110 | void do_drotr (void) | |
111 | { | |
112 | target_ulong tmp; | |
113 | ||
114 | if (T1) { | |
115 | tmp = T0 << (0x40 - T1); | |
116 | T0 = (T0 >> T1) | tmp; | |
117 | } else | |
118 | T0 = T1; | |
119 | } | |
120 | ||
121 | void do_drotr32 (void) | |
122 | { | |
123 | target_ulong tmp; | |
124 | ||
125 | if (T1) { | |
126 | tmp = T0 << (0x40 - (32 + T1)); | |
127 | T0 = (T0 >> (32 + T1)) | tmp; | |
128 | } else | |
129 | T0 = T1; | |
130 | } | |
131 | ||
132 | void do_dsllv (void) | |
133 | { | |
134 | T0 = T1 << (T0 & 0x3F); | |
135 | } | |
136 | ||
137 | void do_dsrav (void) | |
138 | { | |
139 | T0 = (int64_t)T1 >> (T0 & 0x3F); | |
140 | } | |
141 | ||
142 | void do_dsrlv (void) | |
143 | { | |
144 | T0 = T1 >> (T0 & 0x3F); | |
145 | } | |
146 | ||
147 | void do_drotrv (void) | |
148 | { | |
149 | target_ulong tmp; | |
150 | ||
151 | T0 &= 0x3F; | |
152 | if (T0) { | |
153 | tmp = T1 << (0x40 - T0); | |
154 | T0 = (T1 >> T0) | tmp; | |
155 | } else | |
156 | T0 = T1; | |
157 | } | |
158 | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ | |
159 | #endif /* MIPS_HAS_MIPS64 */ | |
160 | ||
6af0bf9c | 161 | /* 64 bits arithmetic for 32 bits hosts */ |
c570fd16 | 162 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
6af0bf9c FB |
163 | static inline uint64_t get_HILO (void) |
164 | { | |
165 | return ((uint64_t)env->HI << 32) | (uint64_t)env->LO; | |
166 | } | |
167 | ||
168 | static inline void set_HILO (uint64_t HILO) | |
169 | { | |
c570fd16 TS |
170 | env->LO = SIGN_EXTEND32(HILO & 0xFFFFFFFF); |
171 | env->HI = SIGN_EXTEND32(HILO >> 32); | |
6af0bf9c FB |
172 | } |
173 | ||
174 | void do_mult (void) | |
175 | { | |
4ad40f36 | 176 | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
6af0bf9c FB |
177 | } |
178 | ||
179 | void do_multu (void) | |
180 | { | |
c570fd16 | 181 | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
6af0bf9c FB |
182 | } |
183 | ||
184 | void do_madd (void) | |
185 | { | |
186 | int64_t tmp; | |
187 | ||
4ad40f36 | 188 | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
6af0bf9c FB |
189 | set_HILO((int64_t)get_HILO() + tmp); |
190 | } | |
191 | ||
192 | void do_maddu (void) | |
193 | { | |
194 | uint64_t tmp; | |
195 | ||
c570fd16 | 196 | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
6af0bf9c FB |
197 | set_HILO(get_HILO() + tmp); |
198 | } | |
199 | ||
200 | void do_msub (void) | |
201 | { | |
202 | int64_t tmp; | |
203 | ||
4ad40f36 | 204 | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
6af0bf9c FB |
205 | set_HILO((int64_t)get_HILO() - tmp); |
206 | } | |
207 | ||
208 | void do_msubu (void) | |
209 | { | |
210 | uint64_t tmp; | |
211 | ||
c570fd16 | 212 | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
6af0bf9c FB |
213 | set_HILO(get_HILO() - tmp); |
214 | } | |
215 | #endif | |
216 | ||
c570fd16 TS |
217 | #ifdef MIPS_HAS_MIPS64 |
218 | void do_dmult (void) | |
219 | { | |
220 | /* XXX */ | |
221 | set_HILO((int64_t)T0 * (int64_t)T1); | |
222 | } | |
223 | ||
224 | void do_dmultu (void) | |
225 | { | |
226 | /* XXX */ | |
227 | set_HILO((uint64_t)T0 * (uint64_t)T1); | |
228 | } | |
229 | ||
230 | void do_ddiv (void) | |
231 | { | |
232 | if (T1 != 0) { | |
233 | env->LO = (int64_t)T0 / (int64_t)T1; | |
234 | env->HI = (int64_t)T0 % (int64_t)T1; | |
235 | } | |
236 | } | |
237 | ||
238 | void do_ddivu (void) | |
239 | { | |
240 | if (T1 != 0) { | |
241 | env->LO = T0 / T1; | |
242 | env->HI = T0 % T1; | |
243 | } | |
244 | } | |
245 | #endif | |
246 | ||
048f6b4d | 247 | #if defined(CONFIG_USER_ONLY) |
873eb012 | 248 | void do_mfc0_random (void) |
048f6b4d | 249 | { |
873eb012 | 250 | cpu_abort(env, "mfc0 random\n"); |
048f6b4d | 251 | } |
873eb012 TS |
252 | |
253 | void do_mfc0_count (void) | |
254 | { | |
255 | cpu_abort(env, "mfc0 count\n"); | |
256 | } | |
257 | ||
8c0fdd85 | 258 | void cpu_mips_store_count(CPUState *env, uint32_t value) |
048f6b4d | 259 | { |
8c0fdd85 TS |
260 | cpu_abort(env, "mtc0 count\n"); |
261 | } | |
262 | ||
263 | void cpu_mips_store_compare(CPUState *env, uint32_t value) | |
264 | { | |
265 | cpu_abort(env, "mtc0 compare\n"); | |
266 | } | |
267 | ||
268 | void do_mtc0_status_debug(uint32_t old, uint32_t val) | |
269 | { | |
7a387fff | 270 | cpu_abort(env, "mtc0 status debug\n"); |
8c0fdd85 TS |
271 | } |
272 | ||
7a387fff | 273 | void do_mtc0_status_irqraise_debug (void) |
8c0fdd85 | 274 | { |
7a387fff | 275 | cpu_abort(env, "mtc0 status irqraise debug\n"); |
048f6b4d FB |
276 | } |
277 | ||
278 | void do_tlbwi (void) | |
279 | { | |
280 | cpu_abort(env, "tlbwi\n"); | |
281 | } | |
282 | ||
283 | void do_tlbwr (void) | |
284 | { | |
285 | cpu_abort(env, "tlbwr\n"); | |
286 | } | |
287 | ||
288 | void do_tlbp (void) | |
289 | { | |
290 | cpu_abort(env, "tlbp\n"); | |
291 | } | |
292 | ||
293 | void do_tlbr (void) | |
294 | { | |
295 | cpu_abort(env, "tlbr\n"); | |
296 | } | |
873eb012 | 297 | |
8c0fdd85 TS |
298 | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
299 | { | |
300 | cpu_abort(env, "mips_tlb_flush\n"); | |
301 | } | |
302 | ||
048f6b4d FB |
303 | #else |
304 | ||
6af0bf9c | 305 | /* CP0 helpers */ |
873eb012 | 306 | void do_mfc0_random (void) |
6af0bf9c | 307 | { |
c570fd16 | 308 | T0 = SIGN_EXTEND32(cpu_mips_get_random(env)); |
873eb012 | 309 | } |
6af0bf9c | 310 | |
873eb012 TS |
311 | void do_mfc0_count (void) |
312 | { | |
c570fd16 | 313 | T0 = SIGN_EXTEND32(cpu_mips_get_count(env)); |
6af0bf9c FB |
314 | } |
315 | ||
8c0fdd85 | 316 | void do_mtc0_status_debug(uint32_t old, uint32_t val) |
6af0bf9c | 317 | { |
8c0fdd85 TS |
318 | const uint32_t mask = 0x0000FF00; |
319 | fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n", | |
320 | old, val, env->CP0_Cause, old & mask, val & mask, | |
321 | env->CP0_Cause & mask); | |
322 | } | |
323 | ||
324 | void do_mtc0_status_irqraise_debug(void) | |
325 | { | |
326 | fprintf(logfile, "Raise pending IRQs\n"); | |
6af0bf9c FB |
327 | } |
328 | ||
6ea83fed FB |
329 | #ifdef MIPS_USES_FPU |
330 | #include "softfloat.h" | |
331 | ||
332 | void fpu_handle_exception(void) | |
333 | { | |
334 | #ifdef CONFIG_SOFTFLOAT | |
335 | int flags = get_float_exception_flags(&env->fp_status); | |
336 | unsigned int cpuflags = 0, enable, cause = 0; | |
337 | ||
338 | enable = GET_FP_ENABLE(env->fcr31); | |
339 | ||
340 | /* determine current flags */ | |
341 | if (flags & float_flag_invalid) { | |
342 | cpuflags |= FP_INVALID; | |
343 | cause |= FP_INVALID & enable; | |
344 | } | |
345 | if (flags & float_flag_divbyzero) { | |
346 | cpuflags |= FP_DIV0; | |
347 | cause |= FP_DIV0 & enable; | |
348 | } | |
349 | if (flags & float_flag_overflow) { | |
350 | cpuflags |= FP_OVERFLOW; | |
351 | cause |= FP_OVERFLOW & enable; | |
352 | } | |
353 | if (flags & float_flag_underflow) { | |
354 | cpuflags |= FP_UNDERFLOW; | |
355 | cause |= FP_UNDERFLOW & enable; | |
356 | } | |
357 | if (flags & float_flag_inexact) { | |
358 | cpuflags |= FP_INEXACT; | |
359 | cause |= FP_INEXACT & enable; | |
360 | } | |
361 | SET_FP_FLAGS(env->fcr31, cpuflags); | |
362 | SET_FP_CAUSE(env->fcr31, cause); | |
363 | #else | |
364 | SET_FP_FLAGS(env->fcr31, 0); | |
365 | SET_FP_CAUSE(env->fcr31, 0); | |
366 | #endif | |
367 | } | |
368 | #endif /* MIPS_USES_FPU */ | |
369 | ||
6af0bf9c FB |
370 | /* TLB management */ |
371 | #if defined(MIPS_USES_R4K_TLB) | |
814b9a47 TS |
372 | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
373 | { | |
374 | /* Flush qemu's TLB and discard all shadowed entries. */ | |
375 | tlb_flush (env, flush_global); | |
376 | env->tlb_in_use = MIPS_TLB_NB; | |
377 | } | |
378 | ||
379 | static void invalidate_tlb (int idx, int use_extra) | |
6af0bf9c FB |
380 | { |
381 | tlb_t *tlb; | |
98c1b82b | 382 | target_ulong addr; |
483dcf53 PB |
383 | uint8_t ASID; |
384 | ||
385 | ASID = env->CP0_EntryHi & 0xFF; | |
6af0bf9c FB |
386 | |
387 | tlb = &env->tlb[idx]; | |
483dcf53 PB |
388 | /* The qemu TLB is flushed then the ASID changes, so no need to |
389 | flush these entries again. */ | |
390 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
391 | return; | |
392 | } | |
393 | ||
814b9a47 TS |
394 | if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) { |
395 | /* For tlbwr, we can shadow the discarded entry into | |
396 | a new (fake) TLB entry, as long as the guest can not | |
397 | tell that it's there. */ | |
398 | env->tlb[env->tlb_in_use] = *tlb; | |
399 | env->tlb_in_use++; | |
400 | return; | |
401 | } | |
402 | ||
98c1b82b PB |
403 | if (tlb->V0) { |
404 | tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN); | |
4ad40f36 FB |
405 | addr = tlb->VPN; |
406 | while (addr < tlb->end) { | |
407 | tlb_flush_page (env, addr); | |
408 | addr += TARGET_PAGE_SIZE; | |
409 | } | |
6af0bf9c | 410 | } |
98c1b82b PB |
411 | if (tlb->V1) { |
412 | tb_invalidate_page_range(tlb->PFN[1], tlb->end2 - tlb->end); | |
4ad40f36 FB |
413 | addr = tlb->end; |
414 | while (addr < tlb->end2) { | |
415 | tlb_flush_page (env, addr); | |
416 | addr += TARGET_PAGE_SIZE; | |
417 | } | |
6af0bf9c FB |
418 | } |
419 | } | |
420 | ||
814b9a47 TS |
421 | static void mips_tlb_flush_extra (CPUState *env, int first) |
422 | { | |
423 | /* Discard entries from env->tlb[first] onwards. */ | |
424 | while (env->tlb_in_use > first) { | |
425 | invalidate_tlb(--env->tlb_in_use, 0); | |
426 | } | |
427 | } | |
428 | ||
98c1b82b | 429 | static void fill_tlb (int idx) |
6af0bf9c FB |
430 | { |
431 | tlb_t *tlb; | |
432 | int size; | |
433 | ||
434 | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ | |
435 | tlb = &env->tlb[idx]; | |
c570fd16 | 436 | tlb->VPN = env->CP0_EntryHi & SIGN_EXTEND32(0xFFFFE000); |
98c1b82b | 437 | tlb->ASID = env->CP0_EntryHi & 0xFF; |
6af0bf9c FB |
438 | size = env->CP0_PageMask >> 13; |
439 | size = 4 * (size + 1); | |
440 | tlb->end = tlb->VPN + (1 << (8 + size)); | |
4ad40f36 | 441 | tlb->end2 = tlb->end + (1 << (8 + size)); |
6af0bf9c | 442 | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
98c1b82b PB |
443 | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
444 | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; | |
445 | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; | |
6af0bf9c | 446 | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
98c1b82b PB |
447 | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
448 | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; | |
449 | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; | |
6af0bf9c FB |
450 | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
451 | } | |
452 | ||
453 | void do_tlbwi (void) | |
454 | { | |
814b9a47 TS |
455 | /* Discard cached TLB entries. We could avoid doing this if the |
456 | tlbwi is just upgrading access permissions on the current entry; | |
457 | that might be a further win. */ | |
458 | mips_tlb_flush_extra (env, MIPS_TLB_NB); | |
459 | ||
7a962d30 FB |
460 | /* Wildly undefined effects for CP0_index containing a too high value and |
461 | MIPS_TLB_NB not being a power of two. But so does real silicon. */ | |
814b9a47 | 462 | invalidate_tlb(env->CP0_index & (MIPS_TLB_NB - 1), 0); |
98c1b82b | 463 | fill_tlb(env->CP0_index & (MIPS_TLB_NB - 1)); |
6af0bf9c FB |
464 | } |
465 | ||
466 | void do_tlbwr (void) | |
467 | { | |
468 | int r = cpu_mips_get_random(env); | |
469 | ||
814b9a47 | 470 | invalidate_tlb(r, 1); |
98c1b82b | 471 | fill_tlb(r); |
6af0bf9c FB |
472 | } |
473 | ||
474 | void do_tlbp (void) | |
475 | { | |
476 | tlb_t *tlb; | |
477 | target_ulong tag; | |
478 | uint8_t ASID; | |
479 | int i; | |
480 | ||
c570fd16 | 481 | tag = env->CP0_EntryHi & SIGN_EXTEND32(0xFFFFE000); |
3d9fb9fe FB |
482 | ASID = env->CP0_EntryHi & 0xFF; |
483 | for (i = 0; i < MIPS_TLB_NB; i++) { | |
6af0bf9c FB |
484 | tlb = &env->tlb[i]; |
485 | /* Check ASID, virtual page number & size */ | |
486 | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { | |
487 | /* TLB match */ | |
488 | env->CP0_index = i; | |
489 | break; | |
490 | } | |
491 | } | |
7a962d30 | 492 | if (i == MIPS_TLB_NB) { |
814b9a47 TS |
493 | /* No match. Discard any shadow entries, if any of them match. */ |
494 | for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) { | |
495 | tlb = &env->tlb[i]; | |
496 | ||
497 | /* Check ASID, virtual page number & size */ | |
498 | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { | |
499 | mips_tlb_flush_extra (env, i); | |
500 | break; | |
501 | } | |
502 | } | |
503 | ||
6af0bf9c FB |
504 | env->CP0_index |= 0x80000000; |
505 | } | |
506 | } | |
507 | ||
508 | void do_tlbr (void) | |
509 | { | |
510 | tlb_t *tlb; | |
09c56b84 | 511 | uint8_t ASID; |
6af0bf9c FB |
512 | int size; |
513 | ||
09c56b84 | 514 | ASID = env->CP0_EntryHi & 0xFF; |
7a962d30 | 515 | tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)]; |
4ad40f36 FB |
516 | |
517 | /* If this will change the current ASID, flush qemu's TLB. */ | |
814b9a47 TS |
518 | if (ASID != tlb->ASID) |
519 | cpu_mips_tlb_flush (env, 1); | |
520 | ||
521 | mips_tlb_flush_extra(env, MIPS_TLB_NB); | |
4ad40f36 | 522 | |
6af0bf9c FB |
523 | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
524 | size = (tlb->end - tlb->VPN) >> 12; | |
525 | env->CP0_PageMask = (size - 1) << 13; | |
98c1b82b PB |
526 | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
527 | | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); | |
528 | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
529 | | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); | |
6af0bf9c FB |
530 | } |
531 | #endif | |
532 | ||
048f6b4d FB |
533 | #endif /* !CONFIG_USER_ONLY */ |
534 | ||
c570fd16 | 535 | void dump_ldst (const unsigned char *func) |
6af0bf9c FB |
536 | { |
537 | if (loglevel) | |
c570fd16 | 538 | fprintf(logfile, "%s => " TLSZ " " TLSZ "\n", __func__, T0, T1); |
6af0bf9c FB |
539 | } |
540 | ||
541 | void dump_sc (void) | |
542 | { | |
543 | if (loglevel) { | |
c570fd16 | 544 | fprintf(logfile, "%s " TLSZ " at " TLSZ " (" TLSZ ")\n", __func__, |
6af0bf9c FB |
545 | T1, T0, env->CP0_LLAddr); |
546 | } | |
547 | } | |
548 | ||
549 | void debug_eret (void) | |
550 | { | |
551 | if (loglevel) { | |
c570fd16 | 552 | fprintf(logfile, "ERET: pc " TLSZ " EPC " TLSZ " ErrorEPC " TLSZ " (%d)\n", |
6af0bf9c FB |
553 | env->PC, env->CP0_EPC, env->CP0_ErrorEPC, |
554 | env->hflags & MIPS_HFLAG_ERL ? 1 : 0); | |
555 | } | |
556 | } | |
557 | ||
6af0bf9c FB |
558 | void do_pmon (int function) |
559 | { | |
560 | function /= 2; | |
561 | switch (function) { | |
562 | case 2: /* TODO: char inbyte(int waitflag); */ | |
563 | if (env->gpr[4] == 0) | |
564 | env->gpr[2] = -1; | |
565 | /* Fall through */ | |
566 | case 11: /* TODO: char inbyte (void); */ | |
567 | env->gpr[2] = -1; | |
568 | break; | |
569 | case 3: | |
570 | case 12: | |
c570fd16 | 571 | printf("%c", (char)(env->gpr[4] & 0xFF)); |
6af0bf9c FB |
572 | break; |
573 | case 17: | |
574 | break; | |
575 | case 158: | |
576 | { | |
c570fd16 | 577 | unsigned char *fmt = (void *)(unsigned long)env->gpr[4]; |
6af0bf9c FB |
578 | printf("%s", fmt); |
579 | } | |
580 | break; | |
581 | } | |
582 | } | |
e37e863f FB |
583 | |
584 | #if !defined(CONFIG_USER_ONLY) | |
585 | ||
4ad40f36 FB |
586 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
587 | ||
e37e863f | 588 | #define MMUSUFFIX _mmu |
4ad40f36 | 589 | #define ALIGNED_ONLY |
e37e863f FB |
590 | |
591 | #define SHIFT 0 | |
592 | #include "softmmu_template.h" | |
593 | ||
594 | #define SHIFT 1 | |
595 | #include "softmmu_template.h" | |
596 | ||
597 | #define SHIFT 2 | |
598 | #include "softmmu_template.h" | |
599 | ||
600 | #define SHIFT 3 | |
601 | #include "softmmu_template.h" | |
602 | ||
4ad40f36 FB |
603 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
604 | { | |
605 | env->CP0_BadVAddr = addr; | |
606 | do_restore_state (retaddr); | |
607 | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); | |
608 | } | |
609 | ||
e37e863f FB |
610 | void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
611 | { | |
612 | TranslationBlock *tb; | |
613 | CPUState *saved_env; | |
614 | unsigned long pc; | |
615 | int ret; | |
616 | ||
617 | /* XXX: hack to restore env in all cases, even if not called from | |
618 | generated code */ | |
619 | saved_env = env; | |
620 | env = cpu_single_env; | |
621 | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1); | |
622 | if (ret) { | |
623 | if (retaddr) { | |
624 | /* now we have a real cpu fault */ | |
625 | pc = (unsigned long)retaddr; | |
626 | tb = tb_find_pc(pc); | |
627 | if (tb) { | |
628 | /* the PC is inside the translated code. It means that we have | |
629 | a virtual CPU fault */ | |
630 | cpu_restore_state(tb, env, pc, NULL); | |
631 | } | |
632 | } | |
633 | do_raise_exception_err(env->exception_index, env->error_code); | |
634 | } | |
635 | env = saved_env; | |
636 | } | |
637 | ||
638 | #endif |