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6af0bf9c FB |
1 | /* |
2 | * MIPS32 emulation for qemu: main translation routines. | |
5fafdf24 | 3 | * |
6af0bf9c | 4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
6ea83fed | 5 | * Copyright (c) 2006 Marius Groeger (FPU operations) |
bb8a53ad | 6 | * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) |
6af0bf9c FB |
7 | * |
8 | * This library is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU Lesser General Public | |
10 | * License as published by the Free Software Foundation; either | |
11 | * version 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This library is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * Lesser General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU Lesser General Public | |
19 | * License along with this library; if not, write to the Free Software | |
fad6cb1a | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
6af0bf9c FB |
21 | */ |
22 | ||
23 | #include <stdarg.h> | |
24 | #include <stdlib.h> | |
25 | #include <stdio.h> | |
26 | #include <string.h> | |
27 | #include <inttypes.h> | |
28 | ||
29 | #include "cpu.h" | |
30 | #include "exec-all.h" | |
31 | #include "disas.h" | |
57fec1fe | 32 | #include "tcg-op.h" |
ca10f867 | 33 | #include "qemu-common.h" |
6af0bf9c | 34 | |
a7812ae4 PB |
35 | #include "helper.h" |
36 | #define GEN_HELPER 1 | |
37 | #include "helper.h" | |
38 | ||
eeef26cd | 39 | //#define MIPS_DEBUG_DISAS |
c570fd16 | 40 | //#define MIPS_DEBUG_SIGN_EXTENSIONS |
6af0bf9c | 41 | |
7a387fff TS |
42 | /* MIPS major opcodes */ |
43 | #define MASK_OP_MAJOR(op) (op & (0x3F << 26)) | |
e37e863f FB |
44 | |
45 | enum { | |
46 | /* indirect opcode tables */ | |
7a387fff TS |
47 | OPC_SPECIAL = (0x00 << 26), |
48 | OPC_REGIMM = (0x01 << 26), | |
49 | OPC_CP0 = (0x10 << 26), | |
50 | OPC_CP1 = (0x11 << 26), | |
51 | OPC_CP2 = (0x12 << 26), | |
52 | OPC_CP3 = (0x13 << 26), | |
53 | OPC_SPECIAL2 = (0x1C << 26), | |
54 | OPC_SPECIAL3 = (0x1F << 26), | |
e37e863f | 55 | /* arithmetic with immediate */ |
7a387fff TS |
56 | OPC_ADDI = (0x08 << 26), |
57 | OPC_ADDIU = (0x09 << 26), | |
58 | OPC_SLTI = (0x0A << 26), | |
59 | OPC_SLTIU = (0x0B << 26), | |
324d9e32 | 60 | /* logic with immediate */ |
7a387fff TS |
61 | OPC_ANDI = (0x0C << 26), |
62 | OPC_ORI = (0x0D << 26), | |
63 | OPC_XORI = (0x0E << 26), | |
64 | OPC_LUI = (0x0F << 26), | |
324d9e32 | 65 | /* arithmetic with immediate */ |
7a387fff TS |
66 | OPC_DADDI = (0x18 << 26), |
67 | OPC_DADDIU = (0x19 << 26), | |
e37e863f | 68 | /* Jump and branches */ |
7a387fff TS |
69 | OPC_J = (0x02 << 26), |
70 | OPC_JAL = (0x03 << 26), | |
71 | OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */ | |
72 | OPC_BEQL = (0x14 << 26), | |
73 | OPC_BNE = (0x05 << 26), | |
74 | OPC_BNEL = (0x15 << 26), | |
75 | OPC_BLEZ = (0x06 << 26), | |
76 | OPC_BLEZL = (0x16 << 26), | |
77 | OPC_BGTZ = (0x07 << 26), | |
78 | OPC_BGTZL = (0x17 << 26), | |
79 | OPC_JALX = (0x1D << 26), /* MIPS 16 only */ | |
e37e863f | 80 | /* Load and stores */ |
7a387fff TS |
81 | OPC_LDL = (0x1A << 26), |
82 | OPC_LDR = (0x1B << 26), | |
83 | OPC_LB = (0x20 << 26), | |
84 | OPC_LH = (0x21 << 26), | |
85 | OPC_LWL = (0x22 << 26), | |
86 | OPC_LW = (0x23 << 26), | |
87 | OPC_LBU = (0x24 << 26), | |
88 | OPC_LHU = (0x25 << 26), | |
89 | OPC_LWR = (0x26 << 26), | |
90 | OPC_LWU = (0x27 << 26), | |
91 | OPC_SB = (0x28 << 26), | |
92 | OPC_SH = (0x29 << 26), | |
93 | OPC_SWL = (0x2A << 26), | |
94 | OPC_SW = (0x2B << 26), | |
95 | OPC_SDL = (0x2C << 26), | |
96 | OPC_SDR = (0x2D << 26), | |
97 | OPC_SWR = (0x2E << 26), | |
98 | OPC_LL = (0x30 << 26), | |
99 | OPC_LLD = (0x34 << 26), | |
100 | OPC_LD = (0x37 << 26), | |
101 | OPC_SC = (0x38 << 26), | |
102 | OPC_SCD = (0x3C << 26), | |
103 | OPC_SD = (0x3F << 26), | |
e37e863f | 104 | /* Floating point load/store */ |
7a387fff TS |
105 | OPC_LWC1 = (0x31 << 26), |
106 | OPC_LWC2 = (0x32 << 26), | |
107 | OPC_LDC1 = (0x35 << 26), | |
108 | OPC_LDC2 = (0x36 << 26), | |
109 | OPC_SWC1 = (0x39 << 26), | |
110 | OPC_SWC2 = (0x3A << 26), | |
111 | OPC_SDC1 = (0x3D << 26), | |
112 | OPC_SDC2 = (0x3E << 26), | |
113 | /* MDMX ASE specific */ | |
114 | OPC_MDMX = (0x1E << 26), | |
e37e863f | 115 | /* Cache and prefetch */ |
7a387fff TS |
116 | OPC_CACHE = (0x2F << 26), |
117 | OPC_PREF = (0x33 << 26), | |
118 | /* Reserved major opcode */ | |
119 | OPC_MAJOR3B_RESERVED = (0x3B << 26), | |
e37e863f FB |
120 | }; |
121 | ||
122 | /* MIPS special opcodes */ | |
7a387fff TS |
123 | #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F) |
124 | ||
e37e863f FB |
125 | enum { |
126 | /* Shifts */ | |
7a387fff | 127 | OPC_SLL = 0x00 | OPC_SPECIAL, |
e37e863f FB |
128 | /* NOP is SLL r0, r0, 0 */ |
129 | /* SSNOP is SLL r0, r0, 1 */ | |
7a387fff TS |
130 | /* EHB is SLL r0, r0, 3 */ |
131 | OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */ | |
132 | OPC_SRA = 0x03 | OPC_SPECIAL, | |
133 | OPC_SLLV = 0x04 | OPC_SPECIAL, | |
e189e748 | 134 | OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */ |
7a387fff TS |
135 | OPC_SRAV = 0x07 | OPC_SPECIAL, |
136 | OPC_DSLLV = 0x14 | OPC_SPECIAL, | |
137 | OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */ | |
138 | OPC_DSRAV = 0x17 | OPC_SPECIAL, | |
139 | OPC_DSLL = 0x38 | OPC_SPECIAL, | |
140 | OPC_DSRL = 0x3A | OPC_SPECIAL, /* also DROTR */ | |
141 | OPC_DSRA = 0x3B | OPC_SPECIAL, | |
142 | OPC_DSLL32 = 0x3C | OPC_SPECIAL, | |
143 | OPC_DSRL32 = 0x3E | OPC_SPECIAL, /* also DROTR32 */ | |
144 | OPC_DSRA32 = 0x3F | OPC_SPECIAL, | |
e37e863f | 145 | /* Multiplication / division */ |
7a387fff TS |
146 | OPC_MULT = 0x18 | OPC_SPECIAL, |
147 | OPC_MULTU = 0x19 | OPC_SPECIAL, | |
148 | OPC_DIV = 0x1A | OPC_SPECIAL, | |
149 | OPC_DIVU = 0x1B | OPC_SPECIAL, | |
150 | OPC_DMULT = 0x1C | OPC_SPECIAL, | |
151 | OPC_DMULTU = 0x1D | OPC_SPECIAL, | |
152 | OPC_DDIV = 0x1E | OPC_SPECIAL, | |
153 | OPC_DDIVU = 0x1F | OPC_SPECIAL, | |
e37e863f | 154 | /* 2 registers arithmetic / logic */ |
7a387fff TS |
155 | OPC_ADD = 0x20 | OPC_SPECIAL, |
156 | OPC_ADDU = 0x21 | OPC_SPECIAL, | |
157 | OPC_SUB = 0x22 | OPC_SPECIAL, | |
158 | OPC_SUBU = 0x23 | OPC_SPECIAL, | |
159 | OPC_AND = 0x24 | OPC_SPECIAL, | |
160 | OPC_OR = 0x25 | OPC_SPECIAL, | |
161 | OPC_XOR = 0x26 | OPC_SPECIAL, | |
162 | OPC_NOR = 0x27 | OPC_SPECIAL, | |
163 | OPC_SLT = 0x2A | OPC_SPECIAL, | |
164 | OPC_SLTU = 0x2B | OPC_SPECIAL, | |
165 | OPC_DADD = 0x2C | OPC_SPECIAL, | |
166 | OPC_DADDU = 0x2D | OPC_SPECIAL, | |
167 | OPC_DSUB = 0x2E | OPC_SPECIAL, | |
168 | OPC_DSUBU = 0x2F | OPC_SPECIAL, | |
e37e863f | 169 | /* Jumps */ |
7a387fff TS |
170 | OPC_JR = 0x08 | OPC_SPECIAL, /* Also JR.HB */ |
171 | OPC_JALR = 0x09 | OPC_SPECIAL, /* Also JALR.HB */ | |
e37e863f | 172 | /* Traps */ |
7a387fff TS |
173 | OPC_TGE = 0x30 | OPC_SPECIAL, |
174 | OPC_TGEU = 0x31 | OPC_SPECIAL, | |
175 | OPC_TLT = 0x32 | OPC_SPECIAL, | |
176 | OPC_TLTU = 0x33 | OPC_SPECIAL, | |
177 | OPC_TEQ = 0x34 | OPC_SPECIAL, | |
178 | OPC_TNE = 0x36 | OPC_SPECIAL, | |
e37e863f | 179 | /* HI / LO registers load & stores */ |
7a387fff TS |
180 | OPC_MFHI = 0x10 | OPC_SPECIAL, |
181 | OPC_MTHI = 0x11 | OPC_SPECIAL, | |
182 | OPC_MFLO = 0x12 | OPC_SPECIAL, | |
183 | OPC_MTLO = 0x13 | OPC_SPECIAL, | |
e37e863f | 184 | /* Conditional moves */ |
7a387fff TS |
185 | OPC_MOVZ = 0x0A | OPC_SPECIAL, |
186 | OPC_MOVN = 0x0B | OPC_SPECIAL, | |
e37e863f | 187 | |
7a387fff | 188 | OPC_MOVCI = 0x01 | OPC_SPECIAL, |
e37e863f FB |
189 | |
190 | /* Special */ | |
7a387fff TS |
191 | OPC_PMON = 0x05 | OPC_SPECIAL, /* inofficial */ |
192 | OPC_SYSCALL = 0x0C | OPC_SPECIAL, | |
193 | OPC_BREAK = 0x0D | OPC_SPECIAL, | |
194 | OPC_SPIM = 0x0E | OPC_SPECIAL, /* inofficial */ | |
195 | OPC_SYNC = 0x0F | OPC_SPECIAL, | |
196 | ||
197 | OPC_SPECIAL15_RESERVED = 0x15 | OPC_SPECIAL, | |
198 | OPC_SPECIAL28_RESERVED = 0x28 | OPC_SPECIAL, | |
199 | OPC_SPECIAL29_RESERVED = 0x29 | OPC_SPECIAL, | |
200 | OPC_SPECIAL35_RESERVED = 0x35 | OPC_SPECIAL, | |
201 | OPC_SPECIAL37_RESERVED = 0x37 | OPC_SPECIAL, | |
202 | OPC_SPECIAL39_RESERVED = 0x39 | OPC_SPECIAL, | |
203 | OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, | |
204 | }; | |
205 | ||
e9c71dd1 TS |
206 | /* Multiplication variants of the vr54xx. */ |
207 | #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6)) | |
208 | ||
209 | enum { | |
210 | OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT, | |
211 | OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU, | |
212 | OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT, | |
213 | OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU, | |
214 | OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT, | |
215 | OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU, | |
216 | OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT, | |
217 | OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU, | |
218 | OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT, | |
219 | OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU, | |
220 | OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT, | |
221 | OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU, | |
222 | OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT, | |
223 | OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU, | |
224 | }; | |
225 | ||
7a387fff TS |
226 | /* REGIMM (rt field) opcodes */ |
227 | #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16)) | |
228 | ||
229 | enum { | |
230 | OPC_BLTZ = (0x00 << 16) | OPC_REGIMM, | |
231 | OPC_BLTZL = (0x02 << 16) | OPC_REGIMM, | |
232 | OPC_BGEZ = (0x01 << 16) | OPC_REGIMM, | |
233 | OPC_BGEZL = (0x03 << 16) | OPC_REGIMM, | |
234 | OPC_BLTZAL = (0x10 << 16) | OPC_REGIMM, | |
235 | OPC_BLTZALL = (0x12 << 16) | OPC_REGIMM, | |
236 | OPC_BGEZAL = (0x11 << 16) | OPC_REGIMM, | |
237 | OPC_BGEZALL = (0x13 << 16) | OPC_REGIMM, | |
238 | OPC_TGEI = (0x08 << 16) | OPC_REGIMM, | |
239 | OPC_TGEIU = (0x09 << 16) | OPC_REGIMM, | |
240 | OPC_TLTI = (0x0A << 16) | OPC_REGIMM, | |
241 | OPC_TLTIU = (0x0B << 16) | OPC_REGIMM, | |
242 | OPC_TEQI = (0x0C << 16) | OPC_REGIMM, | |
243 | OPC_TNEI = (0x0E << 16) | OPC_REGIMM, | |
244 | OPC_SYNCI = (0x1F << 16) | OPC_REGIMM, | |
e37e863f FB |
245 | }; |
246 | ||
7a387fff TS |
247 | /* Special2 opcodes */ |
248 | #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F) | |
249 | ||
e37e863f | 250 | enum { |
7a387fff TS |
251 | /* Multiply & xxx operations */ |
252 | OPC_MADD = 0x00 | OPC_SPECIAL2, | |
253 | OPC_MADDU = 0x01 | OPC_SPECIAL2, | |
254 | OPC_MUL = 0x02 | OPC_SPECIAL2, | |
255 | OPC_MSUB = 0x04 | OPC_SPECIAL2, | |
256 | OPC_MSUBU = 0x05 | OPC_SPECIAL2, | |
e37e863f | 257 | /* Misc */ |
7a387fff TS |
258 | OPC_CLZ = 0x20 | OPC_SPECIAL2, |
259 | OPC_CLO = 0x21 | OPC_SPECIAL2, | |
260 | OPC_DCLZ = 0x24 | OPC_SPECIAL2, | |
261 | OPC_DCLO = 0x25 | OPC_SPECIAL2, | |
e37e863f | 262 | /* Special */ |
7a387fff TS |
263 | OPC_SDBBP = 0x3F | OPC_SPECIAL2, |
264 | }; | |
265 | ||
266 | /* Special3 opcodes */ | |
267 | #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F) | |
268 | ||
269 | enum { | |
270 | OPC_EXT = 0x00 | OPC_SPECIAL3, | |
271 | OPC_DEXTM = 0x01 | OPC_SPECIAL3, | |
272 | OPC_DEXTU = 0x02 | OPC_SPECIAL3, | |
273 | OPC_DEXT = 0x03 | OPC_SPECIAL3, | |
274 | OPC_INS = 0x04 | OPC_SPECIAL3, | |
275 | OPC_DINSM = 0x05 | OPC_SPECIAL3, | |
276 | OPC_DINSU = 0x06 | OPC_SPECIAL3, | |
277 | OPC_DINS = 0x07 | OPC_SPECIAL3, | |
ead9360e TS |
278 | OPC_FORK = 0x08 | OPC_SPECIAL3, |
279 | OPC_YIELD = 0x09 | OPC_SPECIAL3, | |
7a387fff TS |
280 | OPC_BSHFL = 0x20 | OPC_SPECIAL3, |
281 | OPC_DBSHFL = 0x24 | OPC_SPECIAL3, | |
282 | OPC_RDHWR = 0x3B | OPC_SPECIAL3, | |
e37e863f FB |
283 | }; |
284 | ||
7a387fff TS |
285 | /* BSHFL opcodes */ |
286 | #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) | |
287 | ||
e37e863f | 288 | enum { |
7a387fff TS |
289 | OPC_WSBH = (0x02 << 6) | OPC_BSHFL, |
290 | OPC_SEB = (0x10 << 6) | OPC_BSHFL, | |
291 | OPC_SEH = (0x18 << 6) | OPC_BSHFL, | |
e37e863f FB |
292 | }; |
293 | ||
7a387fff TS |
294 | /* DBSHFL opcodes */ |
295 | #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6)) | |
296 | ||
e37e863f | 297 | enum { |
7a387fff TS |
298 | OPC_DSBH = (0x02 << 6) | OPC_DBSHFL, |
299 | OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, | |
e37e863f FB |
300 | }; |
301 | ||
7a387fff TS |
302 | /* Coprocessor 0 (rs field) */ |
303 | #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | |
304 | ||
6ea83fed | 305 | enum { |
7a387fff TS |
306 | OPC_MFC0 = (0x00 << 21) | OPC_CP0, |
307 | OPC_DMFC0 = (0x01 << 21) | OPC_CP0, | |
308 | OPC_MTC0 = (0x04 << 21) | OPC_CP0, | |
309 | OPC_DMTC0 = (0x05 << 21) | OPC_CP0, | |
ead9360e | 310 | OPC_MFTR = (0x08 << 21) | OPC_CP0, |
7a387fff TS |
311 | OPC_RDPGPR = (0x0A << 21) | OPC_CP0, |
312 | OPC_MFMC0 = (0x0B << 21) | OPC_CP0, | |
ead9360e | 313 | OPC_MTTR = (0x0C << 21) | OPC_CP0, |
7a387fff TS |
314 | OPC_WRPGPR = (0x0E << 21) | OPC_CP0, |
315 | OPC_C0 = (0x10 << 21) | OPC_CP0, | |
316 | OPC_C0_FIRST = (0x10 << 21) | OPC_CP0, | |
317 | OPC_C0_LAST = (0x1F << 21) | OPC_CP0, | |
6ea83fed | 318 | }; |
7a387fff TS |
319 | |
320 | /* MFMC0 opcodes */ | |
b48cfdff | 321 | #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF) |
7a387fff TS |
322 | |
323 | enum { | |
ead9360e TS |
324 | OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, |
325 | OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, | |
326 | OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0, | |
327 | OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0, | |
7a387fff TS |
328 | OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, |
329 | OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0, | |
330 | }; | |
331 | ||
332 | /* Coprocessor 0 (with rs == C0) */ | |
333 | #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F) | |
334 | ||
335 | enum { | |
336 | OPC_TLBR = 0x01 | OPC_C0, | |
337 | OPC_TLBWI = 0x02 | OPC_C0, | |
338 | OPC_TLBWR = 0x06 | OPC_C0, | |
339 | OPC_TLBP = 0x08 | OPC_C0, | |
340 | OPC_RFE = 0x10 | OPC_C0, | |
341 | OPC_ERET = 0x18 | OPC_C0, | |
342 | OPC_DERET = 0x1F | OPC_C0, | |
343 | OPC_WAIT = 0x20 | OPC_C0, | |
344 | }; | |
345 | ||
346 | /* Coprocessor 1 (rs field) */ | |
347 | #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | |
348 | ||
349 | enum { | |
350 | OPC_MFC1 = (0x00 << 21) | OPC_CP1, | |
351 | OPC_DMFC1 = (0x01 << 21) | OPC_CP1, | |
352 | OPC_CFC1 = (0x02 << 21) | OPC_CP1, | |
5a5012ec | 353 | OPC_MFHC1 = (0x03 << 21) | OPC_CP1, |
7a387fff TS |
354 | OPC_MTC1 = (0x04 << 21) | OPC_CP1, |
355 | OPC_DMTC1 = (0x05 << 21) | OPC_CP1, | |
356 | OPC_CTC1 = (0x06 << 21) | OPC_CP1, | |
5a5012ec | 357 | OPC_MTHC1 = (0x07 << 21) | OPC_CP1, |
7a387fff | 358 | OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */ |
5a5012ec TS |
359 | OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1, |
360 | OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1, | |
7a387fff TS |
361 | OPC_S_FMT = (0x10 << 21) | OPC_CP1, /* 16: fmt=single fp */ |
362 | OPC_D_FMT = (0x11 << 21) | OPC_CP1, /* 17: fmt=double fp */ | |
363 | OPC_E_FMT = (0x12 << 21) | OPC_CP1, /* 18: fmt=extended fp */ | |
364 | OPC_Q_FMT = (0x13 << 21) | OPC_CP1, /* 19: fmt=quad fp */ | |
365 | OPC_W_FMT = (0x14 << 21) | OPC_CP1, /* 20: fmt=32bit fixed */ | |
366 | OPC_L_FMT = (0x15 << 21) | OPC_CP1, /* 21: fmt=64bit fixed */ | |
5a5012ec | 367 | OPC_PS_FMT = (0x16 << 21) | OPC_CP1, /* 22: fmt=paired single fp */ |
7a387fff TS |
368 | }; |
369 | ||
5a5012ec TS |
370 | #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F) |
371 | #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16)) | |
372 | ||
7a387fff TS |
373 | enum { |
374 | OPC_BC1F = (0x00 << 16) | OPC_BC1, | |
375 | OPC_BC1T = (0x01 << 16) | OPC_BC1, | |
376 | OPC_BC1FL = (0x02 << 16) | OPC_BC1, | |
377 | OPC_BC1TL = (0x03 << 16) | OPC_BC1, | |
378 | }; | |
379 | ||
5a5012ec TS |
380 | enum { |
381 | OPC_BC1FANY2 = (0x00 << 16) | OPC_BC1ANY2, | |
382 | OPC_BC1TANY2 = (0x01 << 16) | OPC_BC1ANY2, | |
383 | }; | |
384 | ||
385 | enum { | |
386 | OPC_BC1FANY4 = (0x00 << 16) | OPC_BC1ANY4, | |
387 | OPC_BC1TANY4 = (0x01 << 16) | OPC_BC1ANY4, | |
388 | }; | |
7a387fff TS |
389 | |
390 | #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) | |
e0c84da7 TS |
391 | |
392 | enum { | |
393 | OPC_MFC2 = (0x00 << 21) | OPC_CP2, | |
394 | OPC_DMFC2 = (0x01 << 21) | OPC_CP2, | |
395 | OPC_CFC2 = (0x02 << 21) | OPC_CP2, | |
396 | OPC_MFHC2 = (0x03 << 21) | OPC_CP2, | |
397 | OPC_MTC2 = (0x04 << 21) | OPC_CP2, | |
398 | OPC_DMTC2 = (0x05 << 21) | OPC_CP2, | |
399 | OPC_CTC2 = (0x06 << 21) | OPC_CP2, | |
400 | OPC_MTHC2 = (0x07 << 21) | OPC_CP2, | |
401 | OPC_BC2 = (0x08 << 21) | OPC_CP2, | |
402 | }; | |
403 | ||
404 | #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F) | |
405 | ||
406 | enum { | |
407 | OPC_LWXC1 = 0x00 | OPC_CP3, | |
408 | OPC_LDXC1 = 0x01 | OPC_CP3, | |
409 | OPC_LUXC1 = 0x05 | OPC_CP3, | |
410 | OPC_SWXC1 = 0x08 | OPC_CP3, | |
411 | OPC_SDXC1 = 0x09 | OPC_CP3, | |
412 | OPC_SUXC1 = 0x0D | OPC_CP3, | |
413 | OPC_PREFX = 0x0F | OPC_CP3, | |
414 | OPC_ALNV_PS = 0x1E | OPC_CP3, | |
415 | OPC_MADD_S = 0x20 | OPC_CP3, | |
416 | OPC_MADD_D = 0x21 | OPC_CP3, | |
417 | OPC_MADD_PS = 0x26 | OPC_CP3, | |
418 | OPC_MSUB_S = 0x28 | OPC_CP3, | |
419 | OPC_MSUB_D = 0x29 | OPC_CP3, | |
420 | OPC_MSUB_PS = 0x2E | OPC_CP3, | |
421 | OPC_NMADD_S = 0x30 | OPC_CP3, | |
fbcc6828 | 422 | OPC_NMADD_D = 0x31 | OPC_CP3, |
e0c84da7 TS |
423 | OPC_NMADD_PS= 0x36 | OPC_CP3, |
424 | OPC_NMSUB_S = 0x38 | OPC_CP3, | |
425 | OPC_NMSUB_D = 0x39 | OPC_CP3, | |
426 | OPC_NMSUB_PS= 0x3E | OPC_CP3, | |
427 | }; | |
428 | ||
39454628 | 429 | /* global register indices */ |
a7812ae4 PB |
430 | static TCGv_ptr cpu_env; |
431 | static TCGv cpu_gpr[32], cpu_PC; | |
4b2eb8d2 | 432 | static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC]; |
41db4607 AJ |
433 | static TCGv cpu_dspctrl, btarget, bcond; |
434 | static TCGv_i32 hflags; | |
a7812ae4 | 435 | static TCGv_i32 fpu_fcr0, fpu_fcr31; |
aa0bf00b | 436 | |
2e70f6ef PB |
437 | #include "gen-icount.h" |
438 | ||
a7812ae4 PB |
439 | #define gen_helper_0i(name, arg) do { \ |
440 | TCGv_i32 helper_tmp = tcg_const_i32(arg); \ | |
441 | gen_helper_##name(helper_tmp); \ | |
442 | tcg_temp_free_i32(helper_tmp); \ | |
443 | } while(0) | |
be24bb4f | 444 | |
a7812ae4 PB |
445 | #define gen_helper_1i(name, arg1, arg2) do { \ |
446 | TCGv_i32 helper_tmp = tcg_const_i32(arg2); \ | |
447 | gen_helper_##name(arg1, helper_tmp); \ | |
448 | tcg_temp_free_i32(helper_tmp); \ | |
449 | } while(0) | |
be24bb4f | 450 | |
a7812ae4 PB |
451 | #define gen_helper_2i(name, arg1, arg2, arg3) do { \ |
452 | TCGv_i32 helper_tmp = tcg_const_i32(arg3); \ | |
453 | gen_helper_##name(arg1, arg2, helper_tmp); \ | |
454 | tcg_temp_free_i32(helper_tmp); \ | |
455 | } while(0) | |
be24bb4f | 456 | |
a7812ae4 PB |
457 | #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \ |
458 | TCGv_i32 helper_tmp = tcg_const_i32(arg4); \ | |
459 | gen_helper_##name(arg1, arg2, arg3, helper_tmp); \ | |
460 | tcg_temp_free_i32(helper_tmp); \ | |
461 | } while(0) | |
c239529e | 462 | |
8e9ade68 TS |
463 | typedef struct DisasContext { |
464 | struct TranslationBlock *tb; | |
465 | target_ulong pc, saved_pc; | |
466 | uint32_t opcode; | |
8e9ade68 TS |
467 | /* Routine used to access memory */ |
468 | int mem_idx; | |
469 | uint32_t hflags, saved_hflags; | |
470 | int bstate; | |
471 | target_ulong btarget; | |
472 | } DisasContext; | |
473 | ||
474 | enum { | |
475 | BS_NONE = 0, /* We go out of the TB without reaching a branch or an | |
d077b6f7 | 476 | * exception condition */ |
8e9ade68 TS |
477 | BS_STOP = 1, /* We want to stop translation for any reason */ |
478 | BS_BRANCH = 2, /* We reached a branch condition */ | |
479 | BS_EXCP = 3, /* We reached an exception condition */ | |
480 | }; | |
481 | ||
482 | static const char *regnames[] = | |
6af0bf9c FB |
483 | { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
484 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
485 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
486 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; | |
487 | ||
4b2eb8d2 TS |
488 | static const char *regnames_HI[] = |
489 | { "HI0", "HI1", "HI2", "HI3", }; | |
490 | ||
491 | static const char *regnames_LO[] = | |
492 | { "LO0", "LO1", "LO2", "LO3", }; | |
493 | ||
494 | static const char *regnames_ACX[] = | |
495 | { "ACX0", "ACX1", "ACX2", "ACX3", }; | |
496 | ||
8e9ade68 TS |
497 | static const char *fregnames[] = |
498 | { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
499 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
500 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
501 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; | |
958fb4a9 | 502 | |
8e9ade68 | 503 | #ifdef MIPS_DEBUG_DISAS |
001faf32 | 504 | #define MIPS_DEBUG(fmt, ...) \ |
93fcfe39 AL |
505 | qemu_log_mask(CPU_LOG_TB_IN_ASM, \ |
506 | TARGET_FMT_lx ": %08x " fmt "\n", \ | |
001faf32 | 507 | ctx->pc, ctx->opcode , ## __VA_ARGS__) |
93fcfe39 | 508 | #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
8e9ade68 | 509 | #else |
001faf32 | 510 | #define MIPS_DEBUG(fmt, ...) do { } while(0) |
d12d51d5 | 511 | #define LOG_DISAS(...) do { } while (0) |
8e9ade68 | 512 | #endif |
958fb4a9 | 513 | |
8e9ade68 TS |
514 | #define MIPS_INVAL(op) \ |
515 | do { \ | |
516 | MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \ | |
517 | ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \ | |
518 | } while (0) | |
ead9360e | 519 | |
8e9ade68 TS |
520 | /* General purpose registers moves. */ |
521 | static inline void gen_load_gpr (TCGv t, int reg) | |
aaa9128a | 522 | { |
8e9ade68 TS |
523 | if (reg == 0) |
524 | tcg_gen_movi_tl(t, 0); | |
525 | else | |
4b2eb8d2 | 526 | tcg_gen_mov_tl(t, cpu_gpr[reg]); |
aaa9128a TS |
527 | } |
528 | ||
8e9ade68 | 529 | static inline void gen_store_gpr (TCGv t, int reg) |
aaa9128a | 530 | { |
8e9ade68 | 531 | if (reg != 0) |
4b2eb8d2 | 532 | tcg_gen_mov_tl(cpu_gpr[reg], t); |
aaa9128a TS |
533 | } |
534 | ||
b10fa3c9 | 535 | /* Moves to/from ACX register. */ |
4b2eb8d2 | 536 | static inline void gen_load_ACX (TCGv t, int reg) |
893f9865 | 537 | { |
4b2eb8d2 | 538 | tcg_gen_mov_tl(t, cpu_ACX[reg]); |
893f9865 TS |
539 | } |
540 | ||
4b2eb8d2 | 541 | static inline void gen_store_ACX (TCGv t, int reg) |
893f9865 | 542 | { |
4b2eb8d2 | 543 | tcg_gen_mov_tl(cpu_ACX[reg], t); |
893f9865 TS |
544 | } |
545 | ||
8e9ade68 | 546 | /* Moves to/from shadow registers. */ |
be24bb4f | 547 | static inline void gen_load_srsgpr (int from, int to) |
aaa9128a | 548 | { |
d9bea114 | 549 | TCGv t0 = tcg_temp_new(); |
be24bb4f TS |
550 | |
551 | if (from == 0) | |
d9bea114 | 552 | tcg_gen_movi_tl(t0, 0); |
8e9ade68 | 553 | else { |
d9bea114 | 554 | TCGv_i32 t2 = tcg_temp_new_i32(); |
a7812ae4 | 555 | TCGv_ptr addr = tcg_temp_new_ptr(); |
aaa9128a | 556 | |
d9bea114 AJ |
557 | tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); |
558 | tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); | |
559 | tcg_gen_andi_i32(t2, t2, 0xf); | |
560 | tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); | |
561 | tcg_gen_ext_i32_ptr(addr, t2); | |
a7812ae4 | 562 | tcg_gen_add_ptr(addr, cpu_env, addr); |
aaa9128a | 563 | |
d9bea114 | 564 | tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); |
a7812ae4 | 565 | tcg_temp_free_ptr(addr); |
d9bea114 | 566 | tcg_temp_free_i32(t2); |
8e9ade68 | 567 | } |
d9bea114 AJ |
568 | gen_store_gpr(t0, to); |
569 | tcg_temp_free(t0); | |
aaa9128a TS |
570 | } |
571 | ||
be24bb4f | 572 | static inline void gen_store_srsgpr (int from, int to) |
aaa9128a | 573 | { |
be24bb4f | 574 | if (to != 0) { |
d9bea114 AJ |
575 | TCGv t0 = tcg_temp_new(); |
576 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
a7812ae4 | 577 | TCGv_ptr addr = tcg_temp_new_ptr(); |
be24bb4f | 578 | |
d9bea114 AJ |
579 | gen_load_gpr(t0, from); |
580 | tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl)); | |
581 | tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); | |
582 | tcg_gen_andi_i32(t2, t2, 0xf); | |
583 | tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); | |
584 | tcg_gen_ext_i32_ptr(addr, t2); | |
a7812ae4 | 585 | tcg_gen_add_ptr(addr, cpu_env, addr); |
be24bb4f | 586 | |
d9bea114 | 587 | tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); |
a7812ae4 | 588 | tcg_temp_free_ptr(addr); |
d9bea114 AJ |
589 | tcg_temp_free_i32(t2); |
590 | tcg_temp_free(t0); | |
8e9ade68 | 591 | } |
aaa9128a TS |
592 | } |
593 | ||
aaa9128a | 594 | /* Floating point register moves. */ |
a7812ae4 | 595 | static inline void gen_load_fpr32 (TCGv_i32 t, int reg) |
aa0bf00b | 596 | { |
6d066274 | 597 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); |
6ea83fed FB |
598 | } |
599 | ||
a7812ae4 | 600 | static inline void gen_store_fpr32 (TCGv_i32 t, int reg) |
aa0bf00b | 601 | { |
6d066274 AJ |
602 | tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); |
603 | } | |
604 | ||
605 | static inline void gen_load_fpr32h (TCGv_i32 t, int reg) | |
606 | { | |
607 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); | |
608 | } | |
609 | ||
610 | static inline void gen_store_fpr32h (TCGv_i32 t, int reg) | |
611 | { | |
612 | tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); | |
aa0bf00b | 613 | } |
6ea83fed | 614 | |
a7812ae4 | 615 | static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) |
aa0bf00b | 616 | { |
f364515c | 617 | if (ctx->hflags & MIPS_HFLAG_F64) { |
6d066274 | 618 | tcg_gen_ld_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); |
f364515c | 619 | } else { |
6d066274 AJ |
620 | TCGv_i32 t0 = tcg_temp_new_i32(); |
621 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
622 | gen_load_fpr32(t0, reg & ~1); | |
623 | gen_load_fpr32(t1, reg | 1); | |
624 | tcg_gen_concat_i32_i64(t, t0, t1); | |
625 | tcg_temp_free_i32(t0); | |
626 | tcg_temp_free_i32(t1); | |
aa0bf00b TS |
627 | } |
628 | } | |
6ea83fed | 629 | |
a7812ae4 | 630 | static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) |
aa0bf00b | 631 | { |
f364515c | 632 | if (ctx->hflags & MIPS_HFLAG_F64) { |
6d066274 | 633 | tcg_gen_st_i64(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].d)); |
f364515c | 634 | } else { |
6d066274 AJ |
635 | TCGv_i64 t0 = tcg_temp_new_i64(); |
636 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
637 | tcg_gen_trunc_i64_i32(t1, t); | |
638 | gen_store_fpr32(t1, reg & ~1); | |
639 | tcg_gen_shri_i64(t0, t, 32); | |
640 | tcg_gen_trunc_i64_i32(t1, t0); | |
641 | gen_store_fpr32(t1, reg | 1); | |
642 | tcg_temp_free_i32(t1); | |
643 | tcg_temp_free_i64(t0); | |
aa0bf00b TS |
644 | } |
645 | } | |
6ea83fed | 646 | |
d94536f4 | 647 | static inline int get_fp_bit (int cc) |
a16336e4 | 648 | { |
d94536f4 AJ |
649 | if (cc) |
650 | return 24 + cc; | |
651 | else | |
652 | return 23; | |
a16336e4 TS |
653 | } |
654 | ||
a7812ae4 PB |
655 | #define FOP_CONDS(type, fmt, bits) \ |
656 | static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \ | |
657 | TCGv_i##bits b, int cc) \ | |
b6d96bed | 658 | { \ |
a7812ae4 PB |
659 | switch (n) { \ |
660 | case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\ | |
661 | case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\ | |
662 | case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\ | |
663 | case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\ | |
664 | case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\ | |
665 | case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\ | |
666 | case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\ | |
667 | case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\ | |
668 | case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\ | |
669 | case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\ | |
670 | case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\ | |
671 | case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\ | |
672 | case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\ | |
673 | case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\ | |
674 | case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\ | |
675 | case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\ | |
676 | default: abort(); \ | |
677 | } \ | |
6ea83fed FB |
678 | } |
679 | ||
a7812ae4 PB |
680 | FOP_CONDS(, d, 64) |
681 | FOP_CONDS(abs, d, 64) | |
682 | FOP_CONDS(, s, 32) | |
683 | FOP_CONDS(abs, s, 32) | |
684 | FOP_CONDS(, ps, 64) | |
685 | FOP_CONDS(abs, ps, 64) | |
5d0fc900 | 686 | #undef FOP_CONDS |
6ea83fed | 687 | |
30898801 | 688 | /* Tests */ |
92e90443 AJ |
689 | #define OP_COND(name, cond) \ |
690 | static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, TCGv t1) \ | |
691 | { \ | |
692 | int l1 = gen_new_label(); \ | |
693 | int l2 = gen_new_label(); \ | |
694 | \ | |
695 | tcg_gen_brcond_tl(cond, t0, t1, l1); \ | |
696 | tcg_gen_movi_tl(ret, 0); \ | |
697 | tcg_gen_br(l2); \ | |
698 | gen_set_label(l1); \ | |
699 | tcg_gen_movi_tl(ret, 1); \ | |
700 | gen_set_label(l2); \ | |
30898801 TS |
701 | } |
702 | OP_COND(eq, TCG_COND_EQ); | |
703 | OP_COND(ne, TCG_COND_NE); | |
704 | OP_COND(ge, TCG_COND_GE); | |
705 | OP_COND(geu, TCG_COND_GEU); | |
706 | OP_COND(lt, TCG_COND_LT); | |
707 | OP_COND(ltu, TCG_COND_LTU); | |
708 | #undef OP_COND | |
709 | ||
92e90443 AJ |
710 | #define OP_CONDI(name, cond) \ |
711 | static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, target_ulong val) \ | |
712 | { \ | |
713 | int l1 = gen_new_label(); \ | |
714 | int l2 = gen_new_label(); \ | |
715 | \ | |
716 | tcg_gen_brcondi_tl(cond, t0, val, l1); \ | |
717 | tcg_gen_movi_tl(ret, 0); \ | |
718 | tcg_gen_br(l2); \ | |
719 | gen_set_label(l1); \ | |
720 | tcg_gen_movi_tl(ret, 1); \ | |
721 | gen_set_label(l2); \ | |
30898801 TS |
722 | } |
723 | OP_CONDI(lti, TCG_COND_LT); | |
724 | OP_CONDI(ltiu, TCG_COND_LTU); | |
725 | #undef OP_CONDI | |
726 | ||
727 | #define OP_CONDZ(name, cond) \ | |
92e90443 | 728 | static inline void glue(gen_op_, name) (TCGv ret, TCGv t0) \ |
30898801 TS |
729 | { \ |
730 | int l1 = gen_new_label(); \ | |
731 | int l2 = gen_new_label(); \ | |
732 | \ | |
92e90443 AJ |
733 | tcg_gen_brcondi_tl(cond, t0, 0, l1); \ |
734 | tcg_gen_movi_tl(ret, 0); \ | |
30898801 TS |
735 | tcg_gen_br(l2); \ |
736 | gen_set_label(l1); \ | |
92e90443 | 737 | tcg_gen_movi_tl(ret, 1); \ |
30898801 TS |
738 | gen_set_label(l2); \ |
739 | } | |
740 | OP_CONDZ(gez, TCG_COND_GE); | |
741 | OP_CONDZ(gtz, TCG_COND_GT); | |
742 | OP_CONDZ(lez, TCG_COND_LE); | |
743 | OP_CONDZ(ltz, TCG_COND_LT); | |
744 | #undef OP_CONDZ | |
745 | ||
8e9ade68 TS |
746 | static inline void gen_save_pc(target_ulong pc) |
747 | { | |
1eb75d4a | 748 | tcg_gen_movi_tl(cpu_PC, pc); |
8e9ade68 | 749 | } |
30898801 | 750 | |
356265ae | 751 | static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) |
6af0bf9c | 752 | { |
d12d51d5 | 753 | LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); |
6af0bf9c | 754 | if (do_save_pc && ctx->pc != ctx->saved_pc) { |
9b9e4393 | 755 | gen_save_pc(ctx->pc); |
6af0bf9c FB |
756 | ctx->saved_pc = ctx->pc; |
757 | } | |
758 | if (ctx->hflags != ctx->saved_hflags) { | |
41db4607 | 759 | tcg_gen_movi_i32(hflags, ctx->hflags); |
6af0bf9c | 760 | ctx->saved_hflags = ctx->hflags; |
5a5012ec TS |
761 | switch (ctx->hflags & MIPS_HFLAG_BMASK) { |
762 | case MIPS_HFLAG_BR: | |
5a5012ec TS |
763 | break; |
764 | case MIPS_HFLAG_BC: | |
5a5012ec | 765 | case MIPS_HFLAG_BL: |
5a5012ec | 766 | case MIPS_HFLAG_B: |
d077b6f7 | 767 | tcg_gen_movi_tl(btarget, ctx->btarget); |
5a5012ec | 768 | break; |
6af0bf9c FB |
769 | } |
770 | } | |
771 | } | |
772 | ||
356265ae | 773 | static inline void restore_cpu_state (CPUState *env, DisasContext *ctx) |
5a5012ec | 774 | { |
fd4a04eb TS |
775 | ctx->saved_hflags = ctx->hflags; |
776 | switch (ctx->hflags & MIPS_HFLAG_BMASK) { | |
777 | case MIPS_HFLAG_BR: | |
fd4a04eb TS |
778 | break; |
779 | case MIPS_HFLAG_BC: | |
780 | case MIPS_HFLAG_BL: | |
39454628 | 781 | case MIPS_HFLAG_B: |
fd4a04eb | 782 | ctx->btarget = env->btarget; |
fd4a04eb | 783 | break; |
5a5012ec TS |
784 | } |
785 | } | |
786 | ||
356265ae | 787 | static inline void |
48d38ca5 | 788 | generate_exception_err (DisasContext *ctx, int excp, int err) |
aaa9128a | 789 | { |
a7812ae4 PB |
790 | TCGv_i32 texcp = tcg_const_i32(excp); |
791 | TCGv_i32 terr = tcg_const_i32(err); | |
aaa9128a | 792 | save_cpu_state(ctx, 1); |
a7812ae4 PB |
793 | gen_helper_raise_exception_err(texcp, terr); |
794 | tcg_temp_free_i32(terr); | |
795 | tcg_temp_free_i32(texcp); | |
aaa9128a TS |
796 | } |
797 | ||
356265ae | 798 | static inline void |
48d38ca5 | 799 | generate_exception (DisasContext *ctx, int excp) |
aaa9128a | 800 | { |
6af0bf9c | 801 | save_cpu_state(ctx, 1); |
a7812ae4 | 802 | gen_helper_0i(raise_exception, excp); |
6af0bf9c FB |
803 | } |
804 | ||
48d38ca5 | 805 | /* Addresses computation */ |
d144d1d9 | 806 | static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1) |
4ad40f36 | 807 | { |
be24bb4f | 808 | tcg_gen_add_tl(t0, t0, t1); |
48d38ca5 TS |
809 | |
810 | #if defined(TARGET_MIPS64) | |
811 | /* For compatibility with 32-bit code, data reference in user mode | |
812 | with Status_UX = 0 should be casted to 32-bit and sign extended. | |
813 | See the MIPS64 PRA manual, section 4.10. */ | |
2623c1ec AJ |
814 | if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && |
815 | !(ctx->hflags & MIPS_HFLAG_UX)) { | |
be24bb4f | 816 | tcg_gen_ext32s_i64(t0, t0); |
48d38ca5 TS |
817 | } |
818 | #endif | |
4ad40f36 FB |
819 | } |
820 | ||
356265ae | 821 | static inline void check_cp0_enabled(DisasContext *ctx) |
387a8fe5 | 822 | { |
fe253235 | 823 | if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) |
387a8fe5 TS |
824 | generate_exception_err(ctx, EXCP_CpU, 1); |
825 | } | |
826 | ||
356265ae | 827 | static inline void check_cp1_enabled(DisasContext *ctx) |
5e755519 | 828 | { |
fe253235 | 829 | if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) |
5e755519 TS |
830 | generate_exception_err(ctx, EXCP_CpU, 1); |
831 | } | |
832 | ||
b8aa4598 TS |
833 | /* Verify that the processor is running with COP1X instructions enabled. |
834 | This is associated with the nabla symbol in the MIPS32 and MIPS64 | |
835 | opcode tables. */ | |
836 | ||
356265ae | 837 | static inline void check_cop1x(DisasContext *ctx) |
b8aa4598 TS |
838 | { |
839 | if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) | |
840 | generate_exception(ctx, EXCP_RI); | |
841 | } | |
842 | ||
843 | /* Verify that the processor is running with 64-bit floating-point | |
844 | operations enabled. */ | |
845 | ||
356265ae | 846 | static inline void check_cp1_64bitmode(DisasContext *ctx) |
5e755519 | 847 | { |
b8aa4598 | 848 | if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) |
5e755519 TS |
849 | generate_exception(ctx, EXCP_RI); |
850 | } | |
851 | ||
852 | /* | |
853 | * Verify if floating point register is valid; an operation is not defined | |
854 | * if bit 0 of any register specification is set and the FR bit in the | |
855 | * Status register equals zero, since the register numbers specify an | |
856 | * even-odd pair of adjacent coprocessor general registers. When the FR bit | |
857 | * in the Status register equals one, both even and odd register numbers | |
858 | * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers. | |
859 | * | |
860 | * Multiple 64 bit wide registers can be checked by calling | |
861 | * gen_op_cp1_registers(freg1 | freg2 | ... | fregN); | |
862 | */ | |
356265ae | 863 | static inline void check_cp1_registers(DisasContext *ctx, int regs) |
5e755519 | 864 | { |
fe253235 | 865 | if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) |
5e755519 TS |
866 | generate_exception(ctx, EXCP_RI); |
867 | } | |
868 | ||
3a95e3a7 | 869 | /* This code generates a "reserved instruction" exception if the |
e189e748 | 870 | CPU does not support the instruction set corresponding to flags. */ |
356265ae | 871 | static inline void check_insn(CPUState *env, DisasContext *ctx, int flags) |
3a95e3a7 | 872 | { |
e189e748 | 873 | if (unlikely(!(env->insn_flags & flags))) |
3a95e3a7 TS |
874 | generate_exception(ctx, EXCP_RI); |
875 | } | |
876 | ||
e189e748 TS |
877 | /* This code generates a "reserved instruction" exception if 64-bit |
878 | instructions are not enabled. */ | |
356265ae | 879 | static inline void check_mips_64(DisasContext *ctx) |
e189e748 | 880 | { |
fe253235 | 881 | if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) |
e189e748 TS |
882 | generate_exception(ctx, EXCP_RI); |
883 | } | |
884 | ||
958fb4a9 | 885 | /* load/store instructions. */ |
d9bea114 AJ |
886 | #define OP_LD(insn,fname) \ |
887 | static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ | |
888 | { \ | |
889 | tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ | |
aaa9128a TS |
890 | } |
891 | OP_LD(lb,ld8s); | |
892 | OP_LD(lbu,ld8u); | |
893 | OP_LD(lh,ld16s); | |
894 | OP_LD(lhu,ld16u); | |
895 | OP_LD(lw,ld32s); | |
896 | #if defined(TARGET_MIPS64) | |
897 | OP_LD(lwu,ld32u); | |
898 | OP_LD(ld,ld64); | |
899 | #endif | |
900 | #undef OP_LD | |
901 | ||
d9bea114 AJ |
902 | #define OP_ST(insn,fname) \ |
903 | static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \ | |
904 | { \ | |
905 | tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \ | |
aaa9128a TS |
906 | } |
907 | OP_ST(sb,st8); | |
908 | OP_ST(sh,st16); | |
909 | OP_ST(sw,st32); | |
910 | #if defined(TARGET_MIPS64) | |
911 | OP_ST(sd,st64); | |
912 | #endif | |
913 | #undef OP_ST | |
914 | ||
d9bea114 AJ |
915 | #define OP_LD_ATOMIC(insn,fname) \ |
916 | static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ | |
917 | { \ | |
918 | TCGv t0 = tcg_temp_new(); \ | |
919 | tcg_gen_mov_tl(t0, arg1); \ | |
920 | tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ | |
921 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \ | |
922 | tcg_temp_free(t0); \ | |
aaa9128a TS |
923 | } |
924 | OP_LD_ATOMIC(ll,ld32s); | |
925 | #if defined(TARGET_MIPS64) | |
926 | OP_LD_ATOMIC(lld,ld64); | |
927 | #endif | |
928 | #undef OP_LD_ATOMIC | |
929 | ||
d9bea114 AJ |
930 | #define OP_ST_ATOMIC(insn,fname,almask) \ |
931 | static inline void op_ldst_##insn(TCGv ret, TCGv arg1, TCGv arg2, DisasContext *ctx) \ | |
932 | { \ | |
933 | TCGv t0 = tcg_temp_new(); \ | |
934 | int l1 = gen_new_label(); \ | |
935 | int l2 = gen_new_label(); \ | |
936 | int l3 = gen_new_label(); \ | |
937 | \ | |
938 | tcg_gen_andi_tl(t0, arg2, almask); \ | |
939 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \ | |
940 | tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \ | |
941 | generate_exception(ctx, EXCP_AdES); \ | |
942 | gen_set_label(l1); \ | |
943 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \ | |
944 | tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \ | |
945 | tcg_temp_free(t0); \ | |
946 | tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \ | |
947 | tcg_gen_movi_tl(ret, 1); \ | |
948 | tcg_gen_br(l3); \ | |
949 | gen_set_label(l2); \ | |
950 | tcg_gen_movi_tl(ret, 0); \ | |
951 | gen_set_label(l3); \ | |
aaa9128a TS |
952 | } |
953 | OP_ST_ATOMIC(sc,st32,0x3); | |
954 | #if defined(TARGET_MIPS64) | |
955 | OP_ST_ATOMIC(scd,st64,0x7); | |
956 | #endif | |
957 | #undef OP_ST_ATOMIC | |
958 | ||
6af0bf9c | 959 | /* Load and store */ |
7a387fff | 960 | static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, |
6af0bf9c FB |
961 | int base, int16_t offset) |
962 | { | |
923617a3 | 963 | const char *opn = "ldst"; |
d66c7132 AJ |
964 | TCGv t0 = tcg_temp_new(); |
965 | TCGv t1 = tcg_temp_new(); | |
6af0bf9c FB |
966 | |
967 | if (base == 0) { | |
78723684 | 968 | tcg_gen_movi_tl(t0, offset); |
6af0bf9c | 969 | } else if (offset == 0) { |
78723684 | 970 | gen_load_gpr(t0, base); |
6af0bf9c | 971 | } else { |
e9203484 AJ |
972 | tcg_gen_movi_tl(t0, offset); |
973 | gen_op_addr_add(ctx, t0, cpu_gpr[base]); | |
6af0bf9c FB |
974 | } |
975 | /* Don't do NOP if destination is zero: we must perform the actual | |
ead9360e | 976 | memory access. */ |
6af0bf9c | 977 | switch (opc) { |
d26bc211 | 978 | #if defined(TARGET_MIPS64) |
6e473128 | 979 | case OPC_LWU: |
d66c7132 | 980 | save_cpu_state(ctx, 0); |
d9bea114 | 981 | op_ldst_lwu(t0, t0, ctx); |
78723684 | 982 | gen_store_gpr(t0, rt); |
6e473128 TS |
983 | opn = "lwu"; |
984 | break; | |
6af0bf9c | 985 | case OPC_LD: |
d66c7132 | 986 | save_cpu_state(ctx, 0); |
d9bea114 | 987 | op_ldst_ld(t0, t0, ctx); |
78723684 | 988 | gen_store_gpr(t0, rt); |
6af0bf9c FB |
989 | opn = "ld"; |
990 | break; | |
7a387fff | 991 | case OPC_LLD: |
d66c7132 | 992 | save_cpu_state(ctx, 0); |
d9bea114 | 993 | op_ldst_lld(t0, t0, ctx); |
78723684 | 994 | gen_store_gpr(t0, rt); |
7a387fff TS |
995 | opn = "lld"; |
996 | break; | |
6af0bf9c | 997 | case OPC_SD: |
d66c7132 | 998 | save_cpu_state(ctx, 0); |
78723684 | 999 | gen_load_gpr(t1, rt); |
d9bea114 | 1000 | op_ldst_sd(t1, t0, ctx); |
6af0bf9c FB |
1001 | opn = "sd"; |
1002 | break; | |
1003 | case OPC_LDL: | |
c8c2227e | 1004 | save_cpu_state(ctx, 1); |
78723684 | 1005 | gen_load_gpr(t1, rt); |
d9bea114 | 1006 | gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx); |
78723684 | 1007 | gen_store_gpr(t1, rt); |
6af0bf9c FB |
1008 | opn = "ldl"; |
1009 | break; | |
1010 | case OPC_SDL: | |
c8c2227e | 1011 | save_cpu_state(ctx, 1); |
78723684 | 1012 | gen_load_gpr(t1, rt); |
d9bea114 | 1013 | gen_helper_2i(sdl, t1, t0, ctx->mem_idx); |
6af0bf9c FB |
1014 | opn = "sdl"; |
1015 | break; | |
1016 | case OPC_LDR: | |
c8c2227e | 1017 | save_cpu_state(ctx, 1); |
78723684 | 1018 | gen_load_gpr(t1, rt); |
d9bea114 | 1019 | gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx); |
78723684 | 1020 | gen_store_gpr(t1, rt); |
6af0bf9c FB |
1021 | opn = "ldr"; |
1022 | break; | |
1023 | case OPC_SDR: | |
c8c2227e | 1024 | save_cpu_state(ctx, 1); |
78723684 | 1025 | gen_load_gpr(t1, rt); |
d9bea114 | 1026 | gen_helper_2i(sdr, t1, t0, ctx->mem_idx); |
6af0bf9c FB |
1027 | opn = "sdr"; |
1028 | break; | |
1029 | #endif | |
1030 | case OPC_LW: | |
d66c7132 | 1031 | save_cpu_state(ctx, 0); |
d9bea114 | 1032 | op_ldst_lw(t0, t0, ctx); |
78723684 | 1033 | gen_store_gpr(t0, rt); |
6af0bf9c FB |
1034 | opn = "lw"; |
1035 | break; | |
1036 | case OPC_SW: | |
d66c7132 | 1037 | save_cpu_state(ctx, 0); |
78723684 | 1038 | gen_load_gpr(t1, rt); |
d9bea114 | 1039 | op_ldst_sw(t1, t0, ctx); |
6af0bf9c FB |
1040 | opn = "sw"; |
1041 | break; | |
1042 | case OPC_LH: | |
d66c7132 | 1043 | save_cpu_state(ctx, 0); |
d9bea114 | 1044 | op_ldst_lh(t0, t0, ctx); |
78723684 | 1045 | gen_store_gpr(t0, rt); |
6af0bf9c FB |
1046 | opn = "lh"; |
1047 | break; | |
1048 | case OPC_SH: | |
d66c7132 | 1049 | save_cpu_state(ctx, 0); |
78723684 | 1050 | gen_load_gpr(t1, rt); |
d9bea114 | 1051 | op_ldst_sh(t1, t0, ctx); |
6af0bf9c FB |
1052 | opn = "sh"; |
1053 | break; | |
1054 | case OPC_LHU: | |
d66c7132 | 1055 | save_cpu_state(ctx, 0); |
d9bea114 | 1056 | op_ldst_lhu(t0, t0, ctx); |
78723684 | 1057 | gen_store_gpr(t0, rt); |
6af0bf9c FB |
1058 | opn = "lhu"; |
1059 | break; | |
1060 | case OPC_LB: | |
d66c7132 | 1061 | save_cpu_state(ctx, 0); |
d9bea114 | 1062 | op_ldst_lb(t0, t0, ctx); |
78723684 | 1063 | gen_store_gpr(t0, rt); |
6af0bf9c FB |
1064 | opn = "lb"; |
1065 | break; | |
1066 | case OPC_SB: | |
d66c7132 | 1067 | save_cpu_state(ctx, 0); |
78723684 | 1068 | gen_load_gpr(t1, rt); |
d9bea114 | 1069 | op_ldst_sb(t1, t0, ctx); |
6af0bf9c FB |
1070 | opn = "sb"; |
1071 | break; | |
1072 | case OPC_LBU: | |
d66c7132 | 1073 | save_cpu_state(ctx, 0); |
d9bea114 | 1074 | op_ldst_lbu(t0, t0, ctx); |
78723684 | 1075 | gen_store_gpr(t0, rt); |
6af0bf9c FB |
1076 | opn = "lbu"; |
1077 | break; | |
1078 | case OPC_LWL: | |
c8c2227e | 1079 | save_cpu_state(ctx, 1); |
6958549d | 1080 | gen_load_gpr(t1, rt); |
d9bea114 | 1081 | gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx); |
78723684 | 1082 | gen_store_gpr(t1, rt); |
6af0bf9c FB |
1083 | opn = "lwl"; |
1084 | break; | |
1085 | case OPC_SWL: | |
c8c2227e | 1086 | save_cpu_state(ctx, 1); |
78723684 | 1087 | gen_load_gpr(t1, rt); |
d9bea114 | 1088 | gen_helper_2i(swl, t1, t0, ctx->mem_idx); |
6af0bf9c FB |
1089 | opn = "swr"; |
1090 | break; | |
1091 | case OPC_LWR: | |
c8c2227e | 1092 | save_cpu_state(ctx, 1); |
6958549d | 1093 | gen_load_gpr(t1, rt); |
d9bea114 | 1094 | gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx); |
78723684 | 1095 | gen_store_gpr(t1, rt); |
6af0bf9c FB |
1096 | opn = "lwr"; |
1097 | break; | |
1098 | case OPC_SWR: | |
c8c2227e | 1099 | save_cpu_state(ctx, 1); |
78723684 | 1100 | gen_load_gpr(t1, rt); |
d9bea114 | 1101 | gen_helper_2i(swr, t1, t0, ctx->mem_idx); |
6af0bf9c FB |
1102 | opn = "swr"; |
1103 | break; | |
1104 | case OPC_LL: | |
d66c7132 | 1105 | save_cpu_state(ctx, 0); |
d9bea114 | 1106 | op_ldst_ll(t0, t0, ctx); |
78723684 | 1107 | gen_store_gpr(t0, rt); |
6af0bf9c FB |
1108 | opn = "ll"; |
1109 | break; | |
d66c7132 AJ |
1110 | } |
1111 | MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); | |
1112 | tcg_temp_free(t0); | |
1113 | tcg_temp_free(t1); | |
1114 | } | |
1115 | ||
1116 | /* Store conditional */ | |
1117 | static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, | |
1118 | int base, int16_t offset) | |
1119 | { | |
1120 | const char *opn = "st_cond"; | |
1121 | TCGv t0, t1; | |
1122 | ||
1123 | t0 = tcg_temp_local_new(); | |
1124 | ||
1125 | if (base == 0) { | |
1126 | tcg_gen_movi_tl(t0, offset); | |
1127 | } else if (offset == 0) { | |
1128 | gen_load_gpr(t0, base); | |
1129 | } else { | |
1130 | tcg_gen_movi_tl(t0, offset); | |
1131 | gen_op_addr_add(ctx, t0, cpu_gpr[base]); | |
1132 | } | |
1133 | /* Don't do NOP if destination is zero: we must perform the actual | |
1134 | memory access. */ | |
1135 | ||
1136 | t1 = tcg_temp_local_new(); | |
1137 | gen_load_gpr(t1, rt); | |
1138 | switch (opc) { | |
1139 | #if defined(TARGET_MIPS64) | |
1140 | case OPC_SCD: | |
1141 | save_cpu_state(ctx, 0); | |
d9bea114 | 1142 | op_ldst_scd(t0, t1, t0, ctx); |
d66c7132 AJ |
1143 | opn = "scd"; |
1144 | break; | |
1145 | #endif | |
6af0bf9c | 1146 | case OPC_SC: |
d66c7132 | 1147 | save_cpu_state(ctx, 0); |
d9bea114 | 1148 | op_ldst_sc(t0, t1, t0, ctx); |
6af0bf9c FB |
1149 | opn = "sc"; |
1150 | break; | |
6af0bf9c FB |
1151 | } |
1152 | MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); | |
78723684 | 1153 | tcg_temp_free(t1); |
d66c7132 AJ |
1154 | gen_store_gpr(t0, rt); |
1155 | tcg_temp_free(t0); | |
6af0bf9c FB |
1156 | } |
1157 | ||
6ea83fed | 1158 | /* Load and store */ |
7a387fff | 1159 | static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, |
356265ae | 1160 | int base, int16_t offset) |
6ea83fed | 1161 | { |
923617a3 | 1162 | const char *opn = "flt_ldst"; |
4e2474d6 | 1163 | TCGv t0 = tcg_temp_new(); |
6ea83fed FB |
1164 | |
1165 | if (base == 0) { | |
78723684 | 1166 | tcg_gen_movi_tl(t0, offset); |
6ea83fed | 1167 | } else if (offset == 0) { |
78723684 | 1168 | gen_load_gpr(t0, base); |
6ea83fed | 1169 | } else { |
e9203484 AJ |
1170 | tcg_gen_movi_tl(t0, offset); |
1171 | gen_op_addr_add(ctx, t0, cpu_gpr[base]); | |
6ea83fed FB |
1172 | } |
1173 | /* Don't do NOP if destination is zero: we must perform the actual | |
ead9360e | 1174 | memory access. */ |
6ea83fed FB |
1175 | switch (opc) { |
1176 | case OPC_LWC1: | |
b6d96bed | 1177 | { |
a7812ae4 | 1178 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed | 1179 | |
c407df81 AJ |
1180 | tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); |
1181 | tcg_gen_trunc_tl_i32(fp0, t0); | |
b6d96bed | 1182 | gen_store_fpr32(fp0, ft); |
a7812ae4 | 1183 | tcg_temp_free_i32(fp0); |
b6d96bed | 1184 | } |
6ea83fed FB |
1185 | opn = "lwc1"; |
1186 | break; | |
1187 | case OPC_SWC1: | |
b6d96bed | 1188 | { |
a7812ae4 PB |
1189 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
1190 | TCGv t1 = tcg_temp_new(); | |
b6d96bed TS |
1191 | |
1192 | gen_load_fpr32(fp0, ft); | |
a7812ae4 PB |
1193 | tcg_gen_extu_i32_tl(t1, fp0); |
1194 | tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); | |
1195 | tcg_temp_free(t1); | |
1196 | tcg_temp_free_i32(fp0); | |
b6d96bed | 1197 | } |
6ea83fed FB |
1198 | opn = "swc1"; |
1199 | break; | |
1200 | case OPC_LDC1: | |
b6d96bed | 1201 | { |
a7812ae4 | 1202 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
1203 | |
1204 | tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); | |
1205 | gen_store_fpr64(ctx, fp0, ft); | |
a7812ae4 | 1206 | tcg_temp_free_i64(fp0); |
b6d96bed | 1207 | } |
6ea83fed FB |
1208 | opn = "ldc1"; |
1209 | break; | |
1210 | case OPC_SDC1: | |
b6d96bed | 1211 | { |
a7812ae4 | 1212 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
1213 | |
1214 | gen_load_fpr64(ctx, fp0, ft); | |
1215 | tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); | |
a7812ae4 | 1216 | tcg_temp_free_i64(fp0); |
b6d96bed | 1217 | } |
6ea83fed FB |
1218 | opn = "sdc1"; |
1219 | break; | |
1220 | default: | |
923617a3 | 1221 | MIPS_INVAL(opn); |
e397ee33 | 1222 | generate_exception(ctx, EXCP_RI); |
78723684 | 1223 | goto out; |
6ea83fed FB |
1224 | } |
1225 | MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]); | |
78723684 TS |
1226 | out: |
1227 | tcg_temp_free(t0); | |
6ea83fed | 1228 | } |
6ea83fed | 1229 | |
6af0bf9c | 1230 | /* Arithmetic with immediate operand */ |
e189e748 TS |
1231 | static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, |
1232 | int rt, int rs, int16_t imm) | |
6af0bf9c | 1233 | { |
324d9e32 | 1234 | target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ |
923617a3 | 1235 | const char *opn = "imm arith"; |
6af0bf9c | 1236 | |
7a387fff | 1237 | if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { |
ead9360e TS |
1238 | /* If no destination, treat it as a NOP. |
1239 | For addi, we must generate the overflow exception when needed. */ | |
6af0bf9c | 1240 | MIPS_DEBUG("NOP"); |
324d9e32 | 1241 | return; |
6af0bf9c FB |
1242 | } |
1243 | switch (opc) { | |
1244 | case OPC_ADDI: | |
48d38ca5 | 1245 | { |
324d9e32 AJ |
1246 | TCGv t0 = tcg_temp_local_new(); |
1247 | TCGv t1 = tcg_temp_new(); | |
1248 | TCGv t2 = tcg_temp_new(); | |
48d38ca5 TS |
1249 | int l1 = gen_new_label(); |
1250 | ||
324d9e32 AJ |
1251 | gen_load_gpr(t1, rs); |
1252 | tcg_gen_addi_tl(t0, t1, uimm); | |
1253 | tcg_gen_ext32s_tl(t0, t0); | |
48d38ca5 | 1254 | |
324d9e32 AJ |
1255 | tcg_gen_xori_tl(t1, t1, ~uimm); |
1256 | tcg_gen_xori_tl(t2, t0, uimm); | |
1257 | tcg_gen_and_tl(t1, t1, t2); | |
1258 | tcg_temp_free(t2); | |
1259 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
1260 | tcg_temp_free(t1); | |
48d38ca5 TS |
1261 | /* operands of same sign, result different sign */ |
1262 | generate_exception(ctx, EXCP_OVERFLOW); | |
1263 | gen_set_label(l1); | |
78723684 | 1264 | tcg_gen_ext32s_tl(t0, t0); |
324d9e32 AJ |
1265 | gen_store_gpr(t0, rt); |
1266 | tcg_temp_free(t0); | |
48d38ca5 | 1267 | } |
6af0bf9c FB |
1268 | opn = "addi"; |
1269 | break; | |
1270 | case OPC_ADDIU: | |
324d9e32 AJ |
1271 | if (rs != 0) { |
1272 | tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); | |
1273 | tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); | |
1274 | } else { | |
1275 | tcg_gen_movi_tl(cpu_gpr[rt], uimm); | |
1276 | } | |
6af0bf9c FB |
1277 | opn = "addiu"; |
1278 | break; | |
d26bc211 | 1279 | #if defined(TARGET_MIPS64) |
7a387fff | 1280 | case OPC_DADDI: |
48d38ca5 | 1281 | { |
324d9e32 AJ |
1282 | TCGv t0 = tcg_temp_local_new(); |
1283 | TCGv t1 = tcg_temp_new(); | |
1284 | TCGv t2 = tcg_temp_new(); | |
48d38ca5 TS |
1285 | int l1 = gen_new_label(); |
1286 | ||
324d9e32 AJ |
1287 | gen_load_gpr(t1, rs); |
1288 | tcg_gen_addi_tl(t0, t1, uimm); | |
48d38ca5 | 1289 | |
324d9e32 AJ |
1290 | tcg_gen_xori_tl(t1, t1, ~uimm); |
1291 | tcg_gen_xori_tl(t2, t0, uimm); | |
1292 | tcg_gen_and_tl(t1, t1, t2); | |
1293 | tcg_temp_free(t2); | |
1294 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
1295 | tcg_temp_free(t1); | |
48d38ca5 TS |
1296 | /* operands of same sign, result different sign */ |
1297 | generate_exception(ctx, EXCP_OVERFLOW); | |
1298 | gen_set_label(l1); | |
324d9e32 AJ |
1299 | gen_store_gpr(t0, rt); |
1300 | tcg_temp_free(t0); | |
48d38ca5 | 1301 | } |
7a387fff TS |
1302 | opn = "daddi"; |
1303 | break; | |
1304 | case OPC_DADDIU: | |
324d9e32 AJ |
1305 | if (rs != 0) { |
1306 | tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); | |
1307 | } else { | |
1308 | tcg_gen_movi_tl(cpu_gpr[rt], uimm); | |
1309 | } | |
7a387fff TS |
1310 | opn = "daddiu"; |
1311 | break; | |
1312 | #endif | |
324d9e32 AJ |
1313 | } |
1314 | MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); | |
1315 | } | |
1316 | ||
1317 | /* Logic with immediate operand */ | |
1318 | static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm) | |
1319 | { | |
1320 | target_ulong uimm; | |
1321 | const char *opn = "imm logic"; | |
1322 | ||
1323 | if (rt == 0) { | |
1324 | /* If no destination, treat it as a NOP. */ | |
1325 | MIPS_DEBUG("NOP"); | |
1326 | return; | |
1327 | } | |
1328 | uimm = (uint16_t)imm; | |
1329 | switch (opc) { | |
6af0bf9c | 1330 | case OPC_ANDI: |
324d9e32 AJ |
1331 | if (likely(rs != 0)) |
1332 | tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); | |
1333 | else | |
1334 | tcg_gen_movi_tl(cpu_gpr[rt], 0); | |
6af0bf9c FB |
1335 | opn = "andi"; |
1336 | break; | |
1337 | case OPC_ORI: | |
324d9e32 AJ |
1338 | if (rs != 0) |
1339 | tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); | |
1340 | else | |
1341 | tcg_gen_movi_tl(cpu_gpr[rt], uimm); | |
6af0bf9c FB |
1342 | opn = "ori"; |
1343 | break; | |
1344 | case OPC_XORI: | |
324d9e32 AJ |
1345 | if (likely(rs != 0)) |
1346 | tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); | |
1347 | else | |
1348 | tcg_gen_movi_tl(cpu_gpr[rt], uimm); | |
6af0bf9c FB |
1349 | opn = "xori"; |
1350 | break; | |
1351 | case OPC_LUI: | |
324d9e32 | 1352 | tcg_gen_movi_tl(cpu_gpr[rt], imm << 16); |
6af0bf9c FB |
1353 | opn = "lui"; |
1354 | break; | |
324d9e32 AJ |
1355 | } |
1356 | MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); | |
1357 | } | |
1358 | ||
1359 | /* Set on less than with immediate operand */ | |
1360 | static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm) | |
1361 | { | |
1362 | target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ | |
1363 | const char *opn = "imm arith"; | |
1364 | TCGv t0; | |
1365 | ||
1366 | if (rt == 0) { | |
1367 | /* If no destination, treat it as a NOP. */ | |
1368 | MIPS_DEBUG("NOP"); | |
1369 | return; | |
1370 | } | |
1371 | t0 = tcg_temp_new(); | |
1372 | gen_load_gpr(t0, rs); | |
1373 | switch (opc) { | |
1374 | case OPC_SLTI: | |
1375 | gen_op_lti(cpu_gpr[rt], t0, uimm); | |
1376 | opn = "slti"; | |
1377 | break; | |
1378 | case OPC_SLTIU: | |
1379 | gen_op_ltiu(cpu_gpr[rt], t0, uimm); | |
1380 | opn = "sltiu"; | |
1381 | break; | |
1382 | } | |
1383 | MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); | |
1384 | tcg_temp_free(t0); | |
1385 | } | |
1386 | ||
1387 | /* Shifts with immediate operand */ | |
1388 | static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc, | |
1389 | int rt, int rs, int16_t imm) | |
1390 | { | |
1391 | target_ulong uimm = ((uint16_t)imm) & 0x1f; | |
1392 | const char *opn = "imm shift"; | |
1393 | TCGv t0; | |
1394 | ||
1395 | if (rt == 0) { | |
1396 | /* If no destination, treat it as a NOP. */ | |
1397 | MIPS_DEBUG("NOP"); | |
1398 | return; | |
1399 | } | |
1400 | ||
1401 | t0 = tcg_temp_new(); | |
1402 | gen_load_gpr(t0, rs); | |
1403 | switch (opc) { | |
6af0bf9c | 1404 | case OPC_SLL: |
78723684 | 1405 | tcg_gen_shli_tl(t0, t0, uimm); |
324d9e32 | 1406 | tcg_gen_ext32s_tl(cpu_gpr[rt], t0); |
6af0bf9c FB |
1407 | opn = "sll"; |
1408 | break; | |
1409 | case OPC_SRA: | |
78723684 | 1410 | tcg_gen_ext32s_tl(t0, t0); |
324d9e32 | 1411 | tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); |
6af0bf9c FB |
1412 | opn = "sra"; |
1413 | break; | |
1414 | case OPC_SRL: | |
5a63bcb2 TS |
1415 | switch ((ctx->opcode >> 21) & 0x1f) { |
1416 | case 0: | |
507563e8 AJ |
1417 | if (uimm != 0) { |
1418 | tcg_gen_ext32u_tl(t0, t0); | |
324d9e32 | 1419 | tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); |
507563e8 | 1420 | } else { |
324d9e32 | 1421 | tcg_gen_ext32s_tl(cpu_gpr[rt], t0); |
507563e8 | 1422 | } |
7a387fff | 1423 | opn = "srl"; |
5a63bcb2 TS |
1424 | break; |
1425 | case 1: | |
e189e748 TS |
1426 | /* rotr is decoded as srl on non-R2 CPUs */ |
1427 | if (env->insn_flags & ISA_MIPS32R2) { | |
48d38ca5 | 1428 | if (uimm != 0) { |
d9bea114 | 1429 | TCGv_i32 t1 = tcg_temp_new_i32(); |
48d38ca5 | 1430 | |
d9bea114 AJ |
1431 | tcg_gen_trunc_tl_i32(t1, t0); |
1432 | tcg_gen_rotri_i32(t1, t1, uimm); | |
1433 | tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); | |
1434 | tcg_temp_free_i32(t1); | |
48d38ca5 | 1435 | } |
e189e748 TS |
1436 | opn = "rotr"; |
1437 | } else { | |
507563e8 AJ |
1438 | if (uimm != 0) { |
1439 | tcg_gen_ext32u_tl(t0, t0); | |
324d9e32 | 1440 | tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); |
507563e8 | 1441 | } else { |
324d9e32 | 1442 | tcg_gen_ext32s_tl(cpu_gpr[rt], t0); |
507563e8 | 1443 | } |
e189e748 TS |
1444 | opn = "srl"; |
1445 | } | |
5a63bcb2 TS |
1446 | break; |
1447 | default: | |
1448 | MIPS_INVAL("invalid srl flag"); | |
1449 | generate_exception(ctx, EXCP_RI); | |
1450 | break; | |
1451 | } | |
7a387fff | 1452 | break; |
d26bc211 | 1453 | #if defined(TARGET_MIPS64) |
7a387fff | 1454 | case OPC_DSLL: |
324d9e32 | 1455 | tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm); |
7a387fff TS |
1456 | opn = "dsll"; |
1457 | break; | |
1458 | case OPC_DSRA: | |
324d9e32 | 1459 | tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); |
7a387fff TS |
1460 | opn = "dsra"; |
1461 | break; | |
1462 | case OPC_DSRL: | |
5a63bcb2 TS |
1463 | switch ((ctx->opcode >> 21) & 0x1f) { |
1464 | case 0: | |
324d9e32 | 1465 | tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); |
7a387fff | 1466 | opn = "dsrl"; |
5a63bcb2 TS |
1467 | break; |
1468 | case 1: | |
e189e748 TS |
1469 | /* drotr is decoded as dsrl on non-R2 CPUs */ |
1470 | if (env->insn_flags & ISA_MIPS32R2) { | |
48d38ca5 | 1471 | if (uimm != 0) { |
324d9e32 | 1472 | tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm); |
48d38ca5 | 1473 | } |
e189e748 TS |
1474 | opn = "drotr"; |
1475 | } else { | |
324d9e32 | 1476 | tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); |
e189e748 TS |
1477 | opn = "dsrl"; |
1478 | } | |
5a63bcb2 TS |
1479 | break; |
1480 | default: | |
1481 | MIPS_INVAL("invalid dsrl flag"); | |
1482 | generate_exception(ctx, EXCP_RI); | |
1483 | break; | |
1484 | } | |
7a387fff TS |
1485 | break; |
1486 | case OPC_DSLL32: | |
324d9e32 | 1487 | tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32); |
7a387fff TS |
1488 | opn = "dsll32"; |
1489 | break; | |
1490 | case OPC_DSRA32: | |
324d9e32 | 1491 | tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32); |
7a387fff TS |
1492 | opn = "dsra32"; |
1493 | break; | |
1494 | case OPC_DSRL32: | |
5a63bcb2 TS |
1495 | switch ((ctx->opcode >> 21) & 0x1f) { |
1496 | case 0: | |
324d9e32 | 1497 | tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); |
7a387fff | 1498 | opn = "dsrl32"; |
5a63bcb2 TS |
1499 | break; |
1500 | case 1: | |
e189e748 TS |
1501 | /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ |
1502 | if (env->insn_flags & ISA_MIPS32R2) { | |
324d9e32 | 1503 | tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32); |
e189e748 TS |
1504 | opn = "drotr32"; |
1505 | } else { | |
324d9e32 | 1506 | tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); |
e189e748 TS |
1507 | opn = "dsrl32"; |
1508 | } | |
5a63bcb2 TS |
1509 | break; |
1510 | default: | |
1511 | MIPS_INVAL("invalid dsrl32 flag"); | |
1512 | generate_exception(ctx, EXCP_RI); | |
1513 | break; | |
1514 | } | |
6af0bf9c | 1515 | break; |
7a387fff | 1516 | #endif |
6af0bf9c | 1517 | } |
93b12ccc | 1518 | MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); |
78723684 | 1519 | tcg_temp_free(t0); |
6af0bf9c FB |
1520 | } |
1521 | ||
1522 | /* Arithmetic */ | |
e189e748 | 1523 | static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, |
6af0bf9c FB |
1524 | int rd, int rs, int rt) |
1525 | { | |
923617a3 | 1526 | const char *opn = "arith"; |
6af0bf9c | 1527 | |
7a387fff TS |
1528 | if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB |
1529 | && opc != OPC_DADD && opc != OPC_DSUB) { | |
ead9360e TS |
1530 | /* If no destination, treat it as a NOP. |
1531 | For add & sub, we must generate the overflow exception when needed. */ | |
6af0bf9c | 1532 | MIPS_DEBUG("NOP"); |
460f00c4 | 1533 | return; |
185f0762 | 1534 | } |
460f00c4 | 1535 | |
6af0bf9c FB |
1536 | switch (opc) { |
1537 | case OPC_ADD: | |
48d38ca5 | 1538 | { |
460f00c4 AJ |
1539 | TCGv t0 = tcg_temp_local_new(); |
1540 | TCGv t1 = tcg_temp_new(); | |
1541 | TCGv t2 = tcg_temp_new(); | |
48d38ca5 TS |
1542 | int l1 = gen_new_label(); |
1543 | ||
460f00c4 AJ |
1544 | gen_load_gpr(t1, rs); |
1545 | gen_load_gpr(t2, rt); | |
1546 | tcg_gen_add_tl(t0, t1, t2); | |
1547 | tcg_gen_ext32s_tl(t0, t0); | |
1548 | tcg_gen_xor_tl(t1, t1, t2); | |
1549 | tcg_gen_not_tl(t1, t1); | |
1550 | tcg_gen_xor_tl(t2, t0, t2); | |
1551 | tcg_gen_and_tl(t1, t1, t2); | |
1552 | tcg_temp_free(t2); | |
1553 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
1554 | tcg_temp_free(t1); | |
48d38ca5 TS |
1555 | /* operands of same sign, result different sign */ |
1556 | generate_exception(ctx, EXCP_OVERFLOW); | |
1557 | gen_set_label(l1); | |
460f00c4 AJ |
1558 | gen_store_gpr(t0, rd); |
1559 | tcg_temp_free(t0); | |
48d38ca5 | 1560 | } |
6af0bf9c FB |
1561 | opn = "add"; |
1562 | break; | |
1563 | case OPC_ADDU: | |
460f00c4 AJ |
1564 | if (rs != 0 && rt != 0) { |
1565 | tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); | |
1566 | tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); | |
1567 | } else if (rs == 0 && rt != 0) { | |
1568 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); | |
1569 | } else if (rs != 0 && rt == 0) { | |
1570 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); | |
1571 | } else { | |
1572 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
1573 | } | |
6af0bf9c FB |
1574 | opn = "addu"; |
1575 | break; | |
1576 | case OPC_SUB: | |
48d38ca5 | 1577 | { |
460f00c4 AJ |
1578 | TCGv t0 = tcg_temp_local_new(); |
1579 | TCGv t1 = tcg_temp_new(); | |
1580 | TCGv t2 = tcg_temp_new(); | |
48d38ca5 TS |
1581 | int l1 = gen_new_label(); |
1582 | ||
460f00c4 AJ |
1583 | gen_load_gpr(t1, rs); |
1584 | gen_load_gpr(t2, rt); | |
1585 | tcg_gen_sub_tl(t0, t1, t2); | |
1586 | tcg_gen_ext32s_tl(t0, t0); | |
1587 | tcg_gen_xor_tl(t2, t1, t2); | |
1588 | tcg_gen_xor_tl(t1, t0, t1); | |
1589 | tcg_gen_and_tl(t1, t1, t2); | |
1590 | tcg_temp_free(t2); | |
1591 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
1592 | tcg_temp_free(t1); | |
88cbb980 | 1593 | /* operands of different sign, first operand and result different sign */ |
48d38ca5 TS |
1594 | generate_exception(ctx, EXCP_OVERFLOW); |
1595 | gen_set_label(l1); | |
460f00c4 AJ |
1596 | gen_store_gpr(t0, rd); |
1597 | tcg_temp_free(t0); | |
48d38ca5 | 1598 | } |
6af0bf9c FB |
1599 | opn = "sub"; |
1600 | break; | |
1601 | case OPC_SUBU: | |
460f00c4 AJ |
1602 | if (rs != 0 && rt != 0) { |
1603 | tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); | |
1604 | tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); | |
1605 | } else if (rs == 0 && rt != 0) { | |
1606 | tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); | |
6bb72b18 | 1607 | tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); |
460f00c4 AJ |
1608 | } else if (rs != 0 && rt == 0) { |
1609 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); | |
1610 | } else { | |
1611 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
1612 | } | |
6af0bf9c FB |
1613 | opn = "subu"; |
1614 | break; | |
d26bc211 | 1615 | #if defined(TARGET_MIPS64) |
7a387fff | 1616 | case OPC_DADD: |
48d38ca5 | 1617 | { |
460f00c4 AJ |
1618 | TCGv t0 = tcg_temp_local_new(); |
1619 | TCGv t1 = tcg_temp_new(); | |
1620 | TCGv t2 = tcg_temp_new(); | |
48d38ca5 TS |
1621 | int l1 = gen_new_label(); |
1622 | ||
460f00c4 AJ |
1623 | gen_load_gpr(t1, rs); |
1624 | gen_load_gpr(t2, rt); | |
1625 | tcg_gen_add_tl(t0, t1, t2); | |
1626 | tcg_gen_xor_tl(t1, t1, t2); | |
1627 | tcg_gen_not_tl(t1, t1); | |
1628 | tcg_gen_xor_tl(t2, t0, t2); | |
1629 | tcg_gen_and_tl(t1, t1, t2); | |
1630 | tcg_temp_free(t2); | |
1631 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
1632 | tcg_temp_free(t1); | |
48d38ca5 TS |
1633 | /* operands of same sign, result different sign */ |
1634 | generate_exception(ctx, EXCP_OVERFLOW); | |
1635 | gen_set_label(l1); | |
460f00c4 AJ |
1636 | gen_store_gpr(t0, rd); |
1637 | tcg_temp_free(t0); | |
48d38ca5 | 1638 | } |
7a387fff TS |
1639 | opn = "dadd"; |
1640 | break; | |
1641 | case OPC_DADDU: | |
460f00c4 AJ |
1642 | if (rs != 0 && rt != 0) { |
1643 | tcg_gen_add_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); | |
1644 | } else if (rs == 0 && rt != 0) { | |
1645 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); | |
1646 | } else if (rs != 0 && rt == 0) { | |
1647 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); | |
1648 | } else { | |
1649 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
1650 | } | |
7a387fff TS |
1651 | opn = "daddu"; |
1652 | break; | |
1653 | case OPC_DSUB: | |
48d38ca5 | 1654 | { |
460f00c4 AJ |
1655 | TCGv t0 = tcg_temp_local_new(); |
1656 | TCGv t1 = tcg_temp_new(); | |
1657 | TCGv t2 = tcg_temp_new(); | |
48d38ca5 TS |
1658 | int l1 = gen_new_label(); |
1659 | ||
460f00c4 AJ |
1660 | gen_load_gpr(t1, rs); |
1661 | gen_load_gpr(t2, rt); | |
1662 | tcg_gen_sub_tl(t0, t1, t2); | |
1663 | tcg_gen_xor_tl(t2, t1, t2); | |
1664 | tcg_gen_xor_tl(t1, t0, t1); | |
1665 | tcg_gen_and_tl(t1, t1, t2); | |
1666 | tcg_temp_free(t2); | |
1667 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
1668 | tcg_temp_free(t1); | |
88cbb980 | 1669 | /* operands of different sign, first operand and result different sign */ |
48d38ca5 TS |
1670 | generate_exception(ctx, EXCP_OVERFLOW); |
1671 | gen_set_label(l1); | |
460f00c4 AJ |
1672 | gen_store_gpr(t0, rd); |
1673 | tcg_temp_free(t0); | |
48d38ca5 | 1674 | } |
7a387fff TS |
1675 | opn = "dsub"; |
1676 | break; | |
1677 | case OPC_DSUBU: | |
460f00c4 AJ |
1678 | if (rs != 0 && rt != 0) { |
1679 | tcg_gen_sub_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); | |
1680 | } else if (rs == 0 && rt != 0) { | |
1681 | tcg_gen_neg_tl(cpu_gpr[rd], cpu_gpr[rt]); | |
1682 | } else if (rs != 0 && rt == 0) { | |
1683 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); | |
1684 | } else { | |
1685 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
1686 | } | |
7a387fff TS |
1687 | opn = "dsubu"; |
1688 | break; | |
1689 | #endif | |
460f00c4 AJ |
1690 | case OPC_MUL: |
1691 | if (likely(rs != 0 && rt != 0)) { | |
1692 | tcg_gen_mul_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); | |
1693 | tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); | |
1694 | } else { | |
1695 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
1696 | } | |
1697 | opn = "mul"; | |
6af0bf9c | 1698 | break; |
460f00c4 AJ |
1699 | } |
1700 | MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); | |
1701 | } | |
1702 | ||
1703 | /* Conditional move */ | |
1704 | static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt) | |
1705 | { | |
1706 | const char *opn = "cond move"; | |
1707 | int l1; | |
1708 | ||
1709 | if (rd == 0) { | |
1710 | /* If no destination, treat it as a NOP. | |
1711 | For add & sub, we must generate the overflow exception when needed. */ | |
1712 | MIPS_DEBUG("NOP"); | |
1713 | return; | |
1714 | } | |
1715 | ||
1716 | l1 = gen_new_label(); | |
1717 | switch (opc) { | |
1718 | case OPC_MOVN: | |
1719 | if (likely(rt != 0)) | |
1720 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rt], 0, l1); | |
1721 | else | |
1722 | tcg_gen_br(l1); | |
1723 | opn = "movn"; | |
6af0bf9c | 1724 | break; |
460f00c4 AJ |
1725 | case OPC_MOVZ: |
1726 | if (likely(rt != 0)) | |
1727 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rt], 0, l1); | |
1728 | opn = "movz"; | |
1729 | break; | |
1730 | } | |
1731 | if (rs != 0) | |
1732 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); | |
1733 | else | |
1734 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
1735 | gen_set_label(l1); | |
1736 | ||
1737 | MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); | |
1738 | } | |
1739 | ||
1740 | /* Logic */ | |
1741 | static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt) | |
1742 | { | |
1743 | const char *opn = "logic"; | |
1744 | ||
1745 | if (rd == 0) { | |
1746 | /* If no destination, treat it as a NOP. */ | |
1747 | MIPS_DEBUG("NOP"); | |
1748 | return; | |
1749 | } | |
1750 | ||
1751 | switch (opc) { | |
6af0bf9c | 1752 | case OPC_AND: |
460f00c4 AJ |
1753 | if (likely(rs != 0 && rt != 0)) { |
1754 | tcg_gen_and_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); | |
1755 | } else { | |
1756 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
1757 | } | |
6af0bf9c FB |
1758 | opn = "and"; |
1759 | break; | |
1760 | case OPC_NOR: | |
460f00c4 AJ |
1761 | if (rs != 0 && rt != 0) { |
1762 | tcg_gen_nor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); | |
1763 | } else if (rs == 0 && rt != 0) { | |
1764 | tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rt]); | |
1765 | } else if (rs != 0 && rt == 0) { | |
1766 | tcg_gen_not_tl(cpu_gpr[rd], cpu_gpr[rs]); | |
1767 | } else { | |
1768 | tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0)); | |
1769 | } | |
6af0bf9c FB |
1770 | opn = "nor"; |
1771 | break; | |
1772 | case OPC_OR: | |
460f00c4 AJ |
1773 | if (likely(rs != 0 && rt != 0)) { |
1774 | tcg_gen_or_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); | |
1775 | } else if (rs == 0 && rt != 0) { | |
1776 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); | |
1777 | } else if (rs != 0 && rt == 0) { | |
1778 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); | |
1779 | } else { | |
1780 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
1781 | } | |
6af0bf9c FB |
1782 | opn = "or"; |
1783 | break; | |
1784 | case OPC_XOR: | |
460f00c4 AJ |
1785 | if (likely(rs != 0 && rt != 0)) { |
1786 | tcg_gen_xor_tl(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]); | |
1787 | } else if (rs == 0 && rt != 0) { | |
1788 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rt]); | |
1789 | } else if (rs != 0 && rt == 0) { | |
1790 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); | |
1791 | } else { | |
1792 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
1793 | } | |
6af0bf9c FB |
1794 | opn = "xor"; |
1795 | break; | |
460f00c4 AJ |
1796 | } |
1797 | MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); | |
1798 | } | |
1799 | ||
1800 | /* Set on lower than */ | |
1801 | static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt) | |
1802 | { | |
1803 | const char *opn = "slt"; | |
1804 | TCGv t0, t1; | |
1805 | ||
1806 | if (rd == 0) { | |
1807 | /* If no destination, treat it as a NOP. */ | |
1808 | MIPS_DEBUG("NOP"); | |
1809 | return; | |
1810 | } | |
1811 | ||
1812 | t0 = tcg_temp_new(); | |
1813 | t1 = tcg_temp_new(); | |
1814 | gen_load_gpr(t0, rs); | |
1815 | gen_load_gpr(t1, rt); | |
1816 | switch (opc) { | |
1817 | case OPC_SLT: | |
1818 | gen_op_lt(cpu_gpr[rd], t0, t1); | |
1819 | opn = "slt"; | |
6af0bf9c | 1820 | break; |
460f00c4 AJ |
1821 | case OPC_SLTU: |
1822 | gen_op_ltu(cpu_gpr[rd], t0, t1); | |
1823 | opn = "sltu"; | |
1824 | break; | |
1825 | } | |
1826 | MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); | |
1827 | tcg_temp_free(t0); | |
1828 | tcg_temp_free(t1); | |
1829 | } | |
20c4c97c | 1830 | |
460f00c4 AJ |
1831 | /* Shifts */ |
1832 | static void gen_shift (CPUState *env, DisasContext *ctx, uint32_t opc, | |
1833 | int rd, int rs, int rt) | |
1834 | { | |
1835 | const char *opn = "shifts"; | |
1836 | TCGv t0, t1; | |
20c4c97c | 1837 | |
460f00c4 AJ |
1838 | if (rd == 0) { |
1839 | /* If no destination, treat it as a NOP. | |
1840 | For add & sub, we must generate the overflow exception when needed. */ | |
1841 | MIPS_DEBUG("NOP"); | |
1842 | return; | |
1843 | } | |
1844 | ||
1845 | t0 = tcg_temp_new(); | |
1846 | t1 = tcg_temp_new(); | |
1847 | gen_load_gpr(t0, rs); | |
1848 | gen_load_gpr(t1, rt); | |
1849 | switch (opc) { | |
6af0bf9c | 1850 | case OPC_SLLV: |
78723684 TS |
1851 | tcg_gen_andi_tl(t0, t0, 0x1f); |
1852 | tcg_gen_shl_tl(t0, t1, t0); | |
460f00c4 | 1853 | tcg_gen_ext32s_tl(cpu_gpr[rd], t0); |
6af0bf9c FB |
1854 | opn = "sllv"; |
1855 | break; | |
1856 | case OPC_SRAV: | |
78723684 TS |
1857 | tcg_gen_ext32s_tl(t1, t1); |
1858 | tcg_gen_andi_tl(t0, t0, 0x1f); | |
460f00c4 | 1859 | tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); |
6af0bf9c FB |
1860 | opn = "srav"; |
1861 | break; | |
1862 | case OPC_SRLV: | |
5a63bcb2 TS |
1863 | switch ((ctx->opcode >> 6) & 0x1f) { |
1864 | case 0: | |
78723684 TS |
1865 | tcg_gen_ext32u_tl(t1, t1); |
1866 | tcg_gen_andi_tl(t0, t0, 0x1f); | |
1867 | tcg_gen_shr_tl(t0, t1, t0); | |
460f00c4 | 1868 | tcg_gen_ext32s_tl(cpu_gpr[rd], t0); |
7a387fff | 1869 | opn = "srlv"; |
5a63bcb2 TS |
1870 | break; |
1871 | case 1: | |
e189e748 TS |
1872 | /* rotrv is decoded as srlv on non-R2 CPUs */ |
1873 | if (env->insn_flags & ISA_MIPS32R2) { | |
460f00c4 AJ |
1874 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1875 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1876 | ||
1877 | tcg_gen_trunc_tl_i32(t2, t0); | |
1878 | tcg_gen_trunc_tl_i32(t3, t1); | |
1879 | tcg_gen_andi_i32(t2, t2, 0x1f); | |
1880 | tcg_gen_rotr_i32(t2, t3, t2); | |
1881 | tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); | |
1882 | tcg_temp_free_i32(t2); | |
1883 | tcg_temp_free_i32(t3); | |
e189e748 TS |
1884 | opn = "rotrv"; |
1885 | } else { | |
78723684 TS |
1886 | tcg_gen_ext32u_tl(t1, t1); |
1887 | tcg_gen_andi_tl(t0, t0, 0x1f); | |
1888 | tcg_gen_shr_tl(t0, t1, t0); | |
460f00c4 | 1889 | tcg_gen_ext32s_tl(cpu_gpr[rd], t0); |
e189e748 TS |
1890 | opn = "srlv"; |
1891 | } | |
5a63bcb2 TS |
1892 | break; |
1893 | default: | |
1894 | MIPS_INVAL("invalid srlv flag"); | |
1895 | generate_exception(ctx, EXCP_RI); | |
1896 | break; | |
1897 | } | |
7a387fff | 1898 | break; |
d26bc211 | 1899 | #if defined(TARGET_MIPS64) |
7a387fff | 1900 | case OPC_DSLLV: |
78723684 | 1901 | tcg_gen_andi_tl(t0, t0, 0x3f); |
460f00c4 | 1902 | tcg_gen_shl_tl(cpu_gpr[rd], t1, t0); |
7a387fff TS |
1903 | opn = "dsllv"; |
1904 | break; | |
1905 | case OPC_DSRAV: | |
78723684 | 1906 | tcg_gen_andi_tl(t0, t0, 0x3f); |
460f00c4 | 1907 | tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); |
7a387fff TS |
1908 | opn = "dsrav"; |
1909 | break; | |
1910 | case OPC_DSRLV: | |
5a63bcb2 TS |
1911 | switch ((ctx->opcode >> 6) & 0x1f) { |
1912 | case 0: | |
78723684 | 1913 | tcg_gen_andi_tl(t0, t0, 0x3f); |
460f00c4 | 1914 | tcg_gen_shr_tl(cpu_gpr[rd], t1, t0); |
7a387fff | 1915 | opn = "dsrlv"; |
5a63bcb2 TS |
1916 | break; |
1917 | case 1: | |
e189e748 TS |
1918 | /* drotrv is decoded as dsrlv on non-R2 CPUs */ |
1919 | if (env->insn_flags & ISA_MIPS32R2) { | |
78723684 | 1920 | tcg_gen_andi_tl(t0, t0, 0x3f); |
460f00c4 | 1921 | tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0); |
e189e748 TS |
1922 | opn = "drotrv"; |
1923 | } else { | |
78723684 TS |
1924 | tcg_gen_andi_tl(t0, t0, 0x3f); |
1925 | tcg_gen_shr_tl(t0, t1, t0); | |
e189e748 TS |
1926 | opn = "dsrlv"; |
1927 | } | |
5a63bcb2 TS |
1928 | break; |
1929 | default: | |
1930 | MIPS_INVAL("invalid dsrlv flag"); | |
1931 | generate_exception(ctx, EXCP_RI); | |
1932 | break; | |
1933 | } | |
6af0bf9c | 1934 | break; |
7a387fff | 1935 | #endif |
6af0bf9c | 1936 | } |
6af0bf9c | 1937 | MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); |
78723684 TS |
1938 | tcg_temp_free(t0); |
1939 | tcg_temp_free(t1); | |
6af0bf9c FB |
1940 | } |
1941 | ||
1942 | /* Arithmetic on HI/LO registers */ | |
7a387fff | 1943 | static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) |
6af0bf9c | 1944 | { |
923617a3 | 1945 | const char *opn = "hilo"; |
6af0bf9c FB |
1946 | |
1947 | if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { | |
ead9360e | 1948 | /* Treat as NOP. */ |
6af0bf9c | 1949 | MIPS_DEBUG("NOP"); |
a1f6684d | 1950 | return; |
6af0bf9c FB |
1951 | } |
1952 | switch (opc) { | |
1953 | case OPC_MFHI: | |
a1f6684d | 1954 | tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]); |
6af0bf9c FB |
1955 | opn = "mfhi"; |
1956 | break; | |
1957 | case OPC_MFLO: | |
a1f6684d | 1958 | tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]); |
6af0bf9c FB |
1959 | opn = "mflo"; |
1960 | break; | |
1961 | case OPC_MTHI: | |
a1f6684d AJ |
1962 | if (reg != 0) |
1963 | tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]); | |
1964 | else | |
1965 | tcg_gen_movi_tl(cpu_HI[0], 0); | |
6af0bf9c FB |
1966 | opn = "mthi"; |
1967 | break; | |
1968 | case OPC_MTLO: | |
a1f6684d AJ |
1969 | if (reg != 0) |
1970 | tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]); | |
1971 | else | |
1972 | tcg_gen_movi_tl(cpu_LO[0], 0); | |
6af0bf9c FB |
1973 | opn = "mtlo"; |
1974 | break; | |
6af0bf9c FB |
1975 | } |
1976 | MIPS_DEBUG("%s %s", opn, regnames[reg]); | |
1977 | } | |
1978 | ||
7a387fff | 1979 | static void gen_muldiv (DisasContext *ctx, uint32_t opc, |
6af0bf9c FB |
1980 | int rs, int rt) |
1981 | { | |
923617a3 | 1982 | const char *opn = "mul/div"; |
d45f89f4 AJ |
1983 | TCGv t0, t1; |
1984 | ||
1985 | switch (opc) { | |
1986 | case OPC_DIV: | |
1987 | case OPC_DIVU: | |
1988 | #if defined(TARGET_MIPS64) | |
1989 | case OPC_DDIV: | |
1990 | case OPC_DDIVU: | |
1991 | #endif | |
1992 | t0 = tcg_temp_local_new(); | |
1993 | t1 = tcg_temp_local_new(); | |
1994 | break; | |
1995 | default: | |
1996 | t0 = tcg_temp_new(); | |
1997 | t1 = tcg_temp_new(); | |
1998 | break; | |
1999 | } | |
6af0bf9c | 2000 | |
78723684 TS |
2001 | gen_load_gpr(t0, rs); |
2002 | gen_load_gpr(t1, rt); | |
6af0bf9c FB |
2003 | switch (opc) { |
2004 | case OPC_DIV: | |
48d38ca5 TS |
2005 | { |
2006 | int l1 = gen_new_label(); | |
d45f89f4 | 2007 | int l2 = gen_new_label(); |
48d38ca5 | 2008 | |
d45f89f4 AJ |
2009 | tcg_gen_ext32s_tl(t0, t0); |
2010 | tcg_gen_ext32s_tl(t1, t1); | |
78723684 | 2011 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
d45f89f4 AJ |
2012 | tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); |
2013 | tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); | |
2014 | ||
2015 | tcg_gen_mov_tl(cpu_LO[0], t0); | |
2016 | tcg_gen_movi_tl(cpu_HI[0], 0); | |
2017 | tcg_gen_br(l1); | |
2018 | gen_set_label(l2); | |
2019 | tcg_gen_div_tl(cpu_LO[0], t0, t1); | |
2020 | tcg_gen_rem_tl(cpu_HI[0], t0, t1); | |
2021 | tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]); | |
2022 | tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]); | |
48d38ca5 TS |
2023 | gen_set_label(l1); |
2024 | } | |
6af0bf9c FB |
2025 | opn = "div"; |
2026 | break; | |
2027 | case OPC_DIVU: | |
48d38ca5 TS |
2028 | { |
2029 | int l1 = gen_new_label(); | |
2030 | ||
0c0ed03b AJ |
2031 | tcg_gen_ext32u_tl(t0, t0); |
2032 | tcg_gen_ext32u_tl(t1, t1); | |
78723684 | 2033 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
d45f89f4 AJ |
2034 | tcg_gen_divu_tl(cpu_LO[0], t0, t1); |
2035 | tcg_gen_remu_tl(cpu_HI[0], t0, t1); | |
2036 | tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]); | |
2037 | tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]); | |
48d38ca5 TS |
2038 | gen_set_label(l1); |
2039 | } | |
6af0bf9c FB |
2040 | opn = "divu"; |
2041 | break; | |
2042 | case OPC_MULT: | |
214c465f | 2043 | { |
d45f89f4 AJ |
2044 | TCGv_i64 t2 = tcg_temp_new_i64(); |
2045 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
2046 | ||
2047 | tcg_gen_ext_tl_i64(t2, t0); | |
2048 | tcg_gen_ext_tl_i64(t3, t1); | |
2049 | tcg_gen_mul_i64(t2, t2, t3); | |
2050 | tcg_temp_free_i64(t3); | |
2051 | tcg_gen_trunc_i64_tl(t0, t2); | |
2052 | tcg_gen_shri_i64(t2, t2, 32); | |
2053 | tcg_gen_trunc_i64_tl(t1, t2); | |
2054 | tcg_temp_free_i64(t2); | |
b10fa3c9 AJ |
2055 | tcg_gen_ext32s_tl(cpu_LO[0], t0); |
2056 | tcg_gen_ext32s_tl(cpu_HI[0], t1); | |
214c465f | 2057 | } |
6af0bf9c FB |
2058 | opn = "mult"; |
2059 | break; | |
2060 | case OPC_MULTU: | |
214c465f | 2061 | { |
d45f89f4 AJ |
2062 | TCGv_i64 t2 = tcg_temp_new_i64(); |
2063 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
214c465f | 2064 | |
78723684 TS |
2065 | tcg_gen_ext32u_tl(t0, t0); |
2066 | tcg_gen_ext32u_tl(t1, t1); | |
d45f89f4 AJ |
2067 | tcg_gen_extu_tl_i64(t2, t0); |
2068 | tcg_gen_extu_tl_i64(t3, t1); | |
2069 | tcg_gen_mul_i64(t2, t2, t3); | |
2070 | tcg_temp_free_i64(t3); | |
2071 | tcg_gen_trunc_i64_tl(t0, t2); | |
2072 | tcg_gen_shri_i64(t2, t2, 32); | |
2073 | tcg_gen_trunc_i64_tl(t1, t2); | |
2074 | tcg_temp_free_i64(t2); | |
b10fa3c9 AJ |
2075 | tcg_gen_ext32s_tl(cpu_LO[0], t0); |
2076 | tcg_gen_ext32s_tl(cpu_HI[0], t1); | |
214c465f | 2077 | } |
6af0bf9c FB |
2078 | opn = "multu"; |
2079 | break; | |
d26bc211 | 2080 | #if defined(TARGET_MIPS64) |
7a387fff | 2081 | case OPC_DDIV: |
48d38ca5 TS |
2082 | { |
2083 | int l1 = gen_new_label(); | |
d45f89f4 | 2084 | int l2 = gen_new_label(); |
48d38ca5 | 2085 | |
78723684 | 2086 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
d45f89f4 AJ |
2087 | tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); |
2088 | tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); | |
2089 | tcg_gen_mov_tl(cpu_LO[0], t0); | |
2090 | tcg_gen_movi_tl(cpu_HI[0], 0); | |
2091 | tcg_gen_br(l1); | |
2092 | gen_set_label(l2); | |
2093 | tcg_gen_div_i64(cpu_LO[0], t0, t1); | |
2094 | tcg_gen_rem_i64(cpu_HI[0], t0, t1); | |
48d38ca5 TS |
2095 | gen_set_label(l1); |
2096 | } | |
7a387fff TS |
2097 | opn = "ddiv"; |
2098 | break; | |
2099 | case OPC_DDIVU: | |
48d38ca5 TS |
2100 | { |
2101 | int l1 = gen_new_label(); | |
2102 | ||
78723684 | 2103 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
b10fa3c9 AJ |
2104 | tcg_gen_divu_i64(cpu_LO[0], t0, t1); |
2105 | tcg_gen_remu_i64(cpu_HI[0], t0, t1); | |
48d38ca5 TS |
2106 | gen_set_label(l1); |
2107 | } | |
7a387fff TS |
2108 | opn = "ddivu"; |
2109 | break; | |
2110 | case OPC_DMULT: | |
a7812ae4 | 2111 | gen_helper_dmult(t0, t1); |
7a387fff TS |
2112 | opn = "dmult"; |
2113 | break; | |
2114 | case OPC_DMULTU: | |
a7812ae4 | 2115 | gen_helper_dmultu(t0, t1); |
7a387fff TS |
2116 | opn = "dmultu"; |
2117 | break; | |
2118 | #endif | |
6af0bf9c | 2119 | case OPC_MADD: |
214c465f | 2120 | { |
d45f89f4 AJ |
2121 | TCGv_i64 t2 = tcg_temp_new_i64(); |
2122 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
2123 | ||
2124 | tcg_gen_ext_tl_i64(t2, t0); | |
2125 | tcg_gen_ext_tl_i64(t3, t1); | |
2126 | tcg_gen_mul_i64(t2, t2, t3); | |
2127 | tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); | |
2128 | tcg_gen_add_i64(t2, t2, t3); | |
2129 | tcg_temp_free_i64(t3); | |
2130 | tcg_gen_trunc_i64_tl(t0, t2); | |
2131 | tcg_gen_shri_i64(t2, t2, 32); | |
2132 | tcg_gen_trunc_i64_tl(t1, t2); | |
2133 | tcg_temp_free_i64(t2); | |
b10fa3c9 AJ |
2134 | tcg_gen_ext32s_tl(cpu_LO[0], t0); |
2135 | tcg_gen_ext32s_tl(cpu_LO[1], t1); | |
214c465f | 2136 | } |
6af0bf9c FB |
2137 | opn = "madd"; |
2138 | break; | |
2139 | case OPC_MADDU: | |
214c465f | 2140 | { |
d45f89f4 AJ |
2141 | TCGv_i64 t2 = tcg_temp_new_i64(); |
2142 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
214c465f | 2143 | |
78723684 TS |
2144 | tcg_gen_ext32u_tl(t0, t0); |
2145 | tcg_gen_ext32u_tl(t1, t1); | |
d45f89f4 AJ |
2146 | tcg_gen_extu_tl_i64(t2, t0); |
2147 | tcg_gen_extu_tl_i64(t3, t1); | |
2148 | tcg_gen_mul_i64(t2, t2, t3); | |
2149 | tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); | |
2150 | tcg_gen_add_i64(t2, t2, t3); | |
2151 | tcg_temp_free_i64(t3); | |
2152 | tcg_gen_trunc_i64_tl(t0, t2); | |
2153 | tcg_gen_shri_i64(t2, t2, 32); | |
2154 | tcg_gen_trunc_i64_tl(t1, t2); | |
2155 | tcg_temp_free_i64(t2); | |
b10fa3c9 AJ |
2156 | tcg_gen_ext32s_tl(cpu_LO[0], t0); |
2157 | tcg_gen_ext32s_tl(cpu_HI[0], t1); | |
214c465f | 2158 | } |
6af0bf9c FB |
2159 | opn = "maddu"; |
2160 | break; | |
2161 | case OPC_MSUB: | |
214c465f | 2162 | { |
d45f89f4 AJ |
2163 | TCGv_i64 t2 = tcg_temp_new_i64(); |
2164 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
2165 | ||
2166 | tcg_gen_ext_tl_i64(t2, t0); | |
2167 | tcg_gen_ext_tl_i64(t3, t1); | |
2168 | tcg_gen_mul_i64(t2, t2, t3); | |
2169 | tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); | |
2170 | tcg_gen_sub_i64(t2, t2, t3); | |
2171 | tcg_temp_free_i64(t3); | |
2172 | tcg_gen_trunc_i64_tl(t0, t2); | |
2173 | tcg_gen_shri_i64(t2, t2, 32); | |
2174 | tcg_gen_trunc_i64_tl(t1, t2); | |
2175 | tcg_temp_free_i64(t2); | |
b10fa3c9 AJ |
2176 | tcg_gen_ext32s_tl(cpu_LO[0], t0); |
2177 | tcg_gen_ext32s_tl(cpu_HI[0], t1); | |
214c465f | 2178 | } |
6af0bf9c FB |
2179 | opn = "msub"; |
2180 | break; | |
2181 | case OPC_MSUBU: | |
214c465f | 2182 | { |
d45f89f4 AJ |
2183 | TCGv_i64 t2 = tcg_temp_new_i64(); |
2184 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
214c465f | 2185 | |
78723684 TS |
2186 | tcg_gen_ext32u_tl(t0, t0); |
2187 | tcg_gen_ext32u_tl(t1, t1); | |
d45f89f4 AJ |
2188 | tcg_gen_extu_tl_i64(t2, t0); |
2189 | tcg_gen_extu_tl_i64(t3, t1); | |
2190 | tcg_gen_mul_i64(t2, t2, t3); | |
2191 | tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); | |
2192 | tcg_gen_sub_i64(t2, t2, t3); | |
2193 | tcg_temp_free_i64(t3); | |
2194 | tcg_gen_trunc_i64_tl(t0, t2); | |
2195 | tcg_gen_shri_i64(t2, t2, 32); | |
2196 | tcg_gen_trunc_i64_tl(t1, t2); | |
2197 | tcg_temp_free_i64(t2); | |
b10fa3c9 AJ |
2198 | tcg_gen_ext32s_tl(cpu_LO[0], t0); |
2199 | tcg_gen_ext32s_tl(cpu_HI[0], t1); | |
214c465f | 2200 | } |
6af0bf9c FB |
2201 | opn = "msubu"; |
2202 | break; | |
2203 | default: | |
923617a3 | 2204 | MIPS_INVAL(opn); |
6af0bf9c | 2205 | generate_exception(ctx, EXCP_RI); |
78723684 | 2206 | goto out; |
6af0bf9c FB |
2207 | } |
2208 | MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]); | |
78723684 TS |
2209 | out: |
2210 | tcg_temp_free(t0); | |
2211 | tcg_temp_free(t1); | |
6af0bf9c FB |
2212 | } |
2213 | ||
e9c71dd1 TS |
2214 | static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, |
2215 | int rd, int rs, int rt) | |
2216 | { | |
2217 | const char *opn = "mul vr54xx"; | |
f157bfe1 AJ |
2218 | TCGv t0 = tcg_temp_new(); |
2219 | TCGv t1 = tcg_temp_new(); | |
e9c71dd1 | 2220 | |
6c5c1e20 TS |
2221 | gen_load_gpr(t0, rs); |
2222 | gen_load_gpr(t1, rt); | |
e9c71dd1 TS |
2223 | |
2224 | switch (opc) { | |
2225 | case OPC_VR54XX_MULS: | |
a7812ae4 | 2226 | gen_helper_muls(t0, t0, t1); |
e9c71dd1 | 2227 | opn = "muls"; |
6958549d | 2228 | break; |
e9c71dd1 | 2229 | case OPC_VR54XX_MULSU: |
a7812ae4 | 2230 | gen_helper_mulsu(t0, t0, t1); |
e9c71dd1 | 2231 | opn = "mulsu"; |
6958549d | 2232 | break; |
e9c71dd1 | 2233 | case OPC_VR54XX_MACC: |
a7812ae4 | 2234 | gen_helper_macc(t0, t0, t1); |
e9c71dd1 | 2235 | opn = "macc"; |
6958549d | 2236 | break; |
e9c71dd1 | 2237 | case OPC_VR54XX_MACCU: |
a7812ae4 | 2238 | gen_helper_maccu(t0, t0, t1); |
e9c71dd1 | 2239 | opn = "maccu"; |
6958549d | 2240 | break; |
e9c71dd1 | 2241 | case OPC_VR54XX_MSAC: |
a7812ae4 | 2242 | gen_helper_msac(t0, t0, t1); |
e9c71dd1 | 2243 | opn = "msac"; |
6958549d | 2244 | break; |
e9c71dd1 | 2245 | case OPC_VR54XX_MSACU: |
a7812ae4 | 2246 | gen_helper_msacu(t0, t0, t1); |
e9c71dd1 | 2247 | opn = "msacu"; |
6958549d | 2248 | break; |
e9c71dd1 | 2249 | case OPC_VR54XX_MULHI: |
a7812ae4 | 2250 | gen_helper_mulhi(t0, t0, t1); |
e9c71dd1 | 2251 | opn = "mulhi"; |
6958549d | 2252 | break; |
e9c71dd1 | 2253 | case OPC_VR54XX_MULHIU: |
a7812ae4 | 2254 | gen_helper_mulhiu(t0, t0, t1); |
e9c71dd1 | 2255 | opn = "mulhiu"; |
6958549d | 2256 | break; |
e9c71dd1 | 2257 | case OPC_VR54XX_MULSHI: |
a7812ae4 | 2258 | gen_helper_mulshi(t0, t0, t1); |
e9c71dd1 | 2259 | opn = "mulshi"; |
6958549d | 2260 | break; |
e9c71dd1 | 2261 | case OPC_VR54XX_MULSHIU: |
a7812ae4 | 2262 | gen_helper_mulshiu(t0, t0, t1); |
e9c71dd1 | 2263 | opn = "mulshiu"; |
6958549d | 2264 | break; |
e9c71dd1 | 2265 | case OPC_VR54XX_MACCHI: |
a7812ae4 | 2266 | gen_helper_macchi(t0, t0, t1); |
e9c71dd1 | 2267 | opn = "macchi"; |
6958549d | 2268 | break; |
e9c71dd1 | 2269 | case OPC_VR54XX_MACCHIU: |
a7812ae4 | 2270 | gen_helper_macchiu(t0, t0, t1); |
e9c71dd1 | 2271 | opn = "macchiu"; |
6958549d | 2272 | break; |
e9c71dd1 | 2273 | case OPC_VR54XX_MSACHI: |
a7812ae4 | 2274 | gen_helper_msachi(t0, t0, t1); |
e9c71dd1 | 2275 | opn = "msachi"; |
6958549d | 2276 | break; |
e9c71dd1 | 2277 | case OPC_VR54XX_MSACHIU: |
a7812ae4 | 2278 | gen_helper_msachiu(t0, t0, t1); |
e9c71dd1 | 2279 | opn = "msachiu"; |
6958549d | 2280 | break; |
e9c71dd1 TS |
2281 | default: |
2282 | MIPS_INVAL("mul vr54xx"); | |
2283 | generate_exception(ctx, EXCP_RI); | |
6c5c1e20 | 2284 | goto out; |
e9c71dd1 | 2285 | } |
6c5c1e20 | 2286 | gen_store_gpr(t0, rd); |
e9c71dd1 | 2287 | MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); |
6c5c1e20 TS |
2288 | |
2289 | out: | |
2290 | tcg_temp_free(t0); | |
2291 | tcg_temp_free(t1); | |
e9c71dd1 TS |
2292 | } |
2293 | ||
7a387fff | 2294 | static void gen_cl (DisasContext *ctx, uint32_t opc, |
6af0bf9c FB |
2295 | int rd, int rs) |
2296 | { | |
923617a3 | 2297 | const char *opn = "CLx"; |
20e1fb52 | 2298 | TCGv t0; |
6c5c1e20 | 2299 | |
6af0bf9c | 2300 | if (rd == 0) { |
ead9360e | 2301 | /* Treat as NOP. */ |
6af0bf9c | 2302 | MIPS_DEBUG("NOP"); |
20e1fb52 | 2303 | return; |
6af0bf9c | 2304 | } |
20e1fb52 | 2305 | t0 = tcg_temp_new(); |
6c5c1e20 | 2306 | gen_load_gpr(t0, rs); |
6af0bf9c FB |
2307 | switch (opc) { |
2308 | case OPC_CLO: | |
20e1fb52 | 2309 | gen_helper_clo(cpu_gpr[rd], t0); |
6af0bf9c FB |
2310 | opn = "clo"; |
2311 | break; | |
2312 | case OPC_CLZ: | |
20e1fb52 | 2313 | gen_helper_clz(cpu_gpr[rd], t0); |
6af0bf9c FB |
2314 | opn = "clz"; |
2315 | break; | |
d26bc211 | 2316 | #if defined(TARGET_MIPS64) |
7a387fff | 2317 | case OPC_DCLO: |
20e1fb52 | 2318 | gen_helper_dclo(cpu_gpr[rd], t0); |
7a387fff TS |
2319 | opn = "dclo"; |
2320 | break; | |
2321 | case OPC_DCLZ: | |
20e1fb52 | 2322 | gen_helper_dclz(cpu_gpr[rd], t0); |
7a387fff TS |
2323 | opn = "dclz"; |
2324 | break; | |
2325 | #endif | |
6af0bf9c | 2326 | } |
6af0bf9c | 2327 | MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); |
6c5c1e20 | 2328 | tcg_temp_free(t0); |
6af0bf9c FB |
2329 | } |
2330 | ||
2331 | /* Traps */ | |
7a387fff | 2332 | static void gen_trap (DisasContext *ctx, uint32_t opc, |
6af0bf9c FB |
2333 | int rs, int rt, int16_t imm) |
2334 | { | |
2335 | int cond; | |
cdc0faa6 | 2336 | TCGv t0 = tcg_temp_new(); |
1ba74fb8 | 2337 | TCGv t1 = tcg_temp_new(); |
6af0bf9c FB |
2338 | |
2339 | cond = 0; | |
2340 | /* Load needed operands */ | |
2341 | switch (opc) { | |
2342 | case OPC_TEQ: | |
2343 | case OPC_TGE: | |
2344 | case OPC_TGEU: | |
2345 | case OPC_TLT: | |
2346 | case OPC_TLTU: | |
2347 | case OPC_TNE: | |
2348 | /* Compare two registers */ | |
2349 | if (rs != rt) { | |
be24bb4f TS |
2350 | gen_load_gpr(t0, rs); |
2351 | gen_load_gpr(t1, rt); | |
6af0bf9c FB |
2352 | cond = 1; |
2353 | } | |
179e32bb | 2354 | break; |
6af0bf9c FB |
2355 | case OPC_TEQI: |
2356 | case OPC_TGEI: | |
2357 | case OPC_TGEIU: | |
2358 | case OPC_TLTI: | |
2359 | case OPC_TLTIU: | |
2360 | case OPC_TNEI: | |
2361 | /* Compare register to immediate */ | |
2362 | if (rs != 0 || imm != 0) { | |
be24bb4f TS |
2363 | gen_load_gpr(t0, rs); |
2364 | tcg_gen_movi_tl(t1, (int32_t)imm); | |
6af0bf9c FB |
2365 | cond = 1; |
2366 | } | |
2367 | break; | |
2368 | } | |
2369 | if (cond == 0) { | |
2370 | switch (opc) { | |
2371 | case OPC_TEQ: /* rs == rs */ | |
2372 | case OPC_TEQI: /* r0 == 0 */ | |
2373 | case OPC_TGE: /* rs >= rs */ | |
2374 | case OPC_TGEI: /* r0 >= 0 */ | |
2375 | case OPC_TGEU: /* rs >= rs unsigned */ | |
2376 | case OPC_TGEIU: /* r0 >= 0 unsigned */ | |
2377 | /* Always trap */ | |
cdc0faa6 | 2378 | generate_exception(ctx, EXCP_TRAP); |
6af0bf9c FB |
2379 | break; |
2380 | case OPC_TLT: /* rs < rs */ | |
2381 | case OPC_TLTI: /* r0 < 0 */ | |
2382 | case OPC_TLTU: /* rs < rs unsigned */ | |
2383 | case OPC_TLTIU: /* r0 < 0 unsigned */ | |
2384 | case OPC_TNE: /* rs != rs */ | |
2385 | case OPC_TNEI: /* r0 != 0 */ | |
ead9360e | 2386 | /* Never trap: treat as NOP. */ |
cdc0faa6 | 2387 | break; |
6af0bf9c FB |
2388 | } |
2389 | } else { | |
cdc0faa6 AJ |
2390 | int l1 = gen_new_label(); |
2391 | ||
6af0bf9c FB |
2392 | switch (opc) { |
2393 | case OPC_TEQ: | |
2394 | case OPC_TEQI: | |
cdc0faa6 | 2395 | tcg_gen_brcond_tl(TCG_COND_NE, t0, t1, l1); |
6af0bf9c FB |
2396 | break; |
2397 | case OPC_TGE: | |
2398 | case OPC_TGEI: | |
cdc0faa6 | 2399 | tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1); |
6af0bf9c FB |
2400 | break; |
2401 | case OPC_TGEU: | |
2402 | case OPC_TGEIU: | |
cdc0faa6 | 2403 | tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1); |
6af0bf9c FB |
2404 | break; |
2405 | case OPC_TLT: | |
2406 | case OPC_TLTI: | |
cdc0faa6 | 2407 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); |
6af0bf9c FB |
2408 | break; |
2409 | case OPC_TLTU: | |
2410 | case OPC_TLTIU: | |
cdc0faa6 | 2411 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
6af0bf9c FB |
2412 | break; |
2413 | case OPC_TNE: | |
2414 | case OPC_TNEI: | |
cdc0faa6 | 2415 | tcg_gen_brcond_tl(TCG_COND_EQ, t0, t1, l1); |
6af0bf9c | 2416 | break; |
6af0bf9c | 2417 | } |
cdc0faa6 | 2418 | generate_exception(ctx, EXCP_TRAP); |
08ba7963 TS |
2419 | gen_set_label(l1); |
2420 | } | |
be24bb4f TS |
2421 | tcg_temp_free(t0); |
2422 | tcg_temp_free(t1); | |
6af0bf9c FB |
2423 | } |
2424 | ||
356265ae | 2425 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c53be334 | 2426 | { |
6e256c93 FB |
2427 | TranslationBlock *tb; |
2428 | tb = ctx->tb; | |
2429 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { | |
57fec1fe | 2430 | tcg_gen_goto_tb(n); |
9b9e4393 | 2431 | gen_save_pc(dest); |
57fec1fe | 2432 | tcg_gen_exit_tb((long)tb + n); |
6e256c93 | 2433 | } else { |
9b9e4393 | 2434 | gen_save_pc(dest); |
57fec1fe | 2435 | tcg_gen_exit_tb(0); |
6e256c93 | 2436 | } |
c53be334 FB |
2437 | } |
2438 | ||
6af0bf9c | 2439 | /* Branches (before delay slot) */ |
7a387fff | 2440 | static void gen_compute_branch (DisasContext *ctx, uint32_t opc, |
6af0bf9c FB |
2441 | int rs, int rt, int32_t offset) |
2442 | { | |
d077b6f7 | 2443 | target_ulong btgt = -1; |
3ad4bb2d | 2444 | int blink = 0; |
2fdbad25 | 2445 | int bcond_compute = 0; |
1ba74fb8 AJ |
2446 | TCGv t0 = tcg_temp_new(); |
2447 | TCGv t1 = tcg_temp_new(); | |
3ad4bb2d TS |
2448 | |
2449 | if (ctx->hflags & MIPS_HFLAG_BMASK) { | |
923617a3 | 2450 | #ifdef MIPS_DEBUG_DISAS |
d12d51d5 | 2451 | LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc); |
923617a3 | 2452 | #endif |
3ad4bb2d | 2453 | generate_exception(ctx, EXCP_RI); |
6c5c1e20 | 2454 | goto out; |
3ad4bb2d | 2455 | } |
6af0bf9c | 2456 | |
6af0bf9c FB |
2457 | /* Load needed operands */ |
2458 | switch (opc) { | |
2459 | case OPC_BEQ: | |
2460 | case OPC_BEQL: | |
2461 | case OPC_BNE: | |
2462 | case OPC_BNEL: | |
2463 | /* Compare two registers */ | |
2464 | if (rs != rt) { | |
6c5c1e20 TS |
2465 | gen_load_gpr(t0, rs); |
2466 | gen_load_gpr(t1, rt); | |
2fdbad25 | 2467 | bcond_compute = 1; |
6af0bf9c | 2468 | } |
d077b6f7 | 2469 | btgt = ctx->pc + 4 + offset; |
6af0bf9c FB |
2470 | break; |
2471 | case OPC_BGEZ: | |
2472 | case OPC_BGEZAL: | |
2473 | case OPC_BGEZALL: | |
2474 | case OPC_BGEZL: | |
2475 | case OPC_BGTZ: | |
2476 | case OPC_BGTZL: | |
2477 | case OPC_BLEZ: | |
2478 | case OPC_BLEZL: | |
2479 | case OPC_BLTZ: | |
2480 | case OPC_BLTZAL: | |
2481 | case OPC_BLTZALL: | |
2482 | case OPC_BLTZL: | |
2483 | /* Compare to zero */ | |
2484 | if (rs != 0) { | |
6c5c1e20 | 2485 | gen_load_gpr(t0, rs); |
2fdbad25 | 2486 | bcond_compute = 1; |
6af0bf9c | 2487 | } |
d077b6f7 | 2488 | btgt = ctx->pc + 4 + offset; |
6af0bf9c FB |
2489 | break; |
2490 | case OPC_J: | |
2491 | case OPC_JAL: | |
2492 | /* Jump to immediate */ | |
d077b6f7 | 2493 | btgt = ((ctx->pc + 4) & (int32_t)0xF0000000) | (uint32_t)offset; |
6af0bf9c FB |
2494 | break; |
2495 | case OPC_JR: | |
2496 | case OPC_JALR: | |
2497 | /* Jump to register */ | |
7a387fff TS |
2498 | if (offset != 0 && offset != 16) { |
2499 | /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the | |
cbeb0857 | 2500 | others are reserved. */ |
923617a3 | 2501 | MIPS_INVAL("jump hint"); |
6af0bf9c | 2502 | generate_exception(ctx, EXCP_RI); |
6c5c1e20 | 2503 | goto out; |
6af0bf9c | 2504 | } |
d077b6f7 | 2505 | gen_load_gpr(btarget, rs); |
6af0bf9c FB |
2506 | break; |
2507 | default: | |
2508 | MIPS_INVAL("branch/jump"); | |
2509 | generate_exception(ctx, EXCP_RI); | |
6c5c1e20 | 2510 | goto out; |
6af0bf9c | 2511 | } |
2fdbad25 | 2512 | if (bcond_compute == 0) { |
6af0bf9c FB |
2513 | /* No condition to be computed */ |
2514 | switch (opc) { | |
2515 | case OPC_BEQ: /* rx == rx */ | |
2516 | case OPC_BEQL: /* rx == rx likely */ | |
2517 | case OPC_BGEZ: /* 0 >= 0 */ | |
2518 | case OPC_BGEZL: /* 0 >= 0 likely */ | |
2519 | case OPC_BLEZ: /* 0 <= 0 */ | |
2520 | case OPC_BLEZL: /* 0 <= 0 likely */ | |
2521 | /* Always take */ | |
4ad40f36 | 2522 | ctx->hflags |= MIPS_HFLAG_B; |
6af0bf9c FB |
2523 | MIPS_DEBUG("balways"); |
2524 | break; | |
2525 | case OPC_BGEZAL: /* 0 >= 0 */ | |
2526 | case OPC_BGEZALL: /* 0 >= 0 likely */ | |
2527 | /* Always take and link */ | |
2528 | blink = 31; | |
4ad40f36 | 2529 | ctx->hflags |= MIPS_HFLAG_B; |
6af0bf9c FB |
2530 | MIPS_DEBUG("balways and link"); |
2531 | break; | |
2532 | case OPC_BNE: /* rx != rx */ | |
2533 | case OPC_BGTZ: /* 0 > 0 */ | |
2534 | case OPC_BLTZ: /* 0 < 0 */ | |
ead9360e | 2535 | /* Treat as NOP. */ |
6af0bf9c | 2536 | MIPS_DEBUG("bnever (NOP)"); |
6c5c1e20 | 2537 | goto out; |
eeef26cd | 2538 | case OPC_BLTZAL: /* 0 < 0 */ |
1ba74fb8 | 2539 | tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8); |
9898128f | 2540 | MIPS_DEBUG("bnever and link"); |
6c5c1e20 | 2541 | goto out; |
eeef26cd | 2542 | case OPC_BLTZALL: /* 0 < 0 likely */ |
1ba74fb8 | 2543 | tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8); |
9898128f TS |
2544 | /* Skip the instruction in the delay slot */ |
2545 | MIPS_DEBUG("bnever, link and skip"); | |
2546 | ctx->pc += 4; | |
6c5c1e20 | 2547 | goto out; |
6af0bf9c FB |
2548 | case OPC_BNEL: /* rx != rx likely */ |
2549 | case OPC_BGTZL: /* 0 > 0 likely */ | |
6af0bf9c FB |
2550 | case OPC_BLTZL: /* 0 < 0 likely */ |
2551 | /* Skip the instruction in the delay slot */ | |
2552 | MIPS_DEBUG("bnever and skip"); | |
9898128f | 2553 | ctx->pc += 4; |
6c5c1e20 | 2554 | goto out; |
6af0bf9c | 2555 | case OPC_J: |
4ad40f36 | 2556 | ctx->hflags |= MIPS_HFLAG_B; |
d077b6f7 | 2557 | MIPS_DEBUG("j " TARGET_FMT_lx, btgt); |
6af0bf9c FB |
2558 | break; |
2559 | case OPC_JAL: | |
2560 | blink = 31; | |
4ad40f36 | 2561 | ctx->hflags |= MIPS_HFLAG_B; |
d077b6f7 | 2562 | MIPS_DEBUG("jal " TARGET_FMT_lx, btgt); |
6af0bf9c FB |
2563 | break; |
2564 | case OPC_JR: | |
4ad40f36 | 2565 | ctx->hflags |= MIPS_HFLAG_BR; |
6af0bf9c FB |
2566 | MIPS_DEBUG("jr %s", regnames[rs]); |
2567 | break; | |
2568 | case OPC_JALR: | |
2569 | blink = rt; | |
4ad40f36 | 2570 | ctx->hflags |= MIPS_HFLAG_BR; |
6af0bf9c FB |
2571 | MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]); |
2572 | break; | |
2573 | default: | |
2574 | MIPS_INVAL("branch/jump"); | |
2575 | generate_exception(ctx, EXCP_RI); | |
6c5c1e20 | 2576 | goto out; |
6af0bf9c FB |
2577 | } |
2578 | } else { | |
2579 | switch (opc) { | |
2580 | case OPC_BEQ: | |
1ba74fb8 | 2581 | gen_op_eq(bcond, t0, t1); |
923617a3 | 2582 | MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx, |
d077b6f7 | 2583 | regnames[rs], regnames[rt], btgt); |
6af0bf9c FB |
2584 | goto not_likely; |
2585 | case OPC_BEQL: | |
1ba74fb8 | 2586 | gen_op_eq(bcond, t0, t1); |
923617a3 | 2587 | MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx, |
d077b6f7 | 2588 | regnames[rs], regnames[rt], btgt); |
6af0bf9c FB |
2589 | goto likely; |
2590 | case OPC_BNE: | |
1ba74fb8 | 2591 | gen_op_ne(bcond, t0, t1); |
923617a3 | 2592 | MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx, |
d077b6f7 | 2593 | regnames[rs], regnames[rt], btgt); |
6af0bf9c FB |
2594 | goto not_likely; |
2595 | case OPC_BNEL: | |
1ba74fb8 | 2596 | gen_op_ne(bcond, t0, t1); |
923617a3 | 2597 | MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx, |
d077b6f7 | 2598 | regnames[rs], regnames[rt], btgt); |
6af0bf9c FB |
2599 | goto likely; |
2600 | case OPC_BGEZ: | |
1ba74fb8 | 2601 | gen_op_gez(bcond, t0); |
d077b6f7 | 2602 | MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2603 | goto not_likely; |
2604 | case OPC_BGEZL: | |
1ba74fb8 | 2605 | gen_op_gez(bcond, t0); |
d077b6f7 | 2606 | MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2607 | goto likely; |
2608 | case OPC_BGEZAL: | |
1ba74fb8 | 2609 | gen_op_gez(bcond, t0); |
d077b6f7 | 2610 | MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2611 | blink = 31; |
2612 | goto not_likely; | |
2613 | case OPC_BGEZALL: | |
1ba74fb8 | 2614 | gen_op_gez(bcond, t0); |
6af0bf9c | 2615 | blink = 31; |
d077b6f7 | 2616 | MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2617 | goto likely; |
2618 | case OPC_BGTZ: | |
1ba74fb8 | 2619 | gen_op_gtz(bcond, t0); |
d077b6f7 | 2620 | MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2621 | goto not_likely; |
2622 | case OPC_BGTZL: | |
1ba74fb8 | 2623 | gen_op_gtz(bcond, t0); |
d077b6f7 | 2624 | MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2625 | goto likely; |
2626 | case OPC_BLEZ: | |
1ba74fb8 | 2627 | gen_op_lez(bcond, t0); |
d077b6f7 | 2628 | MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2629 | goto not_likely; |
2630 | case OPC_BLEZL: | |
1ba74fb8 | 2631 | gen_op_lez(bcond, t0); |
d077b6f7 | 2632 | MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2633 | goto likely; |
2634 | case OPC_BLTZ: | |
1ba74fb8 | 2635 | gen_op_ltz(bcond, t0); |
d077b6f7 | 2636 | MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2637 | goto not_likely; |
2638 | case OPC_BLTZL: | |
1ba74fb8 | 2639 | gen_op_ltz(bcond, t0); |
d077b6f7 | 2640 | MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c FB |
2641 | goto likely; |
2642 | case OPC_BLTZAL: | |
1ba74fb8 | 2643 | gen_op_ltz(bcond, t0); |
6af0bf9c | 2644 | blink = 31; |
d077b6f7 | 2645 | MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c | 2646 | not_likely: |
4ad40f36 | 2647 | ctx->hflags |= MIPS_HFLAG_BC; |
6af0bf9c FB |
2648 | break; |
2649 | case OPC_BLTZALL: | |
1ba74fb8 | 2650 | gen_op_ltz(bcond, t0); |
6af0bf9c | 2651 | blink = 31; |
d077b6f7 | 2652 | MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt); |
6af0bf9c | 2653 | likely: |
4ad40f36 | 2654 | ctx->hflags |= MIPS_HFLAG_BL; |
6af0bf9c | 2655 | break; |
c53f4a62 TS |
2656 | default: |
2657 | MIPS_INVAL("conditional branch/jump"); | |
2658 | generate_exception(ctx, EXCP_RI); | |
6c5c1e20 | 2659 | goto out; |
6af0bf9c | 2660 | } |
6af0bf9c | 2661 | } |
923617a3 | 2662 | MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx, |
d077b6f7 | 2663 | blink, ctx->hflags, btgt); |
9b9e4393 | 2664 | |
d077b6f7 | 2665 | ctx->btarget = btgt; |
6af0bf9c | 2666 | if (blink > 0) { |
1ba74fb8 | 2667 | tcg_gen_movi_tl(cpu_gpr[blink], ctx->pc + 8); |
6af0bf9c | 2668 | } |
6c5c1e20 TS |
2669 | |
2670 | out: | |
2671 | tcg_temp_free(t0); | |
2672 | tcg_temp_free(t1); | |
6af0bf9c FB |
2673 | } |
2674 | ||
7a387fff TS |
2675 | /* special3 bitfield operations */ |
2676 | static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, | |
356265ae | 2677 | int rs, int lsb, int msb) |
7a387fff | 2678 | { |
a7812ae4 PB |
2679 | TCGv t0 = tcg_temp_new(); |
2680 | TCGv t1 = tcg_temp_new(); | |
505ad7c2 | 2681 | target_ulong mask; |
6c5c1e20 TS |
2682 | |
2683 | gen_load_gpr(t1, rs); | |
7a387fff TS |
2684 | switch (opc) { |
2685 | case OPC_EXT: | |
2686 | if (lsb + msb > 31) | |
2687 | goto fail; | |
505ad7c2 AJ |
2688 | tcg_gen_shri_tl(t0, t1, lsb); |
2689 | if (msb != 31) { | |
2690 | tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1); | |
2691 | } else { | |
2692 | tcg_gen_ext32s_tl(t0, t0); | |
2693 | } | |
7a387fff | 2694 | break; |
c6d6dd7c | 2695 | #if defined(TARGET_MIPS64) |
7a387fff | 2696 | case OPC_DEXTM: |
505ad7c2 AJ |
2697 | tcg_gen_shri_tl(t0, t1, lsb); |
2698 | if (msb != 31) { | |
2699 | tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1 + 32)) - 1); | |
2700 | } | |
7a387fff TS |
2701 | break; |
2702 | case OPC_DEXTU: | |
505ad7c2 AJ |
2703 | tcg_gen_shri_tl(t0, t1, lsb + 32); |
2704 | tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); | |
7a387fff TS |
2705 | break; |
2706 | case OPC_DEXT: | |
505ad7c2 AJ |
2707 | tcg_gen_shri_tl(t0, t1, lsb); |
2708 | tcg_gen_andi_tl(t0, t0, (1ULL << (msb + 1)) - 1); | |
7a387fff | 2709 | break; |
c6d6dd7c | 2710 | #endif |
7a387fff TS |
2711 | case OPC_INS: |
2712 | if (lsb > msb) | |
2713 | goto fail; | |
505ad7c2 | 2714 | mask = ((msb - lsb + 1 < 32) ? ((1 << (msb - lsb + 1)) - 1) : ~0) << lsb; |
6c5c1e20 | 2715 | gen_load_gpr(t0, rt); |
505ad7c2 AJ |
2716 | tcg_gen_andi_tl(t0, t0, ~mask); |
2717 | tcg_gen_shli_tl(t1, t1, lsb); | |
2718 | tcg_gen_andi_tl(t1, t1, mask); | |
2719 | tcg_gen_or_tl(t0, t0, t1); | |
2720 | tcg_gen_ext32s_tl(t0, t0); | |
7a387fff | 2721 | break; |
c6d6dd7c | 2722 | #if defined(TARGET_MIPS64) |
7a387fff TS |
2723 | case OPC_DINSM: |
2724 | if (lsb > msb) | |
2725 | goto fail; | |
505ad7c2 | 2726 | mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) - 1) : ~0ULL) << lsb; |
6c5c1e20 | 2727 | gen_load_gpr(t0, rt); |
505ad7c2 AJ |
2728 | tcg_gen_andi_tl(t0, t0, ~mask); |
2729 | tcg_gen_shli_tl(t1, t1, lsb); | |
2730 | tcg_gen_andi_tl(t1, t1, mask); | |
2731 | tcg_gen_or_tl(t0, t0, t1); | |
7a387fff TS |
2732 | break; |
2733 | case OPC_DINSU: | |
2734 | if (lsb > msb) | |
2735 | goto fail; | |
505ad7c2 | 2736 | mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb; |
6c5c1e20 | 2737 | gen_load_gpr(t0, rt); |
505ad7c2 AJ |
2738 | tcg_gen_andi_tl(t0, t0, ~mask); |
2739 | tcg_gen_shli_tl(t1, t1, lsb + 32); | |
2740 | tcg_gen_andi_tl(t1, t1, mask); | |
2741 | tcg_gen_or_tl(t0, t0, t1); | |
7a387fff TS |
2742 | break; |
2743 | case OPC_DINS: | |
2744 | if (lsb > msb) | |
2745 | goto fail; | |
6c5c1e20 | 2746 | gen_load_gpr(t0, rt); |
505ad7c2 AJ |
2747 | mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb; |
2748 | gen_load_gpr(t0, rt); | |
2749 | tcg_gen_andi_tl(t0, t0, ~mask); | |
2750 | tcg_gen_shli_tl(t1, t1, lsb); | |
2751 | tcg_gen_andi_tl(t1, t1, mask); | |
2752 | tcg_gen_or_tl(t0, t0, t1); | |
7a387fff | 2753 | break; |
c6d6dd7c | 2754 | #endif |
7a387fff TS |
2755 | default: |
2756 | fail: | |
2757 | MIPS_INVAL("bitops"); | |
2758 | generate_exception(ctx, EXCP_RI); | |
6c5c1e20 TS |
2759 | tcg_temp_free(t0); |
2760 | tcg_temp_free(t1); | |
7a387fff TS |
2761 | return; |
2762 | } | |
6c5c1e20 TS |
2763 | gen_store_gpr(t0, rt); |
2764 | tcg_temp_free(t0); | |
2765 | tcg_temp_free(t1); | |
7a387fff TS |
2766 | } |
2767 | ||
49bcf33c AJ |
2768 | static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) |
2769 | { | |
3a55fa47 | 2770 | TCGv t0; |
49bcf33c | 2771 | |
3a55fa47 AJ |
2772 | if (rd == 0) { |
2773 | /* If no destination, treat it as a NOP. */ | |
2774 | MIPS_DEBUG("NOP"); | |
2775 | return; | |
2776 | } | |
2777 | ||
2778 | t0 = tcg_temp_new(); | |
2779 | gen_load_gpr(t0, rt); | |
49bcf33c AJ |
2780 | switch (op2) { |
2781 | case OPC_WSBH: | |
3a55fa47 AJ |
2782 | { |
2783 | TCGv t1 = tcg_temp_new(); | |
2784 | ||
2785 | tcg_gen_shri_tl(t1, t0, 8); | |
2786 | tcg_gen_andi_tl(t1, t1, 0x00FF00FF); | |
2787 | tcg_gen_shli_tl(t0, t0, 8); | |
2788 | tcg_gen_andi_tl(t0, t0, ~0x00FF00FF); | |
2789 | tcg_gen_or_tl(t0, t0, t1); | |
2790 | tcg_temp_free(t1); | |
2791 | tcg_gen_ext32s_tl(cpu_gpr[rd], t0); | |
2792 | } | |
49bcf33c AJ |
2793 | break; |
2794 | case OPC_SEB: | |
3a55fa47 | 2795 | tcg_gen_ext8s_tl(cpu_gpr[rd], t0); |
49bcf33c AJ |
2796 | break; |
2797 | case OPC_SEH: | |
3a55fa47 | 2798 | tcg_gen_ext16s_tl(cpu_gpr[rd], t0); |
49bcf33c AJ |
2799 | break; |
2800 | #if defined(TARGET_MIPS64) | |
2801 | case OPC_DSBH: | |
3a55fa47 AJ |
2802 | { |
2803 | TCGv t1 = tcg_temp_new(); | |
2804 | ||
2805 | tcg_gen_shri_tl(t1, t0, 8); | |
2806 | tcg_gen_andi_tl(t1, t1, 0x00FF00FF00FF00FFULL); | |
2807 | tcg_gen_shli_tl(t0, t0, 8); | |
2808 | tcg_gen_andi_tl(t0, t0, ~0x00FF00FF00FF00FFULL); | |
2809 | tcg_gen_or_tl(cpu_gpr[rd], t0, t1); | |
2810 | tcg_temp_free(t1); | |
2811 | } | |
49bcf33c AJ |
2812 | break; |
2813 | case OPC_DSHD: | |
3a55fa47 AJ |
2814 | { |
2815 | TCGv t1 = tcg_temp_new(); | |
2816 | ||
2817 | tcg_gen_shri_tl(t1, t0, 16); | |
2818 | tcg_gen_andi_tl(t1, t1, 0x0000FFFF0000FFFFULL); | |
2819 | tcg_gen_shli_tl(t0, t0, 16); | |
2820 | tcg_gen_andi_tl(t0, t0, ~0x0000FFFF0000FFFFULL); | |
2821 | tcg_gen_or_tl(t0, t0, t1); | |
2822 | tcg_gen_shri_tl(t1, t0, 32); | |
2823 | tcg_gen_shli_tl(t0, t0, 32); | |
2824 | tcg_gen_or_tl(cpu_gpr[rd], t0, t1); | |
2825 | tcg_temp_free(t1); | |
2826 | } | |
49bcf33c AJ |
2827 | break; |
2828 | #endif | |
2829 | default: | |
2830 | MIPS_INVAL("bsfhl"); | |
2831 | generate_exception(ctx, EXCP_RI); | |
2832 | tcg_temp_free(t0); | |
49bcf33c AJ |
2833 | return; |
2834 | } | |
49bcf33c | 2835 | tcg_temp_free(t0); |
49bcf33c AJ |
2836 | } |
2837 | ||
f1aa6320 | 2838 | #ifndef CONFIG_USER_ONLY |
0eaef5aa | 2839 | /* CP0 (MMU and control) */ |
d9bea114 | 2840 | static inline void gen_mfc0_load32 (TCGv arg, target_ulong off) |
4f57689a | 2841 | { |
d9bea114 | 2842 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4f57689a | 2843 | |
d9bea114 AJ |
2844 | tcg_gen_ld_i32(t0, cpu_env, off); |
2845 | tcg_gen_ext_i32_tl(arg, t0); | |
2846 | tcg_temp_free_i32(t0); | |
4f57689a TS |
2847 | } |
2848 | ||
d9bea114 | 2849 | static inline void gen_mfc0_load64 (TCGv arg, target_ulong off) |
4f57689a | 2850 | { |
d9bea114 AJ |
2851 | tcg_gen_ld_tl(arg, cpu_env, off); |
2852 | tcg_gen_ext32s_tl(arg, arg); | |
4f57689a TS |
2853 | } |
2854 | ||
d9bea114 | 2855 | static inline void gen_mtc0_store32 (TCGv arg, target_ulong off) |
f1aa6320 | 2856 | { |
d9bea114 | 2857 | TCGv_i32 t0 = tcg_temp_new_i32(); |
f1aa6320 | 2858 | |
d9bea114 AJ |
2859 | tcg_gen_trunc_tl_i32(t0, arg); |
2860 | tcg_gen_st_i32(t0, cpu_env, off); | |
2861 | tcg_temp_free_i32(t0); | |
f1aa6320 TS |
2862 | } |
2863 | ||
d9bea114 | 2864 | static inline void gen_mtc0_store64 (TCGv arg, target_ulong off) |
f1aa6320 | 2865 | { |
d9bea114 AJ |
2866 | tcg_gen_ext32s_tl(arg, arg); |
2867 | tcg_gen_st_tl(arg, cpu_env, off); | |
f1aa6320 TS |
2868 | } |
2869 | ||
d9bea114 | 2870 | static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) |
873eb012 | 2871 | { |
7a387fff | 2872 | const char *rn = "invalid"; |
873eb012 | 2873 | |
e189e748 TS |
2874 | if (sel != 0) |
2875 | check_insn(env, ctx, ISA_MIPS32); | |
2876 | ||
873eb012 TS |
2877 | switch (reg) { |
2878 | case 0: | |
7a387fff TS |
2879 | switch (sel) { |
2880 | case 0: | |
d9bea114 | 2881 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index)); |
7a387fff TS |
2882 | rn = "Index"; |
2883 | break; | |
2884 | case 1: | |
7385ac0b | 2885 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2886 | gen_helper_mfc0_mvpcontrol(arg); |
7a387fff | 2887 | rn = "MVPControl"; |
ead9360e | 2888 | break; |
7a387fff | 2889 | case 2: |
7385ac0b | 2890 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2891 | gen_helper_mfc0_mvpconf0(arg); |
7a387fff | 2892 | rn = "MVPConf0"; |
ead9360e | 2893 | break; |
7a387fff | 2894 | case 3: |
7385ac0b | 2895 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2896 | gen_helper_mfc0_mvpconf1(arg); |
7a387fff | 2897 | rn = "MVPConf1"; |
ead9360e | 2898 | break; |
7a387fff TS |
2899 | default: |
2900 | goto die; | |
2901 | } | |
873eb012 TS |
2902 | break; |
2903 | case 1: | |
7a387fff TS |
2904 | switch (sel) { |
2905 | case 0: | |
d9bea114 | 2906 | gen_helper_mfc0_random(arg); |
7a387fff | 2907 | rn = "Random"; |
2423f660 | 2908 | break; |
7a387fff | 2909 | case 1: |
7385ac0b | 2910 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2911 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl)); |
7a387fff | 2912 | rn = "VPEControl"; |
ead9360e | 2913 | break; |
7a387fff | 2914 | case 2: |
7385ac0b | 2915 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2916 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0)); |
7a387fff | 2917 | rn = "VPEConf0"; |
ead9360e | 2918 | break; |
7a387fff | 2919 | case 3: |
7385ac0b | 2920 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2921 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1)); |
7a387fff | 2922 | rn = "VPEConf1"; |
ead9360e | 2923 | break; |
7a387fff | 2924 | case 4: |
7385ac0b | 2925 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2926 | gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask)); |
7a387fff | 2927 | rn = "YQMask"; |
ead9360e | 2928 | break; |
7a387fff | 2929 | case 5: |
7385ac0b | 2930 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2931 | gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule)); |
7a387fff | 2932 | rn = "VPESchedule"; |
ead9360e | 2933 | break; |
7a387fff | 2934 | case 6: |
7385ac0b | 2935 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2936 | gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack)); |
7a387fff | 2937 | rn = "VPEScheFBack"; |
ead9360e | 2938 | break; |
7a387fff | 2939 | case 7: |
7385ac0b | 2940 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2941 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt)); |
7a387fff | 2942 | rn = "VPEOpt"; |
ead9360e | 2943 | break; |
7a387fff TS |
2944 | default: |
2945 | goto die; | |
2946 | } | |
873eb012 TS |
2947 | break; |
2948 | case 2: | |
7a387fff TS |
2949 | switch (sel) { |
2950 | case 0: | |
d9bea114 AJ |
2951 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0)); |
2952 | tcg_gen_ext32s_tl(arg, arg); | |
2423f660 TS |
2953 | rn = "EntryLo0"; |
2954 | break; | |
7a387fff | 2955 | case 1: |
7385ac0b | 2956 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2957 | gen_helper_mfc0_tcstatus(arg); |
2423f660 | 2958 | rn = "TCStatus"; |
ead9360e | 2959 | break; |
7a387fff | 2960 | case 2: |
7385ac0b | 2961 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2962 | gen_helper_mfc0_tcbind(arg); |
2423f660 | 2963 | rn = "TCBind"; |
ead9360e | 2964 | break; |
7a387fff | 2965 | case 3: |
7385ac0b | 2966 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2967 | gen_helper_mfc0_tcrestart(arg); |
2423f660 | 2968 | rn = "TCRestart"; |
ead9360e | 2969 | break; |
7a387fff | 2970 | case 4: |
7385ac0b | 2971 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2972 | gen_helper_mfc0_tchalt(arg); |
2423f660 | 2973 | rn = "TCHalt"; |
ead9360e | 2974 | break; |
7a387fff | 2975 | case 5: |
7385ac0b | 2976 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2977 | gen_helper_mfc0_tccontext(arg); |
2423f660 | 2978 | rn = "TCContext"; |
ead9360e | 2979 | break; |
7a387fff | 2980 | case 6: |
7385ac0b | 2981 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2982 | gen_helper_mfc0_tcschedule(arg); |
2423f660 | 2983 | rn = "TCSchedule"; |
ead9360e | 2984 | break; |
7a387fff | 2985 | case 7: |
7385ac0b | 2986 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 2987 | gen_helper_mfc0_tcschefback(arg); |
2423f660 | 2988 | rn = "TCScheFBack"; |
ead9360e | 2989 | break; |
7a387fff TS |
2990 | default: |
2991 | goto die; | |
2992 | } | |
873eb012 TS |
2993 | break; |
2994 | case 3: | |
7a387fff TS |
2995 | switch (sel) { |
2996 | case 0: | |
d9bea114 AJ |
2997 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1)); |
2998 | tcg_gen_ext32s_tl(arg, arg); | |
2423f660 TS |
2999 | rn = "EntryLo1"; |
3000 | break; | |
7a387fff TS |
3001 | default: |
3002 | goto die; | |
1579a72e | 3003 | } |
873eb012 TS |
3004 | break; |
3005 | case 4: | |
7a387fff TS |
3006 | switch (sel) { |
3007 | case 0: | |
d9bea114 AJ |
3008 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context)); |
3009 | tcg_gen_ext32s_tl(arg, arg); | |
2423f660 TS |
3010 | rn = "Context"; |
3011 | break; | |
7a387fff | 3012 | case 1: |
d9bea114 | 3013 | // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */ |
2423f660 TS |
3014 | rn = "ContextConfig"; |
3015 | // break; | |
7a387fff TS |
3016 | default: |
3017 | goto die; | |
1579a72e | 3018 | } |
873eb012 TS |
3019 | break; |
3020 | case 5: | |
7a387fff TS |
3021 | switch (sel) { |
3022 | case 0: | |
d9bea114 | 3023 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask)); |
2423f660 TS |
3024 | rn = "PageMask"; |
3025 | break; | |
7a387fff | 3026 | case 1: |
e189e748 | 3027 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3028 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain)); |
2423f660 TS |
3029 | rn = "PageGrain"; |
3030 | break; | |
7a387fff TS |
3031 | default: |
3032 | goto die; | |
1579a72e | 3033 | } |
873eb012 TS |
3034 | break; |
3035 | case 6: | |
7a387fff TS |
3036 | switch (sel) { |
3037 | case 0: | |
d9bea114 | 3038 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired)); |
2423f660 TS |
3039 | rn = "Wired"; |
3040 | break; | |
7a387fff | 3041 | case 1: |
e189e748 | 3042 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3043 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0)); |
2423f660 | 3044 | rn = "SRSConf0"; |
ead9360e | 3045 | break; |
7a387fff | 3046 | case 2: |
e189e748 | 3047 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3048 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1)); |
2423f660 | 3049 | rn = "SRSConf1"; |
ead9360e | 3050 | break; |
7a387fff | 3051 | case 3: |
e189e748 | 3052 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3053 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2)); |
2423f660 | 3054 | rn = "SRSConf2"; |
ead9360e | 3055 | break; |
7a387fff | 3056 | case 4: |
e189e748 | 3057 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3058 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3)); |
2423f660 | 3059 | rn = "SRSConf3"; |
ead9360e | 3060 | break; |
7a387fff | 3061 | case 5: |
e189e748 | 3062 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3063 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4)); |
2423f660 | 3064 | rn = "SRSConf4"; |
ead9360e | 3065 | break; |
7a387fff TS |
3066 | default: |
3067 | goto die; | |
1579a72e | 3068 | } |
873eb012 | 3069 | break; |
8c0fdd85 | 3070 | case 7: |
7a387fff TS |
3071 | switch (sel) { |
3072 | case 0: | |
e189e748 | 3073 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3074 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna)); |
2423f660 TS |
3075 | rn = "HWREna"; |
3076 | break; | |
7a387fff TS |
3077 | default: |
3078 | goto die; | |
1579a72e | 3079 | } |
8c0fdd85 | 3080 | break; |
873eb012 | 3081 | case 8: |
7a387fff TS |
3082 | switch (sel) { |
3083 | case 0: | |
d9bea114 AJ |
3084 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr)); |
3085 | tcg_gen_ext32s_tl(arg, arg); | |
f0b3f3ae | 3086 | rn = "BadVAddr"; |
2423f660 | 3087 | break; |
7a387fff TS |
3088 | default: |
3089 | goto die; | |
3090 | } | |
873eb012 TS |
3091 | break; |
3092 | case 9: | |
7a387fff TS |
3093 | switch (sel) { |
3094 | case 0: | |
2e70f6ef PB |
3095 | /* Mark as an IO operation because we read the time. */ |
3096 | if (use_icount) | |
3097 | gen_io_start(); | |
d9bea114 | 3098 | gen_helper_mfc0_count(arg); |
2e70f6ef PB |
3099 | if (use_icount) { |
3100 | gen_io_end(); | |
3101 | ctx->bstate = BS_STOP; | |
3102 | } | |
2423f660 TS |
3103 | rn = "Count"; |
3104 | break; | |
3105 | /* 6,7 are implementation dependent */ | |
7a387fff TS |
3106 | default: |
3107 | goto die; | |
2423f660 | 3108 | } |
873eb012 TS |
3109 | break; |
3110 | case 10: | |
7a387fff TS |
3111 | switch (sel) { |
3112 | case 0: | |
d9bea114 AJ |
3113 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi)); |
3114 | tcg_gen_ext32s_tl(arg, arg); | |
2423f660 TS |
3115 | rn = "EntryHi"; |
3116 | break; | |
7a387fff TS |
3117 | default: |
3118 | goto die; | |
1579a72e | 3119 | } |
873eb012 TS |
3120 | break; |
3121 | case 11: | |
7a387fff TS |
3122 | switch (sel) { |
3123 | case 0: | |
d9bea114 | 3124 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare)); |
2423f660 TS |
3125 | rn = "Compare"; |
3126 | break; | |
3127 | /* 6,7 are implementation dependent */ | |
7a387fff TS |
3128 | default: |
3129 | goto die; | |
2423f660 | 3130 | } |
873eb012 TS |
3131 | break; |
3132 | case 12: | |
7a387fff TS |
3133 | switch (sel) { |
3134 | case 0: | |
d9bea114 | 3135 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status)); |
2423f660 TS |
3136 | rn = "Status"; |
3137 | break; | |
7a387fff | 3138 | case 1: |
e189e748 | 3139 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3140 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl)); |
2423f660 TS |
3141 | rn = "IntCtl"; |
3142 | break; | |
7a387fff | 3143 | case 2: |
e189e748 | 3144 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3145 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl)); |
2423f660 TS |
3146 | rn = "SRSCtl"; |
3147 | break; | |
7a387fff | 3148 | case 3: |
e189e748 | 3149 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3150 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap)); |
2423f660 | 3151 | rn = "SRSMap"; |
fd88b6ab | 3152 | break; |
7a387fff TS |
3153 | default: |
3154 | goto die; | |
3155 | } | |
873eb012 TS |
3156 | break; |
3157 | case 13: | |
7a387fff TS |
3158 | switch (sel) { |
3159 | case 0: | |
d9bea114 | 3160 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause)); |
2423f660 TS |
3161 | rn = "Cause"; |
3162 | break; | |
7a387fff TS |
3163 | default: |
3164 | goto die; | |
3165 | } | |
873eb012 TS |
3166 | break; |
3167 | case 14: | |
7a387fff TS |
3168 | switch (sel) { |
3169 | case 0: | |
d9bea114 AJ |
3170 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC)); |
3171 | tcg_gen_ext32s_tl(arg, arg); | |
2423f660 TS |
3172 | rn = "EPC"; |
3173 | break; | |
7a387fff TS |
3174 | default: |
3175 | goto die; | |
1579a72e | 3176 | } |
873eb012 TS |
3177 | break; |
3178 | case 15: | |
7a387fff TS |
3179 | switch (sel) { |
3180 | case 0: | |
d9bea114 | 3181 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid)); |
2423f660 TS |
3182 | rn = "PRid"; |
3183 | break; | |
7a387fff | 3184 | case 1: |
e189e748 | 3185 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3186 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase)); |
2423f660 TS |
3187 | rn = "EBase"; |
3188 | break; | |
7a387fff TS |
3189 | default: |
3190 | goto die; | |
3191 | } | |
873eb012 TS |
3192 | break; |
3193 | case 16: | |
3194 | switch (sel) { | |
3195 | case 0: | |
d9bea114 | 3196 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0)); |
873eb012 TS |
3197 | rn = "Config"; |
3198 | break; | |
3199 | case 1: | |
d9bea114 | 3200 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1)); |
873eb012 TS |
3201 | rn = "Config1"; |
3202 | break; | |
7a387fff | 3203 | case 2: |
d9bea114 | 3204 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2)); |
7a387fff TS |
3205 | rn = "Config2"; |
3206 | break; | |
3207 | case 3: | |
d9bea114 | 3208 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3)); |
7a387fff TS |
3209 | rn = "Config3"; |
3210 | break; | |
e397ee33 TS |
3211 | /* 4,5 are reserved */ |
3212 | /* 6,7 are implementation dependent */ | |
3213 | case 6: | |
d9bea114 | 3214 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6)); |
e397ee33 TS |
3215 | rn = "Config6"; |
3216 | break; | |
3217 | case 7: | |
d9bea114 | 3218 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7)); |
e397ee33 TS |
3219 | rn = "Config7"; |
3220 | break; | |
873eb012 | 3221 | default: |
873eb012 TS |
3222 | goto die; |
3223 | } | |
3224 | break; | |
3225 | case 17: | |
7a387fff TS |
3226 | switch (sel) { |
3227 | case 0: | |
d9bea114 | 3228 | gen_helper_mfc0_lladdr(arg); |
2423f660 TS |
3229 | rn = "LLAddr"; |
3230 | break; | |
7a387fff TS |
3231 | default: |
3232 | goto die; | |
3233 | } | |
873eb012 TS |
3234 | break; |
3235 | case 18: | |
7a387fff | 3236 | switch (sel) { |
fd88b6ab | 3237 | case 0 ... 7: |
d9bea114 | 3238 | gen_helper_1i(mfc0_watchlo, arg, sel); |
2423f660 TS |
3239 | rn = "WatchLo"; |
3240 | break; | |
7a387fff TS |
3241 | default: |
3242 | goto die; | |
3243 | } | |
873eb012 TS |
3244 | break; |
3245 | case 19: | |
7a387fff | 3246 | switch (sel) { |
fd88b6ab | 3247 | case 0 ...7: |
d9bea114 | 3248 | gen_helper_1i(mfc0_watchhi, arg, sel); |
2423f660 TS |
3249 | rn = "WatchHi"; |
3250 | break; | |
7a387fff TS |
3251 | default: |
3252 | goto die; | |
3253 | } | |
873eb012 | 3254 | break; |
8c0fdd85 | 3255 | case 20: |
7a387fff TS |
3256 | switch (sel) { |
3257 | case 0: | |
d26bc211 | 3258 | #if defined(TARGET_MIPS64) |
e189e748 | 3259 | check_insn(env, ctx, ISA_MIPS3); |
d9bea114 AJ |
3260 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext)); |
3261 | tcg_gen_ext32s_tl(arg, arg); | |
2423f660 TS |
3262 | rn = "XContext"; |
3263 | break; | |
703eaf37 | 3264 | #endif |
7a387fff TS |
3265 | default: |
3266 | goto die; | |
3267 | } | |
8c0fdd85 TS |
3268 | break; |
3269 | case 21: | |
7a387fff TS |
3270 | /* Officially reserved, but sel 0 is used for R1x000 framemask */ |
3271 | switch (sel) { | |
3272 | case 0: | |
d9bea114 | 3273 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask)); |
2423f660 TS |
3274 | rn = "Framemask"; |
3275 | break; | |
7a387fff TS |
3276 | default: |
3277 | goto die; | |
3278 | } | |
8c0fdd85 TS |
3279 | break; |
3280 | case 22: | |
d9bea114 | 3281 | tcg_gen_movi_tl(arg, 0); /* unimplemented */ |
2423f660 TS |
3282 | rn = "'Diagnostic"; /* implementation dependent */ |
3283 | break; | |
873eb012 | 3284 | case 23: |
7a387fff TS |
3285 | switch (sel) { |
3286 | case 0: | |
d9bea114 | 3287 | gen_helper_mfc0_debug(arg); /* EJTAG support */ |
2423f660 TS |
3288 | rn = "Debug"; |
3289 | break; | |
7a387fff | 3290 | case 1: |
d9bea114 | 3291 | // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */ |
2423f660 TS |
3292 | rn = "TraceControl"; |
3293 | // break; | |
7a387fff | 3294 | case 2: |
d9bea114 | 3295 | // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */ |
2423f660 TS |
3296 | rn = "TraceControl2"; |
3297 | // break; | |
7a387fff | 3298 | case 3: |
d9bea114 | 3299 | // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */ |
2423f660 TS |
3300 | rn = "UserTraceData"; |
3301 | // break; | |
7a387fff | 3302 | case 4: |
d9bea114 | 3303 | // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */ |
2423f660 TS |
3304 | rn = "TraceBPC"; |
3305 | // break; | |
7a387fff TS |
3306 | default: |
3307 | goto die; | |
3308 | } | |
873eb012 TS |
3309 | break; |
3310 | case 24: | |
7a387fff TS |
3311 | switch (sel) { |
3312 | case 0: | |
f0b3f3ae | 3313 | /* EJTAG support */ |
d9bea114 AJ |
3314 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC)); |
3315 | tcg_gen_ext32s_tl(arg, arg); | |
2423f660 TS |
3316 | rn = "DEPC"; |
3317 | break; | |
7a387fff TS |
3318 | default: |
3319 | goto die; | |
3320 | } | |
873eb012 | 3321 | break; |
8c0fdd85 | 3322 | case 25: |
7a387fff TS |
3323 | switch (sel) { |
3324 | case 0: | |
d9bea114 | 3325 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0)); |
2423f660 | 3326 | rn = "Performance0"; |
7a387fff TS |
3327 | break; |
3328 | case 1: | |
d9bea114 | 3329 | // gen_helper_mfc0_performance1(arg); |
2423f660 TS |
3330 | rn = "Performance1"; |
3331 | // break; | |
7a387fff | 3332 | case 2: |
d9bea114 | 3333 | // gen_helper_mfc0_performance2(arg); |
2423f660 TS |
3334 | rn = "Performance2"; |
3335 | // break; | |
7a387fff | 3336 | case 3: |
d9bea114 | 3337 | // gen_helper_mfc0_performance3(arg); |
2423f660 TS |
3338 | rn = "Performance3"; |
3339 | // break; | |
7a387fff | 3340 | case 4: |
d9bea114 | 3341 | // gen_helper_mfc0_performance4(arg); |
2423f660 TS |
3342 | rn = "Performance4"; |
3343 | // break; | |
7a387fff | 3344 | case 5: |
d9bea114 | 3345 | // gen_helper_mfc0_performance5(arg); |
2423f660 TS |
3346 | rn = "Performance5"; |
3347 | // break; | |
7a387fff | 3348 | case 6: |
d9bea114 | 3349 | // gen_helper_mfc0_performance6(arg); |
2423f660 TS |
3350 | rn = "Performance6"; |
3351 | // break; | |
7a387fff | 3352 | case 7: |
d9bea114 | 3353 | // gen_helper_mfc0_performance7(arg); |
2423f660 TS |
3354 | rn = "Performance7"; |
3355 | // break; | |
7a387fff TS |
3356 | default: |
3357 | goto die; | |
3358 | } | |
8c0fdd85 TS |
3359 | break; |
3360 | case 26: | |
d9bea114 | 3361 | tcg_gen_movi_tl(arg, 0); /* unimplemented */ |
da80682b AJ |
3362 | rn = "ECC"; |
3363 | break; | |
8c0fdd85 | 3364 | case 27: |
7a387fff | 3365 | switch (sel) { |
7a387fff | 3366 | case 0 ... 3: |
d9bea114 | 3367 | tcg_gen_movi_tl(arg, 0); /* unimplemented */ |
2423f660 TS |
3368 | rn = "CacheErr"; |
3369 | break; | |
7a387fff TS |
3370 | default: |
3371 | goto die; | |
3372 | } | |
8c0fdd85 | 3373 | break; |
873eb012 TS |
3374 | case 28: |
3375 | switch (sel) { | |
3376 | case 0: | |
7a387fff TS |
3377 | case 2: |
3378 | case 4: | |
3379 | case 6: | |
d9bea114 | 3380 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo)); |
873eb012 TS |
3381 | rn = "TagLo"; |
3382 | break; | |
3383 | case 1: | |
7a387fff TS |
3384 | case 3: |
3385 | case 5: | |
3386 | case 7: | |
d9bea114 | 3387 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo)); |
873eb012 TS |
3388 | rn = "DataLo"; |
3389 | break; | |
3390 | default: | |
873eb012 TS |
3391 | goto die; |
3392 | } | |
3393 | break; | |
8c0fdd85 | 3394 | case 29: |
7a387fff TS |
3395 | switch (sel) { |
3396 | case 0: | |
3397 | case 2: | |
3398 | case 4: | |
3399 | case 6: | |
d9bea114 | 3400 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi)); |
7a387fff TS |
3401 | rn = "TagHi"; |
3402 | break; | |
3403 | case 1: | |
3404 | case 3: | |
3405 | case 5: | |
3406 | case 7: | |
d9bea114 | 3407 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi)); |
7a387fff TS |
3408 | rn = "DataHi"; |
3409 | break; | |
3410 | default: | |
3411 | goto die; | |
3412 | } | |
8c0fdd85 | 3413 | break; |
873eb012 | 3414 | case 30: |
7a387fff TS |
3415 | switch (sel) { |
3416 | case 0: | |
d9bea114 AJ |
3417 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC)); |
3418 | tcg_gen_ext32s_tl(arg, arg); | |
2423f660 TS |
3419 | rn = "ErrorEPC"; |
3420 | break; | |
7a387fff TS |
3421 | default: |
3422 | goto die; | |
3423 | } | |
873eb012 TS |
3424 | break; |
3425 | case 31: | |
7a387fff TS |
3426 | switch (sel) { |
3427 | case 0: | |
f0b3f3ae | 3428 | /* EJTAG support */ |
d9bea114 | 3429 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE)); |
2423f660 TS |
3430 | rn = "DESAVE"; |
3431 | break; | |
7a387fff TS |
3432 | default: |
3433 | goto die; | |
3434 | } | |
873eb012 TS |
3435 | break; |
3436 | default: | |
873eb012 TS |
3437 | goto die; |
3438 | } | |
d12d51d5 | 3439 | LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel); |
873eb012 TS |
3440 | return; |
3441 | ||
3442 | die: | |
d12d51d5 | 3443 | LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel); |
873eb012 TS |
3444 | generate_exception(ctx, EXCP_RI); |
3445 | } | |
3446 | ||
d9bea114 | 3447 | static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) |
8c0fdd85 | 3448 | { |
7a387fff TS |
3449 | const char *rn = "invalid"; |
3450 | ||
e189e748 TS |
3451 | if (sel != 0) |
3452 | check_insn(env, ctx, ISA_MIPS32); | |
3453 | ||
2e70f6ef PB |
3454 | if (use_icount) |
3455 | gen_io_start(); | |
3456 | ||
8c0fdd85 TS |
3457 | switch (reg) { |
3458 | case 0: | |
7a387fff TS |
3459 | switch (sel) { |
3460 | case 0: | |
d9bea114 | 3461 | gen_helper_mtc0_index(arg); |
7a387fff TS |
3462 | rn = "Index"; |
3463 | break; | |
3464 | case 1: | |
7385ac0b | 3465 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3466 | gen_helper_mtc0_mvpcontrol(arg); |
7a387fff | 3467 | rn = "MVPControl"; |
ead9360e | 3468 | break; |
7a387fff | 3469 | case 2: |
7385ac0b | 3470 | check_insn(env, ctx, ASE_MT); |
ead9360e | 3471 | /* ignored */ |
7a387fff | 3472 | rn = "MVPConf0"; |
ead9360e | 3473 | break; |
7a387fff | 3474 | case 3: |
7385ac0b | 3475 | check_insn(env, ctx, ASE_MT); |
ead9360e | 3476 | /* ignored */ |
7a387fff | 3477 | rn = "MVPConf1"; |
ead9360e | 3478 | break; |
7a387fff TS |
3479 | default: |
3480 | goto die; | |
3481 | } | |
8c0fdd85 TS |
3482 | break; |
3483 | case 1: | |
7a387fff TS |
3484 | switch (sel) { |
3485 | case 0: | |
2423f660 | 3486 | /* ignored */ |
7a387fff | 3487 | rn = "Random"; |
2423f660 | 3488 | break; |
7a387fff | 3489 | case 1: |
7385ac0b | 3490 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3491 | gen_helper_mtc0_vpecontrol(arg); |
7a387fff | 3492 | rn = "VPEControl"; |
ead9360e | 3493 | break; |
7a387fff | 3494 | case 2: |
7385ac0b | 3495 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3496 | gen_helper_mtc0_vpeconf0(arg); |
7a387fff | 3497 | rn = "VPEConf0"; |
ead9360e | 3498 | break; |
7a387fff | 3499 | case 3: |
7385ac0b | 3500 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3501 | gen_helper_mtc0_vpeconf1(arg); |
7a387fff | 3502 | rn = "VPEConf1"; |
ead9360e | 3503 | break; |
7a387fff | 3504 | case 4: |
7385ac0b | 3505 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3506 | gen_helper_mtc0_yqmask(arg); |
7a387fff | 3507 | rn = "YQMask"; |
ead9360e | 3508 | break; |
7a387fff | 3509 | case 5: |
7385ac0b | 3510 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3511 | gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule)); |
7a387fff | 3512 | rn = "VPESchedule"; |
ead9360e | 3513 | break; |
7a387fff | 3514 | case 6: |
7385ac0b | 3515 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3516 | gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack)); |
7a387fff | 3517 | rn = "VPEScheFBack"; |
ead9360e | 3518 | break; |
7a387fff | 3519 | case 7: |
7385ac0b | 3520 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3521 | gen_helper_mtc0_vpeopt(arg); |
7a387fff | 3522 | rn = "VPEOpt"; |
ead9360e | 3523 | break; |
7a387fff TS |
3524 | default: |
3525 | goto die; | |
3526 | } | |
8c0fdd85 TS |
3527 | break; |
3528 | case 2: | |
7a387fff TS |
3529 | switch (sel) { |
3530 | case 0: | |
d9bea114 | 3531 | gen_helper_mtc0_entrylo0(arg); |
2423f660 TS |
3532 | rn = "EntryLo0"; |
3533 | break; | |
7a387fff | 3534 | case 1: |
7385ac0b | 3535 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3536 | gen_helper_mtc0_tcstatus(arg); |
2423f660 | 3537 | rn = "TCStatus"; |
ead9360e | 3538 | break; |
7a387fff | 3539 | case 2: |
7385ac0b | 3540 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3541 | gen_helper_mtc0_tcbind(arg); |
2423f660 | 3542 | rn = "TCBind"; |
ead9360e | 3543 | break; |
7a387fff | 3544 | case 3: |
7385ac0b | 3545 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3546 | gen_helper_mtc0_tcrestart(arg); |
2423f660 | 3547 | rn = "TCRestart"; |
ead9360e | 3548 | break; |
7a387fff | 3549 | case 4: |
7385ac0b | 3550 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3551 | gen_helper_mtc0_tchalt(arg); |
2423f660 | 3552 | rn = "TCHalt"; |
ead9360e | 3553 | break; |
7a387fff | 3554 | case 5: |
7385ac0b | 3555 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3556 | gen_helper_mtc0_tccontext(arg); |
2423f660 | 3557 | rn = "TCContext"; |
ead9360e | 3558 | break; |
7a387fff | 3559 | case 6: |
7385ac0b | 3560 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3561 | gen_helper_mtc0_tcschedule(arg); |
2423f660 | 3562 | rn = "TCSchedule"; |
ead9360e | 3563 | break; |
7a387fff | 3564 | case 7: |
7385ac0b | 3565 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 3566 | gen_helper_mtc0_tcschefback(arg); |
2423f660 | 3567 | rn = "TCScheFBack"; |
ead9360e | 3568 | break; |
7a387fff TS |
3569 | default: |
3570 | goto die; | |
3571 | } | |
8c0fdd85 TS |
3572 | break; |
3573 | case 3: | |
7a387fff TS |
3574 | switch (sel) { |
3575 | case 0: | |
d9bea114 | 3576 | gen_helper_mtc0_entrylo1(arg); |
2423f660 TS |
3577 | rn = "EntryLo1"; |
3578 | break; | |
7a387fff TS |
3579 | default: |
3580 | goto die; | |
876d4b07 | 3581 | } |
8c0fdd85 TS |
3582 | break; |
3583 | case 4: | |
7a387fff TS |
3584 | switch (sel) { |
3585 | case 0: | |
d9bea114 | 3586 | gen_helper_mtc0_context(arg); |
2423f660 TS |
3587 | rn = "Context"; |
3588 | break; | |
7a387fff | 3589 | case 1: |
d9bea114 | 3590 | // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */ |
2423f660 TS |
3591 | rn = "ContextConfig"; |
3592 | // break; | |
7a387fff TS |
3593 | default: |
3594 | goto die; | |
876d4b07 | 3595 | } |
8c0fdd85 TS |
3596 | break; |
3597 | case 5: | |
7a387fff TS |
3598 | switch (sel) { |
3599 | case 0: | |
d9bea114 | 3600 | gen_helper_mtc0_pagemask(arg); |
2423f660 TS |
3601 | rn = "PageMask"; |
3602 | break; | |
7a387fff | 3603 | case 1: |
e189e748 | 3604 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3605 | gen_helper_mtc0_pagegrain(arg); |
2423f660 TS |
3606 | rn = "PageGrain"; |
3607 | break; | |
7a387fff TS |
3608 | default: |
3609 | goto die; | |
876d4b07 | 3610 | } |
8c0fdd85 TS |
3611 | break; |
3612 | case 6: | |
7a387fff TS |
3613 | switch (sel) { |
3614 | case 0: | |
d9bea114 | 3615 | gen_helper_mtc0_wired(arg); |
2423f660 TS |
3616 | rn = "Wired"; |
3617 | break; | |
7a387fff | 3618 | case 1: |
e189e748 | 3619 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3620 | gen_helper_mtc0_srsconf0(arg); |
2423f660 | 3621 | rn = "SRSConf0"; |
ead9360e | 3622 | break; |
7a387fff | 3623 | case 2: |
e189e748 | 3624 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3625 | gen_helper_mtc0_srsconf1(arg); |
2423f660 | 3626 | rn = "SRSConf1"; |
ead9360e | 3627 | break; |
7a387fff | 3628 | case 3: |
e189e748 | 3629 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3630 | gen_helper_mtc0_srsconf2(arg); |
2423f660 | 3631 | rn = "SRSConf2"; |
ead9360e | 3632 | break; |
7a387fff | 3633 | case 4: |
e189e748 | 3634 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3635 | gen_helper_mtc0_srsconf3(arg); |
2423f660 | 3636 | rn = "SRSConf3"; |
ead9360e | 3637 | break; |
7a387fff | 3638 | case 5: |
e189e748 | 3639 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3640 | gen_helper_mtc0_srsconf4(arg); |
2423f660 | 3641 | rn = "SRSConf4"; |
ead9360e | 3642 | break; |
7a387fff TS |
3643 | default: |
3644 | goto die; | |
876d4b07 | 3645 | } |
8c0fdd85 TS |
3646 | break; |
3647 | case 7: | |
7a387fff TS |
3648 | switch (sel) { |
3649 | case 0: | |
e189e748 | 3650 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3651 | gen_helper_mtc0_hwrena(arg); |
2423f660 TS |
3652 | rn = "HWREna"; |
3653 | break; | |
7a387fff TS |
3654 | default: |
3655 | goto die; | |
876d4b07 | 3656 | } |
8c0fdd85 TS |
3657 | break; |
3658 | case 8: | |
7a387fff | 3659 | /* ignored */ |
f0b3f3ae | 3660 | rn = "BadVAddr"; |
8c0fdd85 TS |
3661 | break; |
3662 | case 9: | |
7a387fff TS |
3663 | switch (sel) { |
3664 | case 0: | |
d9bea114 | 3665 | gen_helper_mtc0_count(arg); |
2423f660 TS |
3666 | rn = "Count"; |
3667 | break; | |
876d4b07 | 3668 | /* 6,7 are implementation dependent */ |
7a387fff TS |
3669 | default: |
3670 | goto die; | |
876d4b07 | 3671 | } |
8c0fdd85 TS |
3672 | break; |
3673 | case 10: | |
7a387fff TS |
3674 | switch (sel) { |
3675 | case 0: | |
d9bea114 | 3676 | gen_helper_mtc0_entryhi(arg); |
2423f660 TS |
3677 | rn = "EntryHi"; |
3678 | break; | |
7a387fff TS |
3679 | default: |
3680 | goto die; | |
876d4b07 | 3681 | } |
8c0fdd85 TS |
3682 | break; |
3683 | case 11: | |
7a387fff TS |
3684 | switch (sel) { |
3685 | case 0: | |
d9bea114 | 3686 | gen_helper_mtc0_compare(arg); |
2423f660 TS |
3687 | rn = "Compare"; |
3688 | break; | |
3689 | /* 6,7 are implementation dependent */ | |
7a387fff TS |
3690 | default: |
3691 | goto die; | |
876d4b07 | 3692 | } |
8c0fdd85 TS |
3693 | break; |
3694 | case 12: | |
7a387fff TS |
3695 | switch (sel) { |
3696 | case 0: | |
867abc7e | 3697 | save_cpu_state(ctx, 1); |
d9bea114 | 3698 | gen_helper_mtc0_status(arg); |
8487327a TS |
3699 | /* BS_STOP isn't good enough here, hflags may have changed. */ |
3700 | gen_save_pc(ctx->pc + 4); | |
3701 | ctx->bstate = BS_EXCP; | |
2423f660 TS |
3702 | rn = "Status"; |
3703 | break; | |
7a387fff | 3704 | case 1: |
e189e748 | 3705 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3706 | gen_helper_mtc0_intctl(arg); |
8487327a TS |
3707 | /* Stop translation as we may have switched the execution mode */ |
3708 | ctx->bstate = BS_STOP; | |
2423f660 TS |
3709 | rn = "IntCtl"; |
3710 | break; | |
7a387fff | 3711 | case 2: |
e189e748 | 3712 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3713 | gen_helper_mtc0_srsctl(arg); |
8487327a TS |
3714 | /* Stop translation as we may have switched the execution mode */ |
3715 | ctx->bstate = BS_STOP; | |
2423f660 TS |
3716 | rn = "SRSCtl"; |
3717 | break; | |
7a387fff | 3718 | case 3: |
e189e748 | 3719 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3720 | gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap)); |
8487327a TS |
3721 | /* Stop translation as we may have switched the execution mode */ |
3722 | ctx->bstate = BS_STOP; | |
2423f660 | 3723 | rn = "SRSMap"; |
fd88b6ab | 3724 | break; |
7a387fff TS |
3725 | default: |
3726 | goto die; | |
876d4b07 | 3727 | } |
8c0fdd85 TS |
3728 | break; |
3729 | case 13: | |
7a387fff TS |
3730 | switch (sel) { |
3731 | case 0: | |
867abc7e | 3732 | save_cpu_state(ctx, 1); |
d9bea114 | 3733 | gen_helper_mtc0_cause(arg); |
2423f660 TS |
3734 | rn = "Cause"; |
3735 | break; | |
7a387fff TS |
3736 | default: |
3737 | goto die; | |
876d4b07 | 3738 | } |
8c0fdd85 TS |
3739 | break; |
3740 | case 14: | |
7a387fff TS |
3741 | switch (sel) { |
3742 | case 0: | |
d9bea114 | 3743 | gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC)); |
2423f660 TS |
3744 | rn = "EPC"; |
3745 | break; | |
7a387fff TS |
3746 | default: |
3747 | goto die; | |
876d4b07 | 3748 | } |
8c0fdd85 TS |
3749 | break; |
3750 | case 15: | |
7a387fff TS |
3751 | switch (sel) { |
3752 | case 0: | |
2423f660 TS |
3753 | /* ignored */ |
3754 | rn = "PRid"; | |
3755 | break; | |
7a387fff | 3756 | case 1: |
e189e748 | 3757 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 3758 | gen_helper_mtc0_ebase(arg); |
2423f660 TS |
3759 | rn = "EBase"; |
3760 | break; | |
7a387fff TS |
3761 | default: |
3762 | goto die; | |
1579a72e | 3763 | } |
8c0fdd85 TS |
3764 | break; |
3765 | case 16: | |
3766 | switch (sel) { | |
3767 | case 0: | |
d9bea114 | 3768 | gen_helper_mtc0_config0(arg); |
7a387fff | 3769 | rn = "Config"; |
2423f660 TS |
3770 | /* Stop translation as we may have switched the execution mode */ |
3771 | ctx->bstate = BS_STOP; | |
7a387fff TS |
3772 | break; |
3773 | case 1: | |
e397ee33 | 3774 | /* ignored, read only */ |
7a387fff TS |
3775 | rn = "Config1"; |
3776 | break; | |
3777 | case 2: | |
d9bea114 | 3778 | gen_helper_mtc0_config2(arg); |
7a387fff | 3779 | rn = "Config2"; |
2423f660 TS |
3780 | /* Stop translation as we may have switched the execution mode */ |
3781 | ctx->bstate = BS_STOP; | |
8c0fdd85 | 3782 | break; |
7a387fff | 3783 | case 3: |
e397ee33 | 3784 | /* ignored, read only */ |
7a387fff TS |
3785 | rn = "Config3"; |
3786 | break; | |
e397ee33 TS |
3787 | /* 4,5 are reserved */ |
3788 | /* 6,7 are implementation dependent */ | |
3789 | case 6: | |
3790 | /* ignored */ | |
3791 | rn = "Config6"; | |
3792 | break; | |
3793 | case 7: | |
3794 | /* ignored */ | |
3795 | rn = "Config7"; | |
3796 | break; | |
8c0fdd85 TS |
3797 | default: |
3798 | rn = "Invalid config selector"; | |
3799 | goto die; | |
3800 | } | |
3801 | break; | |
3802 | case 17: | |
7a387fff TS |
3803 | switch (sel) { |
3804 | case 0: | |
2423f660 TS |
3805 | /* ignored */ |
3806 | rn = "LLAddr"; | |
3807 | break; | |
7a387fff TS |
3808 | default: |
3809 | goto die; | |
3810 | } | |
8c0fdd85 TS |
3811 | break; |
3812 | case 18: | |
7a387fff | 3813 | switch (sel) { |
fd88b6ab | 3814 | case 0 ... 7: |
d9bea114 | 3815 | gen_helper_1i(mtc0_watchlo, arg, sel); |
2423f660 TS |
3816 | rn = "WatchLo"; |
3817 | break; | |
7a387fff TS |
3818 | default: |
3819 | goto die; | |
3820 | } | |
8c0fdd85 TS |
3821 | break; |
3822 | case 19: | |
7a387fff | 3823 | switch (sel) { |
fd88b6ab | 3824 | case 0 ... 7: |
d9bea114 | 3825 | gen_helper_1i(mtc0_watchhi, arg, sel); |
2423f660 TS |
3826 | rn = "WatchHi"; |
3827 | break; | |
7a387fff TS |
3828 | default: |
3829 | goto die; | |
3830 | } | |
8c0fdd85 TS |
3831 | break; |
3832 | case 20: | |
7a387fff TS |
3833 | switch (sel) { |
3834 | case 0: | |
d26bc211 | 3835 | #if defined(TARGET_MIPS64) |
e189e748 | 3836 | check_insn(env, ctx, ISA_MIPS3); |
d9bea114 | 3837 | gen_helper_mtc0_xcontext(arg); |
2423f660 TS |
3838 | rn = "XContext"; |
3839 | break; | |
703eaf37 | 3840 | #endif |
7a387fff TS |
3841 | default: |
3842 | goto die; | |
3843 | } | |
8c0fdd85 TS |
3844 | break; |
3845 | case 21: | |
7a387fff TS |
3846 | /* Officially reserved, but sel 0 is used for R1x000 framemask */ |
3847 | switch (sel) { | |
3848 | case 0: | |
d9bea114 | 3849 | gen_helper_mtc0_framemask(arg); |
2423f660 TS |
3850 | rn = "Framemask"; |
3851 | break; | |
7a387fff TS |
3852 | default: |
3853 | goto die; | |
3854 | } | |
3855 | break; | |
8c0fdd85 | 3856 | case 22: |
7a387fff TS |
3857 | /* ignored */ |
3858 | rn = "Diagnostic"; /* implementation dependent */ | |
2423f660 | 3859 | break; |
8c0fdd85 | 3860 | case 23: |
7a387fff TS |
3861 | switch (sel) { |
3862 | case 0: | |
d9bea114 | 3863 | gen_helper_mtc0_debug(arg); /* EJTAG support */ |
8487327a TS |
3864 | /* BS_STOP isn't good enough here, hflags may have changed. */ |
3865 | gen_save_pc(ctx->pc + 4); | |
3866 | ctx->bstate = BS_EXCP; | |
2423f660 TS |
3867 | rn = "Debug"; |
3868 | break; | |
7a387fff | 3869 | case 1: |
d9bea114 | 3870 | // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */ |
2423f660 | 3871 | rn = "TraceControl"; |
8487327a TS |
3872 | /* Stop translation as we may have switched the execution mode */ |
3873 | ctx->bstate = BS_STOP; | |
2423f660 | 3874 | // break; |
7a387fff | 3875 | case 2: |
d9bea114 | 3876 | // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */ |
2423f660 | 3877 | rn = "TraceControl2"; |
8487327a TS |
3878 | /* Stop translation as we may have switched the execution mode */ |
3879 | ctx->bstate = BS_STOP; | |
2423f660 | 3880 | // break; |
7a387fff | 3881 | case 3: |
8487327a TS |
3882 | /* Stop translation as we may have switched the execution mode */ |
3883 | ctx->bstate = BS_STOP; | |
d9bea114 | 3884 | // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */ |
2423f660 | 3885 | rn = "UserTraceData"; |
8487327a TS |
3886 | /* Stop translation as we may have switched the execution mode */ |
3887 | ctx->bstate = BS_STOP; | |
2423f660 | 3888 | // break; |
7a387fff | 3889 | case 4: |
d9bea114 | 3890 | // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */ |
8487327a TS |
3891 | /* Stop translation as we may have switched the execution mode */ |
3892 | ctx->bstate = BS_STOP; | |
2423f660 TS |
3893 | rn = "TraceBPC"; |
3894 | // break; | |
7a387fff TS |
3895 | default: |
3896 | goto die; | |
3897 | } | |
8c0fdd85 TS |
3898 | break; |
3899 | case 24: | |
7a387fff TS |
3900 | switch (sel) { |
3901 | case 0: | |
f1aa6320 | 3902 | /* EJTAG support */ |
d9bea114 | 3903 | gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC)); |
2423f660 TS |
3904 | rn = "DEPC"; |
3905 | break; | |
7a387fff TS |
3906 | default: |
3907 | goto die; | |
3908 | } | |
8c0fdd85 TS |
3909 | break; |
3910 | case 25: | |
7a387fff TS |
3911 | switch (sel) { |
3912 | case 0: | |
d9bea114 | 3913 | gen_helper_mtc0_performance0(arg); |
2423f660 TS |
3914 | rn = "Performance0"; |
3915 | break; | |
7a387fff | 3916 | case 1: |
d9bea114 | 3917 | // gen_helper_mtc0_performance1(arg); |
2423f660 TS |
3918 | rn = "Performance1"; |
3919 | // break; | |
7a387fff | 3920 | case 2: |
d9bea114 | 3921 | // gen_helper_mtc0_performance2(arg); |
2423f660 TS |
3922 | rn = "Performance2"; |
3923 | // break; | |
7a387fff | 3924 | case 3: |
d9bea114 | 3925 | // gen_helper_mtc0_performance3(arg); |
2423f660 TS |
3926 | rn = "Performance3"; |
3927 | // break; | |
7a387fff | 3928 | case 4: |
d9bea114 | 3929 | // gen_helper_mtc0_performance4(arg); |
2423f660 TS |
3930 | rn = "Performance4"; |
3931 | // break; | |
7a387fff | 3932 | case 5: |
d9bea114 | 3933 | // gen_helper_mtc0_performance5(arg); |
2423f660 TS |
3934 | rn = "Performance5"; |
3935 | // break; | |
7a387fff | 3936 | case 6: |
d9bea114 | 3937 | // gen_helper_mtc0_performance6(arg); |
2423f660 TS |
3938 | rn = "Performance6"; |
3939 | // break; | |
7a387fff | 3940 | case 7: |
d9bea114 | 3941 | // gen_helper_mtc0_performance7(arg); |
2423f660 TS |
3942 | rn = "Performance7"; |
3943 | // break; | |
7a387fff TS |
3944 | default: |
3945 | goto die; | |
3946 | } | |
8c0fdd85 TS |
3947 | break; |
3948 | case 26: | |
2423f660 | 3949 | /* ignored */ |
8c0fdd85 | 3950 | rn = "ECC"; |
2423f660 | 3951 | break; |
8c0fdd85 | 3952 | case 27: |
7a387fff TS |
3953 | switch (sel) { |
3954 | case 0 ... 3: | |
2423f660 TS |
3955 | /* ignored */ |
3956 | rn = "CacheErr"; | |
3957 | break; | |
7a387fff TS |
3958 | default: |
3959 | goto die; | |
3960 | } | |
8c0fdd85 TS |
3961 | break; |
3962 | case 28: | |
3963 | switch (sel) { | |
3964 | case 0: | |
7a387fff TS |
3965 | case 2: |
3966 | case 4: | |
3967 | case 6: | |
d9bea114 | 3968 | gen_helper_mtc0_taglo(arg); |
8c0fdd85 TS |
3969 | rn = "TagLo"; |
3970 | break; | |
7a387fff TS |
3971 | case 1: |
3972 | case 3: | |
3973 | case 5: | |
3974 | case 7: | |
d9bea114 | 3975 | gen_helper_mtc0_datalo(arg); |
7a387fff TS |
3976 | rn = "DataLo"; |
3977 | break; | |
8c0fdd85 | 3978 | default: |
8c0fdd85 TS |
3979 | goto die; |
3980 | } | |
3981 | break; | |
3982 | case 29: | |
7a387fff TS |
3983 | switch (sel) { |
3984 | case 0: | |
3985 | case 2: | |
3986 | case 4: | |
3987 | case 6: | |
d9bea114 | 3988 | gen_helper_mtc0_taghi(arg); |
7a387fff TS |
3989 | rn = "TagHi"; |
3990 | break; | |
3991 | case 1: | |
3992 | case 3: | |
3993 | case 5: | |
3994 | case 7: | |
d9bea114 | 3995 | gen_helper_mtc0_datahi(arg); |
7a387fff TS |
3996 | rn = "DataHi"; |
3997 | break; | |
3998 | default: | |
3999 | rn = "invalid sel"; | |
4000 | goto die; | |
4001 | } | |
8c0fdd85 TS |
4002 | break; |
4003 | case 30: | |
7a387fff TS |
4004 | switch (sel) { |
4005 | case 0: | |
d9bea114 | 4006 | gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC)); |
2423f660 TS |
4007 | rn = "ErrorEPC"; |
4008 | break; | |
7a387fff TS |
4009 | default: |
4010 | goto die; | |
4011 | } | |
8c0fdd85 TS |
4012 | break; |
4013 | case 31: | |
7a387fff TS |
4014 | switch (sel) { |
4015 | case 0: | |
f1aa6320 | 4016 | /* EJTAG support */ |
d9bea114 | 4017 | gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE)); |
2423f660 TS |
4018 | rn = "DESAVE"; |
4019 | break; | |
7a387fff TS |
4020 | default: |
4021 | goto die; | |
4022 | } | |
2423f660 TS |
4023 | /* Stop translation as we may have switched the execution mode */ |
4024 | ctx->bstate = BS_STOP; | |
8c0fdd85 TS |
4025 | break; |
4026 | default: | |
8c0fdd85 TS |
4027 | goto die; |
4028 | } | |
d12d51d5 | 4029 | LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); |
bf20dc07 | 4030 | /* For simplicity assume that all writes can cause interrupts. */ |
2e70f6ef PB |
4031 | if (use_icount) { |
4032 | gen_io_end(); | |
4033 | ctx->bstate = BS_STOP; | |
4034 | } | |
8c0fdd85 TS |
4035 | return; |
4036 | ||
4037 | die: | |
d12d51d5 | 4038 | LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel); |
8c0fdd85 TS |
4039 | generate_exception(ctx, EXCP_RI); |
4040 | } | |
4041 | ||
d26bc211 | 4042 | #if defined(TARGET_MIPS64) |
d9bea114 | 4043 | static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) |
9c2149c8 TS |
4044 | { |
4045 | const char *rn = "invalid"; | |
4046 | ||
e189e748 TS |
4047 | if (sel != 0) |
4048 | check_insn(env, ctx, ISA_MIPS64); | |
4049 | ||
9c2149c8 TS |
4050 | switch (reg) { |
4051 | case 0: | |
4052 | switch (sel) { | |
4053 | case 0: | |
d9bea114 | 4054 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index)); |
9c2149c8 TS |
4055 | rn = "Index"; |
4056 | break; | |
4057 | case 1: | |
7385ac0b | 4058 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4059 | gen_helper_mfc0_mvpcontrol(arg); |
9c2149c8 | 4060 | rn = "MVPControl"; |
ead9360e | 4061 | break; |
9c2149c8 | 4062 | case 2: |
7385ac0b | 4063 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4064 | gen_helper_mfc0_mvpconf0(arg); |
9c2149c8 | 4065 | rn = "MVPConf0"; |
ead9360e | 4066 | break; |
9c2149c8 | 4067 | case 3: |
7385ac0b | 4068 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4069 | gen_helper_mfc0_mvpconf1(arg); |
9c2149c8 | 4070 | rn = "MVPConf1"; |
ead9360e | 4071 | break; |
9c2149c8 TS |
4072 | default: |
4073 | goto die; | |
4074 | } | |
4075 | break; | |
4076 | case 1: | |
4077 | switch (sel) { | |
4078 | case 0: | |
d9bea114 | 4079 | gen_helper_mfc0_random(arg); |
9c2149c8 | 4080 | rn = "Random"; |
2423f660 | 4081 | break; |
9c2149c8 | 4082 | case 1: |
7385ac0b | 4083 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4084 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl)); |
9c2149c8 | 4085 | rn = "VPEControl"; |
ead9360e | 4086 | break; |
9c2149c8 | 4087 | case 2: |
7385ac0b | 4088 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4089 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0)); |
9c2149c8 | 4090 | rn = "VPEConf0"; |
ead9360e | 4091 | break; |
9c2149c8 | 4092 | case 3: |
7385ac0b | 4093 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4094 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1)); |
9c2149c8 | 4095 | rn = "VPEConf1"; |
ead9360e | 4096 | break; |
9c2149c8 | 4097 | case 4: |
7385ac0b | 4098 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4099 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_YQMask)); |
9c2149c8 | 4100 | rn = "YQMask"; |
ead9360e | 4101 | break; |
9c2149c8 | 4102 | case 5: |
7385ac0b | 4103 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4104 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule)); |
9c2149c8 | 4105 | rn = "VPESchedule"; |
ead9360e | 4106 | break; |
9c2149c8 | 4107 | case 6: |
7385ac0b | 4108 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4109 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); |
9c2149c8 | 4110 | rn = "VPEScheFBack"; |
ead9360e | 4111 | break; |
9c2149c8 | 4112 | case 7: |
7385ac0b | 4113 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4114 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt)); |
9c2149c8 | 4115 | rn = "VPEOpt"; |
ead9360e | 4116 | break; |
9c2149c8 TS |
4117 | default: |
4118 | goto die; | |
4119 | } | |
4120 | break; | |
4121 | case 2: | |
4122 | switch (sel) { | |
4123 | case 0: | |
d9bea114 | 4124 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0)); |
2423f660 TS |
4125 | rn = "EntryLo0"; |
4126 | break; | |
9c2149c8 | 4127 | case 1: |
7385ac0b | 4128 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4129 | gen_helper_mfc0_tcstatus(arg); |
2423f660 | 4130 | rn = "TCStatus"; |
ead9360e | 4131 | break; |
9c2149c8 | 4132 | case 2: |
7385ac0b | 4133 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4134 | gen_helper_mfc0_tcbind(arg); |
2423f660 | 4135 | rn = "TCBind"; |
ead9360e | 4136 | break; |
9c2149c8 | 4137 | case 3: |
7385ac0b | 4138 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4139 | gen_helper_dmfc0_tcrestart(arg); |
2423f660 | 4140 | rn = "TCRestart"; |
ead9360e | 4141 | break; |
9c2149c8 | 4142 | case 4: |
7385ac0b | 4143 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4144 | gen_helper_dmfc0_tchalt(arg); |
2423f660 | 4145 | rn = "TCHalt"; |
ead9360e | 4146 | break; |
9c2149c8 | 4147 | case 5: |
7385ac0b | 4148 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4149 | gen_helper_dmfc0_tccontext(arg); |
2423f660 | 4150 | rn = "TCContext"; |
ead9360e | 4151 | break; |
9c2149c8 | 4152 | case 6: |
7385ac0b | 4153 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4154 | gen_helper_dmfc0_tcschedule(arg); |
2423f660 | 4155 | rn = "TCSchedule"; |
ead9360e | 4156 | break; |
9c2149c8 | 4157 | case 7: |
7385ac0b | 4158 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4159 | gen_helper_dmfc0_tcschefback(arg); |
2423f660 | 4160 | rn = "TCScheFBack"; |
ead9360e | 4161 | break; |
9c2149c8 TS |
4162 | default: |
4163 | goto die; | |
4164 | } | |
4165 | break; | |
4166 | case 3: | |
4167 | switch (sel) { | |
4168 | case 0: | |
d9bea114 | 4169 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1)); |
2423f660 TS |
4170 | rn = "EntryLo1"; |
4171 | break; | |
9c2149c8 TS |
4172 | default: |
4173 | goto die; | |
1579a72e | 4174 | } |
9c2149c8 TS |
4175 | break; |
4176 | case 4: | |
4177 | switch (sel) { | |
4178 | case 0: | |
d9bea114 | 4179 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context)); |
2423f660 TS |
4180 | rn = "Context"; |
4181 | break; | |
9c2149c8 | 4182 | case 1: |
d9bea114 | 4183 | // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */ |
2423f660 TS |
4184 | rn = "ContextConfig"; |
4185 | // break; | |
9c2149c8 TS |
4186 | default: |
4187 | goto die; | |
876d4b07 | 4188 | } |
9c2149c8 TS |
4189 | break; |
4190 | case 5: | |
4191 | switch (sel) { | |
4192 | case 0: | |
d9bea114 | 4193 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask)); |
2423f660 TS |
4194 | rn = "PageMask"; |
4195 | break; | |
9c2149c8 | 4196 | case 1: |
e189e748 | 4197 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4198 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain)); |
2423f660 TS |
4199 | rn = "PageGrain"; |
4200 | break; | |
9c2149c8 TS |
4201 | default: |
4202 | goto die; | |
876d4b07 | 4203 | } |
9c2149c8 TS |
4204 | break; |
4205 | case 6: | |
4206 | switch (sel) { | |
4207 | case 0: | |
d9bea114 | 4208 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired)); |
2423f660 TS |
4209 | rn = "Wired"; |
4210 | break; | |
9c2149c8 | 4211 | case 1: |
e189e748 | 4212 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4213 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0)); |
2423f660 | 4214 | rn = "SRSConf0"; |
ead9360e | 4215 | break; |
9c2149c8 | 4216 | case 2: |
e189e748 | 4217 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4218 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1)); |
2423f660 | 4219 | rn = "SRSConf1"; |
ead9360e | 4220 | break; |
9c2149c8 | 4221 | case 3: |
e189e748 | 4222 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4223 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2)); |
2423f660 | 4224 | rn = "SRSConf2"; |
ead9360e | 4225 | break; |
9c2149c8 | 4226 | case 4: |
e189e748 | 4227 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4228 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3)); |
2423f660 | 4229 | rn = "SRSConf3"; |
ead9360e | 4230 | break; |
9c2149c8 | 4231 | case 5: |
e189e748 | 4232 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4233 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4)); |
2423f660 | 4234 | rn = "SRSConf4"; |
ead9360e | 4235 | break; |
9c2149c8 TS |
4236 | default: |
4237 | goto die; | |
876d4b07 | 4238 | } |
9c2149c8 TS |
4239 | break; |
4240 | case 7: | |
4241 | switch (sel) { | |
4242 | case 0: | |
e189e748 | 4243 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4244 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna)); |
2423f660 TS |
4245 | rn = "HWREna"; |
4246 | break; | |
9c2149c8 TS |
4247 | default: |
4248 | goto die; | |
876d4b07 | 4249 | } |
9c2149c8 TS |
4250 | break; |
4251 | case 8: | |
4252 | switch (sel) { | |
4253 | case 0: | |
d9bea114 | 4254 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr)); |
f0b3f3ae | 4255 | rn = "BadVAddr"; |
2423f660 | 4256 | break; |
9c2149c8 TS |
4257 | default: |
4258 | goto die; | |
876d4b07 | 4259 | } |
9c2149c8 TS |
4260 | break; |
4261 | case 9: | |
4262 | switch (sel) { | |
4263 | case 0: | |
2e70f6ef PB |
4264 | /* Mark as an IO operation because we read the time. */ |
4265 | if (use_icount) | |
4266 | gen_io_start(); | |
d9bea114 | 4267 | gen_helper_mfc0_count(arg); |
2e70f6ef PB |
4268 | if (use_icount) { |
4269 | gen_io_end(); | |
4270 | ctx->bstate = BS_STOP; | |
4271 | } | |
2423f660 TS |
4272 | rn = "Count"; |
4273 | break; | |
4274 | /* 6,7 are implementation dependent */ | |
9c2149c8 TS |
4275 | default: |
4276 | goto die; | |
876d4b07 | 4277 | } |
9c2149c8 TS |
4278 | break; |
4279 | case 10: | |
4280 | switch (sel) { | |
4281 | case 0: | |
d9bea114 | 4282 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi)); |
2423f660 TS |
4283 | rn = "EntryHi"; |
4284 | break; | |
9c2149c8 TS |
4285 | default: |
4286 | goto die; | |
876d4b07 | 4287 | } |
9c2149c8 TS |
4288 | break; |
4289 | case 11: | |
4290 | switch (sel) { | |
4291 | case 0: | |
d9bea114 | 4292 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare)); |
2423f660 TS |
4293 | rn = "Compare"; |
4294 | break; | |
876d4b07 | 4295 | /* 6,7 are implementation dependent */ |
9c2149c8 TS |
4296 | default: |
4297 | goto die; | |
876d4b07 | 4298 | } |
9c2149c8 TS |
4299 | break; |
4300 | case 12: | |
4301 | switch (sel) { | |
4302 | case 0: | |
d9bea114 | 4303 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status)); |
2423f660 TS |
4304 | rn = "Status"; |
4305 | break; | |
9c2149c8 | 4306 | case 1: |
e189e748 | 4307 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4308 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl)); |
2423f660 TS |
4309 | rn = "IntCtl"; |
4310 | break; | |
9c2149c8 | 4311 | case 2: |
e189e748 | 4312 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4313 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl)); |
2423f660 TS |
4314 | rn = "SRSCtl"; |
4315 | break; | |
9c2149c8 | 4316 | case 3: |
e189e748 | 4317 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4318 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap)); |
2423f660 TS |
4319 | rn = "SRSMap"; |
4320 | break; | |
9c2149c8 TS |
4321 | default: |
4322 | goto die; | |
876d4b07 | 4323 | } |
9c2149c8 TS |
4324 | break; |
4325 | case 13: | |
4326 | switch (sel) { | |
4327 | case 0: | |
d9bea114 | 4328 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause)); |
2423f660 TS |
4329 | rn = "Cause"; |
4330 | break; | |
9c2149c8 TS |
4331 | default: |
4332 | goto die; | |
876d4b07 | 4333 | } |
9c2149c8 TS |
4334 | break; |
4335 | case 14: | |
4336 | switch (sel) { | |
4337 | case 0: | |
d9bea114 | 4338 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC)); |
2423f660 TS |
4339 | rn = "EPC"; |
4340 | break; | |
9c2149c8 TS |
4341 | default: |
4342 | goto die; | |
876d4b07 | 4343 | } |
9c2149c8 TS |
4344 | break; |
4345 | case 15: | |
4346 | switch (sel) { | |
4347 | case 0: | |
d9bea114 | 4348 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid)); |
2423f660 TS |
4349 | rn = "PRid"; |
4350 | break; | |
9c2149c8 | 4351 | case 1: |
e189e748 | 4352 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4353 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase)); |
2423f660 TS |
4354 | rn = "EBase"; |
4355 | break; | |
9c2149c8 TS |
4356 | default: |
4357 | goto die; | |
876d4b07 | 4358 | } |
9c2149c8 TS |
4359 | break; |
4360 | case 16: | |
4361 | switch (sel) { | |
4362 | case 0: | |
d9bea114 | 4363 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0)); |
9c2149c8 TS |
4364 | rn = "Config"; |
4365 | break; | |
4366 | case 1: | |
d9bea114 | 4367 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1)); |
9c2149c8 TS |
4368 | rn = "Config1"; |
4369 | break; | |
4370 | case 2: | |
d9bea114 | 4371 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2)); |
9c2149c8 TS |
4372 | rn = "Config2"; |
4373 | break; | |
4374 | case 3: | |
d9bea114 | 4375 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3)); |
9c2149c8 TS |
4376 | rn = "Config3"; |
4377 | break; | |
4378 | /* 6,7 are implementation dependent */ | |
f0b3f3ae | 4379 | case 6: |
d9bea114 | 4380 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6)); |
f0b3f3ae TS |
4381 | rn = "Config6"; |
4382 | break; | |
4383 | case 7: | |
d9bea114 | 4384 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7)); |
f0b3f3ae TS |
4385 | rn = "Config7"; |
4386 | break; | |
9c2149c8 TS |
4387 | default: |
4388 | goto die; | |
4389 | } | |
4390 | break; | |
4391 | case 17: | |
4392 | switch (sel) { | |
4393 | case 0: | |
d9bea114 | 4394 | gen_helper_dmfc0_lladdr(arg); |
2423f660 TS |
4395 | rn = "LLAddr"; |
4396 | break; | |
9c2149c8 TS |
4397 | default: |
4398 | goto die; | |
4399 | } | |
4400 | break; | |
4401 | case 18: | |
4402 | switch (sel) { | |
fd88b6ab | 4403 | case 0 ... 7: |
d9bea114 | 4404 | gen_helper_1i(dmfc0_watchlo, arg, sel); |
2423f660 TS |
4405 | rn = "WatchLo"; |
4406 | break; | |
9c2149c8 TS |
4407 | default: |
4408 | goto die; | |
4409 | } | |
4410 | break; | |
4411 | case 19: | |
4412 | switch (sel) { | |
fd88b6ab | 4413 | case 0 ... 7: |
d9bea114 | 4414 | gen_helper_1i(mfc0_watchhi, arg, sel); |
2423f660 TS |
4415 | rn = "WatchHi"; |
4416 | break; | |
9c2149c8 TS |
4417 | default: |
4418 | goto die; | |
4419 | } | |
4420 | break; | |
4421 | case 20: | |
4422 | switch (sel) { | |
4423 | case 0: | |
e189e748 | 4424 | check_insn(env, ctx, ISA_MIPS3); |
d9bea114 | 4425 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext)); |
2423f660 TS |
4426 | rn = "XContext"; |
4427 | break; | |
9c2149c8 TS |
4428 | default: |
4429 | goto die; | |
4430 | } | |
4431 | break; | |
4432 | case 21: | |
4433 | /* Officially reserved, but sel 0 is used for R1x000 framemask */ | |
4434 | switch (sel) { | |
4435 | case 0: | |
d9bea114 | 4436 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask)); |
2423f660 TS |
4437 | rn = "Framemask"; |
4438 | break; | |
9c2149c8 TS |
4439 | default: |
4440 | goto die; | |
4441 | } | |
4442 | break; | |
4443 | case 22: | |
d9bea114 | 4444 | tcg_gen_movi_tl(arg, 0); /* unimplemented */ |
2423f660 TS |
4445 | rn = "'Diagnostic"; /* implementation dependent */ |
4446 | break; | |
9c2149c8 TS |
4447 | case 23: |
4448 | switch (sel) { | |
4449 | case 0: | |
d9bea114 | 4450 | gen_helper_mfc0_debug(arg); /* EJTAG support */ |
2423f660 TS |
4451 | rn = "Debug"; |
4452 | break; | |
9c2149c8 | 4453 | case 1: |
d9bea114 | 4454 | // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */ |
2423f660 TS |
4455 | rn = "TraceControl"; |
4456 | // break; | |
9c2149c8 | 4457 | case 2: |
d9bea114 | 4458 | // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */ |
2423f660 TS |
4459 | rn = "TraceControl2"; |
4460 | // break; | |
9c2149c8 | 4461 | case 3: |
d9bea114 | 4462 | // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */ |
2423f660 TS |
4463 | rn = "UserTraceData"; |
4464 | // break; | |
9c2149c8 | 4465 | case 4: |
d9bea114 | 4466 | // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */ |
2423f660 TS |
4467 | rn = "TraceBPC"; |
4468 | // break; | |
9c2149c8 TS |
4469 | default: |
4470 | goto die; | |
4471 | } | |
4472 | break; | |
4473 | case 24: | |
4474 | switch (sel) { | |
4475 | case 0: | |
f0b3f3ae | 4476 | /* EJTAG support */ |
d9bea114 | 4477 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC)); |
2423f660 TS |
4478 | rn = "DEPC"; |
4479 | break; | |
9c2149c8 TS |
4480 | default: |
4481 | goto die; | |
4482 | } | |
4483 | break; | |
4484 | case 25: | |
4485 | switch (sel) { | |
4486 | case 0: | |
d9bea114 | 4487 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0)); |
2423f660 | 4488 | rn = "Performance0"; |
9c2149c8 TS |
4489 | break; |
4490 | case 1: | |
d9bea114 | 4491 | // gen_helper_dmfc0_performance1(arg); |
2423f660 TS |
4492 | rn = "Performance1"; |
4493 | // break; | |
9c2149c8 | 4494 | case 2: |
d9bea114 | 4495 | // gen_helper_dmfc0_performance2(arg); |
2423f660 TS |
4496 | rn = "Performance2"; |
4497 | // break; | |
9c2149c8 | 4498 | case 3: |
d9bea114 | 4499 | // gen_helper_dmfc0_performance3(arg); |
2423f660 TS |
4500 | rn = "Performance3"; |
4501 | // break; | |
9c2149c8 | 4502 | case 4: |
d9bea114 | 4503 | // gen_helper_dmfc0_performance4(arg); |
2423f660 TS |
4504 | rn = "Performance4"; |
4505 | // break; | |
9c2149c8 | 4506 | case 5: |
d9bea114 | 4507 | // gen_helper_dmfc0_performance5(arg); |
2423f660 TS |
4508 | rn = "Performance5"; |
4509 | // break; | |
9c2149c8 | 4510 | case 6: |
d9bea114 | 4511 | // gen_helper_dmfc0_performance6(arg); |
2423f660 TS |
4512 | rn = "Performance6"; |
4513 | // break; | |
9c2149c8 | 4514 | case 7: |
d9bea114 | 4515 | // gen_helper_dmfc0_performance7(arg); |
2423f660 TS |
4516 | rn = "Performance7"; |
4517 | // break; | |
9c2149c8 TS |
4518 | default: |
4519 | goto die; | |
4520 | } | |
4521 | break; | |
4522 | case 26: | |
d9bea114 | 4523 | tcg_gen_movi_tl(arg, 0); /* unimplemented */ |
da80682b AJ |
4524 | rn = "ECC"; |
4525 | break; | |
9c2149c8 TS |
4526 | case 27: |
4527 | switch (sel) { | |
4528 | /* ignored */ | |
4529 | case 0 ... 3: | |
d9bea114 | 4530 | tcg_gen_movi_tl(arg, 0); /* unimplemented */ |
2423f660 TS |
4531 | rn = "CacheErr"; |
4532 | break; | |
9c2149c8 TS |
4533 | default: |
4534 | goto die; | |
4535 | } | |
4536 | break; | |
4537 | case 28: | |
4538 | switch (sel) { | |
4539 | case 0: | |
4540 | case 2: | |
4541 | case 4: | |
4542 | case 6: | |
d9bea114 | 4543 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo)); |
9c2149c8 TS |
4544 | rn = "TagLo"; |
4545 | break; | |
4546 | case 1: | |
4547 | case 3: | |
4548 | case 5: | |
4549 | case 7: | |
d9bea114 | 4550 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo)); |
9c2149c8 TS |
4551 | rn = "DataLo"; |
4552 | break; | |
4553 | default: | |
4554 | goto die; | |
4555 | } | |
4556 | break; | |
4557 | case 29: | |
4558 | switch (sel) { | |
4559 | case 0: | |
4560 | case 2: | |
4561 | case 4: | |
4562 | case 6: | |
d9bea114 | 4563 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi)); |
9c2149c8 TS |
4564 | rn = "TagHi"; |
4565 | break; | |
4566 | case 1: | |
4567 | case 3: | |
4568 | case 5: | |
4569 | case 7: | |
d9bea114 | 4570 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi)); |
9c2149c8 TS |
4571 | rn = "DataHi"; |
4572 | break; | |
4573 | default: | |
4574 | goto die; | |
4575 | } | |
4576 | break; | |
4577 | case 30: | |
4578 | switch (sel) { | |
4579 | case 0: | |
d9bea114 | 4580 | tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC)); |
2423f660 TS |
4581 | rn = "ErrorEPC"; |
4582 | break; | |
9c2149c8 TS |
4583 | default: |
4584 | goto die; | |
4585 | } | |
4586 | break; | |
4587 | case 31: | |
4588 | switch (sel) { | |
4589 | case 0: | |
f0b3f3ae | 4590 | /* EJTAG support */ |
d9bea114 | 4591 | gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE)); |
2423f660 TS |
4592 | rn = "DESAVE"; |
4593 | break; | |
9c2149c8 TS |
4594 | default: |
4595 | goto die; | |
4596 | } | |
4597 | break; | |
4598 | default: | |
876d4b07 | 4599 | goto die; |
9c2149c8 | 4600 | } |
d12d51d5 | 4601 | LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel); |
9c2149c8 TS |
4602 | return; |
4603 | ||
4604 | die: | |
d12d51d5 | 4605 | LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel); |
9c2149c8 TS |
4606 | generate_exception(ctx, EXCP_RI); |
4607 | } | |
4608 | ||
d9bea114 | 4609 | static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel) |
9c2149c8 TS |
4610 | { |
4611 | const char *rn = "invalid"; | |
4612 | ||
e189e748 TS |
4613 | if (sel != 0) |
4614 | check_insn(env, ctx, ISA_MIPS64); | |
4615 | ||
2e70f6ef PB |
4616 | if (use_icount) |
4617 | gen_io_start(); | |
4618 | ||
9c2149c8 TS |
4619 | switch (reg) { |
4620 | case 0: | |
4621 | switch (sel) { | |
4622 | case 0: | |
d9bea114 | 4623 | gen_helper_mtc0_index(arg); |
9c2149c8 TS |
4624 | rn = "Index"; |
4625 | break; | |
4626 | case 1: | |
7385ac0b | 4627 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4628 | gen_helper_mtc0_mvpcontrol(arg); |
9c2149c8 | 4629 | rn = "MVPControl"; |
ead9360e | 4630 | break; |
9c2149c8 | 4631 | case 2: |
7385ac0b | 4632 | check_insn(env, ctx, ASE_MT); |
ead9360e | 4633 | /* ignored */ |
9c2149c8 | 4634 | rn = "MVPConf0"; |
ead9360e | 4635 | break; |
9c2149c8 | 4636 | case 3: |
7385ac0b | 4637 | check_insn(env, ctx, ASE_MT); |
ead9360e | 4638 | /* ignored */ |
9c2149c8 | 4639 | rn = "MVPConf1"; |
ead9360e | 4640 | break; |
9c2149c8 TS |
4641 | default: |
4642 | goto die; | |
4643 | } | |
4644 | break; | |
4645 | case 1: | |
4646 | switch (sel) { | |
4647 | case 0: | |
2423f660 | 4648 | /* ignored */ |
9c2149c8 | 4649 | rn = "Random"; |
2423f660 | 4650 | break; |
9c2149c8 | 4651 | case 1: |
7385ac0b | 4652 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4653 | gen_helper_mtc0_vpecontrol(arg); |
9c2149c8 | 4654 | rn = "VPEControl"; |
ead9360e | 4655 | break; |
9c2149c8 | 4656 | case 2: |
7385ac0b | 4657 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4658 | gen_helper_mtc0_vpeconf0(arg); |
9c2149c8 | 4659 | rn = "VPEConf0"; |
ead9360e | 4660 | break; |
9c2149c8 | 4661 | case 3: |
7385ac0b | 4662 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4663 | gen_helper_mtc0_vpeconf1(arg); |
9c2149c8 | 4664 | rn = "VPEConf1"; |
ead9360e | 4665 | break; |
9c2149c8 | 4666 | case 4: |
7385ac0b | 4667 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4668 | gen_helper_mtc0_yqmask(arg); |
9c2149c8 | 4669 | rn = "YQMask"; |
ead9360e | 4670 | break; |
9c2149c8 | 4671 | case 5: |
7385ac0b | 4672 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4673 | tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPESchedule)); |
9c2149c8 | 4674 | rn = "VPESchedule"; |
ead9360e | 4675 | break; |
9c2149c8 | 4676 | case 6: |
7385ac0b | 4677 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4678 | tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); |
9c2149c8 | 4679 | rn = "VPEScheFBack"; |
ead9360e | 4680 | break; |
9c2149c8 | 4681 | case 7: |
7385ac0b | 4682 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4683 | gen_helper_mtc0_vpeopt(arg); |
9c2149c8 | 4684 | rn = "VPEOpt"; |
ead9360e | 4685 | break; |
9c2149c8 TS |
4686 | default: |
4687 | goto die; | |
4688 | } | |
4689 | break; | |
4690 | case 2: | |
4691 | switch (sel) { | |
4692 | case 0: | |
d9bea114 | 4693 | gen_helper_mtc0_entrylo0(arg); |
2423f660 TS |
4694 | rn = "EntryLo0"; |
4695 | break; | |
9c2149c8 | 4696 | case 1: |
7385ac0b | 4697 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4698 | gen_helper_mtc0_tcstatus(arg); |
2423f660 | 4699 | rn = "TCStatus"; |
ead9360e | 4700 | break; |
9c2149c8 | 4701 | case 2: |
7385ac0b | 4702 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4703 | gen_helper_mtc0_tcbind(arg); |
2423f660 | 4704 | rn = "TCBind"; |
ead9360e | 4705 | break; |
9c2149c8 | 4706 | case 3: |
7385ac0b | 4707 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4708 | gen_helper_mtc0_tcrestart(arg); |
2423f660 | 4709 | rn = "TCRestart"; |
ead9360e | 4710 | break; |
9c2149c8 | 4711 | case 4: |
7385ac0b | 4712 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4713 | gen_helper_mtc0_tchalt(arg); |
2423f660 | 4714 | rn = "TCHalt"; |
ead9360e | 4715 | break; |
9c2149c8 | 4716 | case 5: |
7385ac0b | 4717 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4718 | gen_helper_mtc0_tccontext(arg); |
2423f660 | 4719 | rn = "TCContext"; |
ead9360e | 4720 | break; |
9c2149c8 | 4721 | case 6: |
7385ac0b | 4722 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4723 | gen_helper_mtc0_tcschedule(arg); |
2423f660 | 4724 | rn = "TCSchedule"; |
ead9360e | 4725 | break; |
9c2149c8 | 4726 | case 7: |
7385ac0b | 4727 | check_insn(env, ctx, ASE_MT); |
d9bea114 | 4728 | gen_helper_mtc0_tcschefback(arg); |
2423f660 | 4729 | rn = "TCScheFBack"; |
ead9360e | 4730 | break; |
9c2149c8 TS |
4731 | default: |
4732 | goto die; | |
4733 | } | |
4734 | break; | |
4735 | case 3: | |
4736 | switch (sel) { | |
4737 | case 0: | |
d9bea114 | 4738 | gen_helper_mtc0_entrylo1(arg); |
2423f660 TS |
4739 | rn = "EntryLo1"; |
4740 | break; | |
9c2149c8 TS |
4741 | default: |
4742 | goto die; | |
876d4b07 | 4743 | } |
9c2149c8 TS |
4744 | break; |
4745 | case 4: | |
4746 | switch (sel) { | |
4747 | case 0: | |
d9bea114 | 4748 | gen_helper_mtc0_context(arg); |
2423f660 TS |
4749 | rn = "Context"; |
4750 | break; | |
9c2149c8 | 4751 | case 1: |
d9bea114 | 4752 | // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */ |
2423f660 TS |
4753 | rn = "ContextConfig"; |
4754 | // break; | |
9c2149c8 TS |
4755 | default: |
4756 | goto die; | |
876d4b07 | 4757 | } |
9c2149c8 TS |
4758 | break; |
4759 | case 5: | |
4760 | switch (sel) { | |
4761 | case 0: | |
d9bea114 | 4762 | gen_helper_mtc0_pagemask(arg); |
2423f660 TS |
4763 | rn = "PageMask"; |
4764 | break; | |
9c2149c8 | 4765 | case 1: |
e189e748 | 4766 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4767 | gen_helper_mtc0_pagegrain(arg); |
2423f660 TS |
4768 | rn = "PageGrain"; |
4769 | break; | |
9c2149c8 TS |
4770 | default: |
4771 | goto die; | |
876d4b07 | 4772 | } |
9c2149c8 TS |
4773 | break; |
4774 | case 6: | |
4775 | switch (sel) { | |
4776 | case 0: | |
d9bea114 | 4777 | gen_helper_mtc0_wired(arg); |
2423f660 TS |
4778 | rn = "Wired"; |
4779 | break; | |
9c2149c8 | 4780 | case 1: |
e189e748 | 4781 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4782 | gen_helper_mtc0_srsconf0(arg); |
2423f660 | 4783 | rn = "SRSConf0"; |
ead9360e | 4784 | break; |
9c2149c8 | 4785 | case 2: |
e189e748 | 4786 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4787 | gen_helper_mtc0_srsconf1(arg); |
2423f660 | 4788 | rn = "SRSConf1"; |
ead9360e | 4789 | break; |
9c2149c8 | 4790 | case 3: |
e189e748 | 4791 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4792 | gen_helper_mtc0_srsconf2(arg); |
2423f660 | 4793 | rn = "SRSConf2"; |
ead9360e | 4794 | break; |
9c2149c8 | 4795 | case 4: |
e189e748 | 4796 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4797 | gen_helper_mtc0_srsconf3(arg); |
2423f660 | 4798 | rn = "SRSConf3"; |
ead9360e | 4799 | break; |
9c2149c8 | 4800 | case 5: |
e189e748 | 4801 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4802 | gen_helper_mtc0_srsconf4(arg); |
2423f660 | 4803 | rn = "SRSConf4"; |
ead9360e | 4804 | break; |
9c2149c8 TS |
4805 | default: |
4806 | goto die; | |
876d4b07 | 4807 | } |
9c2149c8 TS |
4808 | break; |
4809 | case 7: | |
4810 | switch (sel) { | |
4811 | case 0: | |
e189e748 | 4812 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4813 | gen_helper_mtc0_hwrena(arg); |
2423f660 TS |
4814 | rn = "HWREna"; |
4815 | break; | |
9c2149c8 TS |
4816 | default: |
4817 | goto die; | |
876d4b07 | 4818 | } |
9c2149c8 TS |
4819 | break; |
4820 | case 8: | |
4821 | /* ignored */ | |
f0b3f3ae | 4822 | rn = "BadVAddr"; |
9c2149c8 TS |
4823 | break; |
4824 | case 9: | |
4825 | switch (sel) { | |
4826 | case 0: | |
d9bea114 | 4827 | gen_helper_mtc0_count(arg); |
2423f660 TS |
4828 | rn = "Count"; |
4829 | break; | |
876d4b07 | 4830 | /* 6,7 are implementation dependent */ |
9c2149c8 TS |
4831 | default: |
4832 | goto die; | |
876d4b07 TS |
4833 | } |
4834 | /* Stop translation as we may have switched the execution mode */ | |
4835 | ctx->bstate = BS_STOP; | |
9c2149c8 TS |
4836 | break; |
4837 | case 10: | |
4838 | switch (sel) { | |
4839 | case 0: | |
d9bea114 | 4840 | gen_helper_mtc0_entryhi(arg); |
2423f660 TS |
4841 | rn = "EntryHi"; |
4842 | break; | |
9c2149c8 TS |
4843 | default: |
4844 | goto die; | |
876d4b07 | 4845 | } |
9c2149c8 TS |
4846 | break; |
4847 | case 11: | |
4848 | switch (sel) { | |
4849 | case 0: | |
d9bea114 | 4850 | gen_helper_mtc0_compare(arg); |
2423f660 TS |
4851 | rn = "Compare"; |
4852 | break; | |
876d4b07 | 4853 | /* 6,7 are implementation dependent */ |
9c2149c8 TS |
4854 | default: |
4855 | goto die; | |
876d4b07 | 4856 | } |
de9a95f0 AJ |
4857 | /* Stop translation as we may have switched the execution mode */ |
4858 | ctx->bstate = BS_STOP; | |
9c2149c8 TS |
4859 | break; |
4860 | case 12: | |
4861 | switch (sel) { | |
4862 | case 0: | |
867abc7e | 4863 | save_cpu_state(ctx, 1); |
d9bea114 | 4864 | gen_helper_mtc0_status(arg); |
8487327a TS |
4865 | /* BS_STOP isn't good enough here, hflags may have changed. */ |
4866 | gen_save_pc(ctx->pc + 4); | |
4867 | ctx->bstate = BS_EXCP; | |
2423f660 TS |
4868 | rn = "Status"; |
4869 | break; | |
9c2149c8 | 4870 | case 1: |
e189e748 | 4871 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4872 | gen_helper_mtc0_intctl(arg); |
8487327a TS |
4873 | /* Stop translation as we may have switched the execution mode */ |
4874 | ctx->bstate = BS_STOP; | |
2423f660 TS |
4875 | rn = "IntCtl"; |
4876 | break; | |
9c2149c8 | 4877 | case 2: |
e189e748 | 4878 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4879 | gen_helper_mtc0_srsctl(arg); |
8487327a TS |
4880 | /* Stop translation as we may have switched the execution mode */ |
4881 | ctx->bstate = BS_STOP; | |
2423f660 TS |
4882 | rn = "SRSCtl"; |
4883 | break; | |
9c2149c8 | 4884 | case 3: |
e189e748 | 4885 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4886 | gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap)); |
8487327a TS |
4887 | /* Stop translation as we may have switched the execution mode */ |
4888 | ctx->bstate = BS_STOP; | |
2423f660 TS |
4889 | rn = "SRSMap"; |
4890 | break; | |
4891 | default: | |
9c2149c8 | 4892 | goto die; |
876d4b07 | 4893 | } |
9c2149c8 TS |
4894 | break; |
4895 | case 13: | |
4896 | switch (sel) { | |
4897 | case 0: | |
867abc7e | 4898 | save_cpu_state(ctx, 1); |
d9bea114 | 4899 | gen_helper_mtc0_cause(arg); |
2423f660 TS |
4900 | rn = "Cause"; |
4901 | break; | |
9c2149c8 TS |
4902 | default: |
4903 | goto die; | |
876d4b07 | 4904 | } |
9c2149c8 TS |
4905 | break; |
4906 | case 14: | |
4907 | switch (sel) { | |
4908 | case 0: | |
d9bea114 | 4909 | tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC)); |
2423f660 TS |
4910 | rn = "EPC"; |
4911 | break; | |
9c2149c8 TS |
4912 | default: |
4913 | goto die; | |
876d4b07 | 4914 | } |
9c2149c8 TS |
4915 | break; |
4916 | case 15: | |
4917 | switch (sel) { | |
4918 | case 0: | |
2423f660 TS |
4919 | /* ignored */ |
4920 | rn = "PRid"; | |
4921 | break; | |
9c2149c8 | 4922 | case 1: |
e189e748 | 4923 | check_insn(env, ctx, ISA_MIPS32R2); |
d9bea114 | 4924 | gen_helper_mtc0_ebase(arg); |
2423f660 TS |
4925 | rn = "EBase"; |
4926 | break; | |
9c2149c8 TS |
4927 | default: |
4928 | goto die; | |
876d4b07 | 4929 | } |
9c2149c8 TS |
4930 | break; |
4931 | case 16: | |
4932 | switch (sel) { | |
4933 | case 0: | |
d9bea114 | 4934 | gen_helper_mtc0_config0(arg); |
9c2149c8 | 4935 | rn = "Config"; |
2423f660 TS |
4936 | /* Stop translation as we may have switched the execution mode */ |
4937 | ctx->bstate = BS_STOP; | |
9c2149c8 TS |
4938 | break; |
4939 | case 1: | |
1fc7bf6e | 4940 | /* ignored, read only */ |
9c2149c8 TS |
4941 | rn = "Config1"; |
4942 | break; | |
4943 | case 2: | |
d9bea114 | 4944 | gen_helper_mtc0_config2(arg); |
9c2149c8 | 4945 | rn = "Config2"; |
2423f660 TS |
4946 | /* Stop translation as we may have switched the execution mode */ |
4947 | ctx->bstate = BS_STOP; | |
9c2149c8 TS |
4948 | break; |
4949 | case 3: | |
2423f660 | 4950 | /* ignored */ |
9c2149c8 TS |
4951 | rn = "Config3"; |
4952 | break; | |
4953 | /* 6,7 are implementation dependent */ | |
4954 | default: | |
4955 | rn = "Invalid config selector"; | |
4956 | goto die; | |
4957 | } | |
9c2149c8 TS |
4958 | break; |
4959 | case 17: | |
4960 | switch (sel) { | |
4961 | case 0: | |
2423f660 TS |
4962 | /* ignored */ |
4963 | rn = "LLAddr"; | |
4964 | break; | |
9c2149c8 TS |
4965 | default: |
4966 | goto die; | |
4967 | } | |
4968 | break; | |
4969 | case 18: | |
4970 | switch (sel) { | |
fd88b6ab | 4971 | case 0 ... 7: |
d9bea114 | 4972 | gen_helper_1i(mtc0_watchlo, arg, sel); |
2423f660 TS |
4973 | rn = "WatchLo"; |
4974 | break; | |
9c2149c8 TS |
4975 | default: |
4976 | goto die; | |
4977 | } | |
4978 | break; | |
4979 | case 19: | |
4980 | switch (sel) { | |
fd88b6ab | 4981 | case 0 ... 7: |
d9bea114 | 4982 | gen_helper_1i(mtc0_watchhi, arg, sel); |
2423f660 TS |
4983 | rn = "WatchHi"; |
4984 | break; | |
9c2149c8 TS |
4985 | default: |
4986 | goto die; | |
4987 | } | |
4988 | break; | |
4989 | case 20: | |
4990 | switch (sel) { | |
4991 | case 0: | |
e189e748 | 4992 | check_insn(env, ctx, ISA_MIPS3); |
d9bea114 | 4993 | gen_helper_mtc0_xcontext(arg); |
2423f660 TS |
4994 | rn = "XContext"; |
4995 | break; | |
9c2149c8 TS |
4996 | default: |
4997 | goto die; | |
4998 | } | |
4999 | break; | |
5000 | case 21: | |
5001 | /* Officially reserved, but sel 0 is used for R1x000 framemask */ | |
5002 | switch (sel) { | |
5003 | case 0: | |
d9bea114 | 5004 | gen_helper_mtc0_framemask(arg); |
2423f660 TS |
5005 | rn = "Framemask"; |
5006 | break; | |
9c2149c8 TS |
5007 | default: |
5008 | goto die; | |
5009 | } | |
5010 | break; | |
5011 | case 22: | |
5012 | /* ignored */ | |
5013 | rn = "Diagnostic"; /* implementation dependent */ | |
876d4b07 | 5014 | break; |
9c2149c8 TS |
5015 | case 23: |
5016 | switch (sel) { | |
5017 | case 0: | |
d9bea114 | 5018 | gen_helper_mtc0_debug(arg); /* EJTAG support */ |
8487327a TS |
5019 | /* BS_STOP isn't good enough here, hflags may have changed. */ |
5020 | gen_save_pc(ctx->pc + 4); | |
5021 | ctx->bstate = BS_EXCP; | |
2423f660 TS |
5022 | rn = "Debug"; |
5023 | break; | |
9c2149c8 | 5024 | case 1: |
d9bea114 | 5025 | // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */ |
8487327a TS |
5026 | /* Stop translation as we may have switched the execution mode */ |
5027 | ctx->bstate = BS_STOP; | |
2423f660 TS |
5028 | rn = "TraceControl"; |
5029 | // break; | |
9c2149c8 | 5030 | case 2: |
d9bea114 | 5031 | // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */ |
8487327a TS |
5032 | /* Stop translation as we may have switched the execution mode */ |
5033 | ctx->bstate = BS_STOP; | |
2423f660 TS |
5034 | rn = "TraceControl2"; |
5035 | // break; | |
9c2149c8 | 5036 | case 3: |
d9bea114 | 5037 | // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */ |
8487327a TS |
5038 | /* Stop translation as we may have switched the execution mode */ |
5039 | ctx->bstate = BS_STOP; | |
2423f660 TS |
5040 | rn = "UserTraceData"; |
5041 | // break; | |
9c2149c8 | 5042 | case 4: |
d9bea114 | 5043 | // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */ |
8487327a TS |
5044 | /* Stop translation as we may have switched the execution mode */ |
5045 | ctx->bstate = BS_STOP; | |
2423f660 TS |
5046 | rn = "TraceBPC"; |
5047 | // break; | |
9c2149c8 TS |
5048 | default: |
5049 | goto die; | |
5050 | } | |
9c2149c8 TS |
5051 | break; |
5052 | case 24: | |
5053 | switch (sel) { | |
5054 | case 0: | |
f1aa6320 | 5055 | /* EJTAG support */ |
d9bea114 | 5056 | tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC)); |
2423f660 TS |
5057 | rn = "DEPC"; |
5058 | break; | |
9c2149c8 TS |
5059 | default: |
5060 | goto die; | |
5061 | } | |
5062 | break; | |
5063 | case 25: | |
5064 | switch (sel) { | |
5065 | case 0: | |
d9bea114 | 5066 | gen_helper_mtc0_performance0(arg); |
2423f660 TS |
5067 | rn = "Performance0"; |
5068 | break; | |
9c2149c8 | 5069 | case 1: |
d9bea114 | 5070 | // gen_helper_mtc0_performance1(arg); |
2423f660 TS |
5071 | rn = "Performance1"; |
5072 | // break; | |
9c2149c8 | 5073 | case 2: |
d9bea114 | 5074 | // gen_helper_mtc0_performance2(arg); |
2423f660 TS |
5075 | rn = "Performance2"; |
5076 | // break; | |
9c2149c8 | 5077 | case 3: |
d9bea114 | 5078 | // gen_helper_mtc0_performance3(arg); |
2423f660 TS |
5079 | rn = "Performance3"; |
5080 | // break; | |
9c2149c8 | 5081 | case 4: |
d9bea114 | 5082 | // gen_helper_mtc0_performance4(arg); |
2423f660 TS |
5083 | rn = "Performance4"; |
5084 | // break; | |
9c2149c8 | 5085 | case 5: |
d9bea114 | 5086 | // gen_helper_mtc0_performance5(arg); |
2423f660 TS |
5087 | rn = "Performance5"; |
5088 | // break; | |
9c2149c8 | 5089 | case 6: |
d9bea114 | 5090 | // gen_helper_mtc0_performance6(arg); |
2423f660 TS |
5091 | rn = "Performance6"; |
5092 | // break; | |
9c2149c8 | 5093 | case 7: |
d9bea114 | 5094 | // gen_helper_mtc0_performance7(arg); |
2423f660 TS |
5095 | rn = "Performance7"; |
5096 | // break; | |
9c2149c8 TS |
5097 | default: |
5098 | goto die; | |
5099 | } | |
876d4b07 | 5100 | break; |
9c2149c8 | 5101 | case 26: |
876d4b07 | 5102 | /* ignored */ |
9c2149c8 | 5103 | rn = "ECC"; |
876d4b07 | 5104 | break; |
9c2149c8 TS |
5105 | case 27: |
5106 | switch (sel) { | |
5107 | case 0 ... 3: | |
2423f660 TS |
5108 | /* ignored */ |
5109 | rn = "CacheErr"; | |
5110 | break; | |
9c2149c8 TS |
5111 | default: |
5112 | goto die; | |
5113 | } | |
876d4b07 | 5114 | break; |
9c2149c8 TS |
5115 | case 28: |
5116 | switch (sel) { | |
5117 | case 0: | |
5118 | case 2: | |
5119 | case 4: | |
5120 | case 6: | |
d9bea114 | 5121 | gen_helper_mtc0_taglo(arg); |
9c2149c8 TS |
5122 | rn = "TagLo"; |
5123 | break; | |
5124 | case 1: | |
5125 | case 3: | |
5126 | case 5: | |
5127 | case 7: | |
d9bea114 | 5128 | gen_helper_mtc0_datalo(arg); |
9c2149c8 TS |
5129 | rn = "DataLo"; |
5130 | break; | |
5131 | default: | |
5132 | goto die; | |
5133 | } | |
5134 | break; | |
5135 | case 29: | |
5136 | switch (sel) { | |
5137 | case 0: | |
5138 | case 2: | |
5139 | case 4: | |
5140 | case 6: | |
d9bea114 | 5141 | gen_helper_mtc0_taghi(arg); |
9c2149c8 TS |
5142 | rn = "TagHi"; |
5143 | break; | |
5144 | case 1: | |
5145 | case 3: | |
5146 | case 5: | |
5147 | case 7: | |
d9bea114 | 5148 | gen_helper_mtc0_datahi(arg); |
9c2149c8 TS |
5149 | rn = "DataHi"; |
5150 | break; | |
5151 | default: | |
5152 | rn = "invalid sel"; | |
5153 | goto die; | |
5154 | } | |
876d4b07 | 5155 | break; |
9c2149c8 TS |
5156 | case 30: |
5157 | switch (sel) { | |
5158 | case 0: | |
d9bea114 | 5159 | tcg_gen_st_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC)); |
2423f660 TS |
5160 | rn = "ErrorEPC"; |
5161 | break; | |
9c2149c8 TS |
5162 | default: |
5163 | goto die; | |
5164 | } | |
5165 | break; | |
5166 | case 31: | |
5167 | switch (sel) { | |
5168 | case 0: | |
f1aa6320 | 5169 | /* EJTAG support */ |
d9bea114 | 5170 | gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE)); |
2423f660 TS |
5171 | rn = "DESAVE"; |
5172 | break; | |
9c2149c8 TS |
5173 | default: |
5174 | goto die; | |
5175 | } | |
876d4b07 TS |
5176 | /* Stop translation as we may have switched the execution mode */ |
5177 | ctx->bstate = BS_STOP; | |
9c2149c8 TS |
5178 | break; |
5179 | default: | |
876d4b07 | 5180 | goto die; |
9c2149c8 | 5181 | } |
d12d51d5 | 5182 | LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); |
bf20dc07 | 5183 | /* For simplicity assume that all writes can cause interrupts. */ |
2e70f6ef PB |
5184 | if (use_icount) { |
5185 | gen_io_end(); | |
5186 | ctx->bstate = BS_STOP; | |
5187 | } | |
9c2149c8 TS |
5188 | return; |
5189 | ||
5190 | die: | |
d12d51d5 | 5191 | LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel); |
9c2149c8 TS |
5192 | generate_exception(ctx, EXCP_RI); |
5193 | } | |
d26bc211 | 5194 | #endif /* TARGET_MIPS64 */ |
9c2149c8 | 5195 | |
6c5c1e20 | 5196 | static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd, |
ead9360e TS |
5197 | int u, int sel, int h) |
5198 | { | |
5199 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
a7812ae4 | 5200 | TCGv t0 = tcg_temp_local_new(); |
ead9360e TS |
5201 | |
5202 | if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && | |
b5dc7732 TS |
5203 | ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != |
5204 | (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) | |
1a3fd9c3 | 5205 | tcg_gen_movi_tl(t0, -1); |
ead9360e TS |
5206 | else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > |
5207 | (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) | |
1a3fd9c3 | 5208 | tcg_gen_movi_tl(t0, -1); |
ead9360e TS |
5209 | else if (u == 0) { |
5210 | switch (rt) { | |
5211 | case 2: | |
5212 | switch (sel) { | |
5213 | case 1: | |
a7812ae4 | 5214 | gen_helper_mftc0_tcstatus(t0); |
ead9360e TS |
5215 | break; |
5216 | case 2: | |
a7812ae4 | 5217 | gen_helper_mftc0_tcbind(t0); |
ead9360e TS |
5218 | break; |
5219 | case 3: | |
a7812ae4 | 5220 | gen_helper_mftc0_tcrestart(t0); |
ead9360e TS |
5221 | break; |
5222 | case 4: | |
a7812ae4 | 5223 | gen_helper_mftc0_tchalt(t0); |
ead9360e TS |
5224 | break; |
5225 | case 5: | |
a7812ae4 | 5226 | gen_helper_mftc0_tccontext(t0); |
ead9360e TS |
5227 | break; |
5228 | case 6: | |
a7812ae4 | 5229 | gen_helper_mftc0_tcschedule(t0); |
ead9360e TS |
5230 | break; |
5231 | case 7: | |
a7812ae4 | 5232 | gen_helper_mftc0_tcschefback(t0); |
ead9360e TS |
5233 | break; |
5234 | default: | |
1a3fd9c3 | 5235 | gen_mfc0(env, ctx, t0, rt, sel); |
ead9360e TS |
5236 | break; |
5237 | } | |
5238 | break; | |
5239 | case 10: | |
5240 | switch (sel) { | |
5241 | case 0: | |
a7812ae4 | 5242 | gen_helper_mftc0_entryhi(t0); |
ead9360e TS |
5243 | break; |
5244 | default: | |
1a3fd9c3 | 5245 | gen_mfc0(env, ctx, t0, rt, sel); |
ead9360e TS |
5246 | break; |
5247 | } | |
5248 | case 12: | |
5249 | switch (sel) { | |
5250 | case 0: | |
a7812ae4 | 5251 | gen_helper_mftc0_status(t0); |
ead9360e TS |
5252 | break; |
5253 | default: | |
1a3fd9c3 | 5254 | gen_mfc0(env, ctx, t0, rt, sel); |
ead9360e TS |
5255 | break; |
5256 | } | |
5257 | case 23: | |
5258 | switch (sel) { | |
5259 | case 0: | |
a7812ae4 | 5260 | gen_helper_mftc0_debug(t0); |
ead9360e TS |
5261 | break; |
5262 | default: | |
1a3fd9c3 | 5263 | gen_mfc0(env, ctx, t0, rt, sel); |
ead9360e TS |
5264 | break; |
5265 | } | |
5266 | break; | |
5267 | default: | |
1a3fd9c3 | 5268 | gen_mfc0(env, ctx, t0, rt, sel); |
ead9360e TS |
5269 | } |
5270 | } else switch (sel) { | |
5271 | /* GPR registers. */ | |
5272 | case 0: | |
a7812ae4 | 5273 | gen_helper_1i(mftgpr, t0, rt); |
ead9360e TS |
5274 | break; |
5275 | /* Auxiliary CPU registers */ | |
5276 | case 1: | |
5277 | switch (rt) { | |
5278 | case 0: | |
a7812ae4 | 5279 | gen_helper_1i(mftlo, t0, 0); |
ead9360e TS |
5280 | break; |
5281 | case 1: | |
a7812ae4 | 5282 | gen_helper_1i(mfthi, t0, 0); |
ead9360e TS |
5283 | break; |
5284 | case 2: | |
a7812ae4 | 5285 | gen_helper_1i(mftacx, t0, 0); |
ead9360e TS |
5286 | break; |
5287 | case 4: | |
a7812ae4 | 5288 | gen_helper_1i(mftlo, t0, 1); |
ead9360e TS |
5289 | break; |
5290 | case 5: | |
a7812ae4 | 5291 | gen_helper_1i(mfthi, t0, 1); |
ead9360e TS |
5292 | break; |
5293 | case 6: | |
a7812ae4 | 5294 | gen_helper_1i(mftacx, t0, 1); |
ead9360e TS |
5295 | break; |
5296 | case 8: | |
a7812ae4 | 5297 | gen_helper_1i(mftlo, t0, 2); |
ead9360e TS |
5298 | break; |
5299 | case 9: | |
a7812ae4 | 5300 | gen_helper_1i(mfthi, t0, 2); |
ead9360e TS |
5301 | break; |
5302 | case 10: | |
a7812ae4 | 5303 | gen_helper_1i(mftacx, t0, 2); |
ead9360e TS |
5304 | break; |
5305 | case 12: | |
a7812ae4 | 5306 | gen_helper_1i(mftlo, t0, 3); |
ead9360e TS |
5307 | break; |
5308 | case 13: | |
a7812ae4 | 5309 | gen_helper_1i(mfthi, t0, 3); |
ead9360e TS |
5310 | break; |
5311 | case 14: | |
a7812ae4 | 5312 | gen_helper_1i(mftacx, t0, 3); |
ead9360e TS |
5313 | break; |
5314 | case 16: | |
a7812ae4 | 5315 | gen_helper_mftdsp(t0); |
ead9360e TS |
5316 | break; |
5317 | default: | |
5318 | goto die; | |
5319 | } | |
5320 | break; | |
5321 | /* Floating point (COP1). */ | |
5322 | case 2: | |
5323 | /* XXX: For now we support only a single FPU context. */ | |
5324 | if (h == 0) { | |
a7812ae4 | 5325 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
5326 | |
5327 | gen_load_fpr32(fp0, rt); | |
5328 | tcg_gen_ext_i32_tl(t0, fp0); | |
a7812ae4 | 5329 | tcg_temp_free_i32(fp0); |
ead9360e | 5330 | } else { |
a7812ae4 | 5331 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
5332 | |
5333 | gen_load_fpr32h(fp0, rt); | |
5334 | tcg_gen_ext_i32_tl(t0, fp0); | |
a7812ae4 | 5335 | tcg_temp_free_i32(fp0); |
ead9360e TS |
5336 | } |
5337 | break; | |
5338 | case 3: | |
5339 | /* XXX: For now we support only a single FPU context. */ | |
a7812ae4 | 5340 | gen_helper_1i(cfc1, t0, rt); |
ead9360e TS |
5341 | break; |
5342 | /* COP2: Not implemented. */ | |
5343 | case 4: | |
5344 | case 5: | |
5345 | /* fall through */ | |
5346 | default: | |
5347 | goto die; | |
5348 | } | |
d12d51d5 | 5349 | LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); |
1a3fd9c3 TS |
5350 | gen_store_gpr(t0, rd); |
5351 | tcg_temp_free(t0); | |
ead9360e TS |
5352 | return; |
5353 | ||
5354 | die: | |
1a3fd9c3 | 5355 | tcg_temp_free(t0); |
d12d51d5 | 5356 | LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); |
ead9360e TS |
5357 | generate_exception(ctx, EXCP_RI); |
5358 | } | |
5359 | ||
6c5c1e20 | 5360 | static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt, |
ead9360e TS |
5361 | int u, int sel, int h) |
5362 | { | |
5363 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); | |
a7812ae4 | 5364 | TCGv t0 = tcg_temp_local_new(); |
ead9360e | 5365 | |
1a3fd9c3 | 5366 | gen_load_gpr(t0, rt); |
ead9360e | 5367 | if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && |
b5dc7732 TS |
5368 | ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != |
5369 | (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) | |
ead9360e TS |
5370 | /* NOP */ ; |
5371 | else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > | |
5372 | (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) | |
5373 | /* NOP */ ; | |
5374 | else if (u == 0) { | |
5375 | switch (rd) { | |
5376 | case 2: | |
5377 | switch (sel) { | |
5378 | case 1: | |
a7812ae4 | 5379 | gen_helper_mttc0_tcstatus(t0); |
ead9360e TS |
5380 | break; |
5381 | case 2: | |
a7812ae4 | 5382 | gen_helper_mttc0_tcbind(t0); |
ead9360e TS |
5383 | break; |
5384 | case 3: | |
a7812ae4 | 5385 | gen_helper_mttc0_tcrestart(t0); |
ead9360e TS |
5386 | break; |
5387 | case 4: | |
a7812ae4 | 5388 | gen_helper_mttc0_tchalt(t0); |
ead9360e TS |
5389 | break; |
5390 | case 5: | |
a7812ae4 | 5391 | gen_helper_mttc0_tccontext(t0); |
ead9360e TS |
5392 | break; |
5393 | case 6: | |
a7812ae4 | 5394 | gen_helper_mttc0_tcschedule(t0); |
ead9360e TS |
5395 | break; |
5396 | case 7: | |
a7812ae4 | 5397 | gen_helper_mttc0_tcschefback(t0); |
ead9360e TS |
5398 | break; |
5399 | default: | |
1a3fd9c3 | 5400 | gen_mtc0(env, ctx, t0, rd, sel); |
ead9360e TS |
5401 | break; |
5402 | } | |
5403 | break; | |
5404 | case 10: | |
5405 | switch (sel) { | |
5406 | case 0: | |
a7812ae4 | 5407 | gen_helper_mttc0_entryhi(t0); |
ead9360e TS |
5408 | break; |
5409 | default: | |
1a3fd9c3 | 5410 | gen_mtc0(env, ctx, t0, rd, sel); |
ead9360e TS |
5411 | break; |
5412 | } | |
5413 | case 12: | |
5414 | switch (sel) { | |
5415 | case 0: | |
a7812ae4 | 5416 | gen_helper_mttc0_status(t0); |
ead9360e TS |
5417 | break; |
5418 | default: | |
1a3fd9c3 | 5419 | gen_mtc0(env, ctx, t0, rd, sel); |
ead9360e TS |
5420 | break; |
5421 | } | |
5422 | case 23: | |
5423 | switch (sel) { | |
5424 | case 0: | |
a7812ae4 | 5425 | gen_helper_mttc0_debug(t0); |
ead9360e TS |
5426 | break; |
5427 | default: | |
1a3fd9c3 | 5428 | gen_mtc0(env, ctx, t0, rd, sel); |
ead9360e TS |
5429 | break; |
5430 | } | |
5431 | break; | |
5432 | default: | |
1a3fd9c3 | 5433 | gen_mtc0(env, ctx, t0, rd, sel); |
ead9360e TS |
5434 | } |
5435 | } else switch (sel) { | |
5436 | /* GPR registers. */ | |
5437 | case 0: | |
a7812ae4 | 5438 | gen_helper_1i(mttgpr, t0, rd); |
ead9360e TS |
5439 | break; |
5440 | /* Auxiliary CPU registers */ | |
5441 | case 1: | |
5442 | switch (rd) { | |
5443 | case 0: | |
a7812ae4 | 5444 | gen_helper_1i(mttlo, t0, 0); |
ead9360e TS |
5445 | break; |
5446 | case 1: | |
a7812ae4 | 5447 | gen_helper_1i(mtthi, t0, 0); |
ead9360e TS |
5448 | break; |
5449 | case 2: | |
a7812ae4 | 5450 | gen_helper_1i(mttacx, t0, 0); |
ead9360e TS |
5451 | break; |
5452 | case 4: | |
a7812ae4 | 5453 | gen_helper_1i(mttlo, t0, 1); |
ead9360e TS |
5454 | break; |
5455 | case 5: | |
a7812ae4 | 5456 | gen_helper_1i(mtthi, t0, 1); |
ead9360e TS |
5457 | break; |
5458 | case 6: | |
a7812ae4 | 5459 | gen_helper_1i(mttacx, t0, 1); |
ead9360e TS |
5460 | break; |
5461 | case 8: | |
a7812ae4 | 5462 | gen_helper_1i(mttlo, t0, 2); |
ead9360e TS |
5463 | break; |
5464 | case 9: | |
a7812ae4 | 5465 | gen_helper_1i(mtthi, t0, 2); |
ead9360e TS |
5466 | break; |
5467 | case 10: | |
a7812ae4 | 5468 | gen_helper_1i(mttacx, t0, 2); |
ead9360e TS |
5469 | break; |
5470 | case 12: | |
a7812ae4 | 5471 | gen_helper_1i(mttlo, t0, 3); |
ead9360e TS |
5472 | break; |
5473 | case 13: | |
a7812ae4 | 5474 | gen_helper_1i(mtthi, t0, 3); |
ead9360e TS |
5475 | break; |
5476 | case 14: | |
a7812ae4 | 5477 | gen_helper_1i(mttacx, t0, 3); |
ead9360e TS |
5478 | break; |
5479 | case 16: | |
a7812ae4 | 5480 | gen_helper_mttdsp(t0); |
ead9360e TS |
5481 | break; |
5482 | default: | |
5483 | goto die; | |
5484 | } | |
5485 | break; | |
5486 | /* Floating point (COP1). */ | |
5487 | case 2: | |
5488 | /* XXX: For now we support only a single FPU context. */ | |
5489 | if (h == 0) { | |
a7812ae4 | 5490 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
5491 | |
5492 | tcg_gen_trunc_tl_i32(fp0, t0); | |
5493 | gen_store_fpr32(fp0, rd); | |
a7812ae4 | 5494 | tcg_temp_free_i32(fp0); |
ead9360e | 5495 | } else { |
a7812ae4 | 5496 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
5497 | |
5498 | tcg_gen_trunc_tl_i32(fp0, t0); | |
5499 | gen_store_fpr32h(fp0, rd); | |
a7812ae4 | 5500 | tcg_temp_free_i32(fp0); |
ead9360e TS |
5501 | } |
5502 | break; | |
5503 | case 3: | |
5504 | /* XXX: For now we support only a single FPU context. */ | |
a7812ae4 | 5505 | gen_helper_1i(ctc1, t0, rd); |
ead9360e TS |
5506 | break; |
5507 | /* COP2: Not implemented. */ | |
5508 | case 4: | |
5509 | case 5: | |
5510 | /* fall through */ | |
5511 | default: | |
5512 | goto die; | |
5513 | } | |
d12d51d5 | 5514 | LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); |
1a3fd9c3 | 5515 | tcg_temp_free(t0); |
ead9360e TS |
5516 | return; |
5517 | ||
5518 | die: | |
1a3fd9c3 | 5519 | tcg_temp_free(t0); |
d12d51d5 | 5520 | LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); |
ead9360e TS |
5521 | generate_exception(ctx, EXCP_RI); |
5522 | } | |
5523 | ||
29929e34 | 5524 | static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd) |
6af0bf9c | 5525 | { |
287c4b84 | 5526 | const char *opn = "ldst"; |
6af0bf9c | 5527 | |
6af0bf9c FB |
5528 | switch (opc) { |
5529 | case OPC_MFC0: | |
5530 | if (rt == 0) { | |
ead9360e | 5531 | /* Treat as NOP. */ |
6af0bf9c FB |
5532 | return; |
5533 | } | |
1fc7bf6e | 5534 | gen_mfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); |
6af0bf9c FB |
5535 | opn = "mfc0"; |
5536 | break; | |
5537 | case OPC_MTC0: | |
1a3fd9c3 | 5538 | { |
1fc7bf6e | 5539 | TCGv t0 = tcg_temp_new(); |
1a3fd9c3 TS |
5540 | |
5541 | gen_load_gpr(t0, rt); | |
1a3fd9c3 TS |
5542 | gen_mtc0(env, ctx, t0, rd, ctx->opcode & 0x7); |
5543 | tcg_temp_free(t0); | |
5544 | } | |
6af0bf9c FB |
5545 | opn = "mtc0"; |
5546 | break; | |
d26bc211 | 5547 | #if defined(TARGET_MIPS64) |
9c2149c8 | 5548 | case OPC_DMFC0: |
e189e748 | 5549 | check_insn(env, ctx, ISA_MIPS3); |
9c2149c8 | 5550 | if (rt == 0) { |
ead9360e | 5551 | /* Treat as NOP. */ |
9c2149c8 TS |
5552 | return; |
5553 | } | |
1fc7bf6e | 5554 | gen_dmfc0(env, ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); |
9c2149c8 TS |
5555 | opn = "dmfc0"; |
5556 | break; | |
5557 | case OPC_DMTC0: | |
e189e748 | 5558 | check_insn(env, ctx, ISA_MIPS3); |
1a3fd9c3 | 5559 | { |
1fc7bf6e | 5560 | TCGv t0 = tcg_temp_new(); |
1a3fd9c3 TS |
5561 | |
5562 | gen_load_gpr(t0, rt); | |
1a3fd9c3 TS |
5563 | gen_dmtc0(env, ctx, t0, rd, ctx->opcode & 0x7); |
5564 | tcg_temp_free(t0); | |
5565 | } | |
9c2149c8 TS |
5566 | opn = "dmtc0"; |
5567 | break; | |
534ce69f | 5568 | #endif |
ead9360e | 5569 | case OPC_MFTR: |
7385ac0b | 5570 | check_insn(env, ctx, ASE_MT); |
ead9360e TS |
5571 | if (rd == 0) { |
5572 | /* Treat as NOP. */ | |
5573 | return; | |
5574 | } | |
6c5c1e20 | 5575 | gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, |
ead9360e | 5576 | ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); |
ead9360e TS |
5577 | opn = "mftr"; |
5578 | break; | |
5579 | case OPC_MTTR: | |
7385ac0b | 5580 | check_insn(env, ctx, ASE_MT); |
6c5c1e20 | 5581 | gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, |
ead9360e TS |
5582 | ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); |
5583 | opn = "mttr"; | |
5584 | break; | |
6af0bf9c | 5585 | case OPC_TLBWI: |
6af0bf9c | 5586 | opn = "tlbwi"; |
c01fccd2 | 5587 | if (!env->tlb->helper_tlbwi) |
29929e34 | 5588 | goto die; |
a7812ae4 | 5589 | gen_helper_tlbwi(); |
6af0bf9c FB |
5590 | break; |
5591 | case OPC_TLBWR: | |
6af0bf9c | 5592 | opn = "tlbwr"; |
c01fccd2 | 5593 | if (!env->tlb->helper_tlbwr) |
29929e34 | 5594 | goto die; |
a7812ae4 | 5595 | gen_helper_tlbwr(); |
6af0bf9c FB |
5596 | break; |
5597 | case OPC_TLBP: | |
6af0bf9c | 5598 | opn = "tlbp"; |
c01fccd2 | 5599 | if (!env->tlb->helper_tlbp) |
29929e34 | 5600 | goto die; |
a7812ae4 | 5601 | gen_helper_tlbp(); |
6af0bf9c FB |
5602 | break; |
5603 | case OPC_TLBR: | |
6af0bf9c | 5604 | opn = "tlbr"; |
c01fccd2 | 5605 | if (!env->tlb->helper_tlbr) |
29929e34 | 5606 | goto die; |
a7812ae4 | 5607 | gen_helper_tlbr(); |
6af0bf9c | 5608 | break; |
6af0bf9c FB |
5609 | case OPC_ERET: |
5610 | opn = "eret"; | |
e189e748 | 5611 | check_insn(env, ctx, ISA_MIPS2); |
a7812ae4 | 5612 | gen_helper_eret(); |
6af0bf9c FB |
5613 | ctx->bstate = BS_EXCP; |
5614 | break; | |
5615 | case OPC_DERET: | |
5616 | opn = "deret"; | |
e189e748 | 5617 | check_insn(env, ctx, ISA_MIPS32); |
6af0bf9c | 5618 | if (!(ctx->hflags & MIPS_HFLAG_DM)) { |
923617a3 | 5619 | MIPS_INVAL(opn); |
6af0bf9c FB |
5620 | generate_exception(ctx, EXCP_RI); |
5621 | } else { | |
a7812ae4 | 5622 | gen_helper_deret(); |
6af0bf9c FB |
5623 | ctx->bstate = BS_EXCP; |
5624 | } | |
5625 | break; | |
4ad40f36 FB |
5626 | case OPC_WAIT: |
5627 | opn = "wait"; | |
e189e748 | 5628 | check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); |
4ad40f36 FB |
5629 | /* If we get an exception, we want to restart at next instruction */ |
5630 | ctx->pc += 4; | |
5631 | save_cpu_state(ctx, 1); | |
5632 | ctx->pc -= 4; | |
a7812ae4 | 5633 | gen_helper_wait(); |
4ad40f36 FB |
5634 | ctx->bstate = BS_EXCP; |
5635 | break; | |
6af0bf9c | 5636 | default: |
29929e34 | 5637 | die: |
923617a3 | 5638 | MIPS_INVAL(opn); |
6af0bf9c FB |
5639 | generate_exception(ctx, EXCP_RI); |
5640 | return; | |
5641 | } | |
5642 | MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd); | |
5643 | } | |
f1aa6320 | 5644 | #endif /* !CONFIG_USER_ONLY */ |
6af0bf9c | 5645 | |
6ea83fed | 5646 | /* CP1 Branches (before delay slot) */ |
e189e748 | 5647 | static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, |
5a5012ec | 5648 | int32_t cc, int32_t offset) |
6ea83fed FB |
5649 | { |
5650 | target_ulong btarget; | |
923617a3 | 5651 | const char *opn = "cp1 cond branch"; |
a7812ae4 | 5652 | TCGv_i32 t0 = tcg_temp_new_i32(); |
6ea83fed | 5653 | |
e189e748 TS |
5654 | if (cc != 0) |
5655 | check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); | |
5656 | ||
6ea83fed FB |
5657 | btarget = ctx->pc + 4 + offset; |
5658 | ||
7a387fff TS |
5659 | switch (op) { |
5660 | case OPC_BC1F: | |
d94536f4 AJ |
5661 | tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
5662 | tcg_gen_not_i32(t0, t0); | |
5663 | tcg_gen_andi_i32(t0, t0, 1); | |
5664 | tcg_gen_extu_i32_tl(bcond, t0); | |
923617a3 | 5665 | opn = "bc1f"; |
6ea83fed | 5666 | goto not_likely; |
7a387fff | 5667 | case OPC_BC1FL: |
d94536f4 AJ |
5668 | tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
5669 | tcg_gen_not_i32(t0, t0); | |
5670 | tcg_gen_andi_i32(t0, t0, 1); | |
5671 | tcg_gen_extu_i32_tl(bcond, t0); | |
923617a3 | 5672 | opn = "bc1fl"; |
6ea83fed | 5673 | goto likely; |
7a387fff | 5674 | case OPC_BC1T: |
d94536f4 AJ |
5675 | tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
5676 | tcg_gen_andi_i32(t0, t0, 1); | |
5677 | tcg_gen_extu_i32_tl(bcond, t0); | |
923617a3 | 5678 | opn = "bc1t"; |
5a5012ec | 5679 | goto not_likely; |
7a387fff | 5680 | case OPC_BC1TL: |
d94536f4 AJ |
5681 | tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
5682 | tcg_gen_andi_i32(t0, t0, 1); | |
5683 | tcg_gen_extu_i32_tl(bcond, t0); | |
923617a3 | 5684 | opn = "bc1tl"; |
6ea83fed FB |
5685 | likely: |
5686 | ctx->hflags |= MIPS_HFLAG_BL; | |
5687 | break; | |
5a5012ec | 5688 | case OPC_BC1FANY2: |
a16336e4 | 5689 | { |
d94536f4 AJ |
5690 | TCGv_i32 t1 = tcg_temp_new_i32(); |
5691 | tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); | |
5692 | tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); | |
5693 | tcg_gen_or_i32(t0, t0, t1); | |
5694 | tcg_temp_free_i32(t1); | |
5695 | tcg_gen_not_i32(t0, t0); | |
5696 | tcg_gen_andi_i32(t0, t0, 1); | |
5697 | tcg_gen_extu_i32_tl(bcond, t0); | |
a16336e4 | 5698 | } |
fd4a04eb | 5699 | opn = "bc1any2f"; |
5a5012ec TS |
5700 | goto not_likely; |
5701 | case OPC_BC1TANY2: | |
a16336e4 | 5702 | { |
d94536f4 AJ |
5703 | TCGv_i32 t1 = tcg_temp_new_i32(); |
5704 | tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); | |
5705 | tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); | |
5706 | tcg_gen_or_i32(t0, t0, t1); | |
5707 | tcg_temp_free_i32(t1); | |
5708 | tcg_gen_andi_i32(t0, t0, 1); | |
5709 | tcg_gen_extu_i32_tl(bcond, t0); | |
a16336e4 | 5710 | } |
fd4a04eb | 5711 | opn = "bc1any2t"; |
5a5012ec TS |
5712 | goto not_likely; |
5713 | case OPC_BC1FANY4: | |
a16336e4 | 5714 | { |
d94536f4 AJ |
5715 | TCGv_i32 t1 = tcg_temp_new_i32(); |
5716 | tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); | |
5717 | tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); | |
5718 | tcg_gen_or_i32(t0, t0, t1); | |
5719 | tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); | |
5720 | tcg_gen_or_i32(t0, t0, t1); | |
5721 | tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); | |
5722 | tcg_gen_or_i32(t0, t0, t1); | |
5723 | tcg_temp_free_i32(t1); | |
5724 | tcg_gen_not_i32(t0, t0); | |
5725 | tcg_gen_andi_i32(t0, t0, 1); | |
5726 | tcg_gen_extu_i32_tl(bcond, t0); | |
a16336e4 | 5727 | } |
fd4a04eb | 5728 | opn = "bc1any4f"; |
5a5012ec TS |
5729 | goto not_likely; |
5730 | case OPC_BC1TANY4: | |
a16336e4 | 5731 | { |
d94536f4 AJ |
5732 | TCGv_i32 t1 = tcg_temp_new_i32(); |
5733 | tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); | |
5734 | tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); | |
5735 | tcg_gen_or_i32(t0, t0, t1); | |
5736 | tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); | |
5737 | tcg_gen_or_i32(t0, t0, t1); | |
5738 | tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); | |
5739 | tcg_gen_or_i32(t0, t0, t1); | |
5740 | tcg_temp_free_i32(t1); | |
5741 | tcg_gen_andi_i32(t0, t0, 1); | |
5742 | tcg_gen_extu_i32_tl(bcond, t0); | |
a16336e4 | 5743 | } |
fd4a04eb | 5744 | opn = "bc1any4t"; |
5a5012ec TS |
5745 | not_likely: |
5746 | ctx->hflags |= MIPS_HFLAG_BC; | |
5a5012ec TS |
5747 | break; |
5748 | default: | |
923617a3 | 5749 | MIPS_INVAL(opn); |
e397ee33 | 5750 | generate_exception (ctx, EXCP_RI); |
6c5c1e20 | 5751 | goto out; |
6ea83fed | 5752 | } |
923617a3 | 5753 | MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn, |
6ea83fed FB |
5754 | ctx->hflags, btarget); |
5755 | ctx->btarget = btarget; | |
6c5c1e20 TS |
5756 | |
5757 | out: | |
a7812ae4 | 5758 | tcg_temp_free_i32(t0); |
6ea83fed FB |
5759 | } |
5760 | ||
6af0bf9c | 5761 | /* Coprocessor 1 (FPU) */ |
5a5012ec | 5762 | |
5a5012ec TS |
5763 | #define FOP(func, fmt) (((fmt) << 21) | (func)) |
5764 | ||
7a387fff | 5765 | static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) |
6ea83fed | 5766 | { |
923617a3 | 5767 | const char *opn = "cp1 move"; |
72c3a3ee | 5768 | TCGv t0 = tcg_temp_new(); |
6ea83fed FB |
5769 | |
5770 | switch (opc) { | |
5771 | case OPC_MFC1: | |
b6d96bed | 5772 | { |
a7812ae4 | 5773 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
5774 | |
5775 | gen_load_fpr32(fp0, fs); | |
5776 | tcg_gen_ext_i32_tl(t0, fp0); | |
a7812ae4 | 5777 | tcg_temp_free_i32(fp0); |
6958549d | 5778 | } |
6c5c1e20 | 5779 | gen_store_gpr(t0, rt); |
6ea83fed FB |
5780 | opn = "mfc1"; |
5781 | break; | |
5782 | case OPC_MTC1: | |
6c5c1e20 | 5783 | gen_load_gpr(t0, rt); |
b6d96bed | 5784 | { |
a7812ae4 | 5785 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
5786 | |
5787 | tcg_gen_trunc_tl_i32(fp0, t0); | |
5788 | gen_store_fpr32(fp0, fs); | |
a7812ae4 | 5789 | tcg_temp_free_i32(fp0); |
6958549d | 5790 | } |
6ea83fed FB |
5791 | opn = "mtc1"; |
5792 | break; | |
5793 | case OPC_CFC1: | |
a7812ae4 | 5794 | gen_helper_1i(cfc1, t0, fs); |
6c5c1e20 | 5795 | gen_store_gpr(t0, rt); |
6ea83fed FB |
5796 | opn = "cfc1"; |
5797 | break; | |
5798 | case OPC_CTC1: | |
6c5c1e20 | 5799 | gen_load_gpr(t0, rt); |
a7812ae4 | 5800 | gen_helper_1i(ctc1, t0, fs); |
6ea83fed FB |
5801 | opn = "ctc1"; |
5802 | break; | |
72c3a3ee | 5803 | #if defined(TARGET_MIPS64) |
9c2149c8 | 5804 | case OPC_DMFC1: |
72c3a3ee | 5805 | gen_load_fpr64(ctx, t0, fs); |
6c5c1e20 | 5806 | gen_store_gpr(t0, rt); |
5a5012ec TS |
5807 | opn = "dmfc1"; |
5808 | break; | |
9c2149c8 | 5809 | case OPC_DMTC1: |
6c5c1e20 | 5810 | gen_load_gpr(t0, rt); |
72c3a3ee | 5811 | gen_store_fpr64(ctx, t0, fs); |
5a5012ec TS |
5812 | opn = "dmtc1"; |
5813 | break; | |
72c3a3ee | 5814 | #endif |
5a5012ec | 5815 | case OPC_MFHC1: |
b6d96bed | 5816 | { |
a7812ae4 | 5817 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
5818 | |
5819 | gen_load_fpr32h(fp0, fs); | |
5820 | tcg_gen_ext_i32_tl(t0, fp0); | |
a7812ae4 | 5821 | tcg_temp_free_i32(fp0); |
6958549d | 5822 | } |
6c5c1e20 | 5823 | gen_store_gpr(t0, rt); |
5a5012ec TS |
5824 | opn = "mfhc1"; |
5825 | break; | |
5826 | case OPC_MTHC1: | |
6c5c1e20 | 5827 | gen_load_gpr(t0, rt); |
b6d96bed | 5828 | { |
a7812ae4 | 5829 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
5830 | |
5831 | tcg_gen_trunc_tl_i32(fp0, t0); | |
5832 | gen_store_fpr32h(fp0, fs); | |
a7812ae4 | 5833 | tcg_temp_free_i32(fp0); |
6958549d | 5834 | } |
5a5012ec TS |
5835 | opn = "mthc1"; |
5836 | break; | |
6ea83fed | 5837 | default: |
923617a3 | 5838 | MIPS_INVAL(opn); |
e397ee33 | 5839 | generate_exception (ctx, EXCP_RI); |
6c5c1e20 | 5840 | goto out; |
6ea83fed FB |
5841 | } |
5842 | MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]); | |
6c5c1e20 TS |
5843 | |
5844 | out: | |
5845 | tcg_temp_free(t0); | |
6ea83fed FB |
5846 | } |
5847 | ||
5a5012ec TS |
5848 | static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) |
5849 | { | |
af58f9ca | 5850 | int l1; |
e214b9bb | 5851 | TCGCond cond; |
af58f9ca AJ |
5852 | TCGv_i32 t0; |
5853 | ||
5854 | if (rd == 0) { | |
5855 | /* Treat as NOP. */ | |
5856 | return; | |
5857 | } | |
6ea83fed | 5858 | |
e214b9bb | 5859 | if (tf) |
e214b9bb | 5860 | cond = TCG_COND_EQ; |
27848470 TS |
5861 | else |
5862 | cond = TCG_COND_NE; | |
5863 | ||
af58f9ca AJ |
5864 | l1 = gen_new_label(); |
5865 | t0 = tcg_temp_new_i32(); | |
5866 | tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); | |
5867 | tcg_gen_brcondi_i32(cond, t0, 0, l1); | |
a4e8338d | 5868 | tcg_temp_free_i32(t0); |
af58f9ca AJ |
5869 | if (rs == 0) { |
5870 | tcg_gen_movi_tl(cpu_gpr[rd], 0); | |
5871 | } else { | |
5872 | tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); | |
5873 | } | |
e214b9bb | 5874 | gen_set_label(l1); |
5a5012ec TS |
5875 | } |
5876 | ||
b6d96bed | 5877 | static inline void gen_movcf_s (int fs, int fd, int cc, int tf) |
a16336e4 | 5878 | { |
a16336e4 | 5879 | int cond; |
cbc37b28 | 5880 | TCGv_i32 t0 = tcg_temp_new_i32(); |
a16336e4 TS |
5881 | int l1 = gen_new_label(); |
5882 | ||
a16336e4 TS |
5883 | if (tf) |
5884 | cond = TCG_COND_EQ; | |
5885 | else | |
5886 | cond = TCG_COND_NE; | |
5887 | ||
cbc37b28 AJ |
5888 | tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
5889 | tcg_gen_brcondi_i32(cond, t0, 0, l1); | |
5890 | gen_load_fpr32(t0, fs); | |
5891 | gen_store_fpr32(t0, fd); | |
a16336e4 | 5892 | gen_set_label(l1); |
cbc37b28 | 5893 | tcg_temp_free_i32(t0); |
5a5012ec | 5894 | } |
a16336e4 | 5895 | |
b6d96bed | 5896 | static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) |
a16336e4 | 5897 | { |
a16336e4 | 5898 | int cond; |
cbc37b28 AJ |
5899 | TCGv_i32 t0 = tcg_temp_new_i32(); |
5900 | TCGv_i64 fp0; | |
a16336e4 TS |
5901 | int l1 = gen_new_label(); |
5902 | ||
a16336e4 TS |
5903 | if (tf) |
5904 | cond = TCG_COND_EQ; | |
5905 | else | |
5906 | cond = TCG_COND_NE; | |
5907 | ||
cbc37b28 AJ |
5908 | tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
5909 | tcg_gen_brcondi_i32(cond, t0, 0, l1); | |
a4e8338d | 5910 | tcg_temp_free_i32(t0); |
11f94258 | 5911 | fp0 = tcg_temp_new_i64(); |
9bf3eb2c | 5912 | gen_load_fpr64(ctx, fp0, fs); |
9bf3eb2c | 5913 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 5914 | tcg_temp_free_i64(fp0); |
cbc37b28 | 5915 | gen_set_label(l1); |
a16336e4 TS |
5916 | } |
5917 | ||
b6d96bed | 5918 | static inline void gen_movcf_ps (int fs, int fd, int cc, int tf) |
a16336e4 TS |
5919 | { |
5920 | int cond; | |
cbc37b28 | 5921 | TCGv_i32 t0 = tcg_temp_new_i32(); |
a16336e4 TS |
5922 | int l1 = gen_new_label(); |
5923 | int l2 = gen_new_label(); | |
5924 | ||
5925 | if (tf) | |
5926 | cond = TCG_COND_EQ; | |
5927 | else | |
5928 | cond = TCG_COND_NE; | |
5929 | ||
cbc37b28 AJ |
5930 | tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
5931 | tcg_gen_brcondi_i32(cond, t0, 0, l1); | |
5932 | gen_load_fpr32(t0, fs); | |
5933 | gen_store_fpr32(t0, fd); | |
a16336e4 | 5934 | gen_set_label(l1); |
9bf3eb2c | 5935 | |
cbc37b28 AJ |
5936 | tcg_gen_andi_i32(t0, fpu_fcr31, get_fp_bit(cc+1)); |
5937 | tcg_gen_brcondi_i32(cond, t0, 0, l2); | |
5938 | gen_load_fpr32h(t0, fs); | |
5939 | gen_store_fpr32h(t0, fd); | |
52a0e9eb | 5940 | tcg_temp_free_i32(t0); |
a16336e4 | 5941 | gen_set_label(l2); |
a16336e4 TS |
5942 | } |
5943 | ||
6ea83fed | 5944 | |
5e755519 TS |
5945 | static void gen_farith (DisasContext *ctx, uint32_t op1, |
5946 | int ft, int fs, int fd, int cc) | |
6ea83fed | 5947 | { |
923617a3 | 5948 | const char *opn = "farith"; |
6ea83fed FB |
5949 | const char *condnames[] = { |
5950 | "c.f", | |
5951 | "c.un", | |
5952 | "c.eq", | |
5953 | "c.ueq", | |
5954 | "c.olt", | |
5955 | "c.ult", | |
5956 | "c.ole", | |
5957 | "c.ule", | |
5958 | "c.sf", | |
5959 | "c.ngle", | |
5960 | "c.seq", | |
5961 | "c.ngl", | |
5962 | "c.lt", | |
5963 | "c.nge", | |
5964 | "c.le", | |
5965 | "c.ngt", | |
5966 | }; | |
5a1e8ffb TS |
5967 | const char *condnames_abs[] = { |
5968 | "cabs.f", | |
5969 | "cabs.un", | |
5970 | "cabs.eq", | |
5971 | "cabs.ueq", | |
5972 | "cabs.olt", | |
5973 | "cabs.ult", | |
5974 | "cabs.ole", | |
5975 | "cabs.ule", | |
5976 | "cabs.sf", | |
5977 | "cabs.ngle", | |
5978 | "cabs.seq", | |
5979 | "cabs.ngl", | |
5980 | "cabs.lt", | |
5981 | "cabs.nge", | |
5982 | "cabs.le", | |
5983 | "cabs.ngt", | |
5984 | }; | |
5985 | enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP; | |
7a387fff TS |
5986 | uint32_t func = ctx->opcode & 0x3f; |
5987 | ||
6ea83fed | 5988 | switch (ctx->opcode & FOP(0x3f, 0x1f)) { |
5a5012ec | 5989 | case FOP(0, 16): |
b6d96bed | 5990 | { |
a7812ae4 PB |
5991 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
5992 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
5993 | |
5994 | gen_load_fpr32(fp0, fs); | |
5995 | gen_load_fpr32(fp1, ft); | |
a7812ae4 PB |
5996 | gen_helper_float_add_s(fp0, fp0, fp1); |
5997 | tcg_temp_free_i32(fp1); | |
b6d96bed | 5998 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 5999 | tcg_temp_free_i32(fp0); |
b6d96bed | 6000 | } |
5a5012ec | 6001 | opn = "add.s"; |
5a1e8ffb | 6002 | optype = BINOP; |
5a5012ec TS |
6003 | break; |
6004 | case FOP(1, 16): | |
b6d96bed | 6005 | { |
a7812ae4 PB |
6006 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
6007 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
6008 | |
6009 | gen_load_fpr32(fp0, fs); | |
6010 | gen_load_fpr32(fp1, ft); | |
a7812ae4 PB |
6011 | gen_helper_float_sub_s(fp0, fp0, fp1); |
6012 | tcg_temp_free_i32(fp1); | |
b6d96bed | 6013 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6014 | tcg_temp_free_i32(fp0); |
b6d96bed | 6015 | } |
5a5012ec | 6016 | opn = "sub.s"; |
5a1e8ffb | 6017 | optype = BINOP; |
5a5012ec TS |
6018 | break; |
6019 | case FOP(2, 16): | |
b6d96bed | 6020 | { |
a7812ae4 PB |
6021 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
6022 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
6023 | |
6024 | gen_load_fpr32(fp0, fs); | |
6025 | gen_load_fpr32(fp1, ft); | |
a7812ae4 PB |
6026 | gen_helper_float_mul_s(fp0, fp0, fp1); |
6027 | tcg_temp_free_i32(fp1); | |
b6d96bed | 6028 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6029 | tcg_temp_free_i32(fp0); |
b6d96bed | 6030 | } |
5a5012ec | 6031 | opn = "mul.s"; |
5a1e8ffb | 6032 | optype = BINOP; |
5a5012ec TS |
6033 | break; |
6034 | case FOP(3, 16): | |
b6d96bed | 6035 | { |
a7812ae4 PB |
6036 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
6037 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
6038 | |
6039 | gen_load_fpr32(fp0, fs); | |
6040 | gen_load_fpr32(fp1, ft); | |
a7812ae4 PB |
6041 | gen_helper_float_div_s(fp0, fp0, fp1); |
6042 | tcg_temp_free_i32(fp1); | |
b6d96bed | 6043 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6044 | tcg_temp_free_i32(fp0); |
b6d96bed | 6045 | } |
5a5012ec | 6046 | opn = "div.s"; |
5a1e8ffb | 6047 | optype = BINOP; |
5a5012ec TS |
6048 | break; |
6049 | case FOP(4, 16): | |
b6d96bed | 6050 | { |
a7812ae4 | 6051 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6052 | |
6053 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6054 | gen_helper_float_sqrt_s(fp0, fp0); |
b6d96bed | 6055 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6056 | tcg_temp_free_i32(fp0); |
b6d96bed | 6057 | } |
5a5012ec TS |
6058 | opn = "sqrt.s"; |
6059 | break; | |
6060 | case FOP(5, 16): | |
b6d96bed | 6061 | { |
a7812ae4 | 6062 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6063 | |
6064 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6065 | gen_helper_float_abs_s(fp0, fp0); |
b6d96bed | 6066 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6067 | tcg_temp_free_i32(fp0); |
b6d96bed | 6068 | } |
5a5012ec TS |
6069 | opn = "abs.s"; |
6070 | break; | |
6071 | case FOP(6, 16): | |
b6d96bed | 6072 | { |
a7812ae4 | 6073 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6074 | |
6075 | gen_load_fpr32(fp0, fs); | |
6076 | gen_store_fpr32(fp0, fd); | |
a7812ae4 | 6077 | tcg_temp_free_i32(fp0); |
b6d96bed | 6078 | } |
5a5012ec TS |
6079 | opn = "mov.s"; |
6080 | break; | |
6081 | case FOP(7, 16): | |
b6d96bed | 6082 | { |
a7812ae4 | 6083 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6084 | |
6085 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6086 | gen_helper_float_chs_s(fp0, fp0); |
b6d96bed | 6087 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6088 | tcg_temp_free_i32(fp0); |
b6d96bed | 6089 | } |
5a5012ec TS |
6090 | opn = "neg.s"; |
6091 | break; | |
6092 | case FOP(8, 16): | |
5e755519 | 6093 | check_cp1_64bitmode(ctx); |
b6d96bed | 6094 | { |
a7812ae4 PB |
6095 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6096 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6097 | |
6098 | gen_load_fpr32(fp32, fs); | |
a7812ae4 PB |
6099 | gen_helper_float_roundl_s(fp64, fp32); |
6100 | tcg_temp_free_i32(fp32); | |
b6d96bed | 6101 | gen_store_fpr64(ctx, fp64, fd); |
a7812ae4 | 6102 | tcg_temp_free_i64(fp64); |
b6d96bed | 6103 | } |
5a5012ec TS |
6104 | opn = "round.l.s"; |
6105 | break; | |
6106 | case FOP(9, 16): | |
5e755519 | 6107 | check_cp1_64bitmode(ctx); |
b6d96bed | 6108 | { |
a7812ae4 PB |
6109 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6110 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6111 | |
6112 | gen_load_fpr32(fp32, fs); | |
a7812ae4 PB |
6113 | gen_helper_float_truncl_s(fp64, fp32); |
6114 | tcg_temp_free_i32(fp32); | |
b6d96bed | 6115 | gen_store_fpr64(ctx, fp64, fd); |
a7812ae4 | 6116 | tcg_temp_free_i64(fp64); |
b6d96bed | 6117 | } |
5a5012ec TS |
6118 | opn = "trunc.l.s"; |
6119 | break; | |
6120 | case FOP(10, 16): | |
5e755519 | 6121 | check_cp1_64bitmode(ctx); |
b6d96bed | 6122 | { |
a7812ae4 PB |
6123 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6124 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6125 | |
6126 | gen_load_fpr32(fp32, fs); | |
a7812ae4 PB |
6127 | gen_helper_float_ceill_s(fp64, fp32); |
6128 | tcg_temp_free_i32(fp32); | |
b6d96bed | 6129 | gen_store_fpr64(ctx, fp64, fd); |
a7812ae4 | 6130 | tcg_temp_free_i64(fp64); |
b6d96bed | 6131 | } |
5a5012ec TS |
6132 | opn = "ceil.l.s"; |
6133 | break; | |
6134 | case FOP(11, 16): | |
5e755519 | 6135 | check_cp1_64bitmode(ctx); |
b6d96bed | 6136 | { |
a7812ae4 PB |
6137 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6138 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6139 | |
6140 | gen_load_fpr32(fp32, fs); | |
a7812ae4 PB |
6141 | gen_helper_float_floorl_s(fp64, fp32); |
6142 | tcg_temp_free_i32(fp32); | |
b6d96bed | 6143 | gen_store_fpr64(ctx, fp64, fd); |
a7812ae4 | 6144 | tcg_temp_free_i64(fp64); |
b6d96bed | 6145 | } |
5a5012ec TS |
6146 | opn = "floor.l.s"; |
6147 | break; | |
6148 | case FOP(12, 16): | |
b6d96bed | 6149 | { |
a7812ae4 | 6150 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6151 | |
6152 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6153 | gen_helper_float_roundw_s(fp0, fp0); |
b6d96bed | 6154 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6155 | tcg_temp_free_i32(fp0); |
b6d96bed | 6156 | } |
5a5012ec TS |
6157 | opn = "round.w.s"; |
6158 | break; | |
6159 | case FOP(13, 16): | |
b6d96bed | 6160 | { |
a7812ae4 | 6161 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6162 | |
6163 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6164 | gen_helper_float_truncw_s(fp0, fp0); |
b6d96bed | 6165 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6166 | tcg_temp_free_i32(fp0); |
b6d96bed | 6167 | } |
5a5012ec TS |
6168 | opn = "trunc.w.s"; |
6169 | break; | |
6170 | case FOP(14, 16): | |
b6d96bed | 6171 | { |
a7812ae4 | 6172 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6173 | |
6174 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6175 | gen_helper_float_ceilw_s(fp0, fp0); |
b6d96bed | 6176 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6177 | tcg_temp_free_i32(fp0); |
b6d96bed | 6178 | } |
5a5012ec TS |
6179 | opn = "ceil.w.s"; |
6180 | break; | |
6181 | case FOP(15, 16): | |
b6d96bed | 6182 | { |
a7812ae4 | 6183 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6184 | |
6185 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6186 | gen_helper_float_floorw_s(fp0, fp0); |
b6d96bed | 6187 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6188 | tcg_temp_free_i32(fp0); |
b6d96bed | 6189 | } |
5a5012ec TS |
6190 | opn = "floor.w.s"; |
6191 | break; | |
6192 | case FOP(17, 16): | |
b6d96bed | 6193 | gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1); |
5a5012ec TS |
6194 | opn = "movcf.s"; |
6195 | break; | |
6196 | case FOP(18, 16): | |
a16336e4 TS |
6197 | { |
6198 | int l1 = gen_new_label(); | |
c9297f4d | 6199 | TCGv_i32 fp0; |
a16336e4 | 6200 | |
c9297f4d AJ |
6201 | if (ft != 0) { |
6202 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); | |
6203 | } | |
6204 | fp0 = tcg_temp_new_i32(); | |
b6d96bed TS |
6205 | gen_load_fpr32(fp0, fs); |
6206 | gen_store_fpr32(fp0, fd); | |
a7812ae4 | 6207 | tcg_temp_free_i32(fp0); |
a16336e4 TS |
6208 | gen_set_label(l1); |
6209 | } | |
5a5012ec TS |
6210 | opn = "movz.s"; |
6211 | break; | |
6212 | case FOP(19, 16): | |
a16336e4 TS |
6213 | { |
6214 | int l1 = gen_new_label(); | |
c9297f4d AJ |
6215 | TCGv_i32 fp0; |
6216 | ||
6217 | if (ft != 0) { | |
6218 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); | |
6219 | fp0 = tcg_temp_new_i32(); | |
6220 | gen_load_fpr32(fp0, fs); | |
6221 | gen_store_fpr32(fp0, fd); | |
6222 | tcg_temp_free_i32(fp0); | |
6223 | gen_set_label(l1); | |
6224 | } | |
a16336e4 | 6225 | } |
5a5012ec TS |
6226 | opn = "movn.s"; |
6227 | break; | |
57fa1fb3 | 6228 | case FOP(21, 16): |
b8aa4598 | 6229 | check_cop1x(ctx); |
b6d96bed | 6230 | { |
a7812ae4 | 6231 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6232 | |
6233 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6234 | gen_helper_float_recip_s(fp0, fp0); |
b6d96bed | 6235 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6236 | tcg_temp_free_i32(fp0); |
b6d96bed | 6237 | } |
57fa1fb3 TS |
6238 | opn = "recip.s"; |
6239 | break; | |
6240 | case FOP(22, 16): | |
b8aa4598 | 6241 | check_cop1x(ctx); |
b6d96bed | 6242 | { |
a7812ae4 | 6243 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6244 | |
6245 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6246 | gen_helper_float_rsqrt_s(fp0, fp0); |
b6d96bed | 6247 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6248 | tcg_temp_free_i32(fp0); |
b6d96bed | 6249 | } |
57fa1fb3 TS |
6250 | opn = "rsqrt.s"; |
6251 | break; | |
6252 | case FOP(28, 16): | |
5e755519 | 6253 | check_cp1_64bitmode(ctx); |
b6d96bed | 6254 | { |
a7812ae4 PB |
6255 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
6256 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
6257 | |
6258 | gen_load_fpr32(fp0, fs); | |
6259 | gen_load_fpr32(fp1, fd); | |
a7812ae4 PB |
6260 | gen_helper_float_recip2_s(fp0, fp0, fp1); |
6261 | tcg_temp_free_i32(fp1); | |
b6d96bed | 6262 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6263 | tcg_temp_free_i32(fp0); |
b6d96bed | 6264 | } |
57fa1fb3 TS |
6265 | opn = "recip2.s"; |
6266 | break; | |
6267 | case FOP(29, 16): | |
5e755519 | 6268 | check_cp1_64bitmode(ctx); |
b6d96bed | 6269 | { |
a7812ae4 | 6270 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6271 | |
6272 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6273 | gen_helper_float_recip1_s(fp0, fp0); |
b6d96bed | 6274 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6275 | tcg_temp_free_i32(fp0); |
b6d96bed | 6276 | } |
57fa1fb3 TS |
6277 | opn = "recip1.s"; |
6278 | break; | |
6279 | case FOP(30, 16): | |
5e755519 | 6280 | check_cp1_64bitmode(ctx); |
b6d96bed | 6281 | { |
a7812ae4 | 6282 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6283 | |
6284 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6285 | gen_helper_float_rsqrt1_s(fp0, fp0); |
b6d96bed | 6286 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6287 | tcg_temp_free_i32(fp0); |
b6d96bed | 6288 | } |
57fa1fb3 TS |
6289 | opn = "rsqrt1.s"; |
6290 | break; | |
6291 | case FOP(31, 16): | |
5e755519 | 6292 | check_cp1_64bitmode(ctx); |
b6d96bed | 6293 | { |
a7812ae4 PB |
6294 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
6295 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
6296 | |
6297 | gen_load_fpr32(fp0, fs); | |
6298 | gen_load_fpr32(fp1, ft); | |
a7812ae4 PB |
6299 | gen_helper_float_rsqrt2_s(fp0, fp0, fp1); |
6300 | tcg_temp_free_i32(fp1); | |
b6d96bed | 6301 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6302 | tcg_temp_free_i32(fp0); |
b6d96bed | 6303 | } |
57fa1fb3 TS |
6304 | opn = "rsqrt2.s"; |
6305 | break; | |
5a5012ec | 6306 | case FOP(33, 16): |
5e755519 | 6307 | check_cp1_registers(ctx, fd); |
b6d96bed | 6308 | { |
a7812ae4 PB |
6309 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6310 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6311 | |
6312 | gen_load_fpr32(fp32, fs); | |
a7812ae4 PB |
6313 | gen_helper_float_cvtd_s(fp64, fp32); |
6314 | tcg_temp_free_i32(fp32); | |
b6d96bed | 6315 | gen_store_fpr64(ctx, fp64, fd); |
a7812ae4 | 6316 | tcg_temp_free_i64(fp64); |
b6d96bed | 6317 | } |
5a5012ec TS |
6318 | opn = "cvt.d.s"; |
6319 | break; | |
6320 | case FOP(36, 16): | |
b6d96bed | 6321 | { |
a7812ae4 | 6322 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6323 | |
6324 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6325 | gen_helper_float_cvtw_s(fp0, fp0); |
b6d96bed | 6326 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6327 | tcg_temp_free_i32(fp0); |
b6d96bed | 6328 | } |
5a5012ec TS |
6329 | opn = "cvt.w.s"; |
6330 | break; | |
6331 | case FOP(37, 16): | |
5e755519 | 6332 | check_cp1_64bitmode(ctx); |
b6d96bed | 6333 | { |
a7812ae4 PB |
6334 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6335 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6336 | |
6337 | gen_load_fpr32(fp32, fs); | |
a7812ae4 PB |
6338 | gen_helper_float_cvtl_s(fp64, fp32); |
6339 | tcg_temp_free_i32(fp32); | |
b6d96bed | 6340 | gen_store_fpr64(ctx, fp64, fd); |
a7812ae4 | 6341 | tcg_temp_free_i64(fp64); |
b6d96bed | 6342 | } |
5a5012ec TS |
6343 | opn = "cvt.l.s"; |
6344 | break; | |
6345 | case FOP(38, 16): | |
5e755519 | 6346 | check_cp1_64bitmode(ctx); |
b6d96bed | 6347 | { |
a7812ae4 PB |
6348 | TCGv_i64 fp64 = tcg_temp_new_i64(); |
6349 | TCGv_i32 fp32_0 = tcg_temp_new_i32(); | |
6350 | TCGv_i32 fp32_1 = tcg_temp_new_i32(); | |
b6d96bed TS |
6351 | |
6352 | gen_load_fpr32(fp32_0, fs); | |
6353 | gen_load_fpr32(fp32_1, ft); | |
36aa55dc | 6354 | tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1); |
a7812ae4 PB |
6355 | tcg_temp_free_i32(fp32_1); |
6356 | tcg_temp_free_i32(fp32_0); | |
36aa55dc | 6357 | gen_store_fpr64(ctx, fp64, fd); |
a7812ae4 | 6358 | tcg_temp_free_i64(fp64); |
b6d96bed | 6359 | } |
5a5012ec TS |
6360 | opn = "cvt.ps.s"; |
6361 | break; | |
6362 | case FOP(48, 16): | |
6363 | case FOP(49, 16): | |
6364 | case FOP(50, 16): | |
6365 | case FOP(51, 16): | |
6366 | case FOP(52, 16): | |
6367 | case FOP(53, 16): | |
6368 | case FOP(54, 16): | |
6369 | case FOP(55, 16): | |
6370 | case FOP(56, 16): | |
6371 | case FOP(57, 16): | |
6372 | case FOP(58, 16): | |
6373 | case FOP(59, 16): | |
6374 | case FOP(60, 16): | |
6375 | case FOP(61, 16): | |
6376 | case FOP(62, 16): | |
6377 | case FOP(63, 16): | |
b6d96bed | 6378 | { |
a7812ae4 PB |
6379 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
6380 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
6381 | |
6382 | gen_load_fpr32(fp0, fs); | |
6383 | gen_load_fpr32(fp1, ft); | |
6384 | if (ctx->opcode & (1 << 6)) { | |
8c0ab41f | 6385 | check_cop1x(ctx); |
b6d96bed TS |
6386 | gen_cmpabs_s(func-48, fp0, fp1, cc); |
6387 | opn = condnames_abs[func-48]; | |
6388 | } else { | |
6389 | gen_cmp_s(func-48, fp0, fp1, cc); | |
6390 | opn = condnames[func-48]; | |
6391 | } | |
a7812ae4 PB |
6392 | tcg_temp_free_i32(fp0); |
6393 | tcg_temp_free_i32(fp1); | |
5a1e8ffb | 6394 | } |
5a5012ec | 6395 | break; |
6ea83fed | 6396 | case FOP(0, 17): |
5e755519 | 6397 | check_cp1_registers(ctx, fs | ft | fd); |
b6d96bed | 6398 | { |
a7812ae4 PB |
6399 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6400 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6401 | |
6402 | gen_load_fpr64(ctx, fp0, fs); | |
6403 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
6404 | gen_helper_float_add_d(fp0, fp0, fp1); |
6405 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6406 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6407 | tcg_temp_free_i64(fp0); |
b6d96bed | 6408 | } |
6ea83fed | 6409 | opn = "add.d"; |
5a1e8ffb | 6410 | optype = BINOP; |
6ea83fed FB |
6411 | break; |
6412 | case FOP(1, 17): | |
5e755519 | 6413 | check_cp1_registers(ctx, fs | ft | fd); |
b6d96bed | 6414 | { |
a7812ae4 PB |
6415 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6416 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6417 | |
6418 | gen_load_fpr64(ctx, fp0, fs); | |
6419 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
6420 | gen_helper_float_sub_d(fp0, fp0, fp1); |
6421 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6422 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6423 | tcg_temp_free_i64(fp0); |
b6d96bed | 6424 | } |
6ea83fed | 6425 | opn = "sub.d"; |
5a1e8ffb | 6426 | optype = BINOP; |
6ea83fed FB |
6427 | break; |
6428 | case FOP(2, 17): | |
5e755519 | 6429 | check_cp1_registers(ctx, fs | ft | fd); |
b6d96bed | 6430 | { |
a7812ae4 PB |
6431 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6432 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6433 | |
6434 | gen_load_fpr64(ctx, fp0, fs); | |
6435 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
6436 | gen_helper_float_mul_d(fp0, fp0, fp1); |
6437 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6438 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6439 | tcg_temp_free_i64(fp0); |
b6d96bed | 6440 | } |
6ea83fed | 6441 | opn = "mul.d"; |
5a1e8ffb | 6442 | optype = BINOP; |
6ea83fed FB |
6443 | break; |
6444 | case FOP(3, 17): | |
5e755519 | 6445 | check_cp1_registers(ctx, fs | ft | fd); |
b6d96bed | 6446 | { |
a7812ae4 PB |
6447 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6448 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6449 | |
6450 | gen_load_fpr64(ctx, fp0, fs); | |
6451 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
6452 | gen_helper_float_div_d(fp0, fp0, fp1); |
6453 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6454 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6455 | tcg_temp_free_i64(fp0); |
b6d96bed | 6456 | } |
6ea83fed | 6457 | opn = "div.d"; |
5a1e8ffb | 6458 | optype = BINOP; |
6ea83fed FB |
6459 | break; |
6460 | case FOP(4, 17): | |
5e755519 | 6461 | check_cp1_registers(ctx, fs | fd); |
b6d96bed | 6462 | { |
a7812ae4 | 6463 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6464 | |
6465 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6466 | gen_helper_float_sqrt_d(fp0, fp0); |
b6d96bed | 6467 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6468 | tcg_temp_free_i64(fp0); |
b6d96bed | 6469 | } |
6ea83fed FB |
6470 | opn = "sqrt.d"; |
6471 | break; | |
6472 | case FOP(5, 17): | |
5e755519 | 6473 | check_cp1_registers(ctx, fs | fd); |
b6d96bed | 6474 | { |
a7812ae4 | 6475 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6476 | |
6477 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6478 | gen_helper_float_abs_d(fp0, fp0); |
b6d96bed | 6479 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6480 | tcg_temp_free_i64(fp0); |
b6d96bed | 6481 | } |
6ea83fed FB |
6482 | opn = "abs.d"; |
6483 | break; | |
6484 | case FOP(6, 17): | |
5e755519 | 6485 | check_cp1_registers(ctx, fs | fd); |
b6d96bed | 6486 | { |
a7812ae4 | 6487 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6488 | |
6489 | gen_load_fpr64(ctx, fp0, fs); | |
6490 | gen_store_fpr64(ctx, fp0, fd); | |
a7812ae4 | 6491 | tcg_temp_free_i64(fp0); |
b6d96bed | 6492 | } |
6ea83fed FB |
6493 | opn = "mov.d"; |
6494 | break; | |
6495 | case FOP(7, 17): | |
5e755519 | 6496 | check_cp1_registers(ctx, fs | fd); |
b6d96bed | 6497 | { |
a7812ae4 | 6498 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6499 | |
6500 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6501 | gen_helper_float_chs_d(fp0, fp0); |
b6d96bed | 6502 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6503 | tcg_temp_free_i64(fp0); |
b6d96bed | 6504 | } |
6ea83fed FB |
6505 | opn = "neg.d"; |
6506 | break; | |
5a5012ec | 6507 | case FOP(8, 17): |
5e755519 | 6508 | check_cp1_64bitmode(ctx); |
b6d96bed | 6509 | { |
a7812ae4 | 6510 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6511 | |
6512 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6513 | gen_helper_float_roundl_d(fp0, fp0); |
b6d96bed | 6514 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6515 | tcg_temp_free_i64(fp0); |
b6d96bed | 6516 | } |
5a5012ec TS |
6517 | opn = "round.l.d"; |
6518 | break; | |
6519 | case FOP(9, 17): | |
5e755519 | 6520 | check_cp1_64bitmode(ctx); |
b6d96bed | 6521 | { |
a7812ae4 | 6522 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6523 | |
6524 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6525 | gen_helper_float_truncl_d(fp0, fp0); |
b6d96bed | 6526 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6527 | tcg_temp_free_i64(fp0); |
b6d96bed | 6528 | } |
5a5012ec TS |
6529 | opn = "trunc.l.d"; |
6530 | break; | |
6531 | case FOP(10, 17): | |
5e755519 | 6532 | check_cp1_64bitmode(ctx); |
b6d96bed | 6533 | { |
a7812ae4 | 6534 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6535 | |
6536 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6537 | gen_helper_float_ceill_d(fp0, fp0); |
b6d96bed | 6538 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6539 | tcg_temp_free_i64(fp0); |
b6d96bed | 6540 | } |
5a5012ec TS |
6541 | opn = "ceil.l.d"; |
6542 | break; | |
6543 | case FOP(11, 17): | |
5e755519 | 6544 | check_cp1_64bitmode(ctx); |
b6d96bed | 6545 | { |
a7812ae4 | 6546 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6547 | |
6548 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6549 | gen_helper_float_floorl_d(fp0, fp0); |
b6d96bed | 6550 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6551 | tcg_temp_free_i64(fp0); |
b6d96bed | 6552 | } |
5a5012ec TS |
6553 | opn = "floor.l.d"; |
6554 | break; | |
6ea83fed | 6555 | case FOP(12, 17): |
5e755519 | 6556 | check_cp1_registers(ctx, fs); |
b6d96bed | 6557 | { |
a7812ae4 PB |
6558 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6559 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6560 | |
6561 | gen_load_fpr64(ctx, fp64, fs); | |
a7812ae4 PB |
6562 | gen_helper_float_roundw_d(fp32, fp64); |
6563 | tcg_temp_free_i64(fp64); | |
b6d96bed | 6564 | gen_store_fpr32(fp32, fd); |
a7812ae4 | 6565 | tcg_temp_free_i32(fp32); |
b6d96bed | 6566 | } |
6ea83fed FB |
6567 | opn = "round.w.d"; |
6568 | break; | |
6569 | case FOP(13, 17): | |
5e755519 | 6570 | check_cp1_registers(ctx, fs); |
b6d96bed | 6571 | { |
a7812ae4 PB |
6572 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6573 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6574 | |
6575 | gen_load_fpr64(ctx, fp64, fs); | |
a7812ae4 PB |
6576 | gen_helper_float_truncw_d(fp32, fp64); |
6577 | tcg_temp_free_i64(fp64); | |
b6d96bed | 6578 | gen_store_fpr32(fp32, fd); |
a7812ae4 | 6579 | tcg_temp_free_i32(fp32); |
b6d96bed | 6580 | } |
6ea83fed FB |
6581 | opn = "trunc.w.d"; |
6582 | break; | |
6583 | case FOP(14, 17): | |
5e755519 | 6584 | check_cp1_registers(ctx, fs); |
b6d96bed | 6585 | { |
a7812ae4 PB |
6586 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6587 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6588 | |
6589 | gen_load_fpr64(ctx, fp64, fs); | |
a7812ae4 PB |
6590 | gen_helper_float_ceilw_d(fp32, fp64); |
6591 | tcg_temp_free_i64(fp64); | |
b6d96bed | 6592 | gen_store_fpr32(fp32, fd); |
a7812ae4 | 6593 | tcg_temp_free_i32(fp32); |
b6d96bed | 6594 | } |
6ea83fed FB |
6595 | opn = "ceil.w.d"; |
6596 | break; | |
6597 | case FOP(15, 17): | |
5e755519 | 6598 | check_cp1_registers(ctx, fs); |
b6d96bed | 6599 | { |
a7812ae4 PB |
6600 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6601 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6602 | |
6603 | gen_load_fpr64(ctx, fp64, fs); | |
a7812ae4 PB |
6604 | gen_helper_float_floorw_d(fp32, fp64); |
6605 | tcg_temp_free_i64(fp64); | |
b6d96bed | 6606 | gen_store_fpr32(fp32, fd); |
a7812ae4 | 6607 | tcg_temp_free_i32(fp32); |
b6d96bed | 6608 | } |
7a387fff | 6609 | opn = "floor.w.d"; |
6ea83fed | 6610 | break; |
5a5012ec | 6611 | case FOP(17, 17): |
b6d96bed | 6612 | gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); |
5a5012ec | 6613 | opn = "movcf.d"; |
dd016883 | 6614 | break; |
5a5012ec | 6615 | case FOP(18, 17): |
a16336e4 TS |
6616 | { |
6617 | int l1 = gen_new_label(); | |
c9297f4d | 6618 | TCGv_i64 fp0; |
a16336e4 | 6619 | |
c9297f4d AJ |
6620 | if (ft != 0) { |
6621 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); | |
6622 | } | |
6623 | fp0 = tcg_temp_new_i64(); | |
b6d96bed TS |
6624 | gen_load_fpr64(ctx, fp0, fs); |
6625 | gen_store_fpr64(ctx, fp0, fd); | |
a7812ae4 | 6626 | tcg_temp_free_i64(fp0); |
a16336e4 TS |
6627 | gen_set_label(l1); |
6628 | } | |
5a5012ec TS |
6629 | opn = "movz.d"; |
6630 | break; | |
6631 | case FOP(19, 17): | |
a16336e4 TS |
6632 | { |
6633 | int l1 = gen_new_label(); | |
c9297f4d AJ |
6634 | TCGv_i64 fp0; |
6635 | ||
6636 | if (ft != 0) { | |
6637 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); | |
6638 | fp0 = tcg_temp_new_i64(); | |
6639 | gen_load_fpr64(ctx, fp0, fs); | |
6640 | gen_store_fpr64(ctx, fp0, fd); | |
6641 | tcg_temp_free_i64(fp0); | |
6642 | gen_set_label(l1); | |
6643 | } | |
a16336e4 | 6644 | } |
5a5012ec | 6645 | opn = "movn.d"; |
6ea83fed | 6646 | break; |
57fa1fb3 | 6647 | case FOP(21, 17): |
b8aa4598 | 6648 | check_cp1_64bitmode(ctx); |
b6d96bed | 6649 | { |
a7812ae4 | 6650 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6651 | |
6652 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6653 | gen_helper_float_recip_d(fp0, fp0); |
b6d96bed | 6654 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6655 | tcg_temp_free_i64(fp0); |
b6d96bed | 6656 | } |
57fa1fb3 TS |
6657 | opn = "recip.d"; |
6658 | break; | |
6659 | case FOP(22, 17): | |
b8aa4598 | 6660 | check_cp1_64bitmode(ctx); |
b6d96bed | 6661 | { |
a7812ae4 | 6662 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6663 | |
6664 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6665 | gen_helper_float_rsqrt_d(fp0, fp0); |
b6d96bed | 6666 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6667 | tcg_temp_free_i64(fp0); |
b6d96bed | 6668 | } |
57fa1fb3 TS |
6669 | opn = "rsqrt.d"; |
6670 | break; | |
6671 | case FOP(28, 17): | |
5e755519 | 6672 | check_cp1_64bitmode(ctx); |
b6d96bed | 6673 | { |
a7812ae4 PB |
6674 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6675 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6676 | |
6677 | gen_load_fpr64(ctx, fp0, fs); | |
6678 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
6679 | gen_helper_float_recip2_d(fp0, fp0, fp1); |
6680 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6681 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6682 | tcg_temp_free_i64(fp0); |
b6d96bed | 6683 | } |
57fa1fb3 TS |
6684 | opn = "recip2.d"; |
6685 | break; | |
6686 | case FOP(29, 17): | |
5e755519 | 6687 | check_cp1_64bitmode(ctx); |
b6d96bed | 6688 | { |
a7812ae4 | 6689 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6690 | |
6691 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6692 | gen_helper_float_recip1_d(fp0, fp0); |
b6d96bed | 6693 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6694 | tcg_temp_free_i64(fp0); |
b6d96bed | 6695 | } |
57fa1fb3 TS |
6696 | opn = "recip1.d"; |
6697 | break; | |
6698 | case FOP(30, 17): | |
5e755519 | 6699 | check_cp1_64bitmode(ctx); |
b6d96bed | 6700 | { |
a7812ae4 | 6701 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6702 | |
6703 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6704 | gen_helper_float_rsqrt1_d(fp0, fp0); |
b6d96bed | 6705 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6706 | tcg_temp_free_i64(fp0); |
b6d96bed | 6707 | } |
57fa1fb3 TS |
6708 | opn = "rsqrt1.d"; |
6709 | break; | |
6710 | case FOP(31, 17): | |
5e755519 | 6711 | check_cp1_64bitmode(ctx); |
b6d96bed | 6712 | { |
a7812ae4 PB |
6713 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6714 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6715 | |
6716 | gen_load_fpr64(ctx, fp0, fs); | |
6717 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
6718 | gen_helper_float_rsqrt2_d(fp0, fp0, fp1); |
6719 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6720 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6721 | tcg_temp_free_i64(fp0); |
b6d96bed | 6722 | } |
57fa1fb3 TS |
6723 | opn = "rsqrt2.d"; |
6724 | break; | |
6ea83fed FB |
6725 | case FOP(48, 17): |
6726 | case FOP(49, 17): | |
6727 | case FOP(50, 17): | |
6728 | case FOP(51, 17): | |
6729 | case FOP(52, 17): | |
6730 | case FOP(53, 17): | |
6731 | case FOP(54, 17): | |
6732 | case FOP(55, 17): | |
6733 | case FOP(56, 17): | |
6734 | case FOP(57, 17): | |
6735 | case FOP(58, 17): | |
6736 | case FOP(59, 17): | |
6737 | case FOP(60, 17): | |
6738 | case FOP(61, 17): | |
6739 | case FOP(62, 17): | |
6740 | case FOP(63, 17): | |
b6d96bed | 6741 | { |
a7812ae4 PB |
6742 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6743 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6744 | |
6745 | gen_load_fpr64(ctx, fp0, fs); | |
6746 | gen_load_fpr64(ctx, fp1, ft); | |
6747 | if (ctx->opcode & (1 << 6)) { | |
8c0ab41f AJ |
6748 | check_cop1x(ctx); |
6749 | check_cp1_registers(ctx, fs | ft); | |
b6d96bed TS |
6750 | gen_cmpabs_d(func-48, fp0, fp1, cc); |
6751 | opn = condnames_abs[func-48]; | |
6752 | } else { | |
8c0ab41f | 6753 | check_cp1_registers(ctx, fs | ft); |
b6d96bed TS |
6754 | gen_cmp_d(func-48, fp0, fp1, cc); |
6755 | opn = condnames[func-48]; | |
6756 | } | |
a7812ae4 PB |
6757 | tcg_temp_free_i64(fp0); |
6758 | tcg_temp_free_i64(fp1); | |
5a1e8ffb | 6759 | } |
6ea83fed | 6760 | break; |
5a5012ec | 6761 | case FOP(32, 17): |
5e755519 | 6762 | check_cp1_registers(ctx, fs); |
b6d96bed | 6763 | { |
a7812ae4 PB |
6764 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6765 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6766 | |
6767 | gen_load_fpr64(ctx, fp64, fs); | |
a7812ae4 PB |
6768 | gen_helper_float_cvts_d(fp32, fp64); |
6769 | tcg_temp_free_i64(fp64); | |
b6d96bed | 6770 | gen_store_fpr32(fp32, fd); |
a7812ae4 | 6771 | tcg_temp_free_i32(fp32); |
b6d96bed | 6772 | } |
5a5012ec TS |
6773 | opn = "cvt.s.d"; |
6774 | break; | |
6775 | case FOP(36, 17): | |
5e755519 | 6776 | check_cp1_registers(ctx, fs); |
b6d96bed | 6777 | { |
a7812ae4 PB |
6778 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6779 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6780 | |
6781 | gen_load_fpr64(ctx, fp64, fs); | |
a7812ae4 PB |
6782 | gen_helper_float_cvtw_d(fp32, fp64); |
6783 | tcg_temp_free_i64(fp64); | |
b6d96bed | 6784 | gen_store_fpr32(fp32, fd); |
a7812ae4 | 6785 | tcg_temp_free_i32(fp32); |
b6d96bed | 6786 | } |
5a5012ec TS |
6787 | opn = "cvt.w.d"; |
6788 | break; | |
6789 | case FOP(37, 17): | |
5e755519 | 6790 | check_cp1_64bitmode(ctx); |
b6d96bed | 6791 | { |
a7812ae4 | 6792 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6793 | |
6794 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6795 | gen_helper_float_cvtl_d(fp0, fp0); |
b6d96bed | 6796 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6797 | tcg_temp_free_i64(fp0); |
b6d96bed | 6798 | } |
5a5012ec TS |
6799 | opn = "cvt.l.d"; |
6800 | break; | |
6801 | case FOP(32, 20): | |
b6d96bed | 6802 | { |
a7812ae4 | 6803 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
6804 | |
6805 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 6806 | gen_helper_float_cvts_w(fp0, fp0); |
b6d96bed | 6807 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 6808 | tcg_temp_free_i32(fp0); |
b6d96bed | 6809 | } |
5a5012ec | 6810 | opn = "cvt.s.w"; |
6ea83fed | 6811 | break; |
5a5012ec | 6812 | case FOP(33, 20): |
5e755519 | 6813 | check_cp1_registers(ctx, fd); |
b6d96bed | 6814 | { |
a7812ae4 PB |
6815 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6816 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6817 | |
6818 | gen_load_fpr32(fp32, fs); | |
a7812ae4 PB |
6819 | gen_helper_float_cvtd_w(fp64, fp32); |
6820 | tcg_temp_free_i32(fp32); | |
b6d96bed | 6821 | gen_store_fpr64(ctx, fp64, fd); |
a7812ae4 | 6822 | tcg_temp_free_i64(fp64); |
b6d96bed | 6823 | } |
5a5012ec TS |
6824 | opn = "cvt.d.w"; |
6825 | break; | |
6826 | case FOP(32, 21): | |
5e755519 | 6827 | check_cp1_64bitmode(ctx); |
b6d96bed | 6828 | { |
a7812ae4 PB |
6829 | TCGv_i32 fp32 = tcg_temp_new_i32(); |
6830 | TCGv_i64 fp64 = tcg_temp_new_i64(); | |
b6d96bed TS |
6831 | |
6832 | gen_load_fpr64(ctx, fp64, fs); | |
a7812ae4 PB |
6833 | gen_helper_float_cvts_l(fp32, fp64); |
6834 | tcg_temp_free_i64(fp64); | |
b6d96bed | 6835 | gen_store_fpr32(fp32, fd); |
a7812ae4 | 6836 | tcg_temp_free_i32(fp32); |
b6d96bed | 6837 | } |
5a5012ec TS |
6838 | opn = "cvt.s.l"; |
6839 | break; | |
6840 | case FOP(33, 21): | |
5e755519 | 6841 | check_cp1_64bitmode(ctx); |
b6d96bed | 6842 | { |
a7812ae4 | 6843 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6844 | |
6845 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6846 | gen_helper_float_cvtd_l(fp0, fp0); |
b6d96bed | 6847 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6848 | tcg_temp_free_i64(fp0); |
b6d96bed | 6849 | } |
5a5012ec TS |
6850 | opn = "cvt.d.l"; |
6851 | break; | |
6852 | case FOP(38, 20): | |
5e755519 | 6853 | check_cp1_64bitmode(ctx); |
b6d96bed | 6854 | { |
a7812ae4 | 6855 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6856 | |
6857 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6858 | gen_helper_float_cvtps_pw(fp0, fp0); |
b6d96bed | 6859 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6860 | tcg_temp_free_i64(fp0); |
b6d96bed | 6861 | } |
5a5012ec TS |
6862 | opn = "cvt.ps.pw"; |
6863 | break; | |
6864 | case FOP(0, 22): | |
5e755519 | 6865 | check_cp1_64bitmode(ctx); |
b6d96bed | 6866 | { |
a7812ae4 PB |
6867 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6868 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6869 | |
6870 | gen_load_fpr64(ctx, fp0, fs); | |
6871 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
6872 | gen_helper_float_add_ps(fp0, fp0, fp1); |
6873 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6874 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6875 | tcg_temp_free_i64(fp0); |
b6d96bed | 6876 | } |
5a5012ec | 6877 | opn = "add.ps"; |
6ea83fed | 6878 | break; |
5a5012ec | 6879 | case FOP(1, 22): |
5e755519 | 6880 | check_cp1_64bitmode(ctx); |
b6d96bed | 6881 | { |
a7812ae4 PB |
6882 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6883 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6884 | |
6885 | gen_load_fpr64(ctx, fp0, fs); | |
6886 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
6887 | gen_helper_float_sub_ps(fp0, fp0, fp1); |
6888 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6889 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6890 | tcg_temp_free_i64(fp0); |
b6d96bed | 6891 | } |
5a5012ec | 6892 | opn = "sub.ps"; |
6ea83fed | 6893 | break; |
5a5012ec | 6894 | case FOP(2, 22): |
5e755519 | 6895 | check_cp1_64bitmode(ctx); |
b6d96bed | 6896 | { |
a7812ae4 PB |
6897 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6898 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6899 | |
6900 | gen_load_fpr64(ctx, fp0, fs); | |
6901 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
6902 | gen_helper_float_mul_ps(fp0, fp0, fp1); |
6903 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6904 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6905 | tcg_temp_free_i64(fp0); |
b6d96bed | 6906 | } |
5a5012ec | 6907 | opn = "mul.ps"; |
6ea83fed | 6908 | break; |
5a5012ec | 6909 | case FOP(5, 22): |
5e755519 | 6910 | check_cp1_64bitmode(ctx); |
b6d96bed | 6911 | { |
a7812ae4 | 6912 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6913 | |
6914 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6915 | gen_helper_float_abs_ps(fp0, fp0); |
b6d96bed | 6916 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6917 | tcg_temp_free_i64(fp0); |
b6d96bed | 6918 | } |
5a5012ec | 6919 | opn = "abs.ps"; |
6ea83fed | 6920 | break; |
5a5012ec | 6921 | case FOP(6, 22): |
5e755519 | 6922 | check_cp1_64bitmode(ctx); |
b6d96bed | 6923 | { |
a7812ae4 | 6924 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6925 | |
6926 | gen_load_fpr64(ctx, fp0, fs); | |
6927 | gen_store_fpr64(ctx, fp0, fd); | |
a7812ae4 | 6928 | tcg_temp_free_i64(fp0); |
b6d96bed | 6929 | } |
5a5012ec | 6930 | opn = "mov.ps"; |
6ea83fed | 6931 | break; |
5a5012ec | 6932 | case FOP(7, 22): |
5e755519 | 6933 | check_cp1_64bitmode(ctx); |
b6d96bed | 6934 | { |
a7812ae4 | 6935 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
6936 | |
6937 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 6938 | gen_helper_float_chs_ps(fp0, fp0); |
b6d96bed | 6939 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6940 | tcg_temp_free_i64(fp0); |
b6d96bed | 6941 | } |
5a5012ec | 6942 | opn = "neg.ps"; |
6ea83fed | 6943 | break; |
5a5012ec | 6944 | case FOP(17, 22): |
5e755519 | 6945 | check_cp1_64bitmode(ctx); |
b6d96bed | 6946 | gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1); |
5a5012ec | 6947 | opn = "movcf.ps"; |
6ea83fed | 6948 | break; |
5a5012ec | 6949 | case FOP(18, 22): |
5e755519 | 6950 | check_cp1_64bitmode(ctx); |
a16336e4 TS |
6951 | { |
6952 | int l1 = gen_new_label(); | |
30a3848b | 6953 | TCGv_i64 fp0; |
a16336e4 | 6954 | |
c9297f4d AJ |
6955 | if (ft != 0) |
6956 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); | |
6957 | fp0 = tcg_temp_new_i64(); | |
6958 | gen_load_fpr64(ctx, fp0, fs); | |
6959 | gen_store_fpr64(ctx, fp0, fd); | |
6960 | tcg_temp_free_i64(fp0); | |
a16336e4 TS |
6961 | gen_set_label(l1); |
6962 | } | |
5a5012ec | 6963 | opn = "movz.ps"; |
6ea83fed | 6964 | break; |
5a5012ec | 6965 | case FOP(19, 22): |
5e755519 | 6966 | check_cp1_64bitmode(ctx); |
a16336e4 TS |
6967 | { |
6968 | int l1 = gen_new_label(); | |
30a3848b | 6969 | TCGv_i64 fp0; |
c9297f4d AJ |
6970 | |
6971 | if (ft != 0) { | |
6972 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); | |
6973 | fp0 = tcg_temp_new_i64(); | |
6974 | gen_load_fpr64(ctx, fp0, fs); | |
6975 | gen_store_fpr64(ctx, fp0, fd); | |
6976 | tcg_temp_free_i64(fp0); | |
6977 | gen_set_label(l1); | |
6978 | } | |
a16336e4 | 6979 | } |
5a5012ec | 6980 | opn = "movn.ps"; |
6ea83fed | 6981 | break; |
fbcc6828 | 6982 | case FOP(24, 22): |
5e755519 | 6983 | check_cp1_64bitmode(ctx); |
b6d96bed | 6984 | { |
a7812ae4 PB |
6985 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
6986 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
6987 | |
6988 | gen_load_fpr64(ctx, fp0, ft); | |
6989 | gen_load_fpr64(ctx, fp1, fs); | |
a7812ae4 PB |
6990 | gen_helper_float_addr_ps(fp0, fp0, fp1); |
6991 | tcg_temp_free_i64(fp1); | |
b6d96bed | 6992 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 6993 | tcg_temp_free_i64(fp0); |
b6d96bed | 6994 | } |
fbcc6828 TS |
6995 | opn = "addr.ps"; |
6996 | break; | |
57fa1fb3 | 6997 | case FOP(26, 22): |
5e755519 | 6998 | check_cp1_64bitmode(ctx); |
b6d96bed | 6999 | { |
a7812ae4 PB |
7000 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7001 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
7002 | |
7003 | gen_load_fpr64(ctx, fp0, ft); | |
7004 | gen_load_fpr64(ctx, fp1, fs); | |
a7812ae4 PB |
7005 | gen_helper_float_mulr_ps(fp0, fp0, fp1); |
7006 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7007 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 7008 | tcg_temp_free_i64(fp0); |
b6d96bed | 7009 | } |
57fa1fb3 TS |
7010 | opn = "mulr.ps"; |
7011 | break; | |
7012 | case FOP(28, 22): | |
5e755519 | 7013 | check_cp1_64bitmode(ctx); |
b6d96bed | 7014 | { |
a7812ae4 PB |
7015 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7016 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
7017 | |
7018 | gen_load_fpr64(ctx, fp0, fs); | |
7019 | gen_load_fpr64(ctx, fp1, fd); | |
a7812ae4 PB |
7020 | gen_helper_float_recip2_ps(fp0, fp0, fp1); |
7021 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7022 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 7023 | tcg_temp_free_i64(fp0); |
b6d96bed | 7024 | } |
57fa1fb3 TS |
7025 | opn = "recip2.ps"; |
7026 | break; | |
7027 | case FOP(29, 22): | |
5e755519 | 7028 | check_cp1_64bitmode(ctx); |
b6d96bed | 7029 | { |
a7812ae4 | 7030 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
7031 | |
7032 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 7033 | gen_helper_float_recip1_ps(fp0, fp0); |
b6d96bed | 7034 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 7035 | tcg_temp_free_i64(fp0); |
b6d96bed | 7036 | } |
57fa1fb3 TS |
7037 | opn = "recip1.ps"; |
7038 | break; | |
7039 | case FOP(30, 22): | |
5e755519 | 7040 | check_cp1_64bitmode(ctx); |
b6d96bed | 7041 | { |
a7812ae4 | 7042 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
7043 | |
7044 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 7045 | gen_helper_float_rsqrt1_ps(fp0, fp0); |
b6d96bed | 7046 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 7047 | tcg_temp_free_i64(fp0); |
b6d96bed | 7048 | } |
57fa1fb3 TS |
7049 | opn = "rsqrt1.ps"; |
7050 | break; | |
7051 | case FOP(31, 22): | |
5e755519 | 7052 | check_cp1_64bitmode(ctx); |
b6d96bed | 7053 | { |
a7812ae4 PB |
7054 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7055 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
7056 | |
7057 | gen_load_fpr64(ctx, fp0, fs); | |
7058 | gen_load_fpr64(ctx, fp1, ft); | |
a7812ae4 PB |
7059 | gen_helper_float_rsqrt2_ps(fp0, fp0, fp1); |
7060 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7061 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 7062 | tcg_temp_free_i64(fp0); |
b6d96bed | 7063 | } |
57fa1fb3 TS |
7064 | opn = "rsqrt2.ps"; |
7065 | break; | |
5a5012ec | 7066 | case FOP(32, 22): |
5e755519 | 7067 | check_cp1_64bitmode(ctx); |
b6d96bed | 7068 | { |
a7812ae4 | 7069 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
7070 | |
7071 | gen_load_fpr32h(fp0, fs); | |
a7812ae4 | 7072 | gen_helper_float_cvts_pu(fp0, fp0); |
b6d96bed | 7073 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 7074 | tcg_temp_free_i32(fp0); |
b6d96bed | 7075 | } |
5a5012ec | 7076 | opn = "cvt.s.pu"; |
dd016883 | 7077 | break; |
5a5012ec | 7078 | case FOP(36, 22): |
5e755519 | 7079 | check_cp1_64bitmode(ctx); |
b6d96bed | 7080 | { |
a7812ae4 | 7081 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
7082 | |
7083 | gen_load_fpr64(ctx, fp0, fs); | |
a7812ae4 | 7084 | gen_helper_float_cvtpw_ps(fp0, fp0); |
b6d96bed | 7085 | gen_store_fpr64(ctx, fp0, fd); |
a7812ae4 | 7086 | tcg_temp_free_i64(fp0); |
b6d96bed | 7087 | } |
5a5012ec | 7088 | opn = "cvt.pw.ps"; |
6ea83fed | 7089 | break; |
5a5012ec | 7090 | case FOP(40, 22): |
5e755519 | 7091 | check_cp1_64bitmode(ctx); |
b6d96bed | 7092 | { |
a7812ae4 | 7093 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed TS |
7094 | |
7095 | gen_load_fpr32(fp0, fs); | |
a7812ae4 | 7096 | gen_helper_float_cvts_pl(fp0, fp0); |
b6d96bed | 7097 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 7098 | tcg_temp_free_i32(fp0); |
b6d96bed | 7099 | } |
5a5012ec | 7100 | opn = "cvt.s.pl"; |
6ea83fed | 7101 | break; |
5a5012ec | 7102 | case FOP(44, 22): |
5e755519 | 7103 | check_cp1_64bitmode(ctx); |
b6d96bed | 7104 | { |
a7812ae4 PB |
7105 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
7106 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
7107 | |
7108 | gen_load_fpr32(fp0, fs); | |
7109 | gen_load_fpr32(fp1, ft); | |
7110 | gen_store_fpr32h(fp0, fd); | |
7111 | gen_store_fpr32(fp1, fd); | |
a7812ae4 PB |
7112 | tcg_temp_free_i32(fp0); |
7113 | tcg_temp_free_i32(fp1); | |
b6d96bed | 7114 | } |
5a5012ec | 7115 | opn = "pll.ps"; |
6ea83fed | 7116 | break; |
5a5012ec | 7117 | case FOP(45, 22): |
5e755519 | 7118 | check_cp1_64bitmode(ctx); |
b6d96bed | 7119 | { |
a7812ae4 PB |
7120 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
7121 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
7122 | |
7123 | gen_load_fpr32(fp0, fs); | |
7124 | gen_load_fpr32h(fp1, ft); | |
7125 | gen_store_fpr32(fp1, fd); | |
7126 | gen_store_fpr32h(fp0, fd); | |
a7812ae4 PB |
7127 | tcg_temp_free_i32(fp0); |
7128 | tcg_temp_free_i32(fp1); | |
b6d96bed | 7129 | } |
5a5012ec TS |
7130 | opn = "plu.ps"; |
7131 | break; | |
7132 | case FOP(46, 22): | |
5e755519 | 7133 | check_cp1_64bitmode(ctx); |
b6d96bed | 7134 | { |
a7812ae4 PB |
7135 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
7136 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
7137 | |
7138 | gen_load_fpr32h(fp0, fs); | |
7139 | gen_load_fpr32(fp1, ft); | |
7140 | gen_store_fpr32(fp1, fd); | |
7141 | gen_store_fpr32h(fp0, fd); | |
a7812ae4 PB |
7142 | tcg_temp_free_i32(fp0); |
7143 | tcg_temp_free_i32(fp1); | |
b6d96bed | 7144 | } |
5a5012ec TS |
7145 | opn = "pul.ps"; |
7146 | break; | |
7147 | case FOP(47, 22): | |
5e755519 | 7148 | check_cp1_64bitmode(ctx); |
b6d96bed | 7149 | { |
a7812ae4 PB |
7150 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
7151 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
b6d96bed TS |
7152 | |
7153 | gen_load_fpr32h(fp0, fs); | |
7154 | gen_load_fpr32h(fp1, ft); | |
7155 | gen_store_fpr32(fp1, fd); | |
7156 | gen_store_fpr32h(fp0, fd); | |
a7812ae4 PB |
7157 | tcg_temp_free_i32(fp0); |
7158 | tcg_temp_free_i32(fp1); | |
b6d96bed | 7159 | } |
5a5012ec TS |
7160 | opn = "puu.ps"; |
7161 | break; | |
7162 | case FOP(48, 22): | |
7163 | case FOP(49, 22): | |
7164 | case FOP(50, 22): | |
7165 | case FOP(51, 22): | |
7166 | case FOP(52, 22): | |
7167 | case FOP(53, 22): | |
7168 | case FOP(54, 22): | |
7169 | case FOP(55, 22): | |
7170 | case FOP(56, 22): | |
7171 | case FOP(57, 22): | |
7172 | case FOP(58, 22): | |
7173 | case FOP(59, 22): | |
7174 | case FOP(60, 22): | |
7175 | case FOP(61, 22): | |
7176 | case FOP(62, 22): | |
7177 | case FOP(63, 22): | |
5e755519 | 7178 | check_cp1_64bitmode(ctx); |
b6d96bed | 7179 | { |
a7812ae4 PB |
7180 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7181 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
b6d96bed TS |
7182 | |
7183 | gen_load_fpr64(ctx, fp0, fs); | |
7184 | gen_load_fpr64(ctx, fp1, ft); | |
7185 | if (ctx->opcode & (1 << 6)) { | |
7186 | gen_cmpabs_ps(func-48, fp0, fp1, cc); | |
7187 | opn = condnames_abs[func-48]; | |
7188 | } else { | |
7189 | gen_cmp_ps(func-48, fp0, fp1, cc); | |
7190 | opn = condnames[func-48]; | |
7191 | } | |
a7812ae4 PB |
7192 | tcg_temp_free_i64(fp0); |
7193 | tcg_temp_free_i64(fp1); | |
5a1e8ffb | 7194 | } |
6ea83fed | 7195 | break; |
5a5012ec | 7196 | default: |
923617a3 | 7197 | MIPS_INVAL(opn); |
e397ee33 | 7198 | generate_exception (ctx, EXCP_RI); |
6ea83fed FB |
7199 | return; |
7200 | } | |
5a1e8ffb TS |
7201 | switch (optype) { |
7202 | case BINOP: | |
6ea83fed | 7203 | MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]); |
5a1e8ffb TS |
7204 | break; |
7205 | case CMPOP: | |
7206 | MIPS_DEBUG("%s %s,%s", opn, fregnames[fs], fregnames[ft]); | |
7207 | break; | |
7208 | default: | |
6ea83fed | 7209 | MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]); |
5a1e8ffb TS |
7210 | break; |
7211 | } | |
6ea83fed | 7212 | } |
6af0bf9c | 7213 | |
5a5012ec | 7214 | /* Coprocessor 3 (FPU) */ |
5e755519 TS |
7215 | static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, |
7216 | int fd, int fs, int base, int index) | |
7a387fff | 7217 | { |
923617a3 | 7218 | const char *opn = "extended float load/store"; |
93b12ccc | 7219 | int store = 0; |
4e2474d6 | 7220 | TCGv t0 = tcg_temp_new(); |
7a387fff | 7221 | |
93b12ccc | 7222 | if (base == 0) { |
6c5c1e20 | 7223 | gen_load_gpr(t0, index); |
93b12ccc | 7224 | } else if (index == 0) { |
6c5c1e20 | 7225 | gen_load_gpr(t0, base); |
93b12ccc | 7226 | } else { |
e9203484 AJ |
7227 | gen_load_gpr(t0, index); |
7228 | gen_op_addr_add(ctx, t0, cpu_gpr[base]); | |
93b12ccc | 7229 | } |
5a5012ec | 7230 | /* Don't do NOP if destination is zero: we must perform the actual |
ead9360e | 7231 | memory access. */ |
4e2474d6 | 7232 | save_cpu_state(ctx, 0); |
5a5012ec TS |
7233 | switch (opc) { |
7234 | case OPC_LWXC1: | |
8c0ab41f | 7235 | check_cop1x(ctx); |
b6d96bed | 7236 | { |
a7812ae4 | 7237 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
b6d96bed | 7238 | |
585c88d5 AJ |
7239 | tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); |
7240 | tcg_gen_trunc_tl_i32(fp0, t0); | |
b6d96bed | 7241 | gen_store_fpr32(fp0, fd); |
a7812ae4 | 7242 | tcg_temp_free_i32(fp0); |
b6d96bed | 7243 | } |
5a5012ec TS |
7244 | opn = "lwxc1"; |
7245 | break; | |
7246 | case OPC_LDXC1: | |
8c0ab41f AJ |
7247 | check_cop1x(ctx); |
7248 | check_cp1_registers(ctx, fd); | |
b6d96bed | 7249 | { |
a7812ae4 | 7250 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
7251 | |
7252 | tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); | |
7253 | gen_store_fpr64(ctx, fp0, fd); | |
a7812ae4 | 7254 | tcg_temp_free_i64(fp0); |
b6d96bed | 7255 | } |
5a5012ec TS |
7256 | opn = "ldxc1"; |
7257 | break; | |
7258 | case OPC_LUXC1: | |
8c0ab41f | 7259 | check_cp1_64bitmode(ctx); |
6c5c1e20 | 7260 | tcg_gen_andi_tl(t0, t0, ~0x7); |
b6d96bed | 7261 | { |
a7812ae4 | 7262 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
7263 | |
7264 | tcg_gen_qemu_ld64(fp0, t0, ctx->mem_idx); | |
7265 | gen_store_fpr64(ctx, fp0, fd); | |
a7812ae4 | 7266 | tcg_temp_free_i64(fp0); |
b6d96bed | 7267 | } |
5a5012ec TS |
7268 | opn = "luxc1"; |
7269 | break; | |
7270 | case OPC_SWXC1: | |
8c0ab41f | 7271 | check_cop1x(ctx); |
b6d96bed | 7272 | { |
a7812ae4 | 7273 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
585c88d5 | 7274 | TCGv t1 = tcg_temp_new(); |
b6d96bed TS |
7275 | |
7276 | gen_load_fpr32(fp0, fs); | |
a7812ae4 PB |
7277 | tcg_gen_extu_i32_tl(t1, fp0); |
7278 | tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); | |
7279 | tcg_temp_free_i32(fp0); | |
a6035857 | 7280 | tcg_temp_free(t1); |
b6d96bed | 7281 | } |
5a5012ec | 7282 | opn = "swxc1"; |
93b12ccc | 7283 | store = 1; |
5a5012ec TS |
7284 | break; |
7285 | case OPC_SDXC1: | |
8c0ab41f AJ |
7286 | check_cop1x(ctx); |
7287 | check_cp1_registers(ctx, fs); | |
b6d96bed | 7288 | { |
a7812ae4 | 7289 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
7290 | |
7291 | gen_load_fpr64(ctx, fp0, fs); | |
7292 | tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); | |
a7812ae4 | 7293 | tcg_temp_free_i64(fp0); |
b6d96bed | 7294 | } |
5a5012ec | 7295 | opn = "sdxc1"; |
93b12ccc | 7296 | store = 1; |
5a5012ec TS |
7297 | break; |
7298 | case OPC_SUXC1: | |
8c0ab41f | 7299 | check_cp1_64bitmode(ctx); |
6c5c1e20 | 7300 | tcg_gen_andi_tl(t0, t0, ~0x7); |
b6d96bed | 7301 | { |
a7812ae4 | 7302 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
b6d96bed TS |
7303 | |
7304 | gen_load_fpr64(ctx, fp0, fs); | |
7305 | tcg_gen_qemu_st64(fp0, t0, ctx->mem_idx); | |
a7812ae4 | 7306 | tcg_temp_free_i64(fp0); |
b6d96bed | 7307 | } |
5a5012ec | 7308 | opn = "suxc1"; |
93b12ccc | 7309 | store = 1; |
5a5012ec | 7310 | break; |
5a5012ec | 7311 | } |
6c5c1e20 | 7312 | tcg_temp_free(t0); |
93b12ccc TS |
7313 | MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd], |
7314 | regnames[index], regnames[base]); | |
5a5012ec TS |
7315 | } |
7316 | ||
5e755519 TS |
7317 | static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, |
7318 | int fd, int fr, int fs, int ft) | |
5a5012ec | 7319 | { |
923617a3 | 7320 | const char *opn = "flt3_arith"; |
5a5012ec | 7321 | |
5a5012ec TS |
7322 | switch (opc) { |
7323 | case OPC_ALNV_PS: | |
b8aa4598 | 7324 | check_cp1_64bitmode(ctx); |
a16336e4 | 7325 | { |
a7812ae4 | 7326 | TCGv t0 = tcg_temp_local_new(); |
c905fdac AJ |
7327 | TCGv_i32 fp = tcg_temp_new_i32(); |
7328 | TCGv_i32 fph = tcg_temp_new_i32(); | |
a16336e4 TS |
7329 | int l1 = gen_new_label(); |
7330 | int l2 = gen_new_label(); | |
7331 | ||
6c5c1e20 TS |
7332 | gen_load_gpr(t0, fr); |
7333 | tcg_gen_andi_tl(t0, t0, 0x7); | |
6c5c1e20 TS |
7334 | |
7335 | tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); | |
c905fdac AJ |
7336 | gen_load_fpr32(fp, fs); |
7337 | gen_load_fpr32h(fph, fs); | |
7338 | gen_store_fpr32(fp, fd); | |
7339 | gen_store_fpr32h(fph, fd); | |
a16336e4 TS |
7340 | tcg_gen_br(l2); |
7341 | gen_set_label(l1); | |
6c5c1e20 TS |
7342 | tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); |
7343 | tcg_temp_free(t0); | |
a16336e4 | 7344 | #ifdef TARGET_WORDS_BIGENDIAN |
c905fdac AJ |
7345 | gen_load_fpr32(fp, fs); |
7346 | gen_load_fpr32h(fph, ft); | |
7347 | gen_store_fpr32h(fp, fd); | |
7348 | gen_store_fpr32(fph, fd); | |
a16336e4 | 7349 | #else |
c905fdac AJ |
7350 | gen_load_fpr32h(fph, fs); |
7351 | gen_load_fpr32(fp, ft); | |
7352 | gen_store_fpr32(fph, fd); | |
7353 | gen_store_fpr32h(fp, fd); | |
a16336e4 TS |
7354 | #endif |
7355 | gen_set_label(l2); | |
c905fdac AJ |
7356 | tcg_temp_free_i32(fp); |
7357 | tcg_temp_free_i32(fph); | |
a16336e4 | 7358 | } |
5a5012ec TS |
7359 | opn = "alnv.ps"; |
7360 | break; | |
7361 | case OPC_MADD_S: | |
b8aa4598 | 7362 | check_cop1x(ctx); |
b6d96bed | 7363 | { |
a7812ae4 PB |
7364 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
7365 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
7366 | TCGv_i32 fp2 = tcg_temp_new_i32(); | |
b6d96bed TS |
7367 | |
7368 | gen_load_fpr32(fp0, fs); | |
7369 | gen_load_fpr32(fp1, ft); | |
7370 | gen_load_fpr32(fp2, fr); | |
a7812ae4 PB |
7371 | gen_helper_float_muladd_s(fp2, fp0, fp1, fp2); |
7372 | tcg_temp_free_i32(fp0); | |
7373 | tcg_temp_free_i32(fp1); | |
b6d96bed | 7374 | gen_store_fpr32(fp2, fd); |
a7812ae4 | 7375 | tcg_temp_free_i32(fp2); |
b6d96bed | 7376 | } |
5a5012ec TS |
7377 | opn = "madd.s"; |
7378 | break; | |
7379 | case OPC_MADD_D: | |
b8aa4598 TS |
7380 | check_cop1x(ctx); |
7381 | check_cp1_registers(ctx, fd | fs | ft | fr); | |
b6d96bed | 7382 | { |
a7812ae4 PB |
7383 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7384 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
7385 | TCGv_i64 fp2 = tcg_temp_new_i64(); | |
b6d96bed TS |
7386 | |
7387 | gen_load_fpr64(ctx, fp0, fs); | |
7388 | gen_load_fpr64(ctx, fp1, ft); | |
7389 | gen_load_fpr64(ctx, fp2, fr); | |
a7812ae4 PB |
7390 | gen_helper_float_muladd_d(fp2, fp0, fp1, fp2); |
7391 | tcg_temp_free_i64(fp0); | |
7392 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7393 | gen_store_fpr64(ctx, fp2, fd); |
a7812ae4 | 7394 | tcg_temp_free_i64(fp2); |
b6d96bed | 7395 | } |
5a5012ec TS |
7396 | opn = "madd.d"; |
7397 | break; | |
7398 | case OPC_MADD_PS: | |
b8aa4598 | 7399 | check_cp1_64bitmode(ctx); |
b6d96bed | 7400 | { |
a7812ae4 PB |
7401 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7402 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
7403 | TCGv_i64 fp2 = tcg_temp_new_i64(); | |
b6d96bed TS |
7404 | |
7405 | gen_load_fpr64(ctx, fp0, fs); | |
7406 | gen_load_fpr64(ctx, fp1, ft); | |
7407 | gen_load_fpr64(ctx, fp2, fr); | |
a7812ae4 PB |
7408 | gen_helper_float_muladd_ps(fp2, fp0, fp1, fp2); |
7409 | tcg_temp_free_i64(fp0); | |
7410 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7411 | gen_store_fpr64(ctx, fp2, fd); |
a7812ae4 | 7412 | tcg_temp_free_i64(fp2); |
b6d96bed | 7413 | } |
5a5012ec TS |
7414 | opn = "madd.ps"; |
7415 | break; | |
7416 | case OPC_MSUB_S: | |
b8aa4598 | 7417 | check_cop1x(ctx); |
b6d96bed | 7418 | { |
a7812ae4 PB |
7419 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
7420 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
7421 | TCGv_i32 fp2 = tcg_temp_new_i32(); | |
b6d96bed TS |
7422 | |
7423 | gen_load_fpr32(fp0, fs); | |
7424 | gen_load_fpr32(fp1, ft); | |
7425 | gen_load_fpr32(fp2, fr); | |
a7812ae4 PB |
7426 | gen_helper_float_mulsub_s(fp2, fp0, fp1, fp2); |
7427 | tcg_temp_free_i32(fp0); | |
7428 | tcg_temp_free_i32(fp1); | |
b6d96bed | 7429 | gen_store_fpr32(fp2, fd); |
a7812ae4 | 7430 | tcg_temp_free_i32(fp2); |
b6d96bed | 7431 | } |
5a5012ec TS |
7432 | opn = "msub.s"; |
7433 | break; | |
7434 | case OPC_MSUB_D: | |
b8aa4598 TS |
7435 | check_cop1x(ctx); |
7436 | check_cp1_registers(ctx, fd | fs | ft | fr); | |
b6d96bed | 7437 | { |
a7812ae4 PB |
7438 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7439 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
7440 | TCGv_i64 fp2 = tcg_temp_new_i64(); | |
b6d96bed TS |
7441 | |
7442 | gen_load_fpr64(ctx, fp0, fs); | |
7443 | gen_load_fpr64(ctx, fp1, ft); | |
7444 | gen_load_fpr64(ctx, fp2, fr); | |
a7812ae4 PB |
7445 | gen_helper_float_mulsub_d(fp2, fp0, fp1, fp2); |
7446 | tcg_temp_free_i64(fp0); | |
7447 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7448 | gen_store_fpr64(ctx, fp2, fd); |
a7812ae4 | 7449 | tcg_temp_free_i64(fp2); |
b6d96bed | 7450 | } |
5a5012ec TS |
7451 | opn = "msub.d"; |
7452 | break; | |
7453 | case OPC_MSUB_PS: | |
b8aa4598 | 7454 | check_cp1_64bitmode(ctx); |
b6d96bed | 7455 | { |
a7812ae4 PB |
7456 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7457 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
7458 | TCGv_i64 fp2 = tcg_temp_new_i64(); | |
b6d96bed TS |
7459 | |
7460 | gen_load_fpr64(ctx, fp0, fs); | |
7461 | gen_load_fpr64(ctx, fp1, ft); | |
7462 | gen_load_fpr64(ctx, fp2, fr); | |
a7812ae4 PB |
7463 | gen_helper_float_mulsub_ps(fp2, fp0, fp1, fp2); |
7464 | tcg_temp_free_i64(fp0); | |
7465 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7466 | gen_store_fpr64(ctx, fp2, fd); |
a7812ae4 | 7467 | tcg_temp_free_i64(fp2); |
b6d96bed | 7468 | } |
5a5012ec TS |
7469 | opn = "msub.ps"; |
7470 | break; | |
7471 | case OPC_NMADD_S: | |
b8aa4598 | 7472 | check_cop1x(ctx); |
b6d96bed | 7473 | { |
a7812ae4 PB |
7474 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
7475 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
7476 | TCGv_i32 fp2 = tcg_temp_new_i32(); | |
b6d96bed TS |
7477 | |
7478 | gen_load_fpr32(fp0, fs); | |
7479 | gen_load_fpr32(fp1, ft); | |
7480 | gen_load_fpr32(fp2, fr); | |
a7812ae4 PB |
7481 | gen_helper_float_nmuladd_s(fp2, fp0, fp1, fp2); |
7482 | tcg_temp_free_i32(fp0); | |
7483 | tcg_temp_free_i32(fp1); | |
b6d96bed | 7484 | gen_store_fpr32(fp2, fd); |
a7812ae4 | 7485 | tcg_temp_free_i32(fp2); |
b6d96bed | 7486 | } |
5a5012ec TS |
7487 | opn = "nmadd.s"; |
7488 | break; | |
7489 | case OPC_NMADD_D: | |
b8aa4598 TS |
7490 | check_cop1x(ctx); |
7491 | check_cp1_registers(ctx, fd | fs | ft | fr); | |
b6d96bed | 7492 | { |
a7812ae4 PB |
7493 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7494 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
7495 | TCGv_i64 fp2 = tcg_temp_new_i64(); | |
b6d96bed TS |
7496 | |
7497 | gen_load_fpr64(ctx, fp0, fs); | |
7498 | gen_load_fpr64(ctx, fp1, ft); | |
7499 | gen_load_fpr64(ctx, fp2, fr); | |
a7812ae4 PB |
7500 | gen_helper_float_nmuladd_d(fp2, fp0, fp1, fp2); |
7501 | tcg_temp_free_i64(fp0); | |
7502 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7503 | gen_store_fpr64(ctx, fp2, fd); |
a7812ae4 | 7504 | tcg_temp_free_i64(fp2); |
b6d96bed | 7505 | } |
5a5012ec TS |
7506 | opn = "nmadd.d"; |
7507 | break; | |
7508 | case OPC_NMADD_PS: | |
b8aa4598 | 7509 | check_cp1_64bitmode(ctx); |
b6d96bed | 7510 | { |
a7812ae4 PB |
7511 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7512 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
7513 | TCGv_i64 fp2 = tcg_temp_new_i64(); | |
b6d96bed TS |
7514 | |
7515 | gen_load_fpr64(ctx, fp0, fs); | |
7516 | gen_load_fpr64(ctx, fp1, ft); | |
7517 | gen_load_fpr64(ctx, fp2, fr); | |
a7812ae4 PB |
7518 | gen_helper_float_nmuladd_ps(fp2, fp0, fp1, fp2); |
7519 | tcg_temp_free_i64(fp0); | |
7520 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7521 | gen_store_fpr64(ctx, fp2, fd); |
a7812ae4 | 7522 | tcg_temp_free_i64(fp2); |
b6d96bed | 7523 | } |
5a5012ec TS |
7524 | opn = "nmadd.ps"; |
7525 | break; | |
7526 | case OPC_NMSUB_S: | |
b8aa4598 | 7527 | check_cop1x(ctx); |
b6d96bed | 7528 | { |
a7812ae4 PB |
7529 | TCGv_i32 fp0 = tcg_temp_new_i32(); |
7530 | TCGv_i32 fp1 = tcg_temp_new_i32(); | |
7531 | TCGv_i32 fp2 = tcg_temp_new_i32(); | |
b6d96bed TS |
7532 | |
7533 | gen_load_fpr32(fp0, fs); | |
7534 | gen_load_fpr32(fp1, ft); | |
7535 | gen_load_fpr32(fp2, fr); | |
a7812ae4 PB |
7536 | gen_helper_float_nmulsub_s(fp2, fp0, fp1, fp2); |
7537 | tcg_temp_free_i32(fp0); | |
7538 | tcg_temp_free_i32(fp1); | |
b6d96bed | 7539 | gen_store_fpr32(fp2, fd); |
a7812ae4 | 7540 | tcg_temp_free_i32(fp2); |
b6d96bed | 7541 | } |
5a5012ec TS |
7542 | opn = "nmsub.s"; |
7543 | break; | |
7544 | case OPC_NMSUB_D: | |
b8aa4598 TS |
7545 | check_cop1x(ctx); |
7546 | check_cp1_registers(ctx, fd | fs | ft | fr); | |
b6d96bed | 7547 | { |
a7812ae4 PB |
7548 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7549 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
7550 | TCGv_i64 fp2 = tcg_temp_new_i64(); | |
b6d96bed TS |
7551 | |
7552 | gen_load_fpr64(ctx, fp0, fs); | |
7553 | gen_load_fpr64(ctx, fp1, ft); | |
7554 | gen_load_fpr64(ctx, fp2, fr); | |
a7812ae4 PB |
7555 | gen_helper_float_nmulsub_d(fp2, fp0, fp1, fp2); |
7556 | tcg_temp_free_i64(fp0); | |
7557 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7558 | gen_store_fpr64(ctx, fp2, fd); |
a7812ae4 | 7559 | tcg_temp_free_i64(fp2); |
b6d96bed | 7560 | } |
5a5012ec TS |
7561 | opn = "nmsub.d"; |
7562 | break; | |
7563 | case OPC_NMSUB_PS: | |
b8aa4598 | 7564 | check_cp1_64bitmode(ctx); |
b6d96bed | 7565 | { |
a7812ae4 PB |
7566 | TCGv_i64 fp0 = tcg_temp_new_i64(); |
7567 | TCGv_i64 fp1 = tcg_temp_new_i64(); | |
7568 | TCGv_i64 fp2 = tcg_temp_new_i64(); | |
b6d96bed TS |
7569 | |
7570 | gen_load_fpr64(ctx, fp0, fs); | |
7571 | gen_load_fpr64(ctx, fp1, ft); | |
7572 | gen_load_fpr64(ctx, fp2, fr); | |
a7812ae4 PB |
7573 | gen_helper_float_nmulsub_ps(fp2, fp0, fp1, fp2); |
7574 | tcg_temp_free_i64(fp0); | |
7575 | tcg_temp_free_i64(fp1); | |
b6d96bed | 7576 | gen_store_fpr64(ctx, fp2, fd); |
a7812ae4 | 7577 | tcg_temp_free_i64(fp2); |
b6d96bed | 7578 | } |
5a5012ec TS |
7579 | opn = "nmsub.ps"; |
7580 | break; | |
923617a3 TS |
7581 | default: |
7582 | MIPS_INVAL(opn); | |
5a5012ec TS |
7583 | generate_exception (ctx, EXCP_RI); |
7584 | return; | |
7585 | } | |
7586 | MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr], | |
7587 | fregnames[fs], fregnames[ft]); | |
7a387fff TS |
7588 | } |
7589 | ||
7590 | /* ISA extensions (ASEs) */ | |
6af0bf9c FB |
7591 | /* MIPS16 extension to MIPS32 */ |
7592 | /* SmartMIPS extension to MIPS32 */ | |
7593 | ||
d26bc211 | 7594 | #if defined(TARGET_MIPS64) |
6af0bf9c FB |
7595 | |
7596 | /* MDMX extension to MIPS64 */ | |
6af0bf9c FB |
7597 | |
7598 | #endif | |
7599 | ||
36d23958 | 7600 | static void decode_opc (CPUState *env, DisasContext *ctx) |
6af0bf9c FB |
7601 | { |
7602 | int32_t offset; | |
7603 | int rs, rt, rd, sa; | |
7a387fff | 7604 | uint32_t op, op1, op2; |
6af0bf9c FB |
7605 | int16_t imm; |
7606 | ||
d796321b FB |
7607 | /* make sure instructions are on a word boundary */ |
7608 | if (ctx->pc & 0x3) { | |
cbeb0857 | 7609 | env->CP0_BadVAddr = ctx->pc; |
d796321b FB |
7610 | generate_exception(ctx, EXCP_AdEL); |
7611 | return; | |
7612 | } | |
7613 | ||
8e9ade68 | 7614 | /* Handle blikely not taken case */ |
4ad40f36 | 7615 | if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) { |
8e9ade68 TS |
7616 | int l1 = gen_new_label(); |
7617 | ||
3594c774 | 7618 | MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4); |
1ba74fb8 | 7619 | tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); |
41db4607 | 7620 | tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); |
5a5012ec TS |
7621 | gen_goto_tb(ctx, 1, ctx->pc + 4); |
7622 | gen_set_label(l1); | |
6af0bf9c | 7623 | } |
7a387fff TS |
7624 | op = MASK_OP_MAJOR(ctx->opcode); |
7625 | rs = (ctx->opcode >> 21) & 0x1f; | |
7626 | rt = (ctx->opcode >> 16) & 0x1f; | |
7627 | rd = (ctx->opcode >> 11) & 0x1f; | |
7628 | sa = (ctx->opcode >> 6) & 0x1f; | |
6af0bf9c FB |
7629 | imm = (int16_t)ctx->opcode; |
7630 | switch (op) { | |
7a387fff TS |
7631 | case OPC_SPECIAL: |
7632 | op1 = MASK_SPECIAL(ctx->opcode); | |
6af0bf9c | 7633 | switch (op1) { |
324d9e32 AJ |
7634 | case OPC_SLL: /* Shift with immediate */ |
7635 | case OPC_SRA: | |
7636 | case OPC_SRL: | |
7637 | gen_shift_imm(env, ctx, op1, rd, rt, sa); | |
7a387fff | 7638 | break; |
460f00c4 AJ |
7639 | case OPC_MOVN: /* Conditional move */ |
7640 | case OPC_MOVZ: | |
e189e748 | 7641 | check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); |
460f00c4 AJ |
7642 | gen_cond_move(env, op1, rd, rs, rt); |
7643 | break; | |
7644 | case OPC_ADD ... OPC_SUBU: | |
e189e748 | 7645 | gen_arith(env, ctx, op1, rd, rs, rt); |
7a387fff | 7646 | break; |
460f00c4 AJ |
7647 | case OPC_SLLV: /* Shifts */ |
7648 | case OPC_SRLV: | |
7649 | case OPC_SRAV: | |
7650 | gen_shift(env, ctx, op1, rd, rs, rt); | |
7651 | break; | |
7652 | case OPC_SLT: /* Set on less than */ | |
7653 | case OPC_SLTU: | |
7654 | gen_slt(env, op1, rd, rs, rt); | |
7655 | break; | |
7656 | case OPC_AND: /* Logic*/ | |
7657 | case OPC_OR: | |
7658 | case OPC_NOR: | |
7659 | case OPC_XOR: | |
7660 | gen_logic(env, op1, rd, rs, rt); | |
7661 | break; | |
7a387fff | 7662 | case OPC_MULT ... OPC_DIVU: |
e9c71dd1 TS |
7663 | if (sa) { |
7664 | check_insn(env, ctx, INSN_VR54XX); | |
7665 | op1 = MASK_MUL_VR54XX(ctx->opcode); | |
7666 | gen_mul_vr54xx(ctx, op1, rd, rs, rt); | |
7667 | } else | |
7668 | gen_muldiv(ctx, op1, rs, rt); | |
7a387fff TS |
7669 | break; |
7670 | case OPC_JR ... OPC_JALR: | |
7671 | gen_compute_branch(ctx, op1, rs, rd, sa); | |
6af0bf9c | 7672 | return; |
7a387fff TS |
7673 | case OPC_TGE ... OPC_TEQ: /* Traps */ |
7674 | case OPC_TNE: | |
7675 | gen_trap(ctx, op1, rs, rt, -1); | |
6af0bf9c | 7676 | break; |
7a387fff TS |
7677 | case OPC_MFHI: /* Move from HI/LO */ |
7678 | case OPC_MFLO: | |
7679 | gen_HILO(ctx, op1, rd); | |
6af0bf9c | 7680 | break; |
7a387fff TS |
7681 | case OPC_MTHI: |
7682 | case OPC_MTLO: /* Move to HI/LO */ | |
7683 | gen_HILO(ctx, op1, rs); | |
6af0bf9c | 7684 | break; |
b48cfdff TS |
7685 | case OPC_PMON: /* Pmon entry point, also R4010 selsl */ |
7686 | #ifdef MIPS_STRICT_STANDARD | |
7687 | MIPS_INVAL("PMON / selsl"); | |
7688 | generate_exception(ctx, EXCP_RI); | |
7689 | #else | |
a7812ae4 | 7690 | gen_helper_0i(pmon, sa); |
b48cfdff | 7691 | #endif |
7a387fff TS |
7692 | break; |
7693 | case OPC_SYSCALL: | |
6af0bf9c | 7694 | generate_exception(ctx, EXCP_SYSCALL); |
8e0f950d | 7695 | ctx->bstate = BS_STOP; |
6af0bf9c | 7696 | break; |
7a387fff | 7697 | case OPC_BREAK: |
6af0bf9c FB |
7698 | generate_exception(ctx, EXCP_BREAK); |
7699 | break; | |
b48cfdff TS |
7700 | case OPC_SPIM: |
7701 | #ifdef MIPS_STRICT_STANDARD | |
7702 | MIPS_INVAL("SPIM"); | |
7703 | generate_exception(ctx, EXCP_RI); | |
7704 | #else | |
7a387fff TS |
7705 | /* Implemented as RI exception for now. */ |
7706 | MIPS_INVAL("spim (unofficial)"); | |
7707 | generate_exception(ctx, EXCP_RI); | |
b48cfdff | 7708 | #endif |
6af0bf9c | 7709 | break; |
7a387fff | 7710 | case OPC_SYNC: |
ead9360e | 7711 | /* Treat as NOP. */ |
6af0bf9c | 7712 | break; |
4ad40f36 | 7713 | |
7a387fff | 7714 | case OPC_MOVCI: |
e189e748 | 7715 | check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); |
36d23958 | 7716 | if (env->CP0_Config1 & (1 << CP0C1_FP)) { |
5e755519 | 7717 | check_cp1_enabled(ctx); |
36d23958 TS |
7718 | gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, |
7719 | (ctx->opcode >> 16) & 1); | |
7720 | } else { | |
e397ee33 | 7721 | generate_exception_err(ctx, EXCP_CpU, 1); |
36d23958 | 7722 | } |
4ad40f36 FB |
7723 | break; |
7724 | ||
d26bc211 | 7725 | #if defined(TARGET_MIPS64) |
7a387fff TS |
7726 | /* MIPS64 specific opcodes */ |
7727 | case OPC_DSLL: | |
324d9e32 AJ |
7728 | case OPC_DSRA: |
7729 | case OPC_DSRL: | |
7a387fff | 7730 | case OPC_DSLL32: |
324d9e32 AJ |
7731 | case OPC_DSRA32: |
7732 | case OPC_DSRL32: | |
e189e748 TS |
7733 | check_insn(env, ctx, ISA_MIPS3); |
7734 | check_mips_64(ctx); | |
324d9e32 | 7735 | gen_shift_imm(env, ctx, op1, rd, rt, sa); |
7a387fff | 7736 | break; |
7a387fff | 7737 | case OPC_DADD ... OPC_DSUBU: |
e189e748 TS |
7738 | check_insn(env, ctx, ISA_MIPS3); |
7739 | check_mips_64(ctx); | |
7740 | gen_arith(env, ctx, op1, rd, rs, rt); | |
7a387fff | 7741 | break; |
460f00c4 AJ |
7742 | case OPC_DSLLV: |
7743 | case OPC_DSRAV: | |
7744 | case OPC_DSRLV: | |
7745 | check_insn(env, ctx, ISA_MIPS3); | |
7746 | check_mips_64(ctx); | |
7747 | gen_shift(env, ctx, op1, rd, rs, rt); | |
7748 | break; | |
7a387fff | 7749 | case OPC_DMULT ... OPC_DDIVU: |
e189e748 TS |
7750 | check_insn(env, ctx, ISA_MIPS3); |
7751 | check_mips_64(ctx); | |
7a387fff TS |
7752 | gen_muldiv(ctx, op1, rs, rt); |
7753 | break; | |
6af0bf9c FB |
7754 | #endif |
7755 | default: /* Invalid */ | |
7756 | MIPS_INVAL("special"); | |
7757 | generate_exception(ctx, EXCP_RI); | |
7758 | break; | |
7759 | } | |
7760 | break; | |
7a387fff TS |
7761 | case OPC_SPECIAL2: |
7762 | op1 = MASK_SPECIAL2(ctx->opcode); | |
6af0bf9c | 7763 | switch (op1) { |
7a387fff TS |
7764 | case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */ |
7765 | case OPC_MSUB ... OPC_MSUBU: | |
e189e748 | 7766 | check_insn(env, ctx, ISA_MIPS32); |
7a387fff | 7767 | gen_muldiv(ctx, op1, rs, rt); |
6af0bf9c | 7768 | break; |
7a387fff | 7769 | case OPC_MUL: |
e189e748 | 7770 | gen_arith(env, ctx, op1, rd, rs, rt); |
6af0bf9c | 7771 | break; |
20e1fb52 AJ |
7772 | case OPC_CLO: |
7773 | case OPC_CLZ: | |
e189e748 | 7774 | check_insn(env, ctx, ISA_MIPS32); |
7a387fff | 7775 | gen_cl(ctx, op1, rd, rs); |
6af0bf9c | 7776 | break; |
7a387fff | 7777 | case OPC_SDBBP: |
6af0bf9c FB |
7778 | /* XXX: not clear which exception should be raised |
7779 | * when in debug mode... | |
7780 | */ | |
e189e748 | 7781 | check_insn(env, ctx, ISA_MIPS32); |
6af0bf9c FB |
7782 | if (!(ctx->hflags & MIPS_HFLAG_DM)) { |
7783 | generate_exception(ctx, EXCP_DBp); | |
7784 | } else { | |
7785 | generate_exception(ctx, EXCP_DBp); | |
7786 | } | |
ead9360e | 7787 | /* Treat as NOP. */ |
6af0bf9c | 7788 | break; |
d26bc211 | 7789 | #if defined(TARGET_MIPS64) |
20e1fb52 AJ |
7790 | case OPC_DCLO: |
7791 | case OPC_DCLZ: | |
e189e748 TS |
7792 | check_insn(env, ctx, ISA_MIPS64); |
7793 | check_mips_64(ctx); | |
7a387fff TS |
7794 | gen_cl(ctx, op1, rd, rs); |
7795 | break; | |
7796 | #endif | |
6af0bf9c FB |
7797 | default: /* Invalid */ |
7798 | MIPS_INVAL("special2"); | |
7799 | generate_exception(ctx, EXCP_RI); | |
7800 | break; | |
7801 | } | |
7802 | break; | |
7a387fff | 7803 | case OPC_SPECIAL3: |
2b0233ab TS |
7804 | op1 = MASK_SPECIAL3(ctx->opcode); |
7805 | switch (op1) { | |
7806 | case OPC_EXT: | |
7807 | case OPC_INS: | |
7808 | check_insn(env, ctx, ISA_MIPS32R2); | |
7809 | gen_bitops(ctx, op1, rt, rs, sa, rd); | |
7810 | break; | |
7811 | case OPC_BSHFL: | |
7812 | check_insn(env, ctx, ISA_MIPS32R2); | |
7813 | op2 = MASK_BSHFL(ctx->opcode); | |
49bcf33c | 7814 | gen_bshfl(ctx, op2, rt, rd); |
7a387fff | 7815 | break; |
1579a72e | 7816 | case OPC_RDHWR: |
e189e748 | 7817 | check_insn(env, ctx, ISA_MIPS32R2); |
6c5c1e20 | 7818 | { |
35fbce2c | 7819 | TCGv t0 = tcg_temp_new(); |
6c5c1e20 TS |
7820 | |
7821 | switch (rd) { | |
7822 | case 0: | |
7823 | save_cpu_state(ctx, 1); | |
a7812ae4 | 7824 | gen_helper_rdhwr_cpunum(t0); |
35fbce2c | 7825 | gen_store_gpr(t0, rt); |
6c5c1e20 TS |
7826 | break; |
7827 | case 1: | |
7828 | save_cpu_state(ctx, 1); | |
a7812ae4 | 7829 | gen_helper_rdhwr_synci_step(t0); |
35fbce2c | 7830 | gen_store_gpr(t0, rt); |
6c5c1e20 TS |
7831 | break; |
7832 | case 2: | |
7833 | save_cpu_state(ctx, 1); | |
a7812ae4 | 7834 | gen_helper_rdhwr_cc(t0); |
35fbce2c | 7835 | gen_store_gpr(t0, rt); |
6c5c1e20 TS |
7836 | break; |
7837 | case 3: | |
7838 | save_cpu_state(ctx, 1); | |
a7812ae4 | 7839 | gen_helper_rdhwr_ccres(t0); |
35fbce2c | 7840 | gen_store_gpr(t0, rt); |
6c5c1e20 TS |
7841 | break; |
7842 | case 29: | |
932e71cd AJ |
7843 | #if defined(CONFIG_USER_ONLY) |
7844 | tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value)); | |
35fbce2c | 7845 | gen_store_gpr(t0, rt); |
932e71cd AJ |
7846 | break; |
7847 | #else | |
7848 | /* XXX: Some CPUs implement this in hardware. | |
7849 | Not supported yet. */ | |
7850 | #endif | |
6c5c1e20 TS |
7851 | default: /* Invalid */ |
7852 | MIPS_INVAL("rdhwr"); | |
7853 | generate_exception(ctx, EXCP_RI); | |
7854 | break; | |
7855 | } | |
6c5c1e20 | 7856 | tcg_temp_free(t0); |
1579a72e | 7857 | } |
1579a72e | 7858 | break; |
ead9360e | 7859 | case OPC_FORK: |
7385ac0b | 7860 | check_insn(env, ctx, ASE_MT); |
6c5c1e20 | 7861 | { |
35fbce2c AJ |
7862 | TCGv t0 = tcg_temp_new(); |
7863 | TCGv t1 = tcg_temp_new(); | |
6c5c1e20 TS |
7864 | |
7865 | gen_load_gpr(t0, rt); | |
7866 | gen_load_gpr(t1, rs); | |
a7812ae4 | 7867 | gen_helper_fork(t0, t1); |
6c5c1e20 TS |
7868 | tcg_temp_free(t0); |
7869 | tcg_temp_free(t1); | |
7870 | } | |
ead9360e TS |
7871 | break; |
7872 | case OPC_YIELD: | |
7385ac0b | 7873 | check_insn(env, ctx, ASE_MT); |
6c5c1e20 | 7874 | { |
35fbce2c | 7875 | TCGv t0 = tcg_temp_new(); |
6c5c1e20 | 7876 | |
35fbce2c | 7877 | save_cpu_state(ctx, 1); |
6c5c1e20 | 7878 | gen_load_gpr(t0, rs); |
a7812ae4 | 7879 | gen_helper_yield(t0, t0); |
6c5c1e20 TS |
7880 | gen_store_gpr(t0, rd); |
7881 | tcg_temp_free(t0); | |
7882 | } | |
ead9360e | 7883 | break; |
d26bc211 | 7884 | #if defined(TARGET_MIPS64) |
1579a72e TS |
7885 | case OPC_DEXTM ... OPC_DEXT: |
7886 | case OPC_DINSM ... OPC_DINS: | |
e189e748 TS |
7887 | check_insn(env, ctx, ISA_MIPS64R2); |
7888 | check_mips_64(ctx); | |
1579a72e | 7889 | gen_bitops(ctx, op1, rt, rs, sa, rd); |
7a387fff | 7890 | break; |
1579a72e | 7891 | case OPC_DBSHFL: |
e189e748 TS |
7892 | check_insn(env, ctx, ISA_MIPS64R2); |
7893 | check_mips_64(ctx); | |
1579a72e | 7894 | op2 = MASK_DBSHFL(ctx->opcode); |
49bcf33c | 7895 | gen_bshfl(ctx, op2, rt, rd); |
c6d6dd7c | 7896 | break; |
7a387fff TS |
7897 | #endif |
7898 | default: /* Invalid */ | |
7899 | MIPS_INVAL("special3"); | |
7900 | generate_exception(ctx, EXCP_RI); | |
7901 | break; | |
7902 | } | |
7903 | break; | |
7904 | case OPC_REGIMM: | |
7905 | op1 = MASK_REGIMM(ctx->opcode); | |
7906 | switch (op1) { | |
7907 | case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */ | |
7908 | case OPC_BLTZAL ... OPC_BGEZALL: | |
7909 | gen_compute_branch(ctx, op1, rs, -1, imm << 2); | |
6af0bf9c | 7910 | return; |
7a387fff TS |
7911 | case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */ |
7912 | case OPC_TNEI: | |
7913 | gen_trap(ctx, op1, rs, -1, imm); | |
7914 | break; | |
7915 | case OPC_SYNCI: | |
e189e748 | 7916 | check_insn(env, ctx, ISA_MIPS32R2); |
ead9360e | 7917 | /* Treat as NOP. */ |
6af0bf9c FB |
7918 | break; |
7919 | default: /* Invalid */ | |
923617a3 | 7920 | MIPS_INVAL("regimm"); |
6af0bf9c FB |
7921 | generate_exception(ctx, EXCP_RI); |
7922 | break; | |
7923 | } | |
7924 | break; | |
7a387fff | 7925 | case OPC_CP0: |
387a8fe5 | 7926 | check_cp0_enabled(ctx); |
7a387fff | 7927 | op1 = MASK_CP0(ctx->opcode); |
6af0bf9c | 7928 | switch (op1) { |
7a387fff TS |
7929 | case OPC_MFC0: |
7930 | case OPC_MTC0: | |
ead9360e TS |
7931 | case OPC_MFTR: |
7932 | case OPC_MTTR: | |
d26bc211 | 7933 | #if defined(TARGET_MIPS64) |
7a387fff TS |
7934 | case OPC_DMFC0: |
7935 | case OPC_DMTC0: | |
7936 | #endif | |
f1aa6320 | 7937 | #ifndef CONFIG_USER_ONLY |
932e71cd | 7938 | gen_cp0(env, ctx, op1, rt, rd); |
0eaef5aa | 7939 | #endif /* !CONFIG_USER_ONLY */ |
7a387fff TS |
7940 | break; |
7941 | case OPC_C0_FIRST ... OPC_C0_LAST: | |
f1aa6320 | 7942 | #ifndef CONFIG_USER_ONLY |
932e71cd | 7943 | gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); |
0eaef5aa | 7944 | #endif /* !CONFIG_USER_ONLY */ |
7a387fff TS |
7945 | break; |
7946 | case OPC_MFMC0: | |
8706c382 | 7947 | #ifndef CONFIG_USER_ONLY |
932e71cd | 7948 | { |
35fbce2c | 7949 | TCGv t0 = tcg_temp_new(); |
6c5c1e20 | 7950 | |
0eaef5aa | 7951 | op2 = MASK_MFMC0(ctx->opcode); |
6c5c1e20 TS |
7952 | switch (op2) { |
7953 | case OPC_DMT: | |
7954 | check_insn(env, ctx, ASE_MT); | |
a7812ae4 | 7955 | gen_helper_dmt(t0, t0); |
35fbce2c | 7956 | gen_store_gpr(t0, rt); |
6c5c1e20 TS |
7957 | break; |
7958 | case OPC_EMT: | |
7959 | check_insn(env, ctx, ASE_MT); | |
a7812ae4 | 7960 | gen_helper_emt(t0, t0); |
35fbce2c | 7961 | gen_store_gpr(t0, rt); |
da80682b | 7962 | break; |
6c5c1e20 TS |
7963 | case OPC_DVPE: |
7964 | check_insn(env, ctx, ASE_MT); | |
a7812ae4 | 7965 | gen_helper_dvpe(t0, t0); |
35fbce2c | 7966 | gen_store_gpr(t0, rt); |
6c5c1e20 TS |
7967 | break; |
7968 | case OPC_EVPE: | |
7969 | check_insn(env, ctx, ASE_MT); | |
a7812ae4 | 7970 | gen_helper_evpe(t0, t0); |
35fbce2c | 7971 | gen_store_gpr(t0, rt); |
6c5c1e20 TS |
7972 | break; |
7973 | case OPC_DI: | |
7974 | check_insn(env, ctx, ISA_MIPS32R2); | |
867abc7e | 7975 | save_cpu_state(ctx, 1); |
a7812ae4 | 7976 | gen_helper_di(t0); |
35fbce2c | 7977 | gen_store_gpr(t0, rt); |
6c5c1e20 TS |
7978 | /* Stop translation as we may have switched the execution mode */ |
7979 | ctx->bstate = BS_STOP; | |
7980 | break; | |
7981 | case OPC_EI: | |
7982 | check_insn(env, ctx, ISA_MIPS32R2); | |
867abc7e | 7983 | save_cpu_state(ctx, 1); |
a7812ae4 | 7984 | gen_helper_ei(t0); |
35fbce2c | 7985 | gen_store_gpr(t0, rt); |
6c5c1e20 TS |
7986 | /* Stop translation as we may have switched the execution mode */ |
7987 | ctx->bstate = BS_STOP; | |
7988 | break; | |
7989 | default: /* Invalid */ | |
7990 | MIPS_INVAL("mfmc0"); | |
7991 | generate_exception(ctx, EXCP_RI); | |
7992 | break; | |
7993 | } | |
6c5c1e20 | 7994 | tcg_temp_free(t0); |
7a387fff | 7995 | } |
0eaef5aa | 7996 | #endif /* !CONFIG_USER_ONLY */ |
6af0bf9c | 7997 | break; |
7a387fff | 7998 | case OPC_RDPGPR: |
e189e748 | 7999 | check_insn(env, ctx, ISA_MIPS32R2); |
be24bb4f | 8000 | gen_load_srsgpr(rt, rd); |
ead9360e | 8001 | break; |
7a387fff | 8002 | case OPC_WRPGPR: |
e189e748 | 8003 | check_insn(env, ctx, ISA_MIPS32R2); |
be24bb4f | 8004 | gen_store_srsgpr(rt, rd); |
38121543 | 8005 | break; |
6af0bf9c | 8006 | default: |
923617a3 | 8007 | MIPS_INVAL("cp0"); |
7a387fff | 8008 | generate_exception(ctx, EXCP_RI); |
6af0bf9c FB |
8009 | break; |
8010 | } | |
8011 | break; | |
324d9e32 AJ |
8012 | case OPC_ADDI: /* Arithmetic with immediate opcode */ |
8013 | case OPC_ADDIU: | |
e189e748 | 8014 | gen_arith_imm(env, ctx, op, rt, rs, imm); |
7a387fff | 8015 | break; |
324d9e32 AJ |
8016 | case OPC_SLTI: /* Set on less than with immediate opcode */ |
8017 | case OPC_SLTIU: | |
8018 | gen_slt_imm(env, op, rt, rs, imm); | |
8019 | break; | |
8020 | case OPC_ANDI: /* Arithmetic with immediate opcode */ | |
8021 | case OPC_LUI: | |
8022 | case OPC_ORI: | |
8023 | case OPC_XORI: | |
8024 | gen_logic_imm(env, op, rt, rs, imm); | |
8025 | break; | |
7a387fff TS |
8026 | case OPC_J ... OPC_JAL: /* Jump */ |
8027 | offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; | |
8028 | gen_compute_branch(ctx, op, rs, rt, offset); | |
8029 | return; | |
8030 | case OPC_BEQ ... OPC_BGTZ: /* Branch */ | |
8031 | case OPC_BEQL ... OPC_BGTZL: | |
8032 | gen_compute_branch(ctx, op, rs, rt, imm << 2); | |
8033 | return; | |
8034 | case OPC_LB ... OPC_LWR: /* Load and stores */ | |
8035 | case OPC_SB ... OPC_SW: | |
8036 | case OPC_SWR: | |
8037 | case OPC_LL: | |
7a387fff TS |
8038 | gen_ldst(ctx, op, rt, rs, imm); |
8039 | break; | |
d66c7132 AJ |
8040 | case OPC_SC: |
8041 | gen_st_cond(ctx, op, rt, rs, imm); | |
8042 | break; | |
7a387fff | 8043 | case OPC_CACHE: |
e189e748 | 8044 | check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); |
ead9360e | 8045 | /* Treat as NOP. */ |
34ae7b51 | 8046 | break; |
7a387fff | 8047 | case OPC_PREF: |
e189e748 | 8048 | check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); |
ead9360e | 8049 | /* Treat as NOP. */ |
6af0bf9c | 8050 | break; |
4ad40f36 | 8051 | |
923617a3 | 8052 | /* Floating point (COP1). */ |
7a387fff TS |
8053 | case OPC_LWC1: |
8054 | case OPC_LDC1: | |
8055 | case OPC_SWC1: | |
8056 | case OPC_SDC1: | |
36d23958 | 8057 | if (env->CP0_Config1 & (1 << CP0C1_FP)) { |
5e755519 | 8058 | check_cp1_enabled(ctx); |
36d23958 TS |
8059 | gen_flt_ldst(ctx, op, rt, rs, imm); |
8060 | } else { | |
8061 | generate_exception_err(ctx, EXCP_CpU, 1); | |
8062 | } | |
6ea83fed FB |
8063 | break; |
8064 | ||
7a387fff | 8065 | case OPC_CP1: |
36d23958 | 8066 | if (env->CP0_Config1 & (1 << CP0C1_FP)) { |
5e755519 | 8067 | check_cp1_enabled(ctx); |
36d23958 TS |
8068 | op1 = MASK_CP1(ctx->opcode); |
8069 | switch (op1) { | |
3a95e3a7 TS |
8070 | case OPC_MFHC1: |
8071 | case OPC_MTHC1: | |
e189e748 | 8072 | check_insn(env, ctx, ISA_MIPS32R2); |
36d23958 TS |
8073 | case OPC_MFC1: |
8074 | case OPC_CFC1: | |
8075 | case OPC_MTC1: | |
8076 | case OPC_CTC1: | |
e189e748 TS |
8077 | gen_cp1(ctx, op1, rt, rd); |
8078 | break; | |
d26bc211 | 8079 | #if defined(TARGET_MIPS64) |
36d23958 TS |
8080 | case OPC_DMFC1: |
8081 | case OPC_DMTC1: | |
e189e748 | 8082 | check_insn(env, ctx, ISA_MIPS3); |
36d23958 TS |
8083 | gen_cp1(ctx, op1, rt, rd); |
8084 | break; | |
e189e748 | 8085 | #endif |
fbcc6828 TS |
8086 | case OPC_BC1ANY2: |
8087 | case OPC_BC1ANY4: | |
b8aa4598 | 8088 | check_cop1x(ctx); |
7385ac0b | 8089 | check_insn(env, ctx, ASE_MIPS3D); |
d8a5950a TS |
8090 | /* fall through */ |
8091 | case OPC_BC1: | |
e189e748 | 8092 | gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), |
5a5012ec | 8093 | (rt >> 2) & 0x7, imm << 2); |
36d23958 TS |
8094 | return; |
8095 | case OPC_S_FMT: | |
8096 | case OPC_D_FMT: | |
8097 | case OPC_W_FMT: | |
8098 | case OPC_L_FMT: | |
5a5012ec TS |
8099 | case OPC_PS_FMT: |
8100 | gen_farith(ctx, MASK_CP1_FUNC(ctx->opcode), rt, rd, sa, | |
8101 | (imm >> 8) & 0x7); | |
36d23958 TS |
8102 | break; |
8103 | default: | |
923617a3 | 8104 | MIPS_INVAL("cp1"); |
e397ee33 | 8105 | generate_exception (ctx, EXCP_RI); |
36d23958 TS |
8106 | break; |
8107 | } | |
8108 | } else { | |
8109 | generate_exception_err(ctx, EXCP_CpU, 1); | |
6ea83fed | 8110 | } |
4ad40f36 FB |
8111 | break; |
8112 | ||
8113 | /* COP2. */ | |
7a387fff TS |
8114 | case OPC_LWC2: |
8115 | case OPC_LDC2: | |
8116 | case OPC_SWC2: | |
8117 | case OPC_SDC2: | |
8118 | case OPC_CP2: | |
8119 | /* COP2: Not implemented. */ | |
4ad40f36 FB |
8120 | generate_exception_err(ctx, EXCP_CpU, 2); |
8121 | break; | |
8122 | ||
7a387fff | 8123 | case OPC_CP3: |
36d23958 | 8124 | if (env->CP0_Config1 & (1 << CP0C1_FP)) { |
5e755519 | 8125 | check_cp1_enabled(ctx); |
36d23958 TS |
8126 | op1 = MASK_CP3(ctx->opcode); |
8127 | switch (op1) { | |
5a5012ec TS |
8128 | case OPC_LWXC1: |
8129 | case OPC_LDXC1: | |
8130 | case OPC_LUXC1: | |
8131 | case OPC_SWXC1: | |
8132 | case OPC_SDXC1: | |
8133 | case OPC_SUXC1: | |
93b12ccc | 8134 | gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); |
5a5012ec | 8135 | break; |
e0c84da7 | 8136 | case OPC_PREFX: |
ead9360e | 8137 | /* Treat as NOP. */ |
e0c84da7 | 8138 | break; |
5a5012ec TS |
8139 | case OPC_ALNV_PS: |
8140 | case OPC_MADD_S: | |
8141 | case OPC_MADD_D: | |
8142 | case OPC_MADD_PS: | |
8143 | case OPC_MSUB_S: | |
8144 | case OPC_MSUB_D: | |
8145 | case OPC_MSUB_PS: | |
8146 | case OPC_NMADD_S: | |
8147 | case OPC_NMADD_D: | |
8148 | case OPC_NMADD_PS: | |
8149 | case OPC_NMSUB_S: | |
8150 | case OPC_NMSUB_D: | |
8151 | case OPC_NMSUB_PS: | |
8152 | gen_flt3_arith(ctx, op1, sa, rs, rd, rt); | |
8153 | break; | |
36d23958 | 8154 | default: |
923617a3 | 8155 | MIPS_INVAL("cp3"); |
e397ee33 | 8156 | generate_exception (ctx, EXCP_RI); |
36d23958 TS |
8157 | break; |
8158 | } | |
8159 | } else { | |
e397ee33 | 8160 | generate_exception_err(ctx, EXCP_CpU, 1); |
7a387fff | 8161 | } |
4ad40f36 FB |
8162 | break; |
8163 | ||
d26bc211 | 8164 | #if defined(TARGET_MIPS64) |
7a387fff TS |
8165 | /* MIPS64 opcodes */ |
8166 | case OPC_LWU: | |
8167 | case OPC_LDL ... OPC_LDR: | |
8168 | case OPC_SDL ... OPC_SDR: | |
8169 | case OPC_LLD: | |
8170 | case OPC_LD: | |
7a387fff | 8171 | case OPC_SD: |
e189e748 TS |
8172 | check_insn(env, ctx, ISA_MIPS3); |
8173 | check_mips_64(ctx); | |
7a387fff TS |
8174 | gen_ldst(ctx, op, rt, rs, imm); |
8175 | break; | |
d66c7132 AJ |
8176 | case OPC_SCD: |
8177 | check_insn(env, ctx, ISA_MIPS3); | |
8178 | check_mips_64(ctx); | |
8179 | gen_st_cond(ctx, op, rt, rs, imm); | |
8180 | break; | |
324d9e32 AJ |
8181 | case OPC_DADDI: |
8182 | case OPC_DADDIU: | |
e189e748 TS |
8183 | check_insn(env, ctx, ISA_MIPS3); |
8184 | check_mips_64(ctx); | |
8185 | gen_arith_imm(env, ctx, op, rt, rs, imm); | |
7a387fff | 8186 | break; |
6af0bf9c | 8187 | #endif |
7a387fff | 8188 | case OPC_JALX: |
e189e748 | 8189 | check_insn(env, ctx, ASE_MIPS16); |
7a387fff | 8190 | /* MIPS16: Not implemented. */ |
7a387fff | 8191 | case OPC_MDMX: |
e189e748 | 8192 | check_insn(env, ctx, ASE_MDMX); |
7a387fff | 8193 | /* MDMX: Not implemented. */ |
6af0bf9c | 8194 | default: /* Invalid */ |
923617a3 | 8195 | MIPS_INVAL("major opcode"); |
6af0bf9c FB |
8196 | generate_exception(ctx, EXCP_RI); |
8197 | break; | |
8198 | } | |
4ad40f36 | 8199 | if (ctx->hflags & MIPS_HFLAG_BMASK) { |
c53f4a62 | 8200 | int hflags = ctx->hflags & MIPS_HFLAG_BMASK; |
6af0bf9c | 8201 | /* Branches completion */ |
4ad40f36 | 8202 | ctx->hflags &= ~MIPS_HFLAG_BMASK; |
6af0bf9c FB |
8203 | ctx->bstate = BS_BRANCH; |
8204 | save_cpu_state(ctx, 0); | |
2e70f6ef | 8205 | /* FIXME: Need to clear can_do_io. */ |
5a5012ec | 8206 | switch (hflags) { |
6af0bf9c FB |
8207 | case MIPS_HFLAG_B: |
8208 | /* unconditional branch */ | |
8209 | MIPS_DEBUG("unconditional branch"); | |
6e256c93 | 8210 | gen_goto_tb(ctx, 0, ctx->btarget); |
6af0bf9c FB |
8211 | break; |
8212 | case MIPS_HFLAG_BL: | |
8213 | /* blikely taken case */ | |
8214 | MIPS_DEBUG("blikely branch taken"); | |
6e256c93 | 8215 | gen_goto_tb(ctx, 0, ctx->btarget); |
6af0bf9c FB |
8216 | break; |
8217 | case MIPS_HFLAG_BC: | |
8218 | /* Conditional branch */ | |
8219 | MIPS_DEBUG("conditional branch"); | |
c53be334 | 8220 | { |
8e9ade68 TS |
8221 | int l1 = gen_new_label(); |
8222 | ||
1ba74fb8 | 8223 | tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); |
8e9ade68 TS |
8224 | gen_goto_tb(ctx, 1, ctx->pc + 4); |
8225 | gen_set_label(l1); | |
8226 | gen_goto_tb(ctx, 0, ctx->btarget); | |
c53be334 | 8227 | } |
6af0bf9c FB |
8228 | break; |
8229 | case MIPS_HFLAG_BR: | |
8230 | /* unconditional branch to register */ | |
8231 | MIPS_DEBUG("branch to register"); | |
4b2eb8d2 | 8232 | tcg_gen_mov_tl(cpu_PC, btarget); |
57fec1fe | 8233 | tcg_gen_exit_tb(0); |
6af0bf9c FB |
8234 | break; |
8235 | default: | |
8236 | MIPS_DEBUG("unknown branch"); | |
8237 | break; | |
8238 | } | |
8239 | } | |
8240 | } | |
8241 | ||
2cfc5f17 | 8242 | static inline void |
820e00f2 TS |
8243 | gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, |
8244 | int search_pc) | |
6af0bf9c | 8245 | { |
278d0702 | 8246 | DisasContext ctx; |
6af0bf9c FB |
8247 | target_ulong pc_start; |
8248 | uint16_t *gen_opc_end; | |
a1d1bb31 | 8249 | CPUBreakpoint *bp; |
6af0bf9c | 8250 | int j, lj = -1; |
2e70f6ef PB |
8251 | int num_insns; |
8252 | int max_insns; | |
6af0bf9c | 8253 | |
93fcfe39 AL |
8254 | if (search_pc) |
8255 | qemu_log("search pc %d\n", search_pc); | |
4ad40f36 | 8256 | |
6af0bf9c | 8257 | pc_start = tb->pc; |
faf7aaa9 TS |
8258 | /* Leave some spare opc slots for branch handling. */ |
8259 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE - 16; | |
6af0bf9c | 8260 | ctx.pc = pc_start; |
4ad40f36 | 8261 | ctx.saved_pc = -1; |
6af0bf9c FB |
8262 | ctx.tb = tb; |
8263 | ctx.bstate = BS_NONE; | |
4ad40f36 | 8264 | /* Restore delay slot state from the tb context. */ |
c068688b | 8265 | ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */ |
fd4a04eb | 8266 | restore_cpu_state(env, &ctx); |
932e71cd | 8267 | #ifdef CONFIG_USER_ONLY |
0eaef5aa | 8268 | ctx.mem_idx = MIPS_HFLAG_UM; |
932e71cd | 8269 | #else |
0eaef5aa | 8270 | ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU; |
932e71cd | 8271 | #endif |
2e70f6ef PB |
8272 | num_insns = 0; |
8273 | max_insns = tb->cflags & CF_COUNT_MASK; | |
8274 | if (max_insns == 0) | |
8275 | max_insns = CF_COUNT_MASK; | |
6af0bf9c | 8276 | #ifdef DEBUG_DISAS |
93fcfe39 AL |
8277 | qemu_log_mask(CPU_LOG_TB_CPU, "------------------------------------------------\n"); |
8278 | /* FIXME: This may print out stale hflags from env... */ | |
8279 | log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0); | |
6af0bf9c | 8280 | #endif |
d12d51d5 | 8281 | LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); |
2e70f6ef | 8282 | gen_icount_start(); |
faf7aaa9 | 8283 | while (ctx.bstate == BS_NONE) { |
c0ce998e AL |
8284 | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { |
8285 | TAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 8286 | if (bp->pc == ctx.pc) { |
278d0702 | 8287 | save_cpu_state(&ctx, 1); |
4ad40f36 | 8288 | ctx.bstate = BS_BRANCH; |
a7812ae4 | 8289 | gen_helper_0i(raise_exception, EXCP_DEBUG); |
ce62e5ba TS |
8290 | /* Include the breakpoint location or the tb won't |
8291 | * be flushed when it must be. */ | |
8292 | ctx.pc += 4; | |
4ad40f36 FB |
8293 | goto done_generating; |
8294 | } | |
8295 | } | |
8296 | } | |
8297 | ||
6af0bf9c FB |
8298 | if (search_pc) { |
8299 | j = gen_opc_ptr - gen_opc_buf; | |
6af0bf9c FB |
8300 | if (lj < j) { |
8301 | lj++; | |
8302 | while (lj < j) | |
8303 | gen_opc_instr_start[lj++] = 0; | |
6af0bf9c | 8304 | } |
4ad40f36 FB |
8305 | gen_opc_pc[lj] = ctx.pc; |
8306 | gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK; | |
8307 | gen_opc_instr_start[lj] = 1; | |
2e70f6ef | 8308 | gen_opc_icount[lj] = num_insns; |
6af0bf9c | 8309 | } |
2e70f6ef PB |
8310 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
8311 | gen_io_start(); | |
6af0bf9c | 8312 | ctx.opcode = ldl_code(ctx.pc); |
36d23958 | 8313 | decode_opc(env, &ctx); |
6af0bf9c | 8314 | ctx.pc += 4; |
2e70f6ef | 8315 | num_insns++; |
4ad40f36 FB |
8316 | |
8317 | if (env->singlestep_enabled) | |
8318 | break; | |
8319 | ||
6af0bf9c FB |
8320 | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
8321 | break; | |
4ad40f36 | 8322 | |
faf7aaa9 TS |
8323 | if (gen_opc_ptr >= gen_opc_end) |
8324 | break; | |
8325 | ||
2e70f6ef PB |
8326 | if (num_insns >= max_insns) |
8327 | break; | |
1b530a6d AJ |
8328 | |
8329 | if (singlestep) | |
8330 | break; | |
6af0bf9c | 8331 | } |
2e70f6ef PB |
8332 | if (tb->cflags & CF_LAST_IO) |
8333 | gen_io_end(); | |
4ad40f36 | 8334 | if (env->singlestep_enabled) { |
278d0702 | 8335 | save_cpu_state(&ctx, ctx.bstate == BS_NONE); |
a7812ae4 | 8336 | gen_helper_0i(raise_exception, EXCP_DEBUG); |
16c00cb2 | 8337 | } else { |
6958549d | 8338 | switch (ctx.bstate) { |
16c00cb2 | 8339 | case BS_STOP: |
a7812ae4 | 8340 | gen_helper_interrupt_restart(); |
df1561e2 TS |
8341 | gen_goto_tb(&ctx, 0, ctx.pc); |
8342 | break; | |
16c00cb2 | 8343 | case BS_NONE: |
278d0702 | 8344 | save_cpu_state(&ctx, 0); |
16c00cb2 TS |
8345 | gen_goto_tb(&ctx, 0, ctx.pc); |
8346 | break; | |
5a5012ec | 8347 | case BS_EXCP: |
a7812ae4 | 8348 | gen_helper_interrupt_restart(); |
57fec1fe | 8349 | tcg_gen_exit_tb(0); |
16c00cb2 | 8350 | break; |
5a5012ec TS |
8351 | case BS_BRANCH: |
8352 | default: | |
8353 | break; | |
6958549d | 8354 | } |
6af0bf9c | 8355 | } |
4ad40f36 | 8356 | done_generating: |
2e70f6ef | 8357 | gen_icount_end(tb, num_insns); |
6af0bf9c FB |
8358 | *gen_opc_ptr = INDEX_op_end; |
8359 | if (search_pc) { | |
8360 | j = gen_opc_ptr - gen_opc_buf; | |
8361 | lj++; | |
8362 | while (lj <= j) | |
8363 | gen_opc_instr_start[lj++] = 0; | |
6af0bf9c FB |
8364 | } else { |
8365 | tb->size = ctx.pc - pc_start; | |
2e70f6ef | 8366 | tb->icount = num_insns; |
6af0bf9c FB |
8367 | } |
8368 | #ifdef DEBUG_DISAS | |
d12d51d5 | 8369 | LOG_DISAS("\n"); |
8fec2b8c | 8370 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
93fcfe39 AL |
8371 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
8372 | log_target_disas(pc_start, ctx.pc - pc_start, 0); | |
8373 | qemu_log("\n"); | |
6af0bf9c | 8374 | } |
93fcfe39 | 8375 | qemu_log_mask(CPU_LOG_TB_CPU, "---------------- %d %08x\n", ctx.bstate, ctx.hflags); |
6af0bf9c | 8376 | #endif |
6af0bf9c FB |
8377 | } |
8378 | ||
2cfc5f17 | 8379 | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
6af0bf9c | 8380 | { |
2cfc5f17 | 8381 | gen_intermediate_code_internal(env, tb, 0); |
6af0bf9c FB |
8382 | } |
8383 | ||
2cfc5f17 | 8384 | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
6af0bf9c | 8385 | { |
2cfc5f17 | 8386 | gen_intermediate_code_internal(env, tb, 1); |
6af0bf9c FB |
8387 | } |
8388 | ||
8706c382 TS |
8389 | static void fpu_dump_state(CPUState *env, FILE *f, |
8390 | int (*fpu_fprintf)(FILE *f, const char *fmt, ...), | |
8391 | int flags) | |
6ea83fed FB |
8392 | { |
8393 | int i; | |
5e755519 | 8394 | int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); |
5a5012ec TS |
8395 | |
8396 | #define printfpr(fp) \ | |
8397 | do { \ | |
8398 | if (is_fpu64) \ | |
8399 | fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \ | |
8400 | (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \ | |
8401 | (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \ | |
8402 | else { \ | |
8403 | fpr_t tmp; \ | |
8404 | tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \ | |
8405 | tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \ | |
8406 | fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \ | |
8407 | tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \ | |
8408 | tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \ | |
8409 | } \ | |
6ea83fed FB |
8410 | } while(0) |
8411 | ||
5a5012ec TS |
8412 | |
8413 | fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", | |
f01be154 TS |
8414 | env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, env->active_fpu.fp_status, |
8415 | get_float_exception_flags(&env->active_fpu.fp_status)); | |
5a5012ec TS |
8416 | for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { |
8417 | fpu_fprintf(f, "%3s: ", fregnames[i]); | |
f01be154 | 8418 | printfpr(&env->active_fpu.fpr[i]); |
6ea83fed FB |
8419 | } |
8420 | ||
8421 | #undef printfpr | |
8422 | } | |
8423 | ||
d26bc211 | 8424 | #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) |
c570fd16 | 8425 | /* Debug help: The architecture requires 32bit code to maintain proper |
c7e8a937 | 8426 | sign-extended values on 64bit machines. */ |
c570fd16 TS |
8427 | |
8428 | #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff)) | |
8429 | ||
8706c382 TS |
8430 | static void |
8431 | cpu_mips_check_sign_extensions (CPUState *env, FILE *f, | |
8432 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
8433 | int flags) | |
c570fd16 TS |
8434 | { |
8435 | int i; | |
8436 | ||
b5dc7732 TS |
8437 | if (!SIGN_EXT_P(env->active_tc.PC)) |
8438 | cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->active_tc.PC); | |
8439 | if (!SIGN_EXT_P(env->active_tc.HI[0])) | |
8440 | cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->active_tc.HI[0]); | |
8441 | if (!SIGN_EXT_P(env->active_tc.LO[0])) | |
8442 | cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->active_tc.LO[0]); | |
c570fd16 | 8443 | if (!SIGN_EXT_P(env->btarget)) |
3594c774 | 8444 | cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget); |
c570fd16 TS |
8445 | |
8446 | for (i = 0; i < 32; i++) { | |
b5dc7732 TS |
8447 | if (!SIGN_EXT_P(env->active_tc.gpr[i])) |
8448 | cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->active_tc.gpr[i]); | |
c570fd16 TS |
8449 | } |
8450 | ||
8451 | if (!SIGN_EXT_P(env->CP0_EPC)) | |
3594c774 | 8452 | cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC); |
c570fd16 | 8453 | if (!SIGN_EXT_P(env->CP0_LLAddr)) |
3594c774 | 8454 | cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->CP0_LLAddr); |
c570fd16 TS |
8455 | } |
8456 | #endif | |
8457 | ||
5fafdf24 | 8458 | void cpu_dump_state (CPUState *env, FILE *f, |
6af0bf9c FB |
8459 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
8460 | int flags) | |
8461 | { | |
8462 | int i; | |
3b46e624 | 8463 | |
3594c774 | 8464 | cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n", |
3d5be870 TS |
8465 | env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], |
8466 | env->hflags, env->btarget, env->bcond); | |
6af0bf9c FB |
8467 | for (i = 0; i < 32; i++) { |
8468 | if ((i & 3) == 0) | |
8469 | cpu_fprintf(f, "GPR%02d:", i); | |
b5dc7732 | 8470 | cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->active_tc.gpr[i]); |
6af0bf9c FB |
8471 | if ((i & 3) == 3) |
8472 | cpu_fprintf(f, "\n"); | |
8473 | } | |
568b600d | 8474 | |
3594c774 | 8475 | cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx "\n", |
5e755519 | 8476 | env->CP0_Status, env->CP0_Cause, env->CP0_EPC); |
3594c774 | 8477 | cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n", |
6af0bf9c | 8478 | env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); |
5e755519 | 8479 | if (env->hflags & MIPS_HFLAG_FPU) |
7a387fff | 8480 | fpu_dump_state(env, f, cpu_fprintf, flags); |
d26bc211 | 8481 | #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) |
c570fd16 TS |
8482 | cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags); |
8483 | #endif | |
6af0bf9c FB |
8484 | } |
8485 | ||
39454628 TS |
8486 | static void mips_tcg_init(void) |
8487 | { | |
f01be154 | 8488 | int i; |
39454628 TS |
8489 | static int inited; |
8490 | ||
8491 | /* Initialize various static tables. */ | |
8492 | if (inited) | |
6958549d | 8493 | return; |
39454628 | 8494 | |
a7812ae4 | 8495 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
f2c94b92 | 8496 | TCGV_UNUSED(cpu_gpr[0]); |
bb928dbe | 8497 | for (i = 1; i < 32; i++) |
a7812ae4 | 8498 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
4b2eb8d2 TS |
8499 | offsetof(CPUState, active_tc.gpr[i]), |
8500 | regnames[i]); | |
a7812ae4 | 8501 | cpu_PC = tcg_global_mem_new(TCG_AREG0, |
4b2eb8d2 TS |
8502 | offsetof(CPUState, active_tc.PC), "PC"); |
8503 | for (i = 0; i < MIPS_DSP_ACC; i++) { | |
a7812ae4 | 8504 | cpu_HI[i] = tcg_global_mem_new(TCG_AREG0, |
4b2eb8d2 TS |
8505 | offsetof(CPUState, active_tc.HI[i]), |
8506 | regnames_HI[i]); | |
a7812ae4 | 8507 | cpu_LO[i] = tcg_global_mem_new(TCG_AREG0, |
4b2eb8d2 TS |
8508 | offsetof(CPUState, active_tc.LO[i]), |
8509 | regnames_LO[i]); | |
a7812ae4 | 8510 | cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0, |
4b2eb8d2 TS |
8511 | offsetof(CPUState, active_tc.ACX[i]), |
8512 | regnames_ACX[i]); | |
8513 | } | |
a7812ae4 | 8514 | cpu_dspctrl = tcg_global_mem_new(TCG_AREG0, |
4b2eb8d2 TS |
8515 | offsetof(CPUState, active_tc.DSPControl), |
8516 | "DSPControl"); | |
1ba74fb8 AJ |
8517 | bcond = tcg_global_mem_new(TCG_AREG0, |
8518 | offsetof(CPUState, bcond), "bcond"); | |
a7812ae4 | 8519 | btarget = tcg_global_mem_new(TCG_AREG0, |
d077b6f7 | 8520 | offsetof(CPUState, btarget), "btarget"); |
41db4607 AJ |
8521 | hflags = tcg_global_mem_new_i32(TCG_AREG0, |
8522 | offsetof(CPUState, hflags), "hflags"); | |
8523 | ||
a7812ae4 PB |
8524 | fpu_fcr0 = tcg_global_mem_new_i32(TCG_AREG0, |
8525 | offsetof(CPUState, active_fpu.fcr0), | |
8526 | "fcr0"); | |
8527 | fpu_fcr31 = tcg_global_mem_new_i32(TCG_AREG0, | |
8528 | offsetof(CPUState, active_fpu.fcr31), | |
8529 | "fcr31"); | |
39454628 | 8530 | |
7dd9e556 | 8531 | /* register helpers */ |
a7812ae4 | 8532 | #define GEN_HELPER 2 |
7dd9e556 TS |
8533 | #include "helper.h" |
8534 | ||
39454628 TS |
8535 | inited = 1; |
8536 | } | |
8537 | ||
aaed909a FB |
8538 | #include "translate_init.c" |
8539 | ||
8540 | CPUMIPSState *cpu_mips_init (const char *cpu_model) | |
6af0bf9c FB |
8541 | { |
8542 | CPUMIPSState *env; | |
aaed909a | 8543 | const mips_def_t *def; |
6af0bf9c | 8544 | |
aaed909a FB |
8545 | def = cpu_mips_find_by_name(cpu_model); |
8546 | if (!def) | |
8547 | return NULL; | |
6af0bf9c | 8548 | env = qemu_mallocz(sizeof(CPUMIPSState)); |
aaed909a FB |
8549 | env->cpu_model = def; |
8550 | ||
173d6cfe | 8551 | cpu_exec_init(env); |
01ba9816 | 8552 | env->cpu_model_str = cpu_model; |
39454628 | 8553 | mips_tcg_init(); |
6ae81775 | 8554 | cpu_reset(env); |
0bf46a40 | 8555 | qemu_init_vcpu(env); |
6ae81775 TS |
8556 | return env; |
8557 | } | |
8558 | ||
8559 | void cpu_reset (CPUMIPSState *env) | |
8560 | { | |
eca1bdf4 AL |
8561 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { |
8562 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
8563 | log_cpu_state(env, 0); | |
8564 | } | |
8565 | ||
6ae81775 TS |
8566 | memset(env, 0, offsetof(CPUMIPSState, breakpoints)); |
8567 | ||
6af0bf9c | 8568 | tlb_flush(env, 1); |
6ae81775 | 8569 | |
6af0bf9c | 8570 | /* Minimal init */ |
0eaef5aa | 8571 | #if defined(CONFIG_USER_ONLY) |
932e71cd | 8572 | env->hflags = MIPS_HFLAG_UM; |
df357f0e PB |
8573 | /* Enable access to the SYNCI_Step register. */ |
8574 | env->CP0_HWREna |= (1 << 1); | |
932e71cd AJ |
8575 | #else |
8576 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
8577 | /* If the exception was raised from a delay slot, | |
8578 | come back to the jump. */ | |
8579 | env->CP0_ErrorEPC = env->active_tc.PC - 4; | |
aa328add | 8580 | } else { |
932e71cd AJ |
8581 | env->CP0_ErrorEPC = env->active_tc.PC; |
8582 | } | |
8583 | env->active_tc.PC = (int32_t)0xBFC00000; | |
8584 | env->CP0_Wired = 0; | |
8585 | /* SMP not implemented */ | |
8586 | env->CP0_EBase = 0x80000000; | |
8587 | env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); | |
8588 | /* vectored interrupts not implemented, timer on int 7, | |
8589 | no performance counters. */ | |
8590 | env->CP0_IntCtl = 0xe0000000; | |
8591 | { | |
8592 | int i; | |
8593 | ||
8594 | for (i = 0; i < 7; i++) { | |
8595 | env->CP0_WatchLo[i] = 0; | |
8596 | env->CP0_WatchHi[i] = 0x80000000; | |
fd88b6ab | 8597 | } |
932e71cd AJ |
8598 | env->CP0_WatchLo[7] = 0; |
8599 | env->CP0_WatchHi[7] = 0; | |
fd88b6ab | 8600 | } |
932e71cd AJ |
8601 | /* Count register increments in debug mode, EJTAG version 1 */ |
8602 | env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); | |
8603 | env->hflags = MIPS_HFLAG_CP0; | |
8604 | #endif | |
6af0bf9c | 8605 | env->exception_index = EXCP_NONE; |
aaed909a | 8606 | cpu_mips_register(env, env->cpu_model); |
6af0bf9c | 8607 | } |
d2856f1a AJ |
8608 | |
8609 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
8610 | unsigned long searched_pc, int pc_pos, void *puc) | |
8611 | { | |
b5dc7732 | 8612 | env->active_tc.PC = gen_opc_pc[pc_pos]; |
d2856f1a AJ |
8613 | env->hflags &= ~MIPS_HFLAG_BMASK; |
8614 | env->hflags |= gen_opc_hflags[pc_pos]; | |
8615 | } |