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33d68b5f TS |
1 | /* |
2 | * MIPS emulation for qemu: CPU initialisation routines. | |
3 | * | |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer | |
5 | * Copyright (c) 2007 Herve Poussineau | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
33d68b5f TS |
19 | */ |
20 | ||
3953d786 TS |
21 | /* CPU / CPU family specific config register values. */ |
22 | ||
6d35524c | 23 | /* Have config1, uncached coherency */ |
3953d786 | 24 | #define MIPS_CONFIG0 \ |
f45cb2f4 | 25 | ((1U << CP0C0_M) | (0x2 << CP0C0_K0)) |
3953d786 | 26 | |
ae5d8053 | 27 | /* Have config2, no coprocessor2 attached, no MDMX support attached, |
3953d786 TS |
28 | no performance counters, watch registers present, |
29 | no code compression, EJTAG present, no FPU */ | |
30 | #define MIPS_CONFIG1 \ | |
f45cb2f4 | 31 | ((1U << CP0C1_M) | \ |
3953d786 TS |
32 | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
33 | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ | |
34 | (0 << CP0C1_FP)) | |
35 | ||
36 | /* Have config3, no tertiary/secondary caches implemented */ | |
37 | #define MIPS_CONFIG2 \ | |
f45cb2f4 | 38 | ((1U << CP0C2_M)) |
3953d786 | 39 | |
6d35524c | 40 | /* No config4, no DSP ASE, no large physaddr (PABITS), |
ff2712ba | 41 | no external interrupt controller, no vectored interrupts, |
ead9360e | 42 | no 1kb pages, no SmartMIPS ASE, no trace logic */ |
3953d786 TS |
43 | #define MIPS_CONFIG3 \ |
44 | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ | |
45 | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ | |
ead9360e | 46 | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
3953d786 | 47 | |
b4160af1 PJ |
48 | #define MIPS_CONFIG4 \ |
49 | ((0 << CP0C4_M)) | |
50 | ||
b4dd99a3 PJ |
51 | #define MIPS_CONFIG5 \ |
52 | ((0 << CP0C5_M)) | |
53 | ||
6d35524c TS |
54 | /* MMU types, the first four entries have the same layout as the |
55 | CP0C0_MT field. */ | |
56 | enum mips_mmu_types { | |
57 | MMU_TYPE_NONE, | |
58 | MMU_TYPE_R4000, | |
59 | MMU_TYPE_RESERVED, | |
60 | MMU_TYPE_FMT, | |
61 | MMU_TYPE_R3000, | |
62 | MMU_TYPE_R6000, | |
63 | MMU_TYPE_R8000 | |
64 | }; | |
65 | ||
c227f099 | 66 | struct mips_def_t { |
50366fe9 | 67 | const char *name; |
33d68b5f TS |
68 | int32_t CP0_PRid; |
69 | int32_t CP0_Config0; | |
70 | int32_t CP0_Config1; | |
3953d786 TS |
71 | int32_t CP0_Config2; |
72 | int32_t CP0_Config3; | |
b4160af1 PJ |
73 | int32_t CP0_Config4; |
74 | int32_t CP0_Config4_rw_bitmask; | |
b4dd99a3 PJ |
75 | int32_t CP0_Config5; |
76 | int32_t CP0_Config5_rw_bitmask; | |
34ee2ede TS |
77 | int32_t CP0_Config6; |
78 | int32_t CP0_Config7; | |
2a6e32dd AJ |
79 | target_ulong CP0_LLAddr_rw_bitmask; |
80 | int CP0_LLAddr_shift; | |
2f644545 TS |
81 | int32_t SYNCI_Step; |
82 | int32_t CCRes; | |
ead9360e TS |
83 | int32_t CP0_Status_rw_bitmask; |
84 | int32_t CP0_TCStatus_rw_bitmask; | |
85 | int32_t CP0_SRSCtl; | |
3953d786 | 86 | int32_t CP1_fcr0; |
599bc5e8 | 87 | int32_t CP1_fcr31_rw_bitmask; |
ba5c79f2 | 88 | int32_t CP1_fcr31; |
863f264d | 89 | int32_t MSAIR; |
e034e2c3 | 90 | int32_t SEGBITS; |
6d35524c | 91 | int32_t PABITS; |
ead9360e TS |
92 | int32_t CP0_SRSConf0_rw_bitmask; |
93 | int32_t CP0_SRSConf0; | |
94 | int32_t CP0_SRSConf1_rw_bitmask; | |
95 | int32_t CP0_SRSConf1; | |
96 | int32_t CP0_SRSConf2_rw_bitmask; | |
97 | int32_t CP0_SRSConf2; | |
98 | int32_t CP0_SRSConf3_rw_bitmask; | |
99 | int32_t CP0_SRSConf3; | |
100 | int32_t CP0_SRSConf4_rw_bitmask; | |
101 | int32_t CP0_SRSConf4; | |
7207c7f9 LA |
102 | int32_t CP0_PageGrain_rw_bitmask; |
103 | int32_t CP0_PageGrain; | |
e189e748 | 104 | int insn_flags; |
6d35524c | 105 | enum mips_mmu_types mmu_type; |
33d68b5f TS |
106 | }; |
107 | ||
108 | /*****************************************************************************/ | |
109 | /* MIPS CPU definitions */ | |
c227f099 | 110 | static const mips_def_t mips_defs[] = |
33d68b5f | 111 | { |
33d68b5f TS |
112 | { |
113 | .name = "4Kc", | |
114 | .CP0_PRid = 0x00018000, | |
6d35524c | 115 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
ae5d8053 | 116 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
6958549d | 117 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
d19954f4 | 118 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
ab3aee26 | 119 | (0 << CP0C1_CA), |
3953d786 TS |
120 | .CP0_Config2 = MIPS_CONFIG2, |
121 | .CP0_Config3 = MIPS_CONFIG3, | |
2a6e32dd AJ |
122 | .CP0_LLAddr_rw_bitmask = 0, |
123 | .CP0_LLAddr_shift = 4, | |
2f644545 TS |
124 | .SYNCI_Step = 32, |
125 | .CCRes = 2, | |
ead9360e | 126 | .CP0_Status_rw_bitmask = 0x1278FF17, |
6d35524c TS |
127 | .SEGBITS = 32, |
128 | .PABITS = 32, | |
73642f5b | 129 | .insn_flags = CPU_MIPS32, |
6d35524c | 130 | .mmu_type = MMU_TYPE_R4000, |
33d68b5f | 131 | }, |
8d162c2b TS |
132 | { |
133 | .name = "4Km", | |
134 | .CP0_PRid = 0x00018300, | |
135 | /* Config1 implemented, fixed mapping MMU, | |
136 | no virtual icache, uncached coherency. */ | |
6d35524c | 137 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
8d162c2b | 138 | .CP0_Config1 = MIPS_CONFIG1 | |
6958549d | 139 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
d19954f4 NF |
140 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
141 | (1 << CP0C1_CA), | |
8d162c2b TS |
142 | .CP0_Config2 = MIPS_CONFIG2, |
143 | .CP0_Config3 = MIPS_CONFIG3, | |
2a6e32dd AJ |
144 | .CP0_LLAddr_rw_bitmask = 0, |
145 | .CP0_LLAddr_shift = 4, | |
8d162c2b TS |
146 | .SYNCI_Step = 32, |
147 | .CCRes = 2, | |
148 | .CP0_Status_rw_bitmask = 0x1258FF17, | |
6d35524c TS |
149 | .SEGBITS = 32, |
150 | .PABITS = 32, | |
8d162c2b | 151 | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
6d35524c | 152 | .mmu_type = MMU_TYPE_FMT, |
8d162c2b | 153 | }, |
33d68b5f | 154 | { |
34ee2ede | 155 | .name = "4KEcR1", |
33d68b5f | 156 | .CP0_PRid = 0x00018400, |
6d35524c | 157 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
ae5d8053 | 158 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
6958549d | 159 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
d19954f4 | 160 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
ab3aee26 | 161 | (0 << CP0C1_CA), |
34ee2ede TS |
162 | .CP0_Config2 = MIPS_CONFIG2, |
163 | .CP0_Config3 = MIPS_CONFIG3, | |
2a6e32dd AJ |
164 | .CP0_LLAddr_rw_bitmask = 0, |
165 | .CP0_LLAddr_shift = 4, | |
2f644545 TS |
166 | .SYNCI_Step = 32, |
167 | .CCRes = 2, | |
ead9360e | 168 | .CP0_Status_rw_bitmask = 0x1278FF17, |
6d35524c TS |
169 | .SEGBITS = 32, |
170 | .PABITS = 32, | |
73642f5b | 171 | .insn_flags = CPU_MIPS32, |
6d35524c | 172 | .mmu_type = MMU_TYPE_R4000, |
34ee2ede | 173 | }, |
8d162c2b TS |
174 | { |
175 | .name = "4KEmR1", | |
176 | .CP0_PRid = 0x00018500, | |
6d35524c | 177 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
8d162c2b | 178 | .CP0_Config1 = MIPS_CONFIG1 | |
6958549d | 179 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
d19954f4 NF |
180 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
181 | (1 << CP0C1_CA), | |
8d162c2b TS |
182 | .CP0_Config2 = MIPS_CONFIG2, |
183 | .CP0_Config3 = MIPS_CONFIG3, | |
2a6e32dd AJ |
184 | .CP0_LLAddr_rw_bitmask = 0, |
185 | .CP0_LLAddr_shift = 4, | |
8d162c2b TS |
186 | .SYNCI_Step = 32, |
187 | .CCRes = 2, | |
188 | .CP0_Status_rw_bitmask = 0x1258FF17, | |
6d35524c TS |
189 | .SEGBITS = 32, |
190 | .PABITS = 32, | |
8d162c2b | 191 | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
6d35524c | 192 | .mmu_type = MMU_TYPE_FMT, |
8d162c2b | 193 | }, |
34ee2ede TS |
194 | { |
195 | .name = "4KEc", | |
196 | .CP0_PRid = 0x00019000, | |
6d35524c TS |
197 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
198 | (MMU_TYPE_R4000 << CP0C0_MT), | |
ae5d8053 | 199 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
6958549d | 200 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
d19954f4 | 201 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
ab3aee26 | 202 | (0 << CP0C1_CA), |
34ee2ede | 203 | .CP0_Config2 = MIPS_CONFIG2, |
ead9360e | 204 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
2a6e32dd AJ |
205 | .CP0_LLAddr_rw_bitmask = 0, |
206 | .CP0_LLAddr_shift = 4, | |
2f644545 TS |
207 | .SYNCI_Step = 32, |
208 | .CCRes = 2, | |
ead9360e | 209 | .CP0_Status_rw_bitmask = 0x1278FF17, |
6d35524c TS |
210 | .SEGBITS = 32, |
211 | .PABITS = 32, | |
73642f5b | 212 | .insn_flags = CPU_MIPS32R2, |
6d35524c | 213 | .mmu_type = MMU_TYPE_R4000, |
34ee2ede | 214 | }, |
3e4587d5 TS |
215 | { |
216 | .name = "4KEm", | |
217 | .CP0_PRid = 0x00019100, | |
6d35524c | 218 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
6958549d | 219 | (MMU_TYPE_FMT << CP0C0_MT), |
3e4587d5 | 220 | .CP0_Config1 = MIPS_CONFIG1 | |
6958549d | 221 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
d19954f4 NF |
222 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
223 | (1 << CP0C1_CA), | |
3e4587d5 TS |
224 | .CP0_Config2 = MIPS_CONFIG2, |
225 | .CP0_Config3 = MIPS_CONFIG3, | |
2a6e32dd AJ |
226 | .CP0_LLAddr_rw_bitmask = 0, |
227 | .CP0_LLAddr_shift = 4, | |
3e4587d5 TS |
228 | .SYNCI_Step = 32, |
229 | .CCRes = 2, | |
230 | .CP0_Status_rw_bitmask = 0x1258FF17, | |
6d35524c TS |
231 | .SEGBITS = 32, |
232 | .PABITS = 32, | |
3e4587d5 | 233 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
6d35524c | 234 | .mmu_type = MMU_TYPE_FMT, |
3e4587d5 | 235 | }, |
34ee2ede TS |
236 | { |
237 | .name = "24Kc", | |
238 | .CP0_PRid = 0x00019300, | |
6d35524c | 239 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
6958549d | 240 | (MMU_TYPE_R4000 << CP0C0_MT), |
ae5d8053 | 241 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
6958549d | 242 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
d19954f4 NF |
243 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
244 | (1 << CP0C1_CA), | |
3953d786 | 245 | .CP0_Config2 = MIPS_CONFIG2, |
ead9360e | 246 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
2a6e32dd AJ |
247 | .CP0_LLAddr_rw_bitmask = 0, |
248 | .CP0_LLAddr_shift = 4, | |
2f644545 TS |
249 | .SYNCI_Step = 32, |
250 | .CCRes = 2, | |
ead9360e | 251 | /* No DSP implemented. */ |
671880e6 | 252 | .CP0_Status_rw_bitmask = 0x1278FF1F, |
6d35524c TS |
253 | .SEGBITS = 32, |
254 | .PABITS = 32, | |
3e4587d5 | 255 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
6d35524c | 256 | .mmu_type = MMU_TYPE_R4000, |
33d68b5f TS |
257 | }, |
258 | { | |
259 | .name = "24Kf", | |
260 | .CP0_PRid = 0x00019300, | |
6d35524c TS |
261 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
262 | (MMU_TYPE_R4000 << CP0C0_MT), | |
ae5d8053 | 263 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
6958549d | 264 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
d19954f4 NF |
265 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
266 | (1 << CP0C1_CA), | |
3953d786 | 267 | .CP0_Config2 = MIPS_CONFIG2, |
ead9360e | 268 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
2a6e32dd AJ |
269 | .CP0_LLAddr_rw_bitmask = 0, |
270 | .CP0_LLAddr_shift = 4, | |
2f644545 TS |
271 | .SYNCI_Step = 32, |
272 | .CCRes = 2, | |
ead9360e | 273 | /* No DSP implemented. */ |
671880e6 | 274 | .CP0_Status_rw_bitmask = 0x3678FF1F, |
5a5012ec TS |
275 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
276 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), | |
599bc5e8 AM |
277 | .CP1_fcr31 = 0, |
278 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
6d35524c TS |
279 | .SEGBITS = 32, |
280 | .PABITS = 32, | |
3e4587d5 | 281 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
6d35524c | 282 | .mmu_type = MMU_TYPE_R4000, |
33d68b5f | 283 | }, |
ead9360e TS |
284 | { |
285 | .name = "34Kf", | |
286 | .CP0_PRid = 0x00019500, | |
6d35524c | 287 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
6958549d | 288 | (MMU_TYPE_R4000 << CP0C0_MT), |
ead9360e | 289 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
6958549d | 290 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
d19954f4 NF |
291 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
292 | (1 << CP0C1_CA), | |
ead9360e | 293 | .CP0_Config2 = MIPS_CONFIG2, |
b9ac5d92 YK |
294 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | |
295 | (1 << CP0C3_DSPP), | |
2a6e32dd AJ |
296 | .CP0_LLAddr_rw_bitmask = 0, |
297 | .CP0_LLAddr_shift = 0, | |
ead9360e TS |
298 | .SYNCI_Step = 32, |
299 | .CCRes = 2, | |
b9ac5d92 | 300 | .CP0_Status_rw_bitmask = 0x3778FF1F, |
ead9360e TS |
301 | .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
302 | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | | |
303 | (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | | |
304 | (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | | |
305 | (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | | |
306 | (0xff << CP0TCSt_TASID), | |
307 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | | |
308 | (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), | |
599bc5e8 AM |
309 | .CP1_fcr31 = 0, |
310 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
ead9360e TS |
311 | .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), |
312 | .CP0_SRSConf0_rw_bitmask = 0x3fffffff, | |
f45cb2f4 | 313 | .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
ead9360e TS |
314 | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
315 | .CP0_SRSConf1_rw_bitmask = 0x3fffffff, | |
f45cb2f4 | 316 | .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
ead9360e TS |
317 | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
318 | .CP0_SRSConf2_rw_bitmask = 0x3fffffff, | |
f45cb2f4 | 319 | .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
ead9360e TS |
320 | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
321 | .CP0_SRSConf3_rw_bitmask = 0x3fffffff, | |
f45cb2f4 | 322 | .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
ead9360e TS |
323 | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
324 | .CP0_SRSConf4_rw_bitmask = 0x3fffffff, | |
325 | .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | | |
326 | (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), | |
6d35524c TS |
327 | .SEGBITS = 32, |
328 | .PABITS = 32, | |
7385ac0b | 329 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, |
6d35524c | 330 | .mmu_type = MMU_TYPE_R4000, |
ead9360e | 331 | }, |
af13ae03 JL |
332 | { |
333 | .name = "74Kf", | |
334 | .CP0_PRid = 0x00019700, | |
335 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | | |
336 | (MMU_TYPE_R4000 << CP0C0_MT), | |
337 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | | |
338 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | | |
339 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | | |
340 | (1 << CP0C1_CA), | |
341 | .CP0_Config2 = MIPS_CONFIG2, | |
e30614d5 | 342 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | |
4386f087 | 343 | (1 << CP0C3_VInt), |
af13ae03 JL |
344 | .CP0_LLAddr_rw_bitmask = 0, |
345 | .CP0_LLAddr_shift = 4, | |
346 | .SYNCI_Step = 32, | |
347 | .CCRes = 2, | |
348 | .CP0_Status_rw_bitmask = 0x3778FF1F, | |
349 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | | |
350 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), | |
599bc5e8 AM |
351 | .CP1_fcr31 = 0, |
352 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
af13ae03 JL |
353 | .SEGBITS = 32, |
354 | .PABITS = 32, | |
355 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, | |
356 | .mmu_type = MMU_TYPE_R4000, | |
357 | }, | |
11f5ea10 MR |
358 | { |
359 | .name = "M14K", | |
360 | .CP0_PRid = 0x00019b00, | |
361 | /* Config1 implemented, fixed mapping MMU, | |
362 | no virtual icache, uncached coherency. */ | |
363 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) | | |
364 | (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT), | |
365 | .CP0_Config1 = MIPS_CONFIG1, | |
366 | .CP0_Config2 = MIPS_CONFIG2, | |
367 | .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt), | |
368 | .CP0_LLAddr_rw_bitmask = 0, | |
369 | .CP0_LLAddr_shift = 4, | |
370 | .SYNCI_Step = 32, | |
371 | .CCRes = 2, | |
372 | .CP0_Status_rw_bitmask = 0x1258FF17, | |
373 | .SEGBITS = 32, | |
374 | .PABITS = 32, | |
375 | .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, | |
376 | .mmu_type = MMU_TYPE_FMT, | |
377 | }, | |
378 | { | |
379 | .name = "M14Kc", | |
380 | /* This is the TLB-based MMU core. */ | |
381 | .CP0_PRid = 0x00019c00, | |
382 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | | |
383 | (MMU_TYPE_R4000 << CP0C0_MT), | |
384 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | | |
385 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | | |
386 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), | |
387 | .CP0_Config2 = MIPS_CONFIG2, | |
388 | .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt), | |
389 | .CP0_LLAddr_rw_bitmask = 0, | |
390 | .CP0_LLAddr_shift = 4, | |
391 | .SYNCI_Step = 32, | |
392 | .CCRes = 2, | |
393 | .CP0_Status_rw_bitmask = 0x1278FF17, | |
394 | .SEGBITS = 32, | |
395 | .PABITS = 32, | |
396 | .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, | |
397 | .mmu_type = MMU_TYPE_R4000, | |
398 | }, | |
e527526d | 399 | { |
aff2bc6d YK |
400 | /* FIXME: |
401 | * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL | |
402 | * Config4: MMUExtDef | |
403 | * Config5: EVA, MRP | |
404 | * FIR(FCR0): Has2008 | |
405 | * */ | |
406 | .name = "P5600", | |
407 | .CP0_PRid = 0x0001A800, | |
408 | .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) | | |
e527526d | 409 | (MMU_TYPE_R4000 << CP0C0_MT), |
aff2bc6d YK |
410 | .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | |
411 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | | |
412 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | | |
413 | (1 << CP0C1_PC) | (1 << CP0C1_FP), | |
e527526d | 414 | .CP0_Config2 = MIPS_CONFIG2, |
6773f9b6 | 415 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | |
aff2bc6d YK |
416 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | |
417 | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), | |
418 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | | |
419 | (0x1c << CP0C4_KScrExist), | |
b4160af1 | 420 | .CP0_Config4_rw_bitmask = 0, |
f6d4dd81 YK |
421 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) | |
422 | (1 << CP0C5_MRP), | |
aff2bc6d YK |
423 | .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | |
424 | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | | |
425 | (1 << CP0C5_FRE) | (1 << CP0C5_UFR), | |
e527526d | 426 | .CP0_LLAddr_rw_bitmask = 0, |
aff2bc6d | 427 | .CP0_LLAddr_shift = 0, |
e527526d PJ |
428 | .SYNCI_Step = 32, |
429 | .CCRes = 2, | |
aff2bc6d YK |
430 | .CP0_Status_rw_bitmask = 0x3C68FF1F, |
431 | .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | | |
432 | (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), | |
ba5c79f2 LA |
433 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) | |
434 | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | | |
435 | (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID), | |
436 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), | |
599bc5e8 | 437 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
e527526d | 438 | .SEGBITS = 32, |
6773f9b6 | 439 | .PABITS = 40, |
aff2bc6d | 440 | .insn_flags = CPU_MIPS32R5 | ASE_MSA, |
e527526d PJ |
441 | .mmu_type = MMU_TYPE_R4000, |
442 | }, | |
4b3bcd01 YK |
443 | { |
444 | /* A generic CPU supporting MIPS32 Release 6 ISA. | |
445 | FIXME: Support IEEE 754-2008 FP. | |
446 | Eventually this should be replaced by a real CPU model. */ | |
447 | .name = "mips32r6-generic", | |
448 | .CP0_PRid = 0x00010000, | |
449 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | | |
450 | (MMU_TYPE_R4000 << CP0C0_MT), | |
451 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | | |
452 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | | |
453 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | | |
454 | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | |
455 | .CP0_Config2 = MIPS_CONFIG2, | |
456 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | | |
457 | (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | | |
458 | (1 << CP0C3_RXI) | (1U << CP0C3_M), | |
459 | .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | | |
460 | (3 << CP0C4_IE) | (1U << CP0C4_M), | |
35ac9e34 | 461 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), |
4b3bcd01 YK |
462 | .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | |
463 | (1 << CP0C5_UFE), | |
464 | .CP0_LLAddr_rw_bitmask = 0, | |
465 | .CP0_LLAddr_shift = 0, | |
466 | .SYNCI_Step = 32, | |
467 | .CCRes = 2, | |
468 | .CP0_Status_rw_bitmask = 0x3058FF1F, | |
469 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | | |
470 | (1U << CP0PG_RIE), | |
471 | .CP0_PageGrain_rw_bitmask = 0, | |
ba5c79f2 LA |
472 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
473 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | | |
474 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), | |
475 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), | |
599bc5e8 | 476 | .CP1_fcr31_rw_bitmask = 0x0103FFFF, |
4b3bcd01 YK |
477 | .SEGBITS = 32, |
478 | .PABITS = 32, | |
479 | .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS, | |
480 | .mmu_type = MMU_TYPE_R4000, | |
481 | }, | |
d26bc211 | 482 | #if defined(TARGET_MIPS64) |
33d68b5f TS |
483 | { |
484 | .name = "R4000", | |
485 | .CP0_PRid = 0x00000400, | |
6d35524c TS |
486 | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
487 | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), | |
6958549d | 488 | /* Note: Config1 is only used internally, the R4000 has only Config0. */ |
6d35524c | 489 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
2a6e32dd AJ |
490 | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, |
491 | .CP0_LLAddr_shift = 4, | |
2f644545 TS |
492 | .SYNCI_Step = 16, |
493 | .CCRes = 2, | |
ead9360e | 494 | .CP0_Status_rw_bitmask = 0x3678FFFF, |
6958549d | 495 | /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
c9c1a064 | 496 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
599bc5e8 AM |
497 | .CP1_fcr31 = 0, |
498 | .CP1_fcr31_rw_bitmask = 0x0183FFFF, | |
e034e2c3 | 499 | .SEGBITS = 40, |
6d35524c | 500 | .PABITS = 36, |
e189e748 | 501 | .insn_flags = CPU_MIPS3, |
6d35524c | 502 | .mmu_type = MMU_TYPE_R4000, |
c9c1a064 | 503 | }, |
e9c71dd1 TS |
504 | { |
505 | .name = "VR5432", | |
506 | .CP0_PRid = 0x00005400, | |
507 | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ | |
508 | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), | |
509 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), | |
2a6e32dd AJ |
510 | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, |
511 | .CP0_LLAddr_shift = 4, | |
e9c71dd1 TS |
512 | .SYNCI_Step = 16, |
513 | .CCRes = 2, | |
514 | .CP0_Status_rw_bitmask = 0x3678FFFF, | |
515 | /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ | |
516 | .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), | |
599bc5e8 AM |
517 | .CP1_fcr31 = 0, |
518 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
e9c71dd1 TS |
519 | .SEGBITS = 40, |
520 | .PABITS = 32, | |
521 | .insn_flags = CPU_VR54XX, | |
522 | .mmu_type = MMU_TYPE_R4000, | |
523 | }, | |
c9c1a064 TS |
524 | { |
525 | .name = "5Kc", | |
526 | .CP0_PRid = 0x00018100, | |
29fe0e34 | 527 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
6958549d | 528 | (MMU_TYPE_R4000 << CP0C0_MT), |
c9c1a064 | 529 | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | |
6958549d AJ |
530 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
531 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | | |
532 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | |
c9c1a064 TS |
533 | .CP0_Config2 = MIPS_CONFIG2, |
534 | .CP0_Config3 = MIPS_CONFIG3, | |
2a6e32dd AJ |
535 | .CP0_LLAddr_rw_bitmask = 0, |
536 | .CP0_LLAddr_shift = 4, | |
c9c1a064 TS |
537 | .SYNCI_Step = 32, |
538 | .CCRes = 2, | |
196a7958 | 539 | .CP0_Status_rw_bitmask = 0x12F8FFFF, |
e034e2c3 | 540 | .SEGBITS = 42, |
6d35524c | 541 | .PABITS = 36, |
e189e748 | 542 | .insn_flags = CPU_MIPS64, |
6d35524c | 543 | .mmu_type = MMU_TYPE_R4000, |
c9c1a064 TS |
544 | }, |
545 | { | |
546 | .name = "5Kf", | |
547 | .CP0_PRid = 0x00018100, | |
29fe0e34 | 548 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
6958549d | 549 | (MMU_TYPE_R4000 << CP0C0_MT), |
c9c1a064 | 550 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
6958549d AJ |
551 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
552 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | | |
553 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | |
c9c1a064 TS |
554 | .CP0_Config2 = MIPS_CONFIG2, |
555 | .CP0_Config3 = MIPS_CONFIG3, | |
2a6e32dd AJ |
556 | .CP0_LLAddr_rw_bitmask = 0, |
557 | .CP0_LLAddr_shift = 4, | |
c9c1a064 TS |
558 | .SYNCI_Step = 32, |
559 | .CCRes = 2, | |
ead9360e | 560 | .CP0_Status_rw_bitmask = 0x36F8FFFF, |
6958549d | 561 | /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ |
c9c1a064 TS |
562 | .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
563 | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), | |
599bc5e8 AM |
564 | .CP1_fcr31 = 0, |
565 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
e034e2c3 | 566 | .SEGBITS = 42, |
6d35524c | 567 | .PABITS = 36, |
e189e748 | 568 | .insn_flags = CPU_MIPS64, |
6d35524c | 569 | .mmu_type = MMU_TYPE_R4000, |
c9c1a064 TS |
570 | }, |
571 | { | |
572 | .name = "20Kc", | |
6958549d | 573 | /* We emulate a later version of the 20Kc, earlier ones had a broken |
bd04c6fe TS |
574 | WAIT instruction. */ |
575 | .CP0_PRid = 0x000182a0, | |
29fe0e34 | 576 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
6d35524c | 577 | (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), |
c9c1a064 | 578 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
6958549d AJ |
579 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
580 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | | |
581 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | |
c9c1a064 TS |
582 | .CP0_Config2 = MIPS_CONFIG2, |
583 | .CP0_Config3 = MIPS_CONFIG3, | |
2a6e32dd AJ |
584 | .CP0_LLAddr_rw_bitmask = 0, |
585 | .CP0_LLAddr_shift = 0, | |
c9c1a064 | 586 | .SYNCI_Step = 32, |
a1daafd8 | 587 | .CCRes = 1, |
ead9360e | 588 | .CP0_Status_rw_bitmask = 0x36FBFFFF, |
6958549d | 589 | /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ |
c9c1a064 | 590 | .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
5a5012ec | 591 | (1 << FCR0_D) | (1 << FCR0_S) | |
c9c1a064 | 592 | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
599bc5e8 AM |
593 | .CP1_fcr31 = 0, |
594 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
e034e2c3 | 595 | .SEGBITS = 40, |
6d35524c | 596 | .PABITS = 36, |
e189e748 | 597 | .insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
6d35524c | 598 | .mmu_type = MMU_TYPE_R4000, |
33d68b5f | 599 | }, |
d2123ead | 600 | { |
6958549d | 601 | /* A generic CPU providing MIPS64 Release 2 features. |
d2123ead TS |
602 | FIXME: Eventually this should be replaced by a real CPU model. */ |
603 | .name = "MIPS64R2-generic", | |
8c89395e | 604 | .CP0_PRid = 0x00010000, |
6d35524c | 605 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
6958549d | 606 | (MMU_TYPE_R4000 << CP0C0_MT), |
d2123ead | 607 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
6958549d AJ |
608 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
609 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | | |
610 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | |
d2123ead | 611 | .CP0_Config2 = MIPS_CONFIG2, |
6d35524c | 612 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), |
2a6e32dd AJ |
613 | .CP0_LLAddr_rw_bitmask = 0, |
614 | .CP0_LLAddr_shift = 0, | |
d2123ead TS |
615 | .SYNCI_Step = 32, |
616 | .CCRes = 2, | |
617 | .CP0_Status_rw_bitmask = 0x36FBFFFF, | |
ea4b07f7 TS |
618 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
619 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | | |
620 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), | |
599bc5e8 AM |
621 | .CP1_fcr31 = 0, |
622 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
6d35524c | 623 | .SEGBITS = 42, |
6d35524c | 624 | .PABITS = 36, |
d2123ead | 625 | .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, |
6d35524c | 626 | .mmu_type = MMU_TYPE_R4000, |
d2123ead | 627 | }, |
36b86e0d MR |
628 | { |
629 | .name = "5KEc", | |
630 | .CP0_PRid = 0x00018900, | |
631 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | | |
632 | (MMU_TYPE_R4000 << CP0C0_MT), | |
633 | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | | |
634 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | | |
635 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | | |
636 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | |
637 | .CP0_Config2 = MIPS_CONFIG2, | |
638 | .CP0_Config3 = MIPS_CONFIG3, | |
639 | .CP0_LLAddr_rw_bitmask = 0, | |
640 | .CP0_LLAddr_shift = 4, | |
641 | .SYNCI_Step = 32, | |
642 | .CCRes = 2, | |
196a7958 | 643 | .CP0_Status_rw_bitmask = 0x12F8FFFF, |
36b86e0d MR |
644 | .SEGBITS = 42, |
645 | .PABITS = 36, | |
646 | .insn_flags = CPU_MIPS64R2, | |
647 | .mmu_type = MMU_TYPE_R4000, | |
648 | }, | |
649 | { | |
650 | .name = "5KEf", | |
651 | .CP0_PRid = 0x00018900, | |
652 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | | |
653 | (MMU_TYPE_R4000 << CP0C0_MT), | |
654 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | | |
655 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | | |
656 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | | |
657 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | |
658 | .CP0_Config2 = MIPS_CONFIG2, | |
659 | .CP0_Config3 = MIPS_CONFIG3, | |
660 | .CP0_LLAddr_rw_bitmask = 0, | |
661 | .CP0_LLAddr_shift = 4, | |
662 | .SYNCI_Step = 32, | |
663 | .CCRes = 2, | |
664 | .CP0_Status_rw_bitmask = 0x36F8FFFF, | |
665 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | | |
666 | (1 << FCR0_D) | (1 << FCR0_S) | | |
667 | (0x89 << FCR0_PRID) | (0x0 << FCR0_REV), | |
668 | .SEGBITS = 42, | |
669 | .PABITS = 36, | |
670 | .insn_flags = CPU_MIPS64R2, | |
671 | .mmu_type = MMU_TYPE_R4000, | |
672 | }, | |
a773cc79 LA |
673 | { |
674 | /* A generic CPU supporting MIPS64 Release 6 ISA. | |
be3a8c53 | 675 | FIXME: Support IEEE 754-2008 FP. |
a773cc79 LA |
676 | Eventually this should be replaced by a real CPU model. */ |
677 | .name = "MIPS64R6-generic", | |
678 | .CP0_PRid = 0x00010000, | |
679 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | | |
680 | (MMU_TYPE_R4000 << CP0C0_MT), | |
681 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | | |
682 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | | |
683 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | | |
684 | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | |
685 | .CP0_Config2 = MIPS_CONFIG2, | |
a9a95061 LA |
686 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | |
687 | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | | |
4dc89b78 YK |
688 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | |
689 | (1 << CP0C3_RXI) | (1 << CP0C3_LPA), | |
690 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | | |
691 | (0xfc << CP0C4_KScrExist), | |
01bc435b YK |
692 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | |
693 | (1 << CP0C5_LLB), | |
4dc89b78 YK |
694 | .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | |
695 | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), | |
a773cc79 LA |
696 | .CP0_LLAddr_rw_bitmask = 0, |
697 | .CP0_LLAddr_shift = 0, | |
698 | .SYNCI_Step = 32, | |
699 | .CCRes = 2, | |
700 | .CP0_Status_rw_bitmask = 0x30D8FFFF, | |
2d9e48bc LA |
701 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | |
702 | (1U << CP0PG_RIE), | |
6773f9b6 | 703 | .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), |
ba5c79f2 LA |
704 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
705 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | | |
706 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), | |
707 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), | |
599bc5e8 | 708 | .CP1_fcr31_rw_bitmask = 0x0103FFFF, |
4dc89b78 | 709 | .SEGBITS = 48, |
6773f9b6 | 710 | .PABITS = 48, |
4dc89b78 | 711 | .insn_flags = CPU_MIPS64R6 | ASE_MSA, |
a773cc79 LA |
712 | .mmu_type = MMU_TYPE_R4000, |
713 | }, | |
5bc6fba8 HC |
714 | { |
715 | .name = "Loongson-2E", | |
716 | .CP0_PRid = 0x6302, | |
6225a4a0 MR |
717 | /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ |
718 | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | | |
719 | (0x1<<5) | (0x1<<4) | (0x1<<1), | |
720 | /* Note: Config1 is only used internally, | |
721 | Loongson-2E has only Config0. */ | |
5bc6fba8 HC |
722 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
723 | .SYNCI_Step = 16, | |
724 | .CCRes = 2, | |
725 | .CP0_Status_rw_bitmask = 0x35D0FFFF, | |
726 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), | |
599bc5e8 AM |
727 | .CP1_fcr31 = 0, |
728 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
5bc6fba8 HC |
729 | .SEGBITS = 40, |
730 | .PABITS = 40, | |
731 | .insn_flags = CPU_LOONGSON2E, | |
732 | .mmu_type = MMU_TYPE_R4000, | |
733 | }, | |
734 | { | |
6225a4a0 MR |
735 | .name = "Loongson-2F", |
736 | .CP0_PRid = 0x6303, | |
737 | /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ | |
738 | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | | |
739 | (0x1<<5) | (0x1<<4) | (0x1<<1), | |
740 | /* Note: Config1 is only used internally, | |
741 | Loongson-2F has only Config0. */ | |
742 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), | |
743 | .SYNCI_Step = 16, | |
744 | .CCRes = 2, | |
745 | .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */ | |
746 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), | |
599bc5e8 AM |
747 | .CP1_fcr31 = 0, |
748 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
6225a4a0 MR |
749 | .SEGBITS = 40, |
750 | .PABITS = 40, | |
751 | .insn_flags = CPU_LOONGSON2F, | |
752 | .mmu_type = MMU_TYPE_R4000, | |
5bc6fba8 | 753 | }, |
af13ae03 JL |
754 | { |
755 | /* A generic CPU providing MIPS64 ASE DSP 2 features. | |
756 | FIXME: Eventually this should be replaced by a real CPU model. */ | |
757 | .name = "mips64dspr2", | |
758 | .CP0_PRid = 0x00010000, | |
759 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | | |
760 | (MMU_TYPE_R4000 << CP0C0_MT), | |
761 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | | |
762 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | | |
763 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | | |
764 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), | |
765 | .CP0_Config2 = MIPS_CONFIG2, | |
e30614d5 MR |
766 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | |
767 | (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), | |
af13ae03 JL |
768 | .CP0_LLAddr_rw_bitmask = 0, |
769 | .CP0_LLAddr_shift = 0, | |
770 | .SYNCI_Step = 32, | |
771 | .CCRes = 2, | |
772 | .CP0_Status_rw_bitmask = 0x37FBFFFF, | |
773 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | | |
774 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | | |
775 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), | |
599bc5e8 AM |
776 | .CP1_fcr31 = 0, |
777 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, | |
af13ae03 | 778 | .SEGBITS = 42, |
af13ae03 JL |
779 | .PABITS = 36, |
780 | .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, | |
781 | .mmu_type = MMU_TYPE_R4000, | |
782 | }, | |
5bc6fba8 | 783 | |
33d68b5f TS |
784 | #endif |
785 | }; | |
786 | ||
c227f099 | 787 | static const mips_def_t *cpu_mips_find_by_name (const char *name) |
33d68b5f | 788 | { |
aaed909a | 789 | int i; |
33d68b5f | 790 | |
b1503cda | 791 | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
33d68b5f | 792 | if (strcasecmp(name, mips_defs[i].name) == 0) { |
aaed909a | 793 | return &mips_defs[i]; |
33d68b5f TS |
794 | } |
795 | } | |
aaed909a | 796 | return NULL; |
33d68b5f TS |
797 | } |
798 | ||
9a78eead | 799 | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf) |
33d68b5f TS |
800 | { |
801 | int i; | |
802 | ||
b1503cda | 803 | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
33d68b5f TS |
804 | (*cpu_fprintf)(f, "MIPS '%s'\n", |
805 | mips_defs[i].name); | |
806 | } | |
807 | } | |
808 | ||
f8a6ec58 | 809 | #ifndef CONFIG_USER_ONLY |
c227f099 | 810 | static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
29929e34 | 811 | { |
ead9360e TS |
812 | env->tlb->nb_tlb = 1; |
813 | env->tlb->map_address = &no_mmu_map_address; | |
29929e34 TS |
814 | } |
815 | ||
c227f099 | 816 | static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
29929e34 | 817 | { |
ead9360e TS |
818 | env->tlb->nb_tlb = 1; |
819 | env->tlb->map_address = &fixed_mmu_map_address; | |
29929e34 TS |
820 | } |
821 | ||
c227f099 | 822 | static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
29929e34 | 823 | { |
ead9360e TS |
824 | env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
825 | env->tlb->map_address = &r4k_map_address; | |
c01fccd2 AJ |
826 | env->tlb->helper_tlbwi = r4k_helper_tlbwi; |
827 | env->tlb->helper_tlbwr = r4k_helper_tlbwr; | |
828 | env->tlb->helper_tlbp = r4k_helper_tlbp; | |
829 | env->tlb->helper_tlbr = r4k_helper_tlbr; | |
9456c2fb LA |
830 | env->tlb->helper_tlbinv = r4k_helper_tlbinv; |
831 | env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; | |
ead9360e TS |
832 | } |
833 | ||
c227f099 | 834 | static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |
ead9360e | 835 | { |
a47dddd7 AF |
836 | MIPSCPU *cpu = mips_env_get_cpu(env); |
837 | ||
7267c094 | 838 | env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); |
ead9360e | 839 | |
6d35524c TS |
840 | switch (def->mmu_type) { |
841 | case MMU_TYPE_NONE: | |
ead9360e TS |
842 | no_mmu_init(env, def); |
843 | break; | |
6d35524c | 844 | case MMU_TYPE_R4000: |
ead9360e TS |
845 | r4k_mmu_init(env, def); |
846 | break; | |
6d35524c | 847 | case MMU_TYPE_FMT: |
ead9360e TS |
848 | fixed_mmu_init(env, def); |
849 | break; | |
6d35524c TS |
850 | case MMU_TYPE_R3000: |
851 | case MMU_TYPE_R6000: | |
852 | case MMU_TYPE_R8000: | |
ead9360e | 853 | default: |
a47dddd7 | 854 | cpu_abort(CPU(cpu), "MMU type not supported\n"); |
ead9360e | 855 | } |
29929e34 | 856 | } |
f8a6ec58 | 857 | #endif /* CONFIG_USER_ONLY */ |
29929e34 | 858 | |
c227f099 | 859 | static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
ead9360e | 860 | { |
f01be154 TS |
861 | int i; |
862 | ||
863 | for (i = 0; i < MIPS_FPU_MAX; i++) | |
864 | env->fpus[i].fcr0 = def->CP1_fcr0; | |
ead9360e | 865 | |
f01be154 | 866 | memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
ead9360e TS |
867 | } |
868 | ||
c227f099 | 869 | static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
ead9360e | 870 | { |
7267c094 | 871 | env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); |
ead9360e TS |
872 | |
873 | /* MVPConf1 implemented, TLB sharable, no gating storage support, | |
874 | programmable cache partitioning implemented, number of allocatable | |
875 | and sharable TLB entries, MVP has allocatable TCs, 2 VPEs | |
876 | implemented, 5 TCs implemented. */ | |
f45cb2f4 | 877 | env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
ead9360e | 878 | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
ead9360e TS |
879 | // TODO: actually do 2 VPEs. |
880 | // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | | |
881 | // (0x04 << CP0MVPC0_PTC); | |
882 | (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | | |
1dab005a | 883 | (0x00 << CP0MVPC0_PTC); |
932e71cd | 884 | #if !defined(CONFIG_USER_ONLY) |
0eaef5aa | 885 | /* Usermode has no TLB support */ |
932e71cd AJ |
886 | env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
887 | #endif | |
0eaef5aa | 888 | |
ead9360e TS |
889 | /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, |
890 | no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ | |
f45cb2f4 | 891 | env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
ead9360e TS |
892 | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
893 | (0x1 << CP0MVPC1_PCP1); | |
894 | } | |
863f264d YK |
895 | |
896 | static void msa_reset(CPUMIPSState *env) | |
897 | { | |
898 | #ifdef CONFIG_USER_ONLY | |
899 | /* MSA access enabled */ | |
900 | env->CP0_Config5 |= 1 << CP0C5_MSAEn; | |
901 | env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); | |
902 | #endif | |
903 | ||
904 | /* MSA CSR: | |
905 | - non-signaling floating point exception mode off (NX bit is 0) | |
906 | - Cause, Enables, and Flags are all 0 | |
907 | - round to nearest / ties to even (RM bits are 0) */ | |
908 | env->active_tc.msacsr = 0; | |
909 | ||
64451111 LA |
910 | restore_msa_fp_status(env); |
911 | ||
863f264d YK |
912 | /* tininess detected after rounding.*/ |
913 | set_float_detect_tininess(float_tininess_after_rounding, | |
914 | &env->active_tc.msa_fp_status); | |
915 | ||
916 | /* clear float_status exception flags */ | |
917 | set_float_exception_flags(0, &env->active_tc.msa_fp_status); | |
918 | ||
863f264d YK |
919 | /* clear float_status nan mode */ |
920 | set_default_nan_mode(0, &env->active_tc.msa_fp_status); | |
af39bc8c | 921 | |
40bd6dd4 AM |
922 | /* set proper signanling bit meaning ("1" means "quiet") */ |
923 | set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); | |
863f264d | 924 | } |