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525bd324 AG |
1 | /* |
2 | * Moxie helper routines. | |
3 | * | |
4 | * Copyright (c) 2008, 2009, 2010, 2013 Anthony Green | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include <stdio.h> | |
21 | #include <string.h> | |
22 | #include <assert.h> | |
23 | ||
24 | #include "config.h" | |
25 | #include "cpu.h" | |
26 | #include "mmu.h" | |
27 | #include "exec/exec-all.h" | |
b1669e5e | 28 | #include "exec/softmmu_exec.h" |
525bd324 AG |
29 | #include "qemu/host-utils.h" |
30 | #include "helper.h" | |
31 | ||
32 | #define MMUSUFFIX _mmu | |
33 | ||
34 | #define SHIFT 0 | |
35 | #include "exec/softmmu_template.h" | |
36 | ||
37 | #define SHIFT 1 | |
38 | #include "exec/softmmu_template.h" | |
39 | ||
40 | #define SHIFT 2 | |
41 | #include "exec/softmmu_template.h" | |
42 | ||
43 | #define SHIFT 3 | |
44 | #include "exec/softmmu_template.h" | |
45 | ||
46 | /* Try to fill the TLB and return an exception if error. If retaddr is | |
47 | NULL, it means that the function was called in C code (i.e. not | |
48 | from generated code or from helper.c) */ | |
d5a11fef | 49 | void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, |
525bd324 AG |
50 | uintptr_t retaddr) |
51 | { | |
d5a11fef AF |
52 | MoxieCPU *cpu = MOXIE_CPU(cs); |
53 | CPUMoxieState *env = &cpu->env; | |
525bd324 AG |
54 | int ret; |
55 | ||
d5a11fef | 56 | ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); |
525bd324 AG |
57 | if (unlikely(ret)) { |
58 | if (retaddr) { | |
59 | cpu_restore_state(env, retaddr); | |
60 | } | |
61 | } | |
5638d180 | 62 | cpu_loop_exit(cs); |
525bd324 AG |
63 | } |
64 | ||
65 | void helper_raise_exception(CPUMoxieState *env, int ex) | |
66 | { | |
27103424 AF |
67 | CPUState *cs = CPU(moxie_env_get_cpu(env)); |
68 | ||
69 | cs->exception_index = ex; | |
525bd324 AG |
70 | /* Stash the exception type. */ |
71 | env->sregs[2] = ex; | |
72 | /* Stash the address where the exception occurred. */ | |
73 | cpu_restore_state(env, GETPC()); | |
74 | env->sregs[5] = env->pc; | |
75 | /* Jump the the exception handline routine. */ | |
76 | env->pc = env->sregs[1]; | |
5638d180 | 77 | cpu_loop_exit(cs); |
525bd324 AG |
78 | } |
79 | ||
80 | uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b) | |
81 | { | |
82 | if (unlikely(b == 0)) { | |
83 | helper_raise_exception(env, MOXIE_EX_DIV0); | |
84 | return 0; | |
85 | } | |
86 | if (unlikely(a == INT_MIN && b == -1)) { | |
87 | return INT_MIN; | |
88 | } | |
89 | ||
90 | return (int32_t)a / (int32_t)b; | |
91 | } | |
92 | ||
93 | uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b) | |
94 | { | |
95 | if (unlikely(b == 0)) { | |
96 | helper_raise_exception(env, MOXIE_EX_DIV0); | |
97 | return 0; | |
98 | } | |
99 | return a / b; | |
100 | } | |
101 | ||
102 | void helper_debug(CPUMoxieState *env) | |
103 | { | |
27103424 AF |
104 | CPUState *cs = CPU(moxie_env_get_cpu(env)); |
105 | ||
106 | cs->exception_index = EXCP_DEBUG; | |
5638d180 | 107 | cpu_loop_exit(cs); |
525bd324 AG |
108 | } |
109 | ||
110 | #if defined(CONFIG_USER_ONLY) | |
111 | ||
7510454e | 112 | void moxie_cpu_do_interrupt(CPUState *cs) |
525bd324 | 113 | { |
27103424 AF |
114 | CPUState *cs = CPU(moxie_env_get_cpu(env)); |
115 | ||
116 | cs->exception_index = -1; | |
525bd324 AG |
117 | } |
118 | ||
7510454e | 119 | int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
525bd324 AG |
120 | int rw, int mmu_idx) |
121 | { | |
7510454e | 122 | MoxieCPU *cpu = MOXIE_CPU(cs); |
878096ee | 123 | |
27103424 | 124 | cs->exception_index = 0xaa; |
7510454e AF |
125 | cpu->env.debug1 = address; |
126 | cpu_dump_state(cs, stderr, fprintf, 0); | |
525bd324 AG |
127 | return 1; |
128 | } | |
129 | ||
525bd324 AG |
130 | #else /* !CONFIG_USER_ONLY */ |
131 | ||
7510454e | 132 | int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address, |
525bd324 AG |
133 | int rw, int mmu_idx) |
134 | { | |
7510454e AF |
135 | MoxieCPU *cpu = MOXIE_CPU(cs); |
136 | CPUMoxieState *env = &cpu->env; | |
525bd324 AG |
137 | MoxieMMUResult res; |
138 | int prot, miss; | |
139 | target_ulong phy; | |
140 | int r = 1; | |
141 | ||
142 | address &= TARGET_PAGE_MASK; | |
143 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
144 | miss = moxie_mmu_translate(&res, env, address, rw, mmu_idx); | |
145 | if (miss) { | |
146 | /* handle the miss. */ | |
147 | phy = 0; | |
27103424 | 148 | cs->exception_index = MOXIE_EX_MMU_MISS; |
525bd324 AG |
149 | } else { |
150 | phy = res.phy; | |
151 | r = 0; | |
152 | } | |
153 | tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE); | |
154 | return r; | |
155 | } | |
156 | ||
157 | ||
53574064 | 158 | void moxie_cpu_do_interrupt(CPUState *cs) |
525bd324 | 159 | { |
27103424 | 160 | switch (cs->exception_index) { |
525bd324 AG |
161 | case MOXIE_EX_BREAK: |
162 | break; | |
163 | default: | |
164 | break; | |
165 | } | |
166 | } | |
167 | ||
00b941e5 | 168 | hwaddr moxie_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
525bd324 | 169 | { |
00b941e5 | 170 | MoxieCPU *cpu = MOXIE_CPU(cs); |
525bd324 AG |
171 | uint32_t phy = addr; |
172 | MoxieMMUResult res; | |
173 | int miss; | |
00b941e5 AF |
174 | |
175 | miss = moxie_mmu_translate(&res, &cpu->env, addr, 0, 0); | |
525bd324 AG |
176 | if (!miss) { |
177 | phy = res.phy; | |
178 | } | |
179 | return phy; | |
180 | } | |
181 | #endif |