]> git.proxmox.com Git - mirror_qemu.git/blame - target-ppc/cpu-qom.h
xics: Add xics_find_source()
[mirror_qemu.git] / target-ppc / cpu-qom.h
CommitLineData
1d0cb67d
AF
1/*
2 * QEMU PowerPC CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20#ifndef QEMU_PPC_CPU_QOM_H
21#define QEMU_PPC_CPU_QOM_H
22
14cccb61 23#include "qom/cpu.h"
1d0cb67d
AF
24#include "cpu.h"
25
26#ifdef TARGET_PPC64
27#define TYPE_POWERPC_CPU "powerpc64-cpu"
28#elif defined(TARGET_PPCEMB)
29#define TYPE_POWERPC_CPU "embedded-powerpc-cpu"
30#else
31#define TYPE_POWERPC_CPU "powerpc-cpu"
32#endif
33
34#define POWERPC_CPU_CLASS(klass) \
35 OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
36#define POWERPC_CPU(obj) \
37 OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
38#define POWERPC_CPU_GET_CLASS(obj) \
39 OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
40
d0e39c5d
AF
41typedef struct PowerPCCPU PowerPCCPU;
42
1d0cb67d
AF
43/**
44 * PowerPCCPUClass:
4776ce60 45 * @parent_realize: The parent class' realize handler.
1d0cb67d
AF
46 * @parent_reset: The parent class' reset handler.
47 *
48 * A PowerPC CPU model.
49 */
50typedef struct PowerPCCPUClass {
51 /*< private >*/
52 CPUClass parent_class;
53 /*< public >*/
54
4776ce60 55 DeviceRealize parent_realize;
1d0cb67d 56 void (*parent_reset)(CPUState *cpu);
2985b86b 57
cfe34f44 58 uint32_t pvr;
3bc9ccc0 59 uint32_t pvr_mask;
1a68b714 60 uint64_t pcr_mask;
cfe34f44
AF
61 uint32_t svr;
62 uint64_t insns_flags;
63 uint64_t insns_flags2;
64 uint64_t msr_mask;
65 powerpc_mmu_t mmu_model;
66 powerpc_excp_t excp_model;
67 powerpc_input_t bus_model;
68 uint32_t flags;
69 int bfd_mach;
0cbad81f 70 uint32_t l1_dcache_size, l1_icache_size;
cfe34f44
AF
71#if defined(TARGET_PPC64)
72 const struct ppc_segment_page_sizes *sps;
73#endif
74 void (*init_proc)(CPUPPCState *env);
75 int (*check_pow)(CPUPPCState *env);
b632a148 76#if defined(CONFIG_SOFTMMU)
d0e39c5d 77 int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
b632a148
DG
78 int mmu_idx);
79#endif
382d2db6 80 bool (*interrupts_big_endian)(PowerPCCPU *cpu);
1d0cb67d
AF
81} PowerPCCPUClass;
82
83/**
84 * PowerPCCPU:
85 * @env: #CPUPPCState
0ce470cd 86 * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
8dfa3a5e 87 * @max_compat: Maximal supported logical PVR from the command line
6d9412ea 88 * @cpu_version: Current logical PVR, zero if in "raw" mode
1d0cb67d
AF
89 *
90 * A PowerPC CPU.
91 */
d0e39c5d 92struct PowerPCCPU {
1d0cb67d
AF
93 /*< private >*/
94 CPUState parent_obj;
95 /*< public >*/
96
97 CPUPPCState env;
0ce470cd 98 int cpu_dt_id;
8dfa3a5e 99 uint32_t max_compat;
6d9412ea 100 uint32_t cpu_version;
d0e39c5d 101};
1d0cb67d
AF
102
103static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
104{
6e42be7c 105 return container_of(env, PowerPCCPU, env);
1d0cb67d
AF
106}
107
108#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
109
fadf9825 110#define ENV_OFFSET offsetof(PowerPCCPU, env)
2985b86b 111
fadf9825 112PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
3bc9ccc0 113PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1d0cb67d 114
97a8ea5a 115void ppc_cpu_do_interrupt(CPUState *cpu);
878096ee
AF
116void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
117 int flags);
118void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
119 fprintf_function cpu_fprintf, int flags);
00b941e5 120hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
5b50e790 121int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
b3cad3ab 122int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
5b50e790 123int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
b3cad3ab 124int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
e62fbc54
AK
125int ppc64_cpu_write_elf64_qemunote(WriteCoreDumpFunction f,
126 CPUState *cpu, void *opaque);
127int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
128 int cpuid, void *opaque);
a90db158
AK
129#ifndef CONFIG_USER_ONLY
130extern const struct VMStateDescription vmstate_ppc_cpu;
98a8b524
AK
131
132typedef struct PPCTimebase {
133 uint64_t guest_timebase;
134 int64_t time_of_the_day_ns;
135} PPCTimebase;
136
137extern const struct VMStateDescription vmstate_ppc_timebase;
138
139#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \
140 .name = (stringify(_field)), \
141 .version_id = (_version), \
142 .size = sizeof(PPCTimebase), \
143 .vmsd = &vmstate_ppc_timebase, \
144 .flags = VMS_STRUCT, \
145 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \
146}
a90db158
AK
147#endif
148
1d0cb67d 149#endif