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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation cpu definitions for qemu. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
79aceca5 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 FB |
18 | */ |
19 | #if !defined (__CPU_PPC_H__) | |
20 | #define __CPU_PPC_H__ | |
21 | ||
3fc6c082 | 22 | #include "config.h" |
9a78eead | 23 | #include "qemu-common.h" |
3fc6c082 | 24 | |
a4f30719 JM |
25 | //#define PPC_EMULATE_32BITS_HYPV |
26 | ||
76a66253 | 27 | #if defined (TARGET_PPC64) |
3cd7d1dd | 28 | /* PowerPC 64 definitions */ |
d9d7210c | 29 | #define TARGET_LONG_BITS 64 |
35cdaad6 | 30 | #define TARGET_PAGE_BITS 12 |
3cd7d1dd | 31 | |
52705890 RH |
32 | /* Note that the official physical address space bits is 62-M where M |
33 | is implementation dependent. I've not looked up M for the set of | |
34 | cpus we emulate at the system level. */ | |
35 | #define TARGET_PHYS_ADDR_SPACE_BITS 62 | |
36 | ||
37 | /* Note that the PPC environment architecture talks about 80 bit virtual | |
38 | addresses, with segmentation. Obviously that's not all visible to a | |
39 | single process, which is all we're concerned with here. */ | |
40 | #ifdef TARGET_ABI32 | |
41 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
42 | #else | |
43 | # define TARGET_VIRT_ADDR_SPACE_BITS 64 | |
44 | #endif | |
45 | ||
81762d6d DG |
46 | #define TARGET_PAGE_BITS_16M 24 |
47 | ||
3cd7d1dd JM |
48 | #else /* defined (TARGET_PPC64) */ |
49 | /* PowerPC 32 definitions */ | |
d9d7210c | 50 | #define TARGET_LONG_BITS 32 |
3cd7d1dd JM |
51 | |
52 | #if defined(TARGET_PPCEMB) | |
53 | /* Specific definitions for PowerPC embedded */ | |
54 | /* BookE have 36 bits physical address space */ | |
3cd7d1dd JM |
55 | #if defined(CONFIG_USER_ONLY) |
56 | /* It looks like a lot of Linux programs assume page size | |
57 | * is 4kB long. This is evil, but we have to deal with it... | |
58 | */ | |
35cdaad6 | 59 | #define TARGET_PAGE_BITS 12 |
3cd7d1dd JM |
60 | #else /* defined(CONFIG_USER_ONLY) */ |
61 | /* Pages can be 1 kB small */ | |
62 | #define TARGET_PAGE_BITS 10 | |
63 | #endif /* defined(CONFIG_USER_ONLY) */ | |
64 | #else /* defined(TARGET_PPCEMB) */ | |
65 | /* "standard" PowerPC 32 definitions */ | |
66 | #define TARGET_PAGE_BITS 12 | |
67 | #endif /* defined(TARGET_PPCEMB) */ | |
68 | ||
52705890 RH |
69 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
70 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 | |
71 | ||
3cd7d1dd | 72 | #endif /* defined (TARGET_PPC64) */ |
3cf1e035 | 73 | |
c2764719 PB |
74 | #define CPUState struct CPUPPCState |
75 | ||
79aceca5 FB |
76 | #include "cpu-defs.h" |
77 | ||
79aceca5 FB |
78 | #include <setjmp.h> |
79 | ||
4ecc3190 FB |
80 | #include "softfloat.h" |
81 | ||
1fddef4b FB |
82 | #define TARGET_HAS_ICE 1 |
83 | ||
7f70c937 | 84 | #if defined (TARGET_PPC64) |
76a66253 JM |
85 | #define ELF_MACHINE EM_PPC64 |
86 | #else | |
87 | #define ELF_MACHINE EM_PPC | |
88 | #endif | |
9042c0e2 | 89 | |
3fc6c082 | 90 | /*****************************************************************************/ |
a750fc0b | 91 | /* MMU model */ |
c227f099 AL |
92 | typedef enum powerpc_mmu_t powerpc_mmu_t; |
93 | enum powerpc_mmu_t { | |
add78955 | 94 | POWERPC_MMU_UNKNOWN = 0x00000000, |
a750fc0b | 95 | /* Standard 32 bits PowerPC MMU */ |
add78955 | 96 | POWERPC_MMU_32B = 0x00000001, |
a750fc0b | 97 | /* PowerPC 6xx MMU with software TLB */ |
add78955 | 98 | POWERPC_MMU_SOFT_6xx = 0x00000002, |
a750fc0b | 99 | /* PowerPC 74xx MMU with software TLB */ |
add78955 | 100 | POWERPC_MMU_SOFT_74xx = 0x00000003, |
a750fc0b | 101 | /* PowerPC 4xx MMU with software TLB */ |
add78955 | 102 | POWERPC_MMU_SOFT_4xx = 0x00000004, |
a750fc0b | 103 | /* PowerPC 4xx MMU with software TLB and zones protections */ |
add78955 | 104 | POWERPC_MMU_SOFT_4xx_Z = 0x00000005, |
b4095fed | 105 | /* PowerPC MMU in real mode only */ |
add78955 | 106 | POWERPC_MMU_REAL = 0x00000006, |
b4095fed | 107 | /* Freescale MPC8xx MMU model */ |
add78955 | 108 | POWERPC_MMU_MPC8xx = 0x00000007, |
a750fc0b | 109 | /* BookE MMU model */ |
add78955 | 110 | POWERPC_MMU_BOOKE = 0x00000008, |
a750fc0b | 111 | /* BookE FSL MMU model */ |
add78955 | 112 | POWERPC_MMU_BOOKE_FSL = 0x00000009, |
faadf50e | 113 | /* PowerPC 601 MMU model (specific BATs format) */ |
add78955 | 114 | POWERPC_MMU_601 = 0x0000000A, |
00af685f | 115 | #if defined(TARGET_PPC64) |
add78955 | 116 | #define POWERPC_MMU_64 0x00010000 |
cdaee006 | 117 | #define POWERPC_MMU_1TSEG 0x00020000 |
12de9a39 | 118 | /* 64 bits PowerPC MMU */ |
add78955 JM |
119 | POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, |
120 | /* 620 variant (no segment exceptions) */ | |
121 | POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002, | |
9d52e907 DG |
122 | /* Architecture 2.06 variant */ |
123 | POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003, | |
00af685f | 124 | #endif /* defined(TARGET_PPC64) */ |
3fc6c082 FB |
125 | }; |
126 | ||
127 | /*****************************************************************************/ | |
a750fc0b | 128 | /* Exception model */ |
c227f099 AL |
129 | typedef enum powerpc_excp_t powerpc_excp_t; |
130 | enum powerpc_excp_t { | |
a750fc0b | 131 | POWERPC_EXCP_UNKNOWN = 0, |
3fc6c082 | 132 | /* Standard PowerPC exception model */ |
a750fc0b | 133 | POWERPC_EXCP_STD, |
2662a059 | 134 | /* PowerPC 40x exception model */ |
a750fc0b | 135 | POWERPC_EXCP_40x, |
2662a059 | 136 | /* PowerPC 601 exception model */ |
a750fc0b | 137 | POWERPC_EXCP_601, |
2662a059 | 138 | /* PowerPC 602 exception model */ |
a750fc0b | 139 | POWERPC_EXCP_602, |
2662a059 | 140 | /* PowerPC 603 exception model */ |
a750fc0b JM |
141 | POWERPC_EXCP_603, |
142 | /* PowerPC 603e exception model */ | |
143 | POWERPC_EXCP_603E, | |
144 | /* PowerPC G2 exception model */ | |
145 | POWERPC_EXCP_G2, | |
2662a059 | 146 | /* PowerPC 604 exception model */ |
a750fc0b | 147 | POWERPC_EXCP_604, |
2662a059 | 148 | /* PowerPC 7x0 exception model */ |
a750fc0b | 149 | POWERPC_EXCP_7x0, |
2662a059 | 150 | /* PowerPC 7x5 exception model */ |
a750fc0b | 151 | POWERPC_EXCP_7x5, |
2662a059 | 152 | /* PowerPC 74xx exception model */ |
a750fc0b | 153 | POWERPC_EXCP_74xx, |
2662a059 | 154 | /* BookE exception model */ |
a750fc0b | 155 | POWERPC_EXCP_BOOKE, |
00af685f JM |
156 | #if defined(TARGET_PPC64) |
157 | /* PowerPC 970 exception model */ | |
158 | POWERPC_EXCP_970, | |
9d52e907 DG |
159 | /* POWER7 exception model */ |
160 | POWERPC_EXCP_POWER7, | |
00af685f | 161 | #endif /* defined(TARGET_PPC64) */ |
a750fc0b JM |
162 | }; |
163 | ||
e1833e1f JM |
164 | /*****************************************************************************/ |
165 | /* Exception vectors definitions */ | |
166 | enum { | |
167 | POWERPC_EXCP_NONE = -1, | |
168 | /* The 64 first entries are used by the PowerPC embedded specification */ | |
169 | POWERPC_EXCP_CRITICAL = 0, /* Critical input */ | |
170 | POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ | |
171 | POWERPC_EXCP_DSI = 2, /* Data storage exception */ | |
172 | POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ | |
173 | POWERPC_EXCP_EXTERNAL = 4, /* External input */ | |
174 | POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ | |
175 | POWERPC_EXCP_PROGRAM = 6, /* Program exception */ | |
176 | POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ | |
177 | POWERPC_EXCP_SYSCALL = 8, /* System call exception */ | |
178 | POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ | |
179 | POWERPC_EXCP_DECR = 10, /* Decrementer exception */ | |
180 | POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ | |
181 | POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ | |
b4095fed JM |
182 | POWERPC_EXCP_DTLB = 13, /* Data TLB miss */ |
183 | POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */ | |
e1833e1f JM |
184 | POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ |
185 | /* Vectors 16 to 31 are reserved */ | |
e1833e1f JM |
186 | POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ |
187 | POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ | |
188 | POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ | |
189 | POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ | |
190 | POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ | |
191 | POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ | |
e1833e1f JM |
192 | /* Vectors 38 to 63 are reserved */ |
193 | /* Exceptions defined in the PowerPC server specification */ | |
194 | POWERPC_EXCP_RESET = 64, /* System reset exception */ | |
e1833e1f JM |
195 | POWERPC_EXCP_DSEG = 65, /* Data segment exception */ |
196 | POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ | |
e1833e1f | 197 | POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ |
e1833e1f | 198 | POWERPC_EXCP_TRACE = 68, /* Trace exception */ |
e1833e1f JM |
199 | POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ |
200 | POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ | |
201 | POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ | |
202 | POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ | |
e1833e1f JM |
203 | POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ |
204 | /* 40x specific exceptions */ | |
205 | POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ | |
206 | /* 601 specific exceptions */ | |
207 | POWERPC_EXCP_IO = 75, /* IO error exception */ | |
208 | POWERPC_EXCP_RUNM = 76, /* Run mode exception */ | |
209 | /* 602 specific exceptions */ | |
210 | POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ | |
211 | /* 602/603 specific exceptions */ | |
b4095fed | 212 | POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */ |
e1833e1f JM |
213 | POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ |
214 | POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ | |
215 | /* Exceptions available on most PowerPC */ | |
216 | POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ | |
b4095fed JM |
217 | POWERPC_EXCP_DABR = 82, /* Data address breakpoint */ |
218 | POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */ | |
219 | POWERPC_EXCP_SMI = 84, /* System management interrupt */ | |
220 | POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */ | |
e1833e1f | 221 | /* 7xx/74xx specific exceptions */ |
b4095fed | 222 | POWERPC_EXCP_THERM = 86, /* Thermal interrupt */ |
e1833e1f | 223 | /* 74xx specific exceptions */ |
b4095fed | 224 | POWERPC_EXCP_VPUA = 87, /* Vector assist exception */ |
e1833e1f | 225 | /* 970FX specific exceptions */ |
b4095fed JM |
226 | POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */ |
227 | POWERPC_EXCP_MAINT = 89, /* Maintenance exception */ | |
228 | /* Freescale embeded cores specific exceptions */ | |
229 | POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */ | |
230 | POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */ | |
231 | POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */ | |
232 | POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ | |
e1833e1f JM |
233 | /* EOL */ |
234 | POWERPC_EXCP_NB = 96, | |
235 | /* Qemu exceptions: used internally during code translation */ | |
236 | POWERPC_EXCP_STOP = 0x200, /* stop translation */ | |
237 | POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ | |
238 | /* Qemu exceptions: special cases we want to stop translation */ | |
239 | POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ | |
240 | POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ | |
4425265b | 241 | POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */ |
e1833e1f JM |
242 | }; |
243 | ||
e1833e1f JM |
244 | /* Exceptions error codes */ |
245 | enum { | |
246 | /* Exception subtypes for POWERPC_EXCP_ALIGN */ | |
247 | POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ | |
248 | POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ | |
249 | POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ | |
250 | POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ | |
251 | POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ | |
252 | POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ | |
253 | /* Exception subtypes for POWERPC_EXCP_PROGRAM */ | |
254 | /* FP exceptions */ | |
255 | POWERPC_EXCP_FP = 0x10, | |
256 | POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ | |
257 | POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ | |
258 | POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ | |
259 | POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ | |
7c58044c | 260 | POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */ |
e1833e1f JM |
261 | POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
262 | POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ | |
263 | POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ | |
264 | POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ | |
265 | POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ | |
266 | POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ | |
267 | POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ | |
268 | POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ | |
269 | /* Invalid instruction */ | |
270 | POWERPC_EXCP_INVAL = 0x20, | |
271 | POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ | |
272 | POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ | |
273 | POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ | |
274 | POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ | |
275 | /* Privileged instruction */ | |
276 | POWERPC_EXCP_PRIV = 0x30, | |
277 | POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ | |
278 | POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ | |
279 | /* Trap */ | |
280 | POWERPC_EXCP_TRAP = 0x40, | |
281 | }; | |
282 | ||
a750fc0b JM |
283 | /*****************************************************************************/ |
284 | /* Input pins model */ | |
c227f099 AL |
285 | typedef enum powerpc_input_t powerpc_input_t; |
286 | enum powerpc_input_t { | |
a750fc0b | 287 | PPC_FLAGS_INPUT_UNKNOWN = 0, |
2662a059 | 288 | /* PowerPC 6xx bus */ |
a750fc0b | 289 | PPC_FLAGS_INPUT_6xx, |
2662a059 | 290 | /* BookE bus */ |
a750fc0b JM |
291 | PPC_FLAGS_INPUT_BookE, |
292 | /* PowerPC 405 bus */ | |
293 | PPC_FLAGS_INPUT_405, | |
2662a059 | 294 | /* PowerPC 970 bus */ |
a750fc0b | 295 | PPC_FLAGS_INPUT_970, |
9d52e907 DG |
296 | /* PowerPC POWER7 bus */ |
297 | PPC_FLAGS_INPUT_POWER7, | |
a750fc0b JM |
298 | /* PowerPC 401 bus */ |
299 | PPC_FLAGS_INPUT_401, | |
b4095fed JM |
300 | /* Freescale RCPU bus */ |
301 | PPC_FLAGS_INPUT_RCPU, | |
3fc6c082 FB |
302 | }; |
303 | ||
a750fc0b | 304 | #define PPC_INPUT(env) (env->bus_model) |
3fc6c082 | 305 | |
be147d08 | 306 | /*****************************************************************************/ |
c227f099 AL |
307 | typedef struct ppc_def_t ppc_def_t; |
308 | typedef struct opc_handler_t opc_handler_t; | |
79aceca5 | 309 | |
3fc6c082 FB |
310 | /*****************************************************************************/ |
311 | /* Types used to describe some PowerPC registers */ | |
312 | typedef struct CPUPPCState CPUPPCState; | |
c227f099 AL |
313 | typedef struct ppc_tb_t ppc_tb_t; |
314 | typedef struct ppc_spr_t ppc_spr_t; | |
315 | typedef struct ppc_dcr_t ppc_dcr_t; | |
316 | typedef union ppc_avr_t ppc_avr_t; | |
317 | typedef union ppc_tlb_t ppc_tlb_t; | |
76a66253 | 318 | |
3fc6c082 | 319 | /* SPR access micro-ops generations callbacks */ |
c227f099 | 320 | struct ppc_spr_t { |
45d827d2 AJ |
321 | void (*uea_read)(void *opaque, int gpr_num, int spr_num); |
322 | void (*uea_write)(void *opaque, int spr_num, int gpr_num); | |
76a66253 | 323 | #if !defined(CONFIG_USER_ONLY) |
45d827d2 AJ |
324 | void (*oea_read)(void *opaque, int gpr_num, int spr_num); |
325 | void (*oea_write)(void *opaque, int spr_num, int gpr_num); | |
326 | void (*hea_read)(void *opaque, int gpr_num, int spr_num); | |
327 | void (*hea_write)(void *opaque, int spr_num, int gpr_num); | |
76a66253 | 328 | #endif |
b55266b5 | 329 | const char *name; |
3fc6c082 FB |
330 | }; |
331 | ||
332 | /* Altivec registers (128 bits) */ | |
c227f099 | 333 | union ppc_avr_t { |
0f6fbcbc | 334 | float32 f[4]; |
a9d9eb8f JM |
335 | uint8_t u8[16]; |
336 | uint16_t u16[8]; | |
337 | uint32_t u32[4]; | |
ab5f265d AJ |
338 | int8_t s8[16]; |
339 | int16_t s16[8]; | |
340 | int32_t s32[4]; | |
a9d9eb8f | 341 | uint64_t u64[2]; |
3fc6c082 | 342 | }; |
9fddaa0c | 343 | |
3c7b48b7 | 344 | #if !defined(CONFIG_USER_ONLY) |
3fc6c082 | 345 | /* Software TLB cache */ |
c227f099 AL |
346 | typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
347 | struct ppc6xx_tlb_t { | |
76a66253 JM |
348 | target_ulong pte0; |
349 | target_ulong pte1; | |
350 | target_ulong EPN; | |
1d0a48fb JM |
351 | }; |
352 | ||
c227f099 AL |
353 | typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
354 | struct ppcemb_tlb_t { | |
355 | target_phys_addr_t RPN; | |
1d0a48fb | 356 | target_ulong EPN; |
76a66253 | 357 | target_ulong PID; |
c55e9aef JM |
358 | target_ulong size; |
359 | uint32_t prot; | |
360 | uint32_t attr; /* Storage attributes */ | |
1d0a48fb JM |
361 | }; |
362 | ||
c227f099 AL |
363 | union ppc_tlb_t { |
364 | ppc6xx_tlb_t tlb6; | |
365 | ppcemb_tlb_t tlbe; | |
3fc6c082 | 366 | }; |
3c7b48b7 | 367 | #endif |
3fc6c082 | 368 | |
bb593904 DG |
369 | #define SDR_32_HTABORG 0xFFFF0000UL |
370 | #define SDR_32_HTABMASK 0x000001FFUL | |
371 | ||
372 | #if defined(TARGET_PPC64) | |
373 | #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL | |
374 | #define SDR_64_HTABSIZE 0x000000000000001FULL | |
375 | #endif /* defined(TARGET_PPC64 */ | |
376 | ||
fda6a0ec DG |
377 | #define HASH_PTE_SIZE_32 8 |
378 | #define HASH_PTE_SIZE_64 16 | |
379 | ||
c227f099 AL |
380 | typedef struct ppc_slb_t ppc_slb_t; |
381 | struct ppc_slb_t { | |
81762d6d DG |
382 | uint64_t esid; |
383 | uint64_t vsid; | |
8eee0af9 BS |
384 | }; |
385 | ||
81762d6d DG |
386 | /* Bits in the SLB ESID word */ |
387 | #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL | |
388 | #define SLB_ESID_V 0x0000000008000000ULL /* valid */ | |
389 | ||
390 | /* Bits in the SLB VSID word */ | |
391 | #define SLB_VSID_SHIFT 12 | |
cdaee006 | 392 | #define SLB_VSID_SHIFT_1T 24 |
81762d6d DG |
393 | #define SLB_VSID_SSIZE_SHIFT 62 |
394 | #define SLB_VSID_B 0xc000000000000000ULL | |
395 | #define SLB_VSID_B_256M 0x0000000000000000ULL | |
cdaee006 | 396 | #define SLB_VSID_B_1T 0x4000000000000000ULL |
81762d6d | 397 | #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL |
256cebe5 | 398 | #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID) |
81762d6d DG |
399 | #define SLB_VSID_KS 0x0000000000000800ULL |
400 | #define SLB_VSID_KP 0x0000000000000400ULL | |
401 | #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */ | |
402 | #define SLB_VSID_L 0x0000000000000100ULL | |
403 | #define SLB_VSID_C 0x0000000000000080ULL /* class */ | |
404 | #define SLB_VSID_LP 0x0000000000000030ULL | |
405 | #define SLB_VSID_ATTR 0x0000000000000FFFULL | |
406 | ||
407 | #define SEGMENT_SHIFT_256M 28 | |
408 | #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1)) | |
409 | ||
cdaee006 DG |
410 | #define SEGMENT_SHIFT_1T 40 |
411 | #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1)) | |
412 | ||
413 | ||
3fc6c082 FB |
414 | /*****************************************************************************/ |
415 | /* Machine state register bits definition */ | |
76a66253 | 416 | #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
bd928eba | 417 | #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ |
3fc6c082 | 418 | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
a4f30719 | 419 | #define MSR_SHV 60 /* hypervisor state hflags */ |
363be49c JM |
420 | #define MSR_CM 31 /* Computation mode for BookE hflags */ |
421 | #define MSR_ICM 30 /* Interrupt computation mode for BookE */ | |
a4f30719 | 422 | #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ |
363be49c | 423 | #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
d26bfc9a JM |
424 | #define MSR_VR 25 /* altivec available x hflags */ |
425 | #define MSR_SPE 25 /* SPE enable for BookE x hflags */ | |
76a66253 JM |
426 | #define MSR_AP 23 /* Access privilege state on 602 hflags */ |
427 | #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ | |
3fc6c082 | 428 | #define MSR_KEY 19 /* key bit on 603e */ |
25ba3a68 | 429 | #define MSR_POW 18 /* Power management */ |
d26bfc9a JM |
430 | #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ |
431 | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ | |
3fc6c082 FB |
432 | #define MSR_ILE 16 /* Interrupt little-endian mode */ |
433 | #define MSR_EE 15 /* External interrupt enable */ | |
76a66253 JM |
434 | #define MSR_PR 14 /* Problem state hflags */ |
435 | #define MSR_FP 13 /* Floating point available hflags */ | |
3fc6c082 | 436 | #define MSR_ME 12 /* Machine check interrupt enable */ |
76a66253 | 437 | #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
d26bfc9a JM |
438 | #define MSR_SE 10 /* Single-step trace enable x hflags */ |
439 | #define MSR_DWE 10 /* Debug wait enable on 405 x */ | |
440 | #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ | |
441 | #define MSR_BE 9 /* Branch trace enable x hflags */ | |
442 | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ | |
76a66253 | 443 | #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
3fc6c082 | 444 | #define MSR_AL 7 /* AL bit on POWER */ |
0411a972 | 445 | #define MSR_EP 6 /* Exception prefix on 601 */ |
3fc6c082 | 446 | #define MSR_IR 5 /* Instruction relocate */ |
3fc6c082 | 447 | #define MSR_DR 4 /* Data relocate */ |
25ba3a68 | 448 | #define MSR_PE 3 /* Protection enable on 403 */ |
d26bfc9a JM |
449 | #define MSR_PX 2 /* Protection exclusive on 403 x */ |
450 | #define MSR_PMM 2 /* Performance monitor mark on POWER x */ | |
451 | #define MSR_RI 1 /* Recoverable interrupt 1 */ | |
452 | #define MSR_LE 0 /* Little-endian mode 1 hflags */ | |
0411a972 JM |
453 | |
454 | #define msr_sf ((env->msr >> MSR_SF) & 1) | |
455 | #define msr_isf ((env->msr >> MSR_ISF) & 1) | |
a4f30719 | 456 | #define msr_shv ((env->msr >> MSR_SHV) & 1) |
0411a972 JM |
457 | #define msr_cm ((env->msr >> MSR_CM) & 1) |
458 | #define msr_icm ((env->msr >> MSR_ICM) & 1) | |
a4f30719 | 459 | #define msr_thv ((env->msr >> MSR_THV) & 1) |
0411a972 JM |
460 | #define msr_ucle ((env->msr >> MSR_UCLE) & 1) |
461 | #define msr_vr ((env->msr >> MSR_VR) & 1) | |
f9320410 | 462 | #define msr_spe ((env->msr >> MSR_SPE) & 1) |
0411a972 JM |
463 | #define msr_ap ((env->msr >> MSR_AP) & 1) |
464 | #define msr_sa ((env->msr >> MSR_SA) & 1) | |
465 | #define msr_key ((env->msr >> MSR_KEY) & 1) | |
466 | #define msr_pow ((env->msr >> MSR_POW) & 1) | |
467 | #define msr_tgpr ((env->msr >> MSR_TGPR) & 1) | |
468 | #define msr_ce ((env->msr >> MSR_CE) & 1) | |
469 | #define msr_ile ((env->msr >> MSR_ILE) & 1) | |
470 | #define msr_ee ((env->msr >> MSR_EE) & 1) | |
471 | #define msr_pr ((env->msr >> MSR_PR) & 1) | |
472 | #define msr_fp ((env->msr >> MSR_FP) & 1) | |
473 | #define msr_me ((env->msr >> MSR_ME) & 1) | |
474 | #define msr_fe0 ((env->msr >> MSR_FE0) & 1) | |
475 | #define msr_se ((env->msr >> MSR_SE) & 1) | |
476 | #define msr_dwe ((env->msr >> MSR_DWE) & 1) | |
477 | #define msr_uble ((env->msr >> MSR_UBLE) & 1) | |
478 | #define msr_be ((env->msr >> MSR_BE) & 1) | |
479 | #define msr_de ((env->msr >> MSR_DE) & 1) | |
480 | #define msr_fe1 ((env->msr >> MSR_FE1) & 1) | |
481 | #define msr_al ((env->msr >> MSR_AL) & 1) | |
482 | #define msr_ep ((env->msr >> MSR_EP) & 1) | |
483 | #define msr_ir ((env->msr >> MSR_IR) & 1) | |
484 | #define msr_dr ((env->msr >> MSR_DR) & 1) | |
485 | #define msr_pe ((env->msr >> MSR_PE) & 1) | |
486 | #define msr_px ((env->msr >> MSR_PX) & 1) | |
487 | #define msr_pmm ((env->msr >> MSR_PMM) & 1) | |
488 | #define msr_ri ((env->msr >> MSR_RI) & 1) | |
489 | #define msr_le ((env->msr >> MSR_LE) & 1) | |
a4f30719 JM |
490 | /* Hypervisor bit is more specific */ |
491 | #if defined(TARGET_PPC64) | |
492 | #define MSR_HVB (1ULL << MSR_SHV) | |
493 | #define msr_hv msr_shv | |
494 | #else | |
495 | #if defined(PPC_EMULATE_32BITS_HYPV) | |
496 | #define MSR_HVB (1ULL << MSR_THV) | |
497 | #define msr_hv msr_thv | |
a4f30719 JM |
498 | #else |
499 | #define MSR_HVB (0ULL) | |
500 | #define msr_hv (0) | |
501 | #endif | |
502 | #endif | |
79aceca5 | 503 | |
a586e548 EI |
504 | /* Exception state register bits definition */ |
505 | #define ESR_ST 23 /* Exception was caused by a store type access. */ | |
506 | ||
d26bfc9a | 507 | enum { |
4018bae9 | 508 | POWERPC_FLAG_NONE = 0x00000000, |
d26bfc9a | 509 | /* Flag for MSR bit 25 signification (VRE/SPE) */ |
4018bae9 JM |
510 | POWERPC_FLAG_SPE = 0x00000001, |
511 | POWERPC_FLAG_VRE = 0x00000002, | |
d26bfc9a | 512 | /* Flag for MSR bit 17 signification (TGPR/CE) */ |
4018bae9 JM |
513 | POWERPC_FLAG_TGPR = 0x00000004, |
514 | POWERPC_FLAG_CE = 0x00000008, | |
d26bfc9a | 515 | /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */ |
4018bae9 JM |
516 | POWERPC_FLAG_SE = 0x00000010, |
517 | POWERPC_FLAG_DWE = 0x00000020, | |
518 | POWERPC_FLAG_UBLE = 0x00000040, | |
d26bfc9a | 519 | /* Flag for MSR bit 9 signification (BE/DE) */ |
4018bae9 JM |
520 | POWERPC_FLAG_BE = 0x00000080, |
521 | POWERPC_FLAG_DE = 0x00000100, | |
a4f30719 | 522 | /* Flag for MSR bit 2 signification (PX/PMM) */ |
4018bae9 JM |
523 | POWERPC_FLAG_PX = 0x00000200, |
524 | POWERPC_FLAG_PMM = 0x00000400, | |
525 | /* Flag for special features */ | |
526 | /* Decrementer clock: RTC clock (POWER, 601) or bus clock */ | |
527 | POWERPC_FLAG_RTC_CLK = 0x00010000, | |
528 | POWERPC_FLAG_BUS_CLK = 0x00020000, | |
d26bfc9a JM |
529 | }; |
530 | ||
7c58044c JM |
531 | /*****************************************************************************/ |
532 | /* Floating point status and control register */ | |
533 | #define FPSCR_FX 31 /* Floating-point exception summary */ | |
534 | #define FPSCR_FEX 30 /* Floating-point enabled exception summary */ | |
535 | #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */ | |
536 | #define FPSCR_OX 28 /* Floating-point overflow exception */ | |
537 | #define FPSCR_UX 27 /* Floating-point underflow exception */ | |
538 | #define FPSCR_ZX 26 /* Floating-point zero divide exception */ | |
539 | #define FPSCR_XX 25 /* Floating-point inexact exception */ | |
540 | #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */ | |
541 | #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */ | |
542 | #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */ | |
543 | #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */ | |
544 | #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */ | |
545 | #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */ | |
546 | #define FPSCR_FR 18 /* Floating-point fraction rounded */ | |
547 | #define FPSCR_FI 17 /* Floating-point fraction inexact */ | |
548 | #define FPSCR_C 16 /* Floating-point result class descriptor */ | |
549 | #define FPSCR_FL 15 /* Floating-point less than or negative */ | |
550 | #define FPSCR_FG 14 /* Floating-point greater than or negative */ | |
551 | #define FPSCR_FE 13 /* Floating-point equal or zero */ | |
552 | #define FPSCR_FU 12 /* Floating-point unordered or NaN */ | |
553 | #define FPSCR_FPCC 12 /* Floating-point condition code */ | |
554 | #define FPSCR_FPRF 12 /* Floating-point result flags */ | |
555 | #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ | |
556 | #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */ | |
557 | #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */ | |
558 | #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ | |
559 | #define FPSCR_OE 6 /* Floating-point overflow exception enable */ | |
560 | #define FPSCR_UE 5 /* Floating-point undeflow exception enable */ | |
561 | #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */ | |
562 | #define FPSCR_XE 3 /* Floating-point inexact exception enable */ | |
563 | #define FPSCR_NI 2 /* Floating-point non-IEEE mode */ | |
564 | #define FPSCR_RN1 1 | |
565 | #define FPSCR_RN 0 /* Floating-point rounding control */ | |
566 | #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1) | |
567 | #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1) | |
568 | #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1) | |
569 | #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1) | |
570 | #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1) | |
571 | #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1) | |
572 | #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1) | |
573 | #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1) | |
574 | #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1) | |
575 | #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1) | |
576 | #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1) | |
577 | #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1) | |
578 | #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF) | |
579 | #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1) | |
580 | #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1) | |
581 | #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1) | |
582 | #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1) | |
583 | #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1) | |
584 | #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1) | |
585 | #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1) | |
586 | #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1) | |
587 | #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1) | |
588 | #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3) | |
589 | /* Invalid operation exception summary */ | |
590 | #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ | |
591 | (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \ | |
592 | (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \ | |
593 | (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \ | |
594 | (1 << FPSCR_VXCVI))) | |
595 | /* exception summary */ | |
596 | #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F) | |
597 | /* enabled exception summary */ | |
598 | #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \ | |
599 | 0x1F) | |
600 | ||
601 | /*****************************************************************************/ | |
6fa724a3 AJ |
602 | /* Vector status and control register */ |
603 | #define VSCR_NJ 16 /* Vector non-java */ | |
604 | #define VSCR_SAT 0 /* Vector saturation */ | |
605 | #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1) | |
606 | #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1) | |
607 | ||
608 | /*****************************************************************************/ | |
7c58044c | 609 | /* The whole PowerPC CPU context */ |
6ebbf390 | 610 | #define NB_MMU_MODES 3 |
6ebbf390 | 611 | |
3fc6c082 FB |
612 | struct CPUPPCState { |
613 | /* First are the most commonly used resources | |
614 | * during translated code execution | |
615 | */ | |
79aceca5 | 616 | /* general purpose registers */ |
bd7d9a6d | 617 | target_ulong gpr[32]; |
65d6c0f3 | 618 | #if !defined(TARGET_PPC64) |
3cd7d1dd | 619 | /* Storage for GPR MSB, used by the SPE extension */ |
bd7d9a6d | 620 | target_ulong gprh[32]; |
3cd7d1dd | 621 | #endif |
3fc6c082 FB |
622 | /* LR */ |
623 | target_ulong lr; | |
624 | /* CTR */ | |
625 | target_ulong ctr; | |
626 | /* condition register */ | |
47e4661c | 627 | uint32_t crf[8]; |
79aceca5 | 628 | /* XER */ |
3d7b417e | 629 | target_ulong xer; |
79aceca5 | 630 | /* Reservation address */ |
18b21a2f NF |
631 | target_ulong reserve_addr; |
632 | /* Reservation value */ | |
633 | target_ulong reserve_val; | |
4425265b NF |
634 | /* Reservation store address */ |
635 | target_ulong reserve_ea; | |
636 | /* Reserved store source register and size */ | |
637 | target_ulong reserve_info; | |
3fc6c082 FB |
638 | |
639 | /* Those ones are used in supervisor mode only */ | |
79aceca5 | 640 | /* machine state register */ |
0411a972 | 641 | target_ulong msr; |
3fc6c082 | 642 | /* temporary general purpose registers */ |
bd7d9a6d | 643 | target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ |
3fc6c082 FB |
644 | |
645 | /* Floating point execution context */ | |
4ecc3190 | 646 | float_status fp_status; |
3fc6c082 FB |
647 | /* floating point registers */ |
648 | float64 fpr[32]; | |
649 | /* floating point status and control register */ | |
7c58044c | 650 | uint32_t fpscr; |
4ecc3190 | 651 | |
cb2dbfc3 AJ |
652 | /* Next instruction pointer */ |
653 | target_ulong nip; | |
a316d335 | 654 | |
ac9eb073 FB |
655 | int access_type; /* when a memory exception occurs, the access |
656 | type is stored here */ | |
a541f297 | 657 | |
cb2dbfc3 AJ |
658 | CPU_COMMON |
659 | ||
f2e63a42 JM |
660 | /* MMU context - only relevant for full system emulation */ |
661 | #if !defined(CONFIG_USER_ONLY) | |
662 | #if defined(TARGET_PPC64) | |
3fc6c082 FB |
663 | /* Address space register */ |
664 | target_ulong asr; | |
f2e63a42 | 665 | /* PowerPC 64 SLB area */ |
c227f099 | 666 | ppc_slb_t slb[64]; |
f2e63a42 JM |
667 | int slb_nr; |
668 | #endif | |
3fc6c082 | 669 | /* segment registers */ |
bb593904 DG |
670 | target_phys_addr_t htab_base; |
671 | target_phys_addr_t htab_mask; | |
74d37793 | 672 | target_ulong sr[32]; |
f43e3525 DG |
673 | /* externally stored hash table */ |
674 | uint8_t *external_htab; | |
3fc6c082 FB |
675 | /* BATs */ |
676 | int nb_BATs; | |
677 | target_ulong DBAT[2][8]; | |
678 | target_ulong IBAT[2][8]; | |
f2e63a42 JM |
679 | /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */ |
680 | int nb_tlb; /* Total number of TLB */ | |
681 | int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ | |
682 | int nb_ways; /* Number of ways in the TLB set */ | |
683 | int last_way; /* Last used way used to allocate TLB in a LRU way */ | |
684 | int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ | |
685 | int nb_pids; /* Number of available PID registers */ | |
c227f099 | 686 | ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */ |
f2e63a42 JM |
687 | /* 403 dedicated access protection registers */ |
688 | target_ulong pb[4]; | |
689 | #endif | |
9fddaa0c | 690 | |
3fc6c082 FB |
691 | /* Other registers */ |
692 | /* Special purpose registers */ | |
693 | target_ulong spr[1024]; | |
c227f099 | 694 | ppc_spr_t spr_cb[1024]; |
3fc6c082 | 695 | /* Altivec registers */ |
c227f099 | 696 | ppc_avr_t avr[32]; |
3fc6c082 | 697 | uint32_t vscr; |
d9bce9d9 | 698 | /* SPE registers */ |
2231ef10 | 699 | uint64_t spe_acc; |
d9bce9d9 | 700 | uint32_t spe_fscr; |
fbd265b6 AJ |
701 | /* SPE and Altivec can share a status since they will never be used |
702 | * simultaneously */ | |
703 | float_status vec_status; | |
3fc6c082 FB |
704 | |
705 | /* Internal devices resources */ | |
9fddaa0c | 706 | /* Time base and decrementer */ |
c227f099 | 707 | ppc_tb_t *tb_env; |
3fc6c082 | 708 | /* Device control registers */ |
c227f099 | 709 | ppc_dcr_t *dcr_env; |
3fc6c082 | 710 | |
d63001d1 JM |
711 | int dcache_line_size; |
712 | int icache_line_size; | |
713 | ||
3fc6c082 FB |
714 | /* Those resources are used during exception processing */ |
715 | /* CPU model definition */ | |
a750fc0b | 716 | target_ulong msr_mask; |
c227f099 AL |
717 | powerpc_mmu_t mmu_model; |
718 | powerpc_excp_t excp_model; | |
719 | powerpc_input_t bus_model; | |
237c0af0 | 720 | int bfd_mach; |
3fc6c082 | 721 | uint32_t flags; |
c29b735c | 722 | uint64_t insns_flags; |
3fc6c082 | 723 | |
ed120055 DG |
724 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
725 | target_phys_addr_t vpa; | |
726 | target_phys_addr_t slb_shadow; | |
727 | target_phys_addr_t dispatch_trace_log; | |
728 | uint32_t dtl_size; | |
729 | #endif /* TARGET_PPC64 */ | |
730 | ||
3fc6c082 | 731 | int error_code; |
47103572 | 732 | uint32_t pending_interrupts; |
e9df014c JM |
733 | #if !defined(CONFIG_USER_ONLY) |
734 | /* This is the IRQ controller, which is implementation dependant | |
735 | * and only relevant when emulating a complete machine. | |
736 | */ | |
737 | uint32_t irq_input_state; | |
738 | void **irq_inputs; | |
e1833e1f JM |
739 | /* Exception vectors */ |
740 | target_ulong excp_vectors[POWERPC_EXCP_NB]; | |
741 | target_ulong excp_prefix; | |
fc1c67bc | 742 | target_ulong hreset_excp_prefix; |
e1833e1f JM |
743 | target_ulong ivor_mask; |
744 | target_ulong ivpr_mask; | |
d63001d1 | 745 | target_ulong hreset_vector; |
e9df014c | 746 | #endif |
3fc6c082 FB |
747 | |
748 | /* Those resources are used only during code translation */ | |
3fc6c082 | 749 | /* opcode handlers */ |
c227f099 | 750 | opc_handler_t *opcodes[0x40]; |
3fc6c082 FB |
751 | |
752 | /* Those resources are used only in Qemu core */ | |
056401ea JM |
753 | target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ |
754 | target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */ | |
6ebbf390 | 755 | int mmu_idx; /* precomputed MMU index to speed up mem accesses */ |
3fc6c082 | 756 | |
9fddaa0c FB |
757 | /* Power management */ |
758 | int power_mode; | |
cd346349 | 759 | int (*check_pow)(CPUPPCState *env); |
a541f297 | 760 | |
2c50e26e EI |
761 | #if !defined(CONFIG_USER_ONLY) |
762 | void *load_info; /* Holds boot loading state. */ | |
763 | #endif | |
3fc6c082 | 764 | }; |
79aceca5 | 765 | |
3c7b48b7 | 766 | #if !defined(CONFIG_USER_ONLY) |
76a66253 | 767 | /* Context used internally during MMU translations */ |
c227f099 AL |
768 | typedef struct mmu_ctx_t mmu_ctx_t; |
769 | struct mmu_ctx_t { | |
770 | target_phys_addr_t raddr; /* Real address */ | |
771 | target_phys_addr_t eaddr; /* Effective address */ | |
76a66253 | 772 | int prot; /* Protection bits */ |
fda6a0ec | 773 | target_phys_addr_t hash[2]; /* Pagetable hash values */ |
76a66253 JM |
774 | target_ulong ptem; /* Virtual segment ID | API */ |
775 | int key; /* Access key */ | |
b227a8e9 | 776 | int nx; /* Non-execute area */ |
76a66253 | 777 | }; |
3c7b48b7 | 778 | #endif |
76a66253 | 779 | |
3fc6c082 | 780 | /*****************************************************************************/ |
aaed909a | 781 | CPUPPCState *cpu_ppc_init (const char *cpu_model); |
2e70f6ef | 782 | void ppc_translate_init(void); |
36081602 JM |
783 | int cpu_ppc_exec (CPUPPCState *s); |
784 | void cpu_ppc_close (CPUPPCState *s); | |
79aceca5 FB |
785 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
786 | signal handlers to inform the virtual CPU of exceptions. non zero | |
787 | is returned if the signal was handled by the virtual CPU. */ | |
36081602 JM |
788 | int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
789 | void *puc); | |
93220573 AJ |
790 | int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw, |
791 | int mmu_idx, int is_softmmu); | |
0b5c1ce8 | 792 | #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault |
3c7b48b7 | 793 | #if !defined(CONFIG_USER_ONLY) |
c227f099 | 794 | int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr, |
93220573 | 795 | int rw, int access_type); |
3c7b48b7 | 796 | #endif |
a541f297 | 797 | void do_interrupt (CPUPPCState *env); |
e9df014c | 798 | void ppc_hw_interrupt (CPUPPCState *env); |
a541f297 | 799 | |
93220573 | 800 | void cpu_dump_rfi (target_ulong RA, target_ulong msr); |
a541f297 | 801 | |
76a66253 | 802 | #if !defined(CONFIG_USER_ONLY) |
93220573 AJ |
803 | void ppc6xx_tlb_store (CPUPPCState *env, target_ulong EPN, int way, int is_code, |
804 | target_ulong pte0, target_ulong pte1); | |
45d827d2 AJ |
805 | void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
806 | void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value); | |
807 | void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value); | |
808 | void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value); | |
809 | void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value); | |
810 | void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value); | |
811 | void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); | |
d9bce9d9 | 812 | #if defined(TARGET_PPC64) |
d9bce9d9 | 813 | void ppc_store_asr (CPUPPCState *env, target_ulong value); |
12de9a39 | 814 | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr); |
f6b868fc | 815 | target_ulong ppc_load_sr (CPUPPCState *env, int sr_nr); |
81762d6d | 816 | int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs); |
efdef95f DG |
817 | int ppc_load_slb_esid (CPUPPCState *env, target_ulong rb, target_ulong *rt); |
818 | int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb, target_ulong *rt); | |
12de9a39 | 819 | #endif /* defined(TARGET_PPC64) */ |
45d827d2 | 820 | void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
12de9a39 | 821 | #endif /* !defined(CONFIG_USER_ONLY) */ |
0411a972 | 822 | void ppc_store_msr (CPUPPCState *env, target_ulong value); |
3fc6c082 | 823 | |
9a78eead | 824 | void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf); |
aaed909a | 825 | |
c227f099 AL |
826 | const ppc_def_t *cpu_ppc_find_by_name (const char *name); |
827 | int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def); | |
85c4adf6 | 828 | |
9fddaa0c FB |
829 | /* Time-base and decrementer management */ |
830 | #ifndef NO_CPU_IO_DEFS | |
e3ea6529 | 831 | uint64_t cpu_ppc_load_tbl (CPUPPCState *env); |
9fddaa0c FB |
832 | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
833 | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value); | |
834 | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value); | |
b711de95 | 835 | uint64_t cpu_ppc_load_atbl (CPUPPCState *env); |
a062e36c JM |
836 | uint32_t cpu_ppc_load_atbu (CPUPPCState *env); |
837 | void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value); | |
838 | void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value); | |
9fddaa0c FB |
839 | uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
840 | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value); | |
58a7d328 JM |
841 | uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); |
842 | void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value); | |
843 | uint64_t cpu_ppc_load_purr (CPUPPCState *env); | |
844 | void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value); | |
d9bce9d9 JM |
845 | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
846 | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); | |
847 | #if !defined(CONFIG_USER_ONLY) | |
848 | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value); | |
849 | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value); | |
850 | target_ulong load_40x_pit (CPUPPCState *env); | |
851 | void store_40x_pit (CPUPPCState *env, target_ulong val); | |
8ecc7913 | 852 | void store_40x_dbcr0 (CPUPPCState *env, uint32_t val); |
c294fc58 | 853 | void store_40x_sler (CPUPPCState *env, uint32_t val); |
d9bce9d9 JM |
854 | void store_booke_tcr (CPUPPCState *env, target_ulong val); |
855 | void store_booke_tsr (CPUPPCState *env, target_ulong val); | |
0a032cbe | 856 | void ppc_tlb_invalidate_all (CPUPPCState *env); |
daf4f96e JM |
857 | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); |
858 | #if defined(TARGET_PPC64) | |
859 | void ppc_slb_invalidate_all (CPUPPCState *env); | |
860 | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0); | |
861 | #endif | |
36081602 | 862 | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid); |
d9bce9d9 | 863 | #endif |
9fddaa0c | 864 | #endif |
79aceca5 | 865 | |
636aa200 | 866 | static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) |
6b542af7 JM |
867 | { |
868 | uint64_t gprv; | |
869 | ||
870 | gprv = env->gpr[gprn]; | |
871 | #if !defined(TARGET_PPC64) | |
872 | if (env->flags & POWERPC_FLAG_SPE) { | |
873 | /* If the CPU implements the SPE extension, we have to get the | |
874 | * high bits of the GPR from the gprh storage area | |
875 | */ | |
876 | gprv &= 0xFFFFFFFFULL; | |
877 | gprv |= (uint64_t)env->gprh[gprn] << 32; | |
878 | } | |
879 | #endif | |
880 | ||
881 | return gprv; | |
882 | } | |
883 | ||
2e719ba3 | 884 | /* Device control registers */ |
73b01960 AG |
885 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); |
886 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); | |
2e719ba3 | 887 | |
9467d44c TS |
888 | #define cpu_init cpu_ppc_init |
889 | #define cpu_exec cpu_ppc_exec | |
890 | #define cpu_gen_code cpu_ppc_gen_code | |
891 | #define cpu_signal_handler cpu_ppc_signal_handler | |
c732abe2 | 892 | #define cpu_list ppc_cpu_list |
9467d44c | 893 | |
fc1c67bc | 894 | #define CPU_SAVE_VERSION 4 |
b3c7724c | 895 | |
6ebbf390 JM |
896 | /* MMU modes definitions */ |
897 | #define MMU_MODE0_SUFFIX _user | |
898 | #define MMU_MODE1_SUFFIX _kernel | |
6ebbf390 | 899 | #define MMU_MODE2_SUFFIX _hypv |
6ebbf390 JM |
900 | #define MMU_USER_IDX 0 |
901 | static inline int cpu_mmu_index (CPUState *env) | |
902 | { | |
903 | return env->mmu_idx; | |
904 | } | |
905 | ||
6e68e076 PB |
906 | #if defined(CONFIG_USER_ONLY) |
907 | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) | |
908 | { | |
f8ed7070 | 909 | if (newsp) |
6e68e076 | 910 | env->gpr[1] = newsp; |
d11f69b2 | 911 | env->gpr[3] = 0; |
6e68e076 PB |
912 | } |
913 | #endif | |
914 | ||
79aceca5 FB |
915 | #include "cpu-all.h" |
916 | ||
3fc6c082 | 917 | /*****************************************************************************/ |
e1571908 | 918 | /* CRF definitions */ |
57951c27 AJ |
919 | #define CRF_LT 3 |
920 | #define CRF_GT 2 | |
921 | #define CRF_EQ 1 | |
922 | #define CRF_SO 0 | |
e6bba2ef NF |
923 | #define CRF_CH (1 << CRF_LT) |
924 | #define CRF_CL (1 << CRF_GT) | |
925 | #define CRF_CH_OR_CL (1 << CRF_EQ) | |
926 | #define CRF_CH_AND_CL (1 << CRF_SO) | |
e1571908 AJ |
927 | |
928 | /* XER definitions */ | |
3d7b417e AJ |
929 | #define XER_SO 31 |
930 | #define XER_OV 30 | |
931 | #define XER_CA 29 | |
932 | #define XER_CMP 8 | |
933 | #define XER_BC 0 | |
934 | #define xer_so ((env->xer >> XER_SO) & 1) | |
935 | #define xer_ov ((env->xer >> XER_OV) & 1) | |
936 | #define xer_ca ((env->xer >> XER_CA) & 1) | |
937 | #define xer_cmp ((env->xer >> XER_CMP) & 0xFF) | |
938 | #define xer_bc ((env->xer >> XER_BC) & 0x7F) | |
79aceca5 | 939 | |
3fc6c082 | 940 | /* SPR definitions */ |
80d11f44 JM |
941 | #define SPR_MQ (0x000) |
942 | #define SPR_XER (0x001) | |
943 | #define SPR_601_VRTCU (0x004) | |
944 | #define SPR_601_VRTCL (0x005) | |
945 | #define SPR_601_UDECR (0x006) | |
946 | #define SPR_LR (0x008) | |
947 | #define SPR_CTR (0x009) | |
948 | #define SPR_DSISR (0x012) | |
949 | #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ | |
950 | #define SPR_601_RTCU (0x014) | |
951 | #define SPR_601_RTCL (0x015) | |
952 | #define SPR_DECR (0x016) | |
953 | #define SPR_SDR1 (0x019) | |
954 | #define SPR_SRR0 (0x01A) | |
955 | #define SPR_SRR1 (0x01B) | |
956 | #define SPR_AMR (0x01D) | |
957 | #define SPR_BOOKE_PID (0x030) | |
958 | #define SPR_BOOKE_DECAR (0x036) | |
959 | #define SPR_BOOKE_CSRR0 (0x03A) | |
960 | #define SPR_BOOKE_CSRR1 (0x03B) | |
961 | #define SPR_BOOKE_DEAR (0x03D) | |
962 | #define SPR_BOOKE_ESR (0x03E) | |
963 | #define SPR_BOOKE_IVPR (0x03F) | |
964 | #define SPR_MPC_EIE (0x050) | |
965 | #define SPR_MPC_EID (0x051) | |
966 | #define SPR_MPC_NRI (0x052) | |
967 | #define SPR_CTRL (0x088) | |
968 | #define SPR_MPC_CMPA (0x090) | |
969 | #define SPR_MPC_CMPB (0x091) | |
970 | #define SPR_MPC_CMPC (0x092) | |
971 | #define SPR_MPC_CMPD (0x093) | |
972 | #define SPR_MPC_ECR (0x094) | |
973 | #define SPR_MPC_DER (0x095) | |
974 | #define SPR_MPC_COUNTA (0x096) | |
975 | #define SPR_MPC_COUNTB (0x097) | |
976 | #define SPR_UCTRL (0x098) | |
977 | #define SPR_MPC_CMPE (0x098) | |
978 | #define SPR_MPC_CMPF (0x099) | |
979 | #define SPR_MPC_CMPG (0x09A) | |
980 | #define SPR_MPC_CMPH (0x09B) | |
981 | #define SPR_MPC_LCTRL1 (0x09C) | |
982 | #define SPR_MPC_LCTRL2 (0x09D) | |
983 | #define SPR_MPC_ICTRL (0x09E) | |
984 | #define SPR_MPC_BAR (0x09F) | |
985 | #define SPR_VRSAVE (0x100) | |
986 | #define SPR_USPRG0 (0x100) | |
987 | #define SPR_USPRG1 (0x101) | |
988 | #define SPR_USPRG2 (0x102) | |
989 | #define SPR_USPRG3 (0x103) | |
990 | #define SPR_USPRG4 (0x104) | |
991 | #define SPR_USPRG5 (0x105) | |
992 | #define SPR_USPRG6 (0x106) | |
993 | #define SPR_USPRG7 (0x107) | |
994 | #define SPR_VTBL (0x10C) | |
995 | #define SPR_VTBU (0x10D) | |
996 | #define SPR_SPRG0 (0x110) | |
997 | #define SPR_SPRG1 (0x111) | |
998 | #define SPR_SPRG2 (0x112) | |
999 | #define SPR_SPRG3 (0x113) | |
1000 | #define SPR_SPRG4 (0x114) | |
1001 | #define SPR_SCOMC (0x114) | |
1002 | #define SPR_SPRG5 (0x115) | |
1003 | #define SPR_SCOMD (0x115) | |
1004 | #define SPR_SPRG6 (0x116) | |
1005 | #define SPR_SPRG7 (0x117) | |
1006 | #define SPR_ASR (0x118) | |
1007 | #define SPR_EAR (0x11A) | |
1008 | #define SPR_TBL (0x11C) | |
1009 | #define SPR_TBU (0x11D) | |
1010 | #define SPR_TBU40 (0x11E) | |
1011 | #define SPR_SVR (0x11E) | |
1012 | #define SPR_BOOKE_PIR (0x11E) | |
1013 | #define SPR_PVR (0x11F) | |
1014 | #define SPR_HSPRG0 (0x130) | |
1015 | #define SPR_BOOKE_DBSR (0x130) | |
1016 | #define SPR_HSPRG1 (0x131) | |
1017 | #define SPR_HDSISR (0x132) | |
1018 | #define SPR_HDAR (0x133) | |
9d52e907 | 1019 | #define SPR_SPURR (0x134) |
80d11f44 JM |
1020 | #define SPR_BOOKE_DBCR0 (0x134) |
1021 | #define SPR_IBCR (0x135) | |
1022 | #define SPR_PURR (0x135) | |
1023 | #define SPR_BOOKE_DBCR1 (0x135) | |
1024 | #define SPR_DBCR (0x136) | |
1025 | #define SPR_HDEC (0x136) | |
1026 | #define SPR_BOOKE_DBCR2 (0x136) | |
1027 | #define SPR_HIOR (0x137) | |
1028 | #define SPR_MBAR (0x137) | |
1029 | #define SPR_RMOR (0x138) | |
1030 | #define SPR_BOOKE_IAC1 (0x138) | |
1031 | #define SPR_HRMOR (0x139) | |
1032 | #define SPR_BOOKE_IAC2 (0x139) | |
1033 | #define SPR_HSRR0 (0x13A) | |
1034 | #define SPR_BOOKE_IAC3 (0x13A) | |
1035 | #define SPR_HSRR1 (0x13B) | |
1036 | #define SPR_BOOKE_IAC4 (0x13B) | |
1037 | #define SPR_LPCR (0x13C) | |
1038 | #define SPR_BOOKE_DAC1 (0x13C) | |
1039 | #define SPR_LPIDR (0x13D) | |
1040 | #define SPR_DABR2 (0x13D) | |
1041 | #define SPR_BOOKE_DAC2 (0x13D) | |
1042 | #define SPR_BOOKE_DVC1 (0x13E) | |
1043 | #define SPR_BOOKE_DVC2 (0x13F) | |
1044 | #define SPR_BOOKE_TSR (0x150) | |
1045 | #define SPR_BOOKE_TCR (0x154) | |
1046 | #define SPR_BOOKE_IVOR0 (0x190) | |
1047 | #define SPR_BOOKE_IVOR1 (0x191) | |
1048 | #define SPR_BOOKE_IVOR2 (0x192) | |
1049 | #define SPR_BOOKE_IVOR3 (0x193) | |
1050 | #define SPR_BOOKE_IVOR4 (0x194) | |
1051 | #define SPR_BOOKE_IVOR5 (0x195) | |
1052 | #define SPR_BOOKE_IVOR6 (0x196) | |
1053 | #define SPR_BOOKE_IVOR7 (0x197) | |
1054 | #define SPR_BOOKE_IVOR8 (0x198) | |
1055 | #define SPR_BOOKE_IVOR9 (0x199) | |
1056 | #define SPR_BOOKE_IVOR10 (0x19A) | |
1057 | #define SPR_BOOKE_IVOR11 (0x19B) | |
1058 | #define SPR_BOOKE_IVOR12 (0x19C) | |
1059 | #define SPR_BOOKE_IVOR13 (0x19D) | |
1060 | #define SPR_BOOKE_IVOR14 (0x19E) | |
1061 | #define SPR_BOOKE_IVOR15 (0x19F) | |
1062 | #define SPR_BOOKE_SPEFSCR (0x200) | |
1063 | #define SPR_Exxx_BBEAR (0x201) | |
1064 | #define SPR_Exxx_BBTAR (0x202) | |
1065 | #define SPR_Exxx_L1CFG0 (0x203) | |
1066 | #define SPR_Exxx_NPIDR (0x205) | |
1067 | #define SPR_ATBL (0x20E) | |
1068 | #define SPR_ATBU (0x20F) | |
1069 | #define SPR_IBAT0U (0x210) | |
1070 | #define SPR_BOOKE_IVOR32 (0x210) | |
1071 | #define SPR_RCPU_MI_GRA (0x210) | |
1072 | #define SPR_IBAT0L (0x211) | |
1073 | #define SPR_BOOKE_IVOR33 (0x211) | |
1074 | #define SPR_IBAT1U (0x212) | |
1075 | #define SPR_BOOKE_IVOR34 (0x212) | |
1076 | #define SPR_IBAT1L (0x213) | |
1077 | #define SPR_BOOKE_IVOR35 (0x213) | |
1078 | #define SPR_IBAT2U (0x214) | |
1079 | #define SPR_BOOKE_IVOR36 (0x214) | |
1080 | #define SPR_IBAT2L (0x215) | |
1081 | #define SPR_BOOKE_IVOR37 (0x215) | |
1082 | #define SPR_IBAT3U (0x216) | |
1083 | #define SPR_IBAT3L (0x217) | |
1084 | #define SPR_DBAT0U (0x218) | |
1085 | #define SPR_RCPU_L2U_GRA (0x218) | |
1086 | #define SPR_DBAT0L (0x219) | |
1087 | #define SPR_DBAT1U (0x21A) | |
1088 | #define SPR_DBAT1L (0x21B) | |
1089 | #define SPR_DBAT2U (0x21C) | |
1090 | #define SPR_DBAT2L (0x21D) | |
1091 | #define SPR_DBAT3U (0x21E) | |
1092 | #define SPR_DBAT3L (0x21F) | |
1093 | #define SPR_IBAT4U (0x230) | |
1094 | #define SPR_RPCU_BBCMCR (0x230) | |
1095 | #define SPR_MPC_IC_CST (0x230) | |
1096 | #define SPR_Exxx_CTXCR (0x230) | |
1097 | #define SPR_IBAT4L (0x231) | |
1098 | #define SPR_MPC_IC_ADR (0x231) | |
1099 | #define SPR_Exxx_DBCR3 (0x231) | |
1100 | #define SPR_IBAT5U (0x232) | |
1101 | #define SPR_MPC_IC_DAT (0x232) | |
1102 | #define SPR_Exxx_DBCNT (0x232) | |
1103 | #define SPR_IBAT5L (0x233) | |
1104 | #define SPR_IBAT6U (0x234) | |
1105 | #define SPR_IBAT6L (0x235) | |
1106 | #define SPR_IBAT7U (0x236) | |
1107 | #define SPR_IBAT7L (0x237) | |
1108 | #define SPR_DBAT4U (0x238) | |
1109 | #define SPR_RCPU_L2U_MCR (0x238) | |
1110 | #define SPR_MPC_DC_CST (0x238) | |
1111 | #define SPR_Exxx_ALTCTXCR (0x238) | |
1112 | #define SPR_DBAT4L (0x239) | |
1113 | #define SPR_MPC_DC_ADR (0x239) | |
1114 | #define SPR_DBAT5U (0x23A) | |
1115 | #define SPR_BOOKE_MCSRR0 (0x23A) | |
1116 | #define SPR_MPC_DC_DAT (0x23A) | |
1117 | #define SPR_DBAT5L (0x23B) | |
1118 | #define SPR_BOOKE_MCSRR1 (0x23B) | |
1119 | #define SPR_DBAT6U (0x23C) | |
1120 | #define SPR_BOOKE_MCSR (0x23C) | |
1121 | #define SPR_DBAT6L (0x23D) | |
1122 | #define SPR_Exxx_MCAR (0x23D) | |
1123 | #define SPR_DBAT7U (0x23E) | |
1124 | #define SPR_BOOKE_DSRR0 (0x23E) | |
1125 | #define SPR_DBAT7L (0x23F) | |
1126 | #define SPR_BOOKE_DSRR1 (0x23F) | |
1127 | #define SPR_BOOKE_SPRG8 (0x25C) | |
1128 | #define SPR_BOOKE_SPRG9 (0x25D) | |
1129 | #define SPR_BOOKE_MAS0 (0x270) | |
1130 | #define SPR_BOOKE_MAS1 (0x271) | |
1131 | #define SPR_BOOKE_MAS2 (0x272) | |
1132 | #define SPR_BOOKE_MAS3 (0x273) | |
1133 | #define SPR_BOOKE_MAS4 (0x274) | |
1134 | #define SPR_BOOKE_MAS5 (0x275) | |
1135 | #define SPR_BOOKE_MAS6 (0x276) | |
1136 | #define SPR_BOOKE_PID1 (0x279) | |
1137 | #define SPR_BOOKE_PID2 (0x27A) | |
1138 | #define SPR_MPC_DPDR (0x280) | |
1139 | #define SPR_MPC_IMMR (0x288) | |
1140 | #define SPR_BOOKE_TLB0CFG (0x2B0) | |
1141 | #define SPR_BOOKE_TLB1CFG (0x2B1) | |
1142 | #define SPR_BOOKE_TLB2CFG (0x2B2) | |
1143 | #define SPR_BOOKE_TLB3CFG (0x2B3) | |
1144 | #define SPR_BOOKE_EPR (0x2BE) | |
1145 | #define SPR_PERF0 (0x300) | |
1146 | #define SPR_RCPU_MI_RBA0 (0x300) | |
1147 | #define SPR_MPC_MI_CTR (0x300) | |
1148 | #define SPR_PERF1 (0x301) | |
1149 | #define SPR_RCPU_MI_RBA1 (0x301) | |
1150 | #define SPR_PERF2 (0x302) | |
1151 | #define SPR_RCPU_MI_RBA2 (0x302) | |
1152 | #define SPR_MPC_MI_AP (0x302) | |
1153 | #define SPR_PERF3 (0x303) | |
082c6681 | 1154 | #define SPR_620_PMC1R (0x303) |
80d11f44 JM |
1155 | #define SPR_RCPU_MI_RBA3 (0x303) |
1156 | #define SPR_MPC_MI_EPN (0x303) | |
1157 | #define SPR_PERF4 (0x304) | |
082c6681 | 1158 | #define SPR_620_PMC2R (0x304) |
80d11f44 JM |
1159 | #define SPR_PERF5 (0x305) |
1160 | #define SPR_MPC_MI_TWC (0x305) | |
1161 | #define SPR_PERF6 (0x306) | |
1162 | #define SPR_MPC_MI_RPN (0x306) | |
1163 | #define SPR_PERF7 (0x307) | |
1164 | #define SPR_PERF8 (0x308) | |
1165 | #define SPR_RCPU_L2U_RBA0 (0x308) | |
1166 | #define SPR_MPC_MD_CTR (0x308) | |
1167 | #define SPR_PERF9 (0x309) | |
1168 | #define SPR_RCPU_L2U_RBA1 (0x309) | |
1169 | #define SPR_MPC_MD_CASID (0x309) | |
1170 | #define SPR_PERFA (0x30A) | |
1171 | #define SPR_RCPU_L2U_RBA2 (0x30A) | |
1172 | #define SPR_MPC_MD_AP (0x30A) | |
1173 | #define SPR_PERFB (0x30B) | |
082c6681 | 1174 | #define SPR_620_MMCR0R (0x30B) |
80d11f44 JM |
1175 | #define SPR_RCPU_L2U_RBA3 (0x30B) |
1176 | #define SPR_MPC_MD_EPN (0x30B) | |
1177 | #define SPR_PERFC (0x30C) | |
1178 | #define SPR_MPC_MD_TWB (0x30C) | |
1179 | #define SPR_PERFD (0x30D) | |
1180 | #define SPR_MPC_MD_TWC (0x30D) | |
1181 | #define SPR_PERFE (0x30E) | |
1182 | #define SPR_MPC_MD_RPN (0x30E) | |
1183 | #define SPR_PERFF (0x30F) | |
1184 | #define SPR_MPC_MD_TW (0x30F) | |
1185 | #define SPR_UPERF0 (0x310) | |
1186 | #define SPR_UPERF1 (0x311) | |
1187 | #define SPR_UPERF2 (0x312) | |
1188 | #define SPR_UPERF3 (0x313) | |
082c6681 | 1189 | #define SPR_620_PMC1W (0x313) |
80d11f44 | 1190 | #define SPR_UPERF4 (0x314) |
082c6681 | 1191 | #define SPR_620_PMC2W (0x314) |
80d11f44 JM |
1192 | #define SPR_UPERF5 (0x315) |
1193 | #define SPR_UPERF6 (0x316) | |
1194 | #define SPR_UPERF7 (0x317) | |
1195 | #define SPR_UPERF8 (0x318) | |
1196 | #define SPR_UPERF9 (0x319) | |
1197 | #define SPR_UPERFA (0x31A) | |
1198 | #define SPR_UPERFB (0x31B) | |
082c6681 | 1199 | #define SPR_620_MMCR0W (0x31B) |
80d11f44 JM |
1200 | #define SPR_UPERFC (0x31C) |
1201 | #define SPR_UPERFD (0x31D) | |
1202 | #define SPR_UPERFE (0x31E) | |
1203 | #define SPR_UPERFF (0x31F) | |
1204 | #define SPR_RCPU_MI_RA0 (0x320) | |
1205 | #define SPR_MPC_MI_DBCAM (0x320) | |
1206 | #define SPR_RCPU_MI_RA1 (0x321) | |
1207 | #define SPR_MPC_MI_DBRAM0 (0x321) | |
1208 | #define SPR_RCPU_MI_RA2 (0x322) | |
1209 | #define SPR_MPC_MI_DBRAM1 (0x322) | |
1210 | #define SPR_RCPU_MI_RA3 (0x323) | |
1211 | #define SPR_RCPU_L2U_RA0 (0x328) | |
1212 | #define SPR_MPC_MD_DBCAM (0x328) | |
1213 | #define SPR_RCPU_L2U_RA1 (0x329) | |
1214 | #define SPR_MPC_MD_DBRAM0 (0x329) | |
1215 | #define SPR_RCPU_L2U_RA2 (0x32A) | |
1216 | #define SPR_MPC_MD_DBRAM1 (0x32A) | |
1217 | #define SPR_RCPU_L2U_RA3 (0x32B) | |
1218 | #define SPR_440_INV0 (0x370) | |
1219 | #define SPR_440_INV1 (0x371) | |
1220 | #define SPR_440_INV2 (0x372) | |
1221 | #define SPR_440_INV3 (0x373) | |
1222 | #define SPR_440_ITV0 (0x374) | |
1223 | #define SPR_440_ITV1 (0x375) | |
1224 | #define SPR_440_ITV2 (0x376) | |
1225 | #define SPR_440_ITV3 (0x377) | |
1226 | #define SPR_440_CCR1 (0x378) | |
1227 | #define SPR_DCRIPR (0x37B) | |
1228 | #define SPR_PPR (0x380) | |
bd928eba | 1229 | #define SPR_750_GQR0 (0x390) |
80d11f44 | 1230 | #define SPR_440_DNV0 (0x390) |
bd928eba | 1231 | #define SPR_750_GQR1 (0x391) |
80d11f44 | 1232 | #define SPR_440_DNV1 (0x391) |
bd928eba | 1233 | #define SPR_750_GQR2 (0x392) |
80d11f44 | 1234 | #define SPR_440_DNV2 (0x392) |
bd928eba | 1235 | #define SPR_750_GQR3 (0x393) |
80d11f44 | 1236 | #define SPR_440_DNV3 (0x393) |
bd928eba | 1237 | #define SPR_750_GQR4 (0x394) |
80d11f44 | 1238 | #define SPR_440_DTV0 (0x394) |
bd928eba | 1239 | #define SPR_750_GQR5 (0x395) |
80d11f44 | 1240 | #define SPR_440_DTV1 (0x395) |
bd928eba | 1241 | #define SPR_750_GQR6 (0x396) |
80d11f44 | 1242 | #define SPR_440_DTV2 (0x396) |
bd928eba | 1243 | #define SPR_750_GQR7 (0x397) |
80d11f44 | 1244 | #define SPR_440_DTV3 (0x397) |
bd928eba JM |
1245 | #define SPR_750_THRM4 (0x398) |
1246 | #define SPR_750CL_HID2 (0x398) | |
80d11f44 | 1247 | #define SPR_440_DVLIM (0x398) |
bd928eba | 1248 | #define SPR_750_WPAR (0x399) |
80d11f44 | 1249 | #define SPR_440_IVLIM (0x399) |
bd928eba JM |
1250 | #define SPR_750_DMAU (0x39A) |
1251 | #define SPR_750_DMAL (0x39B) | |
80d11f44 JM |
1252 | #define SPR_440_RSTCFG (0x39B) |
1253 | #define SPR_BOOKE_DCDBTRL (0x39C) | |
1254 | #define SPR_BOOKE_DCDBTRH (0x39D) | |
1255 | #define SPR_BOOKE_ICDBTRL (0x39E) | |
1256 | #define SPR_BOOKE_ICDBTRH (0x39F) | |
1257 | #define SPR_UMMCR2 (0x3A0) | |
1258 | #define SPR_UPMC5 (0x3A1) | |
1259 | #define SPR_UPMC6 (0x3A2) | |
1260 | #define SPR_UBAMR (0x3A7) | |
1261 | #define SPR_UMMCR0 (0x3A8) | |
1262 | #define SPR_UPMC1 (0x3A9) | |
1263 | #define SPR_UPMC2 (0x3AA) | |
1264 | #define SPR_USIAR (0x3AB) | |
1265 | #define SPR_UMMCR1 (0x3AC) | |
1266 | #define SPR_UPMC3 (0x3AD) | |
1267 | #define SPR_UPMC4 (0x3AE) | |
1268 | #define SPR_USDA (0x3AF) | |
1269 | #define SPR_40x_ZPR (0x3B0) | |
1270 | #define SPR_BOOKE_MAS7 (0x3B0) | |
1271 | #define SPR_620_PMR0 (0x3B0) | |
1272 | #define SPR_MMCR2 (0x3B0) | |
1273 | #define SPR_PMC5 (0x3B1) | |
1274 | #define SPR_40x_PID (0x3B1) | |
1275 | #define SPR_620_PMR1 (0x3B1) | |
1276 | #define SPR_PMC6 (0x3B2) | |
1277 | #define SPR_440_MMUCR (0x3B2) | |
1278 | #define SPR_620_PMR2 (0x3B2) | |
1279 | #define SPR_4xx_CCR0 (0x3B3) | |
1280 | #define SPR_BOOKE_EPLC (0x3B3) | |
1281 | #define SPR_620_PMR3 (0x3B3) | |
1282 | #define SPR_405_IAC3 (0x3B4) | |
1283 | #define SPR_BOOKE_EPSC (0x3B4) | |
1284 | #define SPR_620_PMR4 (0x3B4) | |
1285 | #define SPR_405_IAC4 (0x3B5) | |
1286 | #define SPR_620_PMR5 (0x3B5) | |
1287 | #define SPR_405_DVC1 (0x3B6) | |
1288 | #define SPR_620_PMR6 (0x3B6) | |
1289 | #define SPR_405_DVC2 (0x3B7) | |
1290 | #define SPR_620_PMR7 (0x3B7) | |
1291 | #define SPR_BAMR (0x3B7) | |
1292 | #define SPR_MMCR0 (0x3B8) | |
1293 | #define SPR_620_PMR8 (0x3B8) | |
1294 | #define SPR_PMC1 (0x3B9) | |
1295 | #define SPR_40x_SGR (0x3B9) | |
1296 | #define SPR_620_PMR9 (0x3B9) | |
1297 | #define SPR_PMC2 (0x3BA) | |
1298 | #define SPR_40x_DCWR (0x3BA) | |
1299 | #define SPR_620_PMRA (0x3BA) | |
1300 | #define SPR_SIAR (0x3BB) | |
1301 | #define SPR_405_SLER (0x3BB) | |
1302 | #define SPR_620_PMRB (0x3BB) | |
1303 | #define SPR_MMCR1 (0x3BC) | |
1304 | #define SPR_405_SU0R (0x3BC) | |
1305 | #define SPR_620_PMRC (0x3BC) | |
1306 | #define SPR_401_SKR (0x3BC) | |
1307 | #define SPR_PMC3 (0x3BD) | |
1308 | #define SPR_405_DBCR1 (0x3BD) | |
1309 | #define SPR_620_PMRD (0x3BD) | |
1310 | #define SPR_PMC4 (0x3BE) | |
1311 | #define SPR_620_PMRE (0x3BE) | |
1312 | #define SPR_SDA (0x3BF) | |
1313 | #define SPR_620_PMRF (0x3BF) | |
1314 | #define SPR_403_VTBL (0x3CC) | |
1315 | #define SPR_403_VTBU (0x3CD) | |
1316 | #define SPR_DMISS (0x3D0) | |
1317 | #define SPR_DCMP (0x3D1) | |
1318 | #define SPR_HASH1 (0x3D2) | |
1319 | #define SPR_HASH2 (0x3D3) | |
1320 | #define SPR_BOOKE_ICDBDR (0x3D3) | |
1321 | #define SPR_TLBMISS (0x3D4) | |
1322 | #define SPR_IMISS (0x3D4) | |
1323 | #define SPR_40x_ESR (0x3D4) | |
1324 | #define SPR_PTEHI (0x3D5) | |
1325 | #define SPR_ICMP (0x3D5) | |
1326 | #define SPR_40x_DEAR (0x3D5) | |
1327 | #define SPR_PTELO (0x3D6) | |
1328 | #define SPR_RPA (0x3D6) | |
1329 | #define SPR_40x_EVPR (0x3D6) | |
1330 | #define SPR_L3PM (0x3D7) | |
1331 | #define SPR_403_CDBCR (0x3D7) | |
4e777442 | 1332 | #define SPR_L3ITCR0 (0x3D8) |
80d11f44 JM |
1333 | #define SPR_TCR (0x3D8) |
1334 | #define SPR_40x_TSR (0x3D8) | |
1335 | #define SPR_IBR (0x3DA) | |
1336 | #define SPR_40x_TCR (0x3DA) | |
1337 | #define SPR_ESASRR (0x3DB) | |
1338 | #define SPR_40x_PIT (0x3DB) | |
1339 | #define SPR_403_TBL (0x3DC) | |
1340 | #define SPR_403_TBU (0x3DD) | |
1341 | #define SPR_SEBR (0x3DE) | |
1342 | #define SPR_40x_SRR2 (0x3DE) | |
1343 | #define SPR_SER (0x3DF) | |
1344 | #define SPR_40x_SRR3 (0x3DF) | |
4e777442 | 1345 | #define SPR_L3OHCR (0x3E8) |
80d11f44 JM |
1346 | #define SPR_L3ITCR1 (0x3E9) |
1347 | #define SPR_L3ITCR2 (0x3EA) | |
1348 | #define SPR_L3ITCR3 (0x3EB) | |
1349 | #define SPR_HID0 (0x3F0) | |
1350 | #define SPR_40x_DBSR (0x3F0) | |
1351 | #define SPR_HID1 (0x3F1) | |
1352 | #define SPR_IABR (0x3F2) | |
1353 | #define SPR_40x_DBCR0 (0x3F2) | |
1354 | #define SPR_601_HID2 (0x3F2) | |
1355 | #define SPR_Exxx_L1CSR0 (0x3F2) | |
1356 | #define SPR_ICTRL (0x3F3) | |
1357 | #define SPR_HID2 (0x3F3) | |
bd928eba | 1358 | #define SPR_750CL_HID4 (0x3F3) |
80d11f44 JM |
1359 | #define SPR_Exxx_L1CSR1 (0x3F3) |
1360 | #define SPR_440_DBDR (0x3F3) | |
1361 | #define SPR_LDSTDB (0x3F4) | |
bd928eba | 1362 | #define SPR_750_TDCL (0x3F4) |
80d11f44 JM |
1363 | #define SPR_40x_IAC1 (0x3F4) |
1364 | #define SPR_MMUCSR0 (0x3F4) | |
1365 | #define SPR_DABR (0x3F5) | |
3fc6c082 | 1366 | #define DABR_MASK (~(target_ulong)0x7) |
80d11f44 JM |
1367 | #define SPR_Exxx_BUCSR (0x3F5) |
1368 | #define SPR_40x_IAC2 (0x3F5) | |
1369 | #define SPR_601_HID5 (0x3F5) | |
1370 | #define SPR_40x_DAC1 (0x3F6) | |
1371 | #define SPR_MSSCR0 (0x3F6) | |
1372 | #define SPR_970_HID5 (0x3F6) | |
1373 | #define SPR_MSSSR0 (0x3F7) | |
4e777442 | 1374 | #define SPR_MSSCR1 (0x3F7) |
80d11f44 JM |
1375 | #define SPR_DABRX (0x3F7) |
1376 | #define SPR_40x_DAC2 (0x3F7) | |
1377 | #define SPR_MMUCFG (0x3F7) | |
1378 | #define SPR_LDSTCR (0x3F8) | |
1379 | #define SPR_L2PMCR (0x3F8) | |
bd928eba | 1380 | #define SPR_750FX_HID2 (0x3F8) |
082c6681 | 1381 | #define SPR_620_BUSCSR (0x3F8) |
80d11f44 JM |
1382 | #define SPR_Exxx_L1FINV0 (0x3F8) |
1383 | #define SPR_L2CR (0x3F9) | |
082c6681 | 1384 | #define SPR_620_L2CR (0x3F9) |
80d11f44 | 1385 | #define SPR_L3CR (0x3FA) |
bd928eba | 1386 | #define SPR_750_TDCH (0x3FA) |
80d11f44 JM |
1387 | #define SPR_IABR2 (0x3FA) |
1388 | #define SPR_40x_DCCR (0x3FA) | |
082c6681 | 1389 | #define SPR_620_L2SR (0x3FA) |
80d11f44 JM |
1390 | #define SPR_ICTC (0x3FB) |
1391 | #define SPR_40x_ICCR (0x3FB) | |
1392 | #define SPR_THRM1 (0x3FC) | |
1393 | #define SPR_403_PBL1 (0x3FC) | |
1394 | #define SPR_SP (0x3FD) | |
1395 | #define SPR_THRM2 (0x3FD) | |
1396 | #define SPR_403_PBU1 (0x3FD) | |
1397 | #define SPR_604_HID13 (0x3FD) | |
1398 | #define SPR_LT (0x3FE) | |
1399 | #define SPR_THRM3 (0x3FE) | |
1400 | #define SPR_RCPU_FPECR (0x3FE) | |
1401 | #define SPR_403_PBL2 (0x3FE) | |
1402 | #define SPR_PIR (0x3FF) | |
1403 | #define SPR_403_PBU2 (0x3FF) | |
1404 | #define SPR_601_HID15 (0x3FF) | |
1405 | #define SPR_604_HID15 (0x3FF) | |
1406 | #define SPR_E500_SVR (0x3FF) | |
79aceca5 | 1407 | |
c29b735c NF |
1408 | /*****************************************************************************/ |
1409 | /* PowerPC Instructions types definitions */ | |
1410 | enum { | |
1411 | PPC_NONE = 0x0000000000000000ULL, | |
1412 | /* PowerPC base instructions set */ | |
1413 | PPC_INSNS_BASE = 0x0000000000000001ULL, | |
1414 | /* integer operations instructions */ | |
1415 | #define PPC_INTEGER PPC_INSNS_BASE | |
1416 | /* flow control instructions */ | |
1417 | #define PPC_FLOW PPC_INSNS_BASE | |
1418 | /* virtual memory instructions */ | |
1419 | #define PPC_MEM PPC_INSNS_BASE | |
1420 | /* ld/st with reservation instructions */ | |
1421 | #define PPC_RES PPC_INSNS_BASE | |
1422 | /* spr/msr access instructions */ | |
1423 | #define PPC_MISC PPC_INSNS_BASE | |
1424 | /* Deprecated instruction sets */ | |
1425 | /* Original POWER instruction set */ | |
1426 | PPC_POWER = 0x0000000000000002ULL, | |
1427 | /* POWER2 instruction set extension */ | |
1428 | PPC_POWER2 = 0x0000000000000004ULL, | |
1429 | /* Power RTC support */ | |
1430 | PPC_POWER_RTC = 0x0000000000000008ULL, | |
1431 | /* Power-to-PowerPC bridge (601) */ | |
1432 | PPC_POWER_BR = 0x0000000000000010ULL, | |
1433 | /* 64 bits PowerPC instruction set */ | |
1434 | PPC_64B = 0x0000000000000020ULL, | |
1435 | /* New 64 bits extensions (PowerPC 2.0x) */ | |
1436 | PPC_64BX = 0x0000000000000040ULL, | |
1437 | /* 64 bits hypervisor extensions */ | |
1438 | PPC_64H = 0x0000000000000080ULL, | |
1439 | /* New wait instruction (PowerPC 2.0x) */ | |
1440 | PPC_WAIT = 0x0000000000000100ULL, | |
1441 | /* Time base mftb instruction */ | |
1442 | PPC_MFTB = 0x0000000000000200ULL, | |
1443 | ||
1444 | /* Fixed-point unit extensions */ | |
1445 | /* PowerPC 602 specific */ | |
1446 | PPC_602_SPEC = 0x0000000000000400ULL, | |
1447 | /* isel instruction */ | |
1448 | PPC_ISEL = 0x0000000000000800ULL, | |
1449 | /* popcntb instruction */ | |
1450 | PPC_POPCNTB = 0x0000000000001000ULL, | |
1451 | /* string load / store */ | |
1452 | PPC_STRING = 0x0000000000002000ULL, | |
1453 | ||
1454 | /* Floating-point unit extensions */ | |
1455 | /* Optional floating point instructions */ | |
1456 | PPC_FLOAT = 0x0000000000010000ULL, | |
1457 | /* New floating-point extensions (PowerPC 2.0x) */ | |
1458 | PPC_FLOAT_EXT = 0x0000000000020000ULL, | |
1459 | PPC_FLOAT_FSQRT = 0x0000000000040000ULL, | |
1460 | PPC_FLOAT_FRES = 0x0000000000080000ULL, | |
1461 | PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, | |
1462 | PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, | |
1463 | PPC_FLOAT_FSEL = 0x0000000000400000ULL, | |
1464 | PPC_FLOAT_STFIWX = 0x0000000000800000ULL, | |
1465 | ||
1466 | /* Vector/SIMD extensions */ | |
1467 | /* Altivec support */ | |
1468 | PPC_ALTIVEC = 0x0000000001000000ULL, | |
1469 | /* PowerPC 2.03 SPE extension */ | |
1470 | PPC_SPE = 0x0000000002000000ULL, | |
1471 | /* PowerPC 2.03 SPE single-precision floating-point extension */ | |
1472 | PPC_SPE_SINGLE = 0x0000000004000000ULL, | |
1473 | /* PowerPC 2.03 SPE double-precision floating-point extension */ | |
1474 | PPC_SPE_DOUBLE = 0x0000000008000000ULL, | |
1475 | ||
1476 | /* Optional memory control instructions */ | |
1477 | PPC_MEM_TLBIA = 0x0000000010000000ULL, | |
1478 | PPC_MEM_TLBIE = 0x0000000020000000ULL, | |
1479 | PPC_MEM_TLBSYNC = 0x0000000040000000ULL, | |
1480 | /* sync instruction */ | |
1481 | PPC_MEM_SYNC = 0x0000000080000000ULL, | |
1482 | /* eieio instruction */ | |
1483 | PPC_MEM_EIEIO = 0x0000000100000000ULL, | |
1484 | ||
1485 | /* Cache control instructions */ | |
1486 | PPC_CACHE = 0x0000000200000000ULL, | |
1487 | /* icbi instruction */ | |
1488 | PPC_CACHE_ICBI = 0x0000000400000000ULL, | |
1489 | /* dcbz instruction with fixed cache line size */ | |
1490 | PPC_CACHE_DCBZ = 0x0000000800000000ULL, | |
1491 | /* dcbz instruction with tunable cache line size */ | |
1492 | PPC_CACHE_DCBZT = 0x0000001000000000ULL, | |
1493 | /* dcba instruction */ | |
1494 | PPC_CACHE_DCBA = 0x0000002000000000ULL, | |
1495 | /* Freescale cache locking instructions */ | |
1496 | PPC_CACHE_LOCK = 0x0000004000000000ULL, | |
1497 | ||
1498 | /* MMU related extensions */ | |
1499 | /* external control instructions */ | |
1500 | PPC_EXTERN = 0x0000010000000000ULL, | |
1501 | /* segment register access instructions */ | |
1502 | PPC_SEGMENT = 0x0000020000000000ULL, | |
1503 | /* PowerPC 6xx TLB management instructions */ | |
1504 | PPC_6xx_TLB = 0x0000040000000000ULL, | |
1505 | /* PowerPC 74xx TLB management instructions */ | |
1506 | PPC_74xx_TLB = 0x0000080000000000ULL, | |
1507 | /* PowerPC 40x TLB management instructions */ | |
1508 | PPC_40x_TLB = 0x0000100000000000ULL, | |
1509 | /* segment register access instructions for PowerPC 64 "bridge" */ | |
1510 | PPC_SEGMENT_64B = 0x0000200000000000ULL, | |
1511 | /* SLB management */ | |
1512 | PPC_SLBI = 0x0000400000000000ULL, | |
1513 | ||
1514 | /* Embedded PowerPC dedicated instructions */ | |
1515 | PPC_WRTEE = 0x0001000000000000ULL, | |
1516 | /* PowerPC 40x exception model */ | |
1517 | PPC_40x_EXCP = 0x0002000000000000ULL, | |
1518 | /* PowerPC 405 Mac instructions */ | |
1519 | PPC_405_MAC = 0x0004000000000000ULL, | |
1520 | /* PowerPC 440 specific instructions */ | |
1521 | PPC_440_SPEC = 0x0008000000000000ULL, | |
1522 | /* BookE (embedded) PowerPC specification */ | |
1523 | PPC_BOOKE = 0x0010000000000000ULL, | |
1524 | /* mfapidi instruction */ | |
1525 | PPC_MFAPIDI = 0x0020000000000000ULL, | |
1526 | /* tlbiva instruction */ | |
1527 | PPC_TLBIVA = 0x0040000000000000ULL, | |
1528 | /* tlbivax instruction */ | |
1529 | PPC_TLBIVAX = 0x0080000000000000ULL, | |
1530 | /* PowerPC 4xx dedicated instructions */ | |
1531 | PPC_4xx_COMMON = 0x0100000000000000ULL, | |
1532 | /* PowerPC 40x ibct instructions */ | |
1533 | PPC_40x_ICBT = 0x0200000000000000ULL, | |
1534 | /* rfmci is not implemented in all BookE PowerPC */ | |
1535 | PPC_RFMCI = 0x0400000000000000ULL, | |
1536 | /* rfdi instruction */ | |
1537 | PPC_RFDI = 0x0800000000000000ULL, | |
1538 | /* DCR accesses */ | |
1539 | PPC_DCR = 0x1000000000000000ULL, | |
1540 | /* DCR extended accesse */ | |
1541 | PPC_DCRX = 0x2000000000000000ULL, | |
1542 | /* user-mode DCR access, implemented in PowerPC 460 */ | |
1543 | PPC_DCRUX = 0x4000000000000000ULL, | |
eaabeef2 DG |
1544 | /* popcntw and popcntd instructions */ |
1545 | PPC_POPCNTWD = 0x8000000000000000ULL, | |
c29b735c NF |
1546 | }; |
1547 | ||
76a66253 | 1548 | /*****************************************************************************/ |
9a64fbe4 FB |
1549 | /* Memory access type : |
1550 | * may be needed for precise access rights control and precise exceptions. | |
1551 | */ | |
79aceca5 | 1552 | enum { |
9a64fbe4 FB |
1553 | /* 1 bit to define user level / supervisor access */ |
1554 | ACCESS_USER = 0x00, | |
1555 | ACCESS_SUPER = 0x01, | |
1556 | /* Type of instruction that generated the access */ | |
1557 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
1558 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
1559 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
1560 | ACCESS_RES = 0x40, /* load/store with reservation */ | |
1561 | ACCESS_EXT = 0x50, /* external access */ | |
1562 | ACCESS_CACHE = 0x60, /* Cache manipulation */ | |
1563 | }; | |
1564 | ||
47103572 JM |
1565 | /* Hardware interruption sources: |
1566 | * all those exception can be raised simulteaneously | |
1567 | */ | |
e9df014c JM |
1568 | /* Input pins definitions */ |
1569 | enum { | |
1570 | /* 6xx bus input pins */ | |
24be5ae3 JM |
1571 | PPC6xx_INPUT_HRESET = 0, |
1572 | PPC6xx_INPUT_SRESET = 1, | |
1573 | PPC6xx_INPUT_CKSTP_IN = 2, | |
1574 | PPC6xx_INPUT_MCP = 3, | |
1575 | PPC6xx_INPUT_SMI = 4, | |
1576 | PPC6xx_INPUT_INT = 5, | |
d68f1306 JM |
1577 | PPC6xx_INPUT_TBEN = 6, |
1578 | PPC6xx_INPUT_WAKEUP = 7, | |
1579 | PPC6xx_INPUT_NB, | |
24be5ae3 JM |
1580 | }; |
1581 | ||
1582 | enum { | |
e9df014c | 1583 | /* Embedded PowerPC input pins */ |
24be5ae3 JM |
1584 | PPCBookE_INPUT_HRESET = 0, |
1585 | PPCBookE_INPUT_SRESET = 1, | |
1586 | PPCBookE_INPUT_CKSTP_IN = 2, | |
1587 | PPCBookE_INPUT_MCP = 3, | |
1588 | PPCBookE_INPUT_SMI = 4, | |
1589 | PPCBookE_INPUT_INT = 5, | |
1590 | PPCBookE_INPUT_CINT = 6, | |
d68f1306 | 1591 | PPCBookE_INPUT_NB, |
24be5ae3 JM |
1592 | }; |
1593 | ||
9fdc60bf AJ |
1594 | enum { |
1595 | /* PowerPC E500 input pins */ | |
1596 | PPCE500_INPUT_RESET_CORE = 0, | |
1597 | PPCE500_INPUT_MCK = 1, | |
1598 | PPCE500_INPUT_CINT = 3, | |
1599 | PPCE500_INPUT_INT = 4, | |
1600 | PPCE500_INPUT_DEBUG = 6, | |
1601 | PPCE500_INPUT_NB, | |
1602 | }; | |
1603 | ||
a750fc0b | 1604 | enum { |
4e290a0b JM |
1605 | /* PowerPC 40x input pins */ |
1606 | PPC40x_INPUT_RESET_CORE = 0, | |
1607 | PPC40x_INPUT_RESET_CHIP = 1, | |
1608 | PPC40x_INPUT_RESET_SYS = 2, | |
1609 | PPC40x_INPUT_CINT = 3, | |
1610 | PPC40x_INPUT_INT = 4, | |
1611 | PPC40x_INPUT_HALT = 5, | |
1612 | PPC40x_INPUT_DEBUG = 6, | |
1613 | PPC40x_INPUT_NB, | |
e9df014c JM |
1614 | }; |
1615 | ||
b4095fed JM |
1616 | enum { |
1617 | /* RCPU input pins */ | |
1618 | PPCRCPU_INPUT_PORESET = 0, | |
1619 | PPCRCPU_INPUT_HRESET = 1, | |
1620 | PPCRCPU_INPUT_SRESET = 2, | |
1621 | PPCRCPU_INPUT_IRQ0 = 3, | |
1622 | PPCRCPU_INPUT_IRQ1 = 4, | |
1623 | PPCRCPU_INPUT_IRQ2 = 5, | |
1624 | PPCRCPU_INPUT_IRQ3 = 6, | |
1625 | PPCRCPU_INPUT_IRQ4 = 7, | |
1626 | PPCRCPU_INPUT_IRQ5 = 8, | |
1627 | PPCRCPU_INPUT_IRQ6 = 9, | |
1628 | PPCRCPU_INPUT_IRQ7 = 10, | |
1629 | PPCRCPU_INPUT_NB, | |
1630 | }; | |
1631 | ||
00af685f | 1632 | #if defined(TARGET_PPC64) |
d0dfae6e JM |
1633 | enum { |
1634 | /* PowerPC 970 input pins */ | |
1635 | PPC970_INPUT_HRESET = 0, | |
1636 | PPC970_INPUT_SRESET = 1, | |
1637 | PPC970_INPUT_CKSTP = 2, | |
1638 | PPC970_INPUT_TBEN = 3, | |
1639 | PPC970_INPUT_MCP = 4, | |
1640 | PPC970_INPUT_INT = 5, | |
1641 | PPC970_INPUT_THINT = 6, | |
7b62a955 | 1642 | PPC970_INPUT_NB, |
9d52e907 DG |
1643 | }; |
1644 | ||
1645 | enum { | |
1646 | /* POWER7 input pins */ | |
1647 | POWER7_INPUT_INT = 0, | |
1648 | /* POWER7 probably has other inputs, but we don't care about them | |
1649 | * for any existing machine. We can wire these up when we need | |
1650 | * them */ | |
1651 | POWER7_INPUT_NB, | |
d0dfae6e | 1652 | }; |
00af685f | 1653 | #endif |
d0dfae6e | 1654 | |
e9df014c | 1655 | /* Hardware exceptions definitions */ |
47103572 | 1656 | enum { |
e9df014c | 1657 | /* External hardware exception sources */ |
e1833e1f | 1658 | PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
d68f1306 JM |
1659 | PPC_INTERRUPT_WAKEUP, /* Wakeup exception */ |
1660 | PPC_INTERRUPT_MCK, /* Machine check exception */ | |
1661 | PPC_INTERRUPT_EXT, /* External interrupt */ | |
1662 | PPC_INTERRUPT_SMI, /* System management interrupt */ | |
1663 | PPC_INTERRUPT_CEXT, /* Critical external interrupt */ | |
1664 | PPC_INTERRUPT_DEBUG, /* External debug exception */ | |
1665 | PPC_INTERRUPT_THERM, /* Thermal exception */ | |
e9df014c | 1666 | /* Internal hardware exception sources */ |
d68f1306 JM |
1667 | PPC_INTERRUPT_DECR, /* Decrementer exception */ |
1668 | PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */ | |
1669 | PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */ | |
1670 | PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */ | |
1671 | PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */ | |
1672 | PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */ | |
1673 | PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */ | |
1674 | PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ | |
47103572 JM |
1675 | }; |
1676 | ||
9a64fbe4 FB |
1677 | /*****************************************************************************/ |
1678 | ||
6b917547 AL |
1679 | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
1680 | target_ulong *cs_base, int *flags) | |
1681 | { | |
1682 | *pc = env->nip; | |
1683 | *cs_base = 0; | |
1684 | *flags = env->hflags; | |
1685 | } | |
1686 | ||
174c80d5 NF |
1687 | static inline void cpu_set_tls(CPUState *env, target_ulong newtls) |
1688 | { | |
1689 | #if defined(TARGET_PPC64) | |
1690 | /* The kernel checks TIF_32BIT here; we don't support loading 32-bit | |
1691 | binaries on PPC64 yet. */ | |
1692 | env->gpr[13] = newtls; | |
1693 | #else | |
1694 | env->gpr[2] = newtls; | |
1695 | #endif | |
1696 | } | |
1697 | ||
d569956e DG |
1698 | extern void (*cpu_ppc_hypercall)(CPUState *); |
1699 | ||
79aceca5 | 1700 | #endif /* !defined (__CPU_PPC_H__) */ |