projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 79aceca5 | 1 | /* |
| 3fc6c082 | 2 | * PowerPC emulation cpu definitions for qemu. |
| 5fafdf24 | 3 | * |
| 76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
| 79aceca5 FB |
5 | * |
| 6 | * This library is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU Lesser General Public | |
| 8 | * License as published by the Free Software Foundation; either | |
| 9 | * version 2 of the License, or (at your option) any later version. | |
| 10 | * | |
| 11 | * This library is distributed in the hope that it will be useful, | |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | * Lesser General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU Lesser General Public | |
| 17 | * License along with this library; if not, write to the Free Software | |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 19 | */ | |
| 20 | #if !defined (__CPU_PPC_H__) | |
| 21 | #define __CPU_PPC_H__ | |
| 22 | ||
| 3fc6c082 | 23 | #include "config.h" |
| de270b3c | 24 | #include <inttypes.h> |
| 3fc6c082 | 25 | |
| 76a66253 JM |
26 | #if defined (TARGET_PPC64) |
| 27 | typedef uint64_t ppc_gpr_t; | |
| 0487d6a8 | 28 | #define TARGET_GPR_BITS 64 |
| d9d7210c | 29 | #define TARGET_LONG_BITS 64 |
| 76a66253 | 30 | #define REGX "%016" PRIx64 |
| 35cdaad6 JM |
31 | #define TARGET_PAGE_BITS 12 |
| 32 | #elif defined(TARGET_PPCEMB) | |
| 8b67546f | 33 | /* BookE have 36 bits physical address space */ |
| e96efcfc | 34 | #define TARGET_PHYS_ADDR_BITS 64 |
| 76a66253 JM |
35 | /* GPR are 64 bits: used by vector extension */ |
| 36 | typedef uint64_t ppc_gpr_t; | |
| 0487d6a8 | 37 | #define TARGET_GPR_BITS 64 |
| d9d7210c | 38 | #define TARGET_LONG_BITS 32 |
| 1b9eb036 | 39 | #define REGX "%016" PRIx64 |
| d9d7210c JM |
40 | #if defined(CONFIG_USER_ONLY) |
| 41 | /* It looks like a lot of Linux programs assume page size | |
| 42 | * is 4kB long. This is evil, but we have to deal with it... | |
| 43 | */ | |
| 44 | #define TARGET_PAGE_BITS 12 | |
| 45 | #else | |
| 35cdaad6 JM |
46 | /* Pages can be 1 kB small */ |
| 47 | #define TARGET_PAGE_BITS 10 | |
| d9d7210c JM |
48 | #endif |
| 49 | #else | |
| 50 | #if (HOST_LONG_BITS >= 64) | |
| 51 | /* When using 64 bits temporary registers, | |
| 52 | * we can use 64 bits GPR with no extra cost | |
| 53 | * It's even an optimization as it will prevent | |
| 54 | * the compiler to do unuseful masking in the micro-ops. | |
| 55 | */ | |
| 56 | typedef uint64_t ppc_gpr_t; | |
| 57 | #define TARGET_GPR_BITS 64 | |
| 71c8b8fd | 58 | #define REGX "%08" PRIx64 |
| 76a66253 JM |
59 | #else |
| 60 | typedef uint32_t ppc_gpr_t; | |
| 0487d6a8 | 61 | #define TARGET_GPR_BITS 32 |
| 71c8b8fd | 62 | #define REGX "%08" PRIx32 |
| d9d7210c JM |
63 | #endif |
| 64 | #define TARGET_LONG_BITS 32 | |
| 35cdaad6 | 65 | #define TARGET_PAGE_BITS 12 |
| 76a66253 | 66 | #endif |
| 3cf1e035 | 67 | |
| 79aceca5 FB |
68 | #include "cpu-defs.h" |
| 69 | ||
| e96efcfc JM |
70 | #define ADDRX TARGET_FMT_lx |
| 71 | #define PADDRX TARGET_FMT_plx | |
| 72 | ||
| 79aceca5 FB |
73 | #include <setjmp.h> |
| 74 | ||
| 4ecc3190 FB |
75 | #include "softfloat.h" |
| 76 | ||
| 1fddef4b FB |
77 | #define TARGET_HAS_ICE 1 |
| 78 | ||
| 76a66253 JM |
79 | #if defined (TARGET_PPC64) |
| 80 | #define ELF_MACHINE EM_PPC64 | |
| 81 | #else | |
| 82 | #define ELF_MACHINE EM_PPC | |
| 83 | #endif | |
| 9042c0e2 | 84 | |
| fdabc366 FB |
85 | /* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC |
| 86 | * have different cache line sizes | |
| 87 | */ | |
| 88 | #define ICACHE_LINE_SIZE 32 | |
| 89 | #define DCACHE_LINE_SIZE 32 | |
| 90 | ||
| 3fc6c082 | 91 | /*****************************************************************************/ |
| a750fc0b | 92 | /* MMU model */ |
| 3fc6c082 | 93 | enum { |
| a750fc0b JM |
94 | POWERPC_MMU_UNKNOWN = 0, |
| 95 | /* Standard 32 bits PowerPC MMU */ | |
| 96 | POWERPC_MMU_32B, | |
| a750fc0b JM |
97 | /* PowerPC 601 MMU */ |
| 98 | POWERPC_MMU_601, | |
| 99 | /* PowerPC 6xx MMU with software TLB */ | |
| 100 | POWERPC_MMU_SOFT_6xx, | |
| 101 | /* PowerPC 74xx MMU with software TLB */ | |
| 102 | POWERPC_MMU_SOFT_74xx, | |
| 103 | /* PowerPC 4xx MMU with software TLB */ | |
| 104 | POWERPC_MMU_SOFT_4xx, | |
| 105 | /* PowerPC 4xx MMU with software TLB and zones protections */ | |
| 106 | POWERPC_MMU_SOFT_4xx_Z, | |
| 107 | /* PowerPC 4xx MMU in real mode only */ | |
| 108 | POWERPC_MMU_REAL_4xx, | |
| 109 | /* BookE MMU model */ | |
| 110 | POWERPC_MMU_BOOKE, | |
| 111 | /* BookE FSL MMU model */ | |
| 112 | POWERPC_MMU_BOOKE_FSL, | |
| 00af685f JM |
113 | #if defined(TARGET_PPC64) |
| 114 | /* Standard 64 bits PowerPC MMU */ | |
| 115 | POWERPC_MMU_64B, | |
| a750fc0b JM |
116 | /* 64 bits "bridge" PowerPC MMU */ |
| 117 | POWERPC_MMU_64BRIDGE, | |
| 00af685f | 118 | #endif /* defined(TARGET_PPC64) */ |
| 3fc6c082 FB |
119 | }; |
| 120 | ||
| 121 | /*****************************************************************************/ | |
| a750fc0b | 122 | /* Exception model */ |
| 3fc6c082 | 123 | enum { |
| a750fc0b | 124 | POWERPC_EXCP_UNKNOWN = 0, |
| 3fc6c082 | 125 | /* Standard PowerPC exception model */ |
| a750fc0b | 126 | POWERPC_EXCP_STD, |
| 2662a059 | 127 | /* PowerPC 40x exception model */ |
| a750fc0b | 128 | POWERPC_EXCP_40x, |
| 2662a059 | 129 | /* PowerPC 601 exception model */ |
| a750fc0b | 130 | POWERPC_EXCP_601, |
| 2662a059 | 131 | /* PowerPC 602 exception model */ |
| a750fc0b | 132 | POWERPC_EXCP_602, |
| 2662a059 | 133 | /* PowerPC 603 exception model */ |
| a750fc0b JM |
134 | POWERPC_EXCP_603, |
| 135 | /* PowerPC 603e exception model */ | |
| 136 | POWERPC_EXCP_603E, | |
| 137 | /* PowerPC G2 exception model */ | |
| 138 | POWERPC_EXCP_G2, | |
| 2662a059 | 139 | /* PowerPC 604 exception model */ |
| a750fc0b | 140 | POWERPC_EXCP_604, |
| 2662a059 | 141 | /* PowerPC 7x0 exception model */ |
| a750fc0b | 142 | POWERPC_EXCP_7x0, |
| 2662a059 | 143 | /* PowerPC 7x5 exception model */ |
| a750fc0b | 144 | POWERPC_EXCP_7x5, |
| 2662a059 | 145 | /* PowerPC 74xx exception model */ |
| a750fc0b | 146 | POWERPC_EXCP_74xx, |
| 2662a059 | 147 | /* BookE exception model */ |
| a750fc0b | 148 | POWERPC_EXCP_BOOKE, |
| 00af685f JM |
149 | #if defined(TARGET_PPC64) |
| 150 | /* PowerPC 970 exception model */ | |
| 151 | POWERPC_EXCP_970, | |
| 152 | #endif /* defined(TARGET_PPC64) */ | |
| a750fc0b JM |
153 | }; |
| 154 | ||
| e1833e1f JM |
155 | /*****************************************************************************/ |
| 156 | /* Exception vectors definitions */ | |
| 157 | enum { | |
| 158 | POWERPC_EXCP_NONE = -1, | |
| 159 | /* The 64 first entries are used by the PowerPC embedded specification */ | |
| 160 | POWERPC_EXCP_CRITICAL = 0, /* Critical input */ | |
| 161 | POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ | |
| 162 | POWERPC_EXCP_DSI = 2, /* Data storage exception */ | |
| 163 | POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ | |
| 164 | POWERPC_EXCP_EXTERNAL = 4, /* External input */ | |
| 165 | POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ | |
| 166 | POWERPC_EXCP_PROGRAM = 6, /* Program exception */ | |
| 167 | POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ | |
| 168 | POWERPC_EXCP_SYSCALL = 8, /* System call exception */ | |
| 169 | POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ | |
| 170 | POWERPC_EXCP_DECR = 10, /* Decrementer exception */ | |
| 171 | POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ | |
| 172 | POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ | |
| 173 | POWERPC_EXCP_DTLB = 13, /* Data TLB error */ | |
| 174 | POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */ | |
| 175 | POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ | |
| 176 | /* Vectors 16 to 31 are reserved */ | |
| 177 | #if defined(TARGET_PPCEMB) | |
| 178 | POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ | |
| 179 | POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ | |
| 180 | POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ | |
| 181 | POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ | |
| 182 | POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ | |
| 183 | POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ | |
| 184 | #endif /* defined(TARGET_PPCEMB) */ | |
| 185 | /* Vectors 38 to 63 are reserved */ | |
| 186 | /* Exceptions defined in the PowerPC server specification */ | |
| 187 | POWERPC_EXCP_RESET = 64, /* System reset exception */ | |
| 188 | #if defined(TARGET_PPC64) /* PowerPC 64 */ | |
| 189 | POWERPC_EXCP_DSEG = 65, /* Data segment exception */ | |
| 190 | POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ | |
| 191 | #endif /* defined(TARGET_PPC64) */ | |
| 192 | #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ | |
| 193 | POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ | |
| 194 | #endif /* defined(TARGET_PPC64H) */ | |
| 195 | POWERPC_EXCP_TRACE = 68, /* Trace exception */ | |
| 196 | #if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ | |
| 197 | POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ | |
| 198 | POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ | |
| 199 | POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ | |
| 200 | POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ | |
| 201 | #endif /* defined(TARGET_PPC64H) */ | |
| 202 | POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ | |
| 203 | /* 40x specific exceptions */ | |
| 204 | POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ | |
| 205 | /* 601 specific exceptions */ | |
| 206 | POWERPC_EXCP_IO = 75, /* IO error exception */ | |
| 207 | POWERPC_EXCP_RUNM = 76, /* Run mode exception */ | |
| 208 | /* 602 specific exceptions */ | |
| 209 | POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ | |
| 210 | /* 602/603 specific exceptions */ | |
| 211 | POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */ | |
| 212 | POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ | |
| 213 | POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ | |
| 214 | /* Exceptions available on most PowerPC */ | |
| 215 | POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ | |
| 216 | POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */ | |
| 217 | POWERPC_EXCP_SMI = 83, /* System management interrupt */ | |
| 218 | POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */ | |
| 219 | /* 7xx/74xx specific exceptions */ | |
| 220 | POWERPC_EXCP_THERM = 85, /* Thermal interrupt */ | |
| 221 | /* 74xx specific exceptions */ | |
| 222 | POWERPC_EXCP_VPUA = 86, /* Vector assist exception */ | |
| 223 | /* 970FX specific exceptions */ | |
| 224 | POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */ | |
| 225 | POWERPC_EXCP_MAINT = 88, /* Maintenance exception */ | |
| 226 | /* EOL */ | |
| 227 | POWERPC_EXCP_NB = 96, | |
| 228 | /* Qemu exceptions: used internally during code translation */ | |
| 229 | POWERPC_EXCP_STOP = 0x200, /* stop translation */ | |
| 230 | POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ | |
| 231 | /* Qemu exceptions: special cases we want to stop translation */ | |
| 232 | POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ | |
| 233 | POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ | |
| 234 | }; | |
| 235 | ||
| 236 | ||
| 237 | /* Exceptions error codes */ | |
| 238 | enum { | |
| 239 | /* Exception subtypes for POWERPC_EXCP_ALIGN */ | |
| 240 | POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ | |
| 241 | POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ | |
| 242 | POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ | |
| 243 | POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ | |
| 244 | POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ | |
| 245 | POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ | |
| 246 | /* Exception subtypes for POWERPC_EXCP_PROGRAM */ | |
| 247 | /* FP exceptions */ | |
| 248 | POWERPC_EXCP_FP = 0x10, | |
| 249 | POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ | |
| 250 | POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ | |
| 251 | POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ | |
| 252 | POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ | |
| 253 | POWERPC_EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ | |
| 254 | POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ | |
| 255 | POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ | |
| 256 | POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ | |
| 257 | POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ | |
| 258 | POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ | |
| 259 | POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ | |
| 260 | POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ | |
| 261 | POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ | |
| 262 | /* Invalid instruction */ | |
| 263 | POWERPC_EXCP_INVAL = 0x20, | |
| 264 | POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ | |
| 265 | POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ | |
| 266 | POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ | |
| 267 | POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ | |
| 268 | /* Privileged instruction */ | |
| 269 | POWERPC_EXCP_PRIV = 0x30, | |
| 270 | POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ | |
| 271 | POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ | |
| 272 | /* Trap */ | |
| 273 | POWERPC_EXCP_TRAP = 0x40, | |
| 274 | }; | |
| 275 | ||
| a750fc0b JM |
276 | /*****************************************************************************/ |
| 277 | /* Input pins model */ | |
| 278 | enum { | |
| 279 | PPC_FLAGS_INPUT_UNKNOWN = 0, | |
| 2662a059 | 280 | /* PowerPC 6xx bus */ |
| a750fc0b | 281 | PPC_FLAGS_INPUT_6xx, |
| 2662a059 | 282 | /* BookE bus */ |
| a750fc0b JM |
283 | PPC_FLAGS_INPUT_BookE, |
| 284 | /* PowerPC 405 bus */ | |
| 285 | PPC_FLAGS_INPUT_405, | |
| 2662a059 | 286 | /* PowerPC 970 bus */ |
| a750fc0b JM |
287 | PPC_FLAGS_INPUT_970, |
| 288 | /* PowerPC 401 bus */ | |
| 289 | PPC_FLAGS_INPUT_401, | |
| 3fc6c082 FB |
290 | }; |
| 291 | ||
| a750fc0b | 292 | #define PPC_INPUT(env) (env->bus_model) |
| 3fc6c082 | 293 | |
| be147d08 | 294 | /*****************************************************************************/ |
| 3fc6c082 | 295 | typedef struct ppc_def_t ppc_def_t; |
| a750fc0b | 296 | typedef struct opc_handler_t opc_handler_t; |
| 79aceca5 | 297 | |
| 3fc6c082 FB |
298 | /*****************************************************************************/ |
| 299 | /* Types used to describe some PowerPC registers */ | |
| 300 | typedef struct CPUPPCState CPUPPCState; | |
| 9fddaa0c | 301 | typedef struct ppc_tb_t ppc_tb_t; |
| 3fc6c082 FB |
302 | typedef struct ppc_spr_t ppc_spr_t; |
| 303 | typedef struct ppc_dcr_t ppc_dcr_t; | |
| 304 | typedef struct ppc_avr_t ppc_avr_t; | |
| 1d0a48fb | 305 | typedef union ppc_tlb_t ppc_tlb_t; |
| 76a66253 | 306 | |
| 3fc6c082 FB |
307 | /* SPR access micro-ops generations callbacks */ |
| 308 | struct ppc_spr_t { | |
| 309 | void (*uea_read)(void *opaque, int spr_num); | |
| 310 | void (*uea_write)(void *opaque, int spr_num); | |
| 76a66253 | 311 | #if !defined(CONFIG_USER_ONLY) |
| 3fc6c082 FB |
312 | void (*oea_read)(void *opaque, int spr_num); |
| 313 | void (*oea_write)(void *opaque, int spr_num); | |
| be147d08 JM |
314 | #if defined(TARGET_PPC64H) |
| 315 | void (*hea_read)(void *opaque, int spr_num); | |
| 316 | void (*hea_write)(void *opaque, int spr_num); | |
| 317 | #endif | |
| 76a66253 | 318 | #endif |
| 3fc6c082 FB |
319 | const unsigned char *name; |
| 320 | }; | |
| 321 | ||
| 322 | /* Altivec registers (128 bits) */ | |
| 323 | struct ppc_avr_t { | |
| 324 | uint32_t u[4]; | |
| 325 | }; | |
| 9fddaa0c | 326 | |
| 3fc6c082 | 327 | /* Software TLB cache */ |
| 1d0a48fb JM |
328 | typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
| 329 | struct ppc6xx_tlb_t { | |
| 76a66253 JM |
330 | target_ulong pte0; |
| 331 | target_ulong pte1; | |
| 332 | target_ulong EPN; | |
| 1d0a48fb JM |
333 | }; |
| 334 | ||
| 335 | typedef struct ppcemb_tlb_t ppcemb_tlb_t; | |
| 336 | struct ppcemb_tlb_t { | |
| c55e9aef | 337 | target_phys_addr_t RPN; |
| 1d0a48fb | 338 | target_ulong EPN; |
| 76a66253 | 339 | target_ulong PID; |
| c55e9aef JM |
340 | target_ulong size; |
| 341 | uint32_t prot; | |
| 342 | uint32_t attr; /* Storage attributes */ | |
| 1d0a48fb JM |
343 | }; |
| 344 | ||
| 345 | union ppc_tlb_t { | |
| 346 | ppc6xx_tlb_t tlb6; | |
| 347 | ppcemb_tlb_t tlbe; | |
| 3fc6c082 FB |
348 | }; |
| 349 | ||
| 350 | /*****************************************************************************/ | |
| 351 | /* Machine state register bits definition */ | |
| 76a66253 | 352 | #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
| 3fc6c082 | 353 | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
| 76a66253 | 354 | #define MSR_HV 60 /* hypervisor state hflags */ |
| 363be49c JM |
355 | #define MSR_CM 31 /* Computation mode for BookE hflags */ |
| 356 | #define MSR_ICM 30 /* Interrupt computation mode for BookE */ | |
| 357 | #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ | |
| 76a66253 | 358 | #define MSR_VR 25 /* altivec available hflags */ |
| 363be49c | 359 | #define MSR_SPE 25 /* SPE enable for BookE hflags */ |
| 76a66253 JM |
360 | #define MSR_AP 23 /* Access privilege state on 602 hflags */ |
| 361 | #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ | |
| 3fc6c082 FB |
362 | #define MSR_KEY 19 /* key bit on 603e */ |
| 363 | #define MSR_POW 18 /* Power management */ | |
| 364 | #define MSR_WE 18 /* Wait state enable on embedded PowerPC */ | |
| 365 | #define MSR_TGPR 17 /* TGPR usage on 602/603 */ | |
| 76a66253 | 366 | #define MSR_TLB 17 /* TLB update on ? */ |
| 3fc6c082 FB |
367 | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */ |
| 368 | #define MSR_ILE 16 /* Interrupt little-endian mode */ | |
| 369 | #define MSR_EE 15 /* External interrupt enable */ | |
| 76a66253 JM |
370 | #define MSR_PR 14 /* Problem state hflags */ |
| 371 | #define MSR_FP 13 /* Floating point available hflags */ | |
| 3fc6c082 | 372 | #define MSR_ME 12 /* Machine check interrupt enable */ |
| 76a66253 JM |
373 | #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
| 374 | #define MSR_SE 10 /* Single-step trace enable hflags */ | |
| 3fc6c082 | 375 | #define MSR_DWE 10 /* Debug wait enable on 405 */ |
| 76a66253 JM |
376 | #define MSR_UBLE 10 /* User BTB lock enable on e500 */ |
| 377 | #define MSR_BE 9 /* Branch trace enable hflags */ | |
| 3fc6c082 | 378 | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */ |
| 76a66253 | 379 | #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
| 3fc6c082 FB |
380 | #define MSR_AL 7 /* AL bit on POWER */ |
| 381 | #define MSR_IP 6 /* Interrupt prefix */ | |
| 382 | #define MSR_IR 5 /* Instruction relocate */ | |
| 383 | #define MSR_IS 5 /* Instruction address space on embedded PowerPC */ | |
| 384 | #define MSR_DR 4 /* Data relocate */ | |
| 385 | #define MSR_DS 4 /* Data address space on embedded PowerPC */ | |
| 386 | #define MSR_PE 3 /* Protection enable on 403 */ | |
| 387 | #define MSR_EP 3 /* Exception prefix on 601 */ | |
| 388 | #define MSR_PX 2 /* Protection exclusive on 403 */ | |
| 389 | #define MSR_PMM 2 /* Performance monitor mark on POWER */ | |
| 390 | #define MSR_RI 1 /* Recoverable interrupt */ | |
| 76a66253 | 391 | #define MSR_LE 0 /* Little-endian mode hflags */ |
| 3fc6c082 FB |
392 | #define msr_sf env->msr[MSR_SF] |
| 393 | #define msr_isf env->msr[MSR_ISF] | |
| 394 | #define msr_hv env->msr[MSR_HV] | |
| 363be49c JM |
395 | #define msr_cm env->msr[MSR_CM] |
| 396 | #define msr_icm env->msr[MSR_ICM] | |
| 76a66253 | 397 | #define msr_ucle env->msr[MSR_UCLE] |
| 3fc6c082 | 398 | #define msr_vr env->msr[MSR_VR] |
| 76a66253 | 399 | #define msr_spe env->msr[MSR_SPE] |
| 3fc6c082 FB |
400 | #define msr_ap env->msr[MSR_AP] |
| 401 | #define msr_sa env->msr[MSR_SA] | |
| 402 | #define msr_key env->msr[MSR_KEY] | |
| 76a66253 | 403 | #define msr_pow env->msr[MSR_POW] |
| 3fc6c082 FB |
404 | #define msr_we env->msr[MSR_WE] |
| 405 | #define msr_tgpr env->msr[MSR_TGPR] | |
| 406 | #define msr_tlb env->msr[MSR_TLB] | |
| 407 | #define msr_ce env->msr[MSR_CE] | |
| 76a66253 JM |
408 | #define msr_ile env->msr[MSR_ILE] |
| 409 | #define msr_ee env->msr[MSR_EE] | |
| 410 | #define msr_pr env->msr[MSR_PR] | |
| 411 | #define msr_fp env->msr[MSR_FP] | |
| 412 | #define msr_me env->msr[MSR_ME] | |
| 413 | #define msr_fe0 env->msr[MSR_FE0] | |
| 414 | #define msr_se env->msr[MSR_SE] | |
| 3fc6c082 | 415 | #define msr_dwe env->msr[MSR_DWE] |
| 76a66253 JM |
416 | #define msr_uble env->msr[MSR_UBLE] |
| 417 | #define msr_be env->msr[MSR_BE] | |
| 3fc6c082 | 418 | #define msr_de env->msr[MSR_DE] |
| 76a66253 | 419 | #define msr_fe1 env->msr[MSR_FE1] |
| 3fc6c082 | 420 | #define msr_al env->msr[MSR_AL] |
| 76a66253 JM |
421 | #define msr_ip env->msr[MSR_IP] |
| 422 | #define msr_ir env->msr[MSR_IR] | |
| 3fc6c082 | 423 | #define msr_is env->msr[MSR_IS] |
| 76a66253 | 424 | #define msr_dr env->msr[MSR_DR] |
| 3fc6c082 FB |
425 | #define msr_ds env->msr[MSR_DS] |
| 426 | #define msr_pe env->msr[MSR_PE] | |
| 427 | #define msr_ep env->msr[MSR_EP] | |
| 428 | #define msr_px env->msr[MSR_PX] | |
| 429 | #define msr_pmm env->msr[MSR_PMM] | |
| 76a66253 JM |
430 | #define msr_ri env->msr[MSR_RI] |
| 431 | #define msr_le env->msr[MSR_LE] | |
| 79aceca5 | 432 | |
| 3fc6c082 FB |
433 | /*****************************************************************************/ |
| 434 | /* The whole PowerPC CPU context */ | |
| 435 | struct CPUPPCState { | |
| 436 | /* First are the most commonly used resources | |
| 437 | * during translated code execution | |
| 438 | */ | |
| 0487d6a8 | 439 | #if TARGET_GPR_BITS > HOST_LONG_BITS |
| 3fc6c082 FB |
440 | /* temporary fixed-point registers |
| 441 | * used to emulate 64 bits target on 32 bits hosts | |
| 5fafdf24 | 442 | */ |
| 3c4c9f9f | 443 | ppc_gpr_t t0, t1, t2; |
| 3fc6c082 | 444 | #endif |
| d9bce9d9 JM |
445 | ppc_avr_t t0_avr, t1_avr, t2_avr; |
| 446 | ||
| 79aceca5 | 447 | /* general purpose registers */ |
| 76a66253 | 448 | ppc_gpr_t gpr[32]; |
| 3fc6c082 FB |
449 | /* LR */ |
| 450 | target_ulong lr; | |
| 451 | /* CTR */ | |
| 452 | target_ulong ctr; | |
| 453 | /* condition register */ | |
| 454 | uint8_t crf[8]; | |
| 79aceca5 | 455 | /* XER */ |
| 3fc6c082 FB |
456 | /* XXX: We use only 5 fields, but we want to keep the structure aligned */ |
| 457 | uint8_t xer[8]; | |
| 79aceca5 | 458 | /* Reservation address */ |
| 3fc6c082 FB |
459 | target_ulong reserve; |
| 460 | ||
| 461 | /* Those ones are used in supervisor mode only */ | |
| 79aceca5 | 462 | /* machine state register */ |
| 3fc6c082 FB |
463 | uint8_t msr[64]; |
| 464 | /* temporary general purpose registers */ | |
| 76a66253 | 465 | ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ |
| 3fc6c082 FB |
466 | |
| 467 | /* Floating point execution context */ | |
| 76a66253 | 468 | /* temporary float registers */ |
| 4ecc3190 FB |
469 | float64 ft0; |
| 470 | float64 ft1; | |
| 471 | float64 ft2; | |
| 472 | float_status fp_status; | |
| 3fc6c082 FB |
473 | /* floating point registers */ |
| 474 | float64 fpr[32]; | |
| 475 | /* floating point status and control register */ | |
| 476 | uint8_t fpscr[8]; | |
| 4ecc3190 | 477 | |
| a316d335 FB |
478 | CPU_COMMON |
| 479 | ||
| 50443c98 FB |
480 | int halted; /* TRUE if the CPU is in suspend state */ |
| 481 | ||
| ac9eb073 FB |
482 | int access_type; /* when a memory exception occurs, the access |
| 483 | type is stored here */ | |
| a541f297 | 484 | |
| 3fc6c082 FB |
485 | /* MMU context */ |
| 486 | /* Address space register */ | |
| 487 | target_ulong asr; | |
| 488 | /* segment registers */ | |
| 489 | target_ulong sdr1; | |
| 490 | target_ulong sr[16]; | |
| 491 | /* BATs */ | |
| 492 | int nb_BATs; | |
| 493 | target_ulong DBAT[2][8]; | |
| 494 | target_ulong IBAT[2][8]; | |
| 9fddaa0c | 495 | |
| 3fc6c082 FB |
496 | /* Other registers */ |
| 497 | /* Special purpose registers */ | |
| 498 | target_ulong spr[1024]; | |
| 499 | /* Altivec registers */ | |
| 500 | ppc_avr_t avr[32]; | |
| 501 | uint32_t vscr; | |
| d9bce9d9 JM |
502 | /* SPE registers */ |
| 503 | ppc_gpr_t spe_acc; | |
| 0487d6a8 | 504 | float_status spe_status; |
| d9bce9d9 | 505 | uint32_t spe_fscr; |
| 3fc6c082 FB |
506 | |
| 507 | /* Internal devices resources */ | |
| 9fddaa0c FB |
508 | /* Time base and decrementer */ |
| 509 | ppc_tb_t *tb_env; | |
| 3fc6c082 | 510 | /* Device control registers */ |
| 3fc6c082 FB |
511 | ppc_dcr_t *dcr_env; |
| 512 | ||
| 513 | /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */ | |
| 76a66253 JM |
514 | int nb_tlb; /* Total number of TLB */ |
| 515 | int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ | |
| 516 | int nb_ways; /* Number of ways in the TLB set */ | |
| 517 | int last_way; /* Last used way used to allocate TLB in a LRU way */ | |
| 518 | int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ | |
| 363be49c | 519 | int nb_pids; /* Number of available PID registers */ |
| 76a66253 | 520 | ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */ |
| 3fc6c082 FB |
521 | /* 403 dedicated access protection registers */ |
| 522 | target_ulong pb[4]; | |
| 523 | ||
| 524 | /* Those resources are used during exception processing */ | |
| 525 | /* CPU model definition */ | |
| a750fc0b JM |
526 | target_ulong msr_mask; |
| 527 | uint8_t mmu_model; | |
| 528 | uint8_t excp_model; | |
| 529 | uint8_t bus_model; | |
| 530 | uint8_t pad; | |
| 237c0af0 | 531 | int bfd_mach; |
| 3fc6c082 FB |
532 | uint32_t flags; |
| 533 | ||
| 534 | int exception_index; | |
| 535 | int error_code; | |
| 536 | int interrupt_request; | |
| 47103572 | 537 | uint32_t pending_interrupts; |
| e9df014c JM |
538 | #if !defined(CONFIG_USER_ONLY) |
| 539 | /* This is the IRQ controller, which is implementation dependant | |
| 540 | * and only relevant when emulating a complete machine. | |
| 541 | */ | |
| 542 | uint32_t irq_input_state; | |
| 543 | void **irq_inputs; | |
| e1833e1f JM |
544 | /* Exception vectors */ |
| 545 | target_ulong excp_vectors[POWERPC_EXCP_NB]; | |
| 546 | target_ulong excp_prefix; | |
| 547 | target_ulong ivor_mask; | |
| 548 | target_ulong ivpr_mask; | |
| e9df014c | 549 | #endif |
| 3fc6c082 FB |
550 | |
| 551 | /* Those resources are used only during code translation */ | |
| 552 | /* Next instruction pointer */ | |
| 553 | target_ulong nip; | |
| 554 | /* SPR translation callbacks */ | |
| 555 | ppc_spr_t spr_cb[1024]; | |
| 556 | /* opcode handlers */ | |
| 557 | opc_handler_t *opcodes[0x40]; | |
| 558 | ||
| 559 | /* Those resources are used only in Qemu core */ | |
| 560 | jmp_buf jmp_env; | |
| 561 | int user_mode_only; /* user mode only simulation */ | |
| 4296f459 | 562 | target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ |
| 3fc6c082 | 563 | |
| 9fddaa0c FB |
564 | /* Power management */ |
| 565 | int power_mode; | |
| a541f297 | 566 | |
| 6d506e6d FB |
567 | /* temporary hack to handle OSI calls (only used if non NULL) */ |
| 568 | int (*osi_call)(struct CPUPPCState *env); | |
| 3fc6c082 | 569 | }; |
| 79aceca5 | 570 | |
| 76a66253 JM |
571 | /* Context used internally during MMU translations */ |
| 572 | typedef struct mmu_ctx_t mmu_ctx_t; | |
| 573 | struct mmu_ctx_t { | |
| 574 | target_phys_addr_t raddr; /* Real address */ | |
| 575 | int prot; /* Protection bits */ | |
| 576 | target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */ | |
| 577 | target_ulong ptem; /* Virtual segment ID | API */ | |
| 578 | int key; /* Access key */ | |
| 579 | }; | |
| 580 | ||
| 3fc6c082 | 581 | /*****************************************************************************/ |
| 36081602 JM |
582 | CPUPPCState *cpu_ppc_init (void); |
| 583 | int cpu_ppc_exec (CPUPPCState *s); | |
| 584 | void cpu_ppc_close (CPUPPCState *s); | |
| 79aceca5 FB |
585 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
| 586 | signal handlers to inform the virtual CPU of exceptions. non zero | |
| 587 | is returned if the signal was handled by the virtual CPU. */ | |
| 36081602 JM |
588 | int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
| 589 | void *puc); | |
| 79aceca5 | 590 | |
| a541f297 | 591 | void do_interrupt (CPUPPCState *env); |
| e9df014c | 592 | void ppc_hw_interrupt (CPUPPCState *env); |
| 36081602 | 593 | void cpu_loop_exit (void); |
| a541f297 | 594 | |
| 9a64fbe4 | 595 | void dump_stack (CPUPPCState *env); |
| a541f297 | 596 | |
| 76a66253 | 597 | #if !defined(CONFIG_USER_ONLY) |
| 3fc6c082 FB |
598 | target_ulong do_load_ibatu (CPUPPCState *env, int nr); |
| 599 | target_ulong do_load_ibatl (CPUPPCState *env, int nr); | |
| 600 | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); | |
| 601 | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); | |
| 602 | target_ulong do_load_dbatu (CPUPPCState *env, int nr); | |
| 603 | target_ulong do_load_dbatl (CPUPPCState *env, int nr); | |
| 604 | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); | |
| 605 | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); | |
| 3fc6c082 FB |
606 | target_ulong do_load_sdr1 (CPUPPCState *env); |
| 607 | void do_store_sdr1 (CPUPPCState *env, target_ulong value); | |
| d9bce9d9 JM |
608 | #if defined(TARGET_PPC64) |
| 609 | target_ulong ppc_load_asr (CPUPPCState *env); | |
| 610 | void ppc_store_asr (CPUPPCState *env, target_ulong value); | |
| 611 | #endif | |
| 3fc6c082 FB |
612 | target_ulong do_load_sr (CPUPPCState *env, int srnum); |
| 613 | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); | |
| 76a66253 | 614 | #endif |
| bfa1e5cf JM |
615 | target_ulong ppc_load_xer (CPUPPCState *env); |
| 616 | void ppc_store_xer (CPUPPCState *env, target_ulong value); | |
| 3fc6c082 | 617 | target_ulong do_load_msr (CPUPPCState *env); |
| a97fed52 | 618 | int do_store_msr (CPUPPCState *env, target_ulong value); |
| be147d08 | 619 | #if defined(TARGET_PPC64) |
| a97fed52 | 620 | int ppc_store_msr_32 (CPUPPCState *env, uint32_t value); |
| be147d08 | 621 | #endif |
| 3fc6c082 FB |
622 | |
| 623 | void do_compute_hflags (CPUPPCState *env); | |
| 0a032cbe JM |
624 | void cpu_ppc_reset (void *opaque); |
| 625 | CPUPPCState *cpu_ppc_init (void); | |
| 626 | void cpu_ppc_close(CPUPPCState *env); | |
| a541f297 | 627 | |
| 3fc6c082 FB |
628 | int ppc_find_by_name (const unsigned char *name, ppc_def_t **def); |
| 629 | int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def); | |
| 630 | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); | |
| 631 | int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def); | |
| 85c4adf6 | 632 | |
| 9fddaa0c FB |
633 | /* Time-base and decrementer management */ |
| 634 | #ifndef NO_CPU_IO_DEFS | |
| 635 | uint32_t cpu_ppc_load_tbl (CPUPPCState *env); | |
| 636 | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); | |
| 637 | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value); | |
| 638 | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value); | |
| a062e36c JM |
639 | uint32_t cpu_ppc_load_atbl (CPUPPCState *env); |
| 640 | uint32_t cpu_ppc_load_atbu (CPUPPCState *env); | |
| 641 | void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value); | |
| 642 | void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value); | |
| 9fddaa0c FB |
643 | uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
| 644 | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value); | |
| 58a7d328 JM |
645 | #if defined(TARGET_PPC64H) |
| 646 | uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); | |
| 647 | void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value); | |
| 648 | uint64_t cpu_ppc_load_purr (CPUPPCState *env); | |
| 649 | void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value); | |
| 650 | #endif | |
| d9bce9d9 JM |
651 | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
| 652 | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); | |
| 653 | #if !defined(CONFIG_USER_ONLY) | |
| 654 | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value); | |
| 655 | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value); | |
| 656 | target_ulong load_40x_pit (CPUPPCState *env); | |
| 657 | void store_40x_pit (CPUPPCState *env, target_ulong val); | |
| 8ecc7913 | 658 | void store_40x_dbcr0 (CPUPPCState *env, uint32_t val); |
| c294fc58 | 659 | void store_40x_sler (CPUPPCState *env, uint32_t val); |
| d9bce9d9 JM |
660 | void store_booke_tcr (CPUPPCState *env, target_ulong val); |
| 661 | void store_booke_tsr (CPUPPCState *env, target_ulong val); | |
| 0a032cbe | 662 | void ppc_tlb_invalidate_all (CPUPPCState *env); |
| daf4f96e JM |
663 | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); |
| 664 | #if defined(TARGET_PPC64) | |
| 665 | void ppc_slb_invalidate_all (CPUPPCState *env); | |
| 666 | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0); | |
| 667 | #endif | |
| 36081602 | 668 | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid); |
| d9bce9d9 | 669 | #endif |
| 9fddaa0c | 670 | #endif |
| 79aceca5 | 671 | |
| 2e719ba3 JM |
672 | /* Device control registers */ |
| 673 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); | |
| 674 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); | |
| 675 | ||
| 9467d44c TS |
676 | #define CPUState CPUPPCState |
| 677 | #define cpu_init cpu_ppc_init | |
| 678 | #define cpu_exec cpu_ppc_exec | |
| 679 | #define cpu_gen_code cpu_ppc_gen_code | |
| 680 | #define cpu_signal_handler cpu_ppc_signal_handler | |
| 681 | ||
| 79aceca5 FB |
682 | #include "cpu-all.h" |
| 683 | ||
| 3fc6c082 FB |
684 | /*****************************************************************************/ |
| 685 | /* Registers definitions */ | |
| 79aceca5 FB |
686 | #define XER_SO 31 |
| 687 | #define XER_OV 30 | |
| 688 | #define XER_CA 29 | |
| 3fc6c082 | 689 | #define XER_CMP 8 |
| 36081602 | 690 | #define XER_BC 0 |
| 3fc6c082 FB |
691 | #define xer_so env->xer[4] |
| 692 | #define xer_ov env->xer[6] | |
| 693 | #define xer_ca env->xer[2] | |
| 694 | #define xer_cmp env->xer[1] | |
| 36081602 | 695 | #define xer_bc env->xer[0] |
| 79aceca5 | 696 | |
| 3fc6c082 | 697 | /* SPR definitions */ |
| 76a66253 JM |
698 | #define SPR_MQ (0x000) |
| 699 | #define SPR_XER (0x001) | |
| 700 | #define SPR_601_VRTCU (0x004) | |
| 701 | #define SPR_601_VRTCL (0x005) | |
| 702 | #define SPR_601_UDECR (0x006) | |
| 703 | #define SPR_LR (0x008) | |
| 704 | #define SPR_CTR (0x009) | |
| 705 | #define SPR_DSISR (0x012) | |
| a750fc0b | 706 | #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
| 76a66253 JM |
707 | #define SPR_601_RTCU (0x014) |
| 708 | #define SPR_601_RTCL (0x015) | |
| 709 | #define SPR_DECR (0x016) | |
| 710 | #define SPR_SDR1 (0x019) | |
| 711 | #define SPR_SRR0 (0x01A) | |
| 712 | #define SPR_SRR1 (0x01B) | |
| 2662a059 | 713 | #define SPR_AMR (0x01D) |
| 76a66253 JM |
714 | #define SPR_BOOKE_PID (0x030) |
| 715 | #define SPR_BOOKE_DECAR (0x036) | |
| 363be49c JM |
716 | #define SPR_BOOKE_CSRR0 (0x03A) |
| 717 | #define SPR_BOOKE_CSRR1 (0x03B) | |
| 76a66253 JM |
718 | #define SPR_BOOKE_DEAR (0x03D) |
| 719 | #define SPR_BOOKE_ESR (0x03E) | |
| 363be49c | 720 | #define SPR_BOOKE_IVPR (0x03F) |
| 76a66253 JM |
721 | #define SPR_8xx_EIE (0x050) |
| 722 | #define SPR_8xx_EID (0x051) | |
| 723 | #define SPR_8xx_NRE (0x052) | |
| 2662a059 | 724 | #define SPR_CTRL (0x088) |
| 76a66253 JM |
725 | #define SPR_58x_CMPA (0x090) |
| 726 | #define SPR_58x_CMPB (0x091) | |
| 727 | #define SPR_58x_CMPC (0x092) | |
| 728 | #define SPR_58x_CMPD (0x093) | |
| 729 | #define SPR_58x_ICR (0x094) | |
| 730 | #define SPR_58x_DER (0x094) | |
| 731 | #define SPR_58x_COUNTA (0x096) | |
| 732 | #define SPR_58x_COUNTB (0x097) | |
| 2662a059 | 733 | #define SPR_UCTRL (0x098) |
| 76a66253 JM |
734 | #define SPR_58x_CMPE (0x098) |
| 735 | #define SPR_58x_CMPF (0x099) | |
| 736 | #define SPR_58x_CMPG (0x09A) | |
| 737 | #define SPR_58x_CMPH (0x09B) | |
| 738 | #define SPR_58x_LCTRL1 (0x09C) | |
| 739 | #define SPR_58x_LCTRL2 (0x09D) | |
| 740 | #define SPR_58x_ICTRL (0x09E) | |
| 741 | #define SPR_58x_BAR (0x09F) | |
| 742 | #define SPR_VRSAVE (0x100) | |
| 743 | #define SPR_USPRG0 (0x100) | |
| 363be49c JM |
744 | #define SPR_USPRG1 (0x101) |
| 745 | #define SPR_USPRG2 (0x102) | |
| 746 | #define SPR_USPRG3 (0x103) | |
| 76a66253 JM |
747 | #define SPR_USPRG4 (0x104) |
| 748 | #define SPR_USPRG5 (0x105) | |
| 749 | #define SPR_USPRG6 (0x106) | |
| 750 | #define SPR_USPRG7 (0x107) | |
| 751 | #define SPR_VTBL (0x10C) | |
| 752 | #define SPR_VTBU (0x10D) | |
| 753 | #define SPR_SPRG0 (0x110) | |
| 754 | #define SPR_SPRG1 (0x111) | |
| 755 | #define SPR_SPRG2 (0x112) | |
| 756 | #define SPR_SPRG3 (0x113) | |
| 757 | #define SPR_SPRG4 (0x114) | |
| 758 | #define SPR_SCOMC (0x114) | |
| 759 | #define SPR_SPRG5 (0x115) | |
| 760 | #define SPR_SCOMD (0x115) | |
| 761 | #define SPR_SPRG6 (0x116) | |
| 762 | #define SPR_SPRG7 (0x117) | |
| 763 | #define SPR_ASR (0x118) | |
| 764 | #define SPR_EAR (0x11A) | |
| 765 | #define SPR_TBL (0x11C) | |
| 766 | #define SPR_TBU (0x11D) | |
| 2662a059 | 767 | #define SPR_TBU40 (0x11E) |
| 76a66253 JM |
768 | #define SPR_SVR (0x11E) |
| 769 | #define SPR_BOOKE_PIR (0x11E) | |
| 770 | #define SPR_PVR (0x11F) | |
| 771 | #define SPR_HSPRG0 (0x130) | |
| 772 | #define SPR_BOOKE_DBSR (0x130) | |
| 773 | #define SPR_HSPRG1 (0x131) | |
| 2662a059 JM |
774 | #define SPR_HDSISR (0x132) |
| 775 | #define SPR_HDAR (0x133) | |
| 76a66253 JM |
776 | #define SPR_BOOKE_DBCR0 (0x134) |
| 777 | #define SPR_IBCR (0x135) | |
| 2662a059 | 778 | #define SPR_PURR (0x135) |
| 76a66253 JM |
779 | #define SPR_BOOKE_DBCR1 (0x135) |
| 780 | #define SPR_DBCR (0x136) | |
| 781 | #define SPR_HDEC (0x136) | |
| 782 | #define SPR_BOOKE_DBCR2 (0x136) | |
| 783 | #define SPR_HIOR (0x137) | |
| 784 | #define SPR_MBAR (0x137) | |
| 785 | #define SPR_RMOR (0x138) | |
| 786 | #define SPR_BOOKE_IAC1 (0x138) | |
| 787 | #define SPR_HRMOR (0x139) | |
| 788 | #define SPR_BOOKE_IAC2 (0x139) | |
| e1833e1f | 789 | #define SPR_HSRR0 (0x13A) |
| 76a66253 | 790 | #define SPR_BOOKE_IAC3 (0x13A) |
| e1833e1f | 791 | #define SPR_HSRR1 (0x13B) |
| 76a66253 JM |
792 | #define SPR_BOOKE_IAC4 (0x13B) |
| 793 | #define SPR_LPCR (0x13C) | |
| 794 | #define SPR_BOOKE_DAC1 (0x13C) | |
| 795 | #define SPR_LPIDR (0x13D) | |
| 796 | #define SPR_DABR2 (0x13D) | |
| 797 | #define SPR_BOOKE_DAC2 (0x13D) | |
| 798 | #define SPR_BOOKE_DVC1 (0x13E) | |
| 799 | #define SPR_BOOKE_DVC2 (0x13F) | |
| 800 | #define SPR_BOOKE_TSR (0x150) | |
| 801 | #define SPR_BOOKE_TCR (0x154) | |
| 802 | #define SPR_BOOKE_IVOR0 (0x190) | |
| 803 | #define SPR_BOOKE_IVOR1 (0x191) | |
| 804 | #define SPR_BOOKE_IVOR2 (0x192) | |
| 805 | #define SPR_BOOKE_IVOR3 (0x193) | |
| 806 | #define SPR_BOOKE_IVOR4 (0x194) | |
| 807 | #define SPR_BOOKE_IVOR5 (0x195) | |
| 808 | #define SPR_BOOKE_IVOR6 (0x196) | |
| 809 | #define SPR_BOOKE_IVOR7 (0x197) | |
| 810 | #define SPR_BOOKE_IVOR8 (0x198) | |
| 811 | #define SPR_BOOKE_IVOR9 (0x199) | |
| 812 | #define SPR_BOOKE_IVOR10 (0x19A) | |
| 813 | #define SPR_BOOKE_IVOR11 (0x19B) | |
| 814 | #define SPR_BOOKE_IVOR12 (0x19C) | |
| 815 | #define SPR_BOOKE_IVOR13 (0x19D) | |
| 816 | #define SPR_BOOKE_IVOR14 (0x19E) | |
| 817 | #define SPR_BOOKE_IVOR15 (0x19F) | |
| 2662a059 | 818 | #define SPR_BOOKE_SPEFSCR (0x200) |
| 76a66253 JM |
819 | #define SPR_E500_BBEAR (0x201) |
| 820 | #define SPR_E500_BBTAR (0x202) | |
| a062e36c JM |
821 | #define SPR_ATBL (0x20E) |
| 822 | #define SPR_ATBU (0x20F) | |
| 76a66253 | 823 | #define SPR_IBAT0U (0x210) |
| 363be49c | 824 | #define SPR_BOOKE_IVOR32 (0x210) |
| 76a66253 | 825 | #define SPR_IBAT0L (0x211) |
| 363be49c | 826 | #define SPR_BOOKE_IVOR33 (0x211) |
| 76a66253 | 827 | #define SPR_IBAT1U (0x212) |
| 363be49c | 828 | #define SPR_BOOKE_IVOR34 (0x212) |
| 76a66253 | 829 | #define SPR_IBAT1L (0x213) |
| 363be49c | 830 | #define SPR_BOOKE_IVOR35 (0x213) |
| 76a66253 | 831 | #define SPR_IBAT2U (0x214) |
| 363be49c | 832 | #define SPR_BOOKE_IVOR36 (0x214) |
| 76a66253 JM |
833 | #define SPR_IBAT2L (0x215) |
| 834 | #define SPR_E500_L1CFG0 (0x215) | |
| 363be49c | 835 | #define SPR_BOOKE_IVOR37 (0x215) |
| 76a66253 JM |
836 | #define SPR_IBAT3U (0x216) |
| 837 | #define SPR_E500_L1CFG1 (0x216) | |
| 838 | #define SPR_IBAT3L (0x217) | |
| 839 | #define SPR_DBAT0U (0x218) | |
| 840 | #define SPR_DBAT0L (0x219) | |
| 841 | #define SPR_DBAT1U (0x21A) | |
| 842 | #define SPR_DBAT1L (0x21B) | |
| 843 | #define SPR_DBAT2U (0x21C) | |
| 844 | #define SPR_DBAT2L (0x21D) | |
| 845 | #define SPR_DBAT3U (0x21E) | |
| 846 | #define SPR_DBAT3L (0x21F) | |
| 847 | #define SPR_IBAT4U (0x230) | |
| 848 | #define SPR_IBAT4L (0x231) | |
| 849 | #define SPR_IBAT5U (0x232) | |
| 850 | #define SPR_IBAT5L (0x233) | |
| 851 | #define SPR_IBAT6U (0x234) | |
| 852 | #define SPR_IBAT6L (0x235) | |
| 853 | #define SPR_IBAT7U (0x236) | |
| 854 | #define SPR_IBAT7L (0x237) | |
| 855 | #define SPR_DBAT4U (0x238) | |
| 856 | #define SPR_DBAT4L (0x239) | |
| 857 | #define SPR_DBAT5U (0x23A) | |
| 363be49c | 858 | #define SPR_BOOKE_MCSRR0 (0x23A) |
| 76a66253 | 859 | #define SPR_DBAT5L (0x23B) |
| 363be49c | 860 | #define SPR_BOOKE_MCSRR1 (0x23B) |
| 76a66253 | 861 | #define SPR_DBAT6U (0x23C) |
| 363be49c | 862 | #define SPR_BOOKE_MCSR (0x23C) |
| 76a66253 JM |
863 | #define SPR_DBAT6L (0x23D) |
| 864 | #define SPR_E500_MCAR (0x23D) | |
| 865 | #define SPR_DBAT7U (0x23E) | |
| 363be49c | 866 | #define SPR_BOOKE_DSRR0 (0x23E) |
| 76a66253 | 867 | #define SPR_DBAT7L (0x23F) |
| 363be49c JM |
868 | #define SPR_BOOKE_DSRR1 (0x23F) |
| 869 | #define SPR_BOOKE_SPRG8 (0x25C) | |
| 870 | #define SPR_BOOKE_SPRG9 (0x25D) | |
| 871 | #define SPR_BOOKE_MAS0 (0x270) | |
| 872 | #define SPR_BOOKE_MAS1 (0x271) | |
| 873 | #define SPR_BOOKE_MAS2 (0x272) | |
| 874 | #define SPR_BOOKE_MAS3 (0x273) | |
| 875 | #define SPR_BOOKE_MAS4 (0x274) | |
| 876 | #define SPR_BOOKE_MAS6 (0x276) | |
| 877 | #define SPR_BOOKE_PID1 (0x279) | |
| 878 | #define SPR_BOOKE_PID2 (0x27A) | |
| 879 | #define SPR_BOOKE_TLB0CFG (0x2B0) | |
| 880 | #define SPR_BOOKE_TLB1CFG (0x2B1) | |
| 881 | #define SPR_BOOKE_TLB2CFG (0x2B2) | |
| 882 | #define SPR_BOOKE_TLB3CFG (0x2B3) | |
| 883 | #define SPR_BOOKE_EPR (0x2BE) | |
| 2662a059 JM |
884 | #define SPR_PERF0 (0x300) |
| 885 | #define SPR_PERF1 (0x301) | |
| 886 | #define SPR_PERF2 (0x302) | |
| 887 | #define SPR_PERF3 (0x303) | |
| 888 | #define SPR_PERF4 (0x304) | |
| 889 | #define SPR_PERF5 (0x305) | |
| 890 | #define SPR_PERF6 (0x306) | |
| 891 | #define SPR_PERF7 (0x307) | |
| 892 | #define SPR_PERF8 (0x308) | |
| 893 | #define SPR_PERF9 (0x309) | |
| 894 | #define SPR_PERFA (0x30A) | |
| 895 | #define SPR_PERFB (0x30B) | |
| 896 | #define SPR_PERFC (0x30C) | |
| 897 | #define SPR_PERFD (0x30D) | |
| 898 | #define SPR_PERFE (0x30E) | |
| 899 | #define SPR_PERFF (0x30F) | |
| 900 | #define SPR_UPERF0 (0x310) | |
| 901 | #define SPR_UPERF1 (0x311) | |
| 902 | #define SPR_UPERF2 (0x312) | |
| 903 | #define SPR_UPERF3 (0x313) | |
| 904 | #define SPR_UPERF4 (0x314) | |
| 905 | #define SPR_UPERF5 (0x315) | |
| 906 | #define SPR_UPERF6 (0x316) | |
| 907 | #define SPR_UPERF7 (0x317) | |
| 908 | #define SPR_UPERF8 (0x318) | |
| 909 | #define SPR_UPERF9 (0x319) | |
| 910 | #define SPR_UPERFA (0x31A) | |
| 911 | #define SPR_UPERFB (0x31B) | |
| 912 | #define SPR_UPERFC (0x31C) | |
| 913 | #define SPR_UPERFD (0x31D) | |
| 914 | #define SPR_UPERFE (0x31E) | |
| 915 | #define SPR_UPERFF (0x31F) | |
| 76a66253 JM |
916 | #define SPR_440_INV0 (0x370) |
| 917 | #define SPR_440_INV1 (0x371) | |
| 918 | #define SPR_440_INV2 (0x372) | |
| 919 | #define SPR_440_INV3 (0x373) | |
| 2662a059 JM |
920 | #define SPR_440_ITV0 (0x374) |
| 921 | #define SPR_440_ITV1 (0x375) | |
| 922 | #define SPR_440_ITV2 (0x376) | |
| 923 | #define SPR_440_ITV3 (0x377) | |
| a750fc0b JM |
924 | #define SPR_440_CCR1 (0x378) |
| 925 | #define SPR_DCRIPR (0x37B) | |
| 2662a059 | 926 | #define SPR_PPR (0x380) |
| 76a66253 JM |
927 | #define SPR_440_DNV0 (0x390) |
| 928 | #define SPR_440_DNV1 (0x391) | |
| 929 | #define SPR_440_DNV2 (0x392) | |
| 930 | #define SPR_440_DNV3 (0x393) | |
| 2662a059 JM |
931 | #define SPR_440_DTV0 (0x394) |
| 932 | #define SPR_440_DTV1 (0x395) | |
| 933 | #define SPR_440_DTV2 (0x396) | |
| 934 | #define SPR_440_DTV3 (0x397) | |
| 76a66253 JM |
935 | #define SPR_440_DVLIM (0x398) |
| 936 | #define SPR_440_IVLIM (0x399) | |
| 937 | #define SPR_440_RSTCFG (0x39B) | |
| 2662a059 JM |
938 | #define SPR_BOOKE_DCDBTRL (0x39C) |
| 939 | #define SPR_BOOKE_DCDBTRH (0x39D) | |
| 940 | #define SPR_BOOKE_ICDBTRL (0x39E) | |
| 941 | #define SPR_BOOKE_ICDBTRH (0x39F) | |
| a750fc0b JM |
942 | #define SPR_UMMCR2 (0x3A0) |
| 943 | #define SPR_UPMC5 (0x3A1) | |
| 944 | #define SPR_UPMC6 (0x3A2) | |
| 945 | #define SPR_UBAMR (0x3A7) | |
| 76a66253 JM |
946 | #define SPR_UMMCR0 (0x3A8) |
| 947 | #define SPR_UPMC1 (0x3A9) | |
| 948 | #define SPR_UPMC2 (0x3AA) | |
| a750fc0b | 949 | #define SPR_USIAR (0x3AB) |
| 76a66253 JM |
950 | #define SPR_UMMCR1 (0x3AC) |
| 951 | #define SPR_UPMC3 (0x3AD) | |
| 952 | #define SPR_UPMC4 (0x3AE) | |
| 953 | #define SPR_USDA (0x3AF) | |
| 954 | #define SPR_40x_ZPR (0x3B0) | |
| 363be49c | 955 | #define SPR_BOOKE_MAS7 (0x3B0) |
| a750fc0b JM |
956 | #define SPR_620_PMR0 (0x3B0) |
| 957 | #define SPR_MMCR2 (0x3B0) | |
| 958 | #define SPR_PMC5 (0x3B1) | |
| 76a66253 | 959 | #define SPR_40x_PID (0x3B1) |
| a750fc0b JM |
960 | #define SPR_620_PMR1 (0x3B1) |
| 961 | #define SPR_PMC6 (0x3B2) | |
| 76a66253 | 962 | #define SPR_440_MMUCR (0x3B2) |
| a750fc0b | 963 | #define SPR_620_PMR2 (0x3B2) |
| 76a66253 | 964 | #define SPR_4xx_CCR0 (0x3B3) |
| 363be49c | 965 | #define SPR_BOOKE_EPLC (0x3B3) |
| a750fc0b | 966 | #define SPR_620_PMR3 (0x3B3) |
| 76a66253 | 967 | #define SPR_405_IAC3 (0x3B4) |
| 363be49c | 968 | #define SPR_BOOKE_EPSC (0x3B4) |
| a750fc0b | 969 | #define SPR_620_PMR4 (0x3B4) |
| 76a66253 | 970 | #define SPR_405_IAC4 (0x3B5) |
| a750fc0b | 971 | #define SPR_620_PMR5 (0x3B5) |
| 76a66253 | 972 | #define SPR_405_DVC1 (0x3B6) |
| a750fc0b | 973 | #define SPR_620_PMR6 (0x3B6) |
| 76a66253 | 974 | #define SPR_405_DVC2 (0x3B7) |
| a750fc0b JM |
975 | #define SPR_620_PMR7 (0x3B7) |
| 976 | #define SPR_BAMR (0x3B7) | |
| 76a66253 | 977 | #define SPR_MMCR0 (0x3B8) |
| a750fc0b | 978 | #define SPR_620_PMR8 (0x3B8) |
| 76a66253 JM |
979 | #define SPR_PMC1 (0x3B9) |
| 980 | #define SPR_40x_SGR (0x3B9) | |
| a750fc0b | 981 | #define SPR_620_PMR9 (0x3B9) |
| 76a66253 JM |
982 | #define SPR_PMC2 (0x3BA) |
| 983 | #define SPR_40x_DCWR (0x3BA) | |
| a750fc0b JM |
984 | #define SPR_620_PMRA (0x3BA) |
| 985 | #define SPR_SIAR (0x3BB) | |
| 76a66253 | 986 | #define SPR_405_SLER (0x3BB) |
| a750fc0b | 987 | #define SPR_620_PMRB (0x3BB) |
| 76a66253 JM |
988 | #define SPR_MMCR1 (0x3BC) |
| 989 | #define SPR_405_SU0R (0x3BC) | |
| a750fc0b JM |
990 | #define SPR_620_PMRC (0x3BC) |
| 991 | #define SPR_401_SKR (0x3BC) | |
| 76a66253 JM |
992 | #define SPR_PMC3 (0x3BD) |
| 993 | #define SPR_405_DBCR1 (0x3BD) | |
| a750fc0b | 994 | #define SPR_620_PMRD (0x3BD) |
| 76a66253 | 995 | #define SPR_PMC4 (0x3BE) |
| a750fc0b | 996 | #define SPR_620_PMRE (0x3BE) |
| 76a66253 | 997 | #define SPR_SDA (0x3BF) |
| a750fc0b | 998 | #define SPR_620_PMRF (0x3BF) |
| 76a66253 JM |
999 | #define SPR_403_VTBL (0x3CC) |
| 1000 | #define SPR_403_VTBU (0x3CD) | |
| 1001 | #define SPR_DMISS (0x3D0) | |
| 1002 | #define SPR_DCMP (0x3D1) | |
| 1003 | #define SPR_HASH1 (0x3D2) | |
| 1004 | #define SPR_HASH2 (0x3D3) | |
| 2662a059 | 1005 | #define SPR_BOOKE_ICDBDR (0x3D3) |
| a750fc0b | 1006 | #define SPR_TLBMISS (0x3D4) |
| 76a66253 JM |
1007 | #define SPR_IMISS (0x3D4) |
| 1008 | #define SPR_40x_ESR (0x3D4) | |
| a750fc0b | 1009 | #define SPR_PTEHI (0x3D5) |
| 76a66253 JM |
1010 | #define SPR_ICMP (0x3D5) |
| 1011 | #define SPR_40x_DEAR (0x3D5) | |
| a750fc0b | 1012 | #define SPR_PTELO (0x3D6) |
| 76a66253 JM |
1013 | #define SPR_RPA (0x3D6) |
| 1014 | #define SPR_40x_EVPR (0x3D6) | |
| a750fc0b | 1015 | #define SPR_L3PM (0x3D7) |
| 76a66253 | 1016 | #define SPR_403_CDBCR (0x3D7) |
| a750fc0b | 1017 | #define SPR_L3OHCR (0x3D8) |
| 76a66253 JM |
1018 | #define SPR_TCR (0x3D8) |
| 1019 | #define SPR_40x_TSR (0x3D8) | |
| 1020 | #define SPR_IBR (0x3DA) | |
| 1021 | #define SPR_40x_TCR (0x3DA) | |
| a750fc0b | 1022 | #define SPR_ESASRR (0x3DB) |
| 76a66253 JM |
1023 | #define SPR_40x_PIT (0x3DB) |
| 1024 | #define SPR_403_TBL (0x3DC) | |
| 1025 | #define SPR_403_TBU (0x3DD) | |
| 1026 | #define SPR_SEBR (0x3DE) | |
| 1027 | #define SPR_40x_SRR2 (0x3DE) | |
| 1028 | #define SPR_SER (0x3DF) | |
| 1029 | #define SPR_40x_SRR3 (0x3DF) | |
| a750fc0b JM |
1030 | #define SPR_L3ITCR0 (0x3E8) |
| 1031 | #define SPR_L3ITCR1 (0x3E9) | |
| 1032 | #define SPR_L3ITCR2 (0x3EA) | |
| 1033 | #define SPR_L3ITCR3 (0x3EB) | |
| 76a66253 JM |
1034 | #define SPR_HID0 (0x3F0) |
| 1035 | #define SPR_40x_DBSR (0x3F0) | |
| 1036 | #define SPR_HID1 (0x3F1) | |
| 1037 | #define SPR_IABR (0x3F2) | |
| 1038 | #define SPR_40x_DBCR0 (0x3F2) | |
| 1039 | #define SPR_601_HID2 (0x3F2) | |
| 1040 | #define SPR_E500_L1CSR0 (0x3F2) | |
| a750fc0b | 1041 | #define SPR_ICTRL (0x3F3) |
| 76a66253 JM |
1042 | #define SPR_HID2 (0x3F3) |
| 1043 | #define SPR_E500_L1CSR1 (0x3F3) | |
| 1044 | #define SPR_440_DBDR (0x3F3) | |
| a750fc0b | 1045 | #define SPR_LDSTDB (0x3F4) |
| 76a66253 | 1046 | #define SPR_40x_IAC1 (0x3F4) |
| 363be49c | 1047 | #define SPR_BOOKE_MMUCSR0 (0x3F4) |
| 76a66253 | 1048 | #define SPR_DABR (0x3F5) |
| 3fc6c082 | 1049 | #define DABR_MASK (~(target_ulong)0x7) |
| 76a66253 JM |
1050 | #define SPR_E500_BUCSR (0x3F5) |
| 1051 | #define SPR_40x_IAC2 (0x3F5) | |
| 1052 | #define SPR_601_HID5 (0x3F5) | |
| 1053 | #define SPR_40x_DAC1 (0x3F6) | |
| a750fc0b JM |
1054 | #define SPR_MSSCR0 (0x3F6) |
| 1055 | #define SPR_MSSSR0 (0x3F7) | |
| 2662a059 | 1056 | #define SPR_DABRX (0x3F7) |
| 76a66253 | 1057 | #define SPR_40x_DAC2 (0x3F7) |
| 363be49c | 1058 | #define SPR_BOOKE_MMUCFG (0x3F7) |
| a750fc0b JM |
1059 | #define SPR_LDSTCR (0x3F8) |
| 1060 | #define SPR_L2PMCR (0x3F8) | |
| 76a66253 | 1061 | #define SPR_750_HID2 (0x3F8) |
| a750fc0b | 1062 | #define SPR_620_HID8 (0x3F8) |
| 76a66253 | 1063 | #define SPR_L2CR (0x3F9) |
| a750fc0b JM |
1064 | #define SPR_620_HID9 (0x3F9) |
| 1065 | #define SPR_L3CR (0x3FA) | |
| 76a66253 JM |
1066 | #define SPR_IABR2 (0x3FA) |
| 1067 | #define SPR_40x_DCCR (0x3FA) | |
| 1068 | #define SPR_ICTC (0x3FB) | |
| 1069 | #define SPR_40x_ICCR (0x3FB) | |
| 1070 | #define SPR_THRM1 (0x3FC) | |
| 1071 | #define SPR_403_PBL1 (0x3FC) | |
| 1072 | #define SPR_SP (0x3FD) | |
| 1073 | #define SPR_THRM2 (0x3FD) | |
| 1074 | #define SPR_403_PBU1 (0x3FD) | |
| a750fc0b | 1075 | #define SPR_604_HID13 (0x3FD) |
| 76a66253 JM |
1076 | #define SPR_LT (0x3FE) |
| 1077 | #define SPR_THRM3 (0x3FE) | |
| 1078 | #define SPR_FPECR (0x3FE) | |
| 1079 | #define SPR_403_PBL2 (0x3FE) | |
| 1080 | #define SPR_PIR (0x3FF) | |
| 1081 | #define SPR_403_PBU2 (0x3FF) | |
| 1082 | #define SPR_601_HID15 (0x3FF) | |
| a750fc0b | 1083 | #define SPR_604_HID15 (0x3FF) |
| 76a66253 | 1084 | #define SPR_E500_SVR (0x3FF) |
| 79aceca5 | 1085 | |
| 76a66253 | 1086 | /*****************************************************************************/ |
| 9a64fbe4 FB |
1087 | /* Memory access type : |
| 1088 | * may be needed for precise access rights control and precise exceptions. | |
| 1089 | */ | |
| 79aceca5 | 1090 | enum { |
| 9a64fbe4 FB |
1091 | /* 1 bit to define user level / supervisor access */ |
| 1092 | ACCESS_USER = 0x00, | |
| 1093 | ACCESS_SUPER = 0x01, | |
| 1094 | /* Type of instruction that generated the access */ | |
| 1095 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
| 1096 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
| 1097 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
| 1098 | ACCESS_RES = 0x40, /* load/store with reservation */ | |
| 1099 | ACCESS_EXT = 0x50, /* external access */ | |
| 1100 | ACCESS_CACHE = 0x60, /* Cache manipulation */ | |
| 1101 | }; | |
| 1102 | ||
| 47103572 JM |
1103 | /* Hardware interruption sources: |
| 1104 | * all those exception can be raised simulteaneously | |
| 1105 | */ | |
| e9df014c JM |
1106 | /* Input pins definitions */ |
| 1107 | enum { | |
| 1108 | /* 6xx bus input pins */ | |
| 24be5ae3 JM |
1109 | PPC6xx_INPUT_HRESET = 0, |
| 1110 | PPC6xx_INPUT_SRESET = 1, | |
| 1111 | PPC6xx_INPUT_CKSTP_IN = 2, | |
| 1112 | PPC6xx_INPUT_MCP = 3, | |
| 1113 | PPC6xx_INPUT_SMI = 4, | |
| 1114 | PPC6xx_INPUT_INT = 5, | |
| 1115 | }; | |
| 1116 | ||
| 1117 | enum { | |
| e9df014c | 1118 | /* Embedded PowerPC input pins */ |
| 24be5ae3 JM |
1119 | PPCBookE_INPUT_HRESET = 0, |
| 1120 | PPCBookE_INPUT_SRESET = 1, | |
| 1121 | PPCBookE_INPUT_CKSTP_IN = 2, | |
| 1122 | PPCBookE_INPUT_MCP = 3, | |
| 1123 | PPCBookE_INPUT_SMI = 4, | |
| 1124 | PPCBookE_INPUT_INT = 5, | |
| 1125 | PPCBookE_INPUT_CINT = 6, | |
| 1126 | }; | |
| 1127 | ||
| a750fc0b | 1128 | enum { |
| 4e290a0b JM |
1129 | /* PowerPC 40x input pins */ |
| 1130 | PPC40x_INPUT_RESET_CORE = 0, | |
| 1131 | PPC40x_INPUT_RESET_CHIP = 1, | |
| 1132 | PPC40x_INPUT_RESET_SYS = 2, | |
| 1133 | PPC40x_INPUT_CINT = 3, | |
| 1134 | PPC40x_INPUT_INT = 4, | |
| 1135 | PPC40x_INPUT_HALT = 5, | |
| 1136 | PPC40x_INPUT_DEBUG = 6, | |
| 1137 | PPC40x_INPUT_NB, | |
| e9df014c JM |
1138 | }; |
| 1139 | ||
| 00af685f | 1140 | #if defined(TARGET_PPC64) |
| a750fc0b JM |
1141 | enum { |
| 1142 | /* PowerPC 620 (and probably others) input pins */ | |
| 1143 | PPC620_INPUT_HRESET = 0, | |
| 1144 | PPC620_INPUT_SRESET = 1, | |
| 1145 | PPC620_INPUT_CKSTP = 2, | |
| 1146 | PPC620_INPUT_TBEN = 3, | |
| 1147 | PPC620_INPUT_WAKEUP = 4, | |
| 1148 | PPC620_INPUT_MCP = 5, | |
| 1149 | PPC620_INPUT_SMI = 6, | |
| 1150 | PPC620_INPUT_INT = 7, | |
| 1151 | }; | |
| 1152 | ||
| d0dfae6e JM |
1153 | enum { |
| 1154 | /* PowerPC 970 input pins */ | |
| 1155 | PPC970_INPUT_HRESET = 0, | |
| 1156 | PPC970_INPUT_SRESET = 1, | |
| 1157 | PPC970_INPUT_CKSTP = 2, | |
| 1158 | PPC970_INPUT_TBEN = 3, | |
| 1159 | PPC970_INPUT_MCP = 4, | |
| 1160 | PPC970_INPUT_INT = 5, | |
| 1161 | PPC970_INPUT_THINT = 6, | |
| 1162 | }; | |
| 00af685f | 1163 | #endif |
| d0dfae6e | 1164 | |
| e9df014c | 1165 | /* Hardware exceptions definitions */ |
| 47103572 | 1166 | enum { |
| e9df014c | 1167 | /* External hardware exception sources */ |
| e1833e1f JM |
1168 | PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
| 1169 | PPC_INTERRUPT_MCK = 1, /* Machine check exception */ | |
| 1170 | PPC_INTERRUPT_EXT = 2, /* External interrupt */ | |
| 1171 | PPC_INTERRUPT_SMI = 3, /* System management interrupt */ | |
| 1172 | PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */ | |
| 1173 | PPC_INTERRUPT_DEBUG = 5, /* External debug exception */ | |
| 1174 | PPC_INTERRUPT_THERM = 6, /* Thermal exception */ | |
| e9df014c | 1175 | /* Internal hardware exception sources */ |
| e1833e1f JM |
1176 | PPC_INTERRUPT_DECR = 7, /* Decrementer exception */ |
| 1177 | PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */ | |
| 1178 | PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */ | |
| 1179 | PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */ | |
| 1180 | PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */ | |
| 1181 | PPC_INTERRUPT_CDOORBELL = 12, /* Critical doorbell interrupt */ | |
| 1182 | PPC_INTERRUPT_DOORBELL = 13, /* Doorbell interrupt */ | |
| 1183 | PPC_INTERRUPT_PERFM = 14, /* Performance monitor interrupt */ | |
| 47103572 JM |
1184 | }; |
| 1185 | ||
| 9a64fbe4 FB |
1186 | /*****************************************************************************/ |
| 1187 | ||
| 79aceca5 | 1188 | #endif /* !defined (__CPU_PPC_H__) */ |