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Simple u-boot image loading support.
[mirror_qemu.git] / target-ppc / cpu.h
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
79aceca5 3 *
3fc6c082 4 * Copyright (c) 2003-2005 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082
FB		 23#include "config.h"
24
3cf1e035
FB		 25#define TARGET_LONG_BITS 32
26
79aceca5
FB		 27#include "cpu-defs.h"
28
79aceca5
FB		 29#include <setjmp.h>
30
4ecc3190
FB		 31#include "softfloat.h"
32
1fddef4b
FB		 33#define TARGET_HAS_ICE 1
34
9042c0e2
TS		 35#define ELF_MACHINE EM_PPC
36
fdabc366
FB		 37/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
38 * have different cache line sizes
39 */
40#define ICACHE_LINE_SIZE 32
41#define DCACHE_LINE_SIZE 32
42
43/* XXX: put this in a common place */
44#define likely(x) __builtin_expect(!!(x), 1)
45
3fc6c082
FB		 46/*****************************************************************************/
47/* PVR definitions for most known PowerPC */
48enum {
49 /* PowerPC 401 cores */
50 CPU_PPC_401A1 = 0x00210000,
51 CPU_PPC_401B2 = 0x00220000,
52 CPU_PPC_401C2 = 0x00230000,
53 CPU_PPC_401D2 = 0x00240000,
54 CPU_PPC_401E2 = 0x00250000,
55 CPU_PPC_401F2 = 0x00260000,
56 CPU_PPC_401G2 = 0x00270000,
57 CPU_PPC_IOP480 = 0x40100000,
58 /* PowerPC 403 cores */
59 CPU_PPC_403GA = 0x00200000,
60 CPU_PPC_403GB = 0x00200100,
61 CPU_PPC_403GC = 0x00200200,
62 CPU_PPC_403GCX = 0x00201400,
63 /* PowerPC 405 cores */
64 CPU_PPC_405 = 0x40110000,
65 CPU_PPC_405EP = 0x51210000,
66 CPU_PPC_405GPR = 0x50910000,
67 CPU_PPC_405D2 = 0x20010000,
68 CPU_PPC_405D4 = 0x41810000,
69 CPU_PPC_NPE405H = 0x41410000,
70 CPU_PPC_NPE405L = 0x41610000,
71#if 0
72 CPU_PPC_STB02 = xxx,
73#endif
74 CPU_PPC_STB03 = 0x40310000,
75#if 0
76 CPU_PPC_STB04 = xxx,
77#endif
78 CPU_PPC_STB25 = 0x51510000,
79#if 0
80 CPU_PPC_STB130 = xxx,
81#endif
82 /* PowerPC 440 cores */
83 CPU_PPC_440EP = 0x42220000,
84 CPU_PPC_440GP = 0x40120400,
85 CPU_PPC_440GX = 0x51B20000,
86 /* PowerPC MPC 8xx cores */
87 CPU_PPC_8540 = 0x80200000,
88 CPU_PPC_8xx = 0x00500000,
89 CPU_PPC_8240 = 0x00810100,
90 CPU_PPC_8245 = 0x00811014,
91 /* PowerPC 6xx cores */
92 CPU_PPC_601 = 0x00010000,
93 CPU_PPC_602 = 0x00050000,
94 CPU_PPC_603 = 0x00030000,
95 CPU_PPC_603E = 0x00060000,
96 CPU_PPC_603EV = 0x00070000,
97 CPU_PPC_603R = 0x00071000,
98 CPU_PPC_G2 = 0x80810000,
99 CPU_PPC_G2LE = 0x80820000,
100 CPU_PPC_604 = 0x00040000,
101 CPU_PPC_604E = 0x00090000,
102 CPU_PPC_604R = 0x000a0000,
103 /* PowerPC 74x/75x cores (aka G3) */
104 CPU_PPC_74x = 0x00080000,
105 CPU_PPC_755 = 0x00083000,
106 CPU_PPC_74xP = 0x10080000,
107 CPU_PPC_750CXE22 = 0x00082202,
108 CPU_PPC_750CXE24 = 0x00082214,
109 CPU_PPC_750CXE24b = 0x00083214,
110 CPU_PPC_750CXE31 = 0x00083211,
111 CPU_PPC_750CXE31b = 0x00083311,
112#define CPU_PPC_750CXE CPU_PPC_750CXE31b
113 CPU_PPC_750FX = 0x70000000,
114 CPU_PPC_750GX = 0x70020000,
115 /* PowerPC 74xx cores (aka G4) */
116 CPU_PPC_7400 = 0x000C0000,
117 CPU_PPC_7410 = 0x800C0000,
118 CPU_PPC_7441 = 0x80000200,
119 CPU_PPC_7450 = 0x80000000,
120 CPU_PPC_7451 = 0x80000203,
121 CPU_PPC_7455 = 0x80010000,
122 CPU_PPC_7457 = 0x80020000,
123 CPU_PPC_7457A = 0x80030000,
124 /* 64 bits PowerPC */
125 CPU_PPC_620 = 0x00140000,
126 CPU_PPC_630 = 0x00400000,
127 CPU_PPC_631 = 0x00410000,
128 CPU_PPC_POWER4 = 0x00350000,
129 CPU_PPC_POWER4P = 0x00380000,
130 CPU_PPC_POWER5 = 0x003A0000,
131 CPU_PPC_POWER5P = 0x003B0000,
132 CPU_PPC_970 = 0x00390000,
133 CPU_PPC_970FX = 0x003C0000,
134 CPU_PPC_RS64 = 0x00330000,
135 CPU_PPC_RS64II = 0x00340000,
136 CPU_PPC_RS64III = 0x00360000,
137 CPU_PPC_RS64IV = 0x00370000,
138 /* Original POWER */
139 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
140 * POWER2 (RIOS2) & RSC2 (P2SC) here
141 */
142#if 0
143 CPU_POWER = xxx,
144#endif
145#if 0
146 CPU_POWER2 = xxx,
147#endif
148};
149
150/* System version register (used on MPC 8xx) */
151enum {
152 PPC_SVR_8540 = 0x80300000,
153 PPC_SVR_8541E = 0x807A0000,
154 PPC_SVR_8555E = 0x80790000,
155 PPC_SVR_8560 = 0x80700000,
156};
157
158/*****************************************************************************/
9a64fbe4
FB		 159/* Instruction types */
160enum {
3fc6c082
FB		 161 PPC_NONE = 0x00000000,
162 /* integer operations instructions */
163 /* flow control instructions */
164 /* virtual memory instructions */
165 /* ld/st with reservation instructions */
166 /* cache control instructions */
167 /* spr/msr access instructions */
168 PPC_INSNS_BASE = 0x00000001,
169#define PPC_INTEGER PPC_INSNS_BASE
170#define PPC_FLOW PPC_INSNS_BASE
171#define PPC_MEM PPC_INSNS_BASE
172#define PPC_RES PPC_INSNS_BASE
173#define PPC_CACHE PPC_INSNS_BASE
174#define PPC_MISC PPC_INSNS_BASE
175 /* floating point operations instructions */
176 PPC_FLOAT = 0x00000002,
177 /* more floating point operations instructions */
178 PPC_FLOAT_EXT = 0x00000004,
179 /* external control instructions */
180 PPC_EXTERN = 0x00000008,
181 /* segment register access instructions */
182 PPC_SEGMENT = 0x00000010,
183 /* Optional cache control instructions */
184 PPC_CACHE_OPT = 0x00000020,
185 /* Optional floating point op instructions */
186 PPC_FLOAT_OPT = 0x00000040,
187 /* Optional memory control instructions */
188 PPC_MEM_TLBIA = 0x00000080,
189 PPC_MEM_TLBIE = 0x00000100,
190 PPC_MEM_TLBSYNC = 0x00000200,
191 /* eieio & sync */
192 PPC_MEM_SYNC = 0x00000400,
193 /* PowerPC 6xx TLB management instructions */
194 PPC_6xx_TLB = 0x00000800,
195 /* Altivec support */
196 PPC_ALTIVEC = 0x00001000,
197 /* Time base support */
198 PPC_TB = 0x00002000,
199 /* Embedded PowerPC dedicated instructions */
200 PPC_4xx_COMMON = 0x00004000,
201 /* PowerPC 40x exception model */
202 PPC_40x_EXCP = 0x00008000,
203 /* PowerPC 40x specific instructions */
204 PPC_40x_SPEC = 0x00010000,
205 /* PowerPC 405 Mac instructions */
206 PPC_405_MAC = 0x00020000,
207 /* PowerPC 440 specific instructions */
208 PPC_440_SPEC = 0x00040000,
209 /* Specific extensions */
210 /* Power-to-PowerPC bridge (601) */
211 PPC_POWER_BR = 0x00080000,
212 /* PowerPC 602 specific */
213 PPC_602_SPEC = 0x00100000,
214 /* Deprecated instructions */
215 /* Original POWER instruction set */
216 PPC_POWER = 0x00200000,
217 /* POWER2 instruction set extension */
218 PPC_POWER2 = 0x00400000,
219 /* Power RTC support */
220 PPC_POWER_RTC = 0x00800000,
221 /* 64 bits PowerPC instructions */
222 /* 64 bits PowerPC instruction set */
223 PPC_64B = 0x01000000,
224 /* 64 bits hypervisor extensions */
225 PPC_64H = 0x02000000,
226 /* 64 bits PowerPC "bridge" features */
227 PPC_64_BRIDGE = 0x04000000,
9a64fbe4 228};
79aceca5 229
3fc6c082
FB		 230/* CPU run-time flags (MMU and exception model) */
231enum {
232 /* MMU model */
233#define PPC_FLAGS_MMU_MASK (0x0000000F)
234 /* Standard 32 bits PowerPC MMU */
235 PPC_FLAGS_MMU_32B = 0x00000000,
236 /* Standard 64 bits PowerPC MMU */
237 PPC_FLAGS_MMU_64B = 0x00000001,
238 /* PowerPC 601 MMU */
239 PPC_FLAGS_MMU_601 = 0x00000002,
240 /* PowerPC 6xx MMU with software TLB */
241 PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
242 /* PowerPC 4xx MMU with software TLB */
243 PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
244 /* PowerPC 403 MMU */
245 PPC_FLAGS_MMU_403 = 0x00000005,
246 /* Exception model */
247#define PPC_FLAGS_EXCP_MASK (0x000000F0)
248 /* Standard PowerPC exception model */
249 PPC_FLAGS_EXCP_STD = 0x00000000,
250 /* PowerPC 40x exception model */
251 PPC_FLAGS_EXCP_40x = 0x00000010,
252 /* PowerPC 601 exception model */
253 PPC_FLAGS_EXCP_601 = 0x00000020,
254 /* PowerPC 602 exception model */
255 PPC_FLAGS_EXCP_602 = 0x00000030,
256 /* PowerPC 603 exception model */
257 PPC_FLAGS_EXCP_603 = 0x00000040,
258 /* PowerPC 604 exception model */
259 PPC_FLAGS_EXCP_604 = 0x00000050,
260 /* PowerPC 7x0 exception model */
261 PPC_FLAGS_EXCP_7x0 = 0x00000060,
262 /* PowerPC 7x5 exception model */
263 PPC_FLAGS_EXCP_7x5 = 0x00000070,
264 /* PowerPC 74xx exception model */
265 PPC_FLAGS_EXCP_74xx = 0x00000080,
266 /* PowerPC 970 exception model */
267 PPC_FLAGS_EXCP_970 = 0x00000090,
268};
269
270#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
271#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
272
273/*****************************************************************************/
274/* Supported instruction set definitions */
275/* This generates an empty opcode table... */
276#define PPC_INSNS_TODO (PPC_NONE)
277#define PPC_FLAGS_TODO (0x00000000)
278
279/* PowerPC 40x instruction set */
280#define PPC_INSNS_4xx (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_4xx_COMMON)
281/* PowerPC 401 */
282#define PPC_INSNS_401 (PPC_INSNS_TODO)
283#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
284/* PowerPC 403 */
285#define PPC_INSNS_403 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_MEM_TLBIA | \
286 PPC_40x_EXCP | PPC_40x_SPEC)
287#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
288/* PowerPC 405 */
289#define PPC_INSNS_405 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_CACHE_OPT | \
290 PPC_MEM_TLBIA | PPC_TB | PPC_40x_SPEC | PPC_40x_EXCP | \
291 PPC_405_MAC)
292#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
293/* PowerPC 440 */
294#define PPC_INSNS_440 (PPC_INSNS_4xx | PPC_CACHE_OPT | PPC_405_MAC | \
295 PPC_440_SPEC)
296#define PPC_FLAGS_440 (PPC_FLAGS_TODO)
297/* Non-embedded PowerPC */
298#define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
299 PPC_SEGMENT | PPC_MEM_TLBIE)
300/* PowerPC 601 */
301#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
302#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
303/* PowerPC 602 */
304#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
305 PPC_MEM_TLBSYNC | PPC_TB)
306#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
307/* PowerPC 603 */
308#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
309 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
310#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
311/* PowerPC G2 */
312#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
313 PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
314#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
315/* PowerPC 604 */
316#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
317 PPC_MEM_TLBSYNC | PPC_TB)
318#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
319/* PowerPC 740/750 (aka G3) */
320#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
321 PPC_MEM_TLBSYNC | PPC_TB)
322#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
323/* PowerPC 745/755 */
324#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
325 PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
326#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
327/* PowerPC 74xx (aka G4) */
328#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
329 PPC_MEM_TLBSYNC | PPC_TB)
330#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
331
332/* Default PowerPC will be 604/970 */
333#define PPC_INSNS_PPC32 PPC_INSNS_604
334#define PPC_FLAGS_PPC32 PPC_FLAGS_604
335#if 0
336#define PPC_INSNS_PPC64 PPC_INSNS_970
337#define PPC_FLAGS_PPC64 PPC_FLAGS_970
338#endif
339#define PPC_INSNS_DEFAULT PPC_INSNS_604
340#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
341typedef struct ppc_def_t ppc_def_t;
79aceca5 342
3fc6c082
FB		 343/*****************************************************************************/
344/* Types used to describe some PowerPC registers */
345typedef struct CPUPPCState CPUPPCState;
346typedef struct opc_handler_t opc_handler_t;
9fddaa0c 347typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 348typedef struct ppc_spr_t ppc_spr_t;
349typedef struct ppc_dcr_t ppc_dcr_t;
350typedef struct ppc_avr_t ppc_avr_t;
351
352/* SPR access micro-ops generations callbacks */
353struct ppc_spr_t {
354 void (*uea_read)(void *opaque, int spr_num);
355 void (*uea_write)(void *opaque, int spr_num);
356 void (*oea_read)(void *opaque, int spr_num);
357 void (*oea_write)(void *opaque, int spr_num);
358 const unsigned char *name;
359};
360
361/* Altivec registers (128 bits) */
362struct ppc_avr_t {
363 uint32_t u[4];
364};
9fddaa0c 365
3fc6c082
FB		 366/* Software TLB cache */
367typedef struct ppc_tlb_t ppc_tlb_t;
368struct ppc_tlb_t {
369 /* Physical page number */
370 target_phys_addr_t RPN;
371 /* Virtual page number */
372 target_ulong VPN;
373 /* Page size */
374 target_ulong size;
375 /* Protection bits */
376 int prot;
377 int is_user;
378 uint32_t private;
379 uint32_t flags;
380};
381
382/*****************************************************************************/
383/* Machine state register bits definition */
384#define MSR_SF 63 /* Sixty-four-bit mode */
385#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
386#define MSR_HV 60 /* hypervisor state */
387#define MSR_VR 25 /* altivec available */
388#define MSR_AP 23 /* Access privilege state on 602 */
389#define MSR_SA 22 /* Supervisor access mode on 602 */
390#define MSR_KEY 19 /* key bit on 603e */
391#define MSR_POW 18 /* Power management */
392#define MSR_WE 18 /* Wait state enable on embedded PowerPC */
393#define MSR_TGPR 17 /* TGPR usage on 602/603 */
394#define MSR_TLB 17 /* TLB on ? */
395#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */
396#define MSR_ILE 16 /* Interrupt little-endian mode */
397#define MSR_EE 15 /* External interrupt enable */
398#define MSR_PR 14 /* Problem state */
399#define MSR_FP 13 /* Floating point available */
400#define MSR_ME 12 /* Machine check interrupt enable */
401#define MSR_FE0 11 /* Floating point exception mode 0 */
402#define MSR_SE 10 /* Single-step trace enable */
403#define MSR_DWE 10 /* Debug wait enable on 405 */
404#define MSR_BE 9 /* Branch trace enable */
405#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */
406#define MSR_FE1 8 /* Floating point exception mode 1 */
407#define MSR_AL 7 /* AL bit on POWER */
408#define MSR_IP 6 /* Interrupt prefix */
409#define MSR_IR 5 /* Instruction relocate */
410#define MSR_IS 5 /* Instruction address space on embedded PowerPC */
411#define MSR_DR 4 /* Data relocate */
412#define MSR_DS 4 /* Data address space on embedded PowerPC */
413#define MSR_PE 3 /* Protection enable on 403 */
414#define MSR_EP 3 /* Exception prefix on 601 */
415#define MSR_PX 2 /* Protection exclusive on 403 */
416#define MSR_PMM 2 /* Performance monitor mark on POWER */
417#define MSR_RI 1 /* Recoverable interrupt */
418#define MSR_LE 0 /* Little-endian mode */
419#define msr_sf env->msr[MSR_SF]
420#define msr_isf env->msr[MSR_ISF]
421#define msr_hv env->msr[MSR_HV]
422#define msr_vr env->msr[MSR_VR]
423#define msr_ap env->msr[MSR_AP]
424#define msr_sa env->msr[MSR_SA]
425#define msr_key env->msr[MSR_KEY]
79aceca5 426#define msr_pow env->msr[MSR_POW]
3fc6c082
FB		 427#define msr_we env->msr[MSR_WE]
428#define msr_tgpr env->msr[MSR_TGPR]
429#define msr_tlb env->msr[MSR_TLB]
430#define msr_ce env->msr[MSR_CE]
79aceca5
FB		 431#define msr_ile env->msr[MSR_ILE]
432#define msr_ee env->msr[MSR_EE]
433#define msr_pr env->msr[MSR_PR]
434#define msr_fp env->msr[MSR_FP]
435#define msr_me env->msr[MSR_ME]
436#define msr_fe0 env->msr[MSR_FE0]
437#define msr_se env->msr[MSR_SE]
3fc6c082 438#define msr_dwe env->msr[MSR_DWE]
79aceca5 439#define msr_be env->msr[MSR_BE]
3fc6c082 440#define msr_de env->msr[MSR_DE]
79aceca5 441#define msr_fe1 env->msr[MSR_FE1]
3fc6c082 442#define msr_al env->msr[MSR_AL]
79aceca5
FB		 443#define msr_ip env->msr[MSR_IP]
444#define msr_ir env->msr[MSR_IR]
3fc6c082 445#define msr_is env->msr[MSR_IS]
79aceca5 446#define msr_dr env->msr[MSR_DR]
3fc6c082
FB		 447#define msr_ds env->msr[MSR_DS]
448#define msr_pe env->msr[MSR_PE]
449#define msr_ep env->msr[MSR_EP]
450#define msr_px env->msr[MSR_PX]
451#define msr_pmm env->msr[MSR_PMM]
79aceca5
FB		 452#define msr_ri env->msr[MSR_RI]
453#define msr_le env->msr[MSR_LE]
454
3fc6c082
FB		 455/*****************************************************************************/
456/* The whole PowerPC CPU context */
457struct CPUPPCState {
458 /* First are the most commonly used resources
459 * during translated code execution
460 */
461#if TARGET_LONG_BITS > HOST_LONG_BITS
462 /* temporary fixed-point registers
463 * used to emulate 64 bits target on 32 bits hosts
464 */
465 target_ulong t0, t1, t2;
466#endif
79aceca5 467 /* general purpose registers */
3fc6c082
FB		 468 target_ulong gpr[32];
469 /* LR */
470 target_ulong lr;
471 /* CTR */
472 target_ulong ctr;
473 /* condition register */
474 uint8_t crf[8];
79aceca5 475 /* XER */
3fc6c082
FB		 476 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
477 uint8_t xer[8];
79aceca5 478 /* Reservation address */
3fc6c082
FB		 479 target_ulong reserve;
480
481 /* Those ones are used in supervisor mode only */
79aceca5 482 /* machine state register */
3fc6c082
FB		 483 uint8_t msr[64];
484 /* temporary general purpose registers */
485 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
486
487 /* Floating point execution context */
fb0eaffc 488 /* temporary float registers */
4ecc3190
FB		 489 float64 ft0;
490 float64 ft1;
491 float64 ft2;
492 float_status fp_status;
3fc6c082
FB		 493 /* floating point registers */
494 float64 fpr[32];
495 /* floating point status and control register */
496 uint8_t fpscr[8];
4ecc3190 497
a316d335
FB		 498 CPU_COMMON
499
50443c98
FB		 500 int halted; /* TRUE if the CPU is in suspend state */
501
ac9eb073
FB		 502 int access_type; /* when a memory exception occurs, the access
503 type is stored here */
a541f297 504
3fc6c082
FB		 505 /* MMU context */
506 /* Address space register */
507 target_ulong asr;
508 /* segment registers */
509 target_ulong sdr1;
510 target_ulong sr[16];
511 /* BATs */
512 int nb_BATs;
513 target_ulong DBAT[2][8];
514 target_ulong IBAT[2][8];
9fddaa0c 515
3fc6c082
FB		 516 /* Other registers */
517 /* Special purpose registers */
518 target_ulong spr[1024];
519 /* Altivec registers */
520 ppc_avr_t avr[32];
521 uint32_t vscr;
522
523 /* Internal devices resources */
9fddaa0c
FB		 524 /* Time base and decrementer */
525 ppc_tb_t *tb_env;
3fc6c082
FB		 526 /* Device control registers */
527 int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val);
528 int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val);
529 ppc_dcr_t *dcr_env;
530
531 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
532 int nb_tlb;
533 int nb_ways, last_way;
534 ppc_tlb_t tlb[128];
535 /* Callbacks for specific checks on some implementations */
536 int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,
537 target_ulong vaddr, int rw, int acc_type,
538 int is_user);
539 /* 403 dedicated access protection registers */
540 target_ulong pb[4];
541
542 /* Those resources are used during exception processing */
543 /* CPU model definition */
544 uint64_t msr_mask;
545 uint32_t flags;
546
547 int exception_index;
548 int error_code;
549 int interrupt_request;
550
551 /* Those resources are used only during code translation */
552 /* Next instruction pointer */
553 target_ulong nip;
554 /* SPR translation callbacks */
555 ppc_spr_t spr_cb[1024];
556 /* opcode handlers */
557 opc_handler_t *opcodes[0x40];
558
559 /* Those resources are used only in Qemu core */
560 jmp_buf jmp_env;
561 int user_mode_only; /* user mode only simulation */
3fc6c082
FB		 562 uint32_t hflags;
563
9fddaa0c
FB		 564 /* Power management */
565 int power_mode;
a541f297 566
6d506e6d
FB		 567 /* temporary hack to handle OSI calls (only used if non NULL) */
568 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 569};
79aceca5 570
3fc6c082 571/*****************************************************************************/
79aceca5
FB		 572CPUPPCState *cpu_ppc_init(void);
573int cpu_ppc_exec(CPUPPCState *s);
574void cpu_ppc_close(CPUPPCState *s);
575/* you can call this signal handler from your SIGBUS and SIGSEGV
576 signal handlers to inform the virtual CPU of exceptions. non zero
577 is returned if the signal was handled by the virtual CPU. */
5a7b542b 578int cpu_ppc_signal_handler(int host_signum, void *pinfo,
79aceca5
FB		 579 void *puc);
580
a541f297 581void do_interrupt (CPUPPCState *env);
9a64fbe4 582void cpu_loop_exit(void);
a541f297 583
9a64fbe4 584void dump_stack (CPUPPCState *env);
a541f297 585
3fc6c082
FB		 586target_ulong do_load_ibatu (CPUPPCState *env, int nr);
587target_ulong do_load_ibatl (CPUPPCState *env, int nr);
588void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
589void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
590target_ulong do_load_dbatu (CPUPPCState *env, int nr);
591target_ulong do_load_dbatl (CPUPPCState *env, int nr);
592void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
593void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
594
595target_ulong do_load_nip (CPUPPCState *env);
596void do_store_nip (CPUPPCState *env, target_ulong value);
597target_ulong do_load_sdr1 (CPUPPCState *env);
598void do_store_sdr1 (CPUPPCState *env, target_ulong value);
599target_ulong do_load_asr (CPUPPCState *env);
600void do_store_asr (CPUPPCState *env, target_ulong value);
601target_ulong do_load_sr (CPUPPCState *env, int srnum);
602void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
603uint32_t do_load_cr (CPUPPCState *env);
604void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask);
605uint32_t do_load_xer (CPUPPCState *env);
606void do_store_xer (CPUPPCState *env, uint32_t value);
607target_ulong do_load_msr (CPUPPCState *env);
608void do_store_msr (CPUPPCState *env, target_ulong value);
609float64 do_load_fpscr (CPUPPCState *env);
610void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask);
611
612void do_compute_hflags (CPUPPCState *env);
a541f297 613
3fc6c082
FB		 614int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
615int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
616void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
617int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
85c4adf6 618
9fddaa0c
FB		 619/* Time-base and decrementer management */
620#ifndef NO_CPU_IO_DEFS
621uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
622uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
623void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
624void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
625uint32_t cpu_ppc_load_decr (CPUPPCState *env);
626void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
627#endif
79aceca5
FB		 628
629#define TARGET_PAGE_BITS 12
630#include "cpu-all.h"
631
3fc6c082
FB		 632/*****************************************************************************/
633/* Registers definitions */
79aceca5 634#define ugpr(n) (env->gpr[n])
79aceca5 635
79aceca5
FB		 636#define XER_SO 31
637#define XER_OV 30
638#define XER_CA 29
3fc6c082 639#define XER_CMP 8
79aceca5 640#define XER_BC 0
3fc6c082
FB		 641#define xer_so env->xer[4]
642#define xer_ov env->xer[6]
643#define xer_ca env->xer[2]
644#define xer_cmp env->xer[1]
9a64fbe4 645#define xer_bc env->xer[0]
79aceca5 646
3fc6c082
FB		 647/* SPR definitions */
648#define SPR_MQ (0x000)
649#define SPR_XER (0x001)
650#define SPR_601_VRTCU (0x004)
651#define SPR_601_VRTCL (0x005)
652#define SPR_601_UDECR (0x006)
653#define SPR_LR (0x008)
654#define SPR_CTR (0x009)
655#define SPR_DSISR (0x012)
656#define SPR_DAR (0x013)
657#define SPR_601_RTCU (0x014)
658#define SPR_601_RTCL (0x015)
659#define SPR_DECR (0x016)
660#define SPR_SDR1 (0x019)
661#define SPR_SRR0 (0x01A)
662#define SPR_SRR1 (0x01B)
663#define SPR_440_PID (0x030)
664#define SPR_440_DECAR (0x036)
665#define SPR_CSRR0 (0x03A)
666#define SPR_CSRR1 (0x03B)
667#define SPR_440_DEAR (0x03D)
668#define SPR_440_ESR (0x03E)
669#define SPR_440_IVPR (0x03F)
670#define SPR_8xx_EIE (0x050)
671#define SPR_8xx_EID (0x051)
672#define SPR_8xx_NRE (0x052)
673#define SPR_58x_CMPA (0x090)
674#define SPR_58x_CMPB (0x091)
675#define SPR_58x_CMPC (0x092)
676#define SPR_58x_CMPD (0x093)
677#define SPR_58x_ICR (0x094)
678#define SPR_58x_DER (0x094)
679#define SPR_58x_COUNTA (0x096)
680#define SPR_58x_COUNTB (0x097)
681#define SPR_58x_CMPE (0x098)
682#define SPR_58x_CMPF (0x099)
683#define SPR_58x_CMPG (0x09A)
684#define SPR_58x_CMPH (0x09B)
685#define SPR_58x_LCTRL1 (0x09C)
686#define SPR_58x_LCTRL2 (0x09D)
687#define SPR_58x_ICTRL (0x09E)
688#define SPR_58x_BAR (0x09F)
689#define SPR_VRSAVE (0x100)
690#define SPR_USPRG0 (0x100)
691#define SPR_USPRG4 (0x104)
692#define SPR_USPRG5 (0x105)
693#define SPR_USPRG6 (0x106)
694#define SPR_USPRG7 (0x107)
695#define SPR_VTBL (0x10C)
696#define SPR_VTBU (0x10D)
697#define SPR_SPRG0 (0x110)
698#define SPR_SPRG1 (0x111)
699#define SPR_SPRG2 (0x112)
700#define SPR_SPRG3 (0x113)
701#define SPR_SPRG4 (0x114)
702#define SPR_SCOMC (0x114)
703#define SPR_SPRG5 (0x115)
704#define SPR_SCOMD (0x115)
705#define SPR_SPRG6 (0x116)
706#define SPR_SPRG7 (0x117)
707#define SPR_ASR (0x118)
708#define SPR_EAR (0x11A)
709#define SPR_TBL (0x11C)
710#define SPR_TBU (0x11D)
711#define SPR_SVR (0x11E)
712#define SPR_440_PIR (0x11E)
713#define SPR_PVR (0x11F)
714#define SPR_HSPRG0 (0x130)
715#define SPR_440_DBSR (0x130)
716#define SPR_HSPRG1 (0x131)
717#define SPR_440_DBCR0 (0x134)
718#define SPR_IBCR (0x135)
719#define SPR_440_DBCR1 (0x135)
720#define SPR_DBCR (0x136)
721#define SPR_HDEC (0x136)
722#define SPR_440_DBCR2 (0x136)
723#define SPR_HIOR (0x137)
724#define SPR_MBAR (0x137)
725#define SPR_RMOR (0x138)
726#define SPR_440_IAC1 (0x138)
727#define SPR_HRMOR (0x139)
728#define SPR_440_IAC2 (0x139)
729#define SPR_HSSR0 (0x13A)
730#define SPR_440_IAC3 (0x13A)
731#define SPR_HSSR1 (0x13B)
732#define SPR_440_IAC4 (0x13B)
733#define SPR_LPCR (0x13C)
734#define SPR_440_DAC1 (0x13C)
735#define SPR_LPIDR (0x13D)
736#define SPR_DABR2 (0x13D)
737#define SPR_440_DAC2 (0x13D)
738#define SPR_440_DVC1 (0x13E)
739#define SPR_440_DVC2 (0x13F)
740#define SPR_440_TSR (0x150)
741#define SPR_440_TCR (0x154)
742#define SPR_440_IVOR0 (0x190)
743#define SPR_440_IVOR1 (0x191)
744#define SPR_440_IVOR2 (0x192)
745#define SPR_440_IVOR3 (0x193)
746#define SPR_440_IVOR4 (0x194)
747#define SPR_440_IVOR5 (0x195)
748#define SPR_440_IVOR6 (0x196)
749#define SPR_440_IVOR7 (0x197)
750#define SPR_440_IVOR8 (0x198)
751#define SPR_440_IVOR9 (0x199)
752#define SPR_440_IVOR10 (0x19A)
753#define SPR_440_IVOR11 (0x19B)
754#define SPR_440_IVOR12 (0x19C)
755#define SPR_440_IVOR13 (0x19D)
756#define SPR_440_IVOR14 (0x19E)
757#define SPR_440_IVOR15 (0x19F)
758#define SPR_IBAT0U (0x210)
759#define SPR_IBAT0L (0x211)
760#define SPR_IBAT1U (0x212)
761#define SPR_IBAT1L (0x213)
762#define SPR_IBAT2U (0x214)
763#define SPR_IBAT2L (0x215)
764#define SPR_IBAT3U (0x216)
765#define SPR_IBAT3L (0x217)
766#define SPR_DBAT0U (0x218)
767#define SPR_DBAT0L (0x219)
768#define SPR_DBAT1U (0x21A)
769#define SPR_DBAT1L (0x21B)
770#define SPR_DBAT2U (0x21C)
771#define SPR_DBAT2L (0x21D)
772#define SPR_DBAT3U (0x21E)
773#define SPR_DBAT3L (0x21F)
774#define SPR_IBAT4U (0x230)
775#define SPR_IBAT4L (0x231)
776#define SPR_IBAT5U (0x232)
777#define SPR_IBAT5L (0x233)
778#define SPR_IBAT6U (0x234)
779#define SPR_IBAT6L (0x235)
780#define SPR_IBAT7U (0x236)
781#define SPR_IBAT7L (0x237)
782#define SPR_DBAT4U (0x238)
783#define SPR_DBAT4L (0x239)
784#define SPR_DBAT5U (0x23A)
785#define SPR_DBAT5L (0x23B)
786#define SPR_DBAT6U (0x23C)
787#define SPR_DBAT6L (0x23D)
788#define SPR_DBAT7U (0x23E)
789#define SPR_DBAT7L (0x23F)
790#define SPR_440_INV0 (0x370)
791#define SPR_440_INV1 (0x371)
792#define SPR_440_INV2 (0x372)
793#define SPR_440_INV3 (0x373)
794#define SPR_440_IVT0 (0x374)
795#define SPR_440_IVT1 (0x375)
796#define SPR_440_IVT2 (0x376)
797#define SPR_440_IVT3 (0x377)
798#define SPR_440_DNV0 (0x390)
799#define SPR_440_DNV1 (0x391)
800#define SPR_440_DNV2 (0x392)
801#define SPR_440_DNV3 (0x393)
802#define SPR_440_DVT0 (0x394)
803#define SPR_440_DVT1 (0x395)
804#define SPR_440_DVT2 (0x396)
805#define SPR_440_DVT3 (0x397)
806#define SPR_440_DVLIM (0x398)
807#define SPR_440_IVLIM (0x399)
808#define SPR_440_RSTCFG (0x39B)
809#define SPR_440_DCBTRL (0x39C)
810#define SPR_440_DCBTRH (0x39D)
811#define SPR_440_ICBTRL (0x39E)
812#define SPR_440_ICBTRH (0x39F)
813#define SPR_UMMCR0 (0x3A8)
814#define SPR_UPMC1 (0x3A9)
815#define SPR_UPMC2 (0x3AA)
816#define SPR_USIA (0x3AB)
817#define SPR_UMMCR1 (0x3AC)
818#define SPR_UPMC3 (0x3AD)
819#define SPR_UPMC4 (0x3AE)
820#define SPR_USDA (0x3AF)
821#define SPR_40x_ZPR (0x3B0)
822#define SPR_40x_PID (0x3B1)
823#define SPR_440_MMUCR (0x3B2)
824#define SPR_4xx_CCR0 (0x3B3)
825#define SPR_405_IAC3 (0x3B4)
826#define SPR_405_IAC4 (0x3B5)
827#define SPR_405_DVC1 (0x3B6)
828#define SPR_405_DVC2 (0x3B7)
829#define SPR_MMCR0 (0x3B8)
830#define SPR_PMC1 (0x3B9)
831#define SPR_40x_SGR (0x3B9)
832#define SPR_PMC2 (0x3BA)
833#define SPR_40x_DCWR (0x3BA)
834#define SPR_SIA (0x3BB)
835#define SPR_405_SLER (0x3BB)
836#define SPR_MMCR1 (0x3BC)
837#define SPR_405_SU0R (0x3BC)
838#define SPR_PMC3 (0x3BD)
839#define SPR_405_DBCR1 (0x3BD)
840#define SPR_PMC4 (0x3BE)
841#define SPR_SDA (0x3BF)
842#define SPR_403_VTBL (0x3CC)
843#define SPR_403_VTBU (0x3CD)
844#define SPR_DMISS (0x3D0)
845#define SPR_DCMP (0x3D1)
846#define SPR_DHASH1 (0x3D2)
847#define SPR_DHASH2 (0x3D3)
848#define SPR_4xx_ICDBDR (0x3D3)
849#define SPR_IMISS (0x3D4)
850#define SPR_40x_ESR (0x3D4)
851#define SPR_ICMP (0x3D5)
852#define SPR_40x_DEAR (0x3D5)
853#define SPR_RPA (0x3D6)
854#define SPR_40x_EVPR (0x3D6)
855#define SPR_403_CDBCR (0x3D7)
856#define SPR_TCR (0x3D8)
857#define SPR_40x_TSR (0x3D8)
858#define SPR_IBR (0x3DA)
859#define SPR_40x_TCR (0x3DA)
860#define SPR_ESASR (0x3DB)
861#define SPR_40x_PIT (0x3DB)
862#define SPR_403_TBL (0x3DC)
863#define SPR_403_TBU (0x3DD)
864#define SPR_SEBR (0x3DE)
865#define SPR_40x_SRR2 (0x3DE)
866#define SPR_SER (0x3DF)
867#define SPR_40x_SRR3 (0x3DF)
868#define SPR_HID0 (0x3F0)
869#define SPR_40x_DBSR (0x3F0)
870#define SPR_HID1 (0x3F1)
871#define SPR_IABR (0x3F2)
872#define SPR_40x_DBCR0 (0x3F2)
873#define SPR_601_HID2 (0x3F2)
874#define SPR_HID2 (0x3F3)
875#define SPR_440_DBDR (0x3F3)
876#define SPR_40x_IAC1 (0x3F4)
877#define SPR_DABR (0x3F5)
878#define DABR_MASK (~(target_ulong)0x7)
879#define SPR_40x_IAC2 (0x3F5)
880#define SPR_601_HID5 (0x3F5)
881#define SPR_40x_DAC1 (0x3F6)
882#define SPR_40x_DAC2 (0x3F7)
883#define SPR_L2PM (0x3F8)
884#define SPR_750_HID2 (0x3F8)
885#define SPR_L2CR (0x3F9)
886#define SPR_IABR2 (0x3FA)
887#define SPR_40x_DCCR (0x3FA)
888#define SPR_ICTC (0x3FB)
889#define SPR_40x_ICCR (0x3FB)
890#define SPR_THRM1 (0x3FC)
891#define SPR_403_PBL1 (0x3FC)
892#define SPR_SP (0x3FD)
893#define SPR_THRM2 (0x3FD)
894#define SPR_403_PBU1 (0x3FD)
895#define SPR_LT (0x3FE)
896#define SPR_THRM3 (0x3FE)
897#define SPR_FPECR (0x3FE)
898#define SPR_403_PBL2 (0x3FE)
899#define SPR_PIR (0x3FF)
900#define SPR_403_PBU2 (0x3FF)
901#define SPR_601_HID15 (0x3FF)
79aceca5 902
9a64fbe4
FB		 903/* Memory access type :
904 * may be needed for precise access rights control and precise exceptions.
905 */
79aceca5 906enum {
9a64fbe4
FB		 907 /* 1 bit to define user level / supervisor access */
908 ACCESS_USER = 0x00,
909 ACCESS_SUPER = 0x01,
910 /* Type of instruction that generated the access */
911 ACCESS_CODE = 0x10, /* Code fetch access */
912 ACCESS_INT = 0x20, /* Integer load/store access */
913 ACCESS_FLOAT = 0x30, /* floating point load/store access */
914 ACCESS_RES = 0x40, /* load/store with reservation */
915 ACCESS_EXT = 0x50, /* external access */
916 ACCESS_CACHE = 0x60, /* Cache manipulation */
917};
918
919/*****************************************************************************/
920/* Exceptions */
2be0071f
FB		 921#define EXCP_NONE -1
922/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
923#define EXCP_RESET 0x0100 /* System reset */
924#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */
925#define EXCP_DSI 0x0300 /* Data storage exception */
926#define EXCP_DSEG 0x0380 /* Data segment exception */
927#define EXCP_ISI 0x0400 /* Instruction storage exception */
928#define EXCP_ISEG 0x0480 /* Instruction segment exception */
929#define EXCP_EXTERNAL 0x0500 /* External interruption */
930#define EXCP_ALIGN 0x0600 /* Alignment exception */
931#define EXCP_PROGRAM 0x0700 /* Program exception */
932#define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */
933#define EXCP_DECR 0x0900 /* Decrementer exception */
934#define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */
935#define EXCP_SYSCALL 0x0C00 /* System call */
936#define EXCP_TRACE 0x0D00 /* Trace exception */
937#define EXCP_PERF 0x0F00 /* Performance monitor exception */
938/* Exceptions defined in PowerPC 32 bits programming environment manual */
939#define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */
940/* Implementation specific exceptions */
941/* 40x exceptions */
942#define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */
943#define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */
944#define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */
945#define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */
946#define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */
947#define EXCP_40x_DEBUG 0x2000 /* Debug exception */
948/* 405 specific exceptions */
949#define EXCP_405_APU 0x0F20 /* APU unavailable exception */
950/* TLB assist exceptions (602/603) */
951#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */
952#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */
953#define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */
954/* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
955#define EXCP_IABR 0x1300 /* Instruction address breakpoint */
956#define EXCP_SMI 0x1400 /* System management interrupt */
957/* Altivec related exceptions */
958#define EXCP_VPU 0x0F20 /* VPU unavailable exception */
959/* 601 specific exceptions */
960#define EXCP_601_IO 0x0600 /* IO error exception */
961#define EXCP_601_RUNM 0x2000 /* Run mode exception */
962/* 602 specific exceptions */
963#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */
964#define EXCP_602_EMUL 0x1600 /* Emulation trap exception */
965/* G2 specific exceptions */
966#define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */
967/* MPC740/745/750 & IBM 750 specific exceptions */
968#define EXCP_THRM 0x1700 /* Thermal management interrupt */
969/* 74xx specific exceptions */
970#define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */
971/* 970FX specific exceptions */
972#define EXCP_970_SOFTP 0x1500 /* Soft patch exception */
973#define EXCP_970_MAINT 0x1600 /* Maintenance exception */
974#define EXCP_970_THRM 0x1800 /* Thermal exception */
975#define EXCP_970_VPUA 0x1700 /* VPU assist exception */
976/* End of exception vectors area */
977#define EXCP_PPC_MAX 0x4000
978/* Qemu exceptions: special cases we want to stop translation */
979#define EXCP_MTMSR 0x11000 /* mtmsr instruction: */
9a64fbe4 980 /* may change privilege level */
2be0071f
FB		 981#define EXCP_BRANCH 0x11001 /* branch instruction */
982#define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */
983#define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ */
984
9a64fbe4
FB		 985/* Error codes */
986enum {
9a64fbe4
FB		 987 /* Exception subtypes for EXCP_ALIGN */
988 EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
989 EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
990 EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
991 EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
992 EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
993 EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
994 /* Exception subtypes for EXCP_PROGRAM */
79aceca5 995 /* FP exceptions */
9a64fbe4
FB		 996 EXCP_FP = 0x10,
997 EXCP_FP_OX = 0x01, /* FP overflow */
998 EXCP_FP_UX = 0x02, /* FP underflow */
999 EXCP_FP_ZX = 0x03, /* FP divide by zero */
1000 EXCP_FP_XX = 0x04, /* FP inexact */
1001 EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
1002 EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */
1003 EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
1004 EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
1005 EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
1006 EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
1007 EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
1008 EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
1009 EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
79aceca5 1010 /* Invalid instruction */
9a64fbe4
FB		 1011 EXCP_INVAL = 0x20,
1012 EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
1013 EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
1014 EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
1015 EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
79aceca5 1016 /* Privileged instruction */
9a64fbe4
FB		 1017 EXCP_PRIV = 0x30,
1018 EXCP_PRIV_OPC = 0x01,
1019 EXCP_PRIV_REG = 0x02,
79aceca5 1020 /* Trap */
9a64fbe4 1021 EXCP_TRAP = 0x40,
79aceca5
FB		 1022};
1023
9a64fbe4
FB		 1024/*****************************************************************************/
1025
79aceca5 1026#endif /* !defined (__CPU_PPC_H__) */
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