]> git.proxmox.com Git - mirror_qemu.git/blame - target-ppc/cpu.h
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
PowerPC target coding style fixes.
[mirror_qemu.git] / target-ppc / cpu.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#if !defined (__CPU_PPC_H__)
21#define __CPU_PPC_H__
22
3fc6c082 23#include "config.h"
de270b3c 24#include <inttypes.h>
3fc6c082 25
76a66253
JM		 26#if defined (TARGET_PPC64)
27typedef uint64_t ppc_gpr_t;
0487d6a8 28#define TARGET_GPR_BITS 64
d9d7210c 29#define TARGET_LONG_BITS 64
76a66253 30#define REGX "%016" PRIx64
35cdaad6
JM		 31#define TARGET_PAGE_BITS 12
32#elif defined(TARGET_PPCEMB)
8b67546f 33/* BookE have 36 bits physical address space */
e96efcfc 34#define TARGET_PHYS_ADDR_BITS 64
76a66253
JM		 35/* GPR are 64 bits: used by vector extension */
36typedef uint64_t ppc_gpr_t;
0487d6a8 37#define TARGET_GPR_BITS 64
d9d7210c 38#define TARGET_LONG_BITS 32
1b9eb036 39#define REGX "%016" PRIx64
d9d7210c
JM		 40#if defined(CONFIG_USER_ONLY)
41/* It looks like a lot of Linux programs assume page size
42 * is 4kB long. This is evil, but we have to deal with it...
43 */
44#define TARGET_PAGE_BITS 12
45#else
35cdaad6
JM		 46/* Pages can be 1 kB small */
47#define TARGET_PAGE_BITS 10
d9d7210c
JM		 48#endif
49#else
50#if (HOST_LONG_BITS >= 64)
51/* When using 64 bits temporary registers,
52 * we can use 64 bits GPR with no extra cost
53 * It's even an optimization as it will prevent
54 * the compiler to do unuseful masking in the micro-ops.
55 */
56typedef uint64_t ppc_gpr_t;
57#define TARGET_GPR_BITS 64
71c8b8fd 58#define REGX "%08" PRIx64
76a66253
JM		 59#else
60typedef uint32_t ppc_gpr_t;
0487d6a8 61#define TARGET_GPR_BITS 32
71c8b8fd 62#define REGX "%08" PRIx32
d9d7210c
JM		 63#endif
64#define TARGET_LONG_BITS 32
35cdaad6 65#define TARGET_PAGE_BITS 12
76a66253 66#endif
3cf1e035 67
79aceca5
FB		 68#include "cpu-defs.h"
69
e96efcfc
JM		 70#define ADDRX TARGET_FMT_lx
71#define PADDRX TARGET_FMT_plx
72
79aceca5
FB		 73#include <setjmp.h>
74
4ecc3190
FB		 75#include "softfloat.h"
76
1fddef4b
FB		 77#define TARGET_HAS_ICE 1
78
76a66253
JM		 79#if defined (TARGET_PPC64)
80#define ELF_MACHINE EM_PPC64
81#else
82#define ELF_MACHINE EM_PPC
83#endif
9042c0e2 84
3fc6c082 85/*****************************************************************************/
a750fc0b 86/* MMU model */
3fc6c082 87enum {
a750fc0b
JM		 88 POWERPC_MMU_UNKNOWN = 0,
89 /* Standard 32 bits PowerPC MMU */
90 POWERPC_MMU_32B,
a750fc0b
JM		 91 /* PowerPC 601 MMU */
92 POWERPC_MMU_601,
93 /* PowerPC 6xx MMU with software TLB */
94 POWERPC_MMU_SOFT_6xx,
95 /* PowerPC 74xx MMU with software TLB */
96 POWERPC_MMU_SOFT_74xx,
97 /* PowerPC 4xx MMU with software TLB */
98 POWERPC_MMU_SOFT_4xx,
99 /* PowerPC 4xx MMU with software TLB and zones protections */
100 POWERPC_MMU_SOFT_4xx_Z,
101 /* PowerPC 4xx MMU in real mode only */
102 POWERPC_MMU_REAL_4xx,
103 /* BookE MMU model */
104 POWERPC_MMU_BOOKE,
105 /* BookE FSL MMU model */
106 POWERPC_MMU_BOOKE_FSL,
00af685f 107#if defined(TARGET_PPC64)
12de9a39 108 /* 64 bits PowerPC MMU */
00af685f 109 POWERPC_MMU_64B,
00af685f 110#endif /* defined(TARGET_PPC64) */
3fc6c082
FB		 111};
112
113/*****************************************************************************/
a750fc0b 114/* Exception model */
3fc6c082 115enum {
a750fc0b 116 POWERPC_EXCP_UNKNOWN = 0,
3fc6c082 117 /* Standard PowerPC exception model */
a750fc0b 118 POWERPC_EXCP_STD,
2662a059 119 /* PowerPC 40x exception model */
a750fc0b 120 POWERPC_EXCP_40x,
2662a059 121 /* PowerPC 601 exception model */
a750fc0b 122 POWERPC_EXCP_601,
2662a059 123 /* PowerPC 602 exception model */
a750fc0b 124 POWERPC_EXCP_602,
2662a059 125 /* PowerPC 603 exception model */
a750fc0b
JM		 126 POWERPC_EXCP_603,
127 /* PowerPC 603e exception model */
128 POWERPC_EXCP_603E,
129 /* PowerPC G2 exception model */
130 POWERPC_EXCP_G2,
2662a059 131 /* PowerPC 604 exception model */
a750fc0b 132 POWERPC_EXCP_604,
2662a059 133 /* PowerPC 7x0 exception model */
a750fc0b 134 POWERPC_EXCP_7x0,
2662a059 135 /* PowerPC 7x5 exception model */
a750fc0b 136 POWERPC_EXCP_7x5,
2662a059 137 /* PowerPC 74xx exception model */
a750fc0b 138 POWERPC_EXCP_74xx,
2662a059 139 /* BookE exception model */
a750fc0b 140 POWERPC_EXCP_BOOKE,
00af685f
JM		 141#if defined(TARGET_PPC64)
142 /* PowerPC 970 exception model */
143 POWERPC_EXCP_970,
144#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 145};
146
e1833e1f
JM		 147/*****************************************************************************/
148/* Exception vectors definitions */
149enum {
150 POWERPC_EXCP_NONE = -1,
151 /* The 64 first entries are used by the PowerPC embedded specification */
152 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
153 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
154 POWERPC_EXCP_DSI = 2, /* Data storage exception */
155 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
156 POWERPC_EXCP_EXTERNAL = 4, /* External input */
157 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
158 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
159 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
160 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
161 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
162 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
163 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
164 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
165 POWERPC_EXCP_DTLB = 13, /* Data TLB error */
166 POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */
167 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
168 /* Vectors 16 to 31 are reserved */
169#if defined(TARGET_PPCEMB)
170 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
171 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
172 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
173 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
174 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
175 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
176#endif /* defined(TARGET_PPCEMB) */
177 /* Vectors 38 to 63 are reserved */
178 /* Exceptions defined in the PowerPC server specification */
179 POWERPC_EXCP_RESET = 64, /* System reset exception */
180#if defined(TARGET_PPC64) /* PowerPC 64 */
181 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
182 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
183#endif /* defined(TARGET_PPC64) */
184#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
185 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
186#endif /* defined(TARGET_PPC64H) */
187 POWERPC_EXCP_TRACE = 68, /* Trace exception */
188#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
189 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
190 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
191 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
192 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
193#endif /* defined(TARGET_PPC64H) */
194 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
195 /* 40x specific exceptions */
196 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
197 /* 601 specific exceptions */
198 POWERPC_EXCP_IO = 75, /* IO error exception */
199 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
200 /* 602 specific exceptions */
201 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
202 /* 602/603 specific exceptions */
203 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */
204 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
205 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
206 /* Exceptions available on most PowerPC */
207 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
208 POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */
209 POWERPC_EXCP_SMI = 83, /* System management interrupt */
210 POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */
211 /* 7xx/74xx specific exceptions */
212 POWERPC_EXCP_THERM = 85, /* Thermal interrupt */
213 /* 74xx specific exceptions */
214 POWERPC_EXCP_VPUA = 86, /* Vector assist exception */
215 /* 970FX specific exceptions */
216 POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */
217 POWERPC_EXCP_MAINT = 88, /* Maintenance exception */
218 /* EOL */
219 POWERPC_EXCP_NB = 96,
220 /* Qemu exceptions: used internally during code translation */
221 POWERPC_EXCP_STOP = 0x200, /* stop translation */
222 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
223 /* Qemu exceptions: special cases we want to stop translation */
224 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
225 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
226};
227
e1833e1f
JM		 228/* Exceptions error codes */
229enum {
230 /* Exception subtypes for POWERPC_EXCP_ALIGN */
231 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
232 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
233 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
234 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
235 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
236 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
237 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
238 /* FP exceptions */
239 POWERPC_EXCP_FP = 0x10,
240 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
241 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
242 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
243 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
244 POWERPC_EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */
245 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
246 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
247 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
248 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
249 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
250 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
251 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
252 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
253 /* Invalid instruction */
254 POWERPC_EXCP_INVAL = 0x20,
255 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
256 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
257 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
258 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
259 /* Privileged instruction */
260 POWERPC_EXCP_PRIV = 0x30,
261 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
262 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
263 /* Trap */
264 POWERPC_EXCP_TRAP = 0x40,
265};
266
a750fc0b
JM		 267/*****************************************************************************/
268/* Input pins model */
269enum {
270 PPC_FLAGS_INPUT_UNKNOWN = 0,
2662a059 271 /* PowerPC 6xx bus */
a750fc0b 272 PPC_FLAGS_INPUT_6xx,
2662a059 273 /* BookE bus */
a750fc0b
JM		 274 PPC_FLAGS_INPUT_BookE,
275 /* PowerPC 405 bus */
276 PPC_FLAGS_INPUT_405,
2662a059 277 /* PowerPC 970 bus */
a750fc0b
JM		 278 PPC_FLAGS_INPUT_970,
279 /* PowerPC 401 bus */
280 PPC_FLAGS_INPUT_401,
3fc6c082
FB		 281};
282
a750fc0b 283#define PPC_INPUT(env) (env->bus_model)
3fc6c082 284
be147d08 285/*****************************************************************************/
3fc6c082 286typedef struct ppc_def_t ppc_def_t;
a750fc0b 287typedef struct opc_handler_t opc_handler_t;
79aceca5 288
3fc6c082
FB		 289/*****************************************************************************/
290/* Types used to describe some PowerPC registers */
291typedef struct CPUPPCState CPUPPCState;
9fddaa0c 292typedef struct ppc_tb_t ppc_tb_t;
3fc6c082
FB		 293typedef struct ppc_spr_t ppc_spr_t;
294typedef struct ppc_dcr_t ppc_dcr_t;
295typedef struct ppc_avr_t ppc_avr_t;
1d0a48fb 296typedef union ppc_tlb_t ppc_tlb_t;
76a66253 297
3fc6c082
FB		 298/* SPR access micro-ops generations callbacks */
299struct ppc_spr_t {
300 void (*uea_read)(void *opaque, int spr_num);
301 void (*uea_write)(void *opaque, int spr_num);
76a66253 302#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 303 void (*oea_read)(void *opaque, int spr_num);
304 void (*oea_write)(void *opaque, int spr_num);
be147d08
JM		 305#if defined(TARGET_PPC64H)
306 void (*hea_read)(void *opaque, int spr_num);
307 void (*hea_write)(void *opaque, int spr_num);
308#endif
76a66253 309#endif
3fc6c082
FB		 310 const unsigned char *name;
311};
312
313/* Altivec registers (128 bits) */
314struct ppc_avr_t {
315 uint32_t u[4];
316};
9fddaa0c 317
3fc6c082 318/* Software TLB cache */
1d0a48fb
JM		 319typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
320struct ppc6xx_tlb_t {
76a66253
JM		 321 target_ulong pte0;
322 target_ulong pte1;
323 target_ulong EPN;
1d0a48fb
JM		 324};
325
326typedef struct ppcemb_tlb_t ppcemb_tlb_t;
327struct ppcemb_tlb_t {
c55e9aef 328 target_phys_addr_t RPN;
1d0a48fb 329 target_ulong EPN;
76a66253 330 target_ulong PID;
c55e9aef
JM		 331 target_ulong size;
332 uint32_t prot;
333 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 334};
335
336union ppc_tlb_t {
337 ppc6xx_tlb_t tlb6;
338 ppcemb_tlb_t tlbe;
3fc6c082
FB		 339};
340
341/*****************************************************************************/
342/* Machine state register bits definition */
76a66253 343#define MSR_SF 63 /* Sixty-four-bit mode hflags */
3fc6c082 344#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
76a66253 345#define MSR_HV 60 /* hypervisor state hflags */
363be49c
JM		 346#define MSR_CM 31 /* Computation mode for BookE hflags */
347#define MSR_ICM 30 /* Interrupt computation mode for BookE */
348#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 349#define MSR_VR 25 /* altivec available x hflags */
350#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253
JM		 351#define MSR_AP 23 /* Access privilege state on 602 hflags */
352#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 353#define MSR_KEY 19 /* key bit on 603e */
d26bfc9a
JM		 354#define MSR_POW 18 /* Power management x */
355#define MSR_WE 18 /* Wait state enable on embedded PowerPC x */
356#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
357#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 358#define MSR_ILE 16 /* Interrupt little-endian mode */
359#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 360#define MSR_PR 14 /* Problem state hflags */
361#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 362#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 363#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 364#define MSR_SE 10 /* Single-step trace enable x hflags */
365#define MSR_DWE 10 /* Debug wait enable on 405 x */
366#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
367#define MSR_BE 9 /* Branch trace enable x hflags */
368#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 369#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082
FB		 370#define MSR_AL 7 /* AL bit on POWER */
371#define MSR_IP 6 /* Interrupt prefix */
372#define MSR_IR 5 /* Instruction relocate */
3fc6c082 373#define MSR_DR 4 /* Data relocate */
d26bfc9a
JM		 374#define MSR_PE 3 /* Protection enable on 403 x */
375#define MSR_EP 3 /* Exception prefix on 601 x */
376#define MSR_PX 2 /* Protection exclusive on 403 x */
377#define MSR_PMM 2 /* Performance monitor mark on POWER x */
378#define MSR_RI 1 /* Recoverable interrupt 1 */
379#define MSR_LE 0 /* Little-endian mode 1 hflags */
3fc6c082
FB		 380#define msr_sf env->msr[MSR_SF]
381#define msr_isf env->msr[MSR_ISF]
382#define msr_hv env->msr[MSR_HV]
363be49c
JM		 383#define msr_cm env->msr[MSR_CM]
384#define msr_icm env->msr[MSR_ICM]
76a66253 385#define msr_ucle env->msr[MSR_UCLE]
3fc6c082 386#define msr_vr env->msr[MSR_VR]
76a66253 387#define msr_spe env->msr[MSR_SPE]
3fc6c082
FB		 388#define msr_ap env->msr[MSR_AP]
389#define msr_sa env->msr[MSR_SA]
390#define msr_key env->msr[MSR_KEY]
76a66253 391#define msr_pow env->msr[MSR_POW]
3fc6c082
FB		 392#define msr_we env->msr[MSR_WE]
393#define msr_tgpr env->msr[MSR_TGPR]
3fc6c082 394#define msr_ce env->msr[MSR_CE]
76a66253
JM		 395#define msr_ile env->msr[MSR_ILE]
396#define msr_ee env->msr[MSR_EE]
397#define msr_pr env->msr[MSR_PR]
398#define msr_fp env->msr[MSR_FP]
399#define msr_me env->msr[MSR_ME]
400#define msr_fe0 env->msr[MSR_FE0]
401#define msr_se env->msr[MSR_SE]
3fc6c082 402#define msr_dwe env->msr[MSR_DWE]
76a66253
JM		 403#define msr_uble env->msr[MSR_UBLE]
404#define msr_be env->msr[MSR_BE]
3fc6c082 405#define msr_de env->msr[MSR_DE]
76a66253 406#define msr_fe1 env->msr[MSR_FE1]
3fc6c082 407#define msr_al env->msr[MSR_AL]
76a66253
JM		 408#define msr_ip env->msr[MSR_IP]
409#define msr_ir env->msr[MSR_IR]
76a66253 410#define msr_dr env->msr[MSR_DR]
3fc6c082
FB		 411#define msr_pe env->msr[MSR_PE]
412#define msr_ep env->msr[MSR_EP]
413#define msr_px env->msr[MSR_PX]
414#define msr_pmm env->msr[MSR_PMM]
76a66253
JM		 415#define msr_ri env->msr[MSR_RI]
416#define msr_le env->msr[MSR_LE]
79aceca5 417
d26bfc9a
JM		 418enum {
419 /* Beware that MSR bits are given using IBM standard (ie MSB is 0 !) */
420 POWERPC_FLAG_NONE = 0x00000000,
421 /* Flag for MSR bit 25 signification (VRE/SPE) */
422 POWERPC_FLAG_SPE = 0x00000001,
423 POWERPC_FLAG_VRE = 0x00000002,
424 /* Flag for MSR bit 18 may not be needed... */
425 POWERPC_FLAG_POW = 0x00000004,
426 POWERPC_FLAG_WE = 0x00000008,
427 /* Flag for MSR bit 17 signification (TGPR/CE) */
428 POWERPC_FLAG_TGPR = 0x00000010,
429 POWERPC_FLAG_CE = 0x00000020,
430 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
431 POWERPC_FLAG_SE = 0x00000040,
432 POWERPC_FLAG_DWE = 0x00000080,
433 POWERPC_FLAG_UBLE = 0x00000100,
434 /* Flag for MSR bit 9 signification (BE/DE) */
435 POWERPC_FLAG_BE = 0x00000200,
436 POWERPC_FLAG_DE = 0x00000400,
437 /* Flag for MSR bit 3 signification (PE/EP) */
438 POWERPC_FLAG_PE = 0x00000800,
439 POWERPC_FLAG_EP = 0x00001000,
440 /* Flag for MSR but 2 signification (PX/PMM) */
441 POWERPC_FLAG_PX = 0x00002000,
442 POWERPC_FLAG_PMM = 0x00004000,
443};
444
3fc6c082
FB		 445/*****************************************************************************/
446/* The whole PowerPC CPU context */
447struct CPUPPCState {
448 /* First are the most commonly used resources
449 * during translated code execution
450 */
0487d6a8 451#if TARGET_GPR_BITS > HOST_LONG_BITS
3fc6c082
FB		 452 /* temporary fixed-point registers
453 * used to emulate 64 bits target on 32 bits hosts
5fafdf24 454 */
3c4c9f9f 455 ppc_gpr_t t0, t1, t2;
3fc6c082 456#endif
d9bce9d9
JM		 457 ppc_avr_t t0_avr, t1_avr, t2_avr;
458
79aceca5 459 /* general purpose registers */
76a66253 460 ppc_gpr_t gpr[32];
3fc6c082
FB		 461 /* LR */
462 target_ulong lr;
463 /* CTR */
464 target_ulong ctr;
465 /* condition register */
466 uint8_t crf[8];
79aceca5 467 /* XER */
3fc6c082
FB		 468 /* XXX: We use only 5 fields, but we want to keep the structure aligned */
469 uint8_t xer[8];
79aceca5 470 /* Reservation address */
3fc6c082
FB		 471 target_ulong reserve;
472
473 /* Those ones are used in supervisor mode only */
79aceca5 474 /* machine state register */
3fc6c082
FB		 475 uint8_t msr[64];
476 /* temporary general purpose registers */
76a66253 477 ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 478
479 /* Floating point execution context */
76a66253 480 /* temporary float registers */
4ecc3190
FB		 481 float64 ft0;
482 float64 ft1;
483 float64 ft2;
484 float_status fp_status;
3fc6c082
FB		 485 /* floating point registers */
486 float64 fpr[32];
487 /* floating point status and control register */
488 uint8_t fpscr[8];
4ecc3190 489
a316d335
FB		 490 CPU_COMMON
491
50443c98
FB		 492 int halted; /* TRUE if the CPU is in suspend state */
493
ac9eb073
FB		 494 int access_type; /* when a memory exception occurs, the access
495 type is stored here */
a541f297 496
f2e63a42
JM		 497 /* MMU context - only relevant for full system emulation */
498#if !defined(CONFIG_USER_ONLY)
499#if defined(TARGET_PPC64)
3fc6c082
FB		 500 /* Address space register */
501 target_ulong asr;
f2e63a42
JM		 502 /* PowerPC 64 SLB area */
503 int slb_nr;
504#endif
3fc6c082
FB		 505 /* segment registers */
506 target_ulong sdr1;
507 target_ulong sr[16];
508 /* BATs */
509 int nb_BATs;
510 target_ulong DBAT[2][8];
511 target_ulong IBAT[2][8];
f2e63a42
JM		 512 /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
513 int nb_tlb; /* Total number of TLB */
514 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
515 int nb_ways; /* Number of ways in the TLB set */
516 int last_way; /* Last used way used to allocate TLB in a LRU way */
517 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
518 int nb_pids; /* Number of available PID registers */
519 ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
520 /* 403 dedicated access protection registers */
521 target_ulong pb[4];
522#endif
9fddaa0c 523
3fc6c082
FB		 524 /* Other registers */
525 /* Special purpose registers */
526 target_ulong spr[1024];
f2e63a42 527 ppc_spr_t spr_cb[1024];
3fc6c082
FB		 528 /* Altivec registers */
529 ppc_avr_t avr[32];
530 uint32_t vscr;
f2e63a42 531#if defined(TARGET_PPCEMB)
d9bce9d9
JM		 532 /* SPE registers */
533 ppc_gpr_t spe_acc;
0487d6a8 534 float_status spe_status;
d9bce9d9 535 uint32_t spe_fscr;
f2e63a42 536#endif
3fc6c082
FB		 537
538 /* Internal devices resources */
9fddaa0c
FB		 539 /* Time base and decrementer */
540 ppc_tb_t *tb_env;
3fc6c082 541 /* Device control registers */
3fc6c082
FB		 542 ppc_dcr_t *dcr_env;
543
d63001d1
JM		 544 int dcache_line_size;
545 int icache_line_size;
546
3fc6c082
FB		 547 /* Those resources are used during exception processing */
548 /* CPU model definition */
a750fc0b
JM		 549 target_ulong msr_mask;
550 uint8_t mmu_model;
551 uint8_t excp_model;
552 uint8_t bus_model;
553 uint8_t pad;
237c0af0 554 int bfd_mach;
3fc6c082
FB		 555 uint32_t flags;
556
557 int exception_index;
558 int error_code;
559 int interrupt_request;
47103572 560 uint32_t pending_interrupts;
e9df014c
JM		 561#if !defined(CONFIG_USER_ONLY)
562 /* This is the IRQ controller, which is implementation dependant
563 * and only relevant when emulating a complete machine.
564 */
565 uint32_t irq_input_state;
566 void **irq_inputs;
e1833e1f
JM		 567 /* Exception vectors */
568 target_ulong excp_vectors[POWERPC_EXCP_NB];
569 target_ulong excp_prefix;
570 target_ulong ivor_mask;
571 target_ulong ivpr_mask;
d63001d1 572 target_ulong hreset_vector;
e9df014c 573#endif
3fc6c082
FB		 574
575 /* Those resources are used only during code translation */
576 /* Next instruction pointer */
577 target_ulong nip;
f2e63a42 578
3fc6c082
FB		 579 /* opcode handlers */
580 opc_handler_t *opcodes[0x40];
581
582 /* Those resources are used only in Qemu core */
583 jmp_buf jmp_env;
584 int user_mode_only; /* user mode only simulation */
4296f459 585 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
3fc6c082 586
9fddaa0c
FB		 587 /* Power management */
588 int power_mode;
a541f297 589
6d506e6d
FB		 590 /* temporary hack to handle OSI calls (only used if non NULL) */
591 int (*osi_call)(struct CPUPPCState *env);
3fc6c082 592};
79aceca5 593
76a66253
JM		 594/* Context used internally during MMU translations */
595typedef struct mmu_ctx_t mmu_ctx_t;
596struct mmu_ctx_t {
597 target_phys_addr_t raddr; /* Real address */
598 int prot; /* Protection bits */
599 target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
600 target_ulong ptem; /* Virtual segment ID | API */
601 int key; /* Access key */
602};
603
3fc6c082 604/*****************************************************************************/
36081602
JM		 605CPUPPCState *cpu_ppc_init (void);
606int cpu_ppc_exec (CPUPPCState *s);
607void cpu_ppc_close (CPUPPCState *s);
79aceca5
FB		 608/* you can call this signal handler from your SIGBUS and SIGSEGV
609 signal handlers to inform the virtual CPU of exceptions. non zero
610 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 611int cpu_ppc_signal_handler (int host_signum, void *pinfo,
612 void *puc);
79aceca5 613
a541f297 614void do_interrupt (CPUPPCState *env);
e9df014c 615void ppc_hw_interrupt (CPUPPCState *env);
36081602 616void cpu_loop_exit (void);
a541f297 617
9a64fbe4 618void dump_stack (CPUPPCState *env);
a541f297 619
76a66253 620#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 621target_ulong do_load_ibatu (CPUPPCState *env, int nr);
622target_ulong do_load_ibatl (CPUPPCState *env, int nr);
623void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
624void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
625target_ulong do_load_dbatu (CPUPPCState *env, int nr);
626target_ulong do_load_dbatl (CPUPPCState *env, int nr);
627void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
628void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
3fc6c082
FB		 629target_ulong do_load_sdr1 (CPUPPCState *env);
630void do_store_sdr1 (CPUPPCState *env, target_ulong value);
d9bce9d9
JM		 631#if defined(TARGET_PPC64)
632target_ulong ppc_load_asr (CPUPPCState *env);
633void ppc_store_asr (CPUPPCState *env, target_ulong value);
12de9a39
JM		 634target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
635void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs);
636#endif /* defined(TARGET_PPC64) */
637#if 0 // Unused
3fc6c082 638target_ulong do_load_sr (CPUPPCState *env, int srnum);
76a66253 639#endif
12de9a39
JM		 640void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
641#endif /* !defined(CONFIG_USER_ONLY) */
bfa1e5cf
JM		 642target_ulong ppc_load_xer (CPUPPCState *env);
643void ppc_store_xer (CPUPPCState *env, target_ulong value);
3fc6c082 644target_ulong do_load_msr (CPUPPCState *env);
a97fed52 645int do_store_msr (CPUPPCState *env, target_ulong value);
be147d08 646#if defined(TARGET_PPC64)
a97fed52 647int ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
be147d08 648#endif
3fc6c082
FB		 649
650void do_compute_hflags (CPUPPCState *env);
0a032cbe
JM		 651void cpu_ppc_reset (void *opaque);
652CPUPPCState *cpu_ppc_init (void);
653void cpu_ppc_close(CPUPPCState *env);
a541f297 654
3fc6c082
FB		 655int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
656int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
657void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
658int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
85c4adf6 659
9fddaa0c
FB		 660/* Time-base and decrementer management */
661#ifndef NO_CPU_IO_DEFS
662uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
663uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
664void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
665void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
a062e36c
JM		 666uint32_t cpu_ppc_load_atbl (CPUPPCState *env);
667uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
668void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
669void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
9fddaa0c
FB		 670uint32_t cpu_ppc_load_decr (CPUPPCState *env);
671void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 672#if defined(TARGET_PPC64H)
673uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
674void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
675uint64_t cpu_ppc_load_purr (CPUPPCState *env);
676void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
677#endif
d9bce9d9
JM		 678uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
679uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
680#if !defined(CONFIG_USER_ONLY)
681void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
682void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
683target_ulong load_40x_pit (CPUPPCState *env);
684void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 685void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 686void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 687void store_booke_tcr (CPUPPCState *env, target_ulong val);
688void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 689void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e
JM		 690void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
691#if defined(TARGET_PPC64)
692void ppc_slb_invalidate_all (CPUPPCState *env);
693void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
694#endif
36081602 695int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
d9bce9d9 696#endif
9fddaa0c 697#endif
79aceca5 698
2e719ba3
JM		 699/* Device control registers */
700int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
701int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
702
9467d44c
TS		 703#define CPUState CPUPPCState
704#define cpu_init cpu_ppc_init
705#define cpu_exec cpu_ppc_exec
706#define cpu_gen_code cpu_ppc_gen_code
707#define cpu_signal_handler cpu_ppc_signal_handler
708
79aceca5
FB		 709#include "cpu-all.h"
710
3fc6c082
FB		 711/*****************************************************************************/
712/* Registers definitions */
79aceca5
FB		 713#define XER_SO 31
714#define XER_OV 30
715#define XER_CA 29
3fc6c082 716#define XER_CMP 8
36081602 717#define XER_BC 0
3fc6c082
FB		 718#define xer_so env->xer[4]
719#define xer_ov env->xer[6]
720#define xer_ca env->xer[2]
721#define xer_cmp env->xer[1]
36081602 722#define xer_bc env->xer[0]
79aceca5 723
3fc6c082 724/* SPR definitions */
76a66253
JM		 725#define SPR_MQ (0x000)
726#define SPR_XER (0x001)
727#define SPR_601_VRTCU (0x004)
728#define SPR_601_VRTCL (0x005)
729#define SPR_601_UDECR (0x006)
730#define SPR_LR (0x008)
731#define SPR_CTR (0x009)
732#define SPR_DSISR (0x012)
a750fc0b 733#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
76a66253
JM		 734#define SPR_601_RTCU (0x014)
735#define SPR_601_RTCL (0x015)
736#define SPR_DECR (0x016)
737#define SPR_SDR1 (0x019)
738#define SPR_SRR0 (0x01A)
739#define SPR_SRR1 (0x01B)
2662a059 740#define SPR_AMR (0x01D)
76a66253
JM		 741#define SPR_BOOKE_PID (0x030)
742#define SPR_BOOKE_DECAR (0x036)
363be49c
JM		 743#define SPR_BOOKE_CSRR0 (0x03A)
744#define SPR_BOOKE_CSRR1 (0x03B)
76a66253
JM		 745#define SPR_BOOKE_DEAR (0x03D)
746#define SPR_BOOKE_ESR (0x03E)
363be49c 747#define SPR_BOOKE_IVPR (0x03F)
76a66253
JM		 748#define SPR_8xx_EIE (0x050)
749#define SPR_8xx_EID (0x051)
750#define SPR_8xx_NRE (0x052)
2662a059 751#define SPR_CTRL (0x088)
76a66253
JM		 752#define SPR_58x_CMPA (0x090)
753#define SPR_58x_CMPB (0x091)
754#define SPR_58x_CMPC (0x092)
755#define SPR_58x_CMPD (0x093)
756#define SPR_58x_ICR (0x094)
757#define SPR_58x_DER (0x094)
758#define SPR_58x_COUNTA (0x096)
759#define SPR_58x_COUNTB (0x097)
2662a059 760#define SPR_UCTRL (0x098)
76a66253
JM		 761#define SPR_58x_CMPE (0x098)
762#define SPR_58x_CMPF (0x099)
763#define SPR_58x_CMPG (0x09A)
764#define SPR_58x_CMPH (0x09B)
765#define SPR_58x_LCTRL1 (0x09C)
766#define SPR_58x_LCTRL2 (0x09D)
767#define SPR_58x_ICTRL (0x09E)
768#define SPR_58x_BAR (0x09F)
769#define SPR_VRSAVE (0x100)
770#define SPR_USPRG0 (0x100)
363be49c
JM		 771#define SPR_USPRG1 (0x101)
772#define SPR_USPRG2 (0x102)
773#define SPR_USPRG3 (0x103)
76a66253
JM		 774#define SPR_USPRG4 (0x104)
775#define SPR_USPRG5 (0x105)
776#define SPR_USPRG6 (0x106)
777#define SPR_USPRG7 (0x107)
778#define SPR_VTBL (0x10C)
779#define SPR_VTBU (0x10D)
780#define SPR_SPRG0 (0x110)
781#define SPR_SPRG1 (0x111)
782#define SPR_SPRG2 (0x112)
783#define SPR_SPRG3 (0x113)
784#define SPR_SPRG4 (0x114)
785#define SPR_SCOMC (0x114)
786#define SPR_SPRG5 (0x115)
787#define SPR_SCOMD (0x115)
788#define SPR_SPRG6 (0x116)
789#define SPR_SPRG7 (0x117)
790#define SPR_ASR (0x118)
791#define SPR_EAR (0x11A)
792#define SPR_TBL (0x11C)
793#define SPR_TBU (0x11D)
2662a059 794#define SPR_TBU40 (0x11E)
76a66253
JM		 795#define SPR_SVR (0x11E)
796#define SPR_BOOKE_PIR (0x11E)
797#define SPR_PVR (0x11F)
798#define SPR_HSPRG0 (0x130)
799#define SPR_BOOKE_DBSR (0x130)
800#define SPR_HSPRG1 (0x131)
2662a059
JM		 801#define SPR_HDSISR (0x132)
802#define SPR_HDAR (0x133)
76a66253
JM		 803#define SPR_BOOKE_DBCR0 (0x134)
804#define SPR_IBCR (0x135)
2662a059 805#define SPR_PURR (0x135)
76a66253
JM		 806#define SPR_BOOKE_DBCR1 (0x135)
807#define SPR_DBCR (0x136)
808#define SPR_HDEC (0x136)
809#define SPR_BOOKE_DBCR2 (0x136)
810#define SPR_HIOR (0x137)
811#define SPR_MBAR (0x137)
812#define SPR_RMOR (0x138)
813#define SPR_BOOKE_IAC1 (0x138)
814#define SPR_HRMOR (0x139)
815#define SPR_BOOKE_IAC2 (0x139)
e1833e1f 816#define SPR_HSRR0 (0x13A)
76a66253 817#define SPR_BOOKE_IAC3 (0x13A)
e1833e1f 818#define SPR_HSRR1 (0x13B)
76a66253
JM		 819#define SPR_BOOKE_IAC4 (0x13B)
820#define SPR_LPCR (0x13C)
821#define SPR_BOOKE_DAC1 (0x13C)
822#define SPR_LPIDR (0x13D)
823#define SPR_DABR2 (0x13D)
824#define SPR_BOOKE_DAC2 (0x13D)
825#define SPR_BOOKE_DVC1 (0x13E)
826#define SPR_BOOKE_DVC2 (0x13F)
827#define SPR_BOOKE_TSR (0x150)
828#define SPR_BOOKE_TCR (0x154)
829#define SPR_BOOKE_IVOR0 (0x190)
830#define SPR_BOOKE_IVOR1 (0x191)
831#define SPR_BOOKE_IVOR2 (0x192)
832#define SPR_BOOKE_IVOR3 (0x193)
833#define SPR_BOOKE_IVOR4 (0x194)
834#define SPR_BOOKE_IVOR5 (0x195)
835#define SPR_BOOKE_IVOR6 (0x196)
836#define SPR_BOOKE_IVOR7 (0x197)
837#define SPR_BOOKE_IVOR8 (0x198)
838#define SPR_BOOKE_IVOR9 (0x199)
839#define SPR_BOOKE_IVOR10 (0x19A)
840#define SPR_BOOKE_IVOR11 (0x19B)
841#define SPR_BOOKE_IVOR12 (0x19C)
842#define SPR_BOOKE_IVOR13 (0x19D)
843#define SPR_BOOKE_IVOR14 (0x19E)
844#define SPR_BOOKE_IVOR15 (0x19F)
2662a059 845#define SPR_BOOKE_SPEFSCR (0x200)
76a66253
JM		 846#define SPR_E500_BBEAR (0x201)
847#define SPR_E500_BBTAR (0x202)
a062e36c
JM		 848#define SPR_ATBL (0x20E)
849#define SPR_ATBU (0x20F)
76a66253 850#define SPR_IBAT0U (0x210)
363be49c 851#define SPR_BOOKE_IVOR32 (0x210)
76a66253 852#define SPR_IBAT0L (0x211)
363be49c 853#define SPR_BOOKE_IVOR33 (0x211)
76a66253 854#define SPR_IBAT1U (0x212)
363be49c 855#define SPR_BOOKE_IVOR34 (0x212)
76a66253 856#define SPR_IBAT1L (0x213)
363be49c 857#define SPR_BOOKE_IVOR35 (0x213)
76a66253 858#define SPR_IBAT2U (0x214)
363be49c 859#define SPR_BOOKE_IVOR36 (0x214)
76a66253
JM		 860#define SPR_IBAT2L (0x215)
861#define SPR_E500_L1CFG0 (0x215)
363be49c 862#define SPR_BOOKE_IVOR37 (0x215)
76a66253
JM		 863#define SPR_IBAT3U (0x216)
864#define SPR_E500_L1CFG1 (0x216)
865#define SPR_IBAT3L (0x217)
866#define SPR_DBAT0U (0x218)
867#define SPR_DBAT0L (0x219)
868#define SPR_DBAT1U (0x21A)
869#define SPR_DBAT1L (0x21B)
870#define SPR_DBAT2U (0x21C)
871#define SPR_DBAT2L (0x21D)
872#define SPR_DBAT3U (0x21E)
873#define SPR_DBAT3L (0x21F)
874#define SPR_IBAT4U (0x230)
875#define SPR_IBAT4L (0x231)
876#define SPR_IBAT5U (0x232)
877#define SPR_IBAT5L (0x233)
878#define SPR_IBAT6U (0x234)
879#define SPR_IBAT6L (0x235)
880#define SPR_IBAT7U (0x236)
881#define SPR_IBAT7L (0x237)
882#define SPR_DBAT4U (0x238)
883#define SPR_DBAT4L (0x239)
884#define SPR_DBAT5U (0x23A)
363be49c 885#define SPR_BOOKE_MCSRR0 (0x23A)
76a66253 886#define SPR_DBAT5L (0x23B)
363be49c 887#define SPR_BOOKE_MCSRR1 (0x23B)
76a66253 888#define SPR_DBAT6U (0x23C)
363be49c 889#define SPR_BOOKE_MCSR (0x23C)
76a66253
JM		 890#define SPR_DBAT6L (0x23D)
891#define SPR_E500_MCAR (0x23D)
892#define SPR_DBAT7U (0x23E)
363be49c 893#define SPR_BOOKE_DSRR0 (0x23E)
76a66253 894#define SPR_DBAT7L (0x23F)
363be49c
JM		 895#define SPR_BOOKE_DSRR1 (0x23F)
896#define SPR_BOOKE_SPRG8 (0x25C)
897#define SPR_BOOKE_SPRG9 (0x25D)
898#define SPR_BOOKE_MAS0 (0x270)
899#define SPR_BOOKE_MAS1 (0x271)
900#define SPR_BOOKE_MAS2 (0x272)
901#define SPR_BOOKE_MAS3 (0x273)
902#define SPR_BOOKE_MAS4 (0x274)
903#define SPR_BOOKE_MAS6 (0x276)
904#define SPR_BOOKE_PID1 (0x279)
905#define SPR_BOOKE_PID2 (0x27A)
906#define SPR_BOOKE_TLB0CFG (0x2B0)
907#define SPR_BOOKE_TLB1CFG (0x2B1)
908#define SPR_BOOKE_TLB2CFG (0x2B2)
909#define SPR_BOOKE_TLB3CFG (0x2B3)
910#define SPR_BOOKE_EPR (0x2BE)
2662a059
JM		 911#define SPR_PERF0 (0x300)
912#define SPR_PERF1 (0x301)
913#define SPR_PERF2 (0x302)
914#define SPR_PERF3 (0x303)
915#define SPR_PERF4 (0x304)
916#define SPR_PERF5 (0x305)
917#define SPR_PERF6 (0x306)
918#define SPR_PERF7 (0x307)
919#define SPR_PERF8 (0x308)
920#define SPR_PERF9 (0x309)
921#define SPR_PERFA (0x30A)
922#define SPR_PERFB (0x30B)
923#define SPR_PERFC (0x30C)
924#define SPR_PERFD (0x30D)
925#define SPR_PERFE (0x30E)
926#define SPR_PERFF (0x30F)
927#define SPR_UPERF0 (0x310)
928#define SPR_UPERF1 (0x311)
929#define SPR_UPERF2 (0x312)
930#define SPR_UPERF3 (0x313)
931#define SPR_UPERF4 (0x314)
932#define SPR_UPERF5 (0x315)
933#define SPR_UPERF6 (0x316)
934#define SPR_UPERF7 (0x317)
935#define SPR_UPERF8 (0x318)
936#define SPR_UPERF9 (0x319)
937#define SPR_UPERFA (0x31A)
938#define SPR_UPERFB (0x31B)
939#define SPR_UPERFC (0x31C)
940#define SPR_UPERFD (0x31D)
941#define SPR_UPERFE (0x31E)
942#define SPR_UPERFF (0x31F)
76a66253
JM		 943#define SPR_440_INV0 (0x370)
944#define SPR_440_INV1 (0x371)
945#define SPR_440_INV2 (0x372)
946#define SPR_440_INV3 (0x373)
2662a059
JM		 947#define SPR_440_ITV0 (0x374)
948#define SPR_440_ITV1 (0x375)
949#define SPR_440_ITV2 (0x376)
950#define SPR_440_ITV3 (0x377)
a750fc0b
JM		 951#define SPR_440_CCR1 (0x378)
952#define SPR_DCRIPR (0x37B)
2662a059 953#define SPR_PPR (0x380)
76a66253
JM		 954#define SPR_440_DNV0 (0x390)
955#define SPR_440_DNV1 (0x391)
956#define SPR_440_DNV2 (0x392)
957#define SPR_440_DNV3 (0x393)
2662a059
JM		 958#define SPR_440_DTV0 (0x394)
959#define SPR_440_DTV1 (0x395)
960#define SPR_440_DTV2 (0x396)
961#define SPR_440_DTV3 (0x397)
76a66253
JM		 962#define SPR_440_DVLIM (0x398)
963#define SPR_440_IVLIM (0x399)
964#define SPR_440_RSTCFG (0x39B)
2662a059
JM		 965#define SPR_BOOKE_DCDBTRL (0x39C)
966#define SPR_BOOKE_DCDBTRH (0x39D)
967#define SPR_BOOKE_ICDBTRL (0x39E)
968#define SPR_BOOKE_ICDBTRH (0x39F)
a750fc0b
JM		 969#define SPR_UMMCR2 (0x3A0)
970#define SPR_UPMC5 (0x3A1)
971#define SPR_UPMC6 (0x3A2)
972#define SPR_UBAMR (0x3A7)
76a66253
JM		 973#define SPR_UMMCR0 (0x3A8)
974#define SPR_UPMC1 (0x3A9)
975#define SPR_UPMC2 (0x3AA)
a750fc0b 976#define SPR_USIAR (0x3AB)
76a66253
JM		 977#define SPR_UMMCR1 (0x3AC)
978#define SPR_UPMC3 (0x3AD)
979#define SPR_UPMC4 (0x3AE)
980#define SPR_USDA (0x3AF)
981#define SPR_40x_ZPR (0x3B0)
363be49c 982#define SPR_BOOKE_MAS7 (0x3B0)
a750fc0b
JM		 983#define SPR_620_PMR0 (0x3B0)
984#define SPR_MMCR2 (0x3B0)
985#define SPR_PMC5 (0x3B1)
76a66253 986#define SPR_40x_PID (0x3B1)
a750fc0b
JM		 987#define SPR_620_PMR1 (0x3B1)
988#define SPR_PMC6 (0x3B2)
76a66253 989#define SPR_440_MMUCR (0x3B2)
a750fc0b 990#define SPR_620_PMR2 (0x3B2)
76a66253 991#define SPR_4xx_CCR0 (0x3B3)
363be49c 992#define SPR_BOOKE_EPLC (0x3B3)
a750fc0b 993#define SPR_620_PMR3 (0x3B3)
76a66253 994#define SPR_405_IAC3 (0x3B4)
363be49c 995#define SPR_BOOKE_EPSC (0x3B4)
a750fc0b 996#define SPR_620_PMR4 (0x3B4)
76a66253 997#define SPR_405_IAC4 (0x3B5)
a750fc0b 998#define SPR_620_PMR5 (0x3B5)
76a66253 999#define SPR_405_DVC1 (0x3B6)
a750fc0b 1000#define SPR_620_PMR6 (0x3B6)
76a66253 1001#define SPR_405_DVC2 (0x3B7)
a750fc0b
JM		 1002#define SPR_620_PMR7 (0x3B7)
1003#define SPR_BAMR (0x3B7)
76a66253 1004#define SPR_MMCR0 (0x3B8)
a750fc0b 1005#define SPR_620_PMR8 (0x3B8)
76a66253
JM		 1006#define SPR_PMC1 (0x3B9)
1007#define SPR_40x_SGR (0x3B9)
a750fc0b 1008#define SPR_620_PMR9 (0x3B9)
76a66253
JM		 1009#define SPR_PMC2 (0x3BA)
1010#define SPR_40x_DCWR (0x3BA)
a750fc0b
JM		 1011#define SPR_620_PMRA (0x3BA)
1012#define SPR_SIAR (0x3BB)
76a66253 1013#define SPR_405_SLER (0x3BB)
a750fc0b 1014#define SPR_620_PMRB (0x3BB)
76a66253
JM		 1015#define SPR_MMCR1 (0x3BC)
1016#define SPR_405_SU0R (0x3BC)
a750fc0b
JM		 1017#define SPR_620_PMRC (0x3BC)
1018#define SPR_401_SKR (0x3BC)
76a66253
JM		 1019#define SPR_PMC3 (0x3BD)
1020#define SPR_405_DBCR1 (0x3BD)
a750fc0b 1021#define SPR_620_PMRD (0x3BD)
76a66253 1022#define SPR_PMC4 (0x3BE)
a750fc0b 1023#define SPR_620_PMRE (0x3BE)
76a66253 1024#define SPR_SDA (0x3BF)
a750fc0b 1025#define SPR_620_PMRF (0x3BF)
76a66253
JM		 1026#define SPR_403_VTBL (0x3CC)
1027#define SPR_403_VTBU (0x3CD)
1028#define SPR_DMISS (0x3D0)
1029#define SPR_DCMP (0x3D1)
1030#define SPR_HASH1 (0x3D2)
1031#define SPR_HASH2 (0x3D3)
2662a059 1032#define SPR_BOOKE_ICDBDR (0x3D3)
a750fc0b 1033#define SPR_TLBMISS (0x3D4)
76a66253
JM		 1034#define SPR_IMISS (0x3D4)
1035#define SPR_40x_ESR (0x3D4)
a750fc0b 1036#define SPR_PTEHI (0x3D5)
76a66253
JM		 1037#define SPR_ICMP (0x3D5)
1038#define SPR_40x_DEAR (0x3D5)
a750fc0b 1039#define SPR_PTELO (0x3D6)
76a66253
JM		 1040#define SPR_RPA (0x3D6)
1041#define SPR_40x_EVPR (0x3D6)
a750fc0b 1042#define SPR_L3PM (0x3D7)
76a66253 1043#define SPR_403_CDBCR (0x3D7)
a750fc0b 1044#define SPR_L3OHCR (0x3D8)
76a66253
JM		 1045#define SPR_TCR (0x3D8)
1046#define SPR_40x_TSR (0x3D8)
1047#define SPR_IBR (0x3DA)
1048#define SPR_40x_TCR (0x3DA)
a750fc0b 1049#define SPR_ESASRR (0x3DB)
76a66253
JM		 1050#define SPR_40x_PIT (0x3DB)
1051#define SPR_403_TBL (0x3DC)
1052#define SPR_403_TBU (0x3DD)
1053#define SPR_SEBR (0x3DE)
1054#define SPR_40x_SRR2 (0x3DE)
1055#define SPR_SER (0x3DF)
1056#define SPR_40x_SRR3 (0x3DF)
a750fc0b
JM		 1057#define SPR_L3ITCR0 (0x3E8)
1058#define SPR_L3ITCR1 (0x3E9)
1059#define SPR_L3ITCR2 (0x3EA)
1060#define SPR_L3ITCR3 (0x3EB)
76a66253
JM		 1061#define SPR_HID0 (0x3F0)
1062#define SPR_40x_DBSR (0x3F0)
1063#define SPR_HID1 (0x3F1)
1064#define SPR_IABR (0x3F2)
1065#define SPR_40x_DBCR0 (0x3F2)
1066#define SPR_601_HID2 (0x3F2)
1067#define SPR_E500_L1CSR0 (0x3F2)
a750fc0b 1068#define SPR_ICTRL (0x3F3)
76a66253
JM		 1069#define SPR_HID2 (0x3F3)
1070#define SPR_E500_L1CSR1 (0x3F3)
1071#define SPR_440_DBDR (0x3F3)
a750fc0b 1072#define SPR_LDSTDB (0x3F4)
76a66253 1073#define SPR_40x_IAC1 (0x3F4)
65f9ee8d 1074#define SPR_MMUCSR0 (0x3F4)
76a66253 1075#define SPR_DABR (0x3F5)
3fc6c082 1076#define DABR_MASK (~(target_ulong)0x7)
76a66253
JM		 1077#define SPR_E500_BUCSR (0x3F5)
1078#define SPR_40x_IAC2 (0x3F5)
1079#define SPR_601_HID5 (0x3F5)
1080#define SPR_40x_DAC1 (0x3F6)
a750fc0b 1081#define SPR_MSSCR0 (0x3F6)
d63001d1 1082#define SPR_970_HID5 (0x3F6)
a750fc0b 1083#define SPR_MSSSR0 (0x3F7)
2662a059 1084#define SPR_DABRX (0x3F7)
76a66253 1085#define SPR_40x_DAC2 (0x3F7)
65f9ee8d 1086#define SPR_MMUCFG (0x3F7)
a750fc0b
JM		 1087#define SPR_LDSTCR (0x3F8)
1088#define SPR_L2PMCR (0x3F8)
76a66253 1089#define SPR_750_HID2 (0x3F8)
a750fc0b 1090#define SPR_620_HID8 (0x3F8)
76a66253 1091#define SPR_L2CR (0x3F9)
a750fc0b
JM		 1092#define SPR_620_HID9 (0x3F9)
1093#define SPR_L3CR (0x3FA)
76a66253
JM		 1094#define SPR_IABR2 (0x3FA)
1095#define SPR_40x_DCCR (0x3FA)
1096#define SPR_ICTC (0x3FB)
1097#define SPR_40x_ICCR (0x3FB)
1098#define SPR_THRM1 (0x3FC)
1099#define SPR_403_PBL1 (0x3FC)
1100#define SPR_SP (0x3FD)
1101#define SPR_THRM2 (0x3FD)
1102#define SPR_403_PBU1 (0x3FD)
a750fc0b 1103#define SPR_604_HID13 (0x3FD)
76a66253
JM		 1104#define SPR_LT (0x3FE)
1105#define SPR_THRM3 (0x3FE)
1106#define SPR_FPECR (0x3FE)
1107#define SPR_403_PBL2 (0x3FE)
1108#define SPR_PIR (0x3FF)
1109#define SPR_403_PBU2 (0x3FF)
1110#define SPR_601_HID15 (0x3FF)
a750fc0b 1111#define SPR_604_HID15 (0x3FF)
76a66253 1112#define SPR_E500_SVR (0x3FF)
79aceca5 1113
76a66253 1114/*****************************************************************************/
9a64fbe4
FB		 1115/* Memory access type :
1116 * may be needed for precise access rights control and precise exceptions.
1117 */
79aceca5 1118enum {
9a64fbe4
FB		 1119 /* 1 bit to define user level / supervisor access */
1120 ACCESS_USER = 0x00,
1121 ACCESS_SUPER = 0x01,
1122 /* Type of instruction that generated the access */
1123 ACCESS_CODE = 0x10, /* Code fetch access */
1124 ACCESS_INT = 0x20, /* Integer load/store access */
1125 ACCESS_FLOAT = 0x30, /* floating point load/store access */
1126 ACCESS_RES = 0x40, /* load/store with reservation */
1127 ACCESS_EXT = 0x50, /* external access */
1128 ACCESS_CACHE = 0x60, /* Cache manipulation */
1129};
1130
47103572
JM		 1131/* Hardware interruption sources:
1132 * all those exception can be raised simulteaneously
1133 */
e9df014c
JM		 1134/* Input pins definitions */
1135enum {
1136 /* 6xx bus input pins */
24be5ae3
JM		 1137 PPC6xx_INPUT_HRESET = 0,
1138 PPC6xx_INPUT_SRESET = 1,
1139 PPC6xx_INPUT_CKSTP_IN = 2,
1140 PPC6xx_INPUT_MCP = 3,
1141 PPC6xx_INPUT_SMI = 4,
1142 PPC6xx_INPUT_INT = 5,
1143};
1144
1145enum {
e9df014c 1146 /* Embedded PowerPC input pins */
24be5ae3
JM		 1147 PPCBookE_INPUT_HRESET = 0,
1148 PPCBookE_INPUT_SRESET = 1,
1149 PPCBookE_INPUT_CKSTP_IN = 2,
1150 PPCBookE_INPUT_MCP = 3,
1151 PPCBookE_INPUT_SMI = 4,
1152 PPCBookE_INPUT_INT = 5,
1153 PPCBookE_INPUT_CINT = 6,
1154};
1155
a750fc0b 1156enum {
4e290a0b
JM		 1157 /* PowerPC 40x input pins */
1158 PPC40x_INPUT_RESET_CORE = 0,
1159 PPC40x_INPUT_RESET_CHIP = 1,
1160 PPC40x_INPUT_RESET_SYS = 2,
1161 PPC40x_INPUT_CINT = 3,
1162 PPC40x_INPUT_INT = 4,
1163 PPC40x_INPUT_HALT = 5,
1164 PPC40x_INPUT_DEBUG = 6,
1165 PPC40x_INPUT_NB,
e9df014c
JM		 1166};
1167
00af685f 1168#if defined(TARGET_PPC64)
a750fc0b
JM		 1169enum {
1170 /* PowerPC 620 (and probably others) input pins */
1171 PPC620_INPUT_HRESET = 0,
1172 PPC620_INPUT_SRESET = 1,
1173 PPC620_INPUT_CKSTP = 2,
1174 PPC620_INPUT_TBEN = 3,
1175 PPC620_INPUT_WAKEUP = 4,
1176 PPC620_INPUT_MCP = 5,
1177 PPC620_INPUT_SMI = 6,
1178 PPC620_INPUT_INT = 7,
1179};
1180
d0dfae6e
JM		 1181enum {
1182 /* PowerPC 970 input pins */
1183 PPC970_INPUT_HRESET = 0,
1184 PPC970_INPUT_SRESET = 1,
1185 PPC970_INPUT_CKSTP = 2,
1186 PPC970_INPUT_TBEN = 3,
1187 PPC970_INPUT_MCP = 4,
1188 PPC970_INPUT_INT = 5,
1189 PPC970_INPUT_THINT = 6,
1190};
00af685f 1191#endif
d0dfae6e 1192
e9df014c 1193/* Hardware exceptions definitions */
47103572 1194enum {
e9df014c 1195 /* External hardware exception sources */
e1833e1f
JM		 1196 PPC_INTERRUPT_RESET = 0, /* Reset exception */
1197 PPC_INTERRUPT_MCK = 1, /* Machine check exception */
1198 PPC_INTERRUPT_EXT = 2, /* External interrupt */
1199 PPC_INTERRUPT_SMI = 3, /* System management interrupt */
1200 PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */
1201 PPC_INTERRUPT_DEBUG = 5, /* External debug exception */
1202 PPC_INTERRUPT_THERM = 6, /* Thermal exception */
e9df014c 1203 /* Internal hardware exception sources */
e1833e1f
JM		 1204 PPC_INTERRUPT_DECR = 7, /* Decrementer exception */
1205 PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */
1206 PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */
1207 PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */
1208 PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */
1209 PPC_INTERRUPT_CDOORBELL = 12, /* Critical doorbell interrupt */
1210 PPC_INTERRUPT_DOORBELL = 13, /* Doorbell interrupt */
1211 PPC_INTERRUPT_PERFM = 14, /* Performance monitor interrupt */
47103572
JM		 1212};
1213
9a64fbe4
FB		 1214/*****************************************************************************/
1215
79aceca5 1216#endif /* !defined (__CPU_PPC_H__) */
QEMU mirror