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ad71ed68 BS |
1 | /* |
2 | * PowerPC exception emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0d75590d | 19 | #include "qemu/osdep.h" |
ad71ed68 | 20 | #include "cpu.h" |
2ef6175a | 21 | #include "exec/helper-proto.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
f08b6170 | 23 | #include "exec/cpu_ldst.h" |
ad71ed68 BS |
24 | |
25 | #include "helper_regs.h" | |
26 | ||
27 | //#define DEBUG_OP | |
48880da6 | 28 | //#define DEBUG_SOFTWARE_TLB |
ad71ed68 BS |
29 | //#define DEBUG_EXCEPTIONS |
30 | ||
c79c73f6 BS |
31 | #ifdef DEBUG_EXCEPTIONS |
32 | # define LOG_EXCP(...) qemu_log(__VA_ARGS__) | |
33 | #else | |
34 | # define LOG_EXCP(...) do { } while (0) | |
35 | #endif | |
36 | ||
37 | /*****************************************************************************/ | |
38 | /* PowerPC Hypercall emulation */ | |
39 | ||
1b14670a | 40 | void (*cpu_ppc_hypercall)(PowerPCCPU *); |
c79c73f6 BS |
41 | |
42 | /*****************************************************************************/ | |
43 | /* Exception processing */ | |
44 | #if defined(CONFIG_USER_ONLY) | |
97a8ea5a | 45 | void ppc_cpu_do_interrupt(CPUState *cs) |
c79c73f6 | 46 | { |
97a8ea5a AF |
47 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
48 | CPUPPCState *env = &cpu->env; | |
49 | ||
27103424 | 50 | cs->exception_index = POWERPC_EXCP_NONE; |
c79c73f6 BS |
51 | env->error_code = 0; |
52 | } | |
53 | ||
458dd766 | 54 | static void ppc_hw_interrupt(CPUPPCState *env) |
c79c73f6 | 55 | { |
27103424 AF |
56 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
57 | ||
58 | cs->exception_index = POWERPC_EXCP_NONE; | |
c79c73f6 BS |
59 | env->error_code = 0; |
60 | } | |
61 | #else /* defined(CONFIG_USER_ONLY) */ | |
62 | static inline void dump_syscall(CPUPPCState *env) | |
63 | { | |
64 | qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64 | |
65 | " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64 | |
66 | " nip=" TARGET_FMT_lx "\n", | |
67 | ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), | |
68 | ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), | |
69 | ppc_dump_gpr(env, 6), env->nip); | |
70 | } | |
71 | ||
72 | /* Note that this function should be greatly optimized | |
73 | * when called with a constant excp, from ppc_hw_interrupt | |
74 | */ | |
5c26a5b3 | 75 | static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) |
c79c73f6 | 76 | { |
27103424 | 77 | CPUState *cs = CPU(cpu); |
5c26a5b3 | 78 | CPUPPCState *env = &cpu->env; |
c79c73f6 | 79 | target_ulong msr, new_msr, vector; |
6d49d6d4 BH |
80 | int srr0, srr1, asrr0, asrr1, lev, ail; |
81 | bool lpes0; | |
c79c73f6 BS |
82 | |
83 | qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx | |
84 | " => %08x (%02x)\n", env->nip, excp, env->error_code); | |
85 | ||
86 | /* new srr1 value excluding must-be-zero bits */ | |
a1bb7384 SW |
87 | if (excp_model == POWERPC_EXCP_BOOKE) { |
88 | msr = env->msr; | |
89 | } else { | |
90 | msr = env->msr & ~0x783f0000ULL; | |
91 | } | |
c79c73f6 | 92 | |
6d49d6d4 BH |
93 | /* new interrupt handler msr preserves existing HV and ME unless |
94 | * explicitly overriden | |
95 | */ | |
96 | new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); | |
c79c73f6 BS |
97 | |
98 | /* target registers */ | |
99 | srr0 = SPR_SRR0; | |
100 | srr1 = SPR_SRR1; | |
101 | asrr0 = -1; | |
102 | asrr1 = -1; | |
103 | ||
7778a575 BH |
104 | /* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */ |
105 | if (env->in_pm_state) { | |
106 | env->in_pm_state = false; | |
107 | ||
108 | /* Pretend to be returning from doze always as we don't lose state */ | |
109 | msr |= (0x1ull << (63 - 47)); | |
110 | ||
111 | /* Non-machine check are routed to 0x100 with a wakeup cause | |
112 | * encoded in SRR1 | |
113 | */ | |
114 | if (excp != POWERPC_EXCP_MCHECK) { | |
115 | switch (excp) { | |
116 | case POWERPC_EXCP_RESET: | |
117 | msr |= 0x4ull << (63 - 45); | |
118 | break; | |
119 | case POWERPC_EXCP_EXTERNAL: | |
120 | msr |= 0x8ull << (63 - 45); | |
121 | break; | |
122 | case POWERPC_EXCP_DECR: | |
123 | msr |= 0x6ull << (63 - 45); | |
124 | break; | |
125 | case POWERPC_EXCP_SDOOR: | |
126 | msr |= 0x5ull << (63 - 45); | |
127 | break; | |
128 | case POWERPC_EXCP_SDOOR_HV: | |
129 | msr |= 0x3ull << (63 - 45); | |
130 | break; | |
131 | case POWERPC_EXCP_HV_MAINT: | |
132 | msr |= 0xaull << (63 - 45); | |
133 | break; | |
134 | default: | |
135 | cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", | |
136 | excp); | |
137 | } | |
138 | excp = POWERPC_EXCP_RESET; | |
139 | } | |
140 | } | |
141 | ||
5c94b2a5 | 142 | /* Exception targetting modifiers |
6d49d6d4 BH |
143 | * |
144 | * LPES0 is supported on POWER7/8 | |
145 | * LPES1 is not supported (old iSeries mode) | |
146 | * | |
147 | * On anything else, we behave as if LPES0 is 1 | |
148 | * (externals don't alter MSR:HV) | |
5c94b2a5 CLG |
149 | * |
150 | * AIL is initialized here but can be cleared by | |
151 | * selected exceptions | |
152 | */ | |
153 | #if defined(TARGET_PPC64) | |
154 | if (excp_model == POWERPC_EXCP_POWER7 || | |
155 | excp_model == POWERPC_EXCP_POWER8) { | |
6d49d6d4 | 156 | lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); |
5c94b2a5 CLG |
157 | if (excp_model == POWERPC_EXCP_POWER8) { |
158 | ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; | |
159 | } else { | |
160 | ail = 0; | |
161 | } | |
162 | } else | |
163 | #endif /* defined(TARGET_PPC64) */ | |
164 | { | |
6d49d6d4 | 165 | lpes0 = true; |
5c94b2a5 CLG |
166 | ail = 0; |
167 | } | |
168 | ||
9b2fadda BH |
169 | /* Hypervisor emulation assistance interrupt only exists on server |
170 | * arch 2.05 server or later. We also don't want to generate it if | |
171 | * we don't have HVB in msr_mask (PAPR mode). | |
172 | */ | |
173 | if (excp == POWERPC_EXCP_HV_EMU | |
174 | #if defined(TARGET_PPC64) | |
175 | && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB)) | |
176 | #endif /* defined(TARGET_PPC64) */ | |
177 | ||
178 | ) { | |
179 | excp = POWERPC_EXCP_PROGRAM; | |
180 | } | |
181 | ||
c79c73f6 BS |
182 | switch (excp) { |
183 | case POWERPC_EXCP_NONE: | |
184 | /* Should never happen */ | |
185 | return; | |
186 | case POWERPC_EXCP_CRITICAL: /* Critical input */ | |
187 | switch (excp_model) { | |
188 | case POWERPC_EXCP_40x: | |
189 | srr0 = SPR_40x_SRR2; | |
190 | srr1 = SPR_40x_SRR3; | |
191 | break; | |
192 | case POWERPC_EXCP_BOOKE: | |
193 | srr0 = SPR_BOOKE_CSRR0; | |
194 | srr1 = SPR_BOOKE_CSRR1; | |
195 | break; | |
196 | case POWERPC_EXCP_G2: | |
197 | break; | |
198 | default: | |
199 | goto excp_invalid; | |
200 | } | |
201 | goto store_next; | |
202 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ | |
203 | if (msr_me == 0) { | |
204 | /* Machine check exception is not enabled. | |
205 | * Enter checkstop state. | |
206 | */ | |
013a2942 PB |
207 | fprintf(stderr, "Machine check while not allowed. " |
208 | "Entering checkstop state\n"); | |
209 | if (qemu_log_separate()) { | |
c79c73f6 BS |
210 | qemu_log("Machine check while not allowed. " |
211 | "Entering checkstop state\n"); | |
c79c73f6 | 212 | } |
259186a7 AF |
213 | cs->halted = 1; |
214 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
c79c73f6 | 215 | } |
6d49d6d4 | 216 | new_msr |= (target_ulong)MSR_HVB; |
5c94b2a5 | 217 | ail = 0; |
c79c73f6 BS |
218 | |
219 | /* machine check exceptions don't have ME set */ | |
220 | new_msr &= ~((target_ulong)1 << MSR_ME); | |
221 | ||
222 | /* XXX: should also have something loaded in DAR / DSISR */ | |
223 | switch (excp_model) { | |
224 | case POWERPC_EXCP_40x: | |
225 | srr0 = SPR_40x_SRR2; | |
226 | srr1 = SPR_40x_SRR3; | |
227 | break; | |
228 | case POWERPC_EXCP_BOOKE: | |
a1bb7384 | 229 | /* FIXME: choose one or the other based on CPU type */ |
c79c73f6 BS |
230 | srr0 = SPR_BOOKE_MCSRR0; |
231 | srr1 = SPR_BOOKE_MCSRR1; | |
232 | asrr0 = SPR_BOOKE_CSRR0; | |
233 | asrr1 = SPR_BOOKE_CSRR1; | |
234 | break; | |
235 | default: | |
236 | break; | |
237 | } | |
238 | goto store_next; | |
239 | case POWERPC_EXCP_DSI: /* Data storage exception */ | |
240 | LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx | |
241 | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]); | |
c79c73f6 BS |
242 | goto store_next; |
243 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ | |
244 | LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx | |
245 | "\n", msr, env->nip); | |
c79c73f6 BS |
246 | msr |= env->error_code; |
247 | goto store_next; | |
248 | case POWERPC_EXCP_EXTERNAL: /* External input */ | |
fdfba1a2 EI |
249 | cs = CPU(cpu); |
250 | ||
6d49d6d4 | 251 | if (!lpes0) { |
c79c73f6 | 252 | new_msr |= (target_ulong)MSR_HVB; |
6d49d6d4 BH |
253 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); |
254 | srr0 = SPR_HSRR0; | |
255 | srr1 = SPR_HSRR1; | |
c79c73f6 | 256 | } |
68c2dd70 AG |
257 | if (env->mpic_proxy) { |
258 | /* IACK the IRQ on delivery */ | |
fdfba1a2 | 259 | env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); |
68c2dd70 | 260 | } |
c79c73f6 BS |
261 | goto store_next; |
262 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ | |
c79c73f6 BS |
263 | /* XXX: this is false */ |
264 | /* Get rS/rD and rA from faulting opcode */ | |
2f5a189c BS |
265 | env->spr[SPR_DSISR] |= (cpu_ldl_code(env, (env->nip - 4)) |
266 | & 0x03FF0000) >> 16; | |
6bb9a0a9 | 267 | goto store_next; |
c79c73f6 BS |
268 | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
269 | switch (env->error_code & ~0xF) { | |
270 | case POWERPC_EXCP_FP: | |
271 | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { | |
272 | LOG_EXCP("Ignore floating point exception\n"); | |
27103424 | 273 | cs->exception_index = POWERPC_EXCP_NONE; |
c79c73f6 BS |
274 | env->error_code = 0; |
275 | return; | |
276 | } | |
c79c73f6 BS |
277 | msr |= 0x00100000; |
278 | if (msr_fe0 == msr_fe1) { | |
279 | goto store_next; | |
280 | } | |
281 | msr |= 0x00010000; | |
282 | break; | |
283 | case POWERPC_EXCP_INVAL: | |
284 | LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); | |
c79c73f6 BS |
285 | msr |= 0x00080000; |
286 | env->spr[SPR_BOOKE_ESR] = ESR_PIL; | |
287 | break; | |
288 | case POWERPC_EXCP_PRIV: | |
c79c73f6 BS |
289 | msr |= 0x00040000; |
290 | env->spr[SPR_BOOKE_ESR] = ESR_PPR; | |
291 | break; | |
292 | case POWERPC_EXCP_TRAP: | |
c79c73f6 BS |
293 | msr |= 0x00020000; |
294 | env->spr[SPR_BOOKE_ESR] = ESR_PTR; | |
295 | break; | |
296 | default: | |
297 | /* Should never occur */ | |
a47dddd7 | 298 | cpu_abort(cs, "Invalid program exception %d. Aborting\n", |
c79c73f6 BS |
299 | env->error_code); |
300 | break; | |
301 | } | |
302 | goto store_current; | |
9b2fadda BH |
303 | case POWERPC_EXCP_HV_EMU: |
304 | srr0 = SPR_HSRR0; | |
305 | srr1 = SPR_HSRR1; | |
306 | new_msr |= (target_ulong)MSR_HVB; | |
307 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); | |
308 | goto store_current; | |
c79c73f6 | 309 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
c79c73f6 BS |
310 | goto store_current; |
311 | case POWERPC_EXCP_SYSCALL: /* System call exception */ | |
312 | dump_syscall(env); | |
313 | lev = env->error_code; | |
6d49d6d4 BH |
314 | |
315 | /* "PAPR mode" built-in hypercall emulation */ | |
c79c73f6 | 316 | if ((lev == 1) && cpu_ppc_hypercall) { |
1b14670a | 317 | cpu_ppc_hypercall(cpu); |
c79c73f6 BS |
318 | return; |
319 | } | |
6d49d6d4 | 320 | if (lev == 1) { |
c79c73f6 BS |
321 | new_msr |= (target_ulong)MSR_HVB; |
322 | } | |
323 | goto store_next; | |
324 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ | |
325 | goto store_current; | |
326 | case POWERPC_EXCP_DECR: /* Decrementer exception */ | |
c79c73f6 BS |
327 | goto store_next; |
328 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ | |
329 | /* FIT on 4xx */ | |
330 | LOG_EXCP("FIT exception\n"); | |
331 | goto store_next; | |
332 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ | |
333 | LOG_EXCP("WDT exception\n"); | |
334 | switch (excp_model) { | |
335 | case POWERPC_EXCP_BOOKE: | |
336 | srr0 = SPR_BOOKE_CSRR0; | |
337 | srr1 = SPR_BOOKE_CSRR1; | |
338 | break; | |
339 | default: | |
340 | break; | |
341 | } | |
342 | goto store_next; | |
343 | case POWERPC_EXCP_DTLB: /* Data TLB error */ | |
344 | goto store_next; | |
345 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ | |
346 | goto store_next; | |
347 | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ | |
348 | switch (excp_model) { | |
349 | case POWERPC_EXCP_BOOKE: | |
a1bb7384 | 350 | /* FIXME: choose one or the other based on CPU type */ |
c79c73f6 BS |
351 | srr0 = SPR_BOOKE_DSRR0; |
352 | srr1 = SPR_BOOKE_DSRR1; | |
353 | asrr0 = SPR_BOOKE_CSRR0; | |
354 | asrr1 = SPR_BOOKE_CSRR1; | |
355 | break; | |
356 | default: | |
357 | break; | |
358 | } | |
359 | /* XXX: TODO */ | |
a47dddd7 | 360 | cpu_abort(cs, "Debug exception is not implemented yet !\n"); |
c79c73f6 BS |
361 | goto store_next; |
362 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ | |
363 | env->spr[SPR_BOOKE_ESR] = ESR_SPV; | |
364 | goto store_current; | |
365 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ | |
366 | /* XXX: TODO */ | |
a47dddd7 | 367 | cpu_abort(cs, "Embedded floating point data exception " |
c79c73f6 BS |
368 | "is not implemented yet !\n"); |
369 | env->spr[SPR_BOOKE_ESR] = ESR_SPV; | |
370 | goto store_next; | |
371 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ | |
372 | /* XXX: TODO */ | |
a47dddd7 | 373 | cpu_abort(cs, "Embedded floating point round exception " |
c79c73f6 BS |
374 | "is not implemented yet !\n"); |
375 | env->spr[SPR_BOOKE_ESR] = ESR_SPV; | |
376 | goto store_next; | |
377 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ | |
378 | /* XXX: TODO */ | |
a47dddd7 | 379 | cpu_abort(cs, |
c79c73f6 BS |
380 | "Performance counter exception is not implemented yet !\n"); |
381 | goto store_next; | |
382 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ | |
383 | goto store_next; | |
384 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ | |
385 | srr0 = SPR_BOOKE_CSRR0; | |
386 | srr1 = SPR_BOOKE_CSRR1; | |
387 | goto store_next; | |
388 | case POWERPC_EXCP_RESET: /* System reset exception */ | |
389 | if (msr_pow) { | |
390 | /* indicate that we resumed from power save mode */ | |
391 | msr |= 0x10000; | |
392 | } else { | |
393 | new_msr &= ~((target_ulong)1 << MSR_ME); | |
394 | } | |
395 | ||
6d49d6d4 | 396 | new_msr |= (target_ulong)MSR_HVB; |
5c94b2a5 | 397 | ail = 0; |
c79c73f6 BS |
398 | goto store_next; |
399 | case POWERPC_EXCP_DSEG: /* Data segment exception */ | |
c79c73f6 BS |
400 | goto store_next; |
401 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ | |
c79c73f6 BS |
402 | goto store_next; |
403 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ | |
404 | srr0 = SPR_HSRR0; | |
405 | srr1 = SPR_HSRR1; | |
406 | new_msr |= (target_ulong)MSR_HVB; | |
407 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); | |
408 | goto store_next; | |
409 | case POWERPC_EXCP_TRACE: /* Trace exception */ | |
c79c73f6 BS |
410 | goto store_next; |
411 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ | |
412 | srr0 = SPR_HSRR0; | |
413 | srr1 = SPR_HSRR1; | |
414 | new_msr |= (target_ulong)MSR_HVB; | |
415 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); | |
416 | goto store_next; | |
417 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ | |
418 | srr0 = SPR_HSRR0; | |
419 | srr1 = SPR_HSRR1; | |
420 | new_msr |= (target_ulong)MSR_HVB; | |
421 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); | |
422 | goto store_next; | |
423 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ | |
424 | srr0 = SPR_HSRR0; | |
425 | srr1 = SPR_HSRR1; | |
426 | new_msr |= (target_ulong)MSR_HVB; | |
427 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); | |
428 | goto store_next; | |
429 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ | |
430 | srr0 = SPR_HSRR0; | |
431 | srr1 = SPR_HSRR1; | |
432 | new_msr |= (target_ulong)MSR_HVB; | |
433 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); | |
434 | goto store_next; | |
435 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ | |
c79c73f6 | 436 | goto store_current; |
1f29871c | 437 | case POWERPC_EXCP_VSXU: /* VSX unavailable exception */ |
1f29871c | 438 | goto store_current; |
7019cb3d | 439 | case POWERPC_EXCP_FU: /* Facility unavailable exception */ |
7019cb3d | 440 | goto store_current; |
c79c73f6 BS |
441 | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
442 | LOG_EXCP("PIT exception\n"); | |
443 | goto store_next; | |
444 | case POWERPC_EXCP_IO: /* IO error exception */ | |
445 | /* XXX: TODO */ | |
a47dddd7 | 446 | cpu_abort(cs, "601 IO error exception is not implemented yet !\n"); |
c79c73f6 BS |
447 | goto store_next; |
448 | case POWERPC_EXCP_RUNM: /* Run mode exception */ | |
449 | /* XXX: TODO */ | |
a47dddd7 | 450 | cpu_abort(cs, "601 run mode exception is not implemented yet !\n"); |
c79c73f6 BS |
451 | goto store_next; |
452 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ | |
453 | /* XXX: TODO */ | |
a47dddd7 | 454 | cpu_abort(cs, "602 emulation trap exception " |
c79c73f6 BS |
455 | "is not implemented yet !\n"); |
456 | goto store_next; | |
457 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ | |
c79c73f6 BS |
458 | switch (excp_model) { |
459 | case POWERPC_EXCP_602: | |
460 | case POWERPC_EXCP_603: | |
461 | case POWERPC_EXCP_603E: | |
462 | case POWERPC_EXCP_G2: | |
463 | goto tlb_miss_tgpr; | |
464 | case POWERPC_EXCP_7x5: | |
465 | goto tlb_miss; | |
466 | case POWERPC_EXCP_74xx: | |
467 | goto tlb_miss_74xx; | |
468 | default: | |
a47dddd7 | 469 | cpu_abort(cs, "Invalid instruction TLB miss exception\n"); |
c79c73f6 BS |
470 | break; |
471 | } | |
472 | break; | |
473 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
c79c73f6 BS |
474 | switch (excp_model) { |
475 | case POWERPC_EXCP_602: | |
476 | case POWERPC_EXCP_603: | |
477 | case POWERPC_EXCP_603E: | |
478 | case POWERPC_EXCP_G2: | |
479 | goto tlb_miss_tgpr; | |
480 | case POWERPC_EXCP_7x5: | |
481 | goto tlb_miss; | |
482 | case POWERPC_EXCP_74xx: | |
483 | goto tlb_miss_74xx; | |
484 | default: | |
a47dddd7 | 485 | cpu_abort(cs, "Invalid data load TLB miss exception\n"); |
c79c73f6 BS |
486 | break; |
487 | } | |
488 | break; | |
489 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
c79c73f6 BS |
490 | switch (excp_model) { |
491 | case POWERPC_EXCP_602: | |
492 | case POWERPC_EXCP_603: | |
493 | case POWERPC_EXCP_603E: | |
494 | case POWERPC_EXCP_G2: | |
495 | tlb_miss_tgpr: | |
496 | /* Swap temporary saved registers with GPRs */ | |
497 | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { | |
498 | new_msr |= (target_ulong)1 << MSR_TGPR; | |
499 | hreg_swap_gpr_tgpr(env); | |
500 | } | |
501 | goto tlb_miss; | |
502 | case POWERPC_EXCP_7x5: | |
503 | tlb_miss: | |
504 | #if defined(DEBUG_SOFTWARE_TLB) | |
505 | if (qemu_log_enabled()) { | |
506 | const char *es; | |
507 | target_ulong *miss, *cmp; | |
508 | int en; | |
509 | ||
510 | if (excp == POWERPC_EXCP_IFTLB) { | |
511 | es = "I"; | |
512 | en = 'I'; | |
513 | miss = &env->spr[SPR_IMISS]; | |
514 | cmp = &env->spr[SPR_ICMP]; | |
515 | } else { | |
516 | if (excp == POWERPC_EXCP_DLTLB) { | |
517 | es = "DL"; | |
518 | } else { | |
519 | es = "DS"; | |
520 | } | |
521 | en = 'D'; | |
522 | miss = &env->spr[SPR_DMISS]; | |
523 | cmp = &env->spr[SPR_DCMP]; | |
524 | } | |
525 | qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " | |
526 | TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " | |
527 | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, | |
528 | env->spr[SPR_HASH1], env->spr[SPR_HASH2], | |
529 | env->error_code); | |
530 | } | |
531 | #endif | |
532 | msr |= env->crf[0] << 28; | |
533 | msr |= env->error_code; /* key, D/I, S/L bits */ | |
534 | /* Set way using a LRU mechanism */ | |
535 | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; | |
536 | break; | |
537 | case POWERPC_EXCP_74xx: | |
538 | tlb_miss_74xx: | |
539 | #if defined(DEBUG_SOFTWARE_TLB) | |
540 | if (qemu_log_enabled()) { | |
541 | const char *es; | |
542 | target_ulong *miss, *cmp; | |
543 | int en; | |
544 | ||
545 | if (excp == POWERPC_EXCP_IFTLB) { | |
546 | es = "I"; | |
547 | en = 'I'; | |
548 | miss = &env->spr[SPR_TLBMISS]; | |
549 | cmp = &env->spr[SPR_PTEHI]; | |
550 | } else { | |
551 | if (excp == POWERPC_EXCP_DLTLB) { | |
552 | es = "DL"; | |
553 | } else { | |
554 | es = "DS"; | |
555 | } | |
556 | en = 'D'; | |
557 | miss = &env->spr[SPR_TLBMISS]; | |
558 | cmp = &env->spr[SPR_PTEHI]; | |
559 | } | |
560 | qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " | |
561 | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, | |
562 | env->error_code); | |
563 | } | |
564 | #endif | |
565 | msr |= env->error_code; /* key bit */ | |
566 | break; | |
567 | default: | |
a47dddd7 | 568 | cpu_abort(cs, "Invalid data store TLB miss exception\n"); |
c79c73f6 BS |
569 | break; |
570 | } | |
571 | goto store_next; | |
572 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ | |
573 | /* XXX: TODO */ | |
a47dddd7 | 574 | cpu_abort(cs, "Floating point assist exception " |
c79c73f6 BS |
575 | "is not implemented yet !\n"); |
576 | goto store_next; | |
577 | case POWERPC_EXCP_DABR: /* Data address breakpoint */ | |
578 | /* XXX: TODO */ | |
a47dddd7 | 579 | cpu_abort(cs, "DABR exception is not implemented yet !\n"); |
c79c73f6 BS |
580 | goto store_next; |
581 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ | |
582 | /* XXX: TODO */ | |
a47dddd7 | 583 | cpu_abort(cs, "IABR exception is not implemented yet !\n"); |
c79c73f6 BS |
584 | goto store_next; |
585 | case POWERPC_EXCP_SMI: /* System management interrupt */ | |
586 | /* XXX: TODO */ | |
a47dddd7 | 587 | cpu_abort(cs, "SMI exception is not implemented yet !\n"); |
c79c73f6 BS |
588 | goto store_next; |
589 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ | |
590 | /* XXX: TODO */ | |
a47dddd7 | 591 | cpu_abort(cs, "Thermal management exception " |
c79c73f6 BS |
592 | "is not implemented yet !\n"); |
593 | goto store_next; | |
594 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ | |
c79c73f6 | 595 | /* XXX: TODO */ |
a47dddd7 | 596 | cpu_abort(cs, |
c79c73f6 BS |
597 | "Performance counter exception is not implemented yet !\n"); |
598 | goto store_next; | |
599 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ | |
600 | /* XXX: TODO */ | |
a47dddd7 | 601 | cpu_abort(cs, "VPU assist exception is not implemented yet !\n"); |
c79c73f6 BS |
602 | goto store_next; |
603 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ | |
604 | /* XXX: TODO */ | |
a47dddd7 | 605 | cpu_abort(cs, |
c79c73f6 BS |
606 | "970 soft-patch exception is not implemented yet !\n"); |
607 | goto store_next; | |
608 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ | |
609 | /* XXX: TODO */ | |
a47dddd7 | 610 | cpu_abort(cs, |
c79c73f6 BS |
611 | "970 maintenance exception is not implemented yet !\n"); |
612 | goto store_next; | |
613 | case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ | |
614 | /* XXX: TODO */ | |
a47dddd7 | 615 | cpu_abort(cs, "Maskable external exception " |
c79c73f6 BS |
616 | "is not implemented yet !\n"); |
617 | goto store_next; | |
618 | case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ | |
619 | /* XXX: TODO */ | |
a47dddd7 | 620 | cpu_abort(cs, "Non maskable external exception " |
c79c73f6 BS |
621 | "is not implemented yet !\n"); |
622 | goto store_next; | |
623 | default: | |
624 | excp_invalid: | |
a47dddd7 | 625 | cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); |
c79c73f6 BS |
626 | break; |
627 | store_current: | |
628 | /* save current instruction location */ | |
629 | env->spr[srr0] = env->nip - 4; | |
630 | break; | |
631 | store_next: | |
632 | /* save next instruction location */ | |
633 | env->spr[srr0] = env->nip; | |
634 | break; | |
635 | } | |
636 | /* Save MSR */ | |
637 | env->spr[srr1] = msr; | |
6d49d6d4 BH |
638 | |
639 | /* Sanity check */ | |
640 | if (!(env->msr_mask & MSR_HVB) && (srr0 == SPR_HSRR0)) { | |
641 | cpu_abort(cs, "Trying to deliver HV exception %d with " | |
642 | "no HV support\n", excp); | |
643 | } | |
644 | ||
c79c73f6 BS |
645 | /* If any alternate SRR register are defined, duplicate saved values */ |
646 | if (asrr0 != -1) { | |
647 | env->spr[asrr0] = env->spr[srr0]; | |
648 | } | |
649 | if (asrr1 != -1) { | |
650 | env->spr[asrr1] = env->spr[srr1]; | |
651 | } | |
d5ac4f54 | 652 | |
6d49d6d4 BH |
653 | /* Sort out endianness of interrupt, this differs depending on the |
654 | * CPU, the HV mode, etc... | |
655 | */ | |
1e0c7e55 | 656 | #ifdef TARGET_PPC64 |
6d49d6d4 BH |
657 | if (excp_model == POWERPC_EXCP_POWER7) { |
658 | if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) { | |
659 | new_msr |= (target_ulong)1 << MSR_LE; | |
660 | } | |
661 | } else if (excp_model == POWERPC_EXCP_POWER8) { | |
662 | if (new_msr & MSR_HVB) { | |
663 | if (env->spr[SPR_HID0] & HID0_HILE) { | |
664 | new_msr |= (target_ulong)1 << MSR_LE; | |
665 | } | |
666 | } else if (env->spr[SPR_LPCR] & LPCR_ILE) { | |
1e0c7e55 AB |
667 | new_msr |= (target_ulong)1 << MSR_LE; |
668 | } | |
669 | } else if (msr_ile) { | |
670 | new_msr |= (target_ulong)1 << MSR_LE; | |
671 | } | |
672 | #else | |
c79c73f6 BS |
673 | if (msr_ile) { |
674 | new_msr |= (target_ulong)1 << MSR_LE; | |
675 | } | |
1e0c7e55 | 676 | #endif |
c79c73f6 BS |
677 | |
678 | /* Jump to handler */ | |
679 | vector = env->excp_vectors[excp]; | |
680 | if (vector == (target_ulong)-1ULL) { | |
a47dddd7 | 681 | cpu_abort(cs, "Raised an exception without defined vector %d\n", |
c79c73f6 BS |
682 | excp); |
683 | } | |
684 | vector |= env->excp_prefix; | |
5c94b2a5 CLG |
685 | |
686 | /* AIL only works if there is no HV transition and we are running with | |
687 | * translations enabled | |
688 | */ | |
6d49d6d4 BH |
689 | if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) || |
690 | ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) { | |
5c94b2a5 CLG |
691 | ail = 0; |
692 | } | |
693 | /* Handle AIL */ | |
694 | if (ail) { | |
695 | new_msr |= (1 << MSR_IR) | (1 << MSR_DR); | |
696 | switch(ail) { | |
697 | case AIL_0001_8000: | |
698 | vector |= 0x18000; | |
699 | break; | |
700 | case AIL_C000_0000_0000_4000: | |
701 | vector |= 0xc000000000004000ull; | |
702 | break; | |
703 | default: | |
704 | cpu_abort(cs, "Invalid AIL combination %d\n", ail); | |
705 | break; | |
706 | } | |
707 | } | |
708 | ||
c79c73f6 BS |
709 | #if defined(TARGET_PPC64) |
710 | if (excp_model == POWERPC_EXCP_BOOKE) { | |
e42a61f1 AG |
711 | if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { |
712 | /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ | |
c79c73f6 | 713 | new_msr |= (target_ulong)1 << MSR_CM; |
e42a61f1 AG |
714 | } else { |
715 | vector = (uint32_t)vector; | |
c79c73f6 BS |
716 | } |
717 | } else { | |
718 | if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { | |
719 | vector = (uint32_t)vector; | |
720 | } else { | |
721 | new_msr |= (target_ulong)1 << MSR_SF; | |
722 | } | |
723 | } | |
724 | #endif | |
1c953ba5 BH |
725 | /* We don't use hreg_store_msr here as already have treated |
726 | * any special case that could occur. Just store MSR and update hflags | |
727 | * | |
728 | * Note: We *MUST* not use hreg_store_msr() as-is anyway because it | |
729 | * will prevent setting of the HV bit which some exceptions might need | |
730 | * to do. | |
c79c73f6 BS |
731 | */ |
732 | env->msr = new_msr & env->msr_mask; | |
733 | hreg_compute_hflags(env); | |
734 | env->nip = vector; | |
735 | /* Reset exception state */ | |
27103424 | 736 | cs->exception_index = POWERPC_EXCP_NONE; |
c79c73f6 | 737 | env->error_code = 0; |
cd0c6f47 BH |
738 | |
739 | /* Any interrupt is context synchronizing, check if TCG TLB | |
740 | * needs a delayed flush on ppc64 | |
741 | */ | |
742 | check_tlb_flush(env); | |
c79c73f6 BS |
743 | } |
744 | ||
97a8ea5a | 745 | void ppc_cpu_do_interrupt(CPUState *cs) |
c79c73f6 | 746 | { |
97a8ea5a AF |
747 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
748 | CPUPPCState *env = &cpu->env; | |
5c26a5b3 | 749 | |
27103424 | 750 | powerpc_excp(cpu, env->excp_model, cs->exception_index); |
c79c73f6 BS |
751 | } |
752 | ||
458dd766 | 753 | static void ppc_hw_interrupt(CPUPPCState *env) |
c79c73f6 | 754 | { |
5c26a5b3 | 755 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
c79c73f6 | 756 | int hdice; |
c79c73f6 | 757 | #if 0 |
259186a7 AF |
758 | CPUState *cs = CPU(cpu); |
759 | ||
c79c73f6 | 760 | qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n", |
259186a7 AF |
761 | __func__, env, env->pending_interrupts, |
762 | cs->interrupt_request, (int)msr_me, (int)msr_ee); | |
c79c73f6 BS |
763 | #endif |
764 | /* External reset */ | |
765 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { | |
766 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); | |
5c26a5b3 | 767 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); |
c79c73f6 BS |
768 | return; |
769 | } | |
770 | /* Machine check exception */ | |
771 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { | |
772 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); | |
5c26a5b3 | 773 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK); |
c79c73f6 BS |
774 | return; |
775 | } | |
776 | #if 0 /* TODO */ | |
777 | /* External debug exception */ | |
778 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { | |
779 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); | |
5c26a5b3 | 780 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG); |
c79c73f6 BS |
781 | return; |
782 | } | |
783 | #endif | |
784 | if (0) { | |
785 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
786 | hdice = env->spr[SPR_LPCR] & 1; | |
787 | } else { | |
788 | hdice = 0; | |
789 | } | |
790 | if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { | |
791 | /* Hypervisor decrementer exception */ | |
792 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { | |
5c26a5b3 | 793 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR); |
c79c73f6 BS |
794 | return; |
795 | } | |
796 | } | |
797 | if (msr_ce != 0) { | |
798 | /* External critical interrupt */ | |
799 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { | |
800 | /* Taking a critical external interrupt does not clear the external | |
801 | * critical interrupt status | |
802 | */ | |
803 | #if 0 | |
804 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT); | |
805 | #endif | |
5c26a5b3 | 806 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL); |
c79c73f6 BS |
807 | return; |
808 | } | |
809 | } | |
810 | if (msr_ee != 0) { | |
811 | /* Watchdog timer on embedded PowerPC */ | |
812 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { | |
813 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); | |
5c26a5b3 | 814 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT); |
c79c73f6 BS |
815 | return; |
816 | } | |
817 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { | |
818 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL); | |
5c26a5b3 | 819 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI); |
c79c73f6 BS |
820 | return; |
821 | } | |
822 | /* Fixed interval timer on embedded PowerPC */ | |
823 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { | |
824 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); | |
5c26a5b3 | 825 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT); |
c79c73f6 BS |
826 | return; |
827 | } | |
828 | /* Programmable interval timer on embedded PowerPC */ | |
829 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { | |
830 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); | |
5c26a5b3 | 831 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT); |
c79c73f6 BS |
832 | return; |
833 | } | |
834 | /* Decrementer exception */ | |
835 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { | |
e81a982a AG |
836 | if (ppc_decr_clear_on_delivery(env)) { |
837 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); | |
838 | } | |
5c26a5b3 | 839 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR); |
c79c73f6 BS |
840 | return; |
841 | } | |
842 | /* External interrupt */ | |
843 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { | |
844 | /* Taking an external interrupt does not clear the external | |
845 | * interrupt status | |
846 | */ | |
847 | #if 0 | |
848 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT); | |
849 | #endif | |
5c26a5b3 | 850 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL); |
c79c73f6 BS |
851 | return; |
852 | } | |
853 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { | |
854 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); | |
5c26a5b3 | 855 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI); |
c79c73f6 BS |
856 | return; |
857 | } | |
858 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { | |
859 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM); | |
5c26a5b3 | 860 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM); |
c79c73f6 BS |
861 | return; |
862 | } | |
863 | /* Thermal interrupt */ | |
864 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { | |
865 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM); | |
5c26a5b3 | 866 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM); |
c79c73f6 BS |
867 | return; |
868 | } | |
869 | } | |
870 | } | |
34316482 AK |
871 | |
872 | void ppc_cpu_do_system_reset(CPUState *cs) | |
873 | { | |
874 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
875 | CPUPPCState *env = &cpu->env; | |
876 | ||
877 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); | |
878 | } | |
c79c73f6 BS |
879 | #endif /* !CONFIG_USER_ONLY */ |
880 | ||
458dd766 RH |
881 | bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
882 | { | |
883 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
884 | CPUPPCState *env = &cpu->env; | |
885 | ||
886 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
887 | ppc_hw_interrupt(env); | |
888 | if (env->pending_interrupts == 0) { | |
889 | cs->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
890 | } | |
891 | return true; | |
892 | } | |
893 | return false; | |
894 | } | |
895 | ||
c79c73f6 BS |
896 | #if defined(DEBUG_OP) |
897 | static void cpu_dump_rfi(target_ulong RA, target_ulong msr) | |
898 | { | |
899 | qemu_log("Return from exception at " TARGET_FMT_lx " with flags " | |
900 | TARGET_FMT_lx "\n", RA, msr); | |
901 | } | |
902 | #endif | |
903 | ||
ad71ed68 BS |
904 | /*****************************************************************************/ |
905 | /* Exceptions processing helpers */ | |
906 | ||
e5f17ac6 BS |
907 | void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, |
908 | uint32_t error_code) | |
ad71ed68 | 909 | { |
27103424 AF |
910 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
911 | ||
ad71ed68 BS |
912 | #if 0 |
913 | printf("Raise exception %3x code : %d\n", exception, error_code); | |
914 | #endif | |
27103424 | 915 | cs->exception_index = exception; |
ad71ed68 | 916 | env->error_code = error_code; |
5638d180 | 917 | cpu_loop_exit(cs); |
ad71ed68 BS |
918 | } |
919 | ||
e5f17ac6 | 920 | void helper_raise_exception(CPUPPCState *env, uint32_t exception) |
ad71ed68 | 921 | { |
e5f17ac6 | 922 | helper_raise_exception_err(env, exception, 0); |
ad71ed68 BS |
923 | } |
924 | ||
925 | #if !defined(CONFIG_USER_ONLY) | |
e5f17ac6 | 926 | void helper_store_msr(CPUPPCState *env, target_ulong val) |
ad71ed68 | 927 | { |
259186a7 AF |
928 | CPUState *cs; |
929 | ||
ad71ed68 BS |
930 | val = hreg_store_msr(env, val, 0); |
931 | if (val != 0) { | |
259186a7 AF |
932 | cs = CPU(ppc_env_get_cpu(env)); |
933 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
e5f17ac6 | 934 | helper_raise_exception(env, val); |
ad71ed68 BS |
935 | } |
936 | } | |
937 | ||
7778a575 BH |
938 | #if defined(TARGET_PPC64) |
939 | void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) | |
940 | { | |
941 | CPUState *cs; | |
942 | ||
943 | cs = CPU(ppc_env_get_cpu(env)); | |
944 | cs->halted = 1; | |
945 | env->in_pm_state = true; | |
946 | ||
947 | /* Technically, nap doesn't set EE, but if we don't set it | |
948 | * then ppc_hw_interrupt() won't deliver. We could add some | |
949 | * other tests there based on LPCR but it's simpler to just | |
950 | * whack EE in. It will be cleared by the 0x100 at wakeup | |
951 | * anyway. It will still be observable by the guest in SRR1 | |
952 | * but this doesn't seem to be a problem. | |
953 | */ | |
954 | env->msr |= (1ull << MSR_EE); | |
955 | helper_raise_exception(env, EXCP_HLT); | |
956 | } | |
957 | #endif /* defined(TARGET_PPC64) */ | |
958 | ||
a2e71b28 | 959 | static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) |
ad71ed68 | 960 | { |
259186a7 AF |
961 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
962 | ||
a2e71b28 BH |
963 | /* MSR:POW cannot be set by any form of rfi */ |
964 | msr &= ~(1ULL << MSR_POW); | |
965 | ||
ad71ed68 | 966 | #if defined(TARGET_PPC64) |
a2e71b28 BH |
967 | /* Switching to 32-bit ? Crop the nip */ |
968 | if (!msr_is_64bit(env, msr)) { | |
ad71ed68 | 969 | nip = (uint32_t)nip; |
ad71ed68 BS |
970 | } |
971 | #else | |
972 | nip = (uint32_t)nip; | |
ad71ed68 BS |
973 | #endif |
974 | /* XXX: beware: this is false if VLE is supported */ | |
975 | env->nip = nip & ~((target_ulong)0x00000003); | |
976 | hreg_store_msr(env, msr, 1); | |
977 | #if defined(DEBUG_OP) | |
978 | cpu_dump_rfi(env->nip, env->msr); | |
979 | #endif | |
980 | /* No need to raise an exception here, | |
981 | * as rfi is always the last insn of a TB | |
982 | */ | |
259186a7 | 983 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; |
cd0c6f47 BH |
984 | |
985 | /* Context synchronizing: check if TCG TLB needs flush */ | |
986 | check_tlb_flush(env); | |
ad71ed68 BS |
987 | } |
988 | ||
e5f17ac6 | 989 | void helper_rfi(CPUPPCState *env) |
ad71ed68 | 990 | { |
a2e71b28 | 991 | do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); |
ad71ed68 BS |
992 | } |
993 | ||
a2e71b28 | 994 | #define MSR_BOOK3S_MASK |
ad71ed68 | 995 | #if defined(TARGET_PPC64) |
e5f17ac6 | 996 | void helper_rfid(CPUPPCState *env) |
ad71ed68 | 997 | { |
a2e71b28 BH |
998 | /* The architeture defines a number of rules for which bits |
999 | * can change but in practice, we handle this in hreg_store_msr() | |
1000 | * which will be called by do_rfi(), so there is no need to filter | |
1001 | * here | |
1002 | */ | |
1003 | do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); | |
ad71ed68 BS |
1004 | } |
1005 | ||
e5f17ac6 | 1006 | void helper_hrfid(CPUPPCState *env) |
ad71ed68 | 1007 | { |
a2e71b28 | 1008 | do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); |
ad71ed68 BS |
1009 | } |
1010 | #endif | |
1011 | ||
1012 | /*****************************************************************************/ | |
1013 | /* Embedded PowerPC specific helpers */ | |
e5f17ac6 | 1014 | void helper_40x_rfci(CPUPPCState *env) |
ad71ed68 | 1015 | { |
a2e71b28 | 1016 | do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]); |
ad71ed68 BS |
1017 | } |
1018 | ||
e5f17ac6 | 1019 | void helper_rfci(CPUPPCState *env) |
ad71ed68 | 1020 | { |
a2e71b28 | 1021 | do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]); |
ad71ed68 BS |
1022 | } |
1023 | ||
e5f17ac6 | 1024 | void helper_rfdi(CPUPPCState *env) |
ad71ed68 | 1025 | { |
a1bb7384 | 1026 | /* FIXME: choose CSRR1 or DSRR1 based on cpu type */ |
a2e71b28 | 1027 | do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]); |
ad71ed68 BS |
1028 | } |
1029 | ||
e5f17ac6 | 1030 | void helper_rfmci(CPUPPCState *env) |
ad71ed68 | 1031 | { |
a1bb7384 | 1032 | /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */ |
a2e71b28 | 1033 | do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); |
ad71ed68 BS |
1034 | } |
1035 | #endif | |
1036 | ||
e5f17ac6 BS |
1037 | void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, |
1038 | uint32_t flags) | |
ad71ed68 BS |
1039 | { |
1040 | if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) || | |
1041 | ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) || | |
1042 | ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || | |
1043 | ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || | |
1044 | ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { | |
e5f17ac6 BS |
1045 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
1046 | POWERPC_EXCP_TRAP); | |
ad71ed68 BS |
1047 | } |
1048 | } | |
1049 | ||
1050 | #if defined(TARGET_PPC64) | |
e5f17ac6 BS |
1051 | void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, |
1052 | uint32_t flags) | |
ad71ed68 BS |
1053 | { |
1054 | if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) || | |
1055 | ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) || | |
1056 | ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || | |
1057 | ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || | |
1058 | ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { | |
e5f17ac6 BS |
1059 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
1060 | POWERPC_EXCP_TRAP); | |
ad71ed68 BS |
1061 | } |
1062 | } | |
1063 | #endif | |
1064 | ||
1065 | #if !defined(CONFIG_USER_ONLY) | |
1066 | /*****************************************************************************/ | |
1067 | /* PowerPC 601 specific instructions (POWER bridge) */ | |
1068 | ||
e5f17ac6 | 1069 | void helper_rfsvc(CPUPPCState *env) |
ad71ed68 | 1070 | { |
a2e71b28 | 1071 | do_rfi(env, env->lr, env->ctr & 0x0000FFFF); |
ad71ed68 BS |
1072 | } |
1073 | ||
1074 | /* Embedded.Processor Control */ | |
1075 | static int dbell2irq(target_ulong rb) | |
1076 | { | |
1077 | int msg = rb & DBELL_TYPE_MASK; | |
1078 | int irq = -1; | |
1079 | ||
1080 | switch (msg) { | |
1081 | case DBELL_TYPE_DBELL: | |
1082 | irq = PPC_INTERRUPT_DOORBELL; | |
1083 | break; | |
1084 | case DBELL_TYPE_DBELL_CRIT: | |
1085 | irq = PPC_INTERRUPT_CDOORBELL; | |
1086 | break; | |
1087 | case DBELL_TYPE_G_DBELL: | |
1088 | case DBELL_TYPE_G_DBELL_CRIT: | |
1089 | case DBELL_TYPE_G_DBELL_MC: | |
1090 | /* XXX implement */ | |
1091 | default: | |
1092 | break; | |
1093 | } | |
1094 | ||
1095 | return irq; | |
1096 | } | |
1097 | ||
e5f17ac6 | 1098 | void helper_msgclr(CPUPPCState *env, target_ulong rb) |
ad71ed68 BS |
1099 | { |
1100 | int irq = dbell2irq(rb); | |
1101 | ||
1102 | if (irq < 0) { | |
1103 | return; | |
1104 | } | |
1105 | ||
1106 | env->pending_interrupts &= ~(1 << irq); | |
1107 | } | |
1108 | ||
1109 | void helper_msgsnd(target_ulong rb) | |
1110 | { | |
1111 | int irq = dbell2irq(rb); | |
1112 | int pir = rb & DBELL_PIRTAG_MASK; | |
182735ef | 1113 | CPUState *cs; |
ad71ed68 BS |
1114 | |
1115 | if (irq < 0) { | |
1116 | return; | |
1117 | } | |
1118 | ||
bdc44640 | 1119 | CPU_FOREACH(cs) { |
182735ef AF |
1120 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
1121 | CPUPPCState *cenv = &cpu->env; | |
1122 | ||
ad71ed68 BS |
1123 | if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { |
1124 | cenv->pending_interrupts |= 1 << irq; | |
182735ef | 1125 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
ad71ed68 BS |
1126 | } |
1127 | } | |
1128 | } | |
1129 | #endif |