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Provision for PowerPC 64 with hypervisor mode support - not enabled for now.
[mirror_qemu.git] / target-ppc / helper.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
fdabc366
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
27
28#include "cpu.h"
29#include "exec-all.h"
9a64fbe4
FB		 30
31//#define DEBUG_MMU
32//#define DEBUG_BATS
76a66253 33//#define DEBUG_SOFTWARE_TLB
9a64fbe4 34//#define DEBUG_EXCEPTIONS
fdabc366 35//#define FLUSH_ALL_TLBS
9a64fbe4 36
9a64fbe4 37/*****************************************************************************/
3fc6c082 38/* PowerPC MMU emulation */
a541f297 39
d9bce9d9 40#if defined(CONFIG_USER_ONLY)
e96efcfc 41int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 42 int mmu_idx, int is_softmmu)
24741ef3
FB		 43{
44 int exception, error_code;
d9bce9d9 45
24741ef3 46 if (rw == 2) {
e1833e1f 47 exception = POWERPC_EXCP_ISI;
8f793433 48 error_code = 0x40000000;
24741ef3 49 } else {
e1833e1f 50 exception = POWERPC_EXCP_DSI;
8f793433 51 error_code = 0x40000000;
24741ef3
FB		 52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
76a66253 59
24741ef3
FB		 60 return 1;
61}
76a66253 62
9b3c35e0 63target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
24741ef3
FB		 64{
65 return addr;
66}
36081602 67
24741ef3 68#else
76a66253 69/* Common routines used by software and hardware TLBs emulation */
b068d6a7 70static always_inline int pte_is_valid (target_ulong pte0)
76a66253
JM		 71{
72 return pte0 & 0x80000000 ? 1 : 0;
73}
74
b068d6a7 75static always_inline void pte_invalidate (target_ulong *pte0)
76a66253
JM		 76{
77 *pte0 &= ~0x80000000;
78}
79
caa4039c 80#if defined(TARGET_PPC64)
b068d6a7 81static always_inline int pte64_is_valid (target_ulong pte0)
caa4039c
JM		 82{
83 return pte0 & 0x0000000000000001ULL ? 1 : 0;
84}
85
b068d6a7 86static always_inline void pte64_invalidate (target_ulong *pte0)
caa4039c
JM		 87{
88 *pte0 &= ~0x0000000000000001ULL;
89}
90#endif
91
76a66253
JM		 92#define PTE_PTEM_MASK 0x7FFFFFBF
93#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
caa4039c
JM		 94#if defined(TARGET_PPC64)
95#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
96#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
97#endif
76a66253 98
b068d6a7
JM		 99static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
100 target_ulong pte0, target_ulong pte1,
101 int h, int rw)
76a66253 102{
caa4039c
JM		 103 target_ulong ptem, mmask;
104 int access, ret, pteh, ptev;
76a66253
JM		 105
106 access = 0;
107 ret = -1;
108 /* Check validity and table match */
caa4039c
JM		 109#if defined(TARGET_PPC64)
110 if (is_64b) {
111 ptev = pte64_is_valid(pte0);
112 pteh = (pte0 >> 1) & 1;
113 } else
114#endif
115 {
116 ptev = pte_is_valid(pte0);
117 pteh = (pte0 >> 6) & 1;
118 }
119 if (ptev && h == pteh) {
76a66253 120 /* Check vsid & api */
caa4039c
JM		 121#if defined(TARGET_PPC64)
122 if (is_64b) {
123 ptem = pte0 & PTE64_PTEM_MASK;
124 mmask = PTE64_CHECK_MASK;
125 } else
126#endif
127 {
128 ptem = pte0 & PTE_PTEM_MASK;
129 mmask = PTE_CHECK_MASK;
130 }
131 if (ptem == ctx->ptem) {
76a66253
JM		 132 if (ctx->raddr != (target_ulong)-1) {
133 /* all matches should have equal RPN, WIMG & PP */
caa4039c
JM		 134 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
135 if (loglevel != 0)
76a66253
JM		 136 fprintf(logfile, "Bad RPN/WIMG/PP\n");
137 return -3;
138 }
139 }
140 /* Compute access rights */
141 if (ctx->key == 0) {
142 access = PAGE_READ;
143 if ((pte1 & 0x00000003) != 0x3)
144 access |= PAGE_WRITE;
145 } else {
146 switch (pte1 & 0x00000003) {
147 case 0x0:
148 access = 0;
149 break;
150 case 0x1:
151 case 0x3:
152 access = PAGE_READ;
153 break;
154 case 0x2:
155 access = PAGE_READ | PAGE_WRITE;
156 break;
157 }
158 }
159 /* Keep the matching PTE informations */
160 ctx->raddr = pte1;
161 ctx->prot = access;
162 if ((rw == 0 && (access & PAGE_READ)) ||
163 (rw == 1 && (access & PAGE_WRITE))) {
164 /* Access granted */
165#if defined (DEBUG_MMU)
4a057712 166 if (loglevel != 0)
76a66253
JM		 167 fprintf(logfile, "PTE access granted !\n");
168#endif
169 ret = 0;
170 } else {
171 /* Access right violation */
172#if defined (DEBUG_MMU)
4a057712 173 if (loglevel != 0)
76a66253
JM		 174 fprintf(logfile, "PTE access rejected\n");
175#endif
176 ret = -2;
177 }
178 }
179 }
180
181 return ret;
182}
183
caa4039c
JM		 184static int pte32_check (mmu_ctx_t *ctx,
185 target_ulong pte0, target_ulong pte1, int h, int rw)
186{
187 return _pte_check(ctx, 0, pte0, pte1, h, rw);
188}
189
190#if defined(TARGET_PPC64)
191static int pte64_check (mmu_ctx_t *ctx,
192 target_ulong pte0, target_ulong pte1, int h, int rw)
193{
194 return _pte_check(ctx, 1, pte0, pte1, h, rw);
195}
196#endif
197
76a66253
JM		 198static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
199 int ret, int rw)
200{
201 int store = 0;
202
203 /* Update page flags */
204 if (!(*pte1p & 0x00000100)) {
205 /* Update accessed flag */
206 *pte1p |= 0x00000100;
207 store = 1;
208 }
209 if (!(*pte1p & 0x00000080)) {
210 if (rw == 1 && ret == 0) {
211 /* Update changed flag */
212 *pte1p |= 0x00000080;
213 store = 1;
214 } else {
215 /* Force page fault for first write access */
216 ctx->prot &= ~PAGE_WRITE;
217 }
218 }
219
220 return store;
221}
222
223/* Software driven TLB helpers */
224static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
225 int way, int is_code)
226{
227 int nr;
228
229 /* Select TLB num in a way from address */
230 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
231 /* Select TLB way */
232 nr += env->tlb_per_way * way;
233 /* 6xx have separate TLBs for instructions and data */
234 if (is_code && env->id_tlbs == 1)
235 nr += env->nb_tlb;
236
237 return nr;
238}
239
daf4f96e 240static void ppc6xx_tlb_invalidate_all (CPUState *env)
76a66253 241{
1d0a48fb 242 ppc6xx_tlb_t *tlb;
76a66253
JM		 243 int nr, max;
244
245#if defined (DEBUG_SOFTWARE_TLB) && 0
246 if (loglevel != 0) {
247 fprintf(logfile, "Invalidate all TLBs\n");
248 }
249#endif
250 /* Invalidate all defined software TLB */
251 max = env->nb_tlb;
252 if (env->id_tlbs == 1)
253 max *= 2;
254 for (nr = 0; nr < max; nr++) {
1d0a48fb 255 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 256 pte_invalidate(&tlb->pte0);
257 }
76a66253 258 tlb_flush(env, 1);
76a66253
JM		 259}
260
b068d6a7
JM		 261static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
262 target_ulong eaddr,
263 int is_code,
264 int match_epn)
76a66253 265{
4a057712 266#if !defined(FLUSH_ALL_TLBS)
1d0a48fb 267 ppc6xx_tlb_t *tlb;
76a66253
JM		 268 int way, nr;
269
76a66253
JM		 270 /* Invalidate ITLB + DTLB, all ways */
271 for (way = 0; way < env->nb_ways; way++) {
272 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
1d0a48fb 273 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 274 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
275#if defined (DEBUG_SOFTWARE_TLB)
276 if (loglevel != 0) {
1b9eb036 277 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
76a66253
JM		 278 nr, env->nb_tlb, eaddr);
279 }
280#endif
281 pte_invalidate(&tlb->pte0);
282 tlb_flush_page(env, tlb->EPN);
283 }
284 }
285#else
286 /* XXX: PowerPC specification say this is valid as well */
287 ppc6xx_tlb_invalidate_all(env);
288#endif
289}
290
daf4f96e
JM		 291static void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
292 int is_code)
76a66253
JM		 293{
294 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
295}
296
297void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
298 target_ulong pte0, target_ulong pte1)
299{
1d0a48fb 300 ppc6xx_tlb_t *tlb;
76a66253
JM		 301 int nr;
302
303 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
1d0a48fb 304 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 305#if defined (DEBUG_SOFTWARE_TLB)
306 if (loglevel != 0) {
5fafdf24 307 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
1b9eb036 308 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
76a66253
JM		 309 }
310#endif
311 /* Invalidate any pending reference in Qemu for this virtual address */
312 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
313 tlb->pte0 = pte0;
314 tlb->pte1 = pte1;
315 tlb->EPN = EPN;
76a66253
JM		 316 /* Store last way for LRU mechanism */
317 env->last_way = way;
318}
319
320static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
321 target_ulong eaddr, int rw, int access_type)
322{
1d0a48fb 323 ppc6xx_tlb_t *tlb;
76a66253
JM		 324 int nr, best, way;
325 int ret;
d9bce9d9 326
76a66253
JM		 327 best = -1;
328 ret = -1; /* No TLB found */
329 for (way = 0; way < env->nb_ways; way++) {
330 nr = ppc6xx_tlb_getnum(env, eaddr, way,
331 access_type == ACCESS_CODE ? 1 : 0);
1d0a48fb 332 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 333 /* This test "emulates" the PTE index match for hardware TLBs */
334 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
335#if defined (DEBUG_SOFTWARE_TLB)
336 if (loglevel != 0) {
1b9eb036
JM		 337 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
338 "] <> " ADDRX "\n",
76a66253
JM		 339 nr, env->nb_tlb,
340 pte_is_valid(tlb->pte0) ? "valid" : "inval",
341 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
342 }
343#endif
344 continue;
345 }
346#if defined (DEBUG_SOFTWARE_TLB)
347 if (loglevel != 0) {
1b9eb036
JM		 348 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
349 " %c %c\n",
76a66253
JM		 350 nr, env->nb_tlb,
351 pte_is_valid(tlb->pte0) ? "valid" : "inval",
352 tlb->EPN, eaddr, tlb->pte1,
353 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
354 }
355#endif
caa4039c 356 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
76a66253
JM		 357 case -3:
358 /* TLB inconsistency */
359 return -1;
360 case -2:
361 /* Access violation */
362 ret = -2;
363 best = nr;
364 break;
365 case -1:
366 default:
367 /* No match */
368 break;
369 case 0:
370 /* access granted */
371 /* XXX: we should go on looping to check all TLBs consistency
372 * but we can speed-up the whole thing as the
373 * result would be undefined if TLBs are not consistent.
374 */
375 ret = 0;
376 best = nr;
377 goto done;
378 }
379 }
380 if (best != -1) {
381 done:
382#if defined (DEBUG_SOFTWARE_TLB)
4a057712 383 if (loglevel != 0) {
76a66253
JM		 384 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
385 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
386 }
387#endif
388 /* Update page flags */
1d0a48fb 389 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
76a66253
JM		 390 }
391
392 return ret;
393}
394
9a64fbe4 395/* Perform BAT hit & translation */
76a66253
JM		 396static int get_bat (CPUState *env, mmu_ctx_t *ctx,
397 target_ulong virtual, int rw, int type)
9a64fbe4 398{
76a66253
JM		 399 target_ulong *BATlt, *BATut, *BATu, *BATl;
400 target_ulong base, BEPIl, BEPIu, bl;
9a64fbe4
FB		 401 int i;
402 int ret = -1;
403
404#if defined (DEBUG_BATS)
4a057712 405 if (loglevel != 0) {
1b9eb036 406 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 407 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 408 }
9a64fbe4
FB		 409#endif
410 switch (type) {
411 case ACCESS_CODE:
412 BATlt = env->IBAT[1];
413 BATut = env->IBAT[0];
414 break;
415 default:
416 BATlt = env->DBAT[1];
417 BATut = env->DBAT[0];
418 break;
419 }
420#if defined (DEBUG_BATS)
4a057712 421 if (loglevel != 0) {
1b9eb036 422 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 423 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 424 }
9a64fbe4
FB		 425#endif
426 base = virtual & 0xFFFC0000;
427 for (i = 0; i < 4; i++) {
428 BATu = &BATut[i];
429 BATl = &BATlt[i];
430 BEPIu = *BATu & 0xF0000000;
431 BEPIl = *BATu & 0x0FFE0000;
432 bl = (*BATu & 0x00001FFC) << 15;
433#if defined (DEBUG_BATS)
4a057712 434 if (loglevel != 0) {
5fafdf24 435 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
1b9eb036 436 " BATl 0x" ADDRX "\n",
9a64fbe4
FB		 437 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
438 *BATu, *BATl);
9a64fbe4
FB		 439 }
440#endif
441 if ((virtual & 0xF0000000) == BEPIu &&
442 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
443 /* BAT matches */
444 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
445 (msr_pr == 1 && (*BATu & 0x00000001))) {
446 /* Get physical address */
76a66253 447 ctx->raddr = (*BATl & 0xF0000000) |
9a64fbe4 448 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
a541f297 449 (virtual & 0x0001F000);
9a64fbe4 450 if (*BATl & 0x00000001)
76a66253 451 ctx->prot = PAGE_READ;
9a64fbe4 452 if (*BATl & 0x00000002)
76a66253 453 ctx->prot = PAGE_WRITE | PAGE_READ;
9a64fbe4 454#if defined (DEBUG_BATS)
4a057712
JM		 455 if (loglevel != 0) {
456 fprintf(logfile, "BAT %d match: r 0x" PADDRX
1b9eb036 457 " prot=%c%c\n",
76a66253
JM		 458 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
459 ctx->prot & PAGE_WRITE ? 'W' : '-');
9a64fbe4
FB		 460 }
461#endif
462 ret = 0;
463 break;
464 }
465 }
466 }
467 if (ret < 0) {
468#if defined (DEBUG_BATS)
4a057712
JM		 469 if (loglevel != 0) {
470 fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
471 for (i = 0; i < 4; i++) {
472 BATu = &BATut[i];
473 BATl = &BATlt[i];
474 BEPIu = *BATu & 0xF0000000;
475 BEPIl = *BATu & 0x0FFE0000;
476 bl = (*BATu & 0x00001FFC) << 15;
477 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
478 " BATl 0x" ADDRX " \n\t"
479 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
480 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
481 *BATu, *BATl, BEPIu, BEPIl, bl);
482 }
9a64fbe4
FB		 483 }
484#endif
9a64fbe4
FB		 485 }
486 /* No hit */
487 return ret;
488}
489
490/* PTE table lookup */
b068d6a7 491static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
9a64fbe4 492{
76a66253
JM		 493 target_ulong base, pte0, pte1;
494 int i, good = -1;
caa4039c 495 int ret, r;
9a64fbe4 496
76a66253
JM		 497 ret = -1; /* No entry found */
498 base = ctx->pg_addr[h];
9a64fbe4 499 for (i = 0; i < 8; i++) {
caa4039c
JM		 500#if defined(TARGET_PPC64)
501 if (is_64b) {
502 pte0 = ldq_phys(base + (i * 16));
503 pte1 = ldq_phys(base + (i * 16) + 8);
504 r = pte64_check(ctx, pte0, pte1, h, rw);
12de9a39
JM		 505#if defined (DEBUG_MMU)
506 if (loglevel != 0) {
507 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
508 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
509 base + (i * 16), pte0, pte1,
510 (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
511 ctx->ptem);
512 }
513#endif
caa4039c
JM		 514 } else
515#endif
516 {
517 pte0 = ldl_phys(base + (i * 8));
518 pte1 = ldl_phys(base + (i * 8) + 4);
519 r = pte32_check(ctx, pte0, pte1, h, rw);
9a64fbe4 520#if defined (DEBUG_MMU)
12de9a39
JM		 521 if (loglevel != 0) {
522 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
523 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
524 base + (i * 8), pte0, pte1,
525 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
526 ctx->ptem);
527 }
9a64fbe4 528#endif
12de9a39 529 }
caa4039c 530 switch (r) {
76a66253
JM		 531 case -3:
532 /* PTE inconsistency */
533 return -1;
534 case -2:
535 /* Access violation */
536 ret = -2;
537 good = i;
538 break;
539 case -1:
540 default:
541 /* No PTE match */
542 break;
543 case 0:
544 /* access granted */
545 /* XXX: we should go on looping to check all PTEs consistency
546 * but if we can speed-up the whole thing as the
547 * result would be undefined if PTEs are not consistent.
548 */
549 ret = 0;
550 good = i;
551 goto done;
9a64fbe4
FB		 552 }
553 }
554 if (good != -1) {
76a66253 555 done:
9a64fbe4 556#if defined (DEBUG_MMU)
4a057712
JM		 557 if (loglevel != 0) {
558 fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
1b9eb036 559 "ret=%d\n",
76a66253
JM		 560 ctx->raddr, ctx->prot, ret);
561 }
9a64fbe4
FB		 562#endif
563 /* Update page flags */
76a66253 564 pte1 = ctx->raddr;
caa4039c
JM		 565 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
566#if defined(TARGET_PPC64)
567 if (is_64b) {
568 stq_phys_notdirty(base + (good * 16) + 8, pte1);
569 } else
570#endif
571 {
572 stl_phys_notdirty(base + (good * 8) + 4, pte1);
573 }
574 }
9a64fbe4
FB		 575 }
576
577 return ret;
79aceca5
FB		 578}
579
caa4039c
JM		 580static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
581{
582 return _find_pte(ctx, 0, h, rw);
583}
584
585#if defined(TARGET_PPC64)
586static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
587{
588 return _find_pte(ctx, 1, h, rw);
589}
590#endif
591
b068d6a7
JM		 592static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
593 int h, int rw)
caa4039c
JM		 594{
595#if defined(TARGET_PPC64)
12de9a39 596 if (env->mmu_model == POWERPC_MMU_64B)
caa4039c
JM		 597 return find_pte64(ctx, h, rw);
598#endif
599
600 return find_pte32(ctx, h, rw);
601}
602
caa4039c 603#if defined(TARGET_PPC64)
12de9a39 604static int slb_lookup (CPUPPCState *env, target_ulong eaddr,
caa4039c
JM		 605 target_ulong *vsid, target_ulong *page_mask, int *attr)
606{
607 target_phys_addr_t sr_base;
608 target_ulong mask;
609 uint64_t tmp64;
610 uint32_t tmp;
611 int n, ret;
612 int slb_nr;
613
614 ret = -5;
615 sr_base = env->spr[SPR_ASR];
12de9a39
JM		 616#if defined(DEBUG_SLB)
617 if (loglevel != 0) {
618 fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n",
619 __func__, eaddr, sr_base);
620 }
621#endif
caa4039c 622 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
caa4039c 623 slb_nr = env->slb_nr;
caa4039c
JM		 624 for (n = 0; n < slb_nr; n++) {
625 tmp64 = ldq_phys(sr_base);
12de9a39
JM		 626 tmp = ldl_phys(sr_base + 8);
627#if defined(DEBUG_SLB)
628 if (loglevel != 0) {
b33c17e1
JM		 629 fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08"
630 PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
12de9a39
JM		 631 }
632#endif
caa4039c
JM		 633 if (tmp64 & 0x0000000008000000ULL) {
634 /* SLB entry is valid */
635 switch (tmp64 & 0x0000000006000000ULL) {
636 case 0x0000000000000000ULL:
637 /* 256 MB segment */
638 mask = 0xFFFFFFFFF0000000ULL;
639 break;
640 case 0x0000000002000000ULL:
641 /* 1 TB segment */
642 mask = 0xFFFF000000000000ULL;
643 break;
644 case 0x0000000004000000ULL:
645 case 0x0000000006000000ULL:
646 /* Reserved => segment is invalid */
647 continue;
648 }
649 if ((eaddr & mask) == (tmp64 & mask)) {
650 /* SLB match */
caa4039c
JM		 651 *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
652 *page_mask = ~mask;
653 *attr = tmp & 0xFF;
654 ret = 0;
655 break;
656 }
657 }
658 sr_base += 12;
659 }
660
661 return ret;
79aceca5 662}
12de9a39
JM		 663
664target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
665{
666 target_phys_addr_t sr_base;
667 target_ulong rt;
668 uint64_t tmp64;
669 uint32_t tmp;
670
671 sr_base = env->spr[SPR_ASR];
672 sr_base += 12 * slb_nr;
673 tmp64 = ldq_phys(sr_base);
674 tmp = ldl_phys(sr_base + 8);
675 if (tmp64 & 0x0000000008000000ULL) {
676 /* SLB entry is valid */
677 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
678 rt = tmp >> 8; /* 65:88 => 40:63 */
679 rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
680 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
681 rt |= ((tmp >> 4) & 0xF) << 27;
682 } else {
683 rt = 0;
684 }
685#if defined(DEBUG_SLB)
686 if (loglevel != 0) {
687 fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
688 ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
689 }
690#endif
691
692 return rt;
693}
694
695void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
696{
697 target_phys_addr_t sr_base;
698 uint64_t tmp64;
699 uint32_t tmp;
700
701 sr_base = env->spr[SPR_ASR];
702 sr_base += 12 * slb_nr;
703 /* Copy Rs bits 37:63 to SLB 62:88 */
704 tmp = rs << 8;
705 tmp64 = (rs >> 24) & 0x7;
706 /* Copy Rs bits 33:36 to SLB 89:92 */
707 tmp |= ((rs >> 27) & 0xF) << 4;
708 /* Set the valid bit */
709 tmp64 |= 1 << 27;
710 /* Set ESID */
711 tmp64 |= (uint32_t)slb_nr << 28;
712#if defined(DEBUG_SLB)
713 if (loglevel != 0) {
714 fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64 " %08"
715 PRIx32 "\n", __func__, slb_nr, rs, sr_base, tmp64, tmp);
716 }
717#endif
718 /* Write SLB entry to memory */
719 stq_phys(sr_base, tmp64);
720 stl_phys(sr_base + 8, tmp);
721}
caa4039c 722#endif /* defined(TARGET_PPC64) */
79aceca5 723
9a64fbe4 724/* Perform segment based translation */
b068d6a7
JM		 725static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
726 int sdr_sh,
727 target_phys_addr_t hash,
728 target_phys_addr_t mask)
12de9a39
JM		 729{
730 return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
731}
732
76a66253
JM		 733static int get_segment (CPUState *env, mmu_ctx_t *ctx,
734 target_ulong eaddr, int rw, int type)
79aceca5 735{
12de9a39 736 target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
caa4039c
JM		 737 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
738#if defined(TARGET_PPC64)
739 int attr;
9a64fbe4 740#endif
caa4039c
JM		 741 int ds, nx, vsid_sh, sdr_sh;
742 int ret, ret2;
743
744#if defined(TARGET_PPC64)
12de9a39
JM		 745 if (env->mmu_model == POWERPC_MMU_64B) {
746#if defined (DEBUG_MMU)
747 if (loglevel != 0) {
748 fprintf(logfile, "Check SLBs\n");
749 }
750#endif
caa4039c
JM		 751 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
752 if (ret < 0)
753 return ret;
754 ctx->key = ((attr & 0x40) && msr_pr == 1) ||
755 ((attr & 0x80) && msr_pr == 0) ? 1 : 0;
756 ds = 0;
757 nx = attr & 0x20 ? 1 : 0;
758 vsid_mask = 0x00003FFFFFFFFF80ULL;
759 vsid_sh = 7;
760 sdr_sh = 18;
761 sdr_mask = 0x3FF80;
762 } else
763#endif /* defined(TARGET_PPC64) */
764 {
765 sr = env->sr[eaddr >> 28];
766 page_mask = 0x0FFFFFFF;
767 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
768 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
769 ds = sr & 0x80000000 ? 1 : 0;
770 nx = sr & 0x10000000 ? 1 : 0;
771 vsid = sr & 0x00FFFFFF;
772 vsid_mask = 0x01FFFFC0;
773 vsid_sh = 6;
774 sdr_sh = 16;
775 sdr_mask = 0xFFC0;
9a64fbe4 776#if defined (DEBUG_MMU)
caa4039c
JM		 777 if (loglevel != 0) {
778 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
779 " nip=0x" ADDRX " lr=0x" ADDRX
780 " ir=%d dr=%d pr=%d %d t=%d\n",
781 eaddr, (int)(eaddr >> 28), sr, env->nip,
782 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
783 }
9a64fbe4 784#endif
caa4039c 785 }
12de9a39
JM		 786#if defined (DEBUG_MMU)
787 if (loglevel != 0) {
788 fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
789 ctx->key, ds, nx, vsid);
790 }
791#endif
caa4039c
JM		 792 ret = -1;
793 if (!ds) {
9a64fbe4 794 /* Check if instruction fetch is allowed, if needed */
caa4039c 795 if (type != ACCESS_CODE || nx == 0) {
9a64fbe4 796 /* Page address translation */
76a66253
JM		 797 /* Primary table address */
798 sdr = env->sdr1;
12de9a39
JM		 799 pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
800#if defined(TARGET_PPC64)
801 if (env->mmu_model == POWERPC_MMU_64B) {
802 htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
803 /* XXX: this is false for 1 TB segments */
804 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
805 } else
806#endif
807 {
808 htab_mask = sdr & 0x000001FF;
809 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
810 }
811 mask = (htab_mask << sdr_sh) | sdr_mask;
812#if defined (DEBUG_MMU)
813 if (loglevel != 0) {
814 fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
815 PADDRX " " ADDRX "\n", sdr, sdr_sh, hash, mask,
816 page_mask);
817 }
818#endif
caa4039c 819 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
76a66253 820 /* Secondary table address */
caa4039c 821 hash = (~hash) & vsid_mask;
12de9a39
JM		 822#if defined (DEBUG_MMU)
823 if (loglevel != 0) {
824 fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX " mask "
825 PADDRX "\n", sdr, sdr_sh, hash, mask);
826 }
827#endif
caa4039c
JM		 828 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
829#if defined(TARGET_PPC64)
12de9a39 830 if (env->mmu_model == POWERPC_MMU_64B) {
caa4039c
JM		 831 /* Only 5 bits of the page index are used in the AVPN */
832 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
833 } else
834#endif
835 {
836 ctx->ptem = (vsid << 7) | (pgidx >> 10);
837 }
76a66253
JM		 838 /* Initialize real address with an invalid value */
839 ctx->raddr = (target_ulong)-1;
7dbe11ac
JM		 840 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
841 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
76a66253
JM		 842 /* Software TLB search */
843 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
76a66253 844 } else {
9a64fbe4 845#if defined (DEBUG_MMU)
4a057712
JM		 846 if (loglevel != 0) {
847 fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
848 "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
849 sdr, (uint32_t)vsid, (uint32_t)pgidx,
850 (uint32_t)hash, ctx->pg_addr[0]);
76a66253 851 }
9a64fbe4 852#endif
76a66253 853 /* Primary table lookup */
caa4039c 854 ret = find_pte(env, ctx, 0, rw);
76a66253
JM		 855 if (ret < 0) {
856 /* Secondary table lookup */
9a64fbe4 857#if defined (DEBUG_MMU)
4a057712 858 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
76a66253 859 fprintf(logfile,
4a057712
JM		 860 "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
861 "hash=0x%05x pg_addr=0x" PADDRX "\n",
862 sdr, (uint32_t)vsid, (uint32_t)pgidx,
863 (uint32_t)hash, ctx->pg_addr[1]);
76a66253 864 }
9a64fbe4 865#endif
caa4039c 866 ret2 = find_pte(env, ctx, 1, rw);
76a66253
JM		 867 if (ret2 != -1)
868 ret = ret2;
869 }
9a64fbe4 870 }
12de9a39 871#if defined (DEBUG_MMU)
b33c17e1
JM		 872 if (loglevel != 0) {
873 target_phys_addr_t curaddr;
874 uint32_t a0, a1, a2, a3;
875 fprintf(logfile,
876 "Page table: " PADDRX " len " PADDRX "\n",
877 sdr, mask + 0x80);
878 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
879 curaddr += 16) {
880 a0 = ldl_phys(curaddr);
881 a1 = ldl_phys(curaddr + 4);
882 a2 = ldl_phys(curaddr + 8);
883 a3 = ldl_phys(curaddr + 12);
884 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
12de9a39 885 fprintf(logfile,
b33c17e1
JM		 886 PADDRX ": %08x %08x %08x %08x\n",
887 curaddr, a0, a1, a2, a3);
12de9a39 888 }
b33c17e1
JM		 889 }
890 }
12de9a39 891#endif
9a64fbe4
FB		 892 } else {
893#if defined (DEBUG_MMU)
4a057712 894 if (loglevel != 0)
76a66253 895 fprintf(logfile, "No access allowed\n");
9a64fbe4 896#endif
76a66253 897 ret = -3;
9a64fbe4
FB		 898 }
899 } else {
900#if defined (DEBUG_MMU)
4a057712 901 if (loglevel != 0)
76a66253 902 fprintf(logfile, "direct store...\n");
9a64fbe4
FB		 903#endif
904 /* Direct-store segment : absolutely *BUGGY* for now */
905 switch (type) {
906 case ACCESS_INT:
907 /* Integer load/store : only access allowed */
908 break;
909 case ACCESS_CODE:
910 /* No code fetch is allowed in direct-store areas */
911 return -4;
912 case ACCESS_FLOAT:
913 /* Floating point load/store */
914 return -4;
915 case ACCESS_RES:
916 /* lwarx, ldarx or srwcx. */
917 return -4;
918 case ACCESS_CACHE:
919 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
920 /* Should make the instruction do no-op.
921 * As it already do no-op, it's quite easy :-)
922 */
76a66253 923 ctx->raddr = eaddr;
9a64fbe4
FB		 924 return 0;
925 case ACCESS_EXT:
926 /* eciwx or ecowx */
927 return -4;
928 default:
929 if (logfile) {
930 fprintf(logfile, "ERROR: instruction should not need "
931 "address translation\n");
932 }
9a64fbe4
FB		 933 return -4;
934 }
76a66253
JM		 935 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
936 ctx->raddr = eaddr;
9a64fbe4
FB		 937 ret = 2;
938 } else {
939 ret = -2;
940 }
79aceca5 941 }
9a64fbe4
FB		 942
943 return ret;
79aceca5
FB		 944}
945
c294fc58
JM		 946/* Generic TLB check function for embedded PowerPC implementations */
947static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
948 target_phys_addr_t *raddrp,
36081602
JM		 949 target_ulong address,
950 uint32_t pid, int ext, int i)
c294fc58
JM		 951{
952 target_ulong mask;
953
954 /* Check valid flag */
955 if (!(tlb->prot & PAGE_VALID)) {
956 if (loglevel != 0)
957 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
958 return -1;
959 }
960 mask = ~(tlb->size - 1);
daf4f96e 961#if defined (DEBUG_SOFTWARE_TLB)
c294fc58
JM		 962 if (loglevel != 0) {
963 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
964 ADDRX " " ADDRX " %d\n",
36081602 965 __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
c294fc58 966 }
daf4f96e 967#endif
c294fc58 968 /* Check PID */
36081602 969 if (tlb->PID != 0 && tlb->PID != pid)
c294fc58
JM		 970 return -1;
971 /* Check effective address */
972 if ((address & mask) != tlb->EPN)
973 return -1;
974 *raddrp = (tlb->RPN & mask) | (address & ~mask);
9706285b 975#if (TARGET_PHYS_ADDR_BITS >= 36)
36081602
JM		 976 if (ext) {
977 /* Extend the physical address to 36 bits */
978 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
979 }
9706285b 980#endif
c294fc58
JM		 981
982 return 0;
983}
984
985/* Generic TLB search function for PowerPC embedded implementations */
36081602 986int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
c294fc58
JM		 987{
988 ppcemb_tlb_t *tlb;
989 target_phys_addr_t raddr;
990 int i, ret;
991
992 /* Default return value is no match */
993 ret = -1;
a750fc0b 994 for (i = 0; i < env->nb_tlb; i++) {
c294fc58 995 tlb = &env->tlb[i].tlbe;
36081602 996 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
c294fc58
JM		 997 ret = i;
998 break;
999 }
1000 }
1001
1002 return ret;
1003}
1004
daf4f96e
JM		 1005/* Helpers specific to PowerPC 40x implementations */
1006static void ppc4xx_tlb_invalidate_all (CPUState *env)
a750fc0b
JM		 1007{
1008 ppcemb_tlb_t *tlb;
a750fc0b
JM		 1009 int i;
1010
1011 for (i = 0; i < env->nb_tlb; i++) {
1012 tlb = &env->tlb[i].tlbe;
daf4f96e 1013 tlb->prot &= ~PAGE_VALID;
a750fc0b 1014 }
daf4f96e 1015 tlb_flush(env, 1);
a750fc0b
JM		 1016}
1017
daf4f96e
JM		 1018static void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
1019 uint32_t pid)
0a032cbe 1020{
daf4f96e 1021#if !defined(FLUSH_ALL_TLBS)
0a032cbe 1022 ppcemb_tlb_t *tlb;
daf4f96e
JM		 1023 target_phys_addr_t raddr;
1024 target_ulong page, end;
0a032cbe
JM		 1025 int i;
1026
1027 for (i = 0; i < env->nb_tlb; i++) {
1028 tlb = &env->tlb[i].tlbe;
daf4f96e 1029 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
0a032cbe
JM		 1030 end = tlb->EPN + tlb->size;
1031 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1032 tlb_flush_page(env, page);
0a032cbe 1033 tlb->prot &= ~PAGE_VALID;
daf4f96e 1034 break;
0a032cbe
JM		 1035 }
1036 }
daf4f96e
JM		 1037#else
1038 ppc4xx_tlb_invalidate_all(env);
1039#endif
0a032cbe
JM		 1040}
1041
36081602 1042int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
e96efcfc 1043 target_ulong address, int rw, int access_type)
a8dea12f
JM		 1044{
1045 ppcemb_tlb_t *tlb;
1046 target_phys_addr_t raddr;
a8dea12f 1047 int i, ret, zsel, zpr;
3b46e624 1048
c55e9aef
JM		 1049 ret = -1;
1050 raddr = -1;
a8dea12f
JM		 1051 for (i = 0; i < env->nb_tlb; i++) {
1052 tlb = &env->tlb[i].tlbe;
36081602
JM		 1053 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1054 env->spr[SPR_40x_PID], 0, i) < 0)
a8dea12f 1055 continue;
a8dea12f
JM		 1056 zsel = (tlb->attr >> 4) & 0xF;
1057 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
daf4f96e 1058#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1059 if (loglevel != 0) {
a8dea12f
JM		 1060 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1061 __func__, i, zsel, zpr, rw, tlb->attr);
1062 }
daf4f96e 1063#endif
a8dea12f
JM		 1064 if (access_type == ACCESS_CODE) {
1065 /* Check execute enable bit */
1066 switch (zpr) {
c294fc58
JM		 1067 case 0x2:
1068 if (msr_pr)
1069 goto check_exec_perm;
1070 goto exec_granted;
a8dea12f
JM		 1071 case 0x0:
1072 if (msr_pr) {
a8dea12f 1073 ctx->prot = 0;
c55e9aef 1074 ret = -3;
a8dea12f
JM		 1075 break;
1076 }
1077 /* No break here */
1078 case 0x1:
c294fc58 1079 check_exec_perm:
a8dea12f
JM		 1080 /* Check from TLB entry */
1081 if (!(tlb->prot & PAGE_EXEC)) {
1082 ret = -3;
1083 } else {
c55e9aef 1084 if (tlb->prot & PAGE_WRITE) {
a8dea12f 1085 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 1086 } else {
a8dea12f 1087 ctx->prot = PAGE_READ;
c55e9aef 1088 }
a8dea12f
JM		 1089 ret = 0;
1090 }
1091 break;
1092 case 0x3:
c294fc58 1093 exec_granted:
a8dea12f 1094 /* All accesses granted */
a8dea12f 1095 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 1096 ret = 0;
a8dea12f
JM		 1097 break;
1098 }
1099 } else {
1100 switch (zpr) {
c294fc58
JM		 1101 case 0x2:
1102 if (msr_pr)
1103 goto check_rw_perm;
1104 goto rw_granted;
a8dea12f
JM		 1105 case 0x0:
1106 if (msr_pr) {
a8dea12f 1107 ctx->prot = 0;
c55e9aef 1108 ret = -2;
a8dea12f
JM		 1109 break;
1110 }
1111 /* No break here */
1112 case 0x1:
c294fc58 1113 check_rw_perm:
a8dea12f
JM		 1114 /* Check from TLB entry */
1115 /* Check write protection bit */
c55e9aef
JM		 1116 if (tlb->prot & PAGE_WRITE) {
1117 ctx->prot = PAGE_READ | PAGE_WRITE;
1118 ret = 0;
a8dea12f 1119 } else {
c55e9aef
JM		 1120 ctx->prot = PAGE_READ;
1121 if (rw)
1122 ret = -2;
a8dea12f 1123 else
c55e9aef 1124 ret = 0;
a8dea12f
JM		 1125 }
1126 break;
1127 case 0x3:
c294fc58 1128 rw_granted:
a8dea12f 1129 /* All accesses granted */
a8dea12f 1130 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 1131 ret = 0;
a8dea12f
JM		 1132 break;
1133 }
1134 }
1135 if (ret >= 0) {
1136 ctx->raddr = raddr;
daf4f96e 1137#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1138 if (loglevel != 0) {
a8dea12f 1139 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
c55e9aef
JM		 1140 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1141 ret);
a8dea12f 1142 }
daf4f96e 1143#endif
c55e9aef 1144 return 0;
a8dea12f
JM		 1145 }
1146 }
daf4f96e 1147#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1148 if (loglevel != 0) {
c55e9aef
JM		 1149 fprintf(logfile, "%s: access refused " ADDRX " => " REGX
1150 " %d %d\n", __func__, address, raddr, ctx->prot,
1151 ret);
1152 }
daf4f96e 1153#endif
3b46e624 1154
a8dea12f
JM		 1155 return ret;
1156}
1157
c294fc58
JM		 1158void store_40x_sler (CPUPPCState *env, uint32_t val)
1159{
1160 /* XXX: TO BE FIXED */
1161 if (val != 0x00000000) {
1162 cpu_abort(env, "Little-endian regions are not supported by now\n");
1163 }
1164 env->spr[SPR_405_SLER] = val;
1165}
1166
5eb7995e
JM		 1167int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1168 target_ulong address, int rw,
1169 int access_type)
1170{
1171 ppcemb_tlb_t *tlb;
1172 target_phys_addr_t raddr;
1173 int i, prot, ret;
1174
1175 ret = -1;
1176 raddr = -1;
1177 for (i = 0; i < env->nb_tlb; i++) {
1178 tlb = &env->tlb[i].tlbe;
1179 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1180 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1181 continue;
1182 if (msr_pr)
1183 prot = tlb->prot & 0xF;
1184 else
1185 prot = (tlb->prot >> 4) & 0xF;
1186 /* Check the address space */
1187 if (access_type == ACCESS_CODE) {
d26bfc9a 1188 if (msr_ir != (tlb->attr & 1))
5eb7995e
JM		 1189 continue;
1190 ctx->prot = prot;
1191 if (prot & PAGE_EXEC) {
1192 ret = 0;
1193 break;
1194 }
1195 ret = -3;
1196 } else {
d26bfc9a 1197 if (msr_dr != (tlb->attr & 1))
5eb7995e
JM		 1198 continue;
1199 ctx->prot = prot;
1200 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1201 ret = 0;
1202 break;
1203 }
1204 ret = -2;
1205 }
1206 }
1207 if (ret >= 0)
1208 ctx->raddr = raddr;
1209
1210 return ret;
1211}
1212
76a66253
JM		 1213static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1214 target_ulong eaddr, int rw)
1215{
1216 int in_plb, ret;
3b46e624 1217
76a66253
JM		 1218 ctx->raddr = eaddr;
1219 ctx->prot = PAGE_READ;
1220 ret = 0;
a750fc0b
JM		 1221 switch (env->mmu_model) {
1222 case POWERPC_MMU_32B:
1223 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1224 case POWERPC_MMU_SOFT_74xx:
a750fc0b
JM		 1225 case POWERPC_MMU_601:
1226 case POWERPC_MMU_SOFT_4xx:
1227 case POWERPC_MMU_REAL_4xx:
7dbe11ac 1228 case POWERPC_MMU_BOOKE:
caa4039c
JM		 1229 ctx->prot |= PAGE_WRITE;
1230 break;
1231#if defined(TARGET_PPC64)
a750fc0b 1232 case POWERPC_MMU_64B:
caa4039c 1233 /* Real address are 60 bits long */
a750fc0b 1234 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
caa4039c
JM		 1235 ctx->prot |= PAGE_WRITE;
1236 break;
9706285b 1237#endif
a750fc0b 1238 case POWERPC_MMU_SOFT_4xx_Z:
caa4039c
JM		 1239 if (unlikely(msr_pe != 0)) {
1240 /* 403 family add some particular protections,
1241 * using PBL/PBU registers for accesses with no translation.
1242 */
1243 in_plb =
1244 /* Check PLB validity */
1245 (env->pb[0] < env->pb[1] &&
1246 /* and address in plb area */
1247 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1248 (env->pb[2] < env->pb[3] &&
1249 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1250 if (in_plb ^ msr_px) {
1251 /* Access in protected area */
1252 if (rw == 1) {
1253 /* Access is not allowed */
1254 ret = -2;
1255 }
1256 } else {
1257 /* Read-write access is allowed */
1258 ctx->prot |= PAGE_WRITE;
76a66253 1259 }
76a66253 1260 }
e1833e1f 1261 break;
a750fc0b 1262 case POWERPC_MMU_BOOKE_FSL:
caa4039c
JM		 1263 /* XXX: TODO */
1264 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1265 break;
1266 default:
1267 cpu_abort(env, "Unknown or invalid MMU model\n");
1268 return -1;
76a66253
JM		 1269 }
1270
1271 return ret;
1272}
1273
1274int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1275 int rw, int access_type, int check_BATs)
9a64fbe4
FB		 1276{
1277 int ret;
514fb8c1 1278#if 0
4a057712 1279 if (loglevel != 0) {
9a64fbe4
FB		 1280 fprintf(logfile, "%s\n", __func__);
1281 }
d9bce9d9 1282#endif
4b3686fa
FB		 1283 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1284 (access_type != ACCESS_CODE && msr_dr == 0)) {
9a64fbe4 1285 /* No address translation */
76a66253 1286 ret = check_physical(env, ctx, eaddr, rw);
9a64fbe4 1287 } else {
c55e9aef 1288 ret = -1;
a750fc0b
JM		 1289 switch (env->mmu_model) {
1290 case POWERPC_MMU_32B:
1291 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1292 case POWERPC_MMU_SOFT_74xx:
a8dea12f 1293 /* Try to find a BAT */
a8dea12f
JM		 1294 if (check_BATs)
1295 ret = get_bat(env, ctx, eaddr, rw, access_type);
c55e9aef
JM		 1296 /* No break here */
1297#if defined(TARGET_PPC64)
a750fc0b 1298 case POWERPC_MMU_64B:
c55e9aef 1299#endif
a8dea12f 1300 if (ret < 0) {
c55e9aef 1301 /* We didn't match any BAT entry or don't have BATs */
a8dea12f
JM		 1302 ret = get_segment(env, ctx, eaddr, rw, access_type);
1303 }
1304 break;
a750fc0b
JM		 1305 case POWERPC_MMU_SOFT_4xx:
1306 case POWERPC_MMU_SOFT_4xx_Z:
36081602 1307 ret = mmu40x_get_physical_address(env, ctx, eaddr,
a8dea12f
JM		 1308 rw, access_type);
1309 break;
a750fc0b 1310 case POWERPC_MMU_601:
c55e9aef
JM		 1311 /* XXX: TODO */
1312 cpu_abort(env, "601 MMU model not implemented\n");
1313 return -1;
a750fc0b 1314 case POWERPC_MMU_BOOKE:
5eb7995e
JM		 1315 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1316 rw, access_type);
1317 break;
a750fc0b 1318 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1319 /* XXX: TODO */
1320 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1321 return -1;
a750fc0b 1322 case POWERPC_MMU_REAL_4xx:
2662a059
JM		 1323 cpu_abort(env, "PowerPC 401 does not do any translation\n");
1324 return -1;
c55e9aef
JM		 1325 default:
1326 cpu_abort(env, "Unknown or invalid MMU model\n");
a8dea12f 1327 return -1;
9a64fbe4
FB		 1328 }
1329 }
514fb8c1 1330#if 0
4a057712
JM		 1331 if (loglevel != 0) {
1332 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
c55e9aef 1333 __func__, eaddr, ret, ctx->raddr);
a541f297 1334 }
76a66253 1335#endif
d9bce9d9 1336
9a64fbe4
FB		 1337 return ret;
1338}
1339
9b3c35e0 1340target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
a6b025d3 1341{
76a66253 1342 mmu_ctx_t ctx;
a6b025d3 1343
76a66253 1344 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
a6b025d3 1345 return -1;
76a66253
JM		 1346
1347 return ctx.raddr & TARGET_PAGE_MASK;
a6b025d3 1348}
9a64fbe4 1349
9a64fbe4 1350/* Perform address translation */
e96efcfc 1351int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 1352 int mmu_idx, int is_softmmu)
9a64fbe4 1353{
76a66253 1354 mmu_ctx_t ctx;
a541f297 1355 int access_type;
9a64fbe4 1356 int ret = 0;
d9bce9d9 1357
b769d8fe
FB		 1358 if (rw == 2) {
1359 /* code access */
1360 rw = 0;
1361 access_type = ACCESS_CODE;
1362 } else {
1363 /* data access */
1364 /* XXX: put correct access by using cpu_restore_state()
1365 correctly */
1366 access_type = ACCESS_INT;
1367 // access_type = env->access_type;
1368 }
76a66253 1369 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
9a64fbe4 1370 if (ret == 0) {
76a66253
JM		 1371 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
1372 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
6ebbf390 1373 mmu_idx, is_softmmu);
9a64fbe4 1374 } else if (ret < 0) {
9a64fbe4 1375#if defined (DEBUG_MMU)
4a057712 1376 if (loglevel != 0)
76a66253 1377 cpu_dump_state(env, logfile, fprintf, 0);
9a64fbe4
FB		 1378#endif
1379 if (access_type == ACCESS_CODE) {
9a64fbe4
FB		 1380 switch (ret) {
1381 case -1:
76a66253 1382 /* No matches in page tables or TLB */
a750fc0b
JM		 1383 switch (env->mmu_model) {
1384 case POWERPC_MMU_SOFT_6xx:
8f793433
JM		 1385 env->exception_index = POWERPC_EXCP_IFTLB;
1386 env->error_code = 1 << 18;
76a66253
JM		 1387 env->spr[SPR_IMISS] = address;
1388 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
76a66253 1389 goto tlb_miss;
7dbe11ac 1390 case POWERPC_MMU_SOFT_74xx:
8f793433 1391 env->exception_index = POWERPC_EXCP_IFTLB;
7dbe11ac 1392 goto tlb_miss_74xx;
a750fc0b
JM		 1393 case POWERPC_MMU_SOFT_4xx:
1394 case POWERPC_MMU_SOFT_4xx_Z:
8f793433
JM		 1395 env->exception_index = POWERPC_EXCP_ITLB;
1396 env->error_code = 0;
a8dea12f
JM		 1397 env->spr[SPR_40x_DEAR] = address;
1398 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef 1399 break;
a750fc0b 1400 case POWERPC_MMU_32B:
c55e9aef 1401#if defined(TARGET_PPC64)
a750fc0b 1402 case POWERPC_MMU_64B:
c55e9aef 1403#endif
8f793433
JM		 1404 env->exception_index = POWERPC_EXCP_ISI;
1405 env->error_code = 0x40000000;
1406 break;
a750fc0b 1407 case POWERPC_MMU_601:
c55e9aef
JM		 1408 /* XXX: TODO */
1409 cpu_abort(env, "MMU model not implemented\n");
1410 return -1;
a750fc0b 1411 case POWERPC_MMU_BOOKE:
c55e9aef
JM		 1412 /* XXX: TODO */
1413 cpu_abort(env, "MMU model not implemented\n");
1414 return -1;
a750fc0b 1415 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1416 /* XXX: TODO */
1417 cpu_abort(env, "MMU model not implemented\n");
1418 return -1;
a750fc0b 1419 case POWERPC_MMU_REAL_4xx:
2662a059
JM		 1420 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1421 "exceptions\n");
1422 return -1;
c55e9aef
JM		 1423 default:
1424 cpu_abort(env, "Unknown or invalid MMU model\n");
1425 return -1;
76a66253 1426 }
9a64fbe4
FB		 1427 break;
1428 case -2:
1429 /* Access rights violation */
8f793433
JM		 1430 env->exception_index = POWERPC_EXCP_ISI;
1431 env->error_code = 0x08000000;
9a64fbe4
FB		 1432 break;
1433 case -3:
76a66253 1434 /* No execute protection violation */
8f793433
JM		 1435 env->exception_index = POWERPC_EXCP_ISI;
1436 env->error_code = 0x10000000;
9a64fbe4
FB		 1437 break;
1438 case -4:
1439 /* Direct store exception */
1440 /* No code fetch is allowed in direct-store areas */
8f793433
JM		 1441 env->exception_index = POWERPC_EXCP_ISI;
1442 env->error_code = 0x10000000;
2be0071f 1443 break;
e1833e1f 1444#if defined(TARGET_PPC64)
2be0071f
FB		 1445 case -5:
1446 /* No match in segment table */
8f793433
JM		 1447 env->exception_index = POWERPC_EXCP_ISEG;
1448 env->error_code = 0;
9a64fbe4 1449 break;
e1833e1f 1450#endif
9a64fbe4
FB		 1451 }
1452 } else {
9a64fbe4
FB		 1453 switch (ret) {
1454 case -1:
76a66253 1455 /* No matches in page tables or TLB */
a750fc0b
JM		 1456 switch (env->mmu_model) {
1457 case POWERPC_MMU_SOFT_6xx:
76a66253 1458 if (rw == 1) {
8f793433
JM		 1459 env->exception_index = POWERPC_EXCP_DSTLB;
1460 env->error_code = 1 << 16;
76a66253 1461 } else {
8f793433
JM		 1462 env->exception_index = POWERPC_EXCP_DLTLB;
1463 env->error_code = 0;
76a66253
JM		 1464 }
1465 env->spr[SPR_DMISS] = address;
1466 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1467 tlb_miss:
8f793433 1468 env->error_code |= ctx.key << 19;
76a66253
JM		 1469 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1470 env->spr[SPR_HASH2] = ctx.pg_addr[1];
8f793433 1471 break;
7dbe11ac
JM		 1472 case POWERPC_MMU_SOFT_74xx:
1473 if (rw == 1) {
8f793433 1474 env->exception_index = POWERPC_EXCP_DSTLB;
7dbe11ac 1475 } else {
8f793433 1476 env->exception_index = POWERPC_EXCP_DLTLB;
7dbe11ac
JM		 1477 }
1478 tlb_miss_74xx:
1479 /* Implement LRU algorithm */
8f793433 1480 env->error_code = ctx.key << 19;
7dbe11ac
JM		 1481 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1482 ((env->last_way + 1) & (env->nb_ways - 1));
1483 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
7dbe11ac 1484 break;
a750fc0b
JM		 1485 case POWERPC_MMU_SOFT_4xx:
1486 case POWERPC_MMU_SOFT_4xx_Z:
8f793433
JM		 1487 env->exception_index = POWERPC_EXCP_DTLB;
1488 env->error_code = 0;
a8dea12f
JM		 1489 env->spr[SPR_40x_DEAR] = address;
1490 if (rw)
1491 env->spr[SPR_40x_ESR] = 0x00800000;
1492 else
1493 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef 1494 break;
a750fc0b 1495 case POWERPC_MMU_32B:
c55e9aef 1496#if defined(TARGET_PPC64)
a750fc0b 1497 case POWERPC_MMU_64B:
c55e9aef 1498#endif
8f793433
JM		 1499 env->exception_index = POWERPC_EXCP_DSI;
1500 env->error_code = 0;
1501 env->spr[SPR_DAR] = address;
1502 if (rw == 1)
1503 env->spr[SPR_DSISR] = 0x42000000;
1504 else
1505 env->spr[SPR_DSISR] = 0x40000000;
1506 break;
a750fc0b 1507 case POWERPC_MMU_601:
c55e9aef
JM		 1508 /* XXX: TODO */
1509 cpu_abort(env, "MMU model not implemented\n");
1510 return -1;
a750fc0b 1511 case POWERPC_MMU_BOOKE:
c55e9aef
JM		 1512 /* XXX: TODO */
1513 cpu_abort(env, "MMU model not implemented\n");
1514 return -1;
a750fc0b 1515 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1516 /* XXX: TODO */
1517 cpu_abort(env, "MMU model not implemented\n");
1518 return -1;
a750fc0b 1519 case POWERPC_MMU_REAL_4xx:
2662a059
JM		 1520 cpu_abort(env, "PowerPC 401 should never raise any MMU "
1521 "exceptions\n");
1522 return -1;
c55e9aef
JM		 1523 default:
1524 cpu_abort(env, "Unknown or invalid MMU model\n");
1525 return -1;
76a66253 1526 }
9a64fbe4
FB		 1527 break;
1528 case -2:
1529 /* Access rights violation */
8f793433
JM		 1530 env->exception_index = POWERPC_EXCP_DSI;
1531 env->error_code = 0;
1532 env->spr[SPR_DAR] = address;
1533 if (rw == 1)
1534 env->spr[SPR_DSISR] = 0x0A000000;
1535 else
1536 env->spr[SPR_DSISR] = 0x08000000;
9a64fbe4
FB		 1537 break;
1538 case -4:
1539 /* Direct store exception */
1540 switch (access_type) {
1541 case ACCESS_FLOAT:
1542 /* Floating point load/store */
8f793433
JM		 1543 env->exception_index = POWERPC_EXCP_ALIGN;
1544 env->error_code = POWERPC_EXCP_ALIGN_FP;
1545 env->spr[SPR_DAR] = address;
9a64fbe4
FB		 1546 break;
1547 case ACCESS_RES:
8f793433
JM		 1548 /* lwarx, ldarx or stwcx. */
1549 env->exception_index = POWERPC_EXCP_DSI;
1550 env->error_code = 0;
1551 env->spr[SPR_DAR] = address;
1552 if (rw == 1)
1553 env->spr[SPR_DSISR] = 0x06000000;
1554 else
1555 env->spr[SPR_DSISR] = 0x04000000;
9a64fbe4
FB		 1556 break;
1557 case ACCESS_EXT:
1558 /* eciwx or ecowx */
8f793433
JM		 1559 env->exception_index = POWERPC_EXCP_DSI;
1560 env->error_code = 0;
1561 env->spr[SPR_DAR] = address;
1562 if (rw == 1)
1563 env->spr[SPR_DSISR] = 0x06100000;
1564 else
1565 env->spr[SPR_DSISR] = 0x04100000;
9a64fbe4
FB		 1566 break;
1567 default:
76a66253 1568 printf("DSI: invalid exception (%d)\n", ret);
8f793433
JM		 1569 env->exception_index = POWERPC_EXCP_PROGRAM;
1570 env->error_code =
1571 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1572 env->spr[SPR_DAR] = address;
9a64fbe4
FB		 1573 break;
1574 }
fdabc366 1575 break;
e1833e1f 1576#if defined(TARGET_PPC64)
2be0071f
FB		 1577 case -5:
1578 /* No match in segment table */
8f793433
JM		 1579 env->exception_index = POWERPC_EXCP_DSEG;
1580 env->error_code = 0;
1581 env->spr[SPR_DAR] = address;
2be0071f 1582 break;
e1833e1f 1583#endif
9a64fbe4 1584 }
9a64fbe4
FB		 1585 }
1586#if 0
8f793433
JM		 1587 printf("%s: set exception to %d %02x\n", __func__,
1588 env->exception, env->error_code);
9a64fbe4 1589#endif
9a64fbe4
FB		 1590 ret = 1;
1591 }
76a66253 1592
9a64fbe4
FB		 1593 return ret;
1594}
1595
3fc6c082
FB		 1596/*****************************************************************************/
1597/* BATs management */
1598#if !defined(FLUSH_ALL_TLBS)
b068d6a7
JM		 1599static always_inline void do_invalidate_BAT (CPUPPCState *env,
1600 target_ulong BATu,
1601 target_ulong mask)
3fc6c082
FB		 1602{
1603 target_ulong base, end, page;
76a66253 1604
3fc6c082
FB		 1605 base = BATu & ~0x0001FFFF;
1606 end = base + mask + 0x00020000;
1607#if defined (DEBUG_BATS)
76a66253 1608 if (loglevel != 0) {
1b9eb036 1609 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
76a66253
JM		 1610 base, end, mask);
1611 }
3fc6c082
FB		 1612#endif
1613 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1614 tlb_flush_page(env, page);
1615#if defined (DEBUG_BATS)
1616 if (loglevel != 0)
1617 fprintf(logfile, "Flush done\n");
1618#endif
1619}
1620#endif
1621
b068d6a7
JM		 1622static always_inline void dump_store_bat (CPUPPCState *env, char ID,
1623 int ul, int nr, target_ulong value)
3fc6c082
FB		 1624{
1625#if defined (DEBUG_BATS)
1626 if (loglevel != 0) {
1b9eb036
JM		 1627 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1628 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
3fc6c082
FB		 1629 }
1630#endif
1631}
1632
1633target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1634{
1635 return env->IBAT[0][nr];
1636}
1637
1638target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1639{
1640 return env->IBAT[1][nr];
1641}
1642
1643void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1644{
1645 target_ulong mask;
1646
1647 dump_store_bat(env, 'I', 0, nr, value);
1648 if (env->IBAT[0][nr] != value) {
1649 mask = (value << 15) & 0x0FFE0000UL;
1650#if !defined(FLUSH_ALL_TLBS)
1651 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1652#endif
1653 /* When storing valid upper BAT, mask BEPI and BRPN
1654 * and invalidate all TLBs covered by this BAT
1655 */
1656 mask = (value << 15) & 0x0FFE0000UL;
1657 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1658 (value & ~0x0001FFFFUL & ~mask);
1659 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1660 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1661#if !defined(FLUSH_ALL_TLBS)
1662 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
76a66253 1663#else
3fc6c082
FB		 1664 tlb_flush(env, 1);
1665#endif
1666 }
1667}
1668
1669void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1670{
1671 dump_store_bat(env, 'I', 1, nr, value);
1672 env->IBAT[1][nr] = value;
1673}
1674
1675target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1676{
1677 return env->DBAT[0][nr];
1678}
1679
1680target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1681{
1682 return env->DBAT[1][nr];
1683}
1684
1685void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1686{
1687 target_ulong mask;
1688
1689 dump_store_bat(env, 'D', 0, nr, value);
1690 if (env->DBAT[0][nr] != value) {
1691 /* When storing valid upper BAT, mask BEPI and BRPN
1692 * and invalidate all TLBs covered by this BAT
1693 */
1694 mask = (value << 15) & 0x0FFE0000UL;
1695#if !defined(FLUSH_ALL_TLBS)
1696 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1697#endif
1698 mask = (value << 15) & 0x0FFE0000UL;
1699 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1700 (value & ~0x0001FFFFUL & ~mask);
1701 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1702 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1703#if !defined(FLUSH_ALL_TLBS)
1704 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1705#else
1706 tlb_flush(env, 1);
1707#endif
1708 }
1709}
1710
1711void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1712{
1713 dump_store_bat(env, 'D', 1, nr, value);
1714 env->DBAT[1][nr] = value;
1715}
1716
0a032cbe
JM		 1717/*****************************************************************************/
1718/* TLB management */
1719void ppc_tlb_invalidate_all (CPUPPCState *env)
1720{
daf4f96e
JM		 1721 switch (env->mmu_model) {
1722 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1723 case POWERPC_MMU_SOFT_74xx:
0a032cbe 1724 ppc6xx_tlb_invalidate_all(env);
daf4f96e
JM		 1725 break;
1726 case POWERPC_MMU_SOFT_4xx:
1727 case POWERPC_MMU_SOFT_4xx_Z:
0a032cbe 1728 ppc4xx_tlb_invalidate_all(env);
daf4f96e 1729 break;
7dbe11ac
JM		 1730 case POWERPC_MMU_REAL_4xx:
1731 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1732 break;
1733 case POWERPC_MMU_BOOKE:
1734 /* XXX: TODO */
1735 cpu_abort(env, "MMU model not implemented\n");
1736 break;
1737 case POWERPC_MMU_BOOKE_FSL:
1738 /* XXX: TODO */
1739 cpu_abort(env, "MMU model not implemented\n");
1740 break;
1741 case POWERPC_MMU_601:
1742 /* XXX: TODO */
1743 cpu_abort(env, "MMU model not implemented\n");
1744 break;
1745 case POWERPC_MMU_32B:
00af685f 1746#if defined(TARGET_PPC64)
7dbe11ac 1747 case POWERPC_MMU_64B:
00af685f 1748#endif /* defined(TARGET_PPC64) */
0a032cbe 1749 tlb_flush(env, 1);
daf4f96e 1750 break;
00af685f
JM		 1751 default:
1752 /* XXX: TODO */
12de9a39 1753 cpu_abort(env, "Unknown MMU model\n");
00af685f 1754 break;
0a032cbe
JM		 1755 }
1756}
1757
daf4f96e
JM		 1758void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1759{
1760#if !defined(FLUSH_ALL_TLBS)
1761 addr &= TARGET_PAGE_MASK;
1762 switch (env->mmu_model) {
1763 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1764 case POWERPC_MMU_SOFT_74xx:
daf4f96e
JM		 1765 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1766 if (env->id_tlbs == 1)
1767 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1768 break;
1769 case POWERPC_MMU_SOFT_4xx:
1770 case POWERPC_MMU_SOFT_4xx_Z:
1771 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1772 break;
7dbe11ac
JM		 1773 case POWERPC_MMU_REAL_4xx:
1774 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1775 break;
1776 case POWERPC_MMU_BOOKE:
1777 /* XXX: TODO */
1778 cpu_abort(env, "MMU model not implemented\n");
1779 break;
1780 case POWERPC_MMU_BOOKE_FSL:
1781 /* XXX: TODO */
1782 cpu_abort(env, "MMU model not implemented\n");
1783 break;
1784 case POWERPC_MMU_601:
1785 /* XXX: TODO */
1786 cpu_abort(env, "MMU model not implemented\n");
1787 break;
1788 case POWERPC_MMU_32B:
daf4f96e
JM		 1789 /* tlbie invalidate TLBs for all segments */
1790 addr &= ~((target_ulong)-1 << 28);
1791 /* XXX: this case should be optimized,
1792 * giving a mask to tlb_flush_page
1793 */
1794 tlb_flush_page(env, addr | (0x0 << 28));
1795 tlb_flush_page(env, addr | (0x1 << 28));
1796 tlb_flush_page(env, addr | (0x2 << 28));
1797 tlb_flush_page(env, addr | (0x3 << 28));
1798 tlb_flush_page(env, addr | (0x4 << 28));
1799 tlb_flush_page(env, addr | (0x5 << 28));
1800 tlb_flush_page(env, addr | (0x6 << 28));
1801 tlb_flush_page(env, addr | (0x7 << 28));
1802 tlb_flush_page(env, addr | (0x8 << 28));
1803 tlb_flush_page(env, addr | (0x9 << 28));
1804 tlb_flush_page(env, addr | (0xA << 28));
1805 tlb_flush_page(env, addr | (0xB << 28));
1806 tlb_flush_page(env, addr | (0xC << 28));
1807 tlb_flush_page(env, addr | (0xD << 28));
1808 tlb_flush_page(env, addr | (0xE << 28));
1809 tlb_flush_page(env, addr | (0xF << 28));
7dbe11ac 1810 break;
00af685f 1811#if defined(TARGET_PPC64)
7dbe11ac 1812 case POWERPC_MMU_64B:
7dbe11ac
JM		 1813 /* tlbie invalidate TLBs for all segments */
1814 /* XXX: given the fact that there are too many segments to invalidate,
00af685f 1815 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
7dbe11ac
JM		 1816 * we just invalidate all TLBs
1817 */
1818 tlb_flush(env, 1);
1819 break;
00af685f
JM		 1820#endif /* defined(TARGET_PPC64) */
1821 default:
1822 /* XXX: TODO */
12de9a39 1823 cpu_abort(env, "Unknown MMU model\n");
00af685f 1824 break;
daf4f96e
JM		 1825 }
1826#else
1827 ppc_tlb_invalidate_all(env);
1828#endif
1829}
1830
1831#if defined(TARGET_PPC64)
1832void ppc_slb_invalidate_all (CPUPPCState *env)
1833{
1834 /* XXX: TODO */
1835 tlb_flush(env, 1);
1836}
1837
1838void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
1839{
1840 /* XXX: TODO */
1841 tlb_flush(env, 1);
1842}
1843#endif
1844
3fc6c082
FB		 1845/*****************************************************************************/
1846/* Special registers manipulation */
d9bce9d9
JM		 1847#if defined(TARGET_PPC64)
1848target_ulong ppc_load_asr (CPUPPCState *env)
1849{
1850 return env->asr;
1851}
1852
1853void ppc_store_asr (CPUPPCState *env, target_ulong value)
1854{
1855 if (env->asr != value) {
1856 env->asr = value;
1857 tlb_flush(env, 1);
1858 }
1859}
1860#endif
1861
3fc6c082
FB		 1862target_ulong do_load_sdr1 (CPUPPCState *env)
1863{
1864 return env->sdr1;
1865}
1866
1867void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1868{
1869#if defined (DEBUG_MMU)
1870 if (loglevel != 0) {
1b9eb036 1871 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
3fc6c082
FB		 1872 }
1873#endif
1874 if (env->sdr1 != value) {
12de9a39
JM		 1875 /* XXX: for PowerPC 64, should check that the HTABSIZE value
1876 * is <= 28
1877 */
3fc6c082 1878 env->sdr1 = value;
76a66253 1879 tlb_flush(env, 1);
3fc6c082
FB		 1880 }
1881}
1882
12de9a39 1883#if 0 // Unused
3fc6c082
FB		 1884target_ulong do_load_sr (CPUPPCState *env, int srnum)
1885{
1886 return env->sr[srnum];
1887}
12de9a39 1888#endif
3fc6c082
FB		 1889
1890void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1891{
1892#if defined (DEBUG_MMU)
1893 if (loglevel != 0) {
1b9eb036
JM		 1894 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1895 __func__, srnum, value, env->sr[srnum]);
3fc6c082
FB		 1896 }
1897#endif
1898 if (env->sr[srnum] != value) {
1899 env->sr[srnum] = value;
1900#if !defined(FLUSH_ALL_TLBS) && 0
1901 {
1902 target_ulong page, end;
1903 /* Invalidate 256 MB of virtual memory */
1904 page = (16 << 20) * srnum;
1905 end = page + (16 << 20);
1906 for (; page != end; page += TARGET_PAGE_SIZE)
1907 tlb_flush_page(env, page);
1908 }
1909#else
76a66253 1910 tlb_flush(env, 1);
3fc6c082
FB		 1911#endif
1912 }
1913}
76a66253 1914#endif /* !defined (CONFIG_USER_ONLY) */
3fc6c082 1915
bfa1e5cf 1916target_ulong ppc_load_xer (CPUPPCState *env)
79aceca5
FB		 1917{
1918 return (xer_so << XER_SO) |
1919 (xer_ov << XER_OV) |
1920 (xer_ca << XER_CA) |
3fc6c082
FB		 1921 (xer_bc << XER_BC) |
1922 (xer_cmp << XER_CMP);
79aceca5
FB		 1923}
1924
bfa1e5cf 1925void ppc_store_xer (CPUPPCState *env, target_ulong value)
79aceca5
FB		 1926{
1927 xer_so = (value >> XER_SO) & 0x01;
1928 xer_ov = (value >> XER_OV) & 0x01;
1929 xer_ca = (value >> XER_CA) & 0x01;
3fc6c082 1930 xer_cmp = (value >> XER_CMP) & 0xFF;
d9bce9d9 1931 xer_bc = (value >> XER_BC) & 0x7F;
79aceca5
FB		 1932}
1933
76a66253 1934/* Swap temporary saved registers with GPRs */
b068d6a7 1935static always_inline void swap_gpr_tgpr (CPUPPCState *env)
79aceca5 1936{
76a66253
JM		 1937 ppc_gpr_t tmp;
1938
1939 tmp = env->gpr[0];
1940 env->gpr[0] = env->tgpr[0];
1941 env->tgpr[0] = tmp;
1942 tmp = env->gpr[1];
1943 env->gpr[1] = env->tgpr[1];
1944 env->tgpr[1] = tmp;
1945 tmp = env->gpr[2];
1946 env->gpr[2] = env->tgpr[2];
1947 env->tgpr[2] = tmp;
1948 tmp = env->gpr[3];
1949 env->gpr[3] = env->tgpr[3];
1950 env->tgpr[3] = tmp;
79aceca5
FB		 1951}
1952
76a66253
JM		 1953/* GDBstub can read and write MSR... */
1954target_ulong do_load_msr (CPUPPCState *env)
79aceca5 1955{
76a66253
JM		 1956 return
1957#if defined (TARGET_PPC64)
d9bce9d9
JM		 1958 ((target_ulong)msr_sf << MSR_SF) |
1959 ((target_ulong)msr_isf << MSR_ISF) |
1960 ((target_ulong)msr_hv << MSR_HV) |
76a66253 1961#endif
d9bce9d9
JM		 1962 ((target_ulong)msr_ucle << MSR_UCLE) |
1963 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1964 ((target_ulong)msr_ap << MSR_AP) |
1965 ((target_ulong)msr_sa << MSR_SA) |
1966 ((target_ulong)msr_key << MSR_KEY) |
25ba3a68 1967 ((target_ulong)msr_pow << MSR_POW) |
d26bfc9a 1968 ((target_ulong)msr_tgpr << MSR_TGPR) | /* TGPR / CE */
d9bce9d9
JM		 1969 ((target_ulong)msr_ile << MSR_ILE) |
1970 ((target_ulong)msr_ee << MSR_EE) |
1971 ((target_ulong)msr_pr << MSR_PR) |
1972 ((target_ulong)msr_fp << MSR_FP) |
1973 ((target_ulong)msr_me << MSR_ME) |
1974 ((target_ulong)msr_fe0 << MSR_FE0) |
1975 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1976 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1977 ((target_ulong)msr_fe1 << MSR_FE1) |
1978 ((target_ulong)msr_al << MSR_AL) |
25ba3a68
JM		 1979 ((target_ulong)msr_ep << MSR_EP) |
1980 ((target_ulong)msr_ir << MSR_IR) |
1981 ((target_ulong)msr_dr << MSR_DR) |
1982 ((target_ulong)msr_pe << MSR_PE) |
d9bce9d9
JM		 1983 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1984 ((target_ulong)msr_ri << MSR_RI) |
1985 ((target_ulong)msr_le << MSR_LE);
3fc6c082
FB		 1986}
1987
a97fed52 1988int do_store_msr (CPUPPCState *env, target_ulong value)
313adae9 1989{
50443c98
FB		 1990 int enter_pm;
1991
3fc6c082
FB		 1992 value &= env->msr_mask;
1993 if (((value >> MSR_IR) & 1) != msr_ir ||
1994 ((value >> MSR_DR) & 1) != msr_dr) {
76a66253 1995 /* Flush all tlb when changing translation mode */
d094807b 1996 tlb_flush(env, 1);
3fc6c082 1997 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
a541f297 1998 }
4e80effc 1999#if !defined (CONFIG_USER_ONLY)
d26bfc9a
JM		 2000 if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
2001 ((value >> MSR_TGPR) & 1) != msr_tgpr)) {
2002 /* Swap temporary saved registers with GPRs */
2003 swap_gpr_tgpr(env);
76a66253 2004 }
4e80effc
JM		 2005 if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
2006 /* Change the exception prefix on PowerPC 601 */
2007 env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
2008 }
2009#endif
76a66253
JM		 2010#if defined (TARGET_PPC64)
2011 msr_sf = (value >> MSR_SF) & 1;
2012 msr_isf = (value >> MSR_ISF) & 1;
2013 msr_hv = (value >> MSR_HV) & 1;
2014#endif
2015 msr_ucle = (value >> MSR_UCLE) & 1;
2016 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
2017 msr_ap = (value >> MSR_AP) & 1;
2018 msr_sa = (value >> MSR_SA) & 1;
2019 msr_key = (value >> MSR_KEY) & 1;
25ba3a68 2020 msr_pow = (value >> MSR_POW) & 1;
d26bfc9a 2021 msr_tgpr = (value >> MSR_TGPR) & 1; /* TGPR / CE */
76a66253
JM		 2022 msr_ile = (value >> MSR_ILE) & 1;
2023 msr_ee = (value >> MSR_EE) & 1;
2024 msr_pr = (value >> MSR_PR) & 1;
2025 msr_fp = (value >> MSR_FP) & 1;
2026 msr_me = (value >> MSR_ME) & 1;
2027 msr_fe0 = (value >> MSR_FE0) & 1;
2028 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
2029 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
2030 msr_fe1 = (value >> MSR_FE1) & 1;
2031 msr_al = (value >> MSR_AL) & 1;
25ba3a68
JM		 2032 msr_ep = (value >> MSR_EP) & 1;
2033 msr_ir = (value >> MSR_IR) & 1;
2034 msr_dr = (value >> MSR_DR) & 1;
2035 msr_pe = (value >> MSR_PE) & 1;
76a66253
JM		 2036 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
2037 msr_ri = (value >> MSR_RI) & 1;
2038 msr_le = (value >> MSR_LE) & 1;
3fc6c082 2039 do_compute_hflags(env);
50443c98
FB		 2040
2041 enter_pm = 0;
a750fc0b
JM		 2042 switch (env->excp_model) {
2043 case POWERPC_EXCP_603:
2044 case POWERPC_EXCP_603E:
2045 case POWERPC_EXCP_G2:
d9bce9d9
JM		 2046 /* Don't handle SLEEP mode: we should disable all clocks...
2047 * No dynamic power-management.
2048 */
2049 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
2050 enter_pm = 1;
2051 break;
a750fc0b 2052 case POWERPC_EXCP_604:
d9bce9d9
JM		 2053 if (msr_pow == 1)
2054 enter_pm = 1;
2055 break;
a750fc0b 2056 case POWERPC_EXCP_7x0:
76a66253 2057 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
50443c98
FB		 2058 enter_pm = 1;
2059 break;
2060 default:
2061 break;
2062 }
a97fed52
JM		 2063
2064 return enter_pm;
3fc6c082
FB		 2065}
2066
d9bce9d9 2067#if defined(TARGET_PPC64)
a97fed52 2068int ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
d9bce9d9 2069{
a97fed52
JM		 2070 return do_store_msr(env, (do_load_msr(env) & ~0xFFFFFFFFULL) |
2071 (value & 0xFFFFFFFF));
d9bce9d9
JM		 2072}
2073#endif
2074
76a66253 2075void do_compute_hflags (CPUPPCState *env)
3fc6c082 2076{
76a66253 2077 /* Compute current hflags */
4296f459 2078 env->hflags = (msr_vr << MSR_VR) |
c62db105
JM		 2079 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
2080 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
2081 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
76a66253 2082#if defined (TARGET_PPC64)
4296f459
JM		 2083 env->hflags |= msr_cm << MSR_CM;
2084 env->hflags |= (uint64_t)msr_sf << MSR_SF;
2085 env->hflags |= (uint64_t)msr_hv << MSR_HV;
6ebbf390
JM		 2086 /* Precompute MMU index */
2087 if (msr_pr == 0 && msr_hv == 1)
2088 env->mmu_idx = 2;
2089 else
4b3686fa 2090#endif
6ebbf390 2091 env->mmu_idx = 1 - msr_pr;
3fc6c082
FB		 2092}
2093
2094/*****************************************************************************/
2095/* Exception processing */
18fba28c 2096#if defined (CONFIG_USER_ONLY)
9a64fbe4 2097void do_interrupt (CPUState *env)
79aceca5 2098{
e1833e1f
JM		 2099 env->exception_index = POWERPC_EXCP_NONE;
2100 env->error_code = 0;
18fba28c 2101}
47103572 2102
e9df014c 2103void ppc_hw_interrupt (CPUState *env)
47103572 2104{
e1833e1f
JM		 2105 env->exception_index = POWERPC_EXCP_NONE;
2106 env->error_code = 0;
47103572 2107}
76a66253 2108#else /* defined (CONFIG_USER_ONLY) */
36081602 2109static void dump_syscall (CPUState *env)
d094807b 2110{
d9bce9d9 2111 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1b9eb036 2112 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
d094807b
FB		 2113 env->gpr[0], env->gpr[3], env->gpr[4],
2114 env->gpr[5], env->gpr[6], env->nip);
2115}
2116
e1833e1f
JM		 2117/* Note that this function should be greatly optimized
2118 * when called with a constant excp, from ppc_hw_interrupt
2119 */
2120static always_inline void powerpc_excp (CPUState *env,
2121 int excp_model, int excp)
18fba28c 2122{
e1833e1f
JM		 2123 target_ulong msr, vector;
2124 int srr0, srr1, asrr0, asrr1;
79aceca5 2125
b769d8fe 2126 if (loglevel & CPU_LOG_INT) {
1b9eb036
JM		 2127 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
2128 env->nip, excp, env->error_code);
b769d8fe 2129 }
e1833e1f
JM		 2130 msr = do_load_msr(env);
2131 srr0 = SPR_SRR0;
2132 srr1 = SPR_SRR1;
2133 asrr0 = -1;
2134 asrr1 = -1;
2135 msr &= ~((target_ulong)0x783F0000);
9a64fbe4 2136 switch (excp) {
e1833e1f
JM		 2137 case POWERPC_EXCP_NONE:
2138 /* Should never happen */
2139 return;
2140 case POWERPC_EXCP_CRITICAL: /* Critical input */
2141 msr_ri = 0; /* XXX: check this */
2142 switch (excp_model) {
a750fc0b 2143 case POWERPC_EXCP_40x:
e1833e1f
JM		 2144 srr0 = SPR_40x_SRR2;
2145 srr1 = SPR_40x_SRR3;
c62db105 2146 break;
a750fc0b 2147 case POWERPC_EXCP_BOOKE:
e1833e1f
JM		 2148 srr0 = SPR_BOOKE_CSRR0;
2149 srr1 = SPR_BOOKE_CSRR1;
c62db105 2150 break;
e1833e1f 2151 case POWERPC_EXCP_G2:
c62db105 2152 break;
e1833e1f
JM		 2153 default:
2154 goto excp_invalid;
2be0071f 2155 }
9a64fbe4 2156 goto store_next;
e1833e1f
JM		 2157 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2158 if (msr_me == 0) {
2159 /* Machine check exception is not enabled */
2160 /* XXX: we may just stop the processor here, to allow debugging */
2161 excp = POWERPC_EXCP_RESET;
2162 goto excp_reset;
2163 }
2164 msr_ri = 0;
2165 msr_me = 0;
2166#if defined(TARGET_PPC64H)
2167 msr_hv = 1;
2168#endif
2169 /* XXX: should also have something loaded in DAR / DSISR */
2170 switch (excp_model) {
a750fc0b 2171 case POWERPC_EXCP_40x:
e1833e1f
JM		 2172 srr0 = SPR_40x_SRR2;
2173 srr1 = SPR_40x_SRR3;
c62db105 2174 break;
a750fc0b 2175 case POWERPC_EXCP_BOOKE:
e1833e1f
JM		 2176 srr0 = SPR_BOOKE_MCSRR0;
2177 srr1 = SPR_BOOKE_MCSRR1;
2178 asrr0 = SPR_BOOKE_CSRR0;
2179 asrr1 = SPR_BOOKE_CSRR1;
c62db105
JM		 2180 break;
2181 default:
2182 break;
2be0071f 2183 }
e1833e1f
JM		 2184 goto store_next;
2185 case POWERPC_EXCP_DSI: /* Data storage exception */
a541f297 2186#if defined (DEBUG_EXCEPTIONS)
4a057712 2187 if (loglevel != 0) {
1b9eb036
JM		 2188 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
2189 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
76a66253 2190 }
e1833e1f
JM		 2191#endif
2192 msr_ri = 0;
2193#if defined(TARGET_PPC64H)
2194 if (lpes1 == 0)
2195 msr_hv = 1;
a541f297
FB		 2196#endif
2197 goto store_next;
e1833e1f 2198 case POWERPC_EXCP_ISI: /* Instruction storage exception */
a541f297 2199#if defined (DEBUG_EXCEPTIONS)
76a66253 2200 if (loglevel != 0) {
1b9eb036
JM		 2201 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
2202 "\n", msr, env->nip);
76a66253 2203 }
a541f297 2204#endif
e1833e1f
JM		 2205 msr_ri = 0;
2206#if defined(TARGET_PPC64H)
2207 if (lpes1 == 0)
2208 msr_hv = 1;
2209#endif
2210 msr |= env->error_code;
9a64fbe4 2211 goto store_next;
e1833e1f
JM		 2212 case POWERPC_EXCP_EXTERNAL: /* External input */
2213 msr_ri = 0;
2214#if defined(TARGET_PPC64H)
2215 if (lpes0 == 1)
2216 msr_hv = 1;
2217#endif
9a64fbe4 2218 goto store_next;
e1833e1f
JM		 2219 case POWERPC_EXCP_ALIGN: /* Alignment exception */
2220 msr_ri = 0;
2221#if defined(TARGET_PPC64H)
2222 if (lpes1 == 0)
2223 msr_hv = 1;
2224#endif
2225 /* XXX: this is false */
2226 /* Get rS/rD and rA from faulting opcode */
2227 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
9a64fbe4 2228 goto store_current;
e1833e1f 2229 case POWERPC_EXCP_PROGRAM: /* Program exception */
9a64fbe4 2230 switch (env->error_code & ~0xF) {
e1833e1f
JM		 2231 case POWERPC_EXCP_FP:
2232 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
9a64fbe4 2233#if defined (DEBUG_EXCEPTIONS)
4a057712 2234 if (loglevel != 0) {
a496775f
JM		 2235 fprintf(logfile, "Ignore floating point exception\n");
2236 }
9a64fbe4
FB		 2237#endif
2238 return;
76a66253 2239 }
e1833e1f
JM		 2240 msr_ri = 0;
2241#if defined(TARGET_PPC64H)
2242 if (lpes1 == 0)
2243 msr_hv = 1;
2244#endif
9a64fbe4
FB		 2245 msr |= 0x00100000;
2246 /* Set FX */
2247 env->fpscr[7] |= 0x8;
2248 /* Finally, update FEX */
2249 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
2250 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
2251 env->fpscr[7] |= 0x4;
e1833e1f
JM		 2252 if (msr_fe0 != msr_fe1) {
2253 msr |= 0x00010000;
2254 goto store_current;
2255 }
76a66253 2256 break;
e1833e1f 2257 case POWERPC_EXCP_INVAL:
a496775f 2258#if defined (DEBUG_EXCEPTIONS)
4a057712 2259 if (loglevel != 0) {
a496775f
JM		 2260 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
2261 env->nip);
2262 }
e1833e1f
JM		 2263#endif
2264 msr_ri = 0;
2265#if defined(TARGET_PPC64H)
2266 if (lpes1 == 0)
2267 msr_hv = 1;
a496775f 2268#endif
9a64fbe4 2269 msr |= 0x00080000;
76a66253 2270 break;
e1833e1f
JM		 2271 case POWERPC_EXCP_PRIV:
2272 msr_ri = 0;
2273#if defined(TARGET_PPC64H)
2274 if (lpes1 == 0)
2275 msr_hv = 1;
2276#endif
9a64fbe4 2277 msr |= 0x00040000;
76a66253 2278 break;
e1833e1f
JM		 2279 case POWERPC_EXCP_TRAP:
2280 msr_ri = 0;
2281#if defined(TARGET_PPC64H)
2282 if (lpes1 == 0)
2283 msr_hv = 1;
2284#endif
9a64fbe4
FB		 2285 msr |= 0x00020000;
2286 break;
2287 default:
2288 /* Should never occur */
e1833e1f
JM		 2289 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2290 env->error_code);
76a66253
JM		 2291 break;
2292 }
9a64fbe4 2293 goto store_next;
e1833e1f
JM		 2294 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2295 msr_ri = 0;
2296#if defined(TARGET_PPC64H)
2297 if (lpes1 == 0)
2298 msr_hv = 1;
2299#endif
2300 goto store_current;
2301 case POWERPC_EXCP_SYSCALL: /* System call exception */
d094807b
FB		 2302 /* NOTE: this is a temporary hack to support graphics OSI
2303 calls from the MOL driver */
e1833e1f 2304 /* XXX: To be removed */
d094807b
FB		 2305 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2306 env->osi_call) {
2307 if (env->osi_call(env) != 0)
2308 return;
2309 }
b769d8fe 2310 if (loglevel & CPU_LOG_INT) {
d094807b 2311 dump_syscall(env);
b769d8fe 2312 }
e1833e1f
JM		 2313 msr_ri = 0;
2314#if defined(TARGET_PPC64H)
2315 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2316 msr_hv = 1;
2317#endif
2318 goto store_next;
2319 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2320 msr_ri = 0;
2321 goto store_current;
2322 case POWERPC_EXCP_DECR: /* Decrementer exception */
2323 msr_ri = 0;
2324#if defined(TARGET_PPC64H)
2325 if (lpes1 == 0)
2326 msr_hv = 1;
2327#endif
2328 goto store_next;
2329 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2330 /* FIT on 4xx */
2331#if defined (DEBUG_EXCEPTIONS)
2332 if (loglevel != 0)
2333 fprintf(logfile, "FIT exception\n");
2334#endif
2335 msr_ri = 0; /* XXX: check this */
9a64fbe4 2336 goto store_next;
e1833e1f
JM		 2337 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2338#if defined (DEBUG_EXCEPTIONS)
2339 if (loglevel != 0)
2340 fprintf(logfile, "WDT exception\n");
2341#endif
2342 switch (excp_model) {
2343 case POWERPC_EXCP_BOOKE:
2344 srr0 = SPR_BOOKE_CSRR0;
2345 srr1 = SPR_BOOKE_CSRR1;
2346 break;
2347 default:
2348 break;
2349 }
2350 msr_ri = 0; /* XXX: check this */
2be0071f 2351 goto store_next;
e1833e1f
JM		 2352 case POWERPC_EXCP_DTLB: /* Data TLB error */
2353 msr_ri = 0; /* XXX: check this */
2354 goto store_next;
2355 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2356 msr_ri = 0; /* XXX: check this */
2357 goto store_next;
2358 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2359 switch (excp_model) {
2360 case POWERPC_EXCP_BOOKE:
2361 srr0 = SPR_BOOKE_DSRR0;
2362 srr1 = SPR_BOOKE_DSRR1;
2363 asrr0 = SPR_BOOKE_CSRR0;
2364 asrr1 = SPR_BOOKE_CSRR1;
2365 break;
2366 default:
2367 break;
2368 }
2be0071f 2369 /* XXX: TODO */
e1833e1f 2370 cpu_abort(env, "Debug exception is not implemented yet !\n");
2be0071f 2371 goto store_next;
e1833e1f
JM		 2372#if defined(TARGET_PPCEMB)
2373 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2374 msr_ri = 0; /* XXX: check this */
2375 goto store_current;
2376 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2be0071f 2377 /* XXX: TODO */
e1833e1f 2378 cpu_abort(env, "Embedded floating point data exception "
2be0071f
FB		 2379 "is not implemented yet !\n");
2380 goto store_next;
e1833e1f 2381 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2be0071f 2382 /* XXX: TODO */
e1833e1f
JM		 2383 cpu_abort(env, "Embedded floating point round exception "
2384 "is not implemented yet !\n");
9a64fbe4 2385 goto store_next;
e1833e1f
JM		 2386 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2387 msr_ri = 0;
2be0071f
FB		 2388 /* XXX: TODO */
2389 cpu_abort(env,
e1833e1f 2390 "Performance counter exception is not implemented yet !\n");
9a64fbe4 2391 goto store_next;
e1833e1f 2392 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
76a66253 2393 /* XXX: TODO */
e1833e1f
JM		 2394 cpu_abort(env,
2395 "Embedded doorbell interrupt is not implemented yet !\n");
2be0071f 2396 goto store_next;
e1833e1f
JM		 2397 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2398 switch (excp_model) {
2399 case POWERPC_EXCP_BOOKE:
2400 srr0 = SPR_BOOKE_CSRR0;
2401 srr1 = SPR_BOOKE_CSRR1;
a750fc0b 2402 break;
2be0071f 2403 default:
2be0071f
FB		 2404 break;
2405 }
e1833e1f
JM		 2406 /* XXX: TODO */
2407 cpu_abort(env, "Embedded doorbell critical interrupt "
2408 "is not implemented yet !\n");
2409 goto store_next;
2410#endif /* defined(TARGET_PPCEMB) */
2411 case POWERPC_EXCP_RESET: /* System reset exception */
2412 msr_ri = 0;
2413#if defined(TARGET_PPC64H)
2414 msr_hv = 1;
2415#endif
2416 excp_reset:
2417 goto store_next;
2418#if defined(TARGET_PPC64)
2419 case POWERPC_EXCP_DSEG: /* Data segment exception */
2420 msr_ri = 0;
2421#if defined(TARGET_PPC64H)
2422 if (lpes1 == 0)
2423 msr_hv = 1;
2424#endif
e1833e1f
JM		 2425 goto store_next;
2426 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2427 msr_ri = 0;
2428#if defined(TARGET_PPC64H)
2429 if (lpes1 == 0)
2430 msr_hv = 1;
2431#endif
e1833e1f
JM		 2432 goto store_next;
2433#endif /* defined(TARGET_PPC64) */
2434#if defined(TARGET_PPC64H)
2435 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2436 srr0 = SPR_HSRR0;
2437 srr1 = SPR_HSSR1;
2438 msr_hv = 1;
2439 goto store_next;
2440#endif
2441 case POWERPC_EXCP_TRACE: /* Trace exception */
2442 msr_ri = 0;
2443#if defined(TARGET_PPC64H)
2444 if (lpes1 == 0)
2445 msr_hv = 1;
2446#endif
2447 goto store_next;
2448#if defined(TARGET_PPC64H)
2449 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2450 srr0 = SPR_HSRR0;
2451 srr1 = SPR_HSSR1;
2452 msr_hv = 1;
2453 goto store_next;
2454 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2455 srr0 = SPR_HSRR0;
2456 srr1 = SPR_HSSR1;
2457 msr_hv = 1;
2458 /* XXX: TODO */
2459 cpu_abort(env, "Hypervisor instruction storage exception "
2460 "is not implemented yet !\n");
2461 goto store_next;
2462 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2463 srr0 = SPR_HSRR0;
2464 srr1 = SPR_HSSR1;
2465 msr_hv = 1;
2466 goto store_next;
2467 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2468 srr0 = SPR_HSRR0;
2469 srr1 = SPR_HSSR1;
2470 msr_hv = 1;
2471 goto store_next;
2472#endif /* defined(TARGET_PPC64H) */
2473 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2474 msr_ri = 0;
2475#if defined(TARGET_PPC64H)
2476 if (lpes1 == 0)
2477 msr_hv = 1;
2478#endif
2479 goto store_current;
2480 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
a496775f 2481#if defined (DEBUG_EXCEPTIONS)
e1833e1f
JM		 2482 if (loglevel != 0)
2483 fprintf(logfile, "PIT exception\n");
2484#endif
2485 msr_ri = 0; /* XXX: check this */
2486 goto store_next;
2487 case POWERPC_EXCP_IO: /* IO error exception */
2488 /* XXX: TODO */
2489 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2490 goto store_next;
2491 case POWERPC_EXCP_RUNM: /* Run mode exception */
2492 /* XXX: TODO */
2493 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2494 goto store_next;
2495 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2496 /* XXX: TODO */
2497 cpu_abort(env, "602 emulation trap exception "
2498 "is not implemented yet !\n");
2499 goto store_next;
2500 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2501 msr_ri = 0; /* XXX: check this */
2502#if defined(TARGET_PPC64H) /* XXX: check this */
2503 if (lpes1 == 0)
2504 msr_hv = 1;
a496775f 2505#endif
e1833e1f 2506 switch (excp_model) {
a750fc0b
JM		 2507 case POWERPC_EXCP_602:
2508 case POWERPC_EXCP_603:
2509 case POWERPC_EXCP_603E:
2510 case POWERPC_EXCP_G2:
e1833e1f 2511 goto tlb_miss_tgpr;
a750fc0b 2512 case POWERPC_EXCP_7x5:
76a66253 2513 goto tlb_miss;
7dbe11ac
JM		 2514 case POWERPC_EXCP_74xx:
2515 goto tlb_miss_74xx;
2be0071f 2516 default:
e1833e1f 2517 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2be0071f
FB		 2518 break;
2519 }
e1833e1f
JM		 2520 break;
2521 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2522 msr_ri = 0; /* XXX: check this */
2523#if defined(TARGET_PPC64H) /* XXX: check this */
2524 if (lpes1 == 0)
2525 msr_hv = 1;
a496775f 2526#endif
e1833e1f 2527 switch (excp_model) {
a750fc0b
JM		 2528 case POWERPC_EXCP_602:
2529 case POWERPC_EXCP_603:
2530 case POWERPC_EXCP_603E:
2531 case POWERPC_EXCP_G2:
e1833e1f 2532 goto tlb_miss_tgpr;
a750fc0b 2533 case POWERPC_EXCP_7x5:
76a66253 2534 goto tlb_miss;
7dbe11ac
JM		 2535 case POWERPC_EXCP_74xx:
2536 goto tlb_miss_74xx;
2be0071f 2537 default:
e1833e1f 2538 cpu_abort(env, "Invalid data load TLB miss exception\n");
2be0071f
FB		 2539 break;
2540 }
e1833e1f
JM		 2541 break;
2542 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2543 msr_ri = 0; /* XXX: check this */
2544#if defined(TARGET_PPC64H) /* XXX: check this */
2545 if (lpes1 == 0)
2546 msr_hv = 1;
2547#endif
2548 switch (excp_model) {
a750fc0b
JM		 2549 case POWERPC_EXCP_602:
2550 case POWERPC_EXCP_603:
2551 case POWERPC_EXCP_603E:
2552 case POWERPC_EXCP_G2:
e1833e1f 2553 tlb_miss_tgpr:
76a66253
JM		 2554 /* Swap temporary saved registers with GPRs */
2555 swap_gpr_tgpr(env);
2556 msr_tgpr = 1;
e1833e1f
JM		 2557 goto tlb_miss;
2558 case POWERPC_EXCP_7x5:
2559 tlb_miss:
2be0071f
FB		 2560#if defined (DEBUG_SOFTWARE_TLB)
2561 if (loglevel != 0) {
76a66253
JM		 2562 const unsigned char *es;
2563 target_ulong *miss, *cmp;
2564 int en;
1e6784f9 2565 if (excp == POWERPC_EXCP_IFTLB) {
76a66253
JM		 2566 es = "I";
2567 en = 'I';
2568 miss = &env->spr[SPR_IMISS];
2569 cmp = &env->spr[SPR_ICMP];
2570 } else {
1e6784f9 2571 if (excp == POWERPC_EXCP_DLTLB)
76a66253
JM		 2572 es = "DL";
2573 else
2574 es = "DS";
2575 en = 'D';
2576 miss = &env->spr[SPR_DMISS];
2577 cmp = &env->spr[SPR_DCMP];
2578 }
1b9eb036 2579 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
4a057712 2580 " H1 " ADDRX " H2 " ADDRX " %08x\n",
1b9eb036 2581 es, en, *miss, en, *cmp,
76a66253 2582 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2be0071f
FB		 2583 env->error_code);
2584 }
9a64fbe4 2585#endif
2be0071f
FB		 2586 msr |= env->crf[0] << 28;
2587 msr |= env->error_code; /* key, D/I, S/L bits */
2588 /* Set way using a LRU mechanism */
76a66253 2589 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
c62db105 2590 break;
7dbe11ac
JM		 2591 case POWERPC_EXCP_74xx:
2592 tlb_miss_74xx:
2593#if defined (DEBUG_SOFTWARE_TLB)
2594 if (loglevel != 0) {
2595 const unsigned char *es;
2596 target_ulong *miss, *cmp;
2597 int en;
2598 if (excp == POWERPC_EXCP_IFTLB) {
2599 es = "I";
2600 en = 'I';
2601 miss = &env->spr[SPR_IMISS];
2602 cmp = &env->spr[SPR_ICMP];
2603 } else {
2604 if (excp == POWERPC_EXCP_DLTLB)
2605 es = "DL";
2606 else
2607 es = "DS";
2608 en = 'D';
2609 miss = &env->spr[SPR_TLBMISS];
2610 cmp = &env->spr[SPR_PTEHI];
2611 }
2612 fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2613 " %08x\n",
2614 es, en, *miss, en, *cmp, env->error_code);
2615 }
2616#endif
2617 msr |= env->error_code; /* key bit */
2618 break;
2be0071f 2619 default:
e1833e1f 2620 cpu_abort(env, "Invalid data store TLB miss exception\n");
2be0071f
FB		 2621 break;
2622 }
e1833e1f
JM		 2623 goto store_next;
2624 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2625 /* XXX: TODO */
2626 cpu_abort(env, "Floating point assist exception "
2627 "is not implemented yet !\n");
2628 goto store_next;
2629 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2630 /* XXX: TODO */
2631 cpu_abort(env, "IABR exception is not implemented yet !\n");
2632 goto store_next;
2633 case POWERPC_EXCP_SMI: /* System management interrupt */
2634 /* XXX: TODO */
2635 cpu_abort(env, "SMI exception is not implemented yet !\n");
2636 goto store_next;
2637 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2638 /* XXX: TODO */
2639 cpu_abort(env, "Thermal management exception "
2640 "is not implemented yet !\n");
2641 goto store_next;
2642 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2643 msr_ri = 0;
2644#if defined(TARGET_PPC64H)
2645 if (lpes1 == 0)
2646 msr_hv = 1;
2647#endif
2648 /* XXX: TODO */
2649 cpu_abort(env,
2650 "Performance counter exception is not implemented yet !\n");
2651 goto store_next;
2652 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2653 /* XXX: TODO */
2654 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2655 goto store_next;
2656 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2657 /* XXX: TODO */
2658 cpu_abort(env,
2659 "970 soft-patch exception is not implemented yet !\n");
2660 goto store_next;
2661 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2662 /* XXX: TODO */
2663 cpu_abort(env,
2664 "970 maintenance exception is not implemented yet !\n");
2665 goto store_next;
2be0071f 2666 default:
e1833e1f
JM		 2667 excp_invalid:
2668 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2669 break;
9a64fbe4 2670 store_current:
2be0071f 2671 /* save current instruction location */
e1833e1f 2672 env->spr[srr0] = env->nip - 4;
9a64fbe4
FB		 2673 break;
2674 store_next:
2be0071f 2675 /* save next instruction location */
e1833e1f 2676 env->spr[srr0] = env->nip;
9a64fbe4
FB		 2677 break;
2678 }
e1833e1f
JM		 2679 /* Save MSR */
2680 env->spr[srr1] = msr;
2681 /* If any alternate SRR register are defined, duplicate saved values */
2682 if (asrr0 != -1)
2683 env->spr[asrr0] = env->spr[srr0];
2684 if (asrr1 != -1)
2685 env->spr[asrr1] = env->spr[srr1];
2be0071f 2686 /* If we disactivated any translation, flush TLBs */
e1833e1f 2687 if (msr_ir || msr_dr)
2be0071f 2688 tlb_flush(env, 1);
9a64fbe4 2689 /* reload MSR with correct bits */
9a64fbe4
FB		 2690 msr_ee = 0;
2691 msr_pr = 0;
2692 msr_fp = 0;
2693 msr_fe0 = 0;
2694 msr_se = 0;
2695 msr_be = 0;
2696 msr_fe1 = 0;
2697 msr_ir = 0;
2698 msr_dr = 0;
e1833e1f
JM		 2699#if 0 /* Fix this: not on all targets */
2700 msr_pmm = 0;
2701#endif
9a64fbe4 2702 msr_le = msr_ile;
e1833e1f
JM		 2703 do_compute_hflags(env);
2704 /* Jump to handler */
2705 vector = env->excp_vectors[excp];
2706 if (vector == (target_ulong)-1) {
2707 cpu_abort(env, "Raised an exception without defined vector %d\n",
2708 excp);
2709 }
2710 vector |= env->excp_prefix;
c62db105 2711#if defined(TARGET_PPC64)
e1833e1f
JM		 2712 if (excp_model == POWERPC_EXCP_BOOKE) {
2713 msr_cm = msr_icm;
2714 if (!msr_cm)
2715 vector = (uint32_t)vector;
c62db105
JM		 2716 } else {
2717 msr_sf = msr_isf;
e1833e1f
JM		 2718 if (!msr_sf)
2719 vector = (uint32_t)vector;
c62db105 2720 }
e1833e1f
JM		 2721#endif
2722 env->nip = vector;
2723 /* Reset exception state */
2724 env->exception_index = POWERPC_EXCP_NONE;
2725 env->error_code = 0;
fb0eaffc 2726}
47103572 2727
e1833e1f 2728void do_interrupt (CPUState *env)
47103572 2729{
e1833e1f
JM		 2730 powerpc_excp(env, env->excp_model, env->exception_index);
2731}
47103572 2732
e1833e1f
JM		 2733void ppc_hw_interrupt (CPUPPCState *env)
2734{
a496775f
JM		 2735#if 1
2736 if (loglevel & CPU_LOG_INT) {
2737 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2738 __func__, env, env->pending_interrupts,
2739 env->interrupt_request, msr_me, msr_ee);
2740 }
47103572 2741#endif
e1833e1f 2742 /* External reset */
47103572 2743 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
47103572 2744 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
e1833e1f
JM		 2745 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2746 return;
2747 }
2748 /* Machine check exception */
2749 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2750 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2751 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2752 return;
47103572 2753 }
e1833e1f
JM		 2754#if 0 /* TODO */
2755 /* External debug exception */
2756 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2757 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2758 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2759 return;
2760 }
2761#endif
2762#if defined(TARGET_PPC64H)
2763 if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) {
47103572
JM		 2764 /* Hypervisor decrementer exception */
2765 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
47103572 2766 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
e1833e1f
JM		 2767 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2768 return;
2769 }
2770 }
2771#endif
2772 if (msr_ce != 0) {
2773 /* External critical interrupt */
2774 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2775 /* Taking a critical external interrupt does not clear the external
2776 * critical interrupt status
2777 */
2778#if 0
2779 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
47103572 2780#endif
e1833e1f
JM		 2781 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2782 return;
2783 }
2784 }
2785 if (msr_ee != 0) {
2786 /* Watchdog timer on embedded PowerPC */
2787 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2788 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2789 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2790 return;
2791 }
2792#if defined(TARGET_PPCEMB)
2793 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2794 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2795 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2796 return;
2797 }
2798#endif
2799#if defined(TARGET_PPCEMB)
2800 /* External interrupt */
2801 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2802 /* Taking an external interrupt does not clear the external
2803 * interrupt status
2804 */
2805#if 0
2806 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2807#endif
2808 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2809 return;
2810 }
2811#endif
2812 /* Fixed interval timer on embedded PowerPC */
2813 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2814 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2815 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2816 return;
2817 }
2818 /* Programmable interval timer on embedded PowerPC */
2819 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2820 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2821 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2822 return;
2823 }
47103572
JM		 2824 /* Decrementer exception */
2825 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
47103572 2826 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
e1833e1f
JM		 2827 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2828 return;
2829 }
2830#if !defined(TARGET_PPCEMB)
47103572 2831 /* External interrupt */
e1833e1f 2832 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
e9df014c
JM		 2833 /* Taking an external interrupt does not clear the external
2834 * interrupt status
2835 */
2836#if 0
47103572 2837 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
e9df014c 2838#endif
e1833e1f
JM		 2839 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2840 return;
2841 }
d0dfae6e 2842#endif
e1833e1f
JM		 2843#if defined(TARGET_PPCEMB)
2844 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2845 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2846 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2847 return;
47103572 2848 }
47103572 2849#endif
e1833e1f
JM		 2850 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2851 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2852 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2853 return;
2854 }
2855 /* Thermal interrupt */
2856 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2857 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2858 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2859 return;
2860 }
47103572 2861 }
47103572 2862}
18fba28c 2863#endif /* !CONFIG_USER_ONLY */
a496775f
JM		 2864
2865void cpu_dump_EA (target_ulong EA)
2866{
2867 FILE *f;
2868
2869 if (logfile) {
2870 f = logfile;
2871 } else {
2872 f = stdout;
2873 return;
2874 }
4a057712
JM		 2875 fprintf(f, "Memory access at address " ADDRX "\n", EA);
2876}
2877
2878void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2879{
2880 FILE *f;
2881
2882 if (logfile) {
2883 f = logfile;
2884 } else {
2885 f = stdout;
2886 return;
2887 }
2888 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2889 RA, msr);
a496775f
JM		 2890}
2891
0a032cbe
JM		 2892void cpu_ppc_reset (void *opaque)
2893{
2894 CPUPPCState *env;
5eb7995e 2895 int i;
0a032cbe
JM		 2896
2897 env = opaque;
5eb7995e
JM		 2898 /* XXX: some of those flags initialisation values could depend
2899 * on the actual PowerPC implementation
2900 */
2901 for (i = 0; i < 63; i++)
2902 env->msr[i] = 0;
2903#if defined(TARGET_PPC64)
2904 msr_hv = 0; /* Should be 1... */
2905#endif
2906 msr_ap = 0; /* TO BE CHECKED */
2907 msr_sa = 0; /* TO BE CHECKED */
4e80effc 2908 msr_ep = 1;
0a032cbe
JM		 2909#if defined (DO_SINGLE_STEP) && 0
2910 /* Single step trace mode */
2911 msr_se = 1;
2912 msr_be = 1;
0a032cbe
JM		 2913#endif
2914#if defined(CONFIG_USER_ONLY)
5eb7995e 2915 msr_fp = 1; /* Allow floating point exceptions */
0a032cbe 2916 msr_pr = 1;
fe33cc71 2917#else
1c27f8fb 2918 env->nip = env->hreset_vector | env->excp_prefix;
141c8ae2
JM		 2919 if (env->mmu_model != POWERPC_MMU_REAL_4xx)
2920 ppc_tlb_invalidate_all(env);
0a032cbe
JM		 2921#endif
2922 do_compute_hflags(env);
2923 env->reserve = -1;
5eb7995e
JM		 2924 /* Be sure no exception or interrupt is pending */
2925 env->pending_interrupts = 0;
e1833e1f
JM		 2926 env->exception_index = POWERPC_EXCP_NONE;
2927 env->error_code = 0;
5eb7995e
JM		 2928 /* Flush all TLBs */
2929 tlb_flush(env, 1);
0a032cbe
JM		 2930}
2931
2932CPUPPCState *cpu_ppc_init (void)
2933{
2934 CPUPPCState *env;
2935
2936 env = qemu_mallocz(sizeof(CPUPPCState));
2937 if (!env)
2938 return NULL;
2939 cpu_exec_init(env);
0a032cbe
JM		 2940
2941 return env;
2942}
2943
2944void cpu_ppc_close (CPUPPCState *env)
2945{
2946 /* Should also remove all opcode tables... */
2947 free(env);
2948}
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