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Tkill support, by Stuart Anderson.
[mirror_qemu.git] / target-ppc / helper.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
79aceca5 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
fdabc366
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
27
28#include "cpu.h"
29#include "exec-all.h"
9a64fbe4
FB		 30
31//#define DEBUG_MMU
32//#define DEBUG_BATS
76a66253 33//#define DEBUG_SOFTWARE_TLB
9a64fbe4 34//#define DEBUG_EXCEPTIONS
fdabc366 35//#define FLUSH_ALL_TLBS
9a64fbe4 36
9a64fbe4 37/*****************************************************************************/
3fc6c082 38/* PowerPC MMU emulation */
a541f297 39
d9bce9d9 40#if defined(CONFIG_USER_ONLY)
e96efcfc 41int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
24741ef3
FB		 42 int is_user, int is_softmmu)
43{
44 int exception, error_code;
d9bce9d9 45
24741ef3
FB		 46 if (rw == 2) {
47 exception = EXCP_ISI;
48 error_code = 0;
49 } else {
50 exception = EXCP_DSI;
51 error_code = 0;
52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
76a66253 59
24741ef3
FB		 60 return 1;
61}
76a66253 62
9b3c35e0 63target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
24741ef3
FB		 64{
65 return addr;
66}
67#else
76a66253
JM		 68/* Common routines used by software and hardware TLBs emulation */
69static inline int pte_is_valid (target_ulong pte0)
70{
71 return pte0 & 0x80000000 ? 1 : 0;
72}
73
74static inline void pte_invalidate (target_ulong *pte0)
75{
76 *pte0 &= ~0x80000000;
77}
78
79#define PTE_PTEM_MASK 0x7FFFFFBF
80#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
81
82static int pte_check (mmu_ctx_t *ctx,
83 target_ulong pte0, target_ulong pte1, int h, int rw)
84{
85 int access, ret;
86
87 access = 0;
88 ret = -1;
89 /* Check validity and table match */
90 if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) {
91 /* Check vsid & api */
92 if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {
93 if (ctx->raddr != (target_ulong)-1) {
94 /* all matches should have equal RPN, WIMG & PP */
95 if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
96 if (loglevel > 0)
97 fprintf(logfile, "Bad RPN/WIMG/PP\n");
98 return -3;
99 }
100 }
101 /* Compute access rights */
102 if (ctx->key == 0) {
103 access = PAGE_READ;
104 if ((pte1 & 0x00000003) != 0x3)
105 access |= PAGE_WRITE;
106 } else {
107 switch (pte1 & 0x00000003) {
108 case 0x0:
109 access = 0;
110 break;
111 case 0x1:
112 case 0x3:
113 access = PAGE_READ;
114 break;
115 case 0x2:
116 access = PAGE_READ | PAGE_WRITE;
117 break;
118 }
119 }
120 /* Keep the matching PTE informations */
121 ctx->raddr = pte1;
122 ctx->prot = access;
123 if ((rw == 0 && (access & PAGE_READ)) ||
124 (rw == 1 && (access & PAGE_WRITE))) {
125 /* Access granted */
126#if defined (DEBUG_MMU)
4a057712 127 if (loglevel != 0)
76a66253
JM		 128 fprintf(logfile, "PTE access granted !\n");
129#endif
130 ret = 0;
131 } else {
132 /* Access right violation */
133#if defined (DEBUG_MMU)
4a057712 134 if (loglevel != 0)
76a66253
JM		 135 fprintf(logfile, "PTE access rejected\n");
136#endif
137 ret = -2;
138 }
139 }
140 }
141
142 return ret;
143}
144
145static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
146 int ret, int rw)
147{
148 int store = 0;
149
150 /* Update page flags */
151 if (!(*pte1p & 0x00000100)) {
152 /* Update accessed flag */
153 *pte1p |= 0x00000100;
154 store = 1;
155 }
156 if (!(*pte1p & 0x00000080)) {
157 if (rw == 1 && ret == 0) {
158 /* Update changed flag */
159 *pte1p |= 0x00000080;
160 store = 1;
161 } else {
162 /* Force page fault for first write access */
163 ctx->prot &= ~PAGE_WRITE;
164 }
165 }
166
167 return store;
168}
169
170/* Software driven TLB helpers */
171static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
172 int way, int is_code)
173{
174 int nr;
175
176 /* Select TLB num in a way from address */
177 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
178 /* Select TLB way */
179 nr += env->tlb_per_way * way;
180 /* 6xx have separate TLBs for instructions and data */
181 if (is_code && env->id_tlbs == 1)
182 nr += env->nb_tlb;
183
184 return nr;
185}
186
187void ppc6xx_tlb_invalidate_all (CPUState *env)
188{
1d0a48fb 189 ppc6xx_tlb_t *tlb;
76a66253
JM		 190 int nr, max;
191
192#if defined (DEBUG_SOFTWARE_TLB) && 0
193 if (loglevel != 0) {
194 fprintf(logfile, "Invalidate all TLBs\n");
195 }
196#endif
197 /* Invalidate all defined software TLB */
198 max = env->nb_tlb;
199 if (env->id_tlbs == 1)
200 max *= 2;
201 for (nr = 0; nr < max; nr++) {
1d0a48fb 202 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 203#if !defined(FLUSH_ALL_TLBS)
204 tlb_flush_page(env, tlb->EPN);
205#endif
206 pte_invalidate(&tlb->pte0);
207 }
208#if defined(FLUSH_ALL_TLBS)
209 tlb_flush(env, 1);
210#endif
211}
212
213static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
214 target_ulong eaddr,
215 int is_code, int match_epn)
216{
4a057712 217#if !defined(FLUSH_ALL_TLBS)
1d0a48fb 218 ppc6xx_tlb_t *tlb;
76a66253
JM		 219 int way, nr;
220
76a66253
JM		 221 /* Invalidate ITLB + DTLB, all ways */
222 for (way = 0; way < env->nb_ways; way++) {
223 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
1d0a48fb 224 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 225 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
226#if defined (DEBUG_SOFTWARE_TLB)
227 if (loglevel != 0) {
1b9eb036 228 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
76a66253
JM		 229 nr, env->nb_tlb, eaddr);
230 }
231#endif
232 pte_invalidate(&tlb->pte0);
233 tlb_flush_page(env, tlb->EPN);
234 }
235 }
236#else
237 /* XXX: PowerPC specification say this is valid as well */
238 ppc6xx_tlb_invalidate_all(env);
239#endif
240}
241
242void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
243 int is_code)
244{
245 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
246}
247
248void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
249 target_ulong pte0, target_ulong pte1)
250{
1d0a48fb 251 ppc6xx_tlb_t *tlb;
76a66253
JM		 252 int nr;
253
254 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
1d0a48fb 255 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 256#if defined (DEBUG_SOFTWARE_TLB)
257 if (loglevel != 0) {
1b9eb036
JM		 258 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
259 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
76a66253
JM		 260 }
261#endif
262 /* Invalidate any pending reference in Qemu for this virtual address */
263 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
264 tlb->pte0 = pte0;
265 tlb->pte1 = pte1;
266 tlb->EPN = EPN;
76a66253
JM		 267 /* Store last way for LRU mechanism */
268 env->last_way = way;
269}
270
271static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
272 target_ulong eaddr, int rw, int access_type)
273{
1d0a48fb 274 ppc6xx_tlb_t *tlb;
76a66253
JM		 275 int nr, best, way;
276 int ret;
d9bce9d9 277
76a66253
JM		 278 best = -1;
279 ret = -1; /* No TLB found */
280 for (way = 0; way < env->nb_ways; way++) {
281 nr = ppc6xx_tlb_getnum(env, eaddr, way,
282 access_type == ACCESS_CODE ? 1 : 0);
1d0a48fb 283 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 284 /* This test "emulates" the PTE index match for hardware TLBs */
285 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
286#if defined (DEBUG_SOFTWARE_TLB)
287 if (loglevel != 0) {
1b9eb036
JM		 288 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
289 "] <> " ADDRX "\n",
76a66253
JM		 290 nr, env->nb_tlb,
291 pte_is_valid(tlb->pte0) ? "valid" : "inval",
292 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
293 }
294#endif
295 continue;
296 }
297#if defined (DEBUG_SOFTWARE_TLB)
298 if (loglevel != 0) {
1b9eb036
JM		 299 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
300 " %c %c\n",
76a66253
JM		 301 nr, env->nb_tlb,
302 pte_is_valid(tlb->pte0) ? "valid" : "inval",
303 tlb->EPN, eaddr, tlb->pte1,
304 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
305 }
306#endif
307 switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
308 case -3:
309 /* TLB inconsistency */
310 return -1;
311 case -2:
312 /* Access violation */
313 ret = -2;
314 best = nr;
315 break;
316 case -1:
317 default:
318 /* No match */
319 break;
320 case 0:
321 /* access granted */
322 /* XXX: we should go on looping to check all TLBs consistency
323 * but we can speed-up the whole thing as the
324 * result would be undefined if TLBs are not consistent.
325 */
326 ret = 0;
327 best = nr;
328 goto done;
329 }
330 }
331 if (best != -1) {
332 done:
333#if defined (DEBUG_SOFTWARE_TLB)
4a057712 334 if (loglevel != 0) {
76a66253
JM		 335 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
336 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
337 }
338#endif
339 /* Update page flags */
1d0a48fb 340 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
76a66253
JM		 341 }
342
343 return ret;
344}
345
9a64fbe4 346/* Perform BAT hit & translation */
76a66253
JM		 347static int get_bat (CPUState *env, mmu_ctx_t *ctx,
348 target_ulong virtual, int rw, int type)
9a64fbe4 349{
76a66253
JM		 350 target_ulong *BATlt, *BATut, *BATu, *BATl;
351 target_ulong base, BEPIl, BEPIu, bl;
9a64fbe4
FB		 352 int i;
353 int ret = -1;
354
355#if defined (DEBUG_BATS)
4a057712 356 if (loglevel != 0) {
1b9eb036 357 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 358 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 359 }
9a64fbe4
FB		 360#endif
361 switch (type) {
362 case ACCESS_CODE:
363 BATlt = env->IBAT[1];
364 BATut = env->IBAT[0];
365 break;
366 default:
367 BATlt = env->DBAT[1];
368 BATut = env->DBAT[0];
369 break;
370 }
371#if defined (DEBUG_BATS)
4a057712 372 if (loglevel != 0) {
1b9eb036 373 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 374 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 375 }
9a64fbe4
FB		 376#endif
377 base = virtual & 0xFFFC0000;
378 for (i = 0; i < 4; i++) {
379 BATu = &BATut[i];
380 BATl = &BATlt[i];
381 BEPIu = *BATu & 0xF0000000;
382 BEPIl = *BATu & 0x0FFE0000;
383 bl = (*BATu & 0x00001FFC) << 15;
384#if defined (DEBUG_BATS)
4a057712 385 if (loglevel != 0) {
1b9eb036
JM		 386 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
387 " BATl 0x" ADDRX "\n",
9a64fbe4
FB		 388 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
389 *BATu, *BATl);
9a64fbe4
FB		 390 }
391#endif
392 if ((virtual & 0xF0000000) == BEPIu &&
393 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
394 /* BAT matches */
395 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
396 (msr_pr == 1 && (*BATu & 0x00000001))) {
397 /* Get physical address */
76a66253 398 ctx->raddr = (*BATl & 0xF0000000) |
9a64fbe4 399 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
a541f297 400 (virtual & 0x0001F000);
9a64fbe4 401 if (*BATl & 0x00000001)
76a66253 402 ctx->prot = PAGE_READ;
9a64fbe4 403 if (*BATl & 0x00000002)
76a66253 404 ctx->prot = PAGE_WRITE | PAGE_READ;
9a64fbe4 405#if defined (DEBUG_BATS)
4a057712
JM		 406 if (loglevel != 0) {
407 fprintf(logfile, "BAT %d match: r 0x" PADDRX
1b9eb036 408 " prot=%c%c\n",
76a66253
JM		 409 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
410 ctx->prot & PAGE_WRITE ? 'W' : '-');
9a64fbe4
FB		 411 }
412#endif
413 ret = 0;
414 break;
415 }
416 }
417 }
418 if (ret < 0) {
419#if defined (DEBUG_BATS)
4a057712
JM		 420 if (loglevel != 0) {
421 fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
422 for (i = 0; i < 4; i++) {
423 BATu = &BATut[i];
424 BATl = &BATlt[i];
425 BEPIu = *BATu & 0xF0000000;
426 BEPIl = *BATu & 0x0FFE0000;
427 bl = (*BATu & 0x00001FFC) << 15;
428 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
429 " BATl 0x" ADDRX " \n\t"
430 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
431 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
432 *BATu, *BATl, BEPIu, BEPIl, bl);
433 }
9a64fbe4
FB		 434 }
435#endif
9a64fbe4
FB		 436 }
437 /* No hit */
438 return ret;
439}
440
441/* PTE table lookup */
76a66253 442static int find_pte (mmu_ctx_t *ctx, int h, int rw)
9a64fbe4 443{
76a66253
JM		 444 target_ulong base, pte0, pte1;
445 int i, good = -1;
446 int ret;
9a64fbe4 447
76a66253
JM		 448 ret = -1; /* No entry found */
449 base = ctx->pg_addr[h];
9a64fbe4 450 for (i = 0; i < 8; i++) {
8df1cd07
FB		 451 pte0 = ldl_phys(base + (i * 8));
452 pte1 = ldl_phys(base + (i * 8) + 4);
9a64fbe4 453#if defined (DEBUG_MMU)
d094807b 454 if (loglevel > 0) {
1b9eb036
JM		 455 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
456 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
457 base + (i * 8), pte0, pte1,
76a66253
JM		 458 pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem);
459 }
9a64fbe4 460#endif
76a66253
JM		 461 switch (pte_check(ctx, pte0, pte1, h, rw)) {
462 case -3:
463 /* PTE inconsistency */
464 return -1;
465 case -2:
466 /* Access violation */
467 ret = -2;
468 good = i;
469 break;
470 case -1:
471 default:
472 /* No PTE match */
473 break;
474 case 0:
475 /* access granted */
476 /* XXX: we should go on looping to check all PTEs consistency
477 * but if we can speed-up the whole thing as the
478 * result would be undefined if PTEs are not consistent.
479 */
480 ret = 0;
481 good = i;
482 goto done;
9a64fbe4
FB		 483 }
484 }
485 if (good != -1) {
76a66253 486 done:
9a64fbe4 487#if defined (DEBUG_MMU)
4a057712
JM		 488 if (loglevel != 0) {
489 fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
1b9eb036 490 "ret=%d\n",
76a66253
JM		 491 ctx->raddr, ctx->prot, ret);
492 }
9a64fbe4
FB		 493#endif
494 /* Update page flags */
76a66253
JM		 495 pte1 = ctx->raddr;
496 if (pte_update_flags(ctx, &pte1, ret, rw) == 1)
497 stl_phys_notdirty(base + (good * 8) + 4, pte1);
9a64fbe4
FB		 498 }
499
500 return ret;
79aceca5
FB		 501}
502
76a66253
JM		 503static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
504 target_phys_addr_t hash,
505 target_phys_addr_t mask)
79aceca5 506{
9a64fbe4 507 return (sdr1 & 0xFFFF0000) | (hash & mask);
79aceca5
FB		 508}
509
9a64fbe4 510/* Perform segment based translation */
76a66253
JM		 511static int get_segment (CPUState *env, mmu_ctx_t *ctx,
512 target_ulong eaddr, int rw, int type)
79aceca5 513{
76a66253
JM		 514 target_phys_addr_t sdr, hash, mask;
515 target_ulong sr, vsid, pgidx;
9a64fbe4 516 int ret = -1, ret2;
79aceca5 517
76a66253 518 sr = env->sr[eaddr >> 28];
9a64fbe4 519#if defined (DEBUG_MMU)
a541f297 520 if (loglevel > 0) {
1b9eb036
JM		 521 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x"
522 ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
76a66253
JM		 523 eaddr, eaddr >> 28, sr, env->nip,
524 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
a541f297 525 }
9a64fbe4 526#endif
76a66253
JM		 527 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
528 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
9a64fbe4
FB		 529 if ((sr & 0x80000000) == 0) {
530#if defined (DEBUG_MMU)
76a66253 531 if (loglevel > 0)
1b9eb036 532 fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
76a66253 533 ctx->key, sr & 0x10000000);
9a64fbe4
FB		 534#endif
535 /* Check if instruction fetch is allowed, if needed */
536 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
537 /* Page address translation */
76a66253 538 pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;
9a64fbe4 539 vsid = sr & 0x00FFFFFF;
a541f297 540 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
76a66253
JM		 541 /* Primary table address */
542 sdr = env->sdr1;
9a64fbe4 543 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
76a66253
JM		 544 ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);
545 /* Secondary table address */
546 hash = (~hash) & 0x01FFFFC0;
547 ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);
548 ctx->ptem = (vsid << 7) | (pgidx >> 10);
549 /* Initialize real address with an invalid value */
550 ctx->raddr = (target_ulong)-1;
551 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
552 /* Software TLB search */
553 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
76a66253 554 } else {
9a64fbe4 555#if defined (DEBUG_MMU)
4a057712
JM		 556 if (loglevel != 0) {
557 fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
558 "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
559 sdr, (uint32_t)vsid, (uint32_t)pgidx,
560 (uint32_t)hash, ctx->pg_addr[0]);
76a66253 561 }
9a64fbe4 562#endif
76a66253
JM		 563 /* Primary table lookup */
564 ret = find_pte(ctx, 0, rw);
565 if (ret < 0) {
566 /* Secondary table lookup */
9a64fbe4 567#if defined (DEBUG_MMU)
4a057712 568 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
76a66253 569 fprintf(logfile,
4a057712
JM		 570 "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
571 "hash=0x%05x pg_addr=0x" PADDRX "\n",
572 sdr, (uint32_t)vsid, (uint32_t)pgidx,
573 (uint32_t)hash, ctx->pg_addr[1]);
76a66253 574 }
9a64fbe4 575#endif
76a66253
JM		 576 ret2 = find_pte(ctx, 1, rw);
577 if (ret2 != -1)
578 ret = ret2;
579 }
9a64fbe4 580 }
9a64fbe4
FB		 581 } else {
582#if defined (DEBUG_MMU)
4a057712 583 if (loglevel != 0)
76a66253 584 fprintf(logfile, "No access allowed\n");
9a64fbe4 585#endif
76a66253 586 ret = -3;
9a64fbe4
FB		 587 }
588 } else {
589#if defined (DEBUG_MMU)
4a057712 590 if (loglevel != 0)
76a66253 591 fprintf(logfile, "direct store...\n");
9a64fbe4
FB		 592#endif
593 /* Direct-store segment : absolutely *BUGGY* for now */
594 switch (type) {
595 case ACCESS_INT:
596 /* Integer load/store : only access allowed */
597 break;
598 case ACCESS_CODE:
599 /* No code fetch is allowed in direct-store areas */
600 return -4;
601 case ACCESS_FLOAT:
602 /* Floating point load/store */
603 return -4;
604 case ACCESS_RES:
605 /* lwarx, ldarx or srwcx. */
606 return -4;
607 case ACCESS_CACHE:
608 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
609 /* Should make the instruction do no-op.
610 * As it already do no-op, it's quite easy :-)
611 */
76a66253 612 ctx->raddr = eaddr;
9a64fbe4
FB		 613 return 0;
614 case ACCESS_EXT:
615 /* eciwx or ecowx */
616 return -4;
617 default:
618 if (logfile) {
619 fprintf(logfile, "ERROR: instruction should not need "
620 "address translation\n");
621 }
9a64fbe4
FB		 622 return -4;
623 }
76a66253
JM		 624 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
625 ctx->raddr = eaddr;
9a64fbe4
FB		 626 ret = 2;
627 } else {
628 ret = -2;
629 }
79aceca5 630 }
9a64fbe4
FB		 631
632 return ret;
79aceca5
FB		 633}
634
c294fc58
JM		 635/* Generic TLB check function for embedded PowerPC implementations */
636static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
637 target_phys_addr_t *raddrp,
638 target_ulong address, int i)
639{
640 target_ulong mask;
641
642 /* Check valid flag */
643 if (!(tlb->prot & PAGE_VALID)) {
644 if (loglevel != 0)
645 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
646 return -1;
647 }
648 mask = ~(tlb->size - 1);
649 if (loglevel != 0) {
650 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
651 ADDRX " " ADDRX " %d\n",
652 __func__, i, address, (int)env->spr[SPR_40x_PID],
653 tlb->EPN, mask, (int)tlb->PID);
654 }
655 /* Check PID */
656 if (tlb->PID != 0 && tlb->PID != env->spr[SPR_40x_PID])
657 return -1;
658 /* Check effective address */
659 if ((address & mask) != tlb->EPN)
660 return -1;
661 *raddrp = (tlb->RPN & mask) | (address & ~mask);
662
663 return 0;
664}
665
666/* Generic TLB search function for PowerPC embedded implementations */
667int ppcemb_tlb_search (CPUState *env, target_ulong address)
668{
669 ppcemb_tlb_t *tlb;
670 target_phys_addr_t raddr;
671 int i, ret;
672
673 /* Default return value is no match */
674 ret = -1;
675 for (i = 0; i < 64; i++) {
676 tlb = &env->tlb[i].tlbe;
677 if (ppcemb_tlb_check(env, tlb, &raddr, address, i) == 0) {
678 ret = i;
679 break;
680 }
681 }
682
683 return ret;
684}
685
686/* Helpers specific to PowerPC 40x implementations */
0a032cbe
JM		 687void ppc4xx_tlb_invalidate_all (CPUState *env)
688{
689 ppcemb_tlb_t *tlb;
690 int i;
691
692 for (i = 0; i < env->nb_tlb; i++) {
693 tlb = &env->tlb[i].tlbe;
694 if (tlb->prot & PAGE_VALID) {
695#if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
696 end = tlb->EPN + tlb->size;
697 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
698 tlb_flush_page(env, page);
699#endif
700 tlb->prot &= ~PAGE_VALID;
701 }
702 }
703 tlb_flush(env, 1);
704}
705
a8dea12f 706int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
e96efcfc 707 target_ulong address, int rw, int access_type)
a8dea12f
JM		 708{
709 ppcemb_tlb_t *tlb;
710 target_phys_addr_t raddr;
a8dea12f
JM		 711 int i, ret, zsel, zpr;
712
c55e9aef
JM		 713 ret = -1;
714 raddr = -1;
a8dea12f
JM		 715 for (i = 0; i < env->nb_tlb; i++) {
716 tlb = &env->tlb[i].tlbe;
c294fc58 717 if (ppcemb_tlb_check(env, tlb, &raddr, address, i) < 0)
a8dea12f 718 continue;
a8dea12f
JM		 719 zsel = (tlb->attr >> 4) & 0xF;
720 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
4a057712 721 if (loglevel != 0) {
a8dea12f
JM		 722 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
723 __func__, i, zsel, zpr, rw, tlb->attr);
724 }
725 if (access_type == ACCESS_CODE) {
726 /* Check execute enable bit */
727 switch (zpr) {
c294fc58
JM		 728 case 0x2:
729 if (msr_pr)
730 goto check_exec_perm;
731 goto exec_granted;
a8dea12f
JM		 732 case 0x0:
733 if (msr_pr) {
a8dea12f 734 ctx->prot = 0;
c55e9aef 735 ret = -3;
a8dea12f
JM		 736 break;
737 }
738 /* No break here */
739 case 0x1:
c294fc58 740 check_exec_perm:
a8dea12f
JM		 741 /* Check from TLB entry */
742 if (!(tlb->prot & PAGE_EXEC)) {
743 ret = -3;
744 } else {
c55e9aef 745 if (tlb->prot & PAGE_WRITE) {
a8dea12f 746 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 747 } else {
a8dea12f 748 ctx->prot = PAGE_READ;
c55e9aef 749 }
a8dea12f
JM		 750 ret = 0;
751 }
752 break;
753 case 0x3:
c294fc58 754 exec_granted:
a8dea12f 755 /* All accesses granted */
a8dea12f 756 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 757 ret = 0;
a8dea12f
JM		 758 break;
759 }
760 } else {
761 switch (zpr) {
c294fc58
JM		 762 case 0x2:
763 if (msr_pr)
764 goto check_rw_perm;
765 goto rw_granted;
a8dea12f
JM		 766 case 0x0:
767 if (msr_pr) {
a8dea12f 768 ctx->prot = 0;
c55e9aef 769 ret = -2;
a8dea12f
JM		 770 break;
771 }
772 /* No break here */
773 case 0x1:
c294fc58 774 check_rw_perm:
a8dea12f
JM		 775 /* Check from TLB entry */
776 /* Check write protection bit */
c55e9aef
JM		 777 if (tlb->prot & PAGE_WRITE) {
778 ctx->prot = PAGE_READ | PAGE_WRITE;
779 ret = 0;
a8dea12f 780 } else {
c55e9aef
JM		 781 ctx->prot = PAGE_READ;
782 if (rw)
783 ret = -2;
a8dea12f 784 else
c55e9aef 785 ret = 0;
a8dea12f
JM		 786 }
787 break;
788 case 0x3:
c294fc58 789 rw_granted:
a8dea12f 790 /* All accesses granted */
a8dea12f 791 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 792 ret = 0;
a8dea12f
JM		 793 break;
794 }
795 }
796 if (ret >= 0) {
797 ctx->raddr = raddr;
4a057712 798 if (loglevel != 0) {
a8dea12f 799 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
c55e9aef
JM		 800 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
801 ret);
a8dea12f 802 }
c55e9aef 803 return 0;
a8dea12f
JM		 804 }
805 }
4a057712 806 if (loglevel != 0) {
c55e9aef
JM		 807 fprintf(logfile, "%s: access refused " ADDRX " => " REGX
808 " %d %d\n", __func__, address, raddr, ctx->prot,
809 ret);
810 }
a8dea12f
JM		 811
812 return ret;
813}
814
c294fc58
JM		 815void store_40x_sler (CPUPPCState *env, uint32_t val)
816{
817 /* XXX: TO BE FIXED */
818 if (val != 0x00000000) {
819 cpu_abort(env, "Little-endian regions are not supported by now\n");
820 }
821 env->spr[SPR_405_SLER] = val;
822}
823
76a66253
JM		 824static int check_physical (CPUState *env, mmu_ctx_t *ctx,
825 target_ulong eaddr, int rw)
826{
827 int in_plb, ret;
828
829 ctx->raddr = eaddr;
830 ctx->prot = PAGE_READ;
831 ret = 0;
832 if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) {
833 /* 403 family add some particular protections,
834 * using PBL/PBU registers for accesses with no translation.
835 */
836 in_plb =
837 /* Check PLB validity */
838 (env->pb[0] < env->pb[1] &&
839 /* and address in plb area */
840 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
841 (env->pb[2] < env->pb[3] &&
842 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
843 if (in_plb ^ msr_px) {
844 /* Access in protected area */
845 if (rw == 1) {
846 /* Access is not allowed */
847 ret = -2;
848 }
849 } else {
850 /* Read-write access is allowed */
851 ctx->prot |= PAGE_WRITE;
852 }
853 } else {
854 ctx->prot |= PAGE_WRITE;
855 }
856
857 return ret;
858}
859
860int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
861 int rw, int access_type, int check_BATs)
9a64fbe4
FB		 862{
863 int ret;
514fb8c1 864#if 0
4a057712 865 if (loglevel != 0) {
9a64fbe4
FB		 866 fprintf(logfile, "%s\n", __func__);
867 }
d9bce9d9 868#endif
4b3686fa
FB		 869 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
870 (access_type != ACCESS_CODE && msr_dr == 0)) {
9a64fbe4 871 /* No address translation */
76a66253 872 ret = check_physical(env, ctx, eaddr, rw);
9a64fbe4 873 } else {
c55e9aef 874 ret = -1;
a8dea12f
JM		 875 switch (PPC_MMU(env)) {
876 case PPC_FLAGS_MMU_32B:
877 case PPC_FLAGS_MMU_SOFT_6xx:
878 /* Try to find a BAT */
a8dea12f
JM		 879 if (check_BATs)
880 ret = get_bat(env, ctx, eaddr, rw, access_type);
c55e9aef
JM		 881 /* No break here */
882#if defined(TARGET_PPC64)
883 case PPC_FLAGS_MMU_64B:
884 case PPC_FLAGS_MMU_64BRIDGE:
885#endif
a8dea12f 886 if (ret < 0) {
c55e9aef 887 /* We didn't match any BAT entry or don't have BATs */
a8dea12f
JM		 888 ret = get_segment(env, ctx, eaddr, rw, access_type);
889 }
890 break;
891 case PPC_FLAGS_MMU_SOFT_4xx:
c55e9aef 892 case PPC_FLAGS_MMU_403:
a8dea12f
JM		 893 ret = mmu4xx_get_physical_address(env, ctx, eaddr,
894 rw, access_type);
895 break;
c55e9aef
JM		 896 case PPC_FLAGS_MMU_601:
897 /* XXX: TODO */
898 cpu_abort(env, "601 MMU model not implemented\n");
899 return -1;
900 case PPC_FLAGS_MMU_BOOKE:
a8dea12f 901 /* XXX: TODO */
c55e9aef
JM		 902 cpu_abort(env, "BookeE MMU model not implemented\n");
903 return -1;
904 case PPC_FLAGS_MMU_BOOKE_FSL:
905 /* XXX: TODO */
906 cpu_abort(env, "BookE FSL MMU model not implemented\n");
907 return -1;
908 default:
909 cpu_abort(env, "Unknown or invalid MMU model\n");
a8dea12f 910 return -1;
9a64fbe4
FB		 911 }
912 }
514fb8c1 913#if 0
4a057712
JM		 914 if (loglevel != 0) {
915 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
c55e9aef 916 __func__, eaddr, ret, ctx->raddr);
a541f297 917 }
76a66253 918#endif
d9bce9d9 919
9a64fbe4
FB		 920 return ret;
921}
922
9b3c35e0 923target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
a6b025d3 924{
76a66253 925 mmu_ctx_t ctx;
a6b025d3 926
76a66253 927 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
a6b025d3 928 return -1;
76a66253
JM		 929
930 return ctx.raddr & TARGET_PAGE_MASK;
a6b025d3 931}
9a64fbe4 932
9a64fbe4 933/* Perform address translation */
e96efcfc 934int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
a541f297 935 int is_user, int is_softmmu)
9a64fbe4 936{
76a66253 937 mmu_ctx_t ctx;
9a64fbe4 938 int exception = 0, error_code = 0;
a541f297 939 int access_type;
9a64fbe4 940 int ret = 0;
d9bce9d9 941
b769d8fe
FB		 942 if (rw == 2) {
943 /* code access */
944 rw = 0;
945 access_type = ACCESS_CODE;
946 } else {
947 /* data access */
948 /* XXX: put correct access by using cpu_restore_state()
949 correctly */
950 access_type = ACCESS_INT;
951 // access_type = env->access_type;
952 }
76a66253 953 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
9a64fbe4 954 if (ret == 0) {
76a66253
JM		 955 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
956 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
957 is_user, is_softmmu);
9a64fbe4 958 } else if (ret < 0) {
9a64fbe4 959#if defined (DEBUG_MMU)
4a057712 960 if (loglevel != 0)
76a66253 961 cpu_dump_state(env, logfile, fprintf, 0);
9a64fbe4
FB		 962#endif
963 if (access_type == ACCESS_CODE) {
964 exception = EXCP_ISI;
965 switch (ret) {
966 case -1:
76a66253 967 /* No matches in page tables or TLB */
c55e9aef
JM		 968 switch (PPC_MMU(env)) {
969 case PPC_FLAGS_MMU_SOFT_6xx:
76a66253
JM		 970 exception = EXCP_I_TLBMISS;
971 env->spr[SPR_IMISS] = address;
972 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
973 error_code = 1 << 18;
974 goto tlb_miss;
c55e9aef
JM		 975 case PPC_FLAGS_MMU_SOFT_4xx:
976 case PPC_FLAGS_MMU_403:
a8dea12f
JM		 977 exception = EXCP_40x_ITLBMISS;
978 error_code = 0;
979 env->spr[SPR_40x_DEAR] = address;
980 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef
JM		 981 break;
982 case PPC_FLAGS_MMU_32B:
76a66253 983 error_code = 0x40000000;
c55e9aef
JM		 984 break;
985#if defined(TARGET_PPC64)
986 case PPC_FLAGS_MMU_64B:
987 /* XXX: TODO */
988 cpu_abort(env, "MMU model not implemented\n");
989 return -1;
990 case PPC_FLAGS_MMU_64BRIDGE:
991 /* XXX: TODO */
992 cpu_abort(env, "MMU model not implemented\n");
993 return -1;
994#endif
995 case PPC_FLAGS_MMU_601:
996 /* XXX: TODO */
997 cpu_abort(env, "MMU model not implemented\n");
998 return -1;
999 case PPC_FLAGS_MMU_BOOKE:
1000 /* XXX: TODO */
1001 cpu_abort(env, "MMU model not implemented\n");
1002 return -1;
1003 case PPC_FLAGS_MMU_BOOKE_FSL:
1004 /* XXX: TODO */
1005 cpu_abort(env, "MMU model not implemented\n");
1006 return -1;
1007 default:
1008 cpu_abort(env, "Unknown or invalid MMU model\n");
1009 return -1;
76a66253 1010 }
9a64fbe4
FB		 1011 break;
1012 case -2:
1013 /* Access rights violation */
2be0071f 1014 error_code = 0x08000000;
9a64fbe4
FB		 1015 break;
1016 case -3:
76a66253 1017 /* No execute protection violation */
2be0071f 1018 error_code = 0x10000000;
9a64fbe4
FB		 1019 break;
1020 case -4:
1021 /* Direct store exception */
1022 /* No code fetch is allowed in direct-store areas */
2be0071f
FB		 1023 error_code = 0x10000000;
1024 break;
1025 case -5:
1026 /* No match in segment table */
1027 exception = EXCP_ISEG;
1028 error_code = 0;
9a64fbe4
FB		 1029 break;
1030 }
1031 } else {
1032 exception = EXCP_DSI;
1033 switch (ret) {
1034 case -1:
76a66253 1035 /* No matches in page tables or TLB */
c55e9aef
JM		 1036 switch (PPC_MMU(env)) {
1037 case PPC_FLAGS_MMU_SOFT_6xx:
76a66253
JM		 1038 if (rw == 1) {
1039 exception = EXCP_DS_TLBMISS;
1040 error_code = 1 << 16;
1041 } else {
1042 exception = EXCP_DL_TLBMISS;
1043 error_code = 0;
1044 }
1045 env->spr[SPR_DMISS] = address;
1046 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1047 tlb_miss:
1048 error_code |= ctx.key << 19;
1049 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1050 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1051 /* Do not alter DAR nor DSISR */
1052 goto out;
c55e9aef
JM		 1053 case PPC_FLAGS_MMU_SOFT_4xx:
1054 case PPC_FLAGS_MMU_403:
a8dea12f
JM		 1055 exception = EXCP_40x_DTLBMISS;
1056 error_code = 0;
1057 env->spr[SPR_40x_DEAR] = address;
1058 if (rw)
1059 env->spr[SPR_40x_ESR] = 0x00800000;
1060 else
1061 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef
JM		 1062 break;
1063 case PPC_FLAGS_MMU_32B:
76a66253 1064 error_code = 0x40000000;
c55e9aef
JM		 1065 break;
1066#if defined(TARGET_PPC64)
1067 case PPC_FLAGS_MMU_64B:
1068 /* XXX: TODO */
1069 cpu_abort(env, "MMU model not implemented\n");
1070 return -1;
1071 case PPC_FLAGS_MMU_64BRIDGE:
1072 /* XXX: TODO */
1073 cpu_abort(env, "MMU model not implemented\n");
1074 return -1;
1075#endif
1076 case PPC_FLAGS_MMU_601:
1077 /* XXX: TODO */
1078 cpu_abort(env, "MMU model not implemented\n");
1079 return -1;
1080 case PPC_FLAGS_MMU_BOOKE:
1081 /* XXX: TODO */
1082 cpu_abort(env, "MMU model not implemented\n");
1083 return -1;
1084 case PPC_FLAGS_MMU_BOOKE_FSL:
1085 /* XXX: TODO */
1086 cpu_abort(env, "MMU model not implemented\n");
1087 return -1;
1088 default:
1089 cpu_abort(env, "Unknown or invalid MMU model\n");
1090 return -1;
76a66253 1091 }
9a64fbe4
FB		 1092 break;
1093 case -2:
1094 /* Access rights violation */
2be0071f 1095 error_code = 0x08000000;
9a64fbe4
FB		 1096 break;
1097 case -4:
1098 /* Direct store exception */
1099 switch (access_type) {
1100 case ACCESS_FLOAT:
1101 /* Floating point load/store */
1102 exception = EXCP_ALIGN;
1103 error_code = EXCP_ALIGN_FP;
1104 break;
1105 case ACCESS_RES:
1106 /* lwarx, ldarx or srwcx. */
2be0071f 1107 error_code = 0x04000000;
9a64fbe4
FB		 1108 break;
1109 case ACCESS_EXT:
1110 /* eciwx or ecowx */
2be0071f 1111 error_code = 0x04100000;
9a64fbe4
FB		 1112 break;
1113 default:
76a66253 1114 printf("DSI: invalid exception (%d)\n", ret);
9a64fbe4
FB		 1115 exception = EXCP_PROGRAM;
1116 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
1117 break;
1118 }
fdabc366 1119 break;
2be0071f
FB		 1120 case -5:
1121 /* No match in segment table */
1122 exception = EXCP_DSEG;
1123 error_code = 0;
1124 break;
9a64fbe4 1125 }
fdabc366 1126 if (exception == EXCP_DSI && rw == 1)
2be0071f 1127 error_code |= 0x02000000;
76a66253
JM		 1128 /* Store fault address */
1129 env->spr[SPR_DAR] = address;
2be0071f 1130 env->spr[SPR_DSISR] = error_code;
9a64fbe4 1131 }
76a66253 1132 out:
9a64fbe4
FB		 1133#if 0
1134 printf("%s: set exception to %d %02x\n",
1135 __func__, exception, error_code);
1136#endif
1137 env->exception_index = exception;
1138 env->error_code = error_code;
9a64fbe4
FB		 1139 ret = 1;
1140 }
76a66253 1141
9a64fbe4
FB		 1142 return ret;
1143}
1144
3fc6c082
FB		 1145/*****************************************************************************/
1146/* BATs management */
1147#if !defined(FLUSH_ALL_TLBS)
1148static inline void do_invalidate_BAT (CPUPPCState *env,
1149 target_ulong BATu, target_ulong mask)
1150{
1151 target_ulong base, end, page;
76a66253 1152
3fc6c082
FB		 1153 base = BATu & ~0x0001FFFF;
1154 end = base + mask + 0x00020000;
1155#if defined (DEBUG_BATS)
76a66253 1156 if (loglevel != 0) {
1b9eb036 1157 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
76a66253
JM		 1158 base, end, mask);
1159 }
3fc6c082
FB		 1160#endif
1161 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1162 tlb_flush_page(env, page);
1163#if defined (DEBUG_BATS)
1164 if (loglevel != 0)
1165 fprintf(logfile, "Flush done\n");
1166#endif
1167}
1168#endif
1169
1170static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
1171 target_ulong value)
1172{
1173#if defined (DEBUG_BATS)
1174 if (loglevel != 0) {
1b9eb036
JM		 1175 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1176 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
3fc6c082
FB		 1177 }
1178#endif
1179}
1180
1181target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1182{
1183 return env->IBAT[0][nr];
1184}
1185
1186target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1187{
1188 return env->IBAT[1][nr];
1189}
1190
1191void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1192{
1193 target_ulong mask;
1194
1195 dump_store_bat(env, 'I', 0, nr, value);
1196 if (env->IBAT[0][nr] != value) {
1197 mask = (value << 15) & 0x0FFE0000UL;
1198#if !defined(FLUSH_ALL_TLBS)
1199 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1200#endif
1201 /* When storing valid upper BAT, mask BEPI and BRPN
1202 * and invalidate all TLBs covered by this BAT
1203 */
1204 mask = (value << 15) & 0x0FFE0000UL;
1205 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1206 (value & ~0x0001FFFFUL & ~mask);
1207 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1208 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1209#if !defined(FLUSH_ALL_TLBS)
1210 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
76a66253 1211#else
3fc6c082
FB		 1212 tlb_flush(env, 1);
1213#endif
1214 }
1215}
1216
1217void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1218{
1219 dump_store_bat(env, 'I', 1, nr, value);
1220 env->IBAT[1][nr] = value;
1221}
1222
1223target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1224{
1225 return env->DBAT[0][nr];
1226}
1227
1228target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1229{
1230 return env->DBAT[1][nr];
1231}
1232
1233void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1234{
1235 target_ulong mask;
1236
1237 dump_store_bat(env, 'D', 0, nr, value);
1238 if (env->DBAT[0][nr] != value) {
1239 /* When storing valid upper BAT, mask BEPI and BRPN
1240 * and invalidate all TLBs covered by this BAT
1241 */
1242 mask = (value << 15) & 0x0FFE0000UL;
1243#if !defined(FLUSH_ALL_TLBS)
1244 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1245#endif
1246 mask = (value << 15) & 0x0FFE0000UL;
1247 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1248 (value & ~0x0001FFFFUL & ~mask);
1249 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1250 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1251#if !defined(FLUSH_ALL_TLBS)
1252 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1253#else
1254 tlb_flush(env, 1);
1255#endif
1256 }
1257}
1258
1259void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1260{
1261 dump_store_bat(env, 'D', 1, nr, value);
1262 env->DBAT[1][nr] = value;
1263}
1264
0a032cbe
JM		 1265
1266/*****************************************************************************/
1267/* TLB management */
1268void ppc_tlb_invalidate_all (CPUPPCState *env)
1269{
1270 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
1271 ppc6xx_tlb_invalidate_all(env);
1272 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
1273 ppc4xx_tlb_invalidate_all(env);
1274 } else {
1275 tlb_flush(env, 1);
1276 }
1277}
1278
3fc6c082
FB		 1279/*****************************************************************************/
1280/* Special registers manipulation */
d9bce9d9
JM		 1281#if defined(TARGET_PPC64)
1282target_ulong ppc_load_asr (CPUPPCState *env)
1283{
1284 return env->asr;
1285}
1286
1287void ppc_store_asr (CPUPPCState *env, target_ulong value)
1288{
1289 if (env->asr != value) {
1290 env->asr = value;
1291 tlb_flush(env, 1);
1292 }
1293}
1294#endif
1295
3fc6c082
FB		 1296target_ulong do_load_sdr1 (CPUPPCState *env)
1297{
1298 return env->sdr1;
1299}
1300
1301void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1302{
1303#if defined (DEBUG_MMU)
1304 if (loglevel != 0) {
1b9eb036 1305 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
3fc6c082
FB		 1306 }
1307#endif
1308 if (env->sdr1 != value) {
1309 env->sdr1 = value;
76a66253 1310 tlb_flush(env, 1);
3fc6c082
FB		 1311 }
1312}
1313
1314target_ulong do_load_sr (CPUPPCState *env, int srnum)
1315{
1316 return env->sr[srnum];
1317}
1318
1319void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1320{
1321#if defined (DEBUG_MMU)
1322 if (loglevel != 0) {
1b9eb036
JM		 1323 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1324 __func__, srnum, value, env->sr[srnum]);
3fc6c082
FB		 1325 }
1326#endif
1327 if (env->sr[srnum] != value) {
1328 env->sr[srnum] = value;
1329#if !defined(FLUSH_ALL_TLBS) && 0
1330 {
1331 target_ulong page, end;
1332 /* Invalidate 256 MB of virtual memory */
1333 page = (16 << 20) * srnum;
1334 end = page + (16 << 20);
1335 for (; page != end; page += TARGET_PAGE_SIZE)
1336 tlb_flush_page(env, page);
1337 }
1338#else
76a66253 1339 tlb_flush(env, 1);
3fc6c082
FB		 1340#endif
1341 }
1342}
76a66253 1343#endif /* !defined (CONFIG_USER_ONLY) */
3fc6c082 1344
76a66253 1345uint32_t ppc_load_xer (CPUPPCState *env)
79aceca5
FB		 1346{
1347 return (xer_so << XER_SO) |
1348 (xer_ov << XER_OV) |
1349 (xer_ca << XER_CA) |
3fc6c082
FB		 1350 (xer_bc << XER_BC) |
1351 (xer_cmp << XER_CMP);
79aceca5
FB		 1352}
1353
76a66253 1354void ppc_store_xer (CPUPPCState *env, uint32_t value)
79aceca5
FB		 1355{
1356 xer_so = (value >> XER_SO) & 0x01;
1357 xer_ov = (value >> XER_OV) & 0x01;
1358 xer_ca = (value >> XER_CA) & 0x01;
3fc6c082 1359 xer_cmp = (value >> XER_CMP) & 0xFF;
d9bce9d9 1360 xer_bc = (value >> XER_BC) & 0x7F;
79aceca5
FB		 1361}
1362
76a66253
JM		 1363/* Swap temporary saved registers with GPRs */
1364static inline void swap_gpr_tgpr (CPUPPCState *env)
79aceca5 1365{
76a66253
JM		 1366 ppc_gpr_t tmp;
1367
1368 tmp = env->gpr[0];
1369 env->gpr[0] = env->tgpr[0];
1370 env->tgpr[0] = tmp;
1371 tmp = env->gpr[1];
1372 env->gpr[1] = env->tgpr[1];
1373 env->tgpr[1] = tmp;
1374 tmp = env->gpr[2];
1375 env->gpr[2] = env->tgpr[2];
1376 env->tgpr[2] = tmp;
1377 tmp = env->gpr[3];
1378 env->gpr[3] = env->tgpr[3];
1379 env->tgpr[3] = tmp;
79aceca5
FB		 1380}
1381
76a66253
JM		 1382/* GDBstub can read and write MSR... */
1383target_ulong do_load_msr (CPUPPCState *env)
79aceca5 1384{
76a66253
JM		 1385 return
1386#if defined (TARGET_PPC64)
d9bce9d9
JM		 1387 ((target_ulong)msr_sf << MSR_SF) |
1388 ((target_ulong)msr_isf << MSR_ISF) |
1389 ((target_ulong)msr_hv << MSR_HV) |
76a66253 1390#endif
d9bce9d9
JM		 1391 ((target_ulong)msr_ucle << MSR_UCLE) |
1392 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1393 ((target_ulong)msr_ap << MSR_AP) |
1394 ((target_ulong)msr_sa << MSR_SA) |
1395 ((target_ulong)msr_key << MSR_KEY) |
1396 ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
1397 ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
1398 ((target_ulong)msr_ile << MSR_ILE) |
1399 ((target_ulong)msr_ee << MSR_EE) |
1400 ((target_ulong)msr_pr << MSR_PR) |
1401 ((target_ulong)msr_fp << MSR_FP) |
1402 ((target_ulong)msr_me << MSR_ME) |
1403 ((target_ulong)msr_fe0 << MSR_FE0) |
1404 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1405 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1406 ((target_ulong)msr_fe1 << MSR_FE1) |
1407 ((target_ulong)msr_al << MSR_AL) |
1408 ((target_ulong)msr_ip << MSR_IP) |
1409 ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
1410 ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
1411 ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
1412 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1413 ((target_ulong)msr_ri << MSR_RI) |
1414 ((target_ulong)msr_le << MSR_LE);
3fc6c082
FB		 1415}
1416
1417void do_store_msr (CPUPPCState *env, target_ulong value)
313adae9 1418{
50443c98
FB		 1419 int enter_pm;
1420
3fc6c082
FB		 1421 value &= env->msr_mask;
1422 if (((value >> MSR_IR) & 1) != msr_ir ||
1423 ((value >> MSR_DR) & 1) != msr_dr) {
76a66253 1424 /* Flush all tlb when changing translation mode */
d094807b 1425 tlb_flush(env, 1);
3fc6c082 1426 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
a541f297 1427 }
3fc6c082
FB		 1428#if 0
1429 if (loglevel != 0) {
1430 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1431 }
1432#endif
76a66253
JM		 1433 switch (PPC_EXCP(env)) {
1434 case PPC_FLAGS_EXCP_602:
1435 case PPC_FLAGS_EXCP_603:
1436 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1437 /* Swap temporary saved registers with GPRs */
1438 swap_gpr_tgpr(env);
1439 }
1440 break;
1441 default:
1442 break;
1443 }
1444#if defined (TARGET_PPC64)
1445 msr_sf = (value >> MSR_SF) & 1;
1446 msr_isf = (value >> MSR_ISF) & 1;
1447 msr_hv = (value >> MSR_HV) & 1;
1448#endif
1449 msr_ucle = (value >> MSR_UCLE) & 1;
1450 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
1451 msr_ap = (value >> MSR_AP) & 1;
1452 msr_sa = (value >> MSR_SA) & 1;
1453 msr_key = (value >> MSR_KEY) & 1;
1454 msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
1455 msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
1456 msr_ile = (value >> MSR_ILE) & 1;
1457 msr_ee = (value >> MSR_EE) & 1;
1458 msr_pr = (value >> MSR_PR) & 1;
1459 msr_fp = (value >> MSR_FP) & 1;
1460 msr_me = (value >> MSR_ME) & 1;
1461 msr_fe0 = (value >> MSR_FE0) & 1;
1462 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
1463 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
1464 msr_fe1 = (value >> MSR_FE1) & 1;
1465 msr_al = (value >> MSR_AL) & 1;
1466 msr_ip = (value >> MSR_IP) & 1;
1467 msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
1468 msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
1469 msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
1470 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
1471 msr_ri = (value >> MSR_RI) & 1;
1472 msr_le = (value >> MSR_LE) & 1;
3fc6c082 1473 do_compute_hflags(env);
50443c98
FB		 1474
1475 enter_pm = 0;
1476 switch (PPC_EXCP(env)) {
d9bce9d9
JM		 1477 case PPC_FLAGS_EXCP_603:
1478 /* Don't handle SLEEP mode: we should disable all clocks...
1479 * No dynamic power-management.
1480 */
1481 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1482 enter_pm = 1;
1483 break;
1484 case PPC_FLAGS_EXCP_604:
1485 if (msr_pow == 1)
1486 enter_pm = 1;
1487 break;
50443c98 1488 case PPC_FLAGS_EXCP_7x0:
76a66253 1489 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
50443c98
FB		 1490 enter_pm = 1;
1491 break;
1492 default:
1493 break;
1494 }
1495 if (enter_pm) {
e80e1cc4 1496 /* power save: exit cpu loop */
50443c98 1497 env->halted = 1;
e80e1cc4
FB		 1498 env->exception_index = EXCP_HLT;
1499 cpu_loop_exit();
1500 }
3fc6c082
FB		 1501}
1502
d9bce9d9 1503#if defined(TARGET_PPC64)
426613db 1504void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
d9bce9d9 1505{
426613db
JM		 1506 do_store_msr(env,
1507 (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
d9bce9d9
JM		 1508}
1509#endif
1510
76a66253 1511void do_compute_hflags (CPUPPCState *env)
3fc6c082 1512{
76a66253 1513 /* Compute current hflags */
c62db105
JM		 1514 env->hflags = (msr_cm << MSR_CM) | (msr_vr << MSR_VR) |
1515 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
1516 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
1517 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
76a66253 1518#if defined (TARGET_PPC64)
c62db105 1519 /* No care here: PowerPC 64 MSR_SF means the same as MSR_CM for BookE */
d9bce9d9 1520 env->hflags |= (msr_sf << (MSR_SF - 32)) | (msr_hv << (MSR_HV - 32));
4b3686fa 1521#endif
3fc6c082
FB		 1522}
1523
1524/*****************************************************************************/
1525/* Exception processing */
18fba28c 1526#if defined (CONFIG_USER_ONLY)
9a64fbe4 1527void do_interrupt (CPUState *env)
79aceca5 1528{
18fba28c
FB		 1529 env->exception_index = -1;
1530}
47103572 1531
e9df014c 1532void ppc_hw_interrupt (CPUState *env)
47103572
JM		 1533{
1534 env->exception_index = -1;
47103572 1535}
76a66253 1536#else /* defined (CONFIG_USER_ONLY) */
d094807b
FB		 1537static void dump_syscall(CPUState *env)
1538{
d9bce9d9 1539 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1b9eb036 1540 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
d094807b
FB		 1541 env->gpr[0], env->gpr[3], env->gpr[4],
1542 env->gpr[5], env->gpr[6], env->nip);
1543}
1544
18fba28c
FB		 1545void do_interrupt (CPUState *env)
1546{
c62db105
JM		 1547 target_ulong msr, *srr_0, *srr_1, *asrr_0, *asrr_1;
1548 int excp, idx;
79aceca5 1549
18fba28c 1550 excp = env->exception_index;
3fc6c082 1551 msr = do_load_msr(env);
2be0071f
FB		 1552 /* The default is to use SRR0 & SRR1 to save the exception context */
1553 srr_0 = &env->spr[SPR_SRR0];
1554 srr_1 = &env->spr[SPR_SRR1];
c62db105
JM		 1555 asrr_0 = NULL;
1556 asrr_1 = NULL;
9a64fbe4 1557#if defined (DEBUG_EXCEPTIONS)
2be0071f
FB		 1558 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
1559 if (loglevel != 0) {
1b9eb036
JM		 1560 fprintf(logfile,
1561 "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1562 env->nip, excp, env->error_code);
76a66253 1563 cpu_dump_state(env, logfile, fprintf, 0);
b769d8fe 1564 }
79aceca5 1565 }
9a64fbe4 1566#endif
b769d8fe 1567 if (loglevel & CPU_LOG_INT) {
1b9eb036
JM		 1568 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1569 env->nip, excp, env->error_code);
b769d8fe 1570 }
2be0071f 1571 msr_pow = 0;
c62db105 1572 idx = -1;
9a64fbe4
FB		 1573 /* Generate informations in save/restore registers */
1574 switch (excp) {
76a66253 1575 /* Generic PowerPC exceptions */
2be0071f 1576 case EXCP_RESET: /* 0x0100 */
c62db105
JM		 1577 switch (PPC_EXCP(env)) {
1578 case PPC_FLAGS_EXCP_40x:
1579 srr_0 = &env->spr[SPR_40x_SRR2];
1580 srr_1 = &env->spr[SPR_40x_SRR3];
1581 break;
1582 case PPC_FLAGS_EXCP_BOOKE:
1583 idx = 0;
1584 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1585 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1586 break;
1587 default:
2be0071f
FB		 1588 if (msr_ip)
1589 excp += 0xFFC00;
1590 excp |= 0xFFC00000;
c62db105 1591 break;
2be0071f 1592 }
9a64fbe4 1593 goto store_next;
2be0071f 1594 case EXCP_MACHINE_CHECK: /* 0x0200 */
c62db105
JM		 1595 switch (PPC_EXCP(env)) {
1596 case PPC_FLAGS_EXCP_40x:
2be0071f
FB		 1597 srr_0 = &env->spr[SPR_40x_SRR2];
1598 srr_1 = &env->spr[SPR_40x_SRR3];
c62db105
JM		 1599 break;
1600 case PPC_FLAGS_EXCP_BOOKE:
1601 idx = 1;
1602 srr_0 = &env->spr[SPR_BOOKE_MCSRR0];
1603 srr_1 = &env->spr[SPR_BOOKE_MCSRR1];
1604 asrr_0 = &env->spr[SPR_BOOKE_CSRR0];
1605 asrr_1 = &env->spr[SPR_BOOKE_CSRR1];
1606 msr_ce = 0;
1607 break;
1608 default:
1609 break;
2be0071f 1610 }
9a64fbe4
FB		 1611 msr_me = 0;
1612 break;
2be0071f 1613 case EXCP_DSI: /* 0x0300 */
9a64fbe4
FB		 1614 /* Store exception cause */
1615 /* data location address has been stored
1616 * when the fault has been detected
2be0071f 1617 */
c62db105 1618 idx = 2;
76a66253 1619 msr &= ~0xFFFF0000;
a541f297 1620#if defined (DEBUG_EXCEPTIONS)
4a057712 1621 if (loglevel != 0) {
1b9eb036
JM		 1622 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
1623 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
76a66253 1624 }
a541f297
FB		 1625#endif
1626 goto store_next;
2be0071f 1627 case EXCP_ISI: /* 0x0400 */
9a64fbe4 1628 /* Store exception cause */
c62db105 1629 idx = 3;
76a66253 1630 msr &= ~0xFFFF0000;
2be0071f 1631 msr |= env->error_code;
a541f297 1632#if defined (DEBUG_EXCEPTIONS)
76a66253 1633 if (loglevel != 0) {
1b9eb036
JM		 1634 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
1635 "\n", msr, env->nip);
76a66253 1636 }
a541f297 1637#endif
9a64fbe4 1638 goto store_next;
2be0071f 1639 case EXCP_EXTERNAL: /* 0x0500 */
c62db105 1640 idx = 4;
9a64fbe4 1641 goto store_next;
2be0071f 1642 case EXCP_ALIGN: /* 0x0600 */
76a66253 1643 if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
2be0071f 1644 /* Store exception cause */
c62db105 1645 idx = 5;
2be0071f
FB		 1646 /* Get rS/rD and rA from faulting opcode */
1647 env->spr[SPR_DSISR] |=
1648 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1649 /* data location address has been stored
1650 * when the fault has been detected
1651 */
1652 } else {
1653 /* IO error exception on PowerPC 601 */
1654 /* XXX: TODO */
1655 cpu_abort(env,
1656 "601 IO error exception is not implemented yet !\n");
1657 }
9a64fbe4 1658 goto store_current;
2be0071f 1659 case EXCP_PROGRAM: /* 0x0700 */
c62db105 1660 idx = 6;
9a64fbe4
FB		 1661 msr &= ~0xFFFF0000;
1662 switch (env->error_code & ~0xF) {
1663 case EXCP_FP:
1664 if (msr_fe0 == 0 && msr_fe1 == 0) {
1665#if defined (DEBUG_EXCEPTIONS)
4a057712 1666 if (loglevel != 0) {
a496775f
JM		 1667 fprintf(logfile, "Ignore floating point exception\n");
1668 }
9a64fbe4
FB		 1669#endif
1670 return;
76a66253 1671 }
9a64fbe4
FB		 1672 msr |= 0x00100000;
1673 /* Set FX */
1674 env->fpscr[7] |= 0x8;
1675 /* Finally, update FEX */
1676 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1677 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1678 env->fpscr[7] |= 0x4;
76a66253 1679 break;
9a64fbe4 1680 case EXCP_INVAL:
a496775f 1681#if defined (DEBUG_EXCEPTIONS)
4a057712 1682 if (loglevel != 0) {
a496775f
JM		 1683 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
1684 env->nip);
1685 }
1686#endif
9a64fbe4 1687 msr |= 0x00080000;
76a66253 1688 break;
9a64fbe4
FB		 1689 case EXCP_PRIV:
1690 msr |= 0x00040000;
76a66253 1691 break;
9a64fbe4 1692 case EXCP_TRAP:
c62db105 1693 idx = 15;
9a64fbe4
FB		 1694 msr |= 0x00020000;
1695 break;
1696 default:
1697 /* Should never occur */
76a66253
JM		 1698 break;
1699 }
9a64fbe4
FB		 1700 msr |= 0x00010000;
1701 goto store_current;
2be0071f 1702 case EXCP_NO_FP: /* 0x0800 */
c62db105 1703 idx = 7;
4ecc3190 1704 msr &= ~0xFFFF0000;
9a64fbe4
FB		 1705 goto store_current;
1706 case EXCP_DECR:
9a64fbe4 1707 goto store_next;
2be0071f 1708 case EXCP_SYSCALL: /* 0x0C00 */
c62db105 1709 idx = 8;
d094807b
FB		 1710 /* NOTE: this is a temporary hack to support graphics OSI
1711 calls from the MOL driver */
1712 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1713 env->osi_call) {
1714 if (env->osi_call(env) != 0)
1715 return;
1716 }
b769d8fe 1717 if (loglevel & CPU_LOG_INT) {
d094807b 1718 dump_syscall(env);
b769d8fe 1719 }
9a64fbe4 1720 goto store_next;
2be0071f 1721 case EXCP_TRACE: /* 0x0D00 */
2be0071f
FB		 1722 goto store_next;
1723 case EXCP_PERF: /* 0x0F00 */
1724 /* XXX: TODO */
1725 cpu_abort(env,
1726 "Performance counter exception is not implemented yet !\n");
1727 goto store_next;
1728 /* 32 bits PowerPC specific exceptions */
1729 case EXCP_FP_ASSIST: /* 0x0E00 */
1730 /* XXX: TODO */
1731 cpu_abort(env, "Floating point assist exception "
1732 "is not implemented yet !\n");
1733 goto store_next;
76a66253 1734 /* 64 bits PowerPC exceptions */
2be0071f
FB		 1735 case EXCP_DSEG: /* 0x0380 */
1736 /* XXX: TODO */
1737 cpu_abort(env, "Data segment exception is not implemented yet !\n");
9a64fbe4 1738 goto store_next;
2be0071f
FB		 1739 case EXCP_ISEG: /* 0x0480 */
1740 /* XXX: TODO */
1741 cpu_abort(env,
1742 "Instruction segment exception is not implemented yet !\n");
9a64fbe4 1743 goto store_next;
2be0071f 1744 case EXCP_HDECR: /* 0x0980 */
76a66253
JM		 1745 /* XXX: TODO */
1746 cpu_abort(env, "Hypervisor decrementer exception is not implemented "
1747 "yet !\n");
2be0071f
FB		 1748 goto store_next;
1749 /* Implementation specific exceptions */
1750 case 0x0A00:
76a66253
JM		 1751 if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
1752 env->spr[SPR_PVR] == CPU_PPC_G2LE)) {
2be0071f
FB		 1753 /* Critical interrupt on G2 */
1754 /* XXX: TODO */
1755 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1756 goto store_next;
1757 } else {
1758 cpu_abort(env, "Invalid exception 0x0A00 !\n");
1759 }
9a64fbe4 1760 return;
2be0071f 1761 case 0x0F20:
c62db105 1762 idx = 9;
2be0071f
FB		 1763 switch (PPC_EXCP(env)) {
1764 case PPC_FLAGS_EXCP_40x:
1765 /* APU unavailable on 405 */
1766 /* XXX: TODO */
1767 cpu_abort(env,
1768 "APU unavailable exception is not implemented yet !\n");
1769 goto store_next;
1770 case PPC_FLAGS_EXCP_74xx:
1771 /* Altivec unavailable */
1772 /* XXX: TODO */
1773 cpu_abort(env, "Altivec unavailable exception "
1774 "is not implemented yet !\n");
1775 goto store_next;
1776 default:
1777 cpu_abort(env, "Invalid exception 0x0F20 !\n");
1778 break;
1779 }
1780 return;
1781 case 0x1000:
c62db105 1782 idx = 10;
2be0071f
FB		 1783 switch (PPC_EXCP(env)) {
1784 case PPC_FLAGS_EXCP_40x:
1785 /* PIT on 4xx */
c62db105 1786 msr &= ~0xFFFF0000;
a496775f 1787#if defined (DEBUG_EXCEPTIONS)
c62db105
JM		 1788 if (loglevel != 0)
1789 fprintf(logfile, "PIT exception\n");
a496775f 1790#endif
2be0071f
FB		 1791 goto store_next;
1792 case PPC_FLAGS_EXCP_602:
1793 case PPC_FLAGS_EXCP_603:
1794 /* ITLBMISS on 602/603 */
2be0071f 1795 goto store_gprs;
76a66253
JM		 1796 case PPC_FLAGS_EXCP_7x5:
1797 /* ITLBMISS on 745/755 */
1798 goto tlb_miss;
2be0071f
FB		 1799 default:
1800 cpu_abort(env, "Invalid exception 0x1000 !\n");
1801 break;
1802 }
1803 return;
1804 case 0x1010:
c62db105 1805 idx = 11;
2be0071f
FB		 1806 switch (PPC_EXCP(env)) {
1807 case PPC_FLAGS_EXCP_40x:
1808 /* FIT on 4xx */
c62db105 1809 msr &= ~0xFFFF0000;
a496775f 1810#if defined (DEBUG_EXCEPTIONS)
c62db105
JM		 1811 if (loglevel != 0)
1812 fprintf(logfile, "FIT exception\n");
a496775f 1813#endif
2be0071f
FB		 1814 goto store_next;
1815 default:
1816 cpu_abort(env, "Invalid exception 0x1010 !\n");
1817 break;
1818 }
1819 return;
1820 case 0x1020:
c62db105 1821 idx = 12;
2be0071f
FB		 1822 switch (PPC_EXCP(env)) {
1823 case PPC_FLAGS_EXCP_40x:
1824 /* Watchdog on 4xx */
c62db105 1825 msr &= ~0xFFFF0000;
a496775f 1826#if defined (DEBUG_EXCEPTIONS)
c62db105
JM		 1827 if (loglevel != 0)
1828 fprintf(logfile, "WDT exception\n");
a496775f 1829#endif
2be0071f 1830 goto store_next;
c62db105
JM		 1831 case PPC_FLAGS_EXCP_BOOKE:
1832 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1833 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1834 break;
2be0071f
FB		 1835 default:
1836 cpu_abort(env, "Invalid exception 0x1020 !\n");
1837 break;
1838 }
1839 return;
1840 case 0x1100:
c62db105 1841 idx = 13;
2be0071f
FB		 1842 switch (PPC_EXCP(env)) {
1843 case PPC_FLAGS_EXCP_40x:
1844 /* DTLBMISS on 4xx */
a8dea12f 1845 msr &= ~0xFFFF0000;
2be0071f
FB		 1846 goto store_next;
1847 case PPC_FLAGS_EXCP_602:
1848 case PPC_FLAGS_EXCP_603:
1849 /* DLTLBMISS on 602/603 */
2be0071f 1850 goto store_gprs;
76a66253
JM		 1851 case PPC_FLAGS_EXCP_7x5:
1852 /* DLTLBMISS on 745/755 */
1853 goto tlb_miss;
2be0071f
FB		 1854 default:
1855 cpu_abort(env, "Invalid exception 0x1100 !\n");
1856 break;
1857 }
1858 return;
1859 case 0x1200:
c62db105 1860 idx = 14;
2be0071f
FB		 1861 switch (PPC_EXCP(env)) {
1862 case PPC_FLAGS_EXCP_40x:
1863 /* ITLBMISS on 4xx */
a8dea12f 1864 msr &= ~0xFFFF0000;
2be0071f
FB		 1865 goto store_next;
1866 case PPC_FLAGS_EXCP_602:
1867 case PPC_FLAGS_EXCP_603:
1868 /* DSTLBMISS on 602/603 */
2be0071f 1869 store_gprs:
76a66253
JM		 1870 /* Swap temporary saved registers with GPRs */
1871 swap_gpr_tgpr(env);
1872 msr_tgpr = 1;
2be0071f
FB		 1873#if defined (DEBUG_SOFTWARE_TLB)
1874 if (loglevel != 0) {
76a66253
JM		 1875 const unsigned char *es;
1876 target_ulong *miss, *cmp;
1877 int en;
1878 if (excp == 0x1000) {
1879 es = "I";
1880 en = 'I';
1881 miss = &env->spr[SPR_IMISS];
1882 cmp = &env->spr[SPR_ICMP];
1883 } else {
1884 if (excp == 0x1100)
1885 es = "DL";
1886 else
1887 es = "DS";
1888 en = 'D';
1889 miss = &env->spr[SPR_DMISS];
1890 cmp = &env->spr[SPR_DCMP];
1891 }
1b9eb036 1892 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
4a057712 1893 " H1 " ADDRX " H2 " ADDRX " %08x\n",
1b9eb036 1894 es, en, *miss, en, *cmp,
76a66253 1895 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2be0071f
FB		 1896 env->error_code);
1897 }
9a64fbe4 1898#endif
76a66253
JM		 1899 goto tlb_miss;
1900 case PPC_FLAGS_EXCP_7x5:
1901 /* DSTLBMISS on 745/755 */
1902 tlb_miss:
1903 msr &= ~0xF83F0000;
2be0071f
FB		 1904 msr |= env->crf[0] << 28;
1905 msr |= env->error_code; /* key, D/I, S/L bits */
1906 /* Set way using a LRU mechanism */
76a66253 1907 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2be0071f
FB		 1908 goto store_next;
1909 default:
1910 cpu_abort(env, "Invalid exception 0x1200 !\n");
1911 break;
1912 }
1913 return;
1914 case 0x1300:
1915 switch (PPC_EXCP(env)) {
1916 case PPC_FLAGS_EXCP_601:
1917 case PPC_FLAGS_EXCP_602:
1918 case PPC_FLAGS_EXCP_603:
1919 case PPC_FLAGS_EXCP_604:
1920 case PPC_FLAGS_EXCP_7x0:
1921 case PPC_FLAGS_EXCP_7x5:
1922 /* IABR on 6xx/7xx */
1923 /* XXX: TODO */
1924 cpu_abort(env, "IABR exception is not implemented yet !\n");
1925 goto store_next;
1926 default:
1927 cpu_abort(env, "Invalid exception 0x1300 !\n");
1928 break;
1929 }
1930 return;
1931 case 0x1400:
1932 switch (PPC_EXCP(env)) {
1933 case PPC_FLAGS_EXCP_601:
1934 case PPC_FLAGS_EXCP_602:
1935 case PPC_FLAGS_EXCP_603:
1936 case PPC_FLAGS_EXCP_604:
1937 case PPC_FLAGS_EXCP_7x0:
1938 case PPC_FLAGS_EXCP_7x5:
1939 /* SMI on 6xx/7xx */
1940 /* XXX: TODO */
1941 cpu_abort(env, "SMI exception is not implemented yet !\n");
1942 goto store_next;
1943 default:
1944 cpu_abort(env, "Invalid exception 0x1400 !\n");
1945 break;
1946 }
1947 return;
1948 case 0x1500:
1949 switch (PPC_EXCP(env)) {
1950 case PPC_FLAGS_EXCP_602:
1951 /* Watchdog on 602 */
76a66253 1952 /* XXX: TODO */
2be0071f
FB		 1953 cpu_abort(env,
1954 "602 watchdog exception is not implemented yet !\n");
1955 goto store_next;
1956 case PPC_FLAGS_EXCP_970:
1957 /* Soft patch exception on 970 */
1958 /* XXX: TODO */
1959 cpu_abort(env,
1960 "970 soft-patch exception is not implemented yet !\n");
1961 goto store_next;
1962 case PPC_FLAGS_EXCP_74xx:
1963 /* VPU assist on 74xx */
1964 /* XXX: TODO */
1965 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1966 goto store_next;
1967 default:
1968 cpu_abort(env, "Invalid exception 0x1500 !\n");
1969 break;
1970 }
1971 return;
1972 case 0x1600:
1973 switch (PPC_EXCP(env)) {
1974 case PPC_FLAGS_EXCP_602:
1975 /* Emulation trap on 602 */
1976 /* XXX: TODO */
1977 cpu_abort(env, "602 emulation trap exception "
1978 "is not implemented yet !\n");
1979 goto store_next;
1980 case PPC_FLAGS_EXCP_970:
1981 /* Maintenance exception on 970 */
1982 /* XXX: TODO */
1983 cpu_abort(env,
1984 "970 maintenance exception is not implemented yet !\n");
1985 goto store_next;
1986 default:
1987 cpu_abort(env, "Invalid exception 0x1600 !\n");
1988 break;
1989 }
1990 return;
1991 case 0x1700:
1992 switch (PPC_EXCP(env)) {
1993 case PPC_FLAGS_EXCP_7x0:
1994 case PPC_FLAGS_EXCP_7x5:
1995 /* Thermal management interrupt on G3 */
1996 /* XXX: TODO */
1997 cpu_abort(env, "G3 thermal management exception "
1998 "is not implemented yet !\n");
1999 goto store_next;
2000 case PPC_FLAGS_EXCP_970:
2001 /* VPU assist on 970 */
2002 /* XXX: TODO */
2003 cpu_abort(env,
2004 "970 VPU assist exception is not implemented yet !\n");
2005 goto store_next;
2006 default:
2007 cpu_abort(env, "Invalid exception 0x1700 !\n");
2008 break;
2009 }
2010 return;
2011 case 0x1800:
2012 switch (PPC_EXCP(env)) {
2013 case PPC_FLAGS_EXCP_970:
2014 /* Thermal exception on 970 */
2015 /* XXX: TODO */
2016 cpu_abort(env, "970 thermal management exception "
2017 "is not implemented yet !\n");
2018 goto store_next;
2019 default:
2020 cpu_abort(env, "Invalid exception 0x1800 !\n");
2021 break;
2022 }
2023 return;
2024 case 0x2000:
2025 switch (PPC_EXCP(env)) {
2026 case PPC_FLAGS_EXCP_40x:
2027 /* DEBUG on 4xx */
2028 /* XXX: TODO */
2029 cpu_abort(env, "40x debug exception is not implemented yet !\n");
2030 goto store_next;
2031 case PPC_FLAGS_EXCP_601:
2032 /* Run mode exception on 601 */
2033 /* XXX: TODO */
2034 cpu_abort(env,
2035 "601 run mode exception is not implemented yet !\n");
2036 goto store_next;
c62db105
JM		 2037 case PPC_FLAGS_EXCP_BOOKE:
2038 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
2039 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
2040 break;
2be0071f
FB		 2041 default:
2042 cpu_abort(env, "Invalid exception 0x1800 !\n");
2043 break;
2044 }
2045 return;
2046 /* Other exceptions */
2047 /* Qemu internal exceptions:
2048 * we should never come here with those values: abort execution
2049 */
2050 default:
2051 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
9a64fbe4
FB		 2052 return;
2053 store_current:
2be0071f 2054 /* save current instruction location */
c62db105 2055 *srr_0 = env->nip - 4;
9a64fbe4
FB		 2056 break;
2057 store_next:
2be0071f 2058 /* save next instruction location */
c62db105 2059 *srr_0 = env->nip;
9a64fbe4
FB		 2060 break;
2061 }
2be0071f
FB		 2062 /* Save msr */
2063 *srr_1 = msr;
c62db105
JM		 2064 if (asrr_0 != NULL)
2065 *asrr_0 = *srr_0;
2066 if (asrr_1 != NULL)
2067 *asrr_1 = *srr_1;
2be0071f
FB		 2068 /* If we disactivated any translation, flush TLBs */
2069 if (msr_ir || msr_dr) {
2070 tlb_flush(env, 1);
2071 }
9a64fbe4 2072 /* reload MSR with correct bits */
9a64fbe4
FB		 2073 msr_ee = 0;
2074 msr_pr = 0;
2075 msr_fp = 0;
2076 msr_fe0 = 0;
2077 msr_se = 0;
2078 msr_be = 0;
2079 msr_fe1 = 0;
2080 msr_ir = 0;
2081 msr_dr = 0;
2082 msr_ri = 0;
2083 msr_le = msr_ile;
c62db105
JM		 2084 if (PPC_EXCP(env) == PPC_FLAGS_EXCP_BOOKE) {
2085 msr_cm = msr_icm;
2086 if (idx == -1 || (idx >= 16 && idx < 32)) {
2087 cpu_abort(env, "Invalid exception index for excp %d %08x idx %d\n",
2088 excp, excp, idx);
2089 }
2090#if defined(TARGET_PPC64)
2091 if (msr_cm)
2092 env->nip = (uint64_t)env->spr[SPR_BOOKE_IVPR];
2093 else
2094#endif
2095 env->nip = (uint32_t)env->spr[SPR_BOOKE_IVPR];
2096 if (idx < 16)
2097 env->nip |= env->spr[SPR_BOOKE_IVOR0 + idx];
2098 else if (idx < 38)
2099 env->nip |= env->spr[SPR_BOOKE_IVOR32 + idx - 32];
2100 } else {
2101 msr_sf = msr_isf;
2102 env->nip = excp;
2103 }
3fc6c082 2104 do_compute_hflags(env);
9a64fbe4 2105 /* Jump to handler */
9a64fbe4 2106 env->exception_index = EXCP_NONE;
fb0eaffc 2107}
47103572 2108
e9df014c 2109void ppc_hw_interrupt (CPUPPCState *env)
47103572
JM		 2110{
2111 int raised = 0;
2112
a496775f
JM		 2113#if 1
2114 if (loglevel & CPU_LOG_INT) {
2115 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2116 __func__, env, env->pending_interrupts,
2117 env->interrupt_request, msr_me, msr_ee);
2118 }
47103572
JM		 2119#endif
2120 /* Raise it */
2121 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2122 /* External reset / critical input */
e9df014c
JM		 2123 /* XXX: critical input should be handled another way.
2124 * This code is not correct !
2125 */
47103572
JM		 2126 env->exception_index = EXCP_RESET;
2127 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2128 raised = 1;
2129 }
2130 if (raised == 0 && msr_me != 0) {
2131 /* Machine check exception */
2132 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2133 env->exception_index = EXCP_MACHINE_CHECK;
2134 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2135 raised = 1;
2136 }
2137 }
2138 if (raised == 0 && msr_ee != 0) {
2139#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2140 /* Hypervisor decrementer exception */
2141 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2142 env->exception_index = EXCP_HDECR;
2143 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2144 raised = 1;
2145 } else
2146#endif
2147 /* Decrementer exception */
2148 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2149 env->exception_index = EXCP_DECR;
2150 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2151 raised = 1;
2152 /* Programmable interval timer on embedded PowerPC */
2153 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2154 env->exception_index = EXCP_40x_PIT;
2155 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2156 raised = 1;
2157 /* Fixed interval timer on embedded PowerPC */
2158 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2159 env->exception_index = EXCP_40x_FIT;
2160 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2161 raised = 1;
2162 /* Watchdog timer on embedded PowerPC */
2163 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2164 env->exception_index = EXCP_40x_WATCHDOG;
2165 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2166 raised = 1;
2167 /* External interrupt */
2168 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2169 env->exception_index = EXCP_EXTERNAL;
e9df014c
JM		 2170 /* Taking an external interrupt does not clear the external
2171 * interrupt status
2172 */
2173#if 0
47103572 2174 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
e9df014c 2175#endif
47103572 2176 raised = 1;
d0dfae6e
JM		 2177#if 0 // TODO
2178 /* Thermal interrupt */
2179 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2180 env->exception_index = EXCP_970_THRM;
2181 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2182 raised = 1;
2183#endif
47103572
JM		 2184 }
2185#if 0 // TODO
2186 /* External debug exception */
2187 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2188 env->exception_index = EXCP_xxx;
2189 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2190 raised = 1;
2191#endif
2192 }
2193 if (raised != 0) {
2194 env->error_code = 0;
2195 do_interrupt(env);
2196 }
47103572 2197}
18fba28c 2198#endif /* !CONFIG_USER_ONLY */
a496775f
JM		 2199
2200void cpu_dump_EA (target_ulong EA)
2201{
2202 FILE *f;
2203
2204 if (logfile) {
2205 f = logfile;
2206 } else {
2207 f = stdout;
2208 return;
2209 }
4a057712
JM		 2210 fprintf(f, "Memory access at address " ADDRX "\n", EA);
2211}
2212
2213void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2214{
2215 FILE *f;
2216
2217 if (logfile) {
2218 f = logfile;
2219 } else {
2220 f = stdout;
2221 return;
2222 }
2223 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2224 RA, msr);
a496775f
JM		 2225}
2226
0a032cbe
JM		 2227void cpu_ppc_reset (void *opaque)
2228{
2229 CPUPPCState *env;
2230
2231 env = opaque;
2232#if defined (DO_SINGLE_STEP) && 0
2233 /* Single step trace mode */
2234 msr_se = 1;
2235 msr_be = 1;
2236#endif
2237 msr_fp = 1; /* Allow floating point exceptions */
2238 msr_me = 1; /* Allow machine check exceptions */
2239#if defined(TARGET_PPC64)
2240 msr_sf = 0; /* Boot in 32 bits mode */
2241 msr_cm = 0;
2242#endif
2243#if defined(CONFIG_USER_ONLY)
2244 msr_pr = 1;
2245 tlb_flush(env, 1);
2246#else
2247 env->nip = 0xFFFFFFFC;
2248 ppc_tlb_invalidate_all(env);
2249#endif
2250 do_compute_hflags(env);
2251 env->reserve = -1;
2252}
2253
2254CPUPPCState *cpu_ppc_init (void)
2255{
2256 CPUPPCState *env;
2257
2258 env = qemu_mallocz(sizeof(CPUPPCState));
2259 if (!env)
2260 return NULL;
2261 cpu_exec_init(env);
2262 cpu_ppc_reset(env);
2263
2264 return env;
2265}
2266
2267void cpu_ppc_close (CPUPPCState *env)
2268{
2269 /* Should also remove all opcode tables... */
2270 free(env);
2271}
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