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Commit | Line | Data |
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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation helpers for qemu. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
79aceca5 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 18 | */ |
fdabc366 FB |
19 | #include <stdarg.h> |
20 | #include <stdlib.h> | |
21 | #include <stdio.h> | |
22 | #include <string.h> | |
23 | #include <inttypes.h> | |
24 | #include <signal.h> | |
fdabc366 FB |
25 | |
26 | #include "cpu.h" | |
27 | #include "exec-all.h" | |
0411a972 | 28 | #include "helper_regs.h" |
ca10f867 | 29 | #include "qemu-common.h" |
d76d1650 | 30 | #include "kvm.h" |
9a64fbe4 FB |
31 | |
32 | //#define DEBUG_MMU | |
33 | //#define DEBUG_BATS | |
6b542af7 | 34 | //#define DEBUG_SLB |
76a66253 | 35 | //#define DEBUG_SOFTWARE_TLB |
0411a972 | 36 | //#define DUMP_PAGE_TABLES |
9a64fbe4 | 37 | //#define DEBUG_EXCEPTIONS |
fdabc366 | 38 | //#define FLUSH_ALL_TLBS |
9a64fbe4 | 39 | |
d12d51d5 | 40 | #ifdef DEBUG_MMU |
93fcfe39 AL |
41 | # define LOG_MMU(...) qemu_log(__VA_ARGS__) |
42 | # define LOG_MMU_STATE(env) log_cpu_state((env), 0) | |
d12d51d5 AL |
43 | #else |
44 | # define LOG_MMU(...) do { } while (0) | |
45 | # define LOG_MMU_STATE(...) do { } while (0) | |
46 | #endif | |
47 | ||
48 | ||
49 | #ifdef DEBUG_SOFTWARE_TLB | |
93fcfe39 | 50 | # define LOG_SWTLB(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
51 | #else |
52 | # define LOG_SWTLB(...) do { } while (0) | |
53 | #endif | |
54 | ||
55 | #ifdef DEBUG_BATS | |
93fcfe39 | 56 | # define LOG_BATS(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
57 | #else |
58 | # define LOG_BATS(...) do { } while (0) | |
59 | #endif | |
60 | ||
61 | #ifdef DEBUG_SLB | |
93fcfe39 | 62 | # define LOG_SLB(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
63 | #else |
64 | # define LOG_SLB(...) do { } while (0) | |
65 | #endif | |
66 | ||
67 | #ifdef DEBUG_EXCEPTIONS | |
93fcfe39 | 68 | # define LOG_EXCP(...) qemu_log(__VA_ARGS__) |
d12d51d5 AL |
69 | #else |
70 | # define LOG_EXCP(...) do { } while (0) | |
71 | #endif | |
72 | ||
73 | ||
64adab3f | 74 | /*****************************************************************************/ |
3fc6c082 | 75 | /* PowerPC MMU emulation */ |
a541f297 | 76 | |
d9bce9d9 | 77 | #if defined(CONFIG_USER_ONLY) |
e96efcfc | 78 | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 79 | int mmu_idx, int is_softmmu) |
24741ef3 FB |
80 | { |
81 | int exception, error_code; | |
d9bce9d9 | 82 | |
24741ef3 | 83 | if (rw == 2) { |
e1833e1f | 84 | exception = POWERPC_EXCP_ISI; |
8f793433 | 85 | error_code = 0x40000000; |
24741ef3 | 86 | } else { |
e1833e1f | 87 | exception = POWERPC_EXCP_DSI; |
8f793433 | 88 | error_code = 0x40000000; |
24741ef3 FB |
89 | if (rw) |
90 | error_code |= 0x02000000; | |
91 | env->spr[SPR_DAR] = address; | |
92 | env->spr[SPR_DSISR] = error_code; | |
93 | } | |
94 | env->exception_index = exception; | |
95 | env->error_code = error_code; | |
76a66253 | 96 | |
24741ef3 FB |
97 | return 1; |
98 | } | |
76a66253 | 99 | |
99a0949b | 100 | a_target_phys_addr cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
24741ef3 FB |
101 | { |
102 | return addr; | |
103 | } | |
36081602 | 104 | |
24741ef3 | 105 | #else |
76a66253 | 106 | /* Common routines used by software and hardware TLBs emulation */ |
636aa200 | 107 | static inline int pte_is_valid(target_ulong pte0) |
76a66253 JM |
108 | { |
109 | return pte0 & 0x80000000 ? 1 : 0; | |
110 | } | |
111 | ||
636aa200 | 112 | static inline void pte_invalidate(target_ulong *pte0) |
76a66253 JM |
113 | { |
114 | *pte0 &= ~0x80000000; | |
115 | } | |
116 | ||
caa4039c | 117 | #if defined(TARGET_PPC64) |
636aa200 | 118 | static inline int pte64_is_valid(target_ulong pte0) |
caa4039c JM |
119 | { |
120 | return pte0 & 0x0000000000000001ULL ? 1 : 0; | |
121 | } | |
122 | ||
636aa200 | 123 | static inline void pte64_invalidate(target_ulong *pte0) |
caa4039c JM |
124 | { |
125 | *pte0 &= ~0x0000000000000001ULL; | |
126 | } | |
127 | #endif | |
128 | ||
76a66253 JM |
129 | #define PTE_PTEM_MASK 0x7FFFFFBF |
130 | #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B) | |
caa4039c JM |
131 | #if defined(TARGET_PPC64) |
132 | #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL | |
133 | #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F) | |
134 | #endif | |
76a66253 | 135 | |
636aa200 | 136 | static inline int pp_check(int key, int pp, int nx) |
b227a8e9 JM |
137 | { |
138 | int access; | |
139 | ||
140 | /* Compute access rights */ | |
141 | /* When pp is 3/7, the result is undefined. Set it to noaccess */ | |
142 | access = 0; | |
143 | if (key == 0) { | |
144 | switch (pp) { | |
145 | case 0x0: | |
146 | case 0x1: | |
147 | case 0x2: | |
148 | access |= PAGE_WRITE; | |
149 | /* No break here */ | |
150 | case 0x3: | |
151 | case 0x6: | |
152 | access |= PAGE_READ; | |
153 | break; | |
154 | } | |
155 | } else { | |
156 | switch (pp) { | |
157 | case 0x0: | |
158 | case 0x6: | |
159 | access = 0; | |
160 | break; | |
161 | case 0x1: | |
162 | case 0x3: | |
163 | access = PAGE_READ; | |
164 | break; | |
165 | case 0x2: | |
166 | access = PAGE_READ | PAGE_WRITE; | |
167 | break; | |
168 | } | |
169 | } | |
170 | if (nx == 0) | |
171 | access |= PAGE_EXEC; | |
172 | ||
173 | return access; | |
174 | } | |
175 | ||
636aa200 | 176 | static inline int check_prot(int prot, int rw, int access_type) |
b227a8e9 JM |
177 | { |
178 | int ret; | |
179 | ||
180 | if (access_type == ACCESS_CODE) { | |
181 | if (prot & PAGE_EXEC) | |
182 | ret = 0; | |
183 | else | |
184 | ret = -2; | |
185 | } else if (rw) { | |
186 | if (prot & PAGE_WRITE) | |
187 | ret = 0; | |
188 | else | |
189 | ret = -2; | |
190 | } else { | |
191 | if (prot & PAGE_READ) | |
192 | ret = 0; | |
193 | else | |
194 | ret = -2; | |
195 | } | |
196 | ||
197 | return ret; | |
198 | } | |
199 | ||
99a0949b | 200 | static inline int _pte_check(a_mmu_ctx *ctx, int is_64b, target_ulong pte0, |
636aa200 | 201 | target_ulong pte1, int h, int rw, int type) |
76a66253 | 202 | { |
caa4039c | 203 | target_ulong ptem, mmask; |
b227a8e9 | 204 | int access, ret, pteh, ptev, pp; |
76a66253 JM |
205 | |
206 | access = 0; | |
207 | ret = -1; | |
208 | /* Check validity and table match */ | |
caa4039c JM |
209 | #if defined(TARGET_PPC64) |
210 | if (is_64b) { | |
211 | ptev = pte64_is_valid(pte0); | |
212 | pteh = (pte0 >> 1) & 1; | |
213 | } else | |
214 | #endif | |
215 | { | |
216 | ptev = pte_is_valid(pte0); | |
217 | pteh = (pte0 >> 6) & 1; | |
218 | } | |
219 | if (ptev && h == pteh) { | |
76a66253 | 220 | /* Check vsid & api */ |
caa4039c JM |
221 | #if defined(TARGET_PPC64) |
222 | if (is_64b) { | |
223 | ptem = pte0 & PTE64_PTEM_MASK; | |
224 | mmask = PTE64_CHECK_MASK; | |
b227a8e9 | 225 | pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004); |
29c8ca6f | 226 | ctx->nx = (pte1 >> 2) & 1; /* No execute bit */ |
b227a8e9 | 227 | ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */ |
caa4039c JM |
228 | } else |
229 | #endif | |
230 | { | |
231 | ptem = pte0 & PTE_PTEM_MASK; | |
232 | mmask = PTE_CHECK_MASK; | |
b227a8e9 | 233 | pp = pte1 & 0x00000003; |
caa4039c JM |
234 | } |
235 | if (ptem == ctx->ptem) { | |
99a0949b | 236 | if (ctx->raddr != (a_target_phys_addr)-1ULL) { |
76a66253 | 237 | /* all matches should have equal RPN, WIMG & PP */ |
caa4039c | 238 | if ((ctx->raddr & mmask) != (pte1 & mmask)) { |
93fcfe39 | 239 | qemu_log("Bad RPN/WIMG/PP\n"); |
76a66253 JM |
240 | return -3; |
241 | } | |
242 | } | |
243 | /* Compute access rights */ | |
b227a8e9 | 244 | access = pp_check(ctx->key, pp, ctx->nx); |
76a66253 JM |
245 | /* Keep the matching PTE informations */ |
246 | ctx->raddr = pte1; | |
247 | ctx->prot = access; | |
b227a8e9 JM |
248 | ret = check_prot(ctx->prot, rw, type); |
249 | if (ret == 0) { | |
76a66253 | 250 | /* Access granted */ |
d12d51d5 | 251 | LOG_MMU("PTE access granted !\n"); |
76a66253 JM |
252 | } else { |
253 | /* Access right violation */ | |
d12d51d5 | 254 | LOG_MMU("PTE access rejected\n"); |
76a66253 JM |
255 | } |
256 | } | |
257 | } | |
258 | ||
259 | return ret; | |
260 | } | |
261 | ||
99a0949b | 262 | static inline int pte32_check(a_mmu_ctx *ctx, target_ulong pte0, |
636aa200 | 263 | target_ulong pte1, int h, int rw, int type) |
caa4039c | 264 | { |
b227a8e9 | 265 | return _pte_check(ctx, 0, pte0, pte1, h, rw, type); |
caa4039c JM |
266 | } |
267 | ||
268 | #if defined(TARGET_PPC64) | |
99a0949b | 269 | static inline int pte64_check(a_mmu_ctx *ctx, target_ulong pte0, |
636aa200 | 270 | target_ulong pte1, int h, int rw, int type) |
caa4039c | 271 | { |
b227a8e9 | 272 | return _pte_check(ctx, 1, pte0, pte1, h, rw, type); |
caa4039c JM |
273 | } |
274 | #endif | |
275 | ||
99a0949b | 276 | static inline int pte_update_flags(a_mmu_ctx *ctx, target_ulong *pte1p, |
636aa200 | 277 | int ret, int rw) |
76a66253 JM |
278 | { |
279 | int store = 0; | |
280 | ||
281 | /* Update page flags */ | |
282 | if (!(*pte1p & 0x00000100)) { | |
283 | /* Update accessed flag */ | |
284 | *pte1p |= 0x00000100; | |
285 | store = 1; | |
286 | } | |
287 | if (!(*pte1p & 0x00000080)) { | |
288 | if (rw == 1 && ret == 0) { | |
289 | /* Update changed flag */ | |
290 | *pte1p |= 0x00000080; | |
291 | store = 1; | |
292 | } else { | |
293 | /* Force page fault for first write access */ | |
294 | ctx->prot &= ~PAGE_WRITE; | |
295 | } | |
296 | } | |
297 | ||
298 | return store; | |
299 | } | |
300 | ||
301 | /* Software driven TLB helpers */ | |
636aa200 BS |
302 | static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way, |
303 | int is_code) | |
76a66253 JM |
304 | { |
305 | int nr; | |
306 | ||
307 | /* Select TLB num in a way from address */ | |
308 | nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1); | |
309 | /* Select TLB way */ | |
310 | nr += env->tlb_per_way * way; | |
311 | /* 6xx have separate TLBs for instructions and data */ | |
312 | if (is_code && env->id_tlbs == 1) | |
313 | nr += env->nb_tlb; | |
314 | ||
315 | return nr; | |
316 | } | |
317 | ||
636aa200 | 318 | static inline void ppc6xx_tlb_invalidate_all(CPUState *env) |
76a66253 | 319 | { |
99a0949b | 320 | a_ppc6xx_tlb *tlb; |
76a66253 JM |
321 | int nr, max; |
322 | ||
d12d51d5 | 323 | //LOG_SWTLB("Invalidate all TLBs\n"); |
76a66253 JM |
324 | /* Invalidate all defined software TLB */ |
325 | max = env->nb_tlb; | |
326 | if (env->id_tlbs == 1) | |
327 | max *= 2; | |
328 | for (nr = 0; nr < max; nr++) { | |
1d0a48fb | 329 | tlb = &env->tlb[nr].tlb6; |
76a66253 JM |
330 | pte_invalidate(&tlb->pte0); |
331 | } | |
76a66253 | 332 | tlb_flush(env, 1); |
76a66253 JM |
333 | } |
334 | ||
636aa200 BS |
335 | static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env, |
336 | target_ulong eaddr, | |
337 | int is_code, int match_epn) | |
76a66253 | 338 | { |
4a057712 | 339 | #if !defined(FLUSH_ALL_TLBS) |
99a0949b | 340 | a_ppc6xx_tlb *tlb; |
76a66253 JM |
341 | int way, nr; |
342 | ||
76a66253 JM |
343 | /* Invalidate ITLB + DTLB, all ways */ |
344 | for (way = 0; way < env->nb_ways; way++) { | |
345 | nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); | |
1d0a48fb | 346 | tlb = &env->tlb[nr].tlb6; |
76a66253 | 347 | if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { |
90e189ec BS |
348 | LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr, |
349 | env->nb_tlb, eaddr); | |
76a66253 JM |
350 | pte_invalidate(&tlb->pte0); |
351 | tlb_flush_page(env, tlb->EPN); | |
352 | } | |
353 | } | |
354 | #else | |
355 | /* XXX: PowerPC specification say this is valid as well */ | |
356 | ppc6xx_tlb_invalidate_all(env); | |
357 | #endif | |
358 | } | |
359 | ||
636aa200 BS |
360 | static inline void ppc6xx_tlb_invalidate_virt(CPUState *env, |
361 | target_ulong eaddr, int is_code) | |
76a66253 JM |
362 | { |
363 | __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0); | |
364 | } | |
365 | ||
366 | void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, | |
367 | target_ulong pte0, target_ulong pte1) | |
368 | { | |
99a0949b | 369 | a_ppc6xx_tlb *tlb; |
76a66253 JM |
370 | int nr; |
371 | ||
372 | nr = ppc6xx_tlb_getnum(env, EPN, way, is_code); | |
1d0a48fb | 373 | tlb = &env->tlb[nr].tlb6; |
90e189ec BS |
374 | LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx |
375 | " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1); | |
76a66253 JM |
376 | /* Invalidate any pending reference in Qemu for this virtual address */ |
377 | __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1); | |
378 | tlb->pte0 = pte0; | |
379 | tlb->pte1 = pte1; | |
380 | tlb->EPN = EPN; | |
76a66253 JM |
381 | /* Store last way for LRU mechanism */ |
382 | env->last_way = way; | |
383 | } | |
384 | ||
99a0949b | 385 | static inline int ppc6xx_tlb_check(CPUState *env, a_mmu_ctx *ctx, |
636aa200 | 386 | target_ulong eaddr, int rw, int access_type) |
76a66253 | 387 | { |
99a0949b | 388 | a_ppc6xx_tlb *tlb; |
76a66253 JM |
389 | int nr, best, way; |
390 | int ret; | |
d9bce9d9 | 391 | |
76a66253 JM |
392 | best = -1; |
393 | ret = -1; /* No TLB found */ | |
394 | for (way = 0; way < env->nb_ways; way++) { | |
395 | nr = ppc6xx_tlb_getnum(env, eaddr, way, | |
396 | access_type == ACCESS_CODE ? 1 : 0); | |
1d0a48fb | 397 | tlb = &env->tlb[nr].tlb6; |
76a66253 JM |
398 | /* This test "emulates" the PTE index match for hardware TLBs */ |
399 | if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { | |
90e189ec BS |
400 | LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx |
401 | "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb, | |
402 | pte_is_valid(tlb->pte0) ? "valid" : "inval", | |
403 | tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); | |
76a66253 JM |
404 | continue; |
405 | } | |
90e189ec BS |
406 | LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " " |
407 | TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb, | |
408 | pte_is_valid(tlb->pte0) ? "valid" : "inval", | |
409 | tlb->EPN, eaddr, tlb->pte1, | |
410 | rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D'); | |
b227a8e9 | 411 | switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) { |
76a66253 JM |
412 | case -3: |
413 | /* TLB inconsistency */ | |
414 | return -1; | |
415 | case -2: | |
416 | /* Access violation */ | |
417 | ret = -2; | |
418 | best = nr; | |
419 | break; | |
420 | case -1: | |
421 | default: | |
422 | /* No match */ | |
423 | break; | |
424 | case 0: | |
425 | /* access granted */ | |
426 | /* XXX: we should go on looping to check all TLBs consistency | |
427 | * but we can speed-up the whole thing as the | |
428 | * result would be undefined if TLBs are not consistent. | |
429 | */ | |
430 | ret = 0; | |
431 | best = nr; | |
432 | goto done; | |
433 | } | |
434 | } | |
435 | if (best != -1) { | |
436 | done: | |
90e189ec BS |
437 | LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n", |
438 | ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); | |
76a66253 | 439 | /* Update page flags */ |
1d0a48fb | 440 | pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw); |
76a66253 JM |
441 | } |
442 | ||
443 | return ret; | |
444 | } | |
445 | ||
9a64fbe4 | 446 | /* Perform BAT hit & translation */ |
636aa200 BS |
447 | static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp, |
448 | int *protp, target_ulong *BATu, | |
449 | target_ulong *BATl) | |
faadf50e JM |
450 | { |
451 | target_ulong bl; | |
452 | int pp, valid, prot; | |
453 | ||
454 | bl = (*BATu & 0x00001FFC) << 15; | |
455 | valid = 0; | |
456 | prot = 0; | |
457 | if (((msr_pr == 0) && (*BATu & 0x00000002)) || | |
458 | ((msr_pr != 0) && (*BATu & 0x00000001))) { | |
459 | valid = 1; | |
460 | pp = *BATl & 0x00000003; | |
461 | if (pp != 0) { | |
462 | prot = PAGE_READ | PAGE_EXEC; | |
463 | if (pp == 0x2) | |
464 | prot |= PAGE_WRITE; | |
465 | } | |
466 | } | |
467 | *blp = bl; | |
468 | *validp = valid; | |
469 | *protp = prot; | |
470 | } | |
471 | ||
636aa200 BS |
472 | static inline void bat_601_size_prot(CPUState *env, target_ulong *blp, |
473 | int *validp, int *protp, | |
474 | target_ulong *BATu, target_ulong *BATl) | |
faadf50e JM |
475 | { |
476 | target_ulong bl; | |
477 | int key, pp, valid, prot; | |
478 | ||
479 | bl = (*BATl & 0x0000003F) << 17; | |
90e189ec BS |
480 | LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n", |
481 | (uint8_t)(*BATl & 0x0000003F), bl, ~bl); | |
faadf50e JM |
482 | prot = 0; |
483 | valid = (*BATl >> 6) & 1; | |
484 | if (valid) { | |
485 | pp = *BATu & 0x00000003; | |
486 | if (msr_pr == 0) | |
487 | key = (*BATu >> 3) & 1; | |
488 | else | |
489 | key = (*BATu >> 2) & 1; | |
490 | prot = pp_check(key, pp, 0); | |
491 | } | |
492 | *blp = bl; | |
493 | *validp = valid; | |
494 | *protp = prot; | |
495 | } | |
496 | ||
99a0949b | 497 | static inline int get_bat(CPUState *env, a_mmu_ctx *ctx, target_ulong virtual, |
636aa200 | 498 | int rw, int type) |
9a64fbe4 | 499 | { |
76a66253 JM |
500 | target_ulong *BATlt, *BATut, *BATu, *BATl; |
501 | target_ulong base, BEPIl, BEPIu, bl; | |
faadf50e | 502 | int i, valid, prot; |
9a64fbe4 FB |
503 | int ret = -1; |
504 | ||
90e189ec BS |
505 | LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__, |
506 | type == ACCESS_CODE ? 'I' : 'D', virtual); | |
9a64fbe4 FB |
507 | switch (type) { |
508 | case ACCESS_CODE: | |
509 | BATlt = env->IBAT[1]; | |
510 | BATut = env->IBAT[0]; | |
511 | break; | |
512 | default: | |
513 | BATlt = env->DBAT[1]; | |
514 | BATut = env->DBAT[0]; | |
515 | break; | |
516 | } | |
9a64fbe4 | 517 | base = virtual & 0xFFFC0000; |
faadf50e | 518 | for (i = 0; i < env->nb_BATs; i++) { |
9a64fbe4 FB |
519 | BATu = &BATut[i]; |
520 | BATl = &BATlt[i]; | |
521 | BEPIu = *BATu & 0xF0000000; | |
522 | BEPIl = *BATu & 0x0FFE0000; | |
faadf50e JM |
523 | if (unlikely(env->mmu_model == POWERPC_MMU_601)) { |
524 | bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl); | |
525 | } else { | |
526 | bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); | |
527 | } | |
90e189ec BS |
528 | LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx |
529 | " BATl " TARGET_FMT_lx "\n", __func__, | |
530 | type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl); | |
9a64fbe4 FB |
531 | if ((virtual & 0xF0000000) == BEPIu && |
532 | ((virtual & 0x0FFE0000) & ~bl) == BEPIl) { | |
533 | /* BAT matches */ | |
faadf50e | 534 | if (valid != 0) { |
9a64fbe4 | 535 | /* Get physical address */ |
76a66253 | 536 | ctx->raddr = (*BATl & 0xF0000000) | |
9a64fbe4 | 537 | ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) | |
a541f297 | 538 | (virtual & 0x0001F000); |
b227a8e9 | 539 | /* Compute access rights */ |
faadf50e | 540 | ctx->prot = prot; |
b227a8e9 | 541 | ret = check_prot(ctx->prot, rw, type); |
d12d51d5 | 542 | if (ret == 0) |
90e189ec | 543 | LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n", |
d12d51d5 AL |
544 | i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', |
545 | ctx->prot & PAGE_WRITE ? 'W' : '-'); | |
9a64fbe4 FB |
546 | break; |
547 | } | |
548 | } | |
549 | } | |
550 | if (ret < 0) { | |
d12d51d5 | 551 | #if defined(DEBUG_BATS) |
0bf9e31a | 552 | if (qemu_log_enabled()) { |
90e189ec | 553 | LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual); |
4a057712 JM |
554 | for (i = 0; i < 4; i++) { |
555 | BATu = &BATut[i]; | |
556 | BATl = &BATlt[i]; | |
557 | BEPIu = *BATu & 0xF0000000; | |
558 | BEPIl = *BATu & 0x0FFE0000; | |
559 | bl = (*BATu & 0x00001FFC) << 15; | |
90e189ec BS |
560 | LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx |
561 | " BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " " | |
562 | TARGET_FMT_lx " " TARGET_FMT_lx "\n", | |
0bf9e31a BS |
563 | __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual, |
564 | *BATu, *BATl, BEPIu, BEPIl, bl); | |
4a057712 | 565 | } |
9a64fbe4 FB |
566 | } |
567 | #endif | |
9a64fbe4 FB |
568 | } |
569 | /* No hit */ | |
570 | return ret; | |
571 | } | |
572 | ||
573 | /* PTE table lookup */ | |
99a0949b | 574 | static inline int _find_pte(a_mmu_ctx *ctx, int is_64b, int h, int rw, |
636aa200 | 575 | int type, int target_page_bits) |
9a64fbe4 | 576 | { |
76a66253 JM |
577 | target_ulong base, pte0, pte1; |
578 | int i, good = -1; | |
caa4039c | 579 | int ret, r; |
9a64fbe4 | 580 | |
76a66253 JM |
581 | ret = -1; /* No entry found */ |
582 | base = ctx->pg_addr[h]; | |
9a64fbe4 | 583 | for (i = 0; i < 8; i++) { |
caa4039c JM |
584 | #if defined(TARGET_PPC64) |
585 | if (is_64b) { | |
586 | pte0 = ldq_phys(base + (i * 16)); | |
5b5aba4f BS |
587 | pte1 = ldq_phys(base + (i * 16) + 8); |
588 | ||
589 | /* We have a TLB that saves 4K pages, so let's | |
590 | * split a huge page to 4k chunks */ | |
591 | if (target_page_bits != TARGET_PAGE_BITS) | |
592 | pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1)) | |
593 | & TARGET_PAGE_MASK; | |
594 | ||
b227a8e9 | 595 | r = pte64_check(ctx, pte0, pte1, h, rw, type); |
90e189ec BS |
596 | LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " |
597 | TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", | |
598 | base + (i * 16), pte0, pte1, (int)(pte0 & 1), h, | |
599 | (int)((pte0 >> 1) & 1), ctx->ptem); | |
caa4039c JM |
600 | } else |
601 | #endif | |
602 | { | |
603 | pte0 = ldl_phys(base + (i * 8)); | |
604 | pte1 = ldl_phys(base + (i * 8) + 4); | |
b227a8e9 | 605 | r = pte32_check(ctx, pte0, pte1, h, rw, type); |
90e189ec BS |
606 | LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " " |
607 | TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n", | |
608 | base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h, | |
609 | (int)((pte0 >> 6) & 1), ctx->ptem); | |
12de9a39 | 610 | } |
caa4039c | 611 | switch (r) { |
76a66253 JM |
612 | case -3: |
613 | /* PTE inconsistency */ | |
614 | return -1; | |
615 | case -2: | |
616 | /* Access violation */ | |
617 | ret = -2; | |
618 | good = i; | |
619 | break; | |
620 | case -1: | |
621 | default: | |
622 | /* No PTE match */ | |
623 | break; | |
624 | case 0: | |
625 | /* access granted */ | |
626 | /* XXX: we should go on looping to check all PTEs consistency | |
627 | * but if we can speed-up the whole thing as the | |
628 | * result would be undefined if PTEs are not consistent. | |
629 | */ | |
630 | ret = 0; | |
631 | good = i; | |
632 | goto done; | |
9a64fbe4 FB |
633 | } |
634 | } | |
635 | if (good != -1) { | |
76a66253 | 636 | done: |
90e189ec BS |
637 | LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n", |
638 | ctx->raddr, ctx->prot, ret); | |
9a64fbe4 | 639 | /* Update page flags */ |
76a66253 | 640 | pte1 = ctx->raddr; |
caa4039c JM |
641 | if (pte_update_flags(ctx, &pte1, ret, rw) == 1) { |
642 | #if defined(TARGET_PPC64) | |
643 | if (is_64b) { | |
644 | stq_phys_notdirty(base + (good * 16) + 8, pte1); | |
645 | } else | |
646 | #endif | |
647 | { | |
648 | stl_phys_notdirty(base + (good * 8) + 4, pte1); | |
649 | } | |
650 | } | |
9a64fbe4 FB |
651 | } |
652 | ||
653 | return ret; | |
79aceca5 FB |
654 | } |
655 | ||
99a0949b | 656 | static inline int find_pte32(a_mmu_ctx *ctx, int h, int rw, int type, |
636aa200 | 657 | int target_page_bits) |
caa4039c | 658 | { |
5b5aba4f | 659 | return _find_pte(ctx, 0, h, rw, type, target_page_bits); |
caa4039c JM |
660 | } |
661 | ||
662 | #if defined(TARGET_PPC64) | |
99a0949b | 663 | static inline int find_pte64(a_mmu_ctx *ctx, int h, int rw, int type, |
636aa200 | 664 | int target_page_bits) |
caa4039c | 665 | { |
5b5aba4f | 666 | return _find_pte(ctx, 1, h, rw, type, target_page_bits); |
caa4039c JM |
667 | } |
668 | #endif | |
669 | ||
99a0949b | 670 | static inline int find_pte(CPUState *env, a_mmu_ctx *ctx, int h, int rw, |
636aa200 | 671 | int type, int target_page_bits) |
caa4039c JM |
672 | { |
673 | #if defined(TARGET_PPC64) | |
add78955 | 674 | if (env->mmu_model & POWERPC_MMU_64) |
5b5aba4f | 675 | return find_pte64(ctx, h, rw, type, target_page_bits); |
caa4039c JM |
676 | #endif |
677 | ||
5b5aba4f | 678 | return find_pte32(ctx, h, rw, type, target_page_bits); |
caa4039c JM |
679 | } |
680 | ||
caa4039c | 681 | #if defined(TARGET_PPC64) |
99a0949b | 682 | static a_ppc_slb *slb_get_entry(CPUPPCState *env, int nr) |
eacc3249 | 683 | { |
99a0949b | 684 | a_ppc_slb *retval = &env->slb[nr]; |
8eee0af9 BS |
685 | |
686 | #if 0 // XXX implement bridge mode? | |
687 | if (env->spr[SPR_ASR] & 1) { | |
99a0949b | 688 | a_target_phys_addr sr_base; |
8eee0af9 BS |
689 | |
690 | sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000; | |
691 | sr_base += (12 * nr); | |
692 | ||
693 | retval->tmp64 = ldq_phys(sr_base); | |
694 | retval->tmp = ldl_phys(sr_base + 8); | |
695 | } | |
696 | #endif | |
697 | ||
698 | return retval; | |
eacc3249 JM |
699 | } |
700 | ||
99a0949b | 701 | static void slb_set_entry(CPUPPCState *env, int nr, a_ppc_slb *slb) |
eacc3249 | 702 | { |
99a0949b | 703 | a_ppc_slb *entry = &env->slb[nr]; |
8eee0af9 BS |
704 | |
705 | if (slb == entry) | |
706 | return; | |
707 | ||
708 | entry->tmp64 = slb->tmp64; | |
709 | entry->tmp = slb->tmp; | |
710 | } | |
711 | ||
99a0949b | 712 | static inline int slb_is_valid(a_ppc_slb *slb) |
8eee0af9 BS |
713 | { |
714 | return (int)(slb->tmp64 & 0x0000000008000000ULL); | |
715 | } | |
716 | ||
99a0949b | 717 | static inline void slb_invalidate(a_ppc_slb *slb) |
8eee0af9 BS |
718 | { |
719 | slb->tmp64 &= ~0x0000000008000000ULL; | |
eacc3249 JM |
720 | } |
721 | ||
636aa200 BS |
722 | static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr, |
723 | target_ulong *vsid, target_ulong *page_mask, | |
724 | int *attr, int *target_page_bits) | |
caa4039c | 725 | { |
caa4039c | 726 | target_ulong mask; |
caa4039c | 727 | int n, ret; |
caa4039c JM |
728 | |
729 | ret = -5; | |
90e189ec | 730 | LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); |
caa4039c | 731 | mask = 0x0000000000000000ULL; /* Avoid gcc warning */ |
eacc3249 | 732 | for (n = 0; n < env->slb_nr; n++) { |
99a0949b | 733 | a_ppc_slb *slb = slb_get_entry(env, n); |
8eee0af9 BS |
734 | |
735 | LOG_SLB("%s: seg %d %016" PRIx64 " %08" | |
736 | PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp); | |
737 | if (slb_is_valid(slb)) { | |
caa4039c | 738 | /* SLB entry is valid */ |
8eee0af9 | 739 | if (slb->tmp & 0x8) { |
5b5aba4f | 740 | /* 1 TB Segment */ |
caa4039c | 741 | mask = 0xFFFF000000000000ULL; |
5b5aba4f BS |
742 | if (target_page_bits) |
743 | *target_page_bits = 24; // XXX 16M pages? | |
744 | } else { | |
745 | /* 256MB Segment */ | |
746 | mask = 0xFFFFFFFFF0000000ULL; | |
747 | if (target_page_bits) | |
748 | *target_page_bits = TARGET_PAGE_BITS; | |
caa4039c | 749 | } |
8eee0af9 | 750 | if ((eaddr & mask) == (slb->tmp64 & mask)) { |
caa4039c | 751 | /* SLB match */ |
8eee0af9 | 752 | *vsid = ((slb->tmp64 << 24) | (slb->tmp >> 8)) & 0x0003FFFFFFFFFFFFULL; |
caa4039c | 753 | *page_mask = ~mask; |
8eee0af9 | 754 | *attr = slb->tmp & 0xFF; |
eacc3249 | 755 | ret = n; |
caa4039c JM |
756 | break; |
757 | } | |
758 | } | |
caa4039c JM |
759 | } |
760 | ||
761 | return ret; | |
79aceca5 | 762 | } |
12de9a39 | 763 | |
eacc3249 JM |
764 | void ppc_slb_invalidate_all (CPUPPCState *env) |
765 | { | |
eacc3249 JM |
766 | int n, do_invalidate; |
767 | ||
768 | do_invalidate = 0; | |
2c1ee068 JM |
769 | /* XXX: Warning: slbia never invalidates the first segment */ |
770 | for (n = 1; n < env->slb_nr; n++) { | |
99a0949b | 771 | a_ppc_slb *slb = slb_get_entry(env, n); |
8eee0af9 BS |
772 | |
773 | if (slb_is_valid(slb)) { | |
774 | slb_invalidate(slb); | |
775 | slb_set_entry(env, n, slb); | |
eacc3249 JM |
776 | /* XXX: given the fact that segment size is 256 MB or 1TB, |
777 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
778 | * in Qemu, we just invalidate all TLBs | |
779 | */ | |
780 | do_invalidate = 1; | |
781 | } | |
eacc3249 JM |
782 | } |
783 | if (do_invalidate) | |
784 | tlb_flush(env, 1); | |
785 | } | |
786 | ||
787 | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0) | |
788 | { | |
eacc3249 | 789 | target_ulong vsid, page_mask; |
eacc3249 JM |
790 | int attr; |
791 | int n; | |
792 | ||
5b5aba4f | 793 | n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL); |
eacc3249 | 794 | if (n >= 0) { |
99a0949b | 795 | a_ppc_slb *slb = slb_get_entry(env, n); |
8eee0af9 BS |
796 | |
797 | if (slb_is_valid(slb)) { | |
798 | slb_invalidate(slb); | |
799 | slb_set_entry(env, n, slb); | |
eacc3249 JM |
800 | /* XXX: given the fact that segment size is 256 MB or 1TB, |
801 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
802 | * in Qemu, we just invalidate all TLBs | |
803 | */ | |
804 | tlb_flush(env, 1); | |
805 | } | |
806 | } | |
807 | } | |
808 | ||
12de9a39 JM |
809 | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr) |
810 | { | |
12de9a39 | 811 | target_ulong rt; |
99a0949b | 812 | a_ppc_slb *slb = slb_get_entry(env, slb_nr); |
8eee0af9 BS |
813 | |
814 | if (slb_is_valid(slb)) { | |
12de9a39 JM |
815 | /* SLB entry is valid */ |
816 | /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */ | |
8eee0af9 BS |
817 | rt = slb->tmp >> 8; /* 65:88 => 40:63 */ |
818 | rt |= (slb->tmp64 & 0x7) << 24; /* 62:64 => 37:39 */ | |
12de9a39 | 819 | /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */ |
8eee0af9 | 820 | rt |= ((slb->tmp >> 4) & 0xF) << 27; |
12de9a39 JM |
821 | } else { |
822 | rt = 0; | |
823 | } | |
8eee0af9 | 824 | LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d " |
90e189ec | 825 | TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt); |
12de9a39 JM |
826 | |
827 | return rt; | |
828 | } | |
829 | ||
f6b868fc | 830 | void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs) |
12de9a39 | 831 | { |
99a0949b | 832 | a_ppc_slb *slb; |
12de9a39 | 833 | |
f6b868fc BS |
834 | uint64_t vsid; |
835 | uint64_t esid; | |
836 | int flags, valid, slb_nr; | |
837 | ||
838 | vsid = rs >> 12; | |
839 | flags = ((rs >> 8) & 0xf); | |
840 | ||
841 | esid = rb >> 28; | |
842 | valid = (rb & (1 << 27)); | |
843 | slb_nr = rb & 0xfff; | |
844 | ||
8eee0af9 BS |
845 | slb = slb_get_entry(env, slb_nr); |
846 | slb->tmp64 = (esid << 28) | valid | (vsid >> 24); | |
847 | slb->tmp = (vsid << 8) | (flags << 3); | |
f6b868fc | 848 | |
90e189ec BS |
849 | LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64 |
850 | " %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64, | |
851 | slb->tmp); | |
f6b868fc | 852 | |
8eee0af9 | 853 | slb_set_entry(env, slb_nr, slb); |
12de9a39 | 854 | } |
caa4039c | 855 | #endif /* defined(TARGET_PPC64) */ |
79aceca5 | 856 | |
9a64fbe4 | 857 | /* Perform segment based translation */ |
99a0949b | 858 | static inline a_target_phys_addr get_pgaddr(a_target_phys_addr sdr1, |
636aa200 | 859 | int sdr_sh, |
99a0949b | 860 | a_target_phys_addr hash, |
861 | a_target_phys_addr mask) | |
12de9a39 | 862 | { |
99a0949b | 863 | return (sdr1 & ((a_target_phys_addr)(-1ULL) << sdr_sh)) | (hash & mask); |
12de9a39 JM |
864 | } |
865 | ||
99a0949b | 866 | static inline int get_segment(CPUState *env, a_mmu_ctx *ctx, |
636aa200 | 867 | target_ulong eaddr, int rw, int type) |
79aceca5 | 868 | { |
99a0949b | 869 | a_target_phys_addr sdr, hash, mask, sdr_mask, htab_mask; |
caa4039c JM |
870 | target_ulong sr, vsid, vsid_mask, pgidx, page_mask; |
871 | #if defined(TARGET_PPC64) | |
872 | int attr; | |
9a64fbe4 | 873 | #endif |
5b5aba4f | 874 | int ds, vsid_sh, sdr_sh, pr, target_page_bits; |
caa4039c JM |
875 | int ret, ret2; |
876 | ||
0411a972 | 877 | pr = msr_pr; |
caa4039c | 878 | #if defined(TARGET_PPC64) |
add78955 | 879 | if (env->mmu_model & POWERPC_MMU_64) { |
d12d51d5 | 880 | LOG_MMU("Check SLBs\n"); |
5b5aba4f BS |
881 | ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr, |
882 | &target_page_bits); | |
caa4039c JM |
883 | if (ret < 0) |
884 | return ret; | |
0411a972 JM |
885 | ctx->key = ((attr & 0x40) && (pr != 0)) || |
886 | ((attr & 0x80) && (pr == 0)) ? 1 : 0; | |
caa4039c | 887 | ds = 0; |
5b5aba4f BS |
888 | ctx->nx = attr & 0x10 ? 1 : 0; |
889 | ctx->eaddr = eaddr; | |
caa4039c JM |
890 | vsid_mask = 0x00003FFFFFFFFF80ULL; |
891 | vsid_sh = 7; | |
892 | sdr_sh = 18; | |
893 | sdr_mask = 0x3FF80; | |
894 | } else | |
895 | #endif /* defined(TARGET_PPC64) */ | |
896 | { | |
897 | sr = env->sr[eaddr >> 28]; | |
898 | page_mask = 0x0FFFFFFF; | |
0411a972 JM |
899 | ctx->key = (((sr & 0x20000000) && (pr != 0)) || |
900 | ((sr & 0x40000000) && (pr == 0))) ? 1 : 0; | |
caa4039c | 901 | ds = sr & 0x80000000 ? 1 : 0; |
b227a8e9 | 902 | ctx->nx = sr & 0x10000000 ? 1 : 0; |
caa4039c JM |
903 | vsid = sr & 0x00FFFFFF; |
904 | vsid_mask = 0x01FFFFC0; | |
905 | vsid_sh = 6; | |
906 | sdr_sh = 16; | |
907 | sdr_mask = 0xFFC0; | |
5b5aba4f | 908 | target_page_bits = TARGET_PAGE_BITS; |
90e189ec BS |
909 | LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip=" |
910 | TARGET_FMT_lx " lr=" TARGET_FMT_lx | |
911 | " ir=%d dr=%d pr=%d %d t=%d\n", | |
912 | eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, | |
913 | (int)msr_dr, pr != 0 ? 1 : 0, rw, type); | |
caa4039c | 914 | } |
90e189ec BS |
915 | LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", |
916 | ctx->key, ds, ctx->nx, vsid); | |
caa4039c JM |
917 | ret = -1; |
918 | if (!ds) { | |
9a64fbe4 | 919 | /* Check if instruction fetch is allowed, if needed */ |
b227a8e9 | 920 | if (type != ACCESS_CODE || ctx->nx == 0) { |
9a64fbe4 | 921 | /* Page address translation */ |
76a66253 JM |
922 | /* Primary table address */ |
923 | sdr = env->sdr1; | |
5b5aba4f | 924 | pgidx = (eaddr & page_mask) >> target_page_bits; |
12de9a39 | 925 | #if defined(TARGET_PPC64) |
add78955 | 926 | if (env->mmu_model & POWERPC_MMU_64) { |
12de9a39 JM |
927 | htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F)); |
928 | /* XXX: this is false for 1 TB segments */ | |
929 | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; | |
930 | } else | |
931 | #endif | |
932 | { | |
933 | htab_mask = sdr & 0x000001FF; | |
934 | hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask; | |
935 | } | |
936 | mask = (htab_mask << sdr_sh) | sdr_mask; | |
90e189ec BS |
937 | LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx |
938 | " mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n", | |
939 | sdr, sdr_sh, hash, mask, page_mask); | |
caa4039c | 940 | ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask); |
76a66253 | 941 | /* Secondary table address */ |
caa4039c | 942 | hash = (~hash) & vsid_mask; |
90e189ec BS |
943 | LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx |
944 | " mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask); | |
caa4039c JM |
945 | ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask); |
946 | #if defined(TARGET_PPC64) | |
add78955 | 947 | if (env->mmu_model & POWERPC_MMU_64) { |
caa4039c | 948 | /* Only 5 bits of the page index are used in the AVPN */ |
5b5aba4f BS |
949 | if (target_page_bits > 23) { |
950 | ctx->ptem = (vsid << 12) | | |
951 | ((pgidx << (target_page_bits - 16)) & 0xF80); | |
952 | } else { | |
953 | ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80); | |
954 | } | |
caa4039c JM |
955 | } else |
956 | #endif | |
957 | { | |
958 | ctx->ptem = (vsid << 7) | (pgidx >> 10); | |
959 | } | |
76a66253 | 960 | /* Initialize real address with an invalid value */ |
99a0949b | 961 | ctx->raddr = (a_target_phys_addr)-1ULL; |
7dbe11ac JM |
962 | if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx || |
963 | env->mmu_model == POWERPC_MMU_SOFT_74xx)) { | |
76a66253 JM |
964 | /* Software TLB search */ |
965 | ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type); | |
76a66253 | 966 | } else { |
90e189ec BS |
967 | LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " " |
968 | "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx | |
969 | " pg_addr=" TARGET_FMT_plx "\n", | |
970 | sdr, vsid, pgidx, hash, ctx->pg_addr[0]); | |
76a66253 | 971 | /* Primary table lookup */ |
5b5aba4f | 972 | ret = find_pte(env, ctx, 0, rw, type, target_page_bits); |
76a66253 JM |
973 | if (ret < 0) { |
974 | /* Secondary table lookup */ | |
d12d51d5 | 975 | if (eaddr != 0xEFFFFFFF) |
90e189ec BS |
976 | LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " " |
977 | "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx | |
978 | " pg_addr=" TARGET_FMT_plx "\n", sdr, vsid, | |
979 | pgidx, hash, ctx->pg_addr[1]); | |
5b5aba4f BS |
980 | ret2 = find_pte(env, ctx, 1, rw, type, |
981 | target_page_bits); | |
76a66253 JM |
982 | if (ret2 != -1) |
983 | ret = ret2; | |
984 | } | |
9a64fbe4 | 985 | } |
0411a972 | 986 | #if defined (DUMP_PAGE_TABLES) |
93fcfe39 | 987 | if (qemu_log_enabled()) { |
99a0949b | 988 | a_target_phys_addr curaddr; |
b33c17e1 | 989 | uint32_t a0, a1, a2, a3; |
90e189ec BS |
990 | qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx |
991 | "\n", sdr, mask + 0x80); | |
b33c17e1 JM |
992 | for (curaddr = sdr; curaddr < (sdr + mask + 0x80); |
993 | curaddr += 16) { | |
994 | a0 = ldl_phys(curaddr); | |
995 | a1 = ldl_phys(curaddr + 4); | |
996 | a2 = ldl_phys(curaddr + 8); | |
997 | a3 = ldl_phys(curaddr + 12); | |
998 | if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { | |
90e189ec BS |
999 | qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n", |
1000 | curaddr, a0, a1, a2, a3); | |
12de9a39 | 1001 | } |
b33c17e1 JM |
1002 | } |
1003 | } | |
12de9a39 | 1004 | #endif |
9a64fbe4 | 1005 | } else { |
d12d51d5 | 1006 | LOG_MMU("No access allowed\n"); |
76a66253 | 1007 | ret = -3; |
9a64fbe4 FB |
1008 | } |
1009 | } else { | |
d12d51d5 | 1010 | LOG_MMU("direct store...\n"); |
9a64fbe4 FB |
1011 | /* Direct-store segment : absolutely *BUGGY* for now */ |
1012 | switch (type) { | |
1013 | case ACCESS_INT: | |
1014 | /* Integer load/store : only access allowed */ | |
1015 | break; | |
1016 | case ACCESS_CODE: | |
1017 | /* No code fetch is allowed in direct-store areas */ | |
1018 | return -4; | |
1019 | case ACCESS_FLOAT: | |
1020 | /* Floating point load/store */ | |
1021 | return -4; | |
1022 | case ACCESS_RES: | |
1023 | /* lwarx, ldarx or srwcx. */ | |
1024 | return -4; | |
1025 | case ACCESS_CACHE: | |
1026 | /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */ | |
1027 | /* Should make the instruction do no-op. | |
1028 | * As it already do no-op, it's quite easy :-) | |
1029 | */ | |
76a66253 | 1030 | ctx->raddr = eaddr; |
9a64fbe4 FB |
1031 | return 0; |
1032 | case ACCESS_EXT: | |
1033 | /* eciwx or ecowx */ | |
1034 | return -4; | |
1035 | default: | |
93fcfe39 | 1036 | qemu_log("ERROR: instruction should not need " |
9a64fbe4 | 1037 | "address translation\n"); |
9a64fbe4 FB |
1038 | return -4; |
1039 | } | |
76a66253 JM |
1040 | if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) { |
1041 | ctx->raddr = eaddr; | |
9a64fbe4 FB |
1042 | ret = 2; |
1043 | } else { | |
1044 | ret = -2; | |
1045 | } | |
79aceca5 | 1046 | } |
9a64fbe4 FB |
1047 | |
1048 | return ret; | |
79aceca5 FB |
1049 | } |
1050 | ||
c294fc58 | 1051 | /* Generic TLB check function for embedded PowerPC implementations */ |
99a0949b | 1052 | static inline int ppcemb_tlb_check(CPUState *env, a_ppcemb_tlb *tlb, |
1053 | a_target_phys_addr *raddrp, | |
636aa200 BS |
1054 | target_ulong address, uint32_t pid, int ext, |
1055 | int i) | |
c294fc58 JM |
1056 | { |
1057 | target_ulong mask; | |
1058 | ||
1059 | /* Check valid flag */ | |
1060 | if (!(tlb->prot & PAGE_VALID)) { | |
93fcfe39 | 1061 | qemu_log("%s: TLB %d not valid\n", __func__, i); |
c294fc58 JM |
1062 | return -1; |
1063 | } | |
1064 | mask = ~(tlb->size - 1); | |
90e189ec BS |
1065 | LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx |
1066 | " " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN, | |
1067 | mask, (uint32_t)tlb->PID); | |
c294fc58 | 1068 | /* Check PID */ |
36081602 | 1069 | if (tlb->PID != 0 && tlb->PID != pid) |
c294fc58 JM |
1070 | return -1; |
1071 | /* Check effective address */ | |
1072 | if ((address & mask) != tlb->EPN) | |
1073 | return -1; | |
1074 | *raddrp = (tlb->RPN & mask) | (address & ~mask); | |
9706285b | 1075 | #if (TARGET_PHYS_ADDR_BITS >= 36) |
36081602 JM |
1076 | if (ext) { |
1077 | /* Extend the physical address to 36 bits */ | |
99a0949b | 1078 | *raddrp |= (a_target_phys_addr)(tlb->RPN & 0xF) << 32; |
36081602 | 1079 | } |
9706285b | 1080 | #endif |
c294fc58 JM |
1081 | |
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | /* Generic TLB search function for PowerPC embedded implementations */ | |
36081602 | 1086 | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid) |
c294fc58 | 1087 | { |
99a0949b | 1088 | a_ppcemb_tlb *tlb; |
1089 | a_target_phys_addr raddr; | |
c294fc58 JM |
1090 | int i, ret; |
1091 | ||
1092 | /* Default return value is no match */ | |
1093 | ret = -1; | |
a750fc0b | 1094 | for (i = 0; i < env->nb_tlb; i++) { |
c294fc58 | 1095 | tlb = &env->tlb[i].tlbe; |
36081602 | 1096 | if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) { |
c294fc58 JM |
1097 | ret = i; |
1098 | break; | |
1099 | } | |
1100 | } | |
1101 | ||
1102 | return ret; | |
1103 | } | |
1104 | ||
daf4f96e | 1105 | /* Helpers specific to PowerPC 40x implementations */ |
636aa200 | 1106 | static inline void ppc4xx_tlb_invalidate_all(CPUState *env) |
a750fc0b | 1107 | { |
99a0949b | 1108 | a_ppcemb_tlb *tlb; |
a750fc0b JM |
1109 | int i; |
1110 | ||
1111 | for (i = 0; i < env->nb_tlb; i++) { | |
1112 | tlb = &env->tlb[i].tlbe; | |
daf4f96e | 1113 | tlb->prot &= ~PAGE_VALID; |
a750fc0b | 1114 | } |
daf4f96e | 1115 | tlb_flush(env, 1); |
a750fc0b JM |
1116 | } |
1117 | ||
636aa200 BS |
1118 | static inline void ppc4xx_tlb_invalidate_virt(CPUState *env, |
1119 | target_ulong eaddr, uint32_t pid) | |
0a032cbe | 1120 | { |
daf4f96e | 1121 | #if !defined(FLUSH_ALL_TLBS) |
99a0949b | 1122 | a_ppcemb_tlb *tlb; |
1123 | a_target_phys_addr raddr; | |
daf4f96e | 1124 | target_ulong page, end; |
0a032cbe JM |
1125 | int i; |
1126 | ||
1127 | for (i = 0; i < env->nb_tlb; i++) { | |
1128 | tlb = &env->tlb[i].tlbe; | |
daf4f96e | 1129 | if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) { |
0a032cbe JM |
1130 | end = tlb->EPN + tlb->size; |
1131 | for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) | |
1132 | tlb_flush_page(env, page); | |
0a032cbe | 1133 | tlb->prot &= ~PAGE_VALID; |
daf4f96e | 1134 | break; |
0a032cbe JM |
1135 | } |
1136 | } | |
daf4f96e JM |
1137 | #else |
1138 | ppc4xx_tlb_invalidate_all(env); | |
1139 | #endif | |
0a032cbe JM |
1140 | } |
1141 | ||
99a0949b | 1142 | static int mmu40x_get_physical_address (CPUState *env, a_mmu_ctx *ctx, |
e96efcfc | 1143 | target_ulong address, int rw, int access_type) |
a8dea12f | 1144 | { |
99a0949b | 1145 | a_ppcemb_tlb *tlb; |
1146 | a_target_phys_addr raddr; | |
0411a972 | 1147 | int i, ret, zsel, zpr, pr; |
3b46e624 | 1148 | |
c55e9aef | 1149 | ret = -1; |
99a0949b | 1150 | raddr = (a_target_phys_addr)-1ULL; |
0411a972 | 1151 | pr = msr_pr; |
a8dea12f JM |
1152 | for (i = 0; i < env->nb_tlb; i++) { |
1153 | tlb = &env->tlb[i].tlbe; | |
36081602 JM |
1154 | if (ppcemb_tlb_check(env, tlb, &raddr, address, |
1155 | env->spr[SPR_40x_PID], 0, i) < 0) | |
a8dea12f | 1156 | continue; |
a8dea12f JM |
1157 | zsel = (tlb->attr >> 4) & 0xF; |
1158 | zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3; | |
d12d51d5 | 1159 | LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n", |
a8dea12f | 1160 | __func__, i, zsel, zpr, rw, tlb->attr); |
b227a8e9 JM |
1161 | /* Check execute enable bit */ |
1162 | switch (zpr) { | |
1163 | case 0x2: | |
0411a972 | 1164 | if (pr != 0) |
b227a8e9 JM |
1165 | goto check_perms; |
1166 | /* No break here */ | |
1167 | case 0x3: | |
1168 | /* All accesses granted */ | |
1169 | ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
1170 | ret = 0; | |
1171 | break; | |
1172 | case 0x0: | |
0411a972 | 1173 | if (pr != 0) { |
b227a8e9 JM |
1174 | ctx->prot = 0; |
1175 | ret = -2; | |
a8dea12f JM |
1176 | break; |
1177 | } | |
b227a8e9 JM |
1178 | /* No break here */ |
1179 | case 0x1: | |
1180 | check_perms: | |
1181 | /* Check from TLB entry */ | |
1182 | /* XXX: there is a problem here or in the TLB fill code... */ | |
1183 | ctx->prot = tlb->prot; | |
1184 | ctx->prot |= PAGE_EXEC; | |
1185 | ret = check_prot(ctx->prot, rw, access_type); | |
1186 | break; | |
a8dea12f JM |
1187 | } |
1188 | if (ret >= 0) { | |
1189 | ctx->raddr = raddr; | |
90e189ec BS |
1190 | LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx |
1191 | " %d %d\n", __func__, address, ctx->raddr, ctx->prot, | |
1192 | ret); | |
c55e9aef | 1193 | return 0; |
a8dea12f JM |
1194 | } |
1195 | } | |
90e189ec BS |
1196 | LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx |
1197 | " %d %d\n", __func__, address, raddr, ctx->prot, ret); | |
3b46e624 | 1198 | |
a8dea12f JM |
1199 | return ret; |
1200 | } | |
1201 | ||
c294fc58 JM |
1202 | void store_40x_sler (CPUPPCState *env, uint32_t val) |
1203 | { | |
1204 | /* XXX: TO BE FIXED */ | |
1205 | if (val != 0x00000000) { | |
1206 | cpu_abort(env, "Little-endian regions are not supported by now\n"); | |
1207 | } | |
1208 | env->spr[SPR_405_SLER] = val; | |
1209 | } | |
1210 | ||
99a0949b | 1211 | static int mmubooke_get_physical_address (CPUState *env, a_mmu_ctx *ctx, |
93220573 AJ |
1212 | target_ulong address, int rw, |
1213 | int access_type) | |
5eb7995e | 1214 | { |
99a0949b | 1215 | a_ppcemb_tlb *tlb; |
1216 | a_target_phys_addr raddr; | |
5eb7995e JM |
1217 | int i, prot, ret; |
1218 | ||
1219 | ret = -1; | |
99a0949b | 1220 | raddr = (a_target_phys_addr)-1ULL; |
5eb7995e JM |
1221 | for (i = 0; i < env->nb_tlb; i++) { |
1222 | tlb = &env->tlb[i].tlbe; | |
1223 | if (ppcemb_tlb_check(env, tlb, &raddr, address, | |
1224 | env->spr[SPR_BOOKE_PID], 1, i) < 0) | |
1225 | continue; | |
0411a972 | 1226 | if (msr_pr != 0) |
5eb7995e JM |
1227 | prot = tlb->prot & 0xF; |
1228 | else | |
1229 | prot = (tlb->prot >> 4) & 0xF; | |
1230 | /* Check the address space */ | |
1231 | if (access_type == ACCESS_CODE) { | |
d26bfc9a | 1232 | if (msr_ir != (tlb->attr & 1)) |
5eb7995e JM |
1233 | continue; |
1234 | ctx->prot = prot; | |
1235 | if (prot & PAGE_EXEC) { | |
1236 | ret = 0; | |
1237 | break; | |
1238 | } | |
1239 | ret = -3; | |
1240 | } else { | |
d26bfc9a | 1241 | if (msr_dr != (tlb->attr & 1)) |
5eb7995e JM |
1242 | continue; |
1243 | ctx->prot = prot; | |
1244 | if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) { | |
1245 | ret = 0; | |
1246 | break; | |
1247 | } | |
1248 | ret = -2; | |
1249 | } | |
1250 | } | |
1251 | if (ret >= 0) | |
1252 | ctx->raddr = raddr; | |
1253 | ||
1254 | return ret; | |
1255 | } | |
1256 | ||
99a0949b | 1257 | static inline int check_physical(CPUState *env, a_mmu_ctx *ctx, |
636aa200 | 1258 | target_ulong eaddr, int rw) |
76a66253 JM |
1259 | { |
1260 | int in_plb, ret; | |
3b46e624 | 1261 | |
76a66253 | 1262 | ctx->raddr = eaddr; |
b227a8e9 | 1263 | ctx->prot = PAGE_READ | PAGE_EXEC; |
76a66253 | 1264 | ret = 0; |
a750fc0b JM |
1265 | switch (env->mmu_model) { |
1266 | case POWERPC_MMU_32B: | |
faadf50e | 1267 | case POWERPC_MMU_601: |
a750fc0b | 1268 | case POWERPC_MMU_SOFT_6xx: |
7dbe11ac | 1269 | case POWERPC_MMU_SOFT_74xx: |
a750fc0b | 1270 | case POWERPC_MMU_SOFT_4xx: |
b4095fed | 1271 | case POWERPC_MMU_REAL: |
7dbe11ac | 1272 | case POWERPC_MMU_BOOKE: |
caa4039c JM |
1273 | ctx->prot |= PAGE_WRITE; |
1274 | break; | |
1275 | #if defined(TARGET_PPC64) | |
add78955 | 1276 | case POWERPC_MMU_620: |
a750fc0b | 1277 | case POWERPC_MMU_64B: |
caa4039c | 1278 | /* Real address are 60 bits long */ |
a750fc0b | 1279 | ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL; |
caa4039c JM |
1280 | ctx->prot |= PAGE_WRITE; |
1281 | break; | |
9706285b | 1282 | #endif |
a750fc0b | 1283 | case POWERPC_MMU_SOFT_4xx_Z: |
caa4039c JM |
1284 | if (unlikely(msr_pe != 0)) { |
1285 | /* 403 family add some particular protections, | |
1286 | * using PBL/PBU registers for accesses with no translation. | |
1287 | */ | |
1288 | in_plb = | |
1289 | /* Check PLB validity */ | |
1290 | (env->pb[0] < env->pb[1] && | |
1291 | /* and address in plb area */ | |
1292 | eaddr >= env->pb[0] && eaddr < env->pb[1]) || | |
1293 | (env->pb[2] < env->pb[3] && | |
1294 | eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0; | |
1295 | if (in_plb ^ msr_px) { | |
1296 | /* Access in protected area */ | |
1297 | if (rw == 1) { | |
1298 | /* Access is not allowed */ | |
1299 | ret = -2; | |
1300 | } | |
1301 | } else { | |
1302 | /* Read-write access is allowed */ | |
1303 | ctx->prot |= PAGE_WRITE; | |
76a66253 | 1304 | } |
76a66253 | 1305 | } |
e1833e1f | 1306 | break; |
b4095fed JM |
1307 | case POWERPC_MMU_MPC8xx: |
1308 | /* XXX: TODO */ | |
1309 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1310 | break; | |
a750fc0b | 1311 | case POWERPC_MMU_BOOKE_FSL: |
caa4039c JM |
1312 | /* XXX: TODO */ |
1313 | cpu_abort(env, "BookE FSL MMU model not implemented\n"); | |
1314 | break; | |
1315 | default: | |
1316 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
1317 | return -1; | |
76a66253 JM |
1318 | } |
1319 | ||
1320 | return ret; | |
1321 | } | |
1322 | ||
99a0949b | 1323 | int get_physical_address (CPUState *env, a_mmu_ctx *ctx, target_ulong eaddr, |
faadf50e | 1324 | int rw, int access_type) |
9a64fbe4 FB |
1325 | { |
1326 | int ret; | |
0411a972 | 1327 | |
514fb8c1 | 1328 | #if 0 |
93fcfe39 | 1329 | qemu_log("%s\n", __func__); |
d9bce9d9 | 1330 | #endif |
4b3686fa FB |
1331 | if ((access_type == ACCESS_CODE && msr_ir == 0) || |
1332 | (access_type != ACCESS_CODE && msr_dr == 0)) { | |
9a64fbe4 | 1333 | /* No address translation */ |
76a66253 | 1334 | ret = check_physical(env, ctx, eaddr, rw); |
9a64fbe4 | 1335 | } else { |
c55e9aef | 1336 | ret = -1; |
a750fc0b JM |
1337 | switch (env->mmu_model) { |
1338 | case POWERPC_MMU_32B: | |
faadf50e | 1339 | case POWERPC_MMU_601: |
a750fc0b | 1340 | case POWERPC_MMU_SOFT_6xx: |
7dbe11ac | 1341 | case POWERPC_MMU_SOFT_74xx: |
94855937 BS |
1342 | /* Try to find a BAT */ |
1343 | if (env->nb_BATs != 0) | |
1344 | ret = get_bat(env, ctx, eaddr, rw, access_type); | |
c55e9aef | 1345 | #if defined(TARGET_PPC64) |
add78955 | 1346 | case POWERPC_MMU_620: |
a750fc0b | 1347 | case POWERPC_MMU_64B: |
c55e9aef | 1348 | #endif |
a8dea12f | 1349 | if (ret < 0) { |
c55e9aef | 1350 | /* We didn't match any BAT entry or don't have BATs */ |
a8dea12f JM |
1351 | ret = get_segment(env, ctx, eaddr, rw, access_type); |
1352 | } | |
1353 | break; | |
a750fc0b JM |
1354 | case POWERPC_MMU_SOFT_4xx: |
1355 | case POWERPC_MMU_SOFT_4xx_Z: | |
36081602 | 1356 | ret = mmu40x_get_physical_address(env, ctx, eaddr, |
a8dea12f JM |
1357 | rw, access_type); |
1358 | break; | |
a750fc0b | 1359 | case POWERPC_MMU_BOOKE: |
5eb7995e JM |
1360 | ret = mmubooke_get_physical_address(env, ctx, eaddr, |
1361 | rw, access_type); | |
1362 | break; | |
b4095fed JM |
1363 | case POWERPC_MMU_MPC8xx: |
1364 | /* XXX: TODO */ | |
1365 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1366 | break; | |
a750fc0b | 1367 | case POWERPC_MMU_BOOKE_FSL: |
c55e9aef JM |
1368 | /* XXX: TODO */ |
1369 | cpu_abort(env, "BookE FSL MMU model not implemented\n"); | |
1370 | return -1; | |
b4095fed JM |
1371 | case POWERPC_MMU_REAL: |
1372 | cpu_abort(env, "PowerPC in real mode do not do any translation\n"); | |
2662a059 | 1373 | return -1; |
c55e9aef JM |
1374 | default: |
1375 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
a8dea12f | 1376 | return -1; |
9a64fbe4 FB |
1377 | } |
1378 | } | |
514fb8c1 | 1379 | #if 0 |
90e189ec BS |
1380 | qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n", |
1381 | __func__, eaddr, ret, ctx->raddr); | |
76a66253 | 1382 | #endif |
d9bce9d9 | 1383 | |
9a64fbe4 FB |
1384 | return ret; |
1385 | } | |
1386 | ||
99a0949b | 1387 | a_target_phys_addr cpu_get_phys_page_debug (CPUState *env, target_ulong addr) |
a6b025d3 | 1388 | { |
99a0949b | 1389 | a_mmu_ctx ctx; |
a6b025d3 | 1390 | |
faadf50e | 1391 | if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0)) |
a6b025d3 | 1392 | return -1; |
76a66253 JM |
1393 | |
1394 | return ctx.raddr & TARGET_PAGE_MASK; | |
a6b025d3 | 1395 | } |
9a64fbe4 | 1396 | |
9a64fbe4 | 1397 | /* Perform address translation */ |
e96efcfc | 1398 | int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
6ebbf390 | 1399 | int mmu_idx, int is_softmmu) |
9a64fbe4 | 1400 | { |
99a0949b | 1401 | a_mmu_ctx ctx; |
a541f297 | 1402 | int access_type; |
9a64fbe4 | 1403 | int ret = 0; |
d9bce9d9 | 1404 | |
b769d8fe FB |
1405 | if (rw == 2) { |
1406 | /* code access */ | |
1407 | rw = 0; | |
1408 | access_type = ACCESS_CODE; | |
1409 | } else { | |
1410 | /* data access */ | |
b4cec7b4 | 1411 | access_type = env->access_type; |
b769d8fe | 1412 | } |
faadf50e | 1413 | ret = get_physical_address(env, &ctx, address, rw, access_type); |
9a64fbe4 | 1414 | if (ret == 0) { |
b227a8e9 JM |
1415 | ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK, |
1416 | ctx.raddr & TARGET_PAGE_MASK, ctx.prot, | |
1417 | mmu_idx, is_softmmu); | |
9a64fbe4 | 1418 | } else if (ret < 0) { |
d12d51d5 | 1419 | LOG_MMU_STATE(env); |
9a64fbe4 | 1420 | if (access_type == ACCESS_CODE) { |
9a64fbe4 FB |
1421 | switch (ret) { |
1422 | case -1: | |
76a66253 | 1423 | /* No matches in page tables or TLB */ |
a750fc0b JM |
1424 | switch (env->mmu_model) { |
1425 | case POWERPC_MMU_SOFT_6xx: | |
8f793433 JM |
1426 | env->exception_index = POWERPC_EXCP_IFTLB; |
1427 | env->error_code = 1 << 18; | |
76a66253 JM |
1428 | env->spr[SPR_IMISS] = address; |
1429 | env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem; | |
76a66253 | 1430 | goto tlb_miss; |
7dbe11ac | 1431 | case POWERPC_MMU_SOFT_74xx: |
8f793433 | 1432 | env->exception_index = POWERPC_EXCP_IFTLB; |
7dbe11ac | 1433 | goto tlb_miss_74xx; |
a750fc0b JM |
1434 | case POWERPC_MMU_SOFT_4xx: |
1435 | case POWERPC_MMU_SOFT_4xx_Z: | |
8f793433 JM |
1436 | env->exception_index = POWERPC_EXCP_ITLB; |
1437 | env->error_code = 0; | |
a8dea12f JM |
1438 | env->spr[SPR_40x_DEAR] = address; |
1439 | env->spr[SPR_40x_ESR] = 0x00000000; | |
c55e9aef | 1440 | break; |
a750fc0b | 1441 | case POWERPC_MMU_32B: |
faadf50e | 1442 | case POWERPC_MMU_601: |
c55e9aef | 1443 | #if defined(TARGET_PPC64) |
add78955 | 1444 | case POWERPC_MMU_620: |
a750fc0b | 1445 | case POWERPC_MMU_64B: |
c55e9aef | 1446 | #endif |
8f793433 JM |
1447 | env->exception_index = POWERPC_EXCP_ISI; |
1448 | env->error_code = 0x40000000; | |
1449 | break; | |
a750fc0b | 1450 | case POWERPC_MMU_BOOKE: |
c55e9aef | 1451 | /* XXX: TODO */ |
b4095fed | 1452 | cpu_abort(env, "BookE MMU model is not implemented\n"); |
c55e9aef | 1453 | return -1; |
a750fc0b | 1454 | case POWERPC_MMU_BOOKE_FSL: |
c55e9aef | 1455 | /* XXX: TODO */ |
b4095fed | 1456 | cpu_abort(env, "BookE FSL MMU model is not implemented\n"); |
c55e9aef | 1457 | return -1; |
b4095fed JM |
1458 | case POWERPC_MMU_MPC8xx: |
1459 | /* XXX: TODO */ | |
1460 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1461 | break; | |
1462 | case POWERPC_MMU_REAL: | |
1463 | cpu_abort(env, "PowerPC in real mode should never raise " | |
1464 | "any MMU exceptions\n"); | |
2662a059 | 1465 | return -1; |
c55e9aef JM |
1466 | default: |
1467 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
1468 | return -1; | |
76a66253 | 1469 | } |
9a64fbe4 FB |
1470 | break; |
1471 | case -2: | |
1472 | /* Access rights violation */ | |
8f793433 JM |
1473 | env->exception_index = POWERPC_EXCP_ISI; |
1474 | env->error_code = 0x08000000; | |
9a64fbe4 FB |
1475 | break; |
1476 | case -3: | |
76a66253 | 1477 | /* No execute protection violation */ |
8f793433 JM |
1478 | env->exception_index = POWERPC_EXCP_ISI; |
1479 | env->error_code = 0x10000000; | |
9a64fbe4 FB |
1480 | break; |
1481 | case -4: | |
1482 | /* Direct store exception */ | |
1483 | /* No code fetch is allowed in direct-store areas */ | |
8f793433 JM |
1484 | env->exception_index = POWERPC_EXCP_ISI; |
1485 | env->error_code = 0x10000000; | |
2be0071f | 1486 | break; |
e1833e1f | 1487 | #if defined(TARGET_PPC64) |
2be0071f FB |
1488 | case -5: |
1489 | /* No match in segment table */ | |
add78955 JM |
1490 | if (env->mmu_model == POWERPC_MMU_620) { |
1491 | env->exception_index = POWERPC_EXCP_ISI; | |
1492 | /* XXX: this might be incorrect */ | |
1493 | env->error_code = 0x40000000; | |
1494 | } else { | |
1495 | env->exception_index = POWERPC_EXCP_ISEG; | |
1496 | env->error_code = 0; | |
1497 | } | |
9a64fbe4 | 1498 | break; |
e1833e1f | 1499 | #endif |
9a64fbe4 FB |
1500 | } |
1501 | } else { | |
9a64fbe4 FB |
1502 | switch (ret) { |
1503 | case -1: | |
76a66253 | 1504 | /* No matches in page tables or TLB */ |
a750fc0b JM |
1505 | switch (env->mmu_model) { |
1506 | case POWERPC_MMU_SOFT_6xx: | |
76a66253 | 1507 | if (rw == 1) { |
8f793433 JM |
1508 | env->exception_index = POWERPC_EXCP_DSTLB; |
1509 | env->error_code = 1 << 16; | |
76a66253 | 1510 | } else { |
8f793433 JM |
1511 | env->exception_index = POWERPC_EXCP_DLTLB; |
1512 | env->error_code = 0; | |
76a66253 JM |
1513 | } |
1514 | env->spr[SPR_DMISS] = address; | |
1515 | env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem; | |
1516 | tlb_miss: | |
8f793433 | 1517 | env->error_code |= ctx.key << 19; |
76a66253 JM |
1518 | env->spr[SPR_HASH1] = ctx.pg_addr[0]; |
1519 | env->spr[SPR_HASH2] = ctx.pg_addr[1]; | |
8f793433 | 1520 | break; |
7dbe11ac JM |
1521 | case POWERPC_MMU_SOFT_74xx: |
1522 | if (rw == 1) { | |
8f793433 | 1523 | env->exception_index = POWERPC_EXCP_DSTLB; |
7dbe11ac | 1524 | } else { |
8f793433 | 1525 | env->exception_index = POWERPC_EXCP_DLTLB; |
7dbe11ac JM |
1526 | } |
1527 | tlb_miss_74xx: | |
1528 | /* Implement LRU algorithm */ | |
8f793433 | 1529 | env->error_code = ctx.key << 19; |
7dbe11ac JM |
1530 | env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) | |
1531 | ((env->last_way + 1) & (env->nb_ways - 1)); | |
1532 | env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem; | |
7dbe11ac | 1533 | break; |
a750fc0b JM |
1534 | case POWERPC_MMU_SOFT_4xx: |
1535 | case POWERPC_MMU_SOFT_4xx_Z: | |
8f793433 JM |
1536 | env->exception_index = POWERPC_EXCP_DTLB; |
1537 | env->error_code = 0; | |
a8dea12f JM |
1538 | env->spr[SPR_40x_DEAR] = address; |
1539 | if (rw) | |
1540 | env->spr[SPR_40x_ESR] = 0x00800000; | |
1541 | else | |
1542 | env->spr[SPR_40x_ESR] = 0x00000000; | |
c55e9aef | 1543 | break; |
a750fc0b | 1544 | case POWERPC_MMU_32B: |
faadf50e | 1545 | case POWERPC_MMU_601: |
c55e9aef | 1546 | #if defined(TARGET_PPC64) |
add78955 | 1547 | case POWERPC_MMU_620: |
a750fc0b | 1548 | case POWERPC_MMU_64B: |
c55e9aef | 1549 | #endif |
8f793433 JM |
1550 | env->exception_index = POWERPC_EXCP_DSI; |
1551 | env->error_code = 0; | |
1552 | env->spr[SPR_DAR] = address; | |
1553 | if (rw == 1) | |
1554 | env->spr[SPR_DSISR] = 0x42000000; | |
1555 | else | |
1556 | env->spr[SPR_DSISR] = 0x40000000; | |
1557 | break; | |
b4095fed JM |
1558 | case POWERPC_MMU_MPC8xx: |
1559 | /* XXX: TODO */ | |
1560 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1561 | break; | |
a750fc0b | 1562 | case POWERPC_MMU_BOOKE: |
c55e9aef | 1563 | /* XXX: TODO */ |
b4095fed | 1564 | cpu_abort(env, "BookE MMU model is not implemented\n"); |
c55e9aef | 1565 | return -1; |
a750fc0b | 1566 | case POWERPC_MMU_BOOKE_FSL: |
c55e9aef | 1567 | /* XXX: TODO */ |
b4095fed | 1568 | cpu_abort(env, "BookE FSL MMU model is not implemented\n"); |
c55e9aef | 1569 | return -1; |
b4095fed JM |
1570 | case POWERPC_MMU_REAL: |
1571 | cpu_abort(env, "PowerPC in real mode should never raise " | |
1572 | "any MMU exceptions\n"); | |
2662a059 | 1573 | return -1; |
c55e9aef JM |
1574 | default: |
1575 | cpu_abort(env, "Unknown or invalid MMU model\n"); | |
1576 | return -1; | |
76a66253 | 1577 | } |
9a64fbe4 FB |
1578 | break; |
1579 | case -2: | |
1580 | /* Access rights violation */ | |
8f793433 JM |
1581 | env->exception_index = POWERPC_EXCP_DSI; |
1582 | env->error_code = 0; | |
1583 | env->spr[SPR_DAR] = address; | |
1584 | if (rw == 1) | |
1585 | env->spr[SPR_DSISR] = 0x0A000000; | |
1586 | else | |
1587 | env->spr[SPR_DSISR] = 0x08000000; | |
9a64fbe4 FB |
1588 | break; |
1589 | case -4: | |
1590 | /* Direct store exception */ | |
1591 | switch (access_type) { | |
1592 | case ACCESS_FLOAT: | |
1593 | /* Floating point load/store */ | |
8f793433 JM |
1594 | env->exception_index = POWERPC_EXCP_ALIGN; |
1595 | env->error_code = POWERPC_EXCP_ALIGN_FP; | |
1596 | env->spr[SPR_DAR] = address; | |
9a64fbe4 FB |
1597 | break; |
1598 | case ACCESS_RES: | |
8f793433 JM |
1599 | /* lwarx, ldarx or stwcx. */ |
1600 | env->exception_index = POWERPC_EXCP_DSI; | |
1601 | env->error_code = 0; | |
1602 | env->spr[SPR_DAR] = address; | |
1603 | if (rw == 1) | |
1604 | env->spr[SPR_DSISR] = 0x06000000; | |
1605 | else | |
1606 | env->spr[SPR_DSISR] = 0x04000000; | |
9a64fbe4 FB |
1607 | break; |
1608 | case ACCESS_EXT: | |
1609 | /* eciwx or ecowx */ | |
8f793433 JM |
1610 | env->exception_index = POWERPC_EXCP_DSI; |
1611 | env->error_code = 0; | |
1612 | env->spr[SPR_DAR] = address; | |
1613 | if (rw == 1) | |
1614 | env->spr[SPR_DSISR] = 0x06100000; | |
1615 | else | |
1616 | env->spr[SPR_DSISR] = 0x04100000; | |
9a64fbe4 FB |
1617 | break; |
1618 | default: | |
76a66253 | 1619 | printf("DSI: invalid exception (%d)\n", ret); |
8f793433 JM |
1620 | env->exception_index = POWERPC_EXCP_PROGRAM; |
1621 | env->error_code = | |
1622 | POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL; | |
1623 | env->spr[SPR_DAR] = address; | |
9a64fbe4 FB |
1624 | break; |
1625 | } | |
fdabc366 | 1626 | break; |
e1833e1f | 1627 | #if defined(TARGET_PPC64) |
2be0071f FB |
1628 | case -5: |
1629 | /* No match in segment table */ | |
add78955 JM |
1630 | if (env->mmu_model == POWERPC_MMU_620) { |
1631 | env->exception_index = POWERPC_EXCP_DSI; | |
1632 | env->error_code = 0; | |
1633 | env->spr[SPR_DAR] = address; | |
1634 | /* XXX: this might be incorrect */ | |
1635 | if (rw == 1) | |
1636 | env->spr[SPR_DSISR] = 0x42000000; | |
1637 | else | |
1638 | env->spr[SPR_DSISR] = 0x40000000; | |
1639 | } else { | |
1640 | env->exception_index = POWERPC_EXCP_DSEG; | |
1641 | env->error_code = 0; | |
1642 | env->spr[SPR_DAR] = address; | |
1643 | } | |
2be0071f | 1644 | break; |
e1833e1f | 1645 | #endif |
9a64fbe4 | 1646 | } |
9a64fbe4 FB |
1647 | } |
1648 | #if 0 | |
8f793433 JM |
1649 | printf("%s: set exception to %d %02x\n", __func__, |
1650 | env->exception, env->error_code); | |
9a64fbe4 | 1651 | #endif |
9a64fbe4 FB |
1652 | ret = 1; |
1653 | } | |
76a66253 | 1654 | |
9a64fbe4 FB |
1655 | return ret; |
1656 | } | |
1657 | ||
3fc6c082 FB |
1658 | /*****************************************************************************/ |
1659 | /* BATs management */ | |
1660 | #if !defined(FLUSH_ALL_TLBS) | |
636aa200 BS |
1661 | static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu, |
1662 | target_ulong mask) | |
3fc6c082 FB |
1663 | { |
1664 | target_ulong base, end, page; | |
76a66253 | 1665 | |
3fc6c082 FB |
1666 | base = BATu & ~0x0001FFFF; |
1667 | end = base + mask + 0x00020000; | |
90e189ec BS |
1668 | LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " (" |
1669 | TARGET_FMT_lx ")\n", base, end, mask); | |
3fc6c082 FB |
1670 | for (page = base; page != end; page += TARGET_PAGE_SIZE) |
1671 | tlb_flush_page(env, page); | |
d12d51d5 | 1672 | LOG_BATS("Flush done\n"); |
3fc6c082 FB |
1673 | } |
1674 | #endif | |
1675 | ||
636aa200 BS |
1676 | static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr, |
1677 | target_ulong value) | |
3fc6c082 | 1678 | { |
90e189ec BS |
1679 | LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID, |
1680 | nr, ul == 0 ? 'u' : 'l', value, env->nip); | |
3fc6c082 FB |
1681 | } |
1682 | ||
45d827d2 | 1683 | void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value) |
3fc6c082 FB |
1684 | { |
1685 | target_ulong mask; | |
1686 | ||
1687 | dump_store_bat(env, 'I', 0, nr, value); | |
1688 | if (env->IBAT[0][nr] != value) { | |
1689 | mask = (value << 15) & 0x0FFE0000UL; | |
1690 | #if !defined(FLUSH_ALL_TLBS) | |
1691 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1692 | #endif | |
1693 | /* When storing valid upper BAT, mask BEPI and BRPN | |
1694 | * and invalidate all TLBs covered by this BAT | |
1695 | */ | |
1696 | mask = (value << 15) & 0x0FFE0000UL; | |
1697 | env->IBAT[0][nr] = (value & 0x00001FFFUL) | | |
1698 | (value & ~0x0001FFFFUL & ~mask); | |
1699 | env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) | | |
1700 | (env->IBAT[1][nr] & ~0x0001FFFF & ~mask); | |
1701 | #if !defined(FLUSH_ALL_TLBS) | |
1702 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
76a66253 | 1703 | #else |
3fc6c082 FB |
1704 | tlb_flush(env, 1); |
1705 | #endif | |
1706 | } | |
1707 | } | |
1708 | ||
45d827d2 | 1709 | void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value) |
3fc6c082 FB |
1710 | { |
1711 | dump_store_bat(env, 'I', 1, nr, value); | |
1712 | env->IBAT[1][nr] = value; | |
1713 | } | |
1714 | ||
45d827d2 | 1715 | void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value) |
3fc6c082 FB |
1716 | { |
1717 | target_ulong mask; | |
1718 | ||
1719 | dump_store_bat(env, 'D', 0, nr, value); | |
1720 | if (env->DBAT[0][nr] != value) { | |
1721 | /* When storing valid upper BAT, mask BEPI and BRPN | |
1722 | * and invalidate all TLBs covered by this BAT | |
1723 | */ | |
1724 | mask = (value << 15) & 0x0FFE0000UL; | |
1725 | #if !defined(FLUSH_ALL_TLBS) | |
1726 | do_invalidate_BAT(env, env->DBAT[0][nr], mask); | |
1727 | #endif | |
1728 | mask = (value << 15) & 0x0FFE0000UL; | |
1729 | env->DBAT[0][nr] = (value & 0x00001FFFUL) | | |
1730 | (value & ~0x0001FFFFUL & ~mask); | |
1731 | env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) | | |
1732 | (env->DBAT[1][nr] & ~0x0001FFFF & ~mask); | |
1733 | #if !defined(FLUSH_ALL_TLBS) | |
1734 | do_invalidate_BAT(env, env->DBAT[0][nr], mask); | |
1735 | #else | |
1736 | tlb_flush(env, 1); | |
1737 | #endif | |
1738 | } | |
1739 | } | |
1740 | ||
45d827d2 | 1741 | void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value) |
3fc6c082 FB |
1742 | { |
1743 | dump_store_bat(env, 'D', 1, nr, value); | |
1744 | env->DBAT[1][nr] = value; | |
1745 | } | |
1746 | ||
45d827d2 | 1747 | void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value) |
056401ea JM |
1748 | { |
1749 | target_ulong mask; | |
1750 | int do_inval; | |
1751 | ||
1752 | dump_store_bat(env, 'I', 0, nr, value); | |
1753 | if (env->IBAT[0][nr] != value) { | |
1754 | do_inval = 0; | |
1755 | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; | |
1756 | if (env->IBAT[1][nr] & 0x40) { | |
1757 | /* Invalidate BAT only if it is valid */ | |
1758 | #if !defined(FLUSH_ALL_TLBS) | |
1759 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1760 | #else | |
1761 | do_inval = 1; | |
1762 | #endif | |
1763 | } | |
1764 | /* When storing valid upper BAT, mask BEPI and BRPN | |
1765 | * and invalidate all TLBs covered by this BAT | |
1766 | */ | |
1767 | env->IBAT[0][nr] = (value & 0x00001FFFUL) | | |
1768 | (value & ~0x0001FFFFUL & ~mask); | |
1769 | env->DBAT[0][nr] = env->IBAT[0][nr]; | |
1770 | if (env->IBAT[1][nr] & 0x40) { | |
1771 | #if !defined(FLUSH_ALL_TLBS) | |
1772 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1773 | #else | |
1774 | do_inval = 1; | |
1775 | #endif | |
1776 | } | |
1777 | #if defined(FLUSH_ALL_TLBS) | |
1778 | if (do_inval) | |
1779 | tlb_flush(env, 1); | |
1780 | #endif | |
1781 | } | |
1782 | } | |
1783 | ||
45d827d2 | 1784 | void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value) |
056401ea JM |
1785 | { |
1786 | target_ulong mask; | |
1787 | int do_inval; | |
1788 | ||
1789 | dump_store_bat(env, 'I', 1, nr, value); | |
1790 | if (env->IBAT[1][nr] != value) { | |
1791 | do_inval = 0; | |
1792 | if (env->IBAT[1][nr] & 0x40) { | |
1793 | #if !defined(FLUSH_ALL_TLBS) | |
1794 | mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL; | |
1795 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1796 | #else | |
1797 | do_inval = 1; | |
1798 | #endif | |
1799 | } | |
1800 | if (value & 0x40) { | |
1801 | #if !defined(FLUSH_ALL_TLBS) | |
1802 | mask = (value << 17) & 0x0FFE0000UL; | |
1803 | do_invalidate_BAT(env, env->IBAT[0][nr], mask); | |
1804 | #else | |
1805 | do_inval = 1; | |
1806 | #endif | |
1807 | } | |
1808 | env->IBAT[1][nr] = value; | |
1809 | env->DBAT[1][nr] = value; | |
1810 | #if defined(FLUSH_ALL_TLBS) | |
1811 | if (do_inval) | |
1812 | tlb_flush(env, 1); | |
1813 | #endif | |
1814 | } | |
1815 | } | |
1816 | ||
0a032cbe JM |
1817 | /*****************************************************************************/ |
1818 | /* TLB management */ | |
1819 | void ppc_tlb_invalidate_all (CPUPPCState *env) | |
1820 | { | |
daf4f96e JM |
1821 | switch (env->mmu_model) { |
1822 | case POWERPC_MMU_SOFT_6xx: | |
7dbe11ac | 1823 | case POWERPC_MMU_SOFT_74xx: |
0a032cbe | 1824 | ppc6xx_tlb_invalidate_all(env); |
daf4f96e JM |
1825 | break; |
1826 | case POWERPC_MMU_SOFT_4xx: | |
1827 | case POWERPC_MMU_SOFT_4xx_Z: | |
0a032cbe | 1828 | ppc4xx_tlb_invalidate_all(env); |
daf4f96e | 1829 | break; |
b4095fed | 1830 | case POWERPC_MMU_REAL: |
7dbe11ac JM |
1831 | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); |
1832 | break; | |
b4095fed JM |
1833 | case POWERPC_MMU_MPC8xx: |
1834 | /* XXX: TODO */ | |
1835 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1836 | break; | |
7dbe11ac JM |
1837 | case POWERPC_MMU_BOOKE: |
1838 | /* XXX: TODO */ | |
b4095fed | 1839 | cpu_abort(env, "BookE MMU model is not implemented\n"); |
7dbe11ac JM |
1840 | break; |
1841 | case POWERPC_MMU_BOOKE_FSL: | |
1842 | /* XXX: TODO */ | |
da07cf59 AL |
1843 | if (!kvm_enabled()) |
1844 | cpu_abort(env, "BookE MMU model is not implemented\n"); | |
7dbe11ac | 1845 | break; |
7dbe11ac | 1846 | case POWERPC_MMU_32B: |
faadf50e | 1847 | case POWERPC_MMU_601: |
00af685f | 1848 | #if defined(TARGET_PPC64) |
add78955 | 1849 | case POWERPC_MMU_620: |
7dbe11ac | 1850 | case POWERPC_MMU_64B: |
00af685f | 1851 | #endif /* defined(TARGET_PPC64) */ |
0a032cbe | 1852 | tlb_flush(env, 1); |
daf4f96e | 1853 | break; |
00af685f JM |
1854 | default: |
1855 | /* XXX: TODO */ | |
12de9a39 | 1856 | cpu_abort(env, "Unknown MMU model\n"); |
00af685f | 1857 | break; |
0a032cbe JM |
1858 | } |
1859 | } | |
1860 | ||
daf4f96e JM |
1861 | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr) |
1862 | { | |
1863 | #if !defined(FLUSH_ALL_TLBS) | |
1864 | addr &= TARGET_PAGE_MASK; | |
1865 | switch (env->mmu_model) { | |
1866 | case POWERPC_MMU_SOFT_6xx: | |
7dbe11ac | 1867 | case POWERPC_MMU_SOFT_74xx: |
daf4f96e JM |
1868 | ppc6xx_tlb_invalidate_virt(env, addr, 0); |
1869 | if (env->id_tlbs == 1) | |
1870 | ppc6xx_tlb_invalidate_virt(env, addr, 1); | |
1871 | break; | |
1872 | case POWERPC_MMU_SOFT_4xx: | |
1873 | case POWERPC_MMU_SOFT_4xx_Z: | |
1874 | ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]); | |
1875 | break; | |
b4095fed | 1876 | case POWERPC_MMU_REAL: |
7dbe11ac JM |
1877 | cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n"); |
1878 | break; | |
b4095fed JM |
1879 | case POWERPC_MMU_MPC8xx: |
1880 | /* XXX: TODO */ | |
1881 | cpu_abort(env, "MPC8xx MMU model is not implemented\n"); | |
1882 | break; | |
7dbe11ac JM |
1883 | case POWERPC_MMU_BOOKE: |
1884 | /* XXX: TODO */ | |
b4095fed | 1885 | cpu_abort(env, "BookE MMU model is not implemented\n"); |
7dbe11ac JM |
1886 | break; |
1887 | case POWERPC_MMU_BOOKE_FSL: | |
1888 | /* XXX: TODO */ | |
b4095fed | 1889 | cpu_abort(env, "BookE FSL MMU model is not implemented\n"); |
7dbe11ac JM |
1890 | break; |
1891 | case POWERPC_MMU_32B: | |
faadf50e | 1892 | case POWERPC_MMU_601: |
daf4f96e | 1893 | /* tlbie invalidate TLBs for all segments */ |
6f2d8978 | 1894 | addr &= ~((target_ulong)-1ULL << 28); |
daf4f96e JM |
1895 | /* XXX: this case should be optimized, |
1896 | * giving a mask to tlb_flush_page | |
1897 | */ | |
1898 | tlb_flush_page(env, addr | (0x0 << 28)); | |
1899 | tlb_flush_page(env, addr | (0x1 << 28)); | |
1900 | tlb_flush_page(env, addr | (0x2 << 28)); | |
1901 | tlb_flush_page(env, addr | (0x3 << 28)); | |
1902 | tlb_flush_page(env, addr | (0x4 << 28)); | |
1903 | tlb_flush_page(env, addr | (0x5 << 28)); | |
1904 | tlb_flush_page(env, addr | (0x6 << 28)); | |
1905 | tlb_flush_page(env, addr | (0x7 << 28)); | |
1906 | tlb_flush_page(env, addr | (0x8 << 28)); | |
1907 | tlb_flush_page(env, addr | (0x9 << 28)); | |
1908 | tlb_flush_page(env, addr | (0xA << 28)); | |
1909 | tlb_flush_page(env, addr | (0xB << 28)); | |
1910 | tlb_flush_page(env, addr | (0xC << 28)); | |
1911 | tlb_flush_page(env, addr | (0xD << 28)); | |
1912 | tlb_flush_page(env, addr | (0xE << 28)); | |
1913 | tlb_flush_page(env, addr | (0xF << 28)); | |
7dbe11ac | 1914 | break; |
00af685f | 1915 | #if defined(TARGET_PPC64) |
add78955 | 1916 | case POWERPC_MMU_620: |
7dbe11ac | 1917 | case POWERPC_MMU_64B: |
7dbe11ac JM |
1918 | /* tlbie invalidate TLBs for all segments */ |
1919 | /* XXX: given the fact that there are too many segments to invalidate, | |
00af685f | 1920 | * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu, |
7dbe11ac JM |
1921 | * we just invalidate all TLBs |
1922 | */ | |
1923 | tlb_flush(env, 1); | |
1924 | break; | |
00af685f JM |
1925 | #endif /* defined(TARGET_PPC64) */ |
1926 | default: | |
1927 | /* XXX: TODO */ | |
12de9a39 | 1928 | cpu_abort(env, "Unknown MMU model\n"); |
00af685f | 1929 | break; |
daf4f96e JM |
1930 | } |
1931 | #else | |
1932 | ppc_tlb_invalidate_all(env); | |
1933 | #endif | |
1934 | } | |
1935 | ||
3fc6c082 FB |
1936 | /*****************************************************************************/ |
1937 | /* Special registers manipulation */ | |
d9bce9d9 | 1938 | #if defined(TARGET_PPC64) |
d9bce9d9 JM |
1939 | void ppc_store_asr (CPUPPCState *env, target_ulong value) |
1940 | { | |
1941 | if (env->asr != value) { | |
1942 | env->asr = value; | |
1943 | tlb_flush(env, 1); | |
1944 | } | |
1945 | } | |
1946 | #endif | |
1947 | ||
45d827d2 | 1948 | void ppc_store_sdr1 (CPUPPCState *env, target_ulong value) |
3fc6c082 | 1949 | { |
90e189ec | 1950 | LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value); |
3fc6c082 | 1951 | if (env->sdr1 != value) { |
12de9a39 JM |
1952 | /* XXX: for PowerPC 64, should check that the HTABSIZE value |
1953 | * is <= 28 | |
1954 | */ | |
3fc6c082 | 1955 | env->sdr1 = value; |
76a66253 | 1956 | tlb_flush(env, 1); |
3fc6c082 FB |
1957 | } |
1958 | } | |
1959 | ||
f6b868fc BS |
1960 | #if defined(TARGET_PPC64) |
1961 | target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr) | |
1962 | { | |
1963 | // XXX | |
1964 | return 0; | |
1965 | } | |
1966 | #endif | |
1967 | ||
45d827d2 | 1968 | void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value) |
3fc6c082 | 1969 | { |
90e189ec BS |
1970 | LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, |
1971 | srnum, value, env->sr[srnum]); | |
f6b868fc BS |
1972 | #if defined(TARGET_PPC64) |
1973 | if (env->mmu_model & POWERPC_MMU_64) { | |
1974 | uint64_t rb = 0, rs = 0; | |
1975 | ||
1976 | /* ESID = srnum */ | |
1977 | rb |= ((uint32_t)srnum & 0xf) << 28; | |
1978 | /* Set the valid bit */ | |
1979 | rb |= 1 << 27; | |
1980 | /* Index = ESID */ | |
1981 | rb |= (uint32_t)srnum; | |
1982 | ||
1983 | /* VSID = VSID */ | |
1984 | rs |= (value & 0xfffffff) << 12; | |
1985 | /* flags = flags */ | |
1986 | rs |= ((value >> 27) & 0xf) << 9; | |
1987 | ||
1988 | ppc_store_slb(env, rb, rs); | |
1989 | } else | |
1990 | #endif | |
3fc6c082 FB |
1991 | if (env->sr[srnum] != value) { |
1992 | env->sr[srnum] = value; | |
bf1752ef AJ |
1993 | /* Invalidating 256MB of virtual memory in 4kB pages is way longer than |
1994 | flusing the whole TLB. */ | |
3fc6c082 FB |
1995 | #if !defined(FLUSH_ALL_TLBS) && 0 |
1996 | { | |
1997 | target_ulong page, end; | |
1998 | /* Invalidate 256 MB of virtual memory */ | |
1999 | page = (16 << 20) * srnum; | |
2000 | end = page + (16 << 20); | |
2001 | for (; page != end; page += TARGET_PAGE_SIZE) | |
2002 | tlb_flush_page(env, page); | |
2003 | } | |
2004 | #else | |
76a66253 | 2005 | tlb_flush(env, 1); |
3fc6c082 FB |
2006 | #endif |
2007 | } | |
2008 | } | |
76a66253 | 2009 | #endif /* !defined (CONFIG_USER_ONLY) */ |
3fc6c082 | 2010 | |
76a66253 | 2011 | /* GDBstub can read and write MSR... */ |
0411a972 | 2012 | void ppc_store_msr (CPUPPCState *env, target_ulong value) |
3fc6c082 | 2013 | { |
a4f30719 | 2014 | hreg_store_msr(env, value, 0); |
3fc6c082 FB |
2015 | } |
2016 | ||
2017 | /*****************************************************************************/ | |
2018 | /* Exception processing */ | |
18fba28c | 2019 | #if defined (CONFIG_USER_ONLY) |
9a64fbe4 | 2020 | void do_interrupt (CPUState *env) |
79aceca5 | 2021 | { |
e1833e1f JM |
2022 | env->exception_index = POWERPC_EXCP_NONE; |
2023 | env->error_code = 0; | |
18fba28c | 2024 | } |
47103572 | 2025 | |
e9df014c | 2026 | void ppc_hw_interrupt (CPUState *env) |
47103572 | 2027 | { |
e1833e1f JM |
2028 | env->exception_index = POWERPC_EXCP_NONE; |
2029 | env->error_code = 0; | |
47103572 | 2030 | } |
76a66253 | 2031 | #else /* defined (CONFIG_USER_ONLY) */ |
636aa200 | 2032 | static inline void dump_syscall(CPUState *env) |
d094807b | 2033 | { |
b11ebf64 BS |
2034 | qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64 |
2035 | " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64 | |
2036 | " nip=" TARGET_FMT_lx "\n", | |
90e189ec BS |
2037 | ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), |
2038 | ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), | |
2039 | ppc_dump_gpr(env, 6), env->nip); | |
d094807b FB |
2040 | } |
2041 | ||
e1833e1f JM |
2042 | /* Note that this function should be greatly optimized |
2043 | * when called with a constant excp, from ppc_hw_interrupt | |
2044 | */ | |
636aa200 | 2045 | static inline void powerpc_excp(CPUState *env, int excp_model, int excp) |
18fba28c | 2046 | { |
0411a972 | 2047 | target_ulong msr, new_msr, vector; |
e1833e1f | 2048 | int srr0, srr1, asrr0, asrr1; |
a4f30719 | 2049 | int lpes0, lpes1, lev; |
79aceca5 | 2050 | |
b172c56a JM |
2051 | if (0) { |
2052 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
2053 | lpes0 = (env->spr[SPR_LPCR] >> 1) & 1; | |
2054 | lpes1 = (env->spr[SPR_LPCR] >> 2) & 1; | |
2055 | } else { | |
2056 | /* Those values ensure we won't enter the hypervisor mode */ | |
2057 | lpes0 = 0; | |
2058 | lpes1 = 1; | |
2059 | } | |
2060 | ||
90e189ec BS |
2061 | qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx |
2062 | " => %08x (%02x)\n", env->nip, excp, env->error_code); | |
0411a972 JM |
2063 | msr = env->msr; |
2064 | new_msr = msr; | |
e1833e1f JM |
2065 | srr0 = SPR_SRR0; |
2066 | srr1 = SPR_SRR1; | |
2067 | asrr0 = -1; | |
2068 | asrr1 = -1; | |
2069 | msr &= ~((target_ulong)0x783F0000); | |
9a64fbe4 | 2070 | switch (excp) { |
e1833e1f JM |
2071 | case POWERPC_EXCP_NONE: |
2072 | /* Should never happen */ | |
2073 | return; | |
2074 | case POWERPC_EXCP_CRITICAL: /* Critical input */ | |
0411a972 | 2075 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f | 2076 | switch (excp_model) { |
a750fc0b | 2077 | case POWERPC_EXCP_40x: |
e1833e1f JM |
2078 | srr0 = SPR_40x_SRR2; |
2079 | srr1 = SPR_40x_SRR3; | |
c62db105 | 2080 | break; |
a750fc0b | 2081 | case POWERPC_EXCP_BOOKE: |
e1833e1f JM |
2082 | srr0 = SPR_BOOKE_CSRR0; |
2083 | srr1 = SPR_BOOKE_CSRR1; | |
c62db105 | 2084 | break; |
e1833e1f | 2085 | case POWERPC_EXCP_G2: |
c62db105 | 2086 | break; |
e1833e1f JM |
2087 | default: |
2088 | goto excp_invalid; | |
2be0071f | 2089 | } |
9a64fbe4 | 2090 | goto store_next; |
e1833e1f JM |
2091 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
2092 | if (msr_me == 0) { | |
e63ecc6f JM |
2093 | /* Machine check exception is not enabled. |
2094 | * Enter checkstop state. | |
2095 | */ | |
93fcfe39 AL |
2096 | if (qemu_log_enabled()) { |
2097 | qemu_log("Machine check while not allowed. " | |
e63ecc6f JM |
2098 | "Entering checkstop state\n"); |
2099 | } else { | |
2100 | fprintf(stderr, "Machine check while not allowed. " | |
2101 | "Entering checkstop state\n"); | |
2102 | } | |
2103 | env->halted = 1; | |
2104 | env->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
e1833e1f | 2105 | } |
0411a972 JM |
2106 | new_msr &= ~((target_ulong)1 << MSR_RI); |
2107 | new_msr &= ~((target_ulong)1 << MSR_ME); | |
b172c56a JM |
2108 | if (0) { |
2109 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
a4f30719 | 2110 | new_msr |= (target_ulong)MSR_HVB; |
b172c56a | 2111 | } |
e1833e1f JM |
2112 | /* XXX: should also have something loaded in DAR / DSISR */ |
2113 | switch (excp_model) { | |
a750fc0b | 2114 | case POWERPC_EXCP_40x: |
e1833e1f JM |
2115 | srr0 = SPR_40x_SRR2; |
2116 | srr1 = SPR_40x_SRR3; | |
c62db105 | 2117 | break; |
a750fc0b | 2118 | case POWERPC_EXCP_BOOKE: |
e1833e1f JM |
2119 | srr0 = SPR_BOOKE_MCSRR0; |
2120 | srr1 = SPR_BOOKE_MCSRR1; | |
2121 | asrr0 = SPR_BOOKE_CSRR0; | |
2122 | asrr1 = SPR_BOOKE_CSRR1; | |
c62db105 JM |
2123 | break; |
2124 | default: | |
2125 | break; | |
2be0071f | 2126 | } |
e1833e1f JM |
2127 | goto store_next; |
2128 | case POWERPC_EXCP_DSI: /* Data storage exception */ | |
90e189ec BS |
2129 | LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx |
2130 | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]); | |
0411a972 | 2131 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2132 | if (lpes1 == 0) |
a4f30719 | 2133 | new_msr |= (target_ulong)MSR_HVB; |
a541f297 | 2134 | goto store_next; |
e1833e1f | 2135 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
90e189ec BS |
2136 | LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx |
2137 | "\n", msr, env->nip); | |
0411a972 | 2138 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2139 | if (lpes1 == 0) |
a4f30719 | 2140 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f | 2141 | msr |= env->error_code; |
9a64fbe4 | 2142 | goto store_next; |
e1833e1f | 2143 | case POWERPC_EXCP_EXTERNAL: /* External input */ |
0411a972 | 2144 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2145 | if (lpes0 == 1) |
a4f30719 | 2146 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 | 2147 | goto store_next; |
e1833e1f | 2148 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
0411a972 | 2149 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2150 | if (lpes1 == 0) |
a4f30719 | 2151 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2152 | /* XXX: this is false */ |
2153 | /* Get rS/rD and rA from faulting opcode */ | |
2154 | env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16; | |
9a64fbe4 | 2155 | goto store_current; |
e1833e1f | 2156 | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
9a64fbe4 | 2157 | switch (env->error_code & ~0xF) { |
e1833e1f JM |
2158 | case POWERPC_EXCP_FP: |
2159 | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { | |
d12d51d5 | 2160 | LOG_EXCP("Ignore floating point exception\n"); |
7c58044c JM |
2161 | env->exception_index = POWERPC_EXCP_NONE; |
2162 | env->error_code = 0; | |
9a64fbe4 | 2163 | return; |
76a66253 | 2164 | } |
0411a972 | 2165 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2166 | if (lpes1 == 0) |
a4f30719 | 2167 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 | 2168 | msr |= 0x00100000; |
5b52b991 JM |
2169 | if (msr_fe0 == msr_fe1) |
2170 | goto store_next; | |
2171 | msr |= 0x00010000; | |
76a66253 | 2172 | break; |
e1833e1f | 2173 | case POWERPC_EXCP_INVAL: |
90e189ec | 2174 | LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); |
0411a972 | 2175 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2176 | if (lpes1 == 0) |
a4f30719 | 2177 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 | 2178 | msr |= 0x00080000; |
76a66253 | 2179 | break; |
e1833e1f | 2180 | case POWERPC_EXCP_PRIV: |
0411a972 | 2181 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2182 | if (lpes1 == 0) |
a4f30719 | 2183 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 | 2184 | msr |= 0x00040000; |
76a66253 | 2185 | break; |
e1833e1f | 2186 | case POWERPC_EXCP_TRAP: |
0411a972 | 2187 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2188 | if (lpes1 == 0) |
a4f30719 | 2189 | new_msr |= (target_ulong)MSR_HVB; |
9a64fbe4 FB |
2190 | msr |= 0x00020000; |
2191 | break; | |
2192 | default: | |
2193 | /* Should never occur */ | |
e1833e1f JM |
2194 | cpu_abort(env, "Invalid program exception %d. Aborting\n", |
2195 | env->error_code); | |
76a66253 JM |
2196 | break; |
2197 | } | |
5b52b991 | 2198 | goto store_current; |
e1833e1f | 2199 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ |
0411a972 | 2200 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2201 | if (lpes1 == 0) |
a4f30719 | 2202 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2203 | goto store_current; |
2204 | case POWERPC_EXCP_SYSCALL: /* System call exception */ | |
d094807b FB |
2205 | /* NOTE: this is a temporary hack to support graphics OSI |
2206 | calls from the MOL driver */ | |
e1833e1f | 2207 | /* XXX: To be removed */ |
d094807b FB |
2208 | if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b && |
2209 | env->osi_call) { | |
7c58044c JM |
2210 | if (env->osi_call(env) != 0) { |
2211 | env->exception_index = POWERPC_EXCP_NONE; | |
2212 | env->error_code = 0; | |
d094807b | 2213 | return; |
7c58044c | 2214 | } |
d094807b | 2215 | } |
93fcfe39 | 2216 | dump_syscall(env); |
0411a972 | 2217 | new_msr &= ~((target_ulong)1 << MSR_RI); |
f9fdea6b | 2218 | lev = env->error_code; |
e1833e1f | 2219 | if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) |
a4f30719 | 2220 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2221 | goto store_next; |
2222 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ | |
0411a972 | 2223 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f JM |
2224 | goto store_current; |
2225 | case POWERPC_EXCP_DECR: /* Decrementer exception */ | |
0411a972 | 2226 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2227 | if (lpes1 == 0) |
a4f30719 | 2228 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2229 | goto store_next; |
2230 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ | |
2231 | /* FIT on 4xx */ | |
d12d51d5 | 2232 | LOG_EXCP("FIT exception\n"); |
0411a972 | 2233 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
9a64fbe4 | 2234 | goto store_next; |
e1833e1f | 2235 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
d12d51d5 | 2236 | LOG_EXCP("WDT exception\n"); |
e1833e1f JM |
2237 | switch (excp_model) { |
2238 | case POWERPC_EXCP_BOOKE: | |
2239 | srr0 = SPR_BOOKE_CSRR0; | |
2240 | srr1 = SPR_BOOKE_CSRR1; | |
2241 | break; | |
2242 | default: | |
2243 | break; | |
2244 | } | |
0411a972 | 2245 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
2be0071f | 2246 | goto store_next; |
e1833e1f | 2247 | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
0411a972 | 2248 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2249 | goto store_next; |
2250 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ | |
0411a972 | 2251 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2252 | goto store_next; |
2253 | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ | |
2254 | switch (excp_model) { | |
2255 | case POWERPC_EXCP_BOOKE: | |
2256 | srr0 = SPR_BOOKE_DSRR0; | |
2257 | srr1 = SPR_BOOKE_DSRR1; | |
2258 | asrr0 = SPR_BOOKE_CSRR0; | |
2259 | asrr1 = SPR_BOOKE_CSRR1; | |
2260 | break; | |
2261 | default: | |
2262 | break; | |
2263 | } | |
2be0071f | 2264 | /* XXX: TODO */ |
e1833e1f | 2265 | cpu_abort(env, "Debug exception is not implemented yet !\n"); |
2be0071f | 2266 | goto store_next; |
e1833e1f | 2267 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
0411a972 | 2268 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2269 | goto store_current; |
2270 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ | |
2be0071f | 2271 | /* XXX: TODO */ |
e1833e1f | 2272 | cpu_abort(env, "Embedded floating point data exception " |
2be0071f FB |
2273 | "is not implemented yet !\n"); |
2274 | goto store_next; | |
e1833e1f | 2275 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
2be0071f | 2276 | /* XXX: TODO */ |
e1833e1f JM |
2277 | cpu_abort(env, "Embedded floating point round exception " |
2278 | "is not implemented yet !\n"); | |
9a64fbe4 | 2279 | goto store_next; |
e1833e1f | 2280 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
0411a972 | 2281 | new_msr &= ~((target_ulong)1 << MSR_RI); |
2be0071f FB |
2282 | /* XXX: TODO */ |
2283 | cpu_abort(env, | |
e1833e1f | 2284 | "Performance counter exception is not implemented yet !\n"); |
9a64fbe4 | 2285 | goto store_next; |
e1833e1f | 2286 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
76a66253 | 2287 | /* XXX: TODO */ |
e1833e1f JM |
2288 | cpu_abort(env, |
2289 | "Embedded doorbell interrupt is not implemented yet !\n"); | |
2be0071f | 2290 | goto store_next; |
e1833e1f JM |
2291 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
2292 | switch (excp_model) { | |
2293 | case POWERPC_EXCP_BOOKE: | |
2294 | srr0 = SPR_BOOKE_CSRR0; | |
2295 | srr1 = SPR_BOOKE_CSRR1; | |
a750fc0b | 2296 | break; |
2be0071f | 2297 | default: |
2be0071f FB |
2298 | break; |
2299 | } | |
e1833e1f JM |
2300 | /* XXX: TODO */ |
2301 | cpu_abort(env, "Embedded doorbell critical interrupt " | |
2302 | "is not implemented yet !\n"); | |
2303 | goto store_next; | |
e1833e1f | 2304 | case POWERPC_EXCP_RESET: /* System reset exception */ |
0411a972 | 2305 | new_msr &= ~((target_ulong)1 << MSR_RI); |
a4f30719 JM |
2306 | if (0) { |
2307 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
2308 | new_msr |= (target_ulong)MSR_HVB; | |
2309 | } | |
e1833e1f | 2310 | goto store_next; |
e1833e1f | 2311 | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
0411a972 | 2312 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2313 | if (lpes1 == 0) |
a4f30719 | 2314 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2315 | goto store_next; |
2316 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ | |
0411a972 | 2317 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2318 | if (lpes1 == 0) |
a4f30719 | 2319 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f | 2320 | goto store_next; |
e1833e1f JM |
2321 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ |
2322 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2323 | srr1 = SPR_HSRR1; |
a4f30719 | 2324 | new_msr |= (target_ulong)MSR_HVB; |
b172c56a | 2325 | goto store_next; |
e1833e1f | 2326 | case POWERPC_EXCP_TRACE: /* Trace exception */ |
0411a972 | 2327 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2328 | if (lpes1 == 0) |
a4f30719 | 2329 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f | 2330 | goto store_next; |
e1833e1f JM |
2331 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
2332 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2333 | srr1 = SPR_HSRR1; |
a4f30719 | 2334 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2335 | goto store_next; |
2336 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ | |
2337 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2338 | srr1 = SPR_HSRR1; |
a4f30719 | 2339 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2340 | goto store_next; |
2341 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ | |
2342 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2343 | srr1 = SPR_HSRR1; |
a4f30719 | 2344 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2345 | goto store_next; |
2346 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ | |
2347 | srr0 = SPR_HSRR0; | |
f9fdea6b | 2348 | srr1 = SPR_HSRR1; |
a4f30719 | 2349 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f | 2350 | goto store_next; |
e1833e1f | 2351 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
0411a972 | 2352 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2353 | if (lpes1 == 0) |
a4f30719 | 2354 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2355 | goto store_current; |
2356 | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ | |
d12d51d5 | 2357 | LOG_EXCP("PIT exception\n"); |
0411a972 | 2358 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
e1833e1f JM |
2359 | goto store_next; |
2360 | case POWERPC_EXCP_IO: /* IO error exception */ | |
2361 | /* XXX: TODO */ | |
2362 | cpu_abort(env, "601 IO error exception is not implemented yet !\n"); | |
2363 | goto store_next; | |
2364 | case POWERPC_EXCP_RUNM: /* Run mode exception */ | |
2365 | /* XXX: TODO */ | |
2366 | cpu_abort(env, "601 run mode exception is not implemented yet !\n"); | |
2367 | goto store_next; | |
2368 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ | |
2369 | /* XXX: TODO */ | |
2370 | cpu_abort(env, "602 emulation trap exception " | |
2371 | "is not implemented yet !\n"); | |
2372 | goto store_next; | |
2373 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ | |
0411a972 | 2374 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
a4f30719 JM |
2375 | if (lpes1 == 0) /* XXX: check this */ |
2376 | new_msr |= (target_ulong)MSR_HVB; | |
e1833e1f | 2377 | switch (excp_model) { |
a750fc0b JM |
2378 | case POWERPC_EXCP_602: |
2379 | case POWERPC_EXCP_603: | |
2380 | case POWERPC_EXCP_603E: | |
2381 | case POWERPC_EXCP_G2: | |
e1833e1f | 2382 | goto tlb_miss_tgpr; |
a750fc0b | 2383 | case POWERPC_EXCP_7x5: |
76a66253 | 2384 | goto tlb_miss; |
7dbe11ac JM |
2385 | case POWERPC_EXCP_74xx: |
2386 | goto tlb_miss_74xx; | |
2be0071f | 2387 | default: |
e1833e1f | 2388 | cpu_abort(env, "Invalid instruction TLB miss exception\n"); |
2be0071f FB |
2389 | break; |
2390 | } | |
e1833e1f JM |
2391 | break; |
2392 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
0411a972 | 2393 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
a4f30719 JM |
2394 | if (lpes1 == 0) /* XXX: check this */ |
2395 | new_msr |= (target_ulong)MSR_HVB; | |
e1833e1f | 2396 | switch (excp_model) { |
a750fc0b JM |
2397 | case POWERPC_EXCP_602: |
2398 | case POWERPC_EXCP_603: | |
2399 | case POWERPC_EXCP_603E: | |
2400 | case POWERPC_EXCP_G2: | |
e1833e1f | 2401 | goto tlb_miss_tgpr; |
a750fc0b | 2402 | case POWERPC_EXCP_7x5: |
76a66253 | 2403 | goto tlb_miss; |
7dbe11ac JM |
2404 | case POWERPC_EXCP_74xx: |
2405 | goto tlb_miss_74xx; | |
2be0071f | 2406 | default: |
e1833e1f | 2407 | cpu_abort(env, "Invalid data load TLB miss exception\n"); |
2be0071f FB |
2408 | break; |
2409 | } | |
e1833e1f JM |
2410 | break; |
2411 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
0411a972 | 2412 | new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */ |
a4f30719 JM |
2413 | if (lpes1 == 0) /* XXX: check this */ |
2414 | new_msr |= (target_ulong)MSR_HVB; | |
e1833e1f | 2415 | switch (excp_model) { |
a750fc0b JM |
2416 | case POWERPC_EXCP_602: |
2417 | case POWERPC_EXCP_603: | |
2418 | case POWERPC_EXCP_603E: | |
2419 | case POWERPC_EXCP_G2: | |
e1833e1f | 2420 | tlb_miss_tgpr: |
76a66253 | 2421 | /* Swap temporary saved registers with GPRs */ |
0411a972 JM |
2422 | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { |
2423 | new_msr |= (target_ulong)1 << MSR_TGPR; | |
2424 | hreg_swap_gpr_tgpr(env); | |
2425 | } | |
e1833e1f JM |
2426 | goto tlb_miss; |
2427 | case POWERPC_EXCP_7x5: | |
2428 | tlb_miss: | |
2be0071f | 2429 | #if defined (DEBUG_SOFTWARE_TLB) |
93fcfe39 | 2430 | if (qemu_log_enabled()) { |
0bf9e31a | 2431 | const char *es; |
76a66253 JM |
2432 | target_ulong *miss, *cmp; |
2433 | int en; | |
1e6784f9 | 2434 | if (excp == POWERPC_EXCP_IFTLB) { |
76a66253 JM |
2435 | es = "I"; |
2436 | en = 'I'; | |
2437 | miss = &env->spr[SPR_IMISS]; | |
2438 | cmp = &env->spr[SPR_ICMP]; | |
2439 | } else { | |
1e6784f9 | 2440 | if (excp == POWERPC_EXCP_DLTLB) |
76a66253 JM |
2441 | es = "DL"; |
2442 | else | |
2443 | es = "DS"; | |
2444 | en = 'D'; | |
2445 | miss = &env->spr[SPR_DMISS]; | |
2446 | cmp = &env->spr[SPR_DCMP]; | |
2447 | } | |
90e189ec BS |
2448 | qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " |
2449 | TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " | |
2450 | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, | |
2451 | env->spr[SPR_HASH1], env->spr[SPR_HASH2], | |
2452 | env->error_code); | |
2be0071f | 2453 | } |
9a64fbe4 | 2454 | #endif |
2be0071f FB |
2455 | msr |= env->crf[0] << 28; |
2456 | msr |= env->error_code; /* key, D/I, S/L bits */ | |
2457 | /* Set way using a LRU mechanism */ | |
76a66253 | 2458 | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; |
c62db105 | 2459 | break; |
7dbe11ac JM |
2460 | case POWERPC_EXCP_74xx: |
2461 | tlb_miss_74xx: | |
2462 | #if defined (DEBUG_SOFTWARE_TLB) | |
93fcfe39 | 2463 | if (qemu_log_enabled()) { |
0bf9e31a | 2464 | const char *es; |
7dbe11ac JM |
2465 | target_ulong *miss, *cmp; |
2466 | int en; | |
2467 | if (excp == POWERPC_EXCP_IFTLB) { | |
2468 | es = "I"; | |
2469 | en = 'I'; | |
0411a972 JM |
2470 | miss = &env->spr[SPR_TLBMISS]; |
2471 | cmp = &env->spr[SPR_PTEHI]; | |
7dbe11ac JM |
2472 | } else { |
2473 | if (excp == POWERPC_EXCP_DLTLB) | |
2474 | es = "DL"; | |
2475 | else | |
2476 | es = "DS"; | |
2477 | en = 'D'; | |
2478 | miss = &env->spr[SPR_TLBMISS]; | |
2479 | cmp = &env->spr[SPR_PTEHI]; | |
2480 | } | |
90e189ec BS |
2481 | qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " |
2482 | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, | |
2483 | env->error_code); | |
7dbe11ac JM |
2484 | } |
2485 | #endif | |
2486 | msr |= env->error_code; /* key bit */ | |
2487 | break; | |
2be0071f | 2488 | default: |
e1833e1f | 2489 | cpu_abort(env, "Invalid data store TLB miss exception\n"); |
2be0071f FB |
2490 | break; |
2491 | } | |
e1833e1f JM |
2492 | goto store_next; |
2493 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ | |
2494 | /* XXX: TODO */ | |
2495 | cpu_abort(env, "Floating point assist exception " | |
2496 | "is not implemented yet !\n"); | |
2497 | goto store_next; | |
b4095fed JM |
2498 | case POWERPC_EXCP_DABR: /* Data address breakpoint */ |
2499 | /* XXX: TODO */ | |
2500 | cpu_abort(env, "DABR exception is not implemented yet !\n"); | |
2501 | goto store_next; | |
e1833e1f JM |
2502 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
2503 | /* XXX: TODO */ | |
2504 | cpu_abort(env, "IABR exception is not implemented yet !\n"); | |
2505 | goto store_next; | |
2506 | case POWERPC_EXCP_SMI: /* System management interrupt */ | |
2507 | /* XXX: TODO */ | |
2508 | cpu_abort(env, "SMI exception is not implemented yet !\n"); | |
2509 | goto store_next; | |
2510 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ | |
2511 | /* XXX: TODO */ | |
2512 | cpu_abort(env, "Thermal management exception " | |
2513 | "is not implemented yet !\n"); | |
2514 | goto store_next; | |
2515 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ | |
0411a972 | 2516 | new_msr &= ~((target_ulong)1 << MSR_RI); |
e1833e1f | 2517 | if (lpes1 == 0) |
a4f30719 | 2518 | new_msr |= (target_ulong)MSR_HVB; |
e1833e1f JM |
2519 | /* XXX: TODO */ |
2520 | cpu_abort(env, | |
2521 | "Performance counter exception is not implemented yet !\n"); | |
2522 | goto store_next; | |
2523 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ | |
2524 | /* XXX: TODO */ | |
2525 | cpu_abort(env, "VPU assist exception is not implemented yet !\n"); | |
2526 | goto store_next; | |
2527 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ | |
2528 | /* XXX: TODO */ | |
2529 | cpu_abort(env, | |
2530 | "970 soft-patch exception is not implemented yet !\n"); | |
2531 | goto store_next; | |
2532 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ | |
2533 | /* XXX: TODO */ | |
2534 | cpu_abort(env, | |
2535 | "970 maintenance exception is not implemented yet !\n"); | |
2536 | goto store_next; | |
b4095fed JM |
2537 | case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ |
2538 | /* XXX: TODO */ | |
2539 | cpu_abort(env, "Maskable external exception " | |
2540 | "is not implemented yet !\n"); | |
2541 | goto store_next; | |
2542 | case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ | |
2543 | /* XXX: TODO */ | |
2544 | cpu_abort(env, "Non maskable external exception " | |
2545 | "is not implemented yet !\n"); | |
2546 | goto store_next; | |
2be0071f | 2547 | default: |
e1833e1f JM |
2548 | excp_invalid: |
2549 | cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp); | |
2550 | break; | |
9a64fbe4 | 2551 | store_current: |
2be0071f | 2552 | /* save current instruction location */ |
e1833e1f | 2553 | env->spr[srr0] = env->nip - 4; |
9a64fbe4 FB |
2554 | break; |
2555 | store_next: | |
2be0071f | 2556 | /* save next instruction location */ |
e1833e1f | 2557 | env->spr[srr0] = env->nip; |
9a64fbe4 FB |
2558 | break; |
2559 | } | |
e1833e1f JM |
2560 | /* Save MSR */ |
2561 | env->spr[srr1] = msr; | |
2562 | /* If any alternate SRR register are defined, duplicate saved values */ | |
2563 | if (asrr0 != -1) | |
2564 | env->spr[asrr0] = env->spr[srr0]; | |
2565 | if (asrr1 != -1) | |
2566 | env->spr[asrr1] = env->spr[srr1]; | |
2be0071f | 2567 | /* If we disactivated any translation, flush TLBs */ |
0411a972 | 2568 | if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) |
2be0071f | 2569 | tlb_flush(env, 1); |
9a64fbe4 | 2570 | /* reload MSR with correct bits */ |
0411a972 JM |
2571 | new_msr &= ~((target_ulong)1 << MSR_EE); |
2572 | new_msr &= ~((target_ulong)1 << MSR_PR); | |
2573 | new_msr &= ~((target_ulong)1 << MSR_FP); | |
2574 | new_msr &= ~((target_ulong)1 << MSR_FE0); | |
2575 | new_msr &= ~((target_ulong)1 << MSR_SE); | |
2576 | new_msr &= ~((target_ulong)1 << MSR_BE); | |
2577 | new_msr &= ~((target_ulong)1 << MSR_FE1); | |
2578 | new_msr &= ~((target_ulong)1 << MSR_IR); | |
2579 | new_msr &= ~((target_ulong)1 << MSR_DR); | |
e1833e1f | 2580 | #if 0 /* Fix this: not on all targets */ |
0411a972 | 2581 | new_msr &= ~((target_ulong)1 << MSR_PMM); |
e1833e1f | 2582 | #endif |
0411a972 JM |
2583 | new_msr &= ~((target_ulong)1 << MSR_LE); |
2584 | if (msr_ile) | |
2585 | new_msr |= (target_ulong)1 << MSR_LE; | |
2586 | else | |
2587 | new_msr &= ~((target_ulong)1 << MSR_LE); | |
e1833e1f JM |
2588 | /* Jump to handler */ |
2589 | vector = env->excp_vectors[excp]; | |
6f2d8978 | 2590 | if (vector == (target_ulong)-1ULL) { |
e1833e1f JM |
2591 | cpu_abort(env, "Raised an exception without defined vector %d\n", |
2592 | excp); | |
2593 | } | |
2594 | vector |= env->excp_prefix; | |
c62db105 | 2595 | #if defined(TARGET_PPC64) |
e1833e1f | 2596 | if (excp_model == POWERPC_EXCP_BOOKE) { |
0411a972 JM |
2597 | if (!msr_icm) { |
2598 | new_msr &= ~((target_ulong)1 << MSR_CM); | |
e1833e1f | 2599 | vector = (uint32_t)vector; |
0411a972 JM |
2600 | } else { |
2601 | new_msr |= (target_ulong)1 << MSR_CM; | |
2602 | } | |
c62db105 | 2603 | } else { |
6ce0ca12 | 2604 | if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { |
0411a972 | 2605 | new_msr &= ~((target_ulong)1 << MSR_SF); |
e1833e1f | 2606 | vector = (uint32_t)vector; |
0411a972 JM |
2607 | } else { |
2608 | new_msr |= (target_ulong)1 << MSR_SF; | |
2609 | } | |
c62db105 | 2610 | } |
e1833e1f | 2611 | #endif |
0411a972 JM |
2612 | /* XXX: we don't use hreg_store_msr here as already have treated |
2613 | * any special case that could occur. Just store MSR and update hflags | |
2614 | */ | |
a4f30719 | 2615 | env->msr = new_msr & env->msr_mask; |
0411a972 | 2616 | hreg_compute_hflags(env); |
e1833e1f JM |
2617 | env->nip = vector; |
2618 | /* Reset exception state */ | |
2619 | env->exception_index = POWERPC_EXCP_NONE; | |
2620 | env->error_code = 0; | |
fb0eaffc | 2621 | } |
47103572 | 2622 | |
e1833e1f | 2623 | void do_interrupt (CPUState *env) |
47103572 | 2624 | { |
e1833e1f JM |
2625 | powerpc_excp(env, env->excp_model, env->exception_index); |
2626 | } | |
47103572 | 2627 | |
e1833e1f JM |
2628 | void ppc_hw_interrupt (CPUPPCState *env) |
2629 | { | |
f9fdea6b | 2630 | int hdice; |
f9fdea6b | 2631 | |
0411a972 | 2632 | #if 0 |
93fcfe39 | 2633 | qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n", |
a496775f | 2634 | __func__, env, env->pending_interrupts, |
0411a972 | 2635 | env->interrupt_request, (int)msr_me, (int)msr_ee); |
47103572 | 2636 | #endif |
e1833e1f | 2637 | /* External reset */ |
47103572 | 2638 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { |
47103572 | 2639 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); |
e1833e1f JM |
2640 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); |
2641 | return; | |
2642 | } | |
2643 | /* Machine check exception */ | |
2644 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { | |
2645 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); | |
2646 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); | |
2647 | return; | |
47103572 | 2648 | } |
e1833e1f JM |
2649 | #if 0 /* TODO */ |
2650 | /* External debug exception */ | |
2651 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { | |
2652 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); | |
2653 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG); | |
2654 | return; | |
2655 | } | |
2656 | #endif | |
b172c56a JM |
2657 | if (0) { |
2658 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
2659 | hdice = env->spr[SPR_LPCR] & 1; | |
2660 | } else { | |
2661 | hdice = 0; | |
2662 | } | |
f9fdea6b | 2663 | if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) { |
47103572 JM |
2664 | /* Hypervisor decrementer exception */ |
2665 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { | |
47103572 | 2666 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); |
e1833e1f JM |
2667 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); |
2668 | return; | |
2669 | } | |
2670 | } | |
e1833e1f JM |
2671 | if (msr_ce != 0) { |
2672 | /* External critical interrupt */ | |
2673 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { | |
2674 | /* Taking a critical external interrupt does not clear the external | |
2675 | * critical interrupt status | |
2676 | */ | |
2677 | #if 0 | |
2678 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT); | |
47103572 | 2679 | #endif |
e1833e1f JM |
2680 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); |
2681 | return; | |
2682 | } | |
2683 | } | |
2684 | if (msr_ee != 0) { | |
2685 | /* Watchdog timer on embedded PowerPC */ | |
2686 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { | |
2687 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); | |
2688 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); | |
2689 | return; | |
2690 | } | |
e1833e1f JM |
2691 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { |
2692 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL); | |
2693 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); | |
2694 | return; | |
2695 | } | |
e1833e1f JM |
2696 | /* Fixed interval timer on embedded PowerPC */ |
2697 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { | |
2698 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); | |
2699 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); | |
2700 | return; | |
2701 | } | |
2702 | /* Programmable interval timer on embedded PowerPC */ | |
2703 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { | |
2704 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); | |
2705 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); | |
2706 | return; | |
2707 | } | |
47103572 JM |
2708 | /* Decrementer exception */ |
2709 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { | |
47103572 | 2710 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); |
e1833e1f JM |
2711 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); |
2712 | return; | |
2713 | } | |
47103572 | 2714 | /* External interrupt */ |
e1833e1f | 2715 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
e9df014c JM |
2716 | /* Taking an external interrupt does not clear the external |
2717 | * interrupt status | |
2718 | */ | |
2719 | #if 0 | |
47103572 | 2720 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT); |
e9df014c | 2721 | #endif |
e1833e1f JM |
2722 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); |
2723 | return; | |
2724 | } | |
e1833e1f JM |
2725 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
2726 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); | |
2727 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); | |
2728 | return; | |
47103572 | 2729 | } |
e1833e1f JM |
2730 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
2731 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM); | |
2732 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); | |
2733 | return; | |
2734 | } | |
2735 | /* Thermal interrupt */ | |
2736 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { | |
2737 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM); | |
2738 | powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); | |
2739 | return; | |
2740 | } | |
47103572 | 2741 | } |
47103572 | 2742 | } |
18fba28c | 2743 | #endif /* !CONFIG_USER_ONLY */ |
a496775f | 2744 | |
4a057712 JM |
2745 | void cpu_dump_rfi (target_ulong RA, target_ulong msr) |
2746 | { | |
90e189ec BS |
2747 | qemu_log("Return from exception at " TARGET_FMT_lx " with flags " |
2748 | TARGET_FMT_lx "\n", RA, msr); | |
a496775f JM |
2749 | } |
2750 | ||
0a032cbe JM |
2751 | void cpu_ppc_reset (void *opaque) |
2752 | { | |
eca1bdf4 | 2753 | CPUPPCState *env = opaque; |
0411a972 | 2754 | target_ulong msr; |
0a032cbe | 2755 | |
eca1bdf4 AL |
2756 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { |
2757 | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index); | |
2758 | log_cpu_state(env, 0); | |
2759 | } | |
2760 | ||
0411a972 | 2761 | msr = (target_ulong)0; |
a4f30719 JM |
2762 | if (0) { |
2763 | /* XXX: find a suitable condition to enable the hypervisor mode */ | |
2764 | msr |= (target_ulong)MSR_HVB; | |
2765 | } | |
0411a972 JM |
2766 | msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ |
2767 | msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ | |
2768 | msr |= (target_ulong)1 << MSR_EP; | |
0a032cbe JM |
2769 | #if defined (DO_SINGLE_STEP) && 0 |
2770 | /* Single step trace mode */ | |
0411a972 JM |
2771 | msr |= (target_ulong)1 << MSR_SE; |
2772 | msr |= (target_ulong)1 << MSR_BE; | |
0a032cbe JM |
2773 | #endif |
2774 | #if defined(CONFIG_USER_ONLY) | |
0411a972 | 2775 | msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ |
4c2ab988 AJ |
2776 | msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ |
2777 | msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ | |
0411a972 | 2778 | msr |= (target_ulong)1 << MSR_PR; |
fe33cc71 | 2779 | #else |
fc1c67bc | 2780 | env->excp_prefix = env->hreset_excp_prefix; |
1c27f8fb | 2781 | env->nip = env->hreset_vector | env->excp_prefix; |
b4095fed | 2782 | if (env->mmu_model != POWERPC_MMU_REAL) |
141c8ae2 | 2783 | ppc_tlb_invalidate_all(env); |
0a032cbe | 2784 | #endif |
07c485ce | 2785 | env->msr = msr & env->msr_mask; |
6ce0ca12 BS |
2786 | #if defined(TARGET_PPC64) |
2787 | if (env->mmu_model & POWERPC_MMU_64) | |
2788 | env->msr |= (1ULL << MSR_SF); | |
2789 | #endif | |
0411a972 | 2790 | hreg_compute_hflags(env); |
18b21a2f | 2791 | env->reserve_addr = (target_ulong)-1ULL; |
5eb7995e JM |
2792 | /* Be sure no exception or interrupt is pending */ |
2793 | env->pending_interrupts = 0; | |
e1833e1f JM |
2794 | env->exception_index = POWERPC_EXCP_NONE; |
2795 | env->error_code = 0; | |
5eb7995e JM |
2796 | /* Flush all TLBs */ |
2797 | tlb_flush(env, 1); | |
0a032cbe JM |
2798 | } |
2799 | ||
aaed909a | 2800 | CPUPPCState *cpu_ppc_init (const char *cpu_model) |
0a032cbe JM |
2801 | { |
2802 | CPUPPCState *env; | |
99a0949b | 2803 | const a_ppc_def *def; |
aaed909a FB |
2804 | |
2805 | def = cpu_ppc_find_by_name(cpu_model); | |
2806 | if (!def) | |
2807 | return NULL; | |
0a032cbe JM |
2808 | |
2809 | env = qemu_mallocz(sizeof(CPUPPCState)); | |
0a032cbe | 2810 | cpu_exec_init(env); |
2e70f6ef | 2811 | ppc_translate_init(); |
01ba9816 | 2812 | env->cpu_model_str = cpu_model; |
aaed909a FB |
2813 | cpu_ppc_register_internal(env, def); |
2814 | cpu_ppc_reset(env); | |
d76d1650 | 2815 | |
0bf46a40 | 2816 | qemu_init_vcpu(env); |
d76d1650 | 2817 | |
0a032cbe JM |
2818 | return env; |
2819 | } | |
2820 | ||
2821 | void cpu_ppc_close (CPUPPCState *env) | |
2822 | { | |
2823 | /* Should also remove all opcode tables... */ | |
aaed909a | 2824 | qemu_free(env); |
0a032cbe | 2825 | } |