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PowerPC 405 microcontrollers fixes and improvments:
[mirror_qemu.git] / target-ppc / helper.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
79aceca5 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
fdabc366
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
27
28#include "cpu.h"
29#include "exec-all.h"
9a64fbe4
FB		 30
31//#define DEBUG_MMU
32//#define DEBUG_BATS
76a66253 33//#define DEBUG_SOFTWARE_TLB
9a64fbe4 34//#define DEBUG_EXCEPTIONS
fdabc366 35//#define FLUSH_ALL_TLBS
9a64fbe4 36
9a64fbe4 37/*****************************************************************************/
3fc6c082 38/* PowerPC MMU emulation */
a541f297 39
d9bce9d9 40#if defined(CONFIG_USER_ONLY)
e96efcfc 41int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
24741ef3
FB		 42 int is_user, int is_softmmu)
43{
44 int exception, error_code;
d9bce9d9 45
24741ef3
FB		 46 if (rw == 2) {
47 exception = EXCP_ISI;
48 error_code = 0;
49 } else {
50 exception = EXCP_DSI;
51 error_code = 0;
52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
76a66253 59
24741ef3
FB		 60 return 1;
61}
76a66253 62
9b3c35e0 63target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
24741ef3
FB		 64{
65 return addr;
66}
67#else
76a66253
JM		 68/* Common routines used by software and hardware TLBs emulation */
69static inline int pte_is_valid (target_ulong pte0)
70{
71 return pte0 & 0x80000000 ? 1 : 0;
72}
73
74static inline void pte_invalidate (target_ulong *pte0)
75{
76 *pte0 &= ~0x80000000;
77}
78
79#define PTE_PTEM_MASK 0x7FFFFFBF
80#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
81
82static int pte_check (mmu_ctx_t *ctx,
83 target_ulong pte0, target_ulong pte1, int h, int rw)
84{
85 int access, ret;
86
87 access = 0;
88 ret = -1;
89 /* Check validity and table match */
90 if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) {
91 /* Check vsid & api */
92 if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {
93 if (ctx->raddr != (target_ulong)-1) {
94 /* all matches should have equal RPN, WIMG & PP */
95 if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
96 if (loglevel > 0)
97 fprintf(logfile, "Bad RPN/WIMG/PP\n");
98 return -3;
99 }
100 }
101 /* Compute access rights */
102 if (ctx->key == 0) {
103 access = PAGE_READ;
104 if ((pte1 & 0x00000003) != 0x3)
105 access |= PAGE_WRITE;
106 } else {
107 switch (pte1 & 0x00000003) {
108 case 0x0:
109 access = 0;
110 break;
111 case 0x1:
112 case 0x3:
113 access = PAGE_READ;
114 break;
115 case 0x2:
116 access = PAGE_READ | PAGE_WRITE;
117 break;
118 }
119 }
120 /* Keep the matching PTE informations */
121 ctx->raddr = pte1;
122 ctx->prot = access;
123 if ((rw == 0 && (access & PAGE_READ)) ||
124 (rw == 1 && (access & PAGE_WRITE))) {
125 /* Access granted */
126#if defined (DEBUG_MMU)
4a057712 127 if (loglevel != 0)
76a66253
JM		 128 fprintf(logfile, "PTE access granted !\n");
129#endif
130 ret = 0;
131 } else {
132 /* Access right violation */
133#if defined (DEBUG_MMU)
4a057712 134 if (loglevel != 0)
76a66253
JM		 135 fprintf(logfile, "PTE access rejected\n");
136#endif
137 ret = -2;
138 }
139 }
140 }
141
142 return ret;
143}
144
145static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
146 int ret, int rw)
147{
148 int store = 0;
149
150 /* Update page flags */
151 if (!(*pte1p & 0x00000100)) {
152 /* Update accessed flag */
153 *pte1p |= 0x00000100;
154 store = 1;
155 }
156 if (!(*pte1p & 0x00000080)) {
157 if (rw == 1 && ret == 0) {
158 /* Update changed flag */
159 *pte1p |= 0x00000080;
160 store = 1;
161 } else {
162 /* Force page fault for first write access */
163 ctx->prot &= ~PAGE_WRITE;
164 }
165 }
166
167 return store;
168}
169
170/* Software driven TLB helpers */
171static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
172 int way, int is_code)
173{
174 int nr;
175
176 /* Select TLB num in a way from address */
177 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
178 /* Select TLB way */
179 nr += env->tlb_per_way * way;
180 /* 6xx have separate TLBs for instructions and data */
181 if (is_code && env->id_tlbs == 1)
182 nr += env->nb_tlb;
183
184 return nr;
185}
186
187void ppc6xx_tlb_invalidate_all (CPUState *env)
188{
1d0a48fb 189 ppc6xx_tlb_t *tlb;
76a66253
JM		 190 int nr, max;
191
192#if defined (DEBUG_SOFTWARE_TLB) && 0
193 if (loglevel != 0) {
194 fprintf(logfile, "Invalidate all TLBs\n");
195 }
196#endif
197 /* Invalidate all defined software TLB */
198 max = env->nb_tlb;
199 if (env->id_tlbs == 1)
200 max *= 2;
201 for (nr = 0; nr < max; nr++) {
1d0a48fb 202 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 203#if !defined(FLUSH_ALL_TLBS)
204 tlb_flush_page(env, tlb->EPN);
205#endif
206 pte_invalidate(&tlb->pte0);
207 }
208#if defined(FLUSH_ALL_TLBS)
209 tlb_flush(env, 1);
210#endif
211}
212
213static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
214 target_ulong eaddr,
215 int is_code, int match_epn)
216{
4a057712 217#if !defined(FLUSH_ALL_TLBS)
1d0a48fb 218 ppc6xx_tlb_t *tlb;
76a66253
JM		 219 int way, nr;
220
76a66253
JM		 221 /* Invalidate ITLB + DTLB, all ways */
222 for (way = 0; way < env->nb_ways; way++) {
223 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
1d0a48fb 224 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 225 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
226#if defined (DEBUG_SOFTWARE_TLB)
227 if (loglevel != 0) {
1b9eb036 228 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
76a66253
JM		 229 nr, env->nb_tlb, eaddr);
230 }
231#endif
232 pte_invalidate(&tlb->pte0);
233 tlb_flush_page(env, tlb->EPN);
234 }
235 }
236#else
237 /* XXX: PowerPC specification say this is valid as well */
238 ppc6xx_tlb_invalidate_all(env);
239#endif
240}
241
242void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
243 int is_code)
244{
245 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
246}
247
248void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
249 target_ulong pte0, target_ulong pte1)
250{
1d0a48fb 251 ppc6xx_tlb_t *tlb;
76a66253
JM		 252 int nr;
253
254 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
1d0a48fb 255 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 256#if defined (DEBUG_SOFTWARE_TLB)
257 if (loglevel != 0) {
1b9eb036
JM		 258 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
259 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
76a66253
JM		 260 }
261#endif
262 /* Invalidate any pending reference in Qemu for this virtual address */
263 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
264 tlb->pte0 = pte0;
265 tlb->pte1 = pte1;
266 tlb->EPN = EPN;
76a66253
JM		 267 /* Store last way for LRU mechanism */
268 env->last_way = way;
269}
270
271static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
272 target_ulong eaddr, int rw, int access_type)
273{
1d0a48fb 274 ppc6xx_tlb_t *tlb;
76a66253
JM		 275 int nr, best, way;
276 int ret;
d9bce9d9 277
76a66253
JM		 278 best = -1;
279 ret = -1; /* No TLB found */
280 for (way = 0; way < env->nb_ways; way++) {
281 nr = ppc6xx_tlb_getnum(env, eaddr, way,
282 access_type == ACCESS_CODE ? 1 : 0);
1d0a48fb 283 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 284 /* This test "emulates" the PTE index match for hardware TLBs */
285 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
286#if defined (DEBUG_SOFTWARE_TLB)
287 if (loglevel != 0) {
1b9eb036
JM		 288 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
289 "] <> " ADDRX "\n",
76a66253
JM		 290 nr, env->nb_tlb,
291 pte_is_valid(tlb->pte0) ? "valid" : "inval",
292 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
293 }
294#endif
295 continue;
296 }
297#if defined (DEBUG_SOFTWARE_TLB)
298 if (loglevel != 0) {
1b9eb036
JM		 299 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
300 " %c %c\n",
76a66253
JM		 301 nr, env->nb_tlb,
302 pte_is_valid(tlb->pte0) ? "valid" : "inval",
303 tlb->EPN, eaddr, tlb->pte1,
304 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
305 }
306#endif
307 switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
308 case -3:
309 /* TLB inconsistency */
310 return -1;
311 case -2:
312 /* Access violation */
313 ret = -2;
314 best = nr;
315 break;
316 case -1:
317 default:
318 /* No match */
319 break;
320 case 0:
321 /* access granted */
322 /* XXX: we should go on looping to check all TLBs consistency
323 * but we can speed-up the whole thing as the
324 * result would be undefined if TLBs are not consistent.
325 */
326 ret = 0;
327 best = nr;
328 goto done;
329 }
330 }
331 if (best != -1) {
332 done:
333#if defined (DEBUG_SOFTWARE_TLB)
4a057712 334 if (loglevel != 0) {
76a66253
JM		 335 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
336 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
337 }
338#endif
339 /* Update page flags */
1d0a48fb 340 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
76a66253
JM		 341 }
342
343 return ret;
344}
345
9a64fbe4 346/* Perform BAT hit & translation */
76a66253
JM		 347static int get_bat (CPUState *env, mmu_ctx_t *ctx,
348 target_ulong virtual, int rw, int type)
9a64fbe4 349{
76a66253
JM		 350 target_ulong *BATlt, *BATut, *BATu, *BATl;
351 target_ulong base, BEPIl, BEPIu, bl;
9a64fbe4
FB		 352 int i;
353 int ret = -1;
354
355#if defined (DEBUG_BATS)
4a057712 356 if (loglevel != 0) {
1b9eb036 357 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 358 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 359 }
9a64fbe4
FB		 360#endif
361 switch (type) {
362 case ACCESS_CODE:
363 BATlt = env->IBAT[1];
364 BATut = env->IBAT[0];
365 break;
366 default:
367 BATlt = env->DBAT[1];
368 BATut = env->DBAT[0];
369 break;
370 }
371#if defined (DEBUG_BATS)
4a057712 372 if (loglevel != 0) {
1b9eb036 373 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 374 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 375 }
9a64fbe4
FB		 376#endif
377 base = virtual & 0xFFFC0000;
378 for (i = 0; i < 4; i++) {
379 BATu = &BATut[i];
380 BATl = &BATlt[i];
381 BEPIu = *BATu & 0xF0000000;
382 BEPIl = *BATu & 0x0FFE0000;
383 bl = (*BATu & 0x00001FFC) << 15;
384#if defined (DEBUG_BATS)
4a057712 385 if (loglevel != 0) {
1b9eb036
JM		 386 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
387 " BATl 0x" ADDRX "\n",
9a64fbe4
FB		 388 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
389 *BATu, *BATl);
9a64fbe4
FB		 390 }
391#endif
392 if ((virtual & 0xF0000000) == BEPIu &&
393 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
394 /* BAT matches */
395 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
396 (msr_pr == 1 && (*BATu & 0x00000001))) {
397 /* Get physical address */
76a66253 398 ctx->raddr = (*BATl & 0xF0000000) |
9a64fbe4 399 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
a541f297 400 (virtual & 0x0001F000);
9a64fbe4 401 if (*BATl & 0x00000001)
76a66253 402 ctx->prot = PAGE_READ;
9a64fbe4 403 if (*BATl & 0x00000002)
76a66253 404 ctx->prot = PAGE_WRITE | PAGE_READ;
9a64fbe4 405#if defined (DEBUG_BATS)
4a057712
JM		 406 if (loglevel != 0) {
407 fprintf(logfile, "BAT %d match: r 0x" PADDRX
1b9eb036 408 " prot=%c%c\n",
76a66253
JM		 409 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
410 ctx->prot & PAGE_WRITE ? 'W' : '-');
9a64fbe4
FB		 411 }
412#endif
413 ret = 0;
414 break;
415 }
416 }
417 }
418 if (ret < 0) {
419#if defined (DEBUG_BATS)
4a057712
JM		 420 if (loglevel != 0) {
421 fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
422 for (i = 0; i < 4; i++) {
423 BATu = &BATut[i];
424 BATl = &BATlt[i];
425 BEPIu = *BATu & 0xF0000000;
426 BEPIl = *BATu & 0x0FFE0000;
427 bl = (*BATu & 0x00001FFC) << 15;
428 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
429 " BATl 0x" ADDRX " \n\t"
430 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
431 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
432 *BATu, *BATl, BEPIu, BEPIl, bl);
433 }
9a64fbe4
FB		 434 }
435#endif
9a64fbe4
FB		 436 }
437 /* No hit */
438 return ret;
439}
440
441/* PTE table lookup */
76a66253 442static int find_pte (mmu_ctx_t *ctx, int h, int rw)
9a64fbe4 443{
76a66253
JM		 444 target_ulong base, pte0, pte1;
445 int i, good = -1;
446 int ret;
9a64fbe4 447
76a66253
JM		 448 ret = -1; /* No entry found */
449 base = ctx->pg_addr[h];
9a64fbe4 450 for (i = 0; i < 8; i++) {
8df1cd07
FB		 451 pte0 = ldl_phys(base + (i * 8));
452 pte1 = ldl_phys(base + (i * 8) + 4);
9a64fbe4 453#if defined (DEBUG_MMU)
d094807b 454 if (loglevel > 0) {
1b9eb036
JM		 455 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
456 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
457 base + (i * 8), pte0, pte1,
76a66253
JM		 458 pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem);
459 }
9a64fbe4 460#endif
76a66253
JM		 461 switch (pte_check(ctx, pte0, pte1, h, rw)) {
462 case -3:
463 /* PTE inconsistency */
464 return -1;
465 case -2:
466 /* Access violation */
467 ret = -2;
468 good = i;
469 break;
470 case -1:
471 default:
472 /* No PTE match */
473 break;
474 case 0:
475 /* access granted */
476 /* XXX: we should go on looping to check all PTEs consistency
477 * but if we can speed-up the whole thing as the
478 * result would be undefined if PTEs are not consistent.
479 */
480 ret = 0;
481 good = i;
482 goto done;
9a64fbe4
FB		 483 }
484 }
485 if (good != -1) {
76a66253 486 done:
9a64fbe4 487#if defined (DEBUG_MMU)
4a057712
JM		 488 if (loglevel != 0) {
489 fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
1b9eb036 490 "ret=%d\n",
76a66253
JM		 491 ctx->raddr, ctx->prot, ret);
492 }
9a64fbe4
FB		 493#endif
494 /* Update page flags */
76a66253
JM		 495 pte1 = ctx->raddr;
496 if (pte_update_flags(ctx, &pte1, ret, rw) == 1)
497 stl_phys_notdirty(base + (good * 8) + 4, pte1);
9a64fbe4
FB		 498 }
499
500 return ret;
79aceca5
FB		 501}
502
76a66253
JM		 503static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
504 target_phys_addr_t hash,
505 target_phys_addr_t mask)
79aceca5 506{
9a64fbe4 507 return (sdr1 & 0xFFFF0000) | (hash & mask);
79aceca5
FB		 508}
509
9a64fbe4 510/* Perform segment based translation */
76a66253
JM		 511static int get_segment (CPUState *env, mmu_ctx_t *ctx,
512 target_ulong eaddr, int rw, int type)
79aceca5 513{
76a66253
JM		 514 target_phys_addr_t sdr, hash, mask;
515 target_ulong sr, vsid, pgidx;
9a64fbe4 516 int ret = -1, ret2;
79aceca5 517
76a66253 518 sr = env->sr[eaddr >> 28];
9a64fbe4 519#if defined (DEBUG_MMU)
a541f297 520 if (loglevel > 0) {
1b9eb036
JM		 521 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x"
522 ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
76a66253
JM		 523 eaddr, eaddr >> 28, sr, env->nip,
524 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
a541f297 525 }
9a64fbe4 526#endif
76a66253
JM		 527 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
528 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
9a64fbe4
FB		 529 if ((sr & 0x80000000) == 0) {
530#if defined (DEBUG_MMU)
76a66253 531 if (loglevel > 0)
1b9eb036 532 fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
76a66253 533 ctx->key, sr & 0x10000000);
9a64fbe4
FB		 534#endif
535 /* Check if instruction fetch is allowed, if needed */
536 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
537 /* Page address translation */
76a66253 538 pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;
9a64fbe4 539 vsid = sr & 0x00FFFFFF;
a541f297 540 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
76a66253
JM		 541 /* Primary table address */
542 sdr = env->sdr1;
9a64fbe4 543 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
76a66253
JM		 544 ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);
545 /* Secondary table address */
546 hash = (~hash) & 0x01FFFFC0;
547 ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);
548 ctx->ptem = (vsid << 7) | (pgidx >> 10);
549 /* Initialize real address with an invalid value */
550 ctx->raddr = (target_ulong)-1;
551 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
552 /* Software TLB search */
553 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
76a66253 554 } else {
9a64fbe4 555#if defined (DEBUG_MMU)
4a057712
JM		 556 if (loglevel != 0) {
557 fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
558 "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
559 sdr, (uint32_t)vsid, (uint32_t)pgidx,
560 (uint32_t)hash, ctx->pg_addr[0]);
76a66253 561 }
9a64fbe4 562#endif
76a66253
JM		 563 /* Primary table lookup */
564 ret = find_pte(ctx, 0, rw);
565 if (ret < 0) {
566 /* Secondary table lookup */
9a64fbe4 567#if defined (DEBUG_MMU)
4a057712 568 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
76a66253 569 fprintf(logfile,
4a057712
JM		 570 "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
571 "hash=0x%05x pg_addr=0x" PADDRX "\n",
572 sdr, (uint32_t)vsid, (uint32_t)pgidx,
573 (uint32_t)hash, ctx->pg_addr[1]);
76a66253 574 }
9a64fbe4 575#endif
76a66253
JM		 576 ret2 = find_pte(ctx, 1, rw);
577 if (ret2 != -1)
578 ret = ret2;
579 }
9a64fbe4 580 }
9a64fbe4
FB		 581 } else {
582#if defined (DEBUG_MMU)
4a057712 583 if (loglevel != 0)
76a66253 584 fprintf(logfile, "No access allowed\n");
9a64fbe4 585#endif
76a66253 586 ret = -3;
9a64fbe4
FB		 587 }
588 } else {
589#if defined (DEBUG_MMU)
4a057712 590 if (loglevel != 0)
76a66253 591 fprintf(logfile, "direct store...\n");
9a64fbe4
FB		 592#endif
593 /* Direct-store segment : absolutely *BUGGY* for now */
594 switch (type) {
595 case ACCESS_INT:
596 /* Integer load/store : only access allowed */
597 break;
598 case ACCESS_CODE:
599 /* No code fetch is allowed in direct-store areas */
600 return -4;
601 case ACCESS_FLOAT:
602 /* Floating point load/store */
603 return -4;
604 case ACCESS_RES:
605 /* lwarx, ldarx or srwcx. */
606 return -4;
607 case ACCESS_CACHE:
608 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
609 /* Should make the instruction do no-op.
610 * As it already do no-op, it's quite easy :-)
611 */
76a66253 612 ctx->raddr = eaddr;
9a64fbe4
FB		 613 return 0;
614 case ACCESS_EXT:
615 /* eciwx or ecowx */
616 return -4;
617 default:
618 if (logfile) {
619 fprintf(logfile, "ERROR: instruction should not need "
620 "address translation\n");
621 }
9a64fbe4
FB		 622 return -4;
623 }
76a66253
JM		 624 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
625 ctx->raddr = eaddr;
9a64fbe4
FB		 626 ret = 2;
627 } else {
628 ret = -2;
629 }
79aceca5 630 }
9a64fbe4
FB		 631
632 return ret;
79aceca5
FB		 633}
634
0a032cbe
JM		 635void ppc4xx_tlb_invalidate_all (CPUState *env)
636{
637 ppcemb_tlb_t *tlb;
638 int i;
639
640 for (i = 0; i < env->nb_tlb; i++) {
641 tlb = &env->tlb[i].tlbe;
642 if (tlb->prot & PAGE_VALID) {
643#if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.
644 end = tlb->EPN + tlb->size;
645 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
646 tlb_flush_page(env, page);
647#endif
648 tlb->prot &= ~PAGE_VALID;
649 }
650 }
651 tlb_flush(env, 1);
652}
653
a8dea12f 654int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
e96efcfc 655 target_ulong address, int rw, int access_type)
a8dea12f
JM		 656{
657 ppcemb_tlb_t *tlb;
658 target_phys_addr_t raddr;
659 target_ulong mask;
660 int i, ret, zsel, zpr;
661
c55e9aef
JM		 662 ret = -1;
663 raddr = -1;
a8dea12f
JM		 664 for (i = 0; i < env->nb_tlb; i++) {
665 tlb = &env->tlb[i].tlbe;
666 /* Check valid flag */
667 if (!(tlb->prot & PAGE_VALID)) {
4a057712 668 if (loglevel != 0)
a8dea12f
JM		 669 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
670 continue;
671 }
672 mask = ~(tlb->size - 1);
4a057712 673 if (loglevel != 0) {
a496775f
JM		 674 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
675 ADDRX " " ADDRX " %d\n",
676 __func__, i, address, (int)env->spr[SPR_40x_PID],
677 tlb->EPN, mask, (int)tlb->PID);
a8dea12f
JM		 678 }
679 /* Check PID */
680 if (tlb->PID != 0 && tlb->PID != env->spr[SPR_40x_PID])
681 continue;
682 /* Check effective address */
683 if ((address & mask) != tlb->EPN)
684 continue;
685 raddr = (tlb->RPN & mask) | (address & ~mask);
686 zsel = (tlb->attr >> 4) & 0xF;
687 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
4a057712 688 if (loglevel != 0) {
a8dea12f
JM		 689 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
690 __func__, i, zsel, zpr, rw, tlb->attr);
691 }
692 if (access_type == ACCESS_CODE) {
693 /* Check execute enable bit */
694 switch (zpr) {
695 case 0x0:
696 if (msr_pr) {
a8dea12f 697 ctx->prot = 0;
c55e9aef 698 ret = -3;
a8dea12f
JM		 699 break;
700 }
701 /* No break here */
702 case 0x1:
703 case 0x2:
704 /* Check from TLB entry */
705 if (!(tlb->prot & PAGE_EXEC)) {
706 ret = -3;
707 } else {
c55e9aef 708 if (tlb->prot & PAGE_WRITE) {
a8dea12f 709 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 710 } else {
a8dea12f 711 ctx->prot = PAGE_READ;
c55e9aef 712 }
a8dea12f
JM		 713 ret = 0;
714 }
715 break;
716 case 0x3:
717 /* All accesses granted */
a8dea12f 718 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 719 ret = 0;
a8dea12f
JM		 720 break;
721 }
722 } else {
723 switch (zpr) {
724 case 0x0:
725 if (msr_pr) {
a8dea12f 726 ctx->prot = 0;
c55e9aef 727 ret = -2;
a8dea12f
JM		 728 break;
729 }
730 /* No break here */
731 case 0x1:
732 case 0x2:
733 /* Check from TLB entry */
734 /* Check write protection bit */
c55e9aef
JM		 735 if (tlb->prot & PAGE_WRITE) {
736 ctx->prot = PAGE_READ | PAGE_WRITE;
737 ret = 0;
a8dea12f 738 } else {
c55e9aef
JM		 739 ctx->prot = PAGE_READ;
740 if (rw)
741 ret = -2;
a8dea12f 742 else
c55e9aef 743 ret = 0;
a8dea12f
JM		 744 }
745 break;
746 case 0x3:
747 /* All accesses granted */
a8dea12f 748 ctx->prot = PAGE_READ | PAGE_WRITE;
c55e9aef 749 ret = 0;
a8dea12f
JM		 750 break;
751 }
752 }
753 if (ret >= 0) {
754 ctx->raddr = raddr;
4a057712 755 if (loglevel != 0) {
a8dea12f 756 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
c55e9aef
JM		 757 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
758 ret);
a8dea12f 759 }
c55e9aef 760 return 0;
a8dea12f
JM		 761 }
762 }
4a057712 763 if (loglevel != 0) {
c55e9aef
JM		 764 fprintf(logfile, "%s: access refused " ADDRX " => " REGX
765 " %d %d\n", __func__, address, raddr, ctx->prot,
766 ret);
767 }
a8dea12f
JM		 768
769 return ret;
770}
771
76a66253
JM		 772static int check_physical (CPUState *env, mmu_ctx_t *ctx,
773 target_ulong eaddr, int rw)
774{
775 int in_plb, ret;
776
777 ctx->raddr = eaddr;
778 ctx->prot = PAGE_READ;
779 ret = 0;
780 if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) {
781 /* 403 family add some particular protections,
782 * using PBL/PBU registers for accesses with no translation.
783 */
784 in_plb =
785 /* Check PLB validity */
786 (env->pb[0] < env->pb[1] &&
787 /* and address in plb area */
788 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
789 (env->pb[2] < env->pb[3] &&
790 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
791 if (in_plb ^ msr_px) {
792 /* Access in protected area */
793 if (rw == 1) {
794 /* Access is not allowed */
795 ret = -2;
796 }
797 } else {
798 /* Read-write access is allowed */
799 ctx->prot |= PAGE_WRITE;
800 }
801 } else {
802 ctx->prot |= PAGE_WRITE;
803 }
804
805 return ret;
806}
807
808int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
809 int rw, int access_type, int check_BATs)
9a64fbe4
FB		 810{
811 int ret;
514fb8c1 812#if 0
4a057712 813 if (loglevel != 0) {
9a64fbe4
FB		 814 fprintf(logfile, "%s\n", __func__);
815 }
d9bce9d9 816#endif
4b3686fa
FB		 817 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
818 (access_type != ACCESS_CODE && msr_dr == 0)) {
9a64fbe4 819 /* No address translation */
76a66253 820 ret = check_physical(env, ctx, eaddr, rw);
9a64fbe4 821 } else {
c55e9aef 822 ret = -1;
a8dea12f
JM		 823 switch (PPC_MMU(env)) {
824 case PPC_FLAGS_MMU_32B:
825 case PPC_FLAGS_MMU_SOFT_6xx:
826 /* Try to find a BAT */
a8dea12f
JM		 827 if (check_BATs)
828 ret = get_bat(env, ctx, eaddr, rw, access_type);
c55e9aef
JM		 829 /* No break here */
830#if defined(TARGET_PPC64)
831 case PPC_FLAGS_MMU_64B:
832 case PPC_FLAGS_MMU_64BRIDGE:
833#endif
a8dea12f 834 if (ret < 0) {
c55e9aef 835 /* We didn't match any BAT entry or don't have BATs */
a8dea12f
JM		 836 ret = get_segment(env, ctx, eaddr, rw, access_type);
837 }
838 break;
839 case PPC_FLAGS_MMU_SOFT_4xx:
c55e9aef 840 case PPC_FLAGS_MMU_403:
a8dea12f
JM		 841 ret = mmu4xx_get_physical_address(env, ctx, eaddr,
842 rw, access_type);
843 break;
c55e9aef
JM		 844 case PPC_FLAGS_MMU_601:
845 /* XXX: TODO */
846 cpu_abort(env, "601 MMU model not implemented\n");
847 return -1;
848 case PPC_FLAGS_MMU_BOOKE:
a8dea12f 849 /* XXX: TODO */
c55e9aef
JM		 850 cpu_abort(env, "BookeE MMU model not implemented\n");
851 return -1;
852 case PPC_FLAGS_MMU_BOOKE_FSL:
853 /* XXX: TODO */
854 cpu_abort(env, "BookE FSL MMU model not implemented\n");
855 return -1;
856 default:
857 cpu_abort(env, "Unknown or invalid MMU model\n");
a8dea12f 858 return -1;
9a64fbe4
FB		 859 }
860 }
514fb8c1 861#if 0
4a057712
JM		 862 if (loglevel != 0) {
863 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
c55e9aef 864 __func__, eaddr, ret, ctx->raddr);
a541f297 865 }
76a66253 866#endif
d9bce9d9 867
9a64fbe4
FB		 868 return ret;
869}
870
9b3c35e0 871target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
a6b025d3 872{
76a66253 873 mmu_ctx_t ctx;
a6b025d3 874
76a66253 875 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
a6b025d3 876 return -1;
76a66253
JM		 877
878 return ctx.raddr & TARGET_PAGE_MASK;
a6b025d3 879}
9a64fbe4 880
9a64fbe4 881/* Perform address translation */
e96efcfc 882int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
a541f297 883 int is_user, int is_softmmu)
9a64fbe4 884{
76a66253 885 mmu_ctx_t ctx;
9a64fbe4 886 int exception = 0, error_code = 0;
a541f297 887 int access_type;
9a64fbe4 888 int ret = 0;
d9bce9d9 889
b769d8fe
FB		 890 if (rw == 2) {
891 /* code access */
892 rw = 0;
893 access_type = ACCESS_CODE;
894 } else {
895 /* data access */
896 /* XXX: put correct access by using cpu_restore_state()
897 correctly */
898 access_type = ACCESS_INT;
899 // access_type = env->access_type;
900 }
76a66253 901 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
9a64fbe4 902 if (ret == 0) {
76a66253
JM		 903 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
904 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
905 is_user, is_softmmu);
9a64fbe4 906 } else if (ret < 0) {
9a64fbe4 907#if defined (DEBUG_MMU)
4a057712 908 if (loglevel != 0)
76a66253 909 cpu_dump_state(env, logfile, fprintf, 0);
9a64fbe4
FB		 910#endif
911 if (access_type == ACCESS_CODE) {
912 exception = EXCP_ISI;
913 switch (ret) {
914 case -1:
76a66253 915 /* No matches in page tables or TLB */
c55e9aef
JM		 916 switch (PPC_MMU(env)) {
917 case PPC_FLAGS_MMU_SOFT_6xx:
76a66253
JM		 918 exception = EXCP_I_TLBMISS;
919 env->spr[SPR_IMISS] = address;
920 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
921 error_code = 1 << 18;
922 goto tlb_miss;
c55e9aef
JM		 923 case PPC_FLAGS_MMU_SOFT_4xx:
924 case PPC_FLAGS_MMU_403:
a8dea12f
JM		 925 exception = EXCP_40x_ITLBMISS;
926 error_code = 0;
927 env->spr[SPR_40x_DEAR] = address;
928 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef
JM		 929 break;
930 case PPC_FLAGS_MMU_32B:
76a66253 931 error_code = 0x40000000;
c55e9aef
JM		 932 break;
933#if defined(TARGET_PPC64)
934 case PPC_FLAGS_MMU_64B:
935 /* XXX: TODO */
936 cpu_abort(env, "MMU model not implemented\n");
937 return -1;
938 case PPC_FLAGS_MMU_64BRIDGE:
939 /* XXX: TODO */
940 cpu_abort(env, "MMU model not implemented\n");
941 return -1;
942#endif
943 case PPC_FLAGS_MMU_601:
944 /* XXX: TODO */
945 cpu_abort(env, "MMU model not implemented\n");
946 return -1;
947 case PPC_FLAGS_MMU_BOOKE:
948 /* XXX: TODO */
949 cpu_abort(env, "MMU model not implemented\n");
950 return -1;
951 case PPC_FLAGS_MMU_BOOKE_FSL:
952 /* XXX: TODO */
953 cpu_abort(env, "MMU model not implemented\n");
954 return -1;
955 default:
956 cpu_abort(env, "Unknown or invalid MMU model\n");
957 return -1;
76a66253 958 }
9a64fbe4
FB		 959 break;
960 case -2:
961 /* Access rights violation */
2be0071f 962 error_code = 0x08000000;
9a64fbe4
FB		 963 break;
964 case -3:
76a66253 965 /* No execute protection violation */
2be0071f 966 error_code = 0x10000000;
9a64fbe4
FB		 967 break;
968 case -4:
969 /* Direct store exception */
970 /* No code fetch is allowed in direct-store areas */
2be0071f
FB		 971 error_code = 0x10000000;
972 break;
973 case -5:
974 /* No match in segment table */
975 exception = EXCP_ISEG;
976 error_code = 0;
9a64fbe4
FB		 977 break;
978 }
979 } else {
980 exception = EXCP_DSI;
981 switch (ret) {
982 case -1:
76a66253 983 /* No matches in page tables or TLB */
c55e9aef
JM		 984 switch (PPC_MMU(env)) {
985 case PPC_FLAGS_MMU_SOFT_6xx:
76a66253
JM		 986 if (rw == 1) {
987 exception = EXCP_DS_TLBMISS;
988 error_code = 1 << 16;
989 } else {
990 exception = EXCP_DL_TLBMISS;
991 error_code = 0;
992 }
993 env->spr[SPR_DMISS] = address;
994 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
995 tlb_miss:
996 error_code |= ctx.key << 19;
997 env->spr[SPR_HASH1] = ctx.pg_addr[0];
998 env->spr[SPR_HASH2] = ctx.pg_addr[1];
999 /* Do not alter DAR nor DSISR */
1000 goto out;
c55e9aef
JM		 1001 case PPC_FLAGS_MMU_SOFT_4xx:
1002 case PPC_FLAGS_MMU_403:
a8dea12f
JM		 1003 exception = EXCP_40x_DTLBMISS;
1004 error_code = 0;
1005 env->spr[SPR_40x_DEAR] = address;
1006 if (rw)
1007 env->spr[SPR_40x_ESR] = 0x00800000;
1008 else
1009 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef
JM		 1010 break;
1011 case PPC_FLAGS_MMU_32B:
76a66253 1012 error_code = 0x40000000;
c55e9aef
JM		 1013 break;
1014#if defined(TARGET_PPC64)
1015 case PPC_FLAGS_MMU_64B:
1016 /* XXX: TODO */
1017 cpu_abort(env, "MMU model not implemented\n");
1018 return -1;
1019 case PPC_FLAGS_MMU_64BRIDGE:
1020 /* XXX: TODO */
1021 cpu_abort(env, "MMU model not implemented\n");
1022 return -1;
1023#endif
1024 case PPC_FLAGS_MMU_601:
1025 /* XXX: TODO */
1026 cpu_abort(env, "MMU model not implemented\n");
1027 return -1;
1028 case PPC_FLAGS_MMU_BOOKE:
1029 /* XXX: TODO */
1030 cpu_abort(env, "MMU model not implemented\n");
1031 return -1;
1032 case PPC_FLAGS_MMU_BOOKE_FSL:
1033 /* XXX: TODO */
1034 cpu_abort(env, "MMU model not implemented\n");
1035 return -1;
1036 default:
1037 cpu_abort(env, "Unknown or invalid MMU model\n");
1038 return -1;
76a66253 1039 }
9a64fbe4
FB		 1040 break;
1041 case -2:
1042 /* Access rights violation */
2be0071f 1043 error_code = 0x08000000;
9a64fbe4
FB		 1044 break;
1045 case -4:
1046 /* Direct store exception */
1047 switch (access_type) {
1048 case ACCESS_FLOAT:
1049 /* Floating point load/store */
1050 exception = EXCP_ALIGN;
1051 error_code = EXCP_ALIGN_FP;
1052 break;
1053 case ACCESS_RES:
1054 /* lwarx, ldarx or srwcx. */
2be0071f 1055 error_code = 0x04000000;
9a64fbe4
FB		 1056 break;
1057 case ACCESS_EXT:
1058 /* eciwx or ecowx */
2be0071f 1059 error_code = 0x04100000;
9a64fbe4
FB		 1060 break;
1061 default:
76a66253 1062 printf("DSI: invalid exception (%d)\n", ret);
9a64fbe4
FB		 1063 exception = EXCP_PROGRAM;
1064 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
1065 break;
1066 }
fdabc366 1067 break;
2be0071f
FB		 1068 case -5:
1069 /* No match in segment table */
1070 exception = EXCP_DSEG;
1071 error_code = 0;
1072 break;
9a64fbe4 1073 }
fdabc366 1074 if (exception == EXCP_DSI && rw == 1)
2be0071f 1075 error_code |= 0x02000000;
76a66253
JM		 1076 /* Store fault address */
1077 env->spr[SPR_DAR] = address;
2be0071f 1078 env->spr[SPR_DSISR] = error_code;
9a64fbe4 1079 }
76a66253 1080 out:
9a64fbe4
FB		 1081#if 0
1082 printf("%s: set exception to %d %02x\n",
1083 __func__, exception, error_code);
1084#endif
1085 env->exception_index = exception;
1086 env->error_code = error_code;
9a64fbe4
FB		 1087 ret = 1;
1088 }
76a66253 1089
9a64fbe4
FB		 1090 return ret;
1091}
1092
3fc6c082
FB		 1093/*****************************************************************************/
1094/* BATs management */
1095#if !defined(FLUSH_ALL_TLBS)
1096static inline void do_invalidate_BAT (CPUPPCState *env,
1097 target_ulong BATu, target_ulong mask)
1098{
1099 target_ulong base, end, page;
76a66253 1100
3fc6c082
FB		 1101 base = BATu & ~0x0001FFFF;
1102 end = base + mask + 0x00020000;
1103#if defined (DEBUG_BATS)
76a66253 1104 if (loglevel != 0) {
1b9eb036 1105 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
76a66253
JM		 1106 base, end, mask);
1107 }
3fc6c082
FB		 1108#endif
1109 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1110 tlb_flush_page(env, page);
1111#if defined (DEBUG_BATS)
1112 if (loglevel != 0)
1113 fprintf(logfile, "Flush done\n");
1114#endif
1115}
1116#endif
1117
1118static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
1119 target_ulong value)
1120{
1121#if defined (DEBUG_BATS)
1122 if (loglevel != 0) {
1b9eb036
JM		 1123 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1124 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
3fc6c082
FB		 1125 }
1126#endif
1127}
1128
1129target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1130{
1131 return env->IBAT[0][nr];
1132}
1133
1134target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1135{
1136 return env->IBAT[1][nr];
1137}
1138
1139void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1140{
1141 target_ulong mask;
1142
1143 dump_store_bat(env, 'I', 0, nr, value);
1144 if (env->IBAT[0][nr] != value) {
1145 mask = (value << 15) & 0x0FFE0000UL;
1146#if !defined(FLUSH_ALL_TLBS)
1147 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1148#endif
1149 /* When storing valid upper BAT, mask BEPI and BRPN
1150 * and invalidate all TLBs covered by this BAT
1151 */
1152 mask = (value << 15) & 0x0FFE0000UL;
1153 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1154 (value & ~0x0001FFFFUL & ~mask);
1155 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1156 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1157#if !defined(FLUSH_ALL_TLBS)
1158 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
76a66253 1159#else
3fc6c082
FB		 1160 tlb_flush(env, 1);
1161#endif
1162 }
1163}
1164
1165void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1166{
1167 dump_store_bat(env, 'I', 1, nr, value);
1168 env->IBAT[1][nr] = value;
1169}
1170
1171target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1172{
1173 return env->DBAT[0][nr];
1174}
1175
1176target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1177{
1178 return env->DBAT[1][nr];
1179}
1180
1181void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1182{
1183 target_ulong mask;
1184
1185 dump_store_bat(env, 'D', 0, nr, value);
1186 if (env->DBAT[0][nr] != value) {
1187 /* When storing valid upper BAT, mask BEPI and BRPN
1188 * and invalidate all TLBs covered by this BAT
1189 */
1190 mask = (value << 15) & 0x0FFE0000UL;
1191#if !defined(FLUSH_ALL_TLBS)
1192 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1193#endif
1194 mask = (value << 15) & 0x0FFE0000UL;
1195 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1196 (value & ~0x0001FFFFUL & ~mask);
1197 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1198 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1199#if !defined(FLUSH_ALL_TLBS)
1200 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1201#else
1202 tlb_flush(env, 1);
1203#endif
1204 }
1205}
1206
1207void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1208{
1209 dump_store_bat(env, 'D', 1, nr, value);
1210 env->DBAT[1][nr] = value;
1211}
1212
0a032cbe
JM		 1213
1214/*****************************************************************************/
1215/* TLB management */
1216void ppc_tlb_invalidate_all (CPUPPCState *env)
1217{
1218 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
1219 ppc6xx_tlb_invalidate_all(env);
1220 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
1221 ppc4xx_tlb_invalidate_all(env);
1222 } else {
1223 tlb_flush(env, 1);
1224 }
1225}
1226
3fc6c082
FB		 1227/*****************************************************************************/
1228/* Special registers manipulation */
d9bce9d9
JM		 1229#if defined(TARGET_PPC64)
1230target_ulong ppc_load_asr (CPUPPCState *env)
1231{
1232 return env->asr;
1233}
1234
1235void ppc_store_asr (CPUPPCState *env, target_ulong value)
1236{
1237 if (env->asr != value) {
1238 env->asr = value;
1239 tlb_flush(env, 1);
1240 }
1241}
1242#endif
1243
3fc6c082
FB		 1244target_ulong do_load_sdr1 (CPUPPCState *env)
1245{
1246 return env->sdr1;
1247}
1248
1249void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1250{
1251#if defined (DEBUG_MMU)
1252 if (loglevel != 0) {
1b9eb036 1253 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
3fc6c082
FB		 1254 }
1255#endif
1256 if (env->sdr1 != value) {
1257 env->sdr1 = value;
76a66253 1258 tlb_flush(env, 1);
3fc6c082
FB		 1259 }
1260}
1261
1262target_ulong do_load_sr (CPUPPCState *env, int srnum)
1263{
1264 return env->sr[srnum];
1265}
1266
1267void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1268{
1269#if defined (DEBUG_MMU)
1270 if (loglevel != 0) {
1b9eb036
JM		 1271 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1272 __func__, srnum, value, env->sr[srnum]);
3fc6c082
FB		 1273 }
1274#endif
1275 if (env->sr[srnum] != value) {
1276 env->sr[srnum] = value;
1277#if !defined(FLUSH_ALL_TLBS) && 0
1278 {
1279 target_ulong page, end;
1280 /* Invalidate 256 MB of virtual memory */
1281 page = (16 << 20) * srnum;
1282 end = page + (16 << 20);
1283 for (; page != end; page += TARGET_PAGE_SIZE)
1284 tlb_flush_page(env, page);
1285 }
1286#else
76a66253 1287 tlb_flush(env, 1);
3fc6c082
FB		 1288#endif
1289 }
1290}
76a66253 1291#endif /* !defined (CONFIG_USER_ONLY) */
3fc6c082 1292
76a66253 1293uint32_t ppc_load_xer (CPUPPCState *env)
79aceca5
FB		 1294{
1295 return (xer_so << XER_SO) |
1296 (xer_ov << XER_OV) |
1297 (xer_ca << XER_CA) |
3fc6c082
FB		 1298 (xer_bc << XER_BC) |
1299 (xer_cmp << XER_CMP);
79aceca5
FB		 1300}
1301
76a66253 1302void ppc_store_xer (CPUPPCState *env, uint32_t value)
79aceca5
FB		 1303{
1304 xer_so = (value >> XER_SO) & 0x01;
1305 xer_ov = (value >> XER_OV) & 0x01;
1306 xer_ca = (value >> XER_CA) & 0x01;
3fc6c082 1307 xer_cmp = (value >> XER_CMP) & 0xFF;
d9bce9d9 1308 xer_bc = (value >> XER_BC) & 0x7F;
79aceca5
FB		 1309}
1310
76a66253
JM		 1311/* Swap temporary saved registers with GPRs */
1312static inline void swap_gpr_tgpr (CPUPPCState *env)
79aceca5 1313{
76a66253
JM		 1314 ppc_gpr_t tmp;
1315
1316 tmp = env->gpr[0];
1317 env->gpr[0] = env->tgpr[0];
1318 env->tgpr[0] = tmp;
1319 tmp = env->gpr[1];
1320 env->gpr[1] = env->tgpr[1];
1321 env->tgpr[1] = tmp;
1322 tmp = env->gpr[2];
1323 env->gpr[2] = env->tgpr[2];
1324 env->tgpr[2] = tmp;
1325 tmp = env->gpr[3];
1326 env->gpr[3] = env->tgpr[3];
1327 env->tgpr[3] = tmp;
79aceca5
FB		 1328}
1329
76a66253
JM		 1330/* GDBstub can read and write MSR... */
1331target_ulong do_load_msr (CPUPPCState *env)
79aceca5 1332{
76a66253
JM		 1333 return
1334#if defined (TARGET_PPC64)
d9bce9d9
JM		 1335 ((target_ulong)msr_sf << MSR_SF) |
1336 ((target_ulong)msr_isf << MSR_ISF) |
1337 ((target_ulong)msr_hv << MSR_HV) |
76a66253 1338#endif
d9bce9d9
JM		 1339 ((target_ulong)msr_ucle << MSR_UCLE) |
1340 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1341 ((target_ulong)msr_ap << MSR_AP) |
1342 ((target_ulong)msr_sa << MSR_SA) |
1343 ((target_ulong)msr_key << MSR_KEY) |
1344 ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
1345 ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
1346 ((target_ulong)msr_ile << MSR_ILE) |
1347 ((target_ulong)msr_ee << MSR_EE) |
1348 ((target_ulong)msr_pr << MSR_PR) |
1349 ((target_ulong)msr_fp << MSR_FP) |
1350 ((target_ulong)msr_me << MSR_ME) |
1351 ((target_ulong)msr_fe0 << MSR_FE0) |
1352 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1353 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1354 ((target_ulong)msr_fe1 << MSR_FE1) |
1355 ((target_ulong)msr_al << MSR_AL) |
1356 ((target_ulong)msr_ip << MSR_IP) |
1357 ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
1358 ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
1359 ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
1360 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1361 ((target_ulong)msr_ri << MSR_RI) |
1362 ((target_ulong)msr_le << MSR_LE);
3fc6c082
FB		 1363}
1364
1365void do_store_msr (CPUPPCState *env, target_ulong value)
313adae9 1366{
50443c98
FB		 1367 int enter_pm;
1368
3fc6c082
FB		 1369 value &= env->msr_mask;
1370 if (((value >> MSR_IR) & 1) != msr_ir ||
1371 ((value >> MSR_DR) & 1) != msr_dr) {
76a66253 1372 /* Flush all tlb when changing translation mode */
d094807b 1373 tlb_flush(env, 1);
3fc6c082 1374 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
a541f297 1375 }
3fc6c082
FB		 1376#if 0
1377 if (loglevel != 0) {
1378 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1379 }
1380#endif
76a66253
JM		 1381 switch (PPC_EXCP(env)) {
1382 case PPC_FLAGS_EXCP_602:
1383 case PPC_FLAGS_EXCP_603:
1384 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1385 /* Swap temporary saved registers with GPRs */
1386 swap_gpr_tgpr(env);
1387 }
1388 break;
1389 default:
1390 break;
1391 }
1392#if defined (TARGET_PPC64)
1393 msr_sf = (value >> MSR_SF) & 1;
1394 msr_isf = (value >> MSR_ISF) & 1;
1395 msr_hv = (value >> MSR_HV) & 1;
1396#endif
1397 msr_ucle = (value >> MSR_UCLE) & 1;
1398 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
1399 msr_ap = (value >> MSR_AP) & 1;
1400 msr_sa = (value >> MSR_SA) & 1;
1401 msr_key = (value >> MSR_KEY) & 1;
1402 msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
1403 msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
1404 msr_ile = (value >> MSR_ILE) & 1;
1405 msr_ee = (value >> MSR_EE) & 1;
1406 msr_pr = (value >> MSR_PR) & 1;
1407 msr_fp = (value >> MSR_FP) & 1;
1408 msr_me = (value >> MSR_ME) & 1;
1409 msr_fe0 = (value >> MSR_FE0) & 1;
1410 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
1411 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
1412 msr_fe1 = (value >> MSR_FE1) & 1;
1413 msr_al = (value >> MSR_AL) & 1;
1414 msr_ip = (value >> MSR_IP) & 1;
1415 msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
1416 msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
1417 msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
1418 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
1419 msr_ri = (value >> MSR_RI) & 1;
1420 msr_le = (value >> MSR_LE) & 1;
3fc6c082 1421 do_compute_hflags(env);
50443c98
FB		 1422
1423 enter_pm = 0;
1424 switch (PPC_EXCP(env)) {
d9bce9d9
JM		 1425 case PPC_FLAGS_EXCP_603:
1426 /* Don't handle SLEEP mode: we should disable all clocks...
1427 * No dynamic power-management.
1428 */
1429 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1430 enter_pm = 1;
1431 break;
1432 case PPC_FLAGS_EXCP_604:
1433 if (msr_pow == 1)
1434 enter_pm = 1;
1435 break;
50443c98 1436 case PPC_FLAGS_EXCP_7x0:
76a66253 1437 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
50443c98
FB		 1438 enter_pm = 1;
1439 break;
1440 default:
1441 break;
1442 }
1443 if (enter_pm) {
e80e1cc4 1444 /* power save: exit cpu loop */
50443c98 1445 env->halted = 1;
e80e1cc4
FB		 1446 env->exception_index = EXCP_HLT;
1447 cpu_loop_exit();
1448 }
3fc6c082
FB		 1449}
1450
d9bce9d9 1451#if defined(TARGET_PPC64)
426613db 1452void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
d9bce9d9 1453{
426613db
JM		 1454 do_store_msr(env,
1455 (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
d9bce9d9
JM		 1456}
1457#endif
1458
76a66253 1459void do_compute_hflags (CPUPPCState *env)
3fc6c082 1460{
76a66253 1461 /* Compute current hflags */
c62db105
JM		 1462 env->hflags = (msr_cm << MSR_CM) | (msr_vr << MSR_VR) |
1463 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
1464 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
1465 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
76a66253 1466#if defined (TARGET_PPC64)
c62db105 1467 /* No care here: PowerPC 64 MSR_SF means the same as MSR_CM for BookE */
d9bce9d9 1468 env->hflags |= (msr_sf << (MSR_SF - 32)) | (msr_hv << (MSR_HV - 32));
4b3686fa 1469#endif
3fc6c082
FB		 1470}
1471
1472/*****************************************************************************/
1473/* Exception processing */
18fba28c 1474#if defined (CONFIG_USER_ONLY)
9a64fbe4 1475void do_interrupt (CPUState *env)
79aceca5 1476{
18fba28c
FB		 1477 env->exception_index = -1;
1478}
47103572 1479
e9df014c 1480void ppc_hw_interrupt (CPUState *env)
47103572
JM		 1481{
1482 env->exception_index = -1;
47103572 1483}
76a66253 1484#else /* defined (CONFIG_USER_ONLY) */
d094807b
FB		 1485static void dump_syscall(CPUState *env)
1486{
d9bce9d9 1487 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1b9eb036 1488 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
d094807b
FB		 1489 env->gpr[0], env->gpr[3], env->gpr[4],
1490 env->gpr[5], env->gpr[6], env->nip);
1491}
1492
18fba28c
FB		 1493void do_interrupt (CPUState *env)
1494{
c62db105
JM		 1495 target_ulong msr, *srr_0, *srr_1, *asrr_0, *asrr_1;
1496 int excp, idx;
79aceca5 1497
18fba28c 1498 excp = env->exception_index;
3fc6c082 1499 msr = do_load_msr(env);
2be0071f
FB		 1500 /* The default is to use SRR0 & SRR1 to save the exception context */
1501 srr_0 = &env->spr[SPR_SRR0];
1502 srr_1 = &env->spr[SPR_SRR1];
c62db105
JM		 1503 asrr_0 = NULL;
1504 asrr_1 = NULL;
9a64fbe4 1505#if defined (DEBUG_EXCEPTIONS)
2be0071f
FB		 1506 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
1507 if (loglevel != 0) {
1b9eb036
JM		 1508 fprintf(logfile,
1509 "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1510 env->nip, excp, env->error_code);
76a66253 1511 cpu_dump_state(env, logfile, fprintf, 0);
b769d8fe 1512 }
79aceca5 1513 }
9a64fbe4 1514#endif
b769d8fe 1515 if (loglevel & CPU_LOG_INT) {
1b9eb036
JM		 1516 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1517 env->nip, excp, env->error_code);
b769d8fe 1518 }
2be0071f 1519 msr_pow = 0;
c62db105 1520 idx = -1;
9a64fbe4
FB		 1521 /* Generate informations in save/restore registers */
1522 switch (excp) {
76a66253 1523 /* Generic PowerPC exceptions */
2be0071f 1524 case EXCP_RESET: /* 0x0100 */
c62db105
JM		 1525 switch (PPC_EXCP(env)) {
1526 case PPC_FLAGS_EXCP_40x:
1527 srr_0 = &env->spr[SPR_40x_SRR2];
1528 srr_1 = &env->spr[SPR_40x_SRR3];
1529 break;
1530 case PPC_FLAGS_EXCP_BOOKE:
1531 idx = 0;
1532 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1533 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1534 break;
1535 default:
2be0071f
FB		 1536 if (msr_ip)
1537 excp += 0xFFC00;
1538 excp |= 0xFFC00000;
c62db105 1539 break;
2be0071f 1540 }
9a64fbe4 1541 goto store_next;
2be0071f 1542 case EXCP_MACHINE_CHECK: /* 0x0200 */
c62db105
JM		 1543 switch (PPC_EXCP(env)) {
1544 case PPC_FLAGS_EXCP_40x:
2be0071f
FB		 1545 srr_0 = &env->spr[SPR_40x_SRR2];
1546 srr_1 = &env->spr[SPR_40x_SRR3];
c62db105
JM		 1547 break;
1548 case PPC_FLAGS_EXCP_BOOKE:
1549 idx = 1;
1550 srr_0 = &env->spr[SPR_BOOKE_MCSRR0];
1551 srr_1 = &env->spr[SPR_BOOKE_MCSRR1];
1552 asrr_0 = &env->spr[SPR_BOOKE_CSRR0];
1553 asrr_1 = &env->spr[SPR_BOOKE_CSRR1];
1554 msr_ce = 0;
1555 break;
1556 default:
1557 break;
2be0071f 1558 }
9a64fbe4
FB		 1559 msr_me = 0;
1560 break;
2be0071f 1561 case EXCP_DSI: /* 0x0300 */
9a64fbe4
FB		 1562 /* Store exception cause */
1563 /* data location address has been stored
1564 * when the fault has been detected
2be0071f 1565 */
c62db105 1566 idx = 2;
76a66253 1567 msr &= ~0xFFFF0000;
a541f297 1568#if defined (DEBUG_EXCEPTIONS)
4a057712 1569 if (loglevel != 0) {
1b9eb036
JM		 1570 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
1571 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
76a66253 1572 }
a541f297
FB		 1573#endif
1574 goto store_next;
2be0071f 1575 case EXCP_ISI: /* 0x0400 */
9a64fbe4 1576 /* Store exception cause */
c62db105 1577 idx = 3;
76a66253 1578 msr &= ~0xFFFF0000;
2be0071f 1579 msr |= env->error_code;
a541f297 1580#if defined (DEBUG_EXCEPTIONS)
76a66253 1581 if (loglevel != 0) {
1b9eb036
JM		 1582 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
1583 "\n", msr, env->nip);
76a66253 1584 }
a541f297 1585#endif
9a64fbe4 1586 goto store_next;
2be0071f 1587 case EXCP_EXTERNAL: /* 0x0500 */
c62db105 1588 idx = 4;
9a64fbe4 1589 goto store_next;
2be0071f 1590 case EXCP_ALIGN: /* 0x0600 */
76a66253 1591 if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
2be0071f 1592 /* Store exception cause */
c62db105 1593 idx = 5;
2be0071f
FB		 1594 /* Get rS/rD and rA from faulting opcode */
1595 env->spr[SPR_DSISR] |=
1596 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1597 /* data location address has been stored
1598 * when the fault has been detected
1599 */
1600 } else {
1601 /* IO error exception on PowerPC 601 */
1602 /* XXX: TODO */
1603 cpu_abort(env,
1604 "601 IO error exception is not implemented yet !\n");
1605 }
9a64fbe4 1606 goto store_current;
2be0071f 1607 case EXCP_PROGRAM: /* 0x0700 */
c62db105 1608 idx = 6;
9a64fbe4
FB		 1609 msr &= ~0xFFFF0000;
1610 switch (env->error_code & ~0xF) {
1611 case EXCP_FP:
1612 if (msr_fe0 == 0 && msr_fe1 == 0) {
1613#if defined (DEBUG_EXCEPTIONS)
4a057712 1614 if (loglevel != 0) {
a496775f
JM		 1615 fprintf(logfile, "Ignore floating point exception\n");
1616 }
9a64fbe4
FB		 1617#endif
1618 return;
76a66253 1619 }
9a64fbe4
FB		 1620 msr |= 0x00100000;
1621 /* Set FX */
1622 env->fpscr[7] |= 0x8;
1623 /* Finally, update FEX */
1624 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1625 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1626 env->fpscr[7] |= 0x4;
76a66253 1627 break;
9a64fbe4 1628 case EXCP_INVAL:
a496775f 1629#if defined (DEBUG_EXCEPTIONS)
4a057712 1630 if (loglevel != 0) {
a496775f
JM		 1631 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
1632 env->nip);
1633 }
1634#endif
9a64fbe4 1635 msr |= 0x00080000;
76a66253 1636 break;
9a64fbe4
FB		 1637 case EXCP_PRIV:
1638 msr |= 0x00040000;
76a66253 1639 break;
9a64fbe4 1640 case EXCP_TRAP:
c62db105 1641 idx = 15;
9a64fbe4
FB		 1642 msr |= 0x00020000;
1643 break;
1644 default:
1645 /* Should never occur */
76a66253
JM		 1646 break;
1647 }
9a64fbe4
FB		 1648 msr |= 0x00010000;
1649 goto store_current;
2be0071f 1650 case EXCP_NO_FP: /* 0x0800 */
c62db105 1651 idx = 7;
4ecc3190 1652 msr &= ~0xFFFF0000;
9a64fbe4
FB		 1653 goto store_current;
1654 case EXCP_DECR:
9a64fbe4 1655 goto store_next;
2be0071f 1656 case EXCP_SYSCALL: /* 0x0C00 */
c62db105 1657 idx = 8;
d094807b
FB		 1658 /* NOTE: this is a temporary hack to support graphics OSI
1659 calls from the MOL driver */
1660 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1661 env->osi_call) {
1662 if (env->osi_call(env) != 0)
1663 return;
1664 }
b769d8fe 1665 if (loglevel & CPU_LOG_INT) {
d094807b 1666 dump_syscall(env);
b769d8fe 1667 }
9a64fbe4 1668 goto store_next;
2be0071f 1669 case EXCP_TRACE: /* 0x0D00 */
2be0071f
FB		 1670 goto store_next;
1671 case EXCP_PERF: /* 0x0F00 */
1672 /* XXX: TODO */
1673 cpu_abort(env,
1674 "Performance counter exception is not implemented yet !\n");
1675 goto store_next;
1676 /* 32 bits PowerPC specific exceptions */
1677 case EXCP_FP_ASSIST: /* 0x0E00 */
1678 /* XXX: TODO */
1679 cpu_abort(env, "Floating point assist exception "
1680 "is not implemented yet !\n");
1681 goto store_next;
76a66253 1682 /* 64 bits PowerPC exceptions */
2be0071f
FB		 1683 case EXCP_DSEG: /* 0x0380 */
1684 /* XXX: TODO */
1685 cpu_abort(env, "Data segment exception is not implemented yet !\n");
9a64fbe4 1686 goto store_next;
2be0071f
FB		 1687 case EXCP_ISEG: /* 0x0480 */
1688 /* XXX: TODO */
1689 cpu_abort(env,
1690 "Instruction segment exception is not implemented yet !\n");
9a64fbe4 1691 goto store_next;
2be0071f 1692 case EXCP_HDECR: /* 0x0980 */
76a66253
JM		 1693 /* XXX: TODO */
1694 cpu_abort(env, "Hypervisor decrementer exception is not implemented "
1695 "yet !\n");
2be0071f
FB		 1696 goto store_next;
1697 /* Implementation specific exceptions */
1698 case 0x0A00:
76a66253
JM		 1699 if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
1700 env->spr[SPR_PVR] == CPU_PPC_G2LE)) {
2be0071f
FB		 1701 /* Critical interrupt on G2 */
1702 /* XXX: TODO */
1703 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1704 goto store_next;
1705 } else {
1706 cpu_abort(env, "Invalid exception 0x0A00 !\n");
1707 }
9a64fbe4 1708 return;
2be0071f 1709 case 0x0F20:
c62db105 1710 idx = 9;
2be0071f
FB		 1711 switch (PPC_EXCP(env)) {
1712 case PPC_FLAGS_EXCP_40x:
1713 /* APU unavailable on 405 */
1714 /* XXX: TODO */
1715 cpu_abort(env,
1716 "APU unavailable exception is not implemented yet !\n");
1717 goto store_next;
1718 case PPC_FLAGS_EXCP_74xx:
1719 /* Altivec unavailable */
1720 /* XXX: TODO */
1721 cpu_abort(env, "Altivec unavailable exception "
1722 "is not implemented yet !\n");
1723 goto store_next;
1724 default:
1725 cpu_abort(env, "Invalid exception 0x0F20 !\n");
1726 break;
1727 }
1728 return;
1729 case 0x1000:
c62db105 1730 idx = 10;
2be0071f
FB		 1731 switch (PPC_EXCP(env)) {
1732 case PPC_FLAGS_EXCP_40x:
1733 /* PIT on 4xx */
c62db105 1734 msr &= ~0xFFFF0000;
a496775f 1735#if defined (DEBUG_EXCEPTIONS)
c62db105
JM		 1736 if (loglevel != 0)
1737 fprintf(logfile, "PIT exception\n");
a496775f 1738#endif
2be0071f
FB		 1739 goto store_next;
1740 case PPC_FLAGS_EXCP_602:
1741 case PPC_FLAGS_EXCP_603:
1742 /* ITLBMISS on 602/603 */
2be0071f 1743 goto store_gprs;
76a66253
JM		 1744 case PPC_FLAGS_EXCP_7x5:
1745 /* ITLBMISS on 745/755 */
1746 goto tlb_miss;
2be0071f
FB		 1747 default:
1748 cpu_abort(env, "Invalid exception 0x1000 !\n");
1749 break;
1750 }
1751 return;
1752 case 0x1010:
c62db105 1753 idx = 11;
2be0071f
FB		 1754 switch (PPC_EXCP(env)) {
1755 case PPC_FLAGS_EXCP_40x:
1756 /* FIT on 4xx */
c62db105 1757 msr &= ~0xFFFF0000;
a496775f 1758#if defined (DEBUG_EXCEPTIONS)
c62db105
JM		 1759 if (loglevel != 0)
1760 fprintf(logfile, "FIT exception\n");
a496775f 1761#endif
2be0071f
FB		 1762 goto store_next;
1763 default:
1764 cpu_abort(env, "Invalid exception 0x1010 !\n");
1765 break;
1766 }
1767 return;
1768 case 0x1020:
c62db105 1769 idx = 12;
2be0071f
FB		 1770 switch (PPC_EXCP(env)) {
1771 case PPC_FLAGS_EXCP_40x:
1772 /* Watchdog on 4xx */
c62db105 1773 msr &= ~0xFFFF0000;
a496775f 1774#if defined (DEBUG_EXCEPTIONS)
c62db105
JM		 1775 if (loglevel != 0)
1776 fprintf(logfile, "WDT exception\n");
a496775f 1777#endif
2be0071f 1778 goto store_next;
c62db105
JM		 1779 case PPC_FLAGS_EXCP_BOOKE:
1780 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1781 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1782 break;
2be0071f
FB		 1783 default:
1784 cpu_abort(env, "Invalid exception 0x1020 !\n");
1785 break;
1786 }
1787 return;
1788 case 0x1100:
c62db105 1789 idx = 13;
2be0071f
FB		 1790 switch (PPC_EXCP(env)) {
1791 case PPC_FLAGS_EXCP_40x:
1792 /* DTLBMISS on 4xx */
a8dea12f 1793 msr &= ~0xFFFF0000;
2be0071f
FB		 1794 goto store_next;
1795 case PPC_FLAGS_EXCP_602:
1796 case PPC_FLAGS_EXCP_603:
1797 /* DLTLBMISS on 602/603 */
2be0071f 1798 goto store_gprs;
76a66253
JM		 1799 case PPC_FLAGS_EXCP_7x5:
1800 /* DLTLBMISS on 745/755 */
1801 goto tlb_miss;
2be0071f
FB		 1802 default:
1803 cpu_abort(env, "Invalid exception 0x1100 !\n");
1804 break;
1805 }
1806 return;
1807 case 0x1200:
c62db105 1808 idx = 14;
2be0071f
FB		 1809 switch (PPC_EXCP(env)) {
1810 case PPC_FLAGS_EXCP_40x:
1811 /* ITLBMISS on 4xx */
a8dea12f 1812 msr &= ~0xFFFF0000;
2be0071f
FB		 1813 goto store_next;
1814 case PPC_FLAGS_EXCP_602:
1815 case PPC_FLAGS_EXCP_603:
1816 /* DSTLBMISS on 602/603 */
2be0071f 1817 store_gprs:
76a66253
JM		 1818 /* Swap temporary saved registers with GPRs */
1819 swap_gpr_tgpr(env);
1820 msr_tgpr = 1;
2be0071f
FB		 1821#if defined (DEBUG_SOFTWARE_TLB)
1822 if (loglevel != 0) {
76a66253
JM		 1823 const unsigned char *es;
1824 target_ulong *miss, *cmp;
1825 int en;
1826 if (excp == 0x1000) {
1827 es = "I";
1828 en = 'I';
1829 miss = &env->spr[SPR_IMISS];
1830 cmp = &env->spr[SPR_ICMP];
1831 } else {
1832 if (excp == 0x1100)
1833 es = "DL";
1834 else
1835 es = "DS";
1836 en = 'D';
1837 miss = &env->spr[SPR_DMISS];
1838 cmp = &env->spr[SPR_DCMP];
1839 }
1b9eb036 1840 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
4a057712 1841 " H1 " ADDRX " H2 " ADDRX " %08x\n",
1b9eb036 1842 es, en, *miss, en, *cmp,
76a66253 1843 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2be0071f
FB		 1844 env->error_code);
1845 }
9a64fbe4 1846#endif
76a66253
JM		 1847 goto tlb_miss;
1848 case PPC_FLAGS_EXCP_7x5:
1849 /* DSTLBMISS on 745/755 */
1850 tlb_miss:
1851 msr &= ~0xF83F0000;
2be0071f
FB		 1852 msr |= env->crf[0] << 28;
1853 msr |= env->error_code; /* key, D/I, S/L bits */
1854 /* Set way using a LRU mechanism */
76a66253 1855 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2be0071f
FB		 1856 goto store_next;
1857 default:
1858 cpu_abort(env, "Invalid exception 0x1200 !\n");
1859 break;
1860 }
1861 return;
1862 case 0x1300:
1863 switch (PPC_EXCP(env)) {
1864 case PPC_FLAGS_EXCP_601:
1865 case PPC_FLAGS_EXCP_602:
1866 case PPC_FLAGS_EXCP_603:
1867 case PPC_FLAGS_EXCP_604:
1868 case PPC_FLAGS_EXCP_7x0:
1869 case PPC_FLAGS_EXCP_7x5:
1870 /* IABR on 6xx/7xx */
1871 /* XXX: TODO */
1872 cpu_abort(env, "IABR exception is not implemented yet !\n");
1873 goto store_next;
1874 default:
1875 cpu_abort(env, "Invalid exception 0x1300 !\n");
1876 break;
1877 }
1878 return;
1879 case 0x1400:
1880 switch (PPC_EXCP(env)) {
1881 case PPC_FLAGS_EXCP_601:
1882 case PPC_FLAGS_EXCP_602:
1883 case PPC_FLAGS_EXCP_603:
1884 case PPC_FLAGS_EXCP_604:
1885 case PPC_FLAGS_EXCP_7x0:
1886 case PPC_FLAGS_EXCP_7x5:
1887 /* SMI on 6xx/7xx */
1888 /* XXX: TODO */
1889 cpu_abort(env, "SMI exception is not implemented yet !\n");
1890 goto store_next;
1891 default:
1892 cpu_abort(env, "Invalid exception 0x1400 !\n");
1893 break;
1894 }
1895 return;
1896 case 0x1500:
1897 switch (PPC_EXCP(env)) {
1898 case PPC_FLAGS_EXCP_602:
1899 /* Watchdog on 602 */
76a66253 1900 /* XXX: TODO */
2be0071f
FB		 1901 cpu_abort(env,
1902 "602 watchdog exception is not implemented yet !\n");
1903 goto store_next;
1904 case PPC_FLAGS_EXCP_970:
1905 /* Soft patch exception on 970 */
1906 /* XXX: TODO */
1907 cpu_abort(env,
1908 "970 soft-patch exception is not implemented yet !\n");
1909 goto store_next;
1910 case PPC_FLAGS_EXCP_74xx:
1911 /* VPU assist on 74xx */
1912 /* XXX: TODO */
1913 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1914 goto store_next;
1915 default:
1916 cpu_abort(env, "Invalid exception 0x1500 !\n");
1917 break;
1918 }
1919 return;
1920 case 0x1600:
1921 switch (PPC_EXCP(env)) {
1922 case PPC_FLAGS_EXCP_602:
1923 /* Emulation trap on 602 */
1924 /* XXX: TODO */
1925 cpu_abort(env, "602 emulation trap exception "
1926 "is not implemented yet !\n");
1927 goto store_next;
1928 case PPC_FLAGS_EXCP_970:
1929 /* Maintenance exception on 970 */
1930 /* XXX: TODO */
1931 cpu_abort(env,
1932 "970 maintenance exception is not implemented yet !\n");
1933 goto store_next;
1934 default:
1935 cpu_abort(env, "Invalid exception 0x1600 !\n");
1936 break;
1937 }
1938 return;
1939 case 0x1700:
1940 switch (PPC_EXCP(env)) {
1941 case PPC_FLAGS_EXCP_7x0:
1942 case PPC_FLAGS_EXCP_7x5:
1943 /* Thermal management interrupt on G3 */
1944 /* XXX: TODO */
1945 cpu_abort(env, "G3 thermal management exception "
1946 "is not implemented yet !\n");
1947 goto store_next;
1948 case PPC_FLAGS_EXCP_970:
1949 /* VPU assist on 970 */
1950 /* XXX: TODO */
1951 cpu_abort(env,
1952 "970 VPU assist exception is not implemented yet !\n");
1953 goto store_next;
1954 default:
1955 cpu_abort(env, "Invalid exception 0x1700 !\n");
1956 break;
1957 }
1958 return;
1959 case 0x1800:
1960 switch (PPC_EXCP(env)) {
1961 case PPC_FLAGS_EXCP_970:
1962 /* Thermal exception on 970 */
1963 /* XXX: TODO */
1964 cpu_abort(env, "970 thermal management exception "
1965 "is not implemented yet !\n");
1966 goto store_next;
1967 default:
1968 cpu_abort(env, "Invalid exception 0x1800 !\n");
1969 break;
1970 }
1971 return;
1972 case 0x2000:
1973 switch (PPC_EXCP(env)) {
1974 case PPC_FLAGS_EXCP_40x:
1975 /* DEBUG on 4xx */
1976 /* XXX: TODO */
1977 cpu_abort(env, "40x debug exception is not implemented yet !\n");
1978 goto store_next;
1979 case PPC_FLAGS_EXCP_601:
1980 /* Run mode exception on 601 */
1981 /* XXX: TODO */
1982 cpu_abort(env,
1983 "601 run mode exception is not implemented yet !\n");
1984 goto store_next;
c62db105
JM		 1985 case PPC_FLAGS_EXCP_BOOKE:
1986 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1987 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1988 break;
2be0071f
FB		 1989 default:
1990 cpu_abort(env, "Invalid exception 0x1800 !\n");
1991 break;
1992 }
1993 return;
1994 /* Other exceptions */
1995 /* Qemu internal exceptions:
1996 * we should never come here with those values: abort execution
1997 */
1998 default:
1999 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
9a64fbe4
FB		 2000 return;
2001 store_current:
2be0071f 2002 /* save current instruction location */
c62db105 2003 *srr_0 = env->nip - 4;
9a64fbe4
FB		 2004 break;
2005 store_next:
2be0071f 2006 /* save next instruction location */
c62db105 2007 *srr_0 = env->nip;
9a64fbe4
FB		 2008 break;
2009 }
2be0071f
FB		 2010 /* Save msr */
2011 *srr_1 = msr;
c62db105
JM		 2012 if (asrr_0 != NULL)
2013 *asrr_0 = *srr_0;
2014 if (asrr_1 != NULL)
2015 *asrr_1 = *srr_1;
2be0071f
FB		 2016 /* If we disactivated any translation, flush TLBs */
2017 if (msr_ir || msr_dr) {
2018 tlb_flush(env, 1);
2019 }
9a64fbe4 2020 /* reload MSR with correct bits */
9a64fbe4
FB		 2021 msr_ee = 0;
2022 msr_pr = 0;
2023 msr_fp = 0;
2024 msr_fe0 = 0;
2025 msr_se = 0;
2026 msr_be = 0;
2027 msr_fe1 = 0;
2028 msr_ir = 0;
2029 msr_dr = 0;
2030 msr_ri = 0;
2031 msr_le = msr_ile;
c62db105
JM		 2032 if (PPC_EXCP(env) == PPC_FLAGS_EXCP_BOOKE) {
2033 msr_cm = msr_icm;
2034 if (idx == -1 || (idx >= 16 && idx < 32)) {
2035 cpu_abort(env, "Invalid exception index for excp %d %08x idx %d\n",
2036 excp, excp, idx);
2037 }
2038#if defined(TARGET_PPC64)
2039 if (msr_cm)
2040 env->nip = (uint64_t)env->spr[SPR_BOOKE_IVPR];
2041 else
2042#endif
2043 env->nip = (uint32_t)env->spr[SPR_BOOKE_IVPR];
2044 if (idx < 16)
2045 env->nip |= env->spr[SPR_BOOKE_IVOR0 + idx];
2046 else if (idx < 38)
2047 env->nip |= env->spr[SPR_BOOKE_IVOR32 + idx - 32];
2048 } else {
2049 msr_sf = msr_isf;
2050 env->nip = excp;
2051 }
3fc6c082 2052 do_compute_hflags(env);
9a64fbe4 2053 /* Jump to handler */
9a64fbe4 2054 env->exception_index = EXCP_NONE;
fb0eaffc 2055}
47103572 2056
e9df014c 2057void ppc_hw_interrupt (CPUPPCState *env)
47103572
JM		 2058{
2059 int raised = 0;
2060
a496775f
JM		 2061#if 1
2062 if (loglevel & CPU_LOG_INT) {
2063 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2064 __func__, env, env->pending_interrupts,
2065 env->interrupt_request, msr_me, msr_ee);
2066 }
47103572
JM		 2067#endif
2068 /* Raise it */
2069 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2070 /* External reset / critical input */
e9df014c
JM		 2071 /* XXX: critical input should be handled another way.
2072 * This code is not correct !
2073 */
47103572
JM		 2074 env->exception_index = EXCP_RESET;
2075 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2076 raised = 1;
2077 }
2078 if (raised == 0 && msr_me != 0) {
2079 /* Machine check exception */
2080 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2081 env->exception_index = EXCP_MACHINE_CHECK;
2082 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2083 raised = 1;
2084 }
2085 }
2086 if (raised == 0 && msr_ee != 0) {
2087#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2088 /* Hypervisor decrementer exception */
2089 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2090 env->exception_index = EXCP_HDECR;
2091 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2092 raised = 1;
2093 } else
2094#endif
2095 /* Decrementer exception */
2096 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2097 env->exception_index = EXCP_DECR;
2098 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2099 raised = 1;
2100 /* Programmable interval timer on embedded PowerPC */
2101 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2102 env->exception_index = EXCP_40x_PIT;
2103 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2104 raised = 1;
2105 /* Fixed interval timer on embedded PowerPC */
2106 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2107 env->exception_index = EXCP_40x_FIT;
2108 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2109 raised = 1;
2110 /* Watchdog timer on embedded PowerPC */
2111 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2112 env->exception_index = EXCP_40x_WATCHDOG;
2113 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2114 raised = 1;
2115 /* External interrupt */
2116 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2117 env->exception_index = EXCP_EXTERNAL;
e9df014c
JM		 2118 /* Taking an external interrupt does not clear the external
2119 * interrupt status
2120 */
2121#if 0
47103572 2122 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
e9df014c 2123#endif
47103572 2124 raised = 1;
d0dfae6e
JM		 2125#if 0 // TODO
2126 /* Thermal interrupt */
2127 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2128 env->exception_index = EXCP_970_THRM;
2129 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2130 raised = 1;
2131#endif
47103572
JM		 2132 }
2133#if 0 // TODO
2134 /* External debug exception */
2135 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2136 env->exception_index = EXCP_xxx;
2137 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2138 raised = 1;
2139#endif
2140 }
2141 if (raised != 0) {
2142 env->error_code = 0;
2143 do_interrupt(env);
2144 }
47103572 2145}
18fba28c 2146#endif /* !CONFIG_USER_ONLY */
a496775f
JM		 2147
2148void cpu_dump_EA (target_ulong EA)
2149{
2150 FILE *f;
2151
2152 if (logfile) {
2153 f = logfile;
2154 } else {
2155 f = stdout;
2156 return;
2157 }
4a057712
JM		 2158 fprintf(f, "Memory access at address " ADDRX "\n", EA);
2159}
2160
2161void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2162{
2163 FILE *f;
2164
2165 if (logfile) {
2166 f = logfile;
2167 } else {
2168 f = stdout;
2169 return;
2170 }
2171 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2172 RA, msr);
a496775f
JM		 2173}
2174
0a032cbe
JM		 2175void cpu_ppc_reset (void *opaque)
2176{
2177 CPUPPCState *env;
2178
2179 env = opaque;
2180#if defined (DO_SINGLE_STEP) && 0
2181 /* Single step trace mode */
2182 msr_se = 1;
2183 msr_be = 1;
2184#endif
2185 msr_fp = 1; /* Allow floating point exceptions */
2186 msr_me = 1; /* Allow machine check exceptions */
2187#if defined(TARGET_PPC64)
2188 msr_sf = 0; /* Boot in 32 bits mode */
2189 msr_cm = 0;
2190#endif
2191#if defined(CONFIG_USER_ONLY)
2192 msr_pr = 1;
2193 tlb_flush(env, 1);
2194#else
2195 env->nip = 0xFFFFFFFC;
2196 ppc_tlb_invalidate_all(env);
2197#endif
2198 do_compute_hflags(env);
2199 env->reserve = -1;
2200}
2201
2202CPUPPCState *cpu_ppc_init (void)
2203{
2204 CPUPPCState *env;
2205
2206 env = qemu_mallocz(sizeof(CPUPPCState));
2207 if (!env)
2208 return NULL;
2209 cpu_exec_init(env);
2210 cpu_ppc_reset(env);
2211
2212 return env;
2213}
2214
2215void cpu_ppc_close (CPUPPCState *env)
2216{
2217 /* Should also remove all opcode tables... */
2218 free(env);
2219}
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