]> git.proxmox.com Git - mirror_qemu.git/blame - target-ppc/helper.c
PREP and heathrow machines only support PowerPC CPU with a 6xx bus.
[mirror_qemu.git] / target-ppc / helper.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
79aceca5 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
fdabc366
FB
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
27
28#include "cpu.h"
29#include "exec-all.h"
9a64fbe4
FB
30
31//#define DEBUG_MMU
32//#define DEBUG_BATS
76a66253 33//#define DEBUG_SOFTWARE_TLB
9a64fbe4 34//#define DEBUG_EXCEPTIONS
fdabc366 35//#define FLUSH_ALL_TLBS
9a64fbe4 36
9a64fbe4 37/*****************************************************************************/
3fc6c082 38/* PowerPC MMU emulation */
a541f297 39
d9bce9d9 40#if defined(CONFIG_USER_ONLY)
e96efcfc 41int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
24741ef3
FB
42 int is_user, int is_softmmu)
43{
44 int exception, error_code;
d9bce9d9 45
24741ef3
FB
46 if (rw == 2) {
47 exception = EXCP_ISI;
48 error_code = 0;
49 } else {
50 exception = EXCP_DSI;
51 error_code = 0;
52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
76a66253 59
24741ef3
FB
60 return 1;
61}
76a66253 62
9b3c35e0 63target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
24741ef3
FB
64{
65 return addr;
66}
67#else
76a66253
JM
68/* Common routines used by software and hardware TLBs emulation */
69static inline int pte_is_valid (target_ulong pte0)
70{
71 return pte0 & 0x80000000 ? 1 : 0;
72}
73
74static inline void pte_invalidate (target_ulong *pte0)
75{
76 *pte0 &= ~0x80000000;
77}
78
79#define PTE_PTEM_MASK 0x7FFFFFBF
80#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
81
82static int pte_check (mmu_ctx_t *ctx,
83 target_ulong pte0, target_ulong pte1, int h, int rw)
84{
85 int access, ret;
86
87 access = 0;
88 ret = -1;
89 /* Check validity and table match */
90 if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) {
91 /* Check vsid & api */
92 if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {
93 if (ctx->raddr != (target_ulong)-1) {
94 /* all matches should have equal RPN, WIMG & PP */
95 if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
96 if (loglevel > 0)
97 fprintf(logfile, "Bad RPN/WIMG/PP\n");
98 return -3;
99 }
100 }
101 /* Compute access rights */
102 if (ctx->key == 0) {
103 access = PAGE_READ;
104 if ((pte1 & 0x00000003) != 0x3)
105 access |= PAGE_WRITE;
106 } else {
107 switch (pte1 & 0x00000003) {
108 case 0x0:
109 access = 0;
110 break;
111 case 0x1:
112 case 0x3:
113 access = PAGE_READ;
114 break;
115 case 0x2:
116 access = PAGE_READ | PAGE_WRITE;
117 break;
118 }
119 }
120 /* Keep the matching PTE informations */
121 ctx->raddr = pte1;
122 ctx->prot = access;
123 if ((rw == 0 && (access & PAGE_READ)) ||
124 (rw == 1 && (access & PAGE_WRITE))) {
125 /* Access granted */
126#if defined (DEBUG_MMU)
127 if (loglevel > 0)
128 fprintf(logfile, "PTE access granted !\n");
129#endif
130 ret = 0;
131 } else {
132 /* Access right violation */
133#if defined (DEBUG_MMU)
134 if (loglevel > 0)
135 fprintf(logfile, "PTE access rejected\n");
136#endif
137 ret = -2;
138 }
139 }
140 }
141
142 return ret;
143}
144
145static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
146 int ret, int rw)
147{
148 int store = 0;
149
150 /* Update page flags */
151 if (!(*pte1p & 0x00000100)) {
152 /* Update accessed flag */
153 *pte1p |= 0x00000100;
154 store = 1;
155 }
156 if (!(*pte1p & 0x00000080)) {
157 if (rw == 1 && ret == 0) {
158 /* Update changed flag */
159 *pte1p |= 0x00000080;
160 store = 1;
161 } else {
162 /* Force page fault for first write access */
163 ctx->prot &= ~PAGE_WRITE;
164 }
165 }
166
167 return store;
168}
169
170/* Software driven TLB helpers */
171static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
172 int way, int is_code)
173{
174 int nr;
175
176 /* Select TLB num in a way from address */
177 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
178 /* Select TLB way */
179 nr += env->tlb_per_way * way;
180 /* 6xx have separate TLBs for instructions and data */
181 if (is_code && env->id_tlbs == 1)
182 nr += env->nb_tlb;
183
184 return nr;
185}
186
187void ppc6xx_tlb_invalidate_all (CPUState *env)
188{
1d0a48fb 189 ppc6xx_tlb_t *tlb;
76a66253
JM
190 int nr, max;
191
192#if defined (DEBUG_SOFTWARE_TLB) && 0
193 if (loglevel != 0) {
194 fprintf(logfile, "Invalidate all TLBs\n");
195 }
196#endif
197 /* Invalidate all defined software TLB */
198 max = env->nb_tlb;
199 if (env->id_tlbs == 1)
200 max *= 2;
201 for (nr = 0; nr < max; nr++) {
1d0a48fb 202 tlb = &env->tlb[nr].tlb6;
76a66253
JM
203#if !defined(FLUSH_ALL_TLBS)
204 tlb_flush_page(env, tlb->EPN);
205#endif
206 pte_invalidate(&tlb->pte0);
207 }
208#if defined(FLUSH_ALL_TLBS)
209 tlb_flush(env, 1);
210#endif
211}
212
213static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
214 target_ulong eaddr,
215 int is_code, int match_epn)
216{
1d0a48fb 217 ppc6xx_tlb_t *tlb;
76a66253
JM
218 int way, nr;
219
220#if !defined(FLUSH_ALL_TLBS)
221 /* Invalidate ITLB + DTLB, all ways */
222 for (way = 0; way < env->nb_ways; way++) {
223 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
1d0a48fb 224 tlb = &env->tlb[nr].tlb6;
76a66253
JM
225 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
226#if defined (DEBUG_SOFTWARE_TLB)
227 if (loglevel != 0) {
1b9eb036 228 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
76a66253
JM
229 nr, env->nb_tlb, eaddr);
230 }
231#endif
232 pte_invalidate(&tlb->pte0);
233 tlb_flush_page(env, tlb->EPN);
234 }
235 }
236#else
237 /* XXX: PowerPC specification say this is valid as well */
238 ppc6xx_tlb_invalidate_all(env);
239#endif
240}
241
242void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
243 int is_code)
244{
245 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
246}
247
248void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
249 target_ulong pte0, target_ulong pte1)
250{
1d0a48fb 251 ppc6xx_tlb_t *tlb;
76a66253
JM
252 int nr;
253
254 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
1d0a48fb 255 tlb = &env->tlb[nr].tlb6;
76a66253
JM
256#if defined (DEBUG_SOFTWARE_TLB)
257 if (loglevel != 0) {
1b9eb036
JM
258 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
259 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
76a66253
JM
260 }
261#endif
262 /* Invalidate any pending reference in Qemu for this virtual address */
263 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
264 tlb->pte0 = pte0;
265 tlb->pte1 = pte1;
266 tlb->EPN = EPN;
76a66253
JM
267 /* Store last way for LRU mechanism */
268 env->last_way = way;
269}
270
271static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
272 target_ulong eaddr, int rw, int access_type)
273{
1d0a48fb 274 ppc6xx_tlb_t *tlb;
76a66253
JM
275 int nr, best, way;
276 int ret;
d9bce9d9 277
76a66253
JM
278 best = -1;
279 ret = -1; /* No TLB found */
280 for (way = 0; way < env->nb_ways; way++) {
281 nr = ppc6xx_tlb_getnum(env, eaddr, way,
282 access_type == ACCESS_CODE ? 1 : 0);
1d0a48fb 283 tlb = &env->tlb[nr].tlb6;
76a66253
JM
284 /* This test "emulates" the PTE index match for hardware TLBs */
285 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
286#if defined (DEBUG_SOFTWARE_TLB)
287 if (loglevel != 0) {
1b9eb036
JM
288 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
289 "] <> " ADDRX "\n",
76a66253
JM
290 nr, env->nb_tlb,
291 pte_is_valid(tlb->pte0) ? "valid" : "inval",
292 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
293 }
294#endif
295 continue;
296 }
297#if defined (DEBUG_SOFTWARE_TLB)
298 if (loglevel != 0) {
1b9eb036
JM
299 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
300 " %c %c\n",
76a66253
JM
301 nr, env->nb_tlb,
302 pte_is_valid(tlb->pte0) ? "valid" : "inval",
303 tlb->EPN, eaddr, tlb->pte1,
304 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
305 }
306#endif
307 switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
308 case -3:
309 /* TLB inconsistency */
310 return -1;
311 case -2:
312 /* Access violation */
313 ret = -2;
314 best = nr;
315 break;
316 case -1:
317 default:
318 /* No match */
319 break;
320 case 0:
321 /* access granted */
322 /* XXX: we should go on looping to check all TLBs consistency
323 * but we can speed-up the whole thing as the
324 * result would be undefined if TLBs are not consistent.
325 */
326 ret = 0;
327 best = nr;
328 goto done;
329 }
330 }
331 if (best != -1) {
332 done:
333#if defined (DEBUG_SOFTWARE_TLB)
334 if (loglevel > 0) {
335 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
336 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
337 }
338#endif
339 /* Update page flags */
1d0a48fb 340 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
76a66253
JM
341 }
342
343 return ret;
344}
345
9a64fbe4 346/* Perform BAT hit & translation */
76a66253
JM
347static int get_bat (CPUState *env, mmu_ctx_t *ctx,
348 target_ulong virtual, int rw, int type)
9a64fbe4 349{
76a66253
JM
350 target_ulong *BATlt, *BATut, *BATu, *BATl;
351 target_ulong base, BEPIl, BEPIu, bl;
9a64fbe4
FB
352 int i;
353 int ret = -1;
354
355#if defined (DEBUG_BATS)
356 if (loglevel > 0) {
1b9eb036 357 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 358 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 359 }
9a64fbe4
FB
360#endif
361 switch (type) {
362 case ACCESS_CODE:
363 BATlt = env->IBAT[1];
364 BATut = env->IBAT[0];
365 break;
366 default:
367 BATlt = env->DBAT[1];
368 BATut = env->DBAT[0];
369 break;
370 }
371#if defined (DEBUG_BATS)
372 if (loglevel > 0) {
1b9eb036 373 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 374 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 375 }
9a64fbe4
FB
376#endif
377 base = virtual & 0xFFFC0000;
378 for (i = 0; i < 4; i++) {
379 BATu = &BATut[i];
380 BATl = &BATlt[i];
381 BEPIu = *BATu & 0xF0000000;
382 BEPIl = *BATu & 0x0FFE0000;
383 bl = (*BATu & 0x00001FFC) << 15;
384#if defined (DEBUG_BATS)
385 if (loglevel > 0) {
1b9eb036
JM
386 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
387 " BATl 0x" ADDRX "\n",
9a64fbe4
FB
388 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
389 *BATu, *BATl);
9a64fbe4
FB
390 }
391#endif
392 if ((virtual & 0xF0000000) == BEPIu &&
393 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
394 /* BAT matches */
395 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
396 (msr_pr == 1 && (*BATu & 0x00000001))) {
397 /* Get physical address */
76a66253 398 ctx->raddr = (*BATl & 0xF0000000) |
9a64fbe4 399 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
a541f297 400 (virtual & 0x0001F000);
9a64fbe4 401 if (*BATl & 0x00000001)
76a66253 402 ctx->prot = PAGE_READ;
9a64fbe4 403 if (*BATl & 0x00000002)
76a66253 404 ctx->prot = PAGE_WRITE | PAGE_READ;
9a64fbe4
FB
405#if defined (DEBUG_BATS)
406 if (loglevel > 0) {
1b9eb036
JM
407 fprintf(logfile, "BAT %d match: r 0x" ADDRX
408 " prot=%c%c\n",
76a66253
JM
409 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
410 ctx->prot & PAGE_WRITE ? 'W' : '-');
9a64fbe4
FB
411 }
412#endif
413 ret = 0;
414 break;
415 }
416 }
417 }
418 if (ret < 0) {
419#if defined (DEBUG_BATS)
1b9eb036 420 printf("no BAT match for 0x" ADDRX ":\n", virtual);
9a64fbe4
FB
421 for (i = 0; i < 4; i++) {
422 BATu = &BATut[i];
423 BATl = &BATlt[i];
424 BEPIu = *BATu & 0xF0000000;
425 BEPIl = *BATu & 0x0FFE0000;
426 bl = (*BATu & 0x00001FFC) << 15;
1b9eb036
JM
427 printf("%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
428 " BATl 0x" ADDRX " \n\t"
429 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
9a64fbe4
FB
430 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
431 *BATu, *BATl, BEPIu, BEPIl, bl);
432 }
433#endif
9a64fbe4
FB
434 }
435 /* No hit */
436 return ret;
437}
438
439/* PTE table lookup */
76a66253 440static int find_pte (mmu_ctx_t *ctx, int h, int rw)
9a64fbe4 441{
76a66253
JM
442 target_ulong base, pte0, pte1;
443 int i, good = -1;
444 int ret;
9a64fbe4 445
76a66253
JM
446 ret = -1; /* No entry found */
447 base = ctx->pg_addr[h];
9a64fbe4 448 for (i = 0; i < 8; i++) {
8df1cd07
FB
449 pte0 = ldl_phys(base + (i * 8));
450 pte1 = ldl_phys(base + (i * 8) + 4);
9a64fbe4 451#if defined (DEBUG_MMU)
d094807b 452 if (loglevel > 0) {
1b9eb036
JM
453 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
454 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
455 base + (i * 8), pte0, pte1,
76a66253
JM
456 pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem);
457 }
9a64fbe4 458#endif
76a66253
JM
459 switch (pte_check(ctx, pte0, pte1, h, rw)) {
460 case -3:
461 /* PTE inconsistency */
462 return -1;
463 case -2:
464 /* Access violation */
465 ret = -2;
466 good = i;
467 break;
468 case -1:
469 default:
470 /* No PTE match */
471 break;
472 case 0:
473 /* access granted */
474 /* XXX: we should go on looping to check all PTEs consistency
475 * but if we can speed-up the whole thing as the
476 * result would be undefined if PTEs are not consistent.
477 */
478 ret = 0;
479 good = i;
480 goto done;
9a64fbe4
FB
481 }
482 }
483 if (good != -1) {
76a66253 484 done:
9a64fbe4 485#if defined (DEBUG_MMU)
d094807b 486 if (loglevel > 0) {
1b9eb036
JM
487 fprintf(logfile, "found PTE at addr 0x" ADDRX " prot=0x%01x "
488 "ret=%d\n",
76a66253
JM
489 ctx->raddr, ctx->prot, ret);
490 }
9a64fbe4
FB
491#endif
492 /* Update page flags */
76a66253
JM
493 pte1 = ctx->raddr;
494 if (pte_update_flags(ctx, &pte1, ret, rw) == 1)
495 stl_phys_notdirty(base + (good * 8) + 4, pte1);
9a64fbe4
FB
496 }
497
498 return ret;
79aceca5
FB
499}
500
76a66253
JM
501static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
502 target_phys_addr_t hash,
503 target_phys_addr_t mask)
79aceca5 504{
9a64fbe4 505 return (sdr1 & 0xFFFF0000) | (hash & mask);
79aceca5
FB
506}
507
9a64fbe4 508/* Perform segment based translation */
76a66253
JM
509static int get_segment (CPUState *env, mmu_ctx_t *ctx,
510 target_ulong eaddr, int rw, int type)
79aceca5 511{
76a66253
JM
512 target_phys_addr_t sdr, hash, mask;
513 target_ulong sr, vsid, pgidx;
9a64fbe4 514 int ret = -1, ret2;
79aceca5 515
76a66253 516 sr = env->sr[eaddr >> 28];
9a64fbe4 517#if defined (DEBUG_MMU)
a541f297 518 if (loglevel > 0) {
1b9eb036
JM
519 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x"
520 ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
76a66253
JM
521 eaddr, eaddr >> 28, sr, env->nip,
522 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
a541f297 523 }
9a64fbe4 524#endif
76a66253
JM
525 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
526 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
9a64fbe4
FB
527 if ((sr & 0x80000000) == 0) {
528#if defined (DEBUG_MMU)
76a66253 529 if (loglevel > 0)
1b9eb036 530 fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
76a66253 531 ctx->key, sr & 0x10000000);
9a64fbe4
FB
532#endif
533 /* Check if instruction fetch is allowed, if needed */
534 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
535 /* Page address translation */
76a66253 536 pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;
9a64fbe4 537 vsid = sr & 0x00FFFFFF;
a541f297 538 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
76a66253
JM
539 /* Primary table address */
540 sdr = env->sdr1;
9a64fbe4 541 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
76a66253
JM
542 ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);
543 /* Secondary table address */
544 hash = (~hash) & 0x01FFFFC0;
545 ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);
546 ctx->ptem = (vsid << 7) | (pgidx >> 10);
547 /* Initialize real address with an invalid value */
548 ctx->raddr = (target_ulong)-1;
549 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
550 /* Software TLB search */
551 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
76a66253 552 } else {
9a64fbe4 553#if defined (DEBUG_MMU)
76a66253 554 if (loglevel > 0) {
1b9eb036
JM
555 fprintf(logfile, "0 sdr1=0x" ADDRX " vsid=0x%06x "
556 "api=0x%04x hash=0x%07x pg_addr=0x" ADDRX "\n",
557 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
76a66253 558 }
9a64fbe4 559#endif
76a66253
JM
560 /* Primary table lookup */
561 ret = find_pte(ctx, 0, rw);
562 if (ret < 0) {
563 /* Secondary table lookup */
9a64fbe4 564#if defined (DEBUG_MMU)
76a66253
JM
565 if (eaddr != 0xEFFFFFFF && loglevel > 0) {
566 fprintf(logfile,
1b9eb036
JM
567 "1 sdr1=0x" ADDRX " vsid=0x%06x api=0x%04x "
568 "hash=0x%05x pg_addr=0x" ADDRX "\n",
569 sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
76a66253 570 }
9a64fbe4 571#endif
76a66253
JM
572 ret2 = find_pte(ctx, 1, rw);
573 if (ret2 != -1)
574 ret = ret2;
575 }
9a64fbe4 576 }
9a64fbe4
FB
577 } else {
578#if defined (DEBUG_MMU)
76a66253
JM
579 if (loglevel > 0)
580 fprintf(logfile, "No access allowed\n");
9a64fbe4 581#endif
76a66253 582 ret = -3;
9a64fbe4
FB
583 }
584 } else {
585#if defined (DEBUG_MMU)
a541f297 586 if (loglevel > 0)
76a66253 587 fprintf(logfile, "direct store...\n");
9a64fbe4
FB
588#endif
589 /* Direct-store segment : absolutely *BUGGY* for now */
590 switch (type) {
591 case ACCESS_INT:
592 /* Integer load/store : only access allowed */
593 break;
594 case ACCESS_CODE:
595 /* No code fetch is allowed in direct-store areas */
596 return -4;
597 case ACCESS_FLOAT:
598 /* Floating point load/store */
599 return -4;
600 case ACCESS_RES:
601 /* lwarx, ldarx or srwcx. */
602 return -4;
603 case ACCESS_CACHE:
604 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
605 /* Should make the instruction do no-op.
606 * As it already do no-op, it's quite easy :-)
607 */
76a66253 608 ctx->raddr = eaddr;
9a64fbe4
FB
609 return 0;
610 case ACCESS_EXT:
611 /* eciwx or ecowx */
612 return -4;
613 default:
614 if (logfile) {
615 fprintf(logfile, "ERROR: instruction should not need "
616 "address translation\n");
617 }
618 printf("ERROR: instruction should not need "
619 "address translation\n");
620 return -4;
621 }
76a66253
JM
622 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
623 ctx->raddr = eaddr;
9a64fbe4
FB
624 ret = 2;
625 } else {
626 ret = -2;
627 }
79aceca5 628 }
9a64fbe4
FB
629
630 return ret;
79aceca5
FB
631}
632
a8dea12f 633int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
e96efcfc 634 target_ulong address, int rw, int access_type)
a8dea12f
JM
635{
636 ppcemb_tlb_t *tlb;
637 target_phys_addr_t raddr;
638 target_ulong mask;
639 int i, ret, zsel, zpr;
640
641 ret = -6;
642 for (i = 0; i < env->nb_tlb; i++) {
643 tlb = &env->tlb[i].tlbe;
644 /* Check valid flag */
645 if (!(tlb->prot & PAGE_VALID)) {
646 if (loglevel)
647 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
648 continue;
649 }
650 mask = ~(tlb->size - 1);
651 if (loglevel) {
a496775f
JM
652 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
653 ADDRX " " ADDRX " %d\n",
654 __func__, i, address, (int)env->spr[SPR_40x_PID],
655 tlb->EPN, mask, (int)tlb->PID);
a8dea12f
JM
656 }
657 /* Check PID */
658 if (tlb->PID != 0 && tlb->PID != env->spr[SPR_40x_PID])
659 continue;
660 /* Check effective address */
661 if ((address & mask) != tlb->EPN)
662 continue;
663 raddr = (tlb->RPN & mask) | (address & ~mask);
664 zsel = (tlb->attr >> 4) & 0xF;
665 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
666 if (loglevel) {
667 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
668 __func__, i, zsel, zpr, rw, tlb->attr);
669 }
670 if (access_type == ACCESS_CODE) {
671 /* Check execute enable bit */
672 switch (zpr) {
673 case 0x0:
674 if (msr_pr) {
675 ret = -3;
676 ctx->prot = 0;
677 break;
678 }
679 /* No break here */
680 case 0x1:
681 case 0x2:
682 /* Check from TLB entry */
683 if (!(tlb->prot & PAGE_EXEC)) {
684 ret = -3;
685 } else {
686 if (tlb->prot & PAGE_WRITE)
687 ctx->prot = PAGE_READ | PAGE_WRITE;
688 else
689 ctx->prot = PAGE_READ;
690 ret = 0;
691 }
692 break;
693 case 0x3:
694 /* All accesses granted */
695 ret = 0;
696 ctx->prot = PAGE_READ | PAGE_WRITE;
697 break;
698 }
699 } else {
700 switch (zpr) {
701 case 0x0:
702 if (msr_pr) {
703 ret = -2;
704 ctx->prot = 0;
705 break;
706 }
707 /* No break here */
708 case 0x1:
709 case 0x2:
710 /* Check from TLB entry */
711 /* Check write protection bit */
712 if (rw && !(tlb->prot & PAGE_WRITE)) {
713 ret = -2;
714 } else {
715 ret = 2;
716 if (tlb->prot & PAGE_WRITE)
717 ctx->prot = PAGE_READ | PAGE_WRITE;
718 else
719 ctx->prot = PAGE_READ;
720 }
721 break;
722 case 0x3:
723 /* All accesses granted */
724 ret = 2;
725 ctx->prot = PAGE_READ | PAGE_WRITE;
726 break;
727 }
728 }
729 if (ret >= 0) {
730 ctx->raddr = raddr;
731 if (loglevel) {
732 fprintf(logfile, "%s: access granted " ADDRX " => " REGX
733 " %d\n", __func__, address, ctx->raddr, ctx->prot);
734 }
735 return i;
736 }
737 }
738
739 return ret;
740}
741
76a66253
JM
742static int check_physical (CPUState *env, mmu_ctx_t *ctx,
743 target_ulong eaddr, int rw)
744{
745 int in_plb, ret;
746
747 ctx->raddr = eaddr;
748 ctx->prot = PAGE_READ;
749 ret = 0;
750 if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) {
751 /* 403 family add some particular protections,
752 * using PBL/PBU registers for accesses with no translation.
753 */
754 in_plb =
755 /* Check PLB validity */
756 (env->pb[0] < env->pb[1] &&
757 /* and address in plb area */
758 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
759 (env->pb[2] < env->pb[3] &&
760 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
761 if (in_plb ^ msr_px) {
762 /* Access in protected area */
763 if (rw == 1) {
764 /* Access is not allowed */
765 ret = -2;
766 }
767 } else {
768 /* Read-write access is allowed */
769 ctx->prot |= PAGE_WRITE;
770 }
771 } else {
772 ctx->prot |= PAGE_WRITE;
773 }
774
775 return ret;
776}
777
778int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
779 int rw, int access_type, int check_BATs)
9a64fbe4
FB
780{
781 int ret;
514fb8c1 782#if 0
9a64fbe4
FB
783 if (loglevel > 0) {
784 fprintf(logfile, "%s\n", __func__);
785 }
d9bce9d9 786#endif
4b3686fa
FB
787 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
788 (access_type != ACCESS_CODE && msr_dr == 0)) {
9a64fbe4 789 /* No address translation */
76a66253 790 ret = check_physical(env, ctx, eaddr, rw);
9a64fbe4 791 } else {
a8dea12f
JM
792 switch (PPC_MMU(env)) {
793 case PPC_FLAGS_MMU_32B:
794 case PPC_FLAGS_MMU_SOFT_6xx:
795 /* Try to find a BAT */
796 ret = -1;
797 if (check_BATs)
798 ret = get_bat(env, ctx, eaddr, rw, access_type);
799 if (ret < 0) {
800 /* We didn't match any BAT entry */
801 ret = get_segment(env, ctx, eaddr, rw, access_type);
802 }
803 break;
804 case PPC_FLAGS_MMU_SOFT_4xx:
805 ret = mmu4xx_get_physical_address(env, ctx, eaddr,
806 rw, access_type);
807 break;
808 default:
809 /* XXX: TODO */
810 cpu_abort(env, "MMU model not implemented\n");
811 return -1;
9a64fbe4
FB
812 }
813 }
514fb8c1 814#if 0
a541f297 815 if (loglevel > 0) {
1b9eb036 816 fprintf(logfile, "%s address " ADDRX " => " ADDRX "\n",
76a66253 817 __func__, eaddr, ctx->raddr);
a541f297 818 }
76a66253 819#endif
d9bce9d9 820
9a64fbe4
FB
821 return ret;
822}
823
9b3c35e0 824target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
a6b025d3 825{
76a66253 826 mmu_ctx_t ctx;
a6b025d3 827
76a66253 828 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
a6b025d3 829 return -1;
76a66253
JM
830
831 return ctx.raddr & TARGET_PAGE_MASK;
a6b025d3 832}
9a64fbe4 833
9a64fbe4 834/* Perform address translation */
e96efcfc 835int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
a541f297 836 int is_user, int is_softmmu)
9a64fbe4 837{
76a66253 838 mmu_ctx_t ctx;
9a64fbe4 839 int exception = 0, error_code = 0;
a541f297 840 int access_type;
9a64fbe4 841 int ret = 0;
d9bce9d9 842
b769d8fe
FB
843 if (rw == 2) {
844 /* code access */
845 rw = 0;
846 access_type = ACCESS_CODE;
847 } else {
848 /* data access */
849 /* XXX: put correct access by using cpu_restore_state()
850 correctly */
851 access_type = ACCESS_INT;
852 // access_type = env->access_type;
853 }
76a66253 854 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
9a64fbe4 855 if (ret == 0) {
76a66253
JM
856 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
857 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
858 is_user, is_softmmu);
9a64fbe4 859 } else if (ret < 0) {
9a64fbe4 860#if defined (DEBUG_MMU)
76a66253
JM
861 if (loglevel > 0)
862 cpu_dump_state(env, logfile, fprintf, 0);
9a64fbe4
FB
863#endif
864 if (access_type == ACCESS_CODE) {
865 exception = EXCP_ISI;
866 switch (ret) {
867 case -1:
76a66253
JM
868 /* No matches in page tables or TLB */
869 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
870 exception = EXCP_I_TLBMISS;
871 env->spr[SPR_IMISS] = address;
872 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
873 error_code = 1 << 18;
874 goto tlb_miss;
875 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
a8dea12f
JM
876 exception = EXCP_40x_ITLBMISS;
877 error_code = 0;
878 env->spr[SPR_40x_DEAR] = address;
879 env->spr[SPR_40x_ESR] = 0x00000000;
76a66253
JM
880 } else {
881 error_code = 0x40000000;
882 }
9a64fbe4
FB
883 break;
884 case -2:
885 /* Access rights violation */
2be0071f 886 error_code = 0x08000000;
9a64fbe4
FB
887 break;
888 case -3:
76a66253 889 /* No execute protection violation */
2be0071f 890 error_code = 0x10000000;
9a64fbe4
FB
891 break;
892 case -4:
893 /* Direct store exception */
894 /* No code fetch is allowed in direct-store areas */
2be0071f
FB
895 error_code = 0x10000000;
896 break;
897 case -5:
898 /* No match in segment table */
899 exception = EXCP_ISEG;
900 error_code = 0;
9a64fbe4
FB
901 break;
902 }
903 } else {
904 exception = EXCP_DSI;
905 switch (ret) {
906 case -1:
76a66253
JM
907 /* No matches in page tables or TLB */
908 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
909 if (rw == 1) {
910 exception = EXCP_DS_TLBMISS;
911 error_code = 1 << 16;
912 } else {
913 exception = EXCP_DL_TLBMISS;
914 error_code = 0;
915 }
916 env->spr[SPR_DMISS] = address;
917 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
918 tlb_miss:
919 error_code |= ctx.key << 19;
920 env->spr[SPR_HASH1] = ctx.pg_addr[0];
921 env->spr[SPR_HASH2] = ctx.pg_addr[1];
922 /* Do not alter DAR nor DSISR */
923 goto out;
924 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
a8dea12f
JM
925 exception = EXCP_40x_DTLBMISS;
926 error_code = 0;
927 env->spr[SPR_40x_DEAR] = address;
928 if (rw)
929 env->spr[SPR_40x_ESR] = 0x00800000;
930 else
931 env->spr[SPR_40x_ESR] = 0x00000000;
76a66253
JM
932 } else {
933 error_code = 0x40000000;
934 }
9a64fbe4
FB
935 break;
936 case -2:
937 /* Access rights violation */
2be0071f 938 error_code = 0x08000000;
9a64fbe4
FB
939 break;
940 case -4:
941 /* Direct store exception */
942 switch (access_type) {
943 case ACCESS_FLOAT:
944 /* Floating point load/store */
945 exception = EXCP_ALIGN;
946 error_code = EXCP_ALIGN_FP;
947 break;
948 case ACCESS_RES:
949 /* lwarx, ldarx or srwcx. */
2be0071f 950 error_code = 0x04000000;
9a64fbe4
FB
951 break;
952 case ACCESS_EXT:
953 /* eciwx or ecowx */
2be0071f 954 error_code = 0x04100000;
9a64fbe4
FB
955 break;
956 default:
76a66253 957 printf("DSI: invalid exception (%d)\n", ret);
9a64fbe4
FB
958 exception = EXCP_PROGRAM;
959 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
960 break;
961 }
fdabc366 962 break;
2be0071f
FB
963 case -5:
964 /* No match in segment table */
965 exception = EXCP_DSEG;
966 error_code = 0;
967 break;
9a64fbe4 968 }
fdabc366 969 if (exception == EXCP_DSI && rw == 1)
2be0071f 970 error_code |= 0x02000000;
76a66253
JM
971 /* Store fault address */
972 env->spr[SPR_DAR] = address;
2be0071f 973 env->spr[SPR_DSISR] = error_code;
9a64fbe4 974 }
76a66253 975 out:
9a64fbe4
FB
976#if 0
977 printf("%s: set exception to %d %02x\n",
978 __func__, exception, error_code);
979#endif
980 env->exception_index = exception;
981 env->error_code = error_code;
9a64fbe4
FB
982 ret = 1;
983 }
76a66253 984
9a64fbe4
FB
985 return ret;
986}
987
3fc6c082
FB
988/*****************************************************************************/
989/* BATs management */
990#if !defined(FLUSH_ALL_TLBS)
991static inline void do_invalidate_BAT (CPUPPCState *env,
992 target_ulong BATu, target_ulong mask)
993{
994 target_ulong base, end, page;
76a66253 995
3fc6c082
FB
996 base = BATu & ~0x0001FFFF;
997 end = base + mask + 0x00020000;
998#if defined (DEBUG_BATS)
76a66253 999 if (loglevel != 0) {
1b9eb036 1000 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
76a66253
JM
1001 base, end, mask);
1002 }
3fc6c082
FB
1003#endif
1004 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1005 tlb_flush_page(env, page);
1006#if defined (DEBUG_BATS)
1007 if (loglevel != 0)
1008 fprintf(logfile, "Flush done\n");
1009#endif
1010}
1011#endif
1012
1013static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
1014 target_ulong value)
1015{
1016#if defined (DEBUG_BATS)
1017 if (loglevel != 0) {
1b9eb036
JM
1018 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1019 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
3fc6c082
FB
1020 }
1021#endif
1022}
1023
1024target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1025{
1026 return env->IBAT[0][nr];
1027}
1028
1029target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1030{
1031 return env->IBAT[1][nr];
1032}
1033
1034void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1035{
1036 target_ulong mask;
1037
1038 dump_store_bat(env, 'I', 0, nr, value);
1039 if (env->IBAT[0][nr] != value) {
1040 mask = (value << 15) & 0x0FFE0000UL;
1041#if !defined(FLUSH_ALL_TLBS)
1042 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1043#endif
1044 /* When storing valid upper BAT, mask BEPI and BRPN
1045 * and invalidate all TLBs covered by this BAT
1046 */
1047 mask = (value << 15) & 0x0FFE0000UL;
1048 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1049 (value & ~0x0001FFFFUL & ~mask);
1050 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1051 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1052#if !defined(FLUSH_ALL_TLBS)
1053 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
76a66253 1054#else
3fc6c082
FB
1055 tlb_flush(env, 1);
1056#endif
1057 }
1058}
1059
1060void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1061{
1062 dump_store_bat(env, 'I', 1, nr, value);
1063 env->IBAT[1][nr] = value;
1064}
1065
1066target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1067{
1068 return env->DBAT[0][nr];
1069}
1070
1071target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1072{
1073 return env->DBAT[1][nr];
1074}
1075
1076void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1077{
1078 target_ulong mask;
1079
1080 dump_store_bat(env, 'D', 0, nr, value);
1081 if (env->DBAT[0][nr] != value) {
1082 /* When storing valid upper BAT, mask BEPI and BRPN
1083 * and invalidate all TLBs covered by this BAT
1084 */
1085 mask = (value << 15) & 0x0FFE0000UL;
1086#if !defined(FLUSH_ALL_TLBS)
1087 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1088#endif
1089 mask = (value << 15) & 0x0FFE0000UL;
1090 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1091 (value & ~0x0001FFFFUL & ~mask);
1092 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1093 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1094#if !defined(FLUSH_ALL_TLBS)
1095 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1096#else
1097 tlb_flush(env, 1);
1098#endif
1099 }
1100}
1101
1102void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1103{
1104 dump_store_bat(env, 'D', 1, nr, value);
1105 env->DBAT[1][nr] = value;
1106}
1107
3fc6c082
FB
1108/*****************************************************************************/
1109/* Special registers manipulation */
d9bce9d9
JM
1110#if defined(TARGET_PPC64)
1111target_ulong ppc_load_asr (CPUPPCState *env)
1112{
1113 return env->asr;
1114}
1115
1116void ppc_store_asr (CPUPPCState *env, target_ulong value)
1117{
1118 if (env->asr != value) {
1119 env->asr = value;
1120 tlb_flush(env, 1);
1121 }
1122}
1123#endif
1124
3fc6c082
FB
1125target_ulong do_load_sdr1 (CPUPPCState *env)
1126{
1127 return env->sdr1;
1128}
1129
1130void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1131{
1132#if defined (DEBUG_MMU)
1133 if (loglevel != 0) {
1b9eb036 1134 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
3fc6c082
FB
1135 }
1136#endif
1137 if (env->sdr1 != value) {
1138 env->sdr1 = value;
76a66253 1139 tlb_flush(env, 1);
3fc6c082
FB
1140 }
1141}
1142
1143target_ulong do_load_sr (CPUPPCState *env, int srnum)
1144{
1145 return env->sr[srnum];
1146}
1147
1148void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1149{
1150#if defined (DEBUG_MMU)
1151 if (loglevel != 0) {
1b9eb036
JM
1152 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1153 __func__, srnum, value, env->sr[srnum]);
3fc6c082
FB
1154 }
1155#endif
1156 if (env->sr[srnum] != value) {
1157 env->sr[srnum] = value;
1158#if !defined(FLUSH_ALL_TLBS) && 0
1159 {
1160 target_ulong page, end;
1161 /* Invalidate 256 MB of virtual memory */
1162 page = (16 << 20) * srnum;
1163 end = page + (16 << 20);
1164 for (; page != end; page += TARGET_PAGE_SIZE)
1165 tlb_flush_page(env, page);
1166 }
1167#else
76a66253 1168 tlb_flush(env, 1);
3fc6c082
FB
1169#endif
1170 }
1171}
76a66253 1172#endif /* !defined (CONFIG_USER_ONLY) */
3fc6c082 1173
76a66253 1174uint32_t ppc_load_xer (CPUPPCState *env)
79aceca5
FB
1175{
1176 return (xer_so << XER_SO) |
1177 (xer_ov << XER_OV) |
1178 (xer_ca << XER_CA) |
3fc6c082
FB
1179 (xer_bc << XER_BC) |
1180 (xer_cmp << XER_CMP);
79aceca5
FB
1181}
1182
76a66253 1183void ppc_store_xer (CPUPPCState *env, uint32_t value)
79aceca5
FB
1184{
1185 xer_so = (value >> XER_SO) & 0x01;
1186 xer_ov = (value >> XER_OV) & 0x01;
1187 xer_ca = (value >> XER_CA) & 0x01;
3fc6c082 1188 xer_cmp = (value >> XER_CMP) & 0xFF;
d9bce9d9 1189 xer_bc = (value >> XER_BC) & 0x7F;
79aceca5
FB
1190}
1191
76a66253
JM
1192/* Swap temporary saved registers with GPRs */
1193static inline void swap_gpr_tgpr (CPUPPCState *env)
79aceca5 1194{
76a66253
JM
1195 ppc_gpr_t tmp;
1196
1197 tmp = env->gpr[0];
1198 env->gpr[0] = env->tgpr[0];
1199 env->tgpr[0] = tmp;
1200 tmp = env->gpr[1];
1201 env->gpr[1] = env->tgpr[1];
1202 env->tgpr[1] = tmp;
1203 tmp = env->gpr[2];
1204 env->gpr[2] = env->tgpr[2];
1205 env->tgpr[2] = tmp;
1206 tmp = env->gpr[3];
1207 env->gpr[3] = env->tgpr[3];
1208 env->tgpr[3] = tmp;
79aceca5
FB
1209}
1210
76a66253
JM
1211/* GDBstub can read and write MSR... */
1212target_ulong do_load_msr (CPUPPCState *env)
79aceca5 1213{
76a66253
JM
1214 return
1215#if defined (TARGET_PPC64)
d9bce9d9
JM
1216 ((target_ulong)msr_sf << MSR_SF) |
1217 ((target_ulong)msr_isf << MSR_ISF) |
1218 ((target_ulong)msr_hv << MSR_HV) |
76a66253 1219#endif
d9bce9d9
JM
1220 ((target_ulong)msr_ucle << MSR_UCLE) |
1221 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1222 ((target_ulong)msr_ap << MSR_AP) |
1223 ((target_ulong)msr_sa << MSR_SA) |
1224 ((target_ulong)msr_key << MSR_KEY) |
1225 ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
1226 ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
1227 ((target_ulong)msr_ile << MSR_ILE) |
1228 ((target_ulong)msr_ee << MSR_EE) |
1229 ((target_ulong)msr_pr << MSR_PR) |
1230 ((target_ulong)msr_fp << MSR_FP) |
1231 ((target_ulong)msr_me << MSR_ME) |
1232 ((target_ulong)msr_fe0 << MSR_FE0) |
1233 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1234 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1235 ((target_ulong)msr_fe1 << MSR_FE1) |
1236 ((target_ulong)msr_al << MSR_AL) |
1237 ((target_ulong)msr_ip << MSR_IP) |
1238 ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
1239 ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
1240 ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
1241 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1242 ((target_ulong)msr_ri << MSR_RI) |
1243 ((target_ulong)msr_le << MSR_LE);
3fc6c082
FB
1244}
1245
1246void do_store_msr (CPUPPCState *env, target_ulong value)
313adae9 1247{
50443c98
FB
1248 int enter_pm;
1249
3fc6c082
FB
1250 value &= env->msr_mask;
1251 if (((value >> MSR_IR) & 1) != msr_ir ||
1252 ((value >> MSR_DR) & 1) != msr_dr) {
76a66253 1253 /* Flush all tlb when changing translation mode */
d094807b 1254 tlb_flush(env, 1);
3fc6c082 1255 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
a541f297 1256 }
3fc6c082
FB
1257#if 0
1258 if (loglevel != 0) {
1259 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1260 }
1261#endif
76a66253
JM
1262 switch (PPC_EXCP(env)) {
1263 case PPC_FLAGS_EXCP_602:
1264 case PPC_FLAGS_EXCP_603:
1265 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1266 /* Swap temporary saved registers with GPRs */
1267 swap_gpr_tgpr(env);
1268 }
1269 break;
1270 default:
1271 break;
1272 }
1273#if defined (TARGET_PPC64)
1274 msr_sf = (value >> MSR_SF) & 1;
1275 msr_isf = (value >> MSR_ISF) & 1;
1276 msr_hv = (value >> MSR_HV) & 1;
1277#endif
1278 msr_ucle = (value >> MSR_UCLE) & 1;
1279 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
1280 msr_ap = (value >> MSR_AP) & 1;
1281 msr_sa = (value >> MSR_SA) & 1;
1282 msr_key = (value >> MSR_KEY) & 1;
1283 msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
1284 msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
1285 msr_ile = (value >> MSR_ILE) & 1;
1286 msr_ee = (value >> MSR_EE) & 1;
1287 msr_pr = (value >> MSR_PR) & 1;
1288 msr_fp = (value >> MSR_FP) & 1;
1289 msr_me = (value >> MSR_ME) & 1;
1290 msr_fe0 = (value >> MSR_FE0) & 1;
1291 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
1292 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
1293 msr_fe1 = (value >> MSR_FE1) & 1;
1294 msr_al = (value >> MSR_AL) & 1;
1295 msr_ip = (value >> MSR_IP) & 1;
1296 msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
1297 msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
1298 msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
1299 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
1300 msr_ri = (value >> MSR_RI) & 1;
1301 msr_le = (value >> MSR_LE) & 1;
3fc6c082 1302 do_compute_hflags(env);
50443c98
FB
1303
1304 enter_pm = 0;
1305 switch (PPC_EXCP(env)) {
d9bce9d9
JM
1306 case PPC_FLAGS_EXCP_603:
1307 /* Don't handle SLEEP mode: we should disable all clocks...
1308 * No dynamic power-management.
1309 */
1310 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1311 enter_pm = 1;
1312 break;
1313 case PPC_FLAGS_EXCP_604:
1314 if (msr_pow == 1)
1315 enter_pm = 1;
1316 break;
50443c98 1317 case PPC_FLAGS_EXCP_7x0:
76a66253 1318 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
50443c98
FB
1319 enter_pm = 1;
1320 break;
1321 default:
1322 break;
1323 }
1324 if (enter_pm) {
e80e1cc4 1325 /* power save: exit cpu loop */
50443c98 1326 env->halted = 1;
e80e1cc4
FB
1327 env->exception_index = EXCP_HLT;
1328 cpu_loop_exit();
1329 }
3fc6c082
FB
1330}
1331
d9bce9d9 1332#if defined(TARGET_PPC64)
426613db 1333void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
d9bce9d9 1334{
426613db
JM
1335 do_store_msr(env,
1336 (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
d9bce9d9
JM
1337}
1338#endif
1339
76a66253 1340void do_compute_hflags (CPUPPCState *env)
3fc6c082 1341{
76a66253 1342 /* Compute current hflags */
c62db105
JM
1343 env->hflags = (msr_cm << MSR_CM) | (msr_vr << MSR_VR) |
1344 (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
1345 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
1346 (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
76a66253 1347#if defined (TARGET_PPC64)
c62db105 1348 /* No care here: PowerPC 64 MSR_SF means the same as MSR_CM for BookE */
d9bce9d9 1349 env->hflags |= (msr_sf << (MSR_SF - 32)) | (msr_hv << (MSR_HV - 32));
4b3686fa 1350#endif
3fc6c082
FB
1351}
1352
1353/*****************************************************************************/
1354/* Exception processing */
18fba28c 1355#if defined (CONFIG_USER_ONLY)
9a64fbe4 1356void do_interrupt (CPUState *env)
79aceca5 1357{
18fba28c
FB
1358 env->exception_index = -1;
1359}
47103572 1360
e9df014c 1361void ppc_hw_interrupt (CPUState *env)
47103572
JM
1362{
1363 env->exception_index = -1;
47103572 1364}
76a66253 1365#else /* defined (CONFIG_USER_ONLY) */
d094807b
FB
1366static void dump_syscall(CPUState *env)
1367{
d9bce9d9 1368 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1b9eb036 1369 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
d094807b
FB
1370 env->gpr[0], env->gpr[3], env->gpr[4],
1371 env->gpr[5], env->gpr[6], env->nip);
1372}
1373
18fba28c
FB
1374void do_interrupt (CPUState *env)
1375{
c62db105
JM
1376 target_ulong msr, *srr_0, *srr_1, *asrr_0, *asrr_1;
1377 int excp, idx;
79aceca5 1378
18fba28c 1379 excp = env->exception_index;
3fc6c082 1380 msr = do_load_msr(env);
2be0071f
FB
1381 /* The default is to use SRR0 & SRR1 to save the exception context */
1382 srr_0 = &env->spr[SPR_SRR0];
1383 srr_1 = &env->spr[SPR_SRR1];
c62db105
JM
1384 asrr_0 = NULL;
1385 asrr_1 = NULL;
9a64fbe4 1386#if defined (DEBUG_EXCEPTIONS)
2be0071f
FB
1387 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
1388 if (loglevel != 0) {
1b9eb036
JM
1389 fprintf(logfile,
1390 "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1391 env->nip, excp, env->error_code);
76a66253 1392 cpu_dump_state(env, logfile, fprintf, 0);
b769d8fe 1393 }
79aceca5 1394 }
9a64fbe4 1395#endif
b769d8fe 1396 if (loglevel & CPU_LOG_INT) {
1b9eb036
JM
1397 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1398 env->nip, excp, env->error_code);
b769d8fe 1399 }
2be0071f 1400 msr_pow = 0;
c62db105 1401 idx = -1;
9a64fbe4
FB
1402 /* Generate informations in save/restore registers */
1403 switch (excp) {
76a66253 1404 /* Generic PowerPC exceptions */
2be0071f 1405 case EXCP_RESET: /* 0x0100 */
c62db105
JM
1406 switch (PPC_EXCP(env)) {
1407 case PPC_FLAGS_EXCP_40x:
1408 srr_0 = &env->spr[SPR_40x_SRR2];
1409 srr_1 = &env->spr[SPR_40x_SRR3];
1410 break;
1411 case PPC_FLAGS_EXCP_BOOKE:
1412 idx = 0;
1413 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1414 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1415 break;
1416 default:
2be0071f
FB
1417 if (msr_ip)
1418 excp += 0xFFC00;
1419 excp |= 0xFFC00000;
c62db105 1420 break;
2be0071f 1421 }
9a64fbe4 1422 goto store_next;
2be0071f 1423 case EXCP_MACHINE_CHECK: /* 0x0200 */
c62db105
JM
1424 switch (PPC_EXCP(env)) {
1425 case PPC_FLAGS_EXCP_40x:
2be0071f
FB
1426 srr_0 = &env->spr[SPR_40x_SRR2];
1427 srr_1 = &env->spr[SPR_40x_SRR3];
c62db105
JM
1428 break;
1429 case PPC_FLAGS_EXCP_BOOKE:
1430 idx = 1;
1431 srr_0 = &env->spr[SPR_BOOKE_MCSRR0];
1432 srr_1 = &env->spr[SPR_BOOKE_MCSRR1];
1433 asrr_0 = &env->spr[SPR_BOOKE_CSRR0];
1434 asrr_1 = &env->spr[SPR_BOOKE_CSRR1];
1435 msr_ce = 0;
1436 break;
1437 default:
1438 break;
2be0071f 1439 }
9a64fbe4
FB
1440 msr_me = 0;
1441 break;
2be0071f 1442 case EXCP_DSI: /* 0x0300 */
9a64fbe4
FB
1443 /* Store exception cause */
1444 /* data location address has been stored
1445 * when the fault has been detected
2be0071f 1446 */
c62db105 1447 idx = 2;
76a66253 1448 msr &= ~0xFFFF0000;
a541f297 1449#if defined (DEBUG_EXCEPTIONS)
76a66253 1450 if (loglevel) {
1b9eb036
JM
1451 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
1452 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
76a66253 1453 }
a541f297
FB
1454#endif
1455 goto store_next;
2be0071f 1456 case EXCP_ISI: /* 0x0400 */
9a64fbe4 1457 /* Store exception cause */
c62db105 1458 idx = 3;
76a66253 1459 msr &= ~0xFFFF0000;
2be0071f 1460 msr |= env->error_code;
a541f297 1461#if defined (DEBUG_EXCEPTIONS)
76a66253 1462 if (loglevel != 0) {
1b9eb036
JM
1463 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
1464 "\n", msr, env->nip);
76a66253 1465 }
a541f297 1466#endif
9a64fbe4 1467 goto store_next;
2be0071f 1468 case EXCP_EXTERNAL: /* 0x0500 */
c62db105 1469 idx = 4;
9a64fbe4 1470 goto store_next;
2be0071f 1471 case EXCP_ALIGN: /* 0x0600 */
76a66253 1472 if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
2be0071f 1473 /* Store exception cause */
c62db105 1474 idx = 5;
2be0071f
FB
1475 /* Get rS/rD and rA from faulting opcode */
1476 env->spr[SPR_DSISR] |=
1477 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1478 /* data location address has been stored
1479 * when the fault has been detected
1480 */
1481 } else {
1482 /* IO error exception on PowerPC 601 */
1483 /* XXX: TODO */
1484 cpu_abort(env,
1485 "601 IO error exception is not implemented yet !\n");
1486 }
9a64fbe4 1487 goto store_current;
2be0071f 1488 case EXCP_PROGRAM: /* 0x0700 */
c62db105 1489 idx = 6;
9a64fbe4
FB
1490 msr &= ~0xFFFF0000;
1491 switch (env->error_code & ~0xF) {
1492 case EXCP_FP:
1493 if (msr_fe0 == 0 && msr_fe1 == 0) {
1494#if defined (DEBUG_EXCEPTIONS)
a496775f
JM
1495 if (loglevel) {
1496 fprintf(logfile, "Ignore floating point exception\n");
1497 }
9a64fbe4
FB
1498#endif
1499 return;
76a66253 1500 }
9a64fbe4
FB
1501 msr |= 0x00100000;
1502 /* Set FX */
1503 env->fpscr[7] |= 0x8;
1504 /* Finally, update FEX */
1505 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1506 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1507 env->fpscr[7] |= 0x4;
76a66253 1508 break;
9a64fbe4 1509 case EXCP_INVAL:
a496775f
JM
1510#if defined (DEBUG_EXCEPTIONS)
1511 if (loglevel) {
1512 fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
1513 env->nip);
1514 }
1515#endif
9a64fbe4 1516 msr |= 0x00080000;
76a66253 1517 break;
9a64fbe4
FB
1518 case EXCP_PRIV:
1519 msr |= 0x00040000;
76a66253 1520 break;
9a64fbe4 1521 case EXCP_TRAP:
c62db105 1522 idx = 15;
9a64fbe4
FB
1523 msr |= 0x00020000;
1524 break;
1525 default:
1526 /* Should never occur */
76a66253
JM
1527 break;
1528 }
9a64fbe4
FB
1529 msr |= 0x00010000;
1530 goto store_current;
2be0071f 1531 case EXCP_NO_FP: /* 0x0800 */
c62db105 1532 idx = 7;
4ecc3190 1533 msr &= ~0xFFFF0000;
9a64fbe4
FB
1534 goto store_current;
1535 case EXCP_DECR:
9a64fbe4 1536 goto store_next;
2be0071f 1537 case EXCP_SYSCALL: /* 0x0C00 */
c62db105 1538 idx = 8;
d094807b
FB
1539 /* NOTE: this is a temporary hack to support graphics OSI
1540 calls from the MOL driver */
1541 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1542 env->osi_call) {
1543 if (env->osi_call(env) != 0)
1544 return;
1545 }
b769d8fe 1546 if (loglevel & CPU_LOG_INT) {
d094807b 1547 dump_syscall(env);
b769d8fe 1548 }
9a64fbe4 1549 goto store_next;
2be0071f 1550 case EXCP_TRACE: /* 0x0D00 */
2be0071f
FB
1551 goto store_next;
1552 case EXCP_PERF: /* 0x0F00 */
1553 /* XXX: TODO */
1554 cpu_abort(env,
1555 "Performance counter exception is not implemented yet !\n");
1556 goto store_next;
1557 /* 32 bits PowerPC specific exceptions */
1558 case EXCP_FP_ASSIST: /* 0x0E00 */
1559 /* XXX: TODO */
1560 cpu_abort(env, "Floating point assist exception "
1561 "is not implemented yet !\n");
1562 goto store_next;
76a66253 1563 /* 64 bits PowerPC exceptions */
2be0071f
FB
1564 case EXCP_DSEG: /* 0x0380 */
1565 /* XXX: TODO */
1566 cpu_abort(env, "Data segment exception is not implemented yet !\n");
9a64fbe4 1567 goto store_next;
2be0071f
FB
1568 case EXCP_ISEG: /* 0x0480 */
1569 /* XXX: TODO */
1570 cpu_abort(env,
1571 "Instruction segment exception is not implemented yet !\n");
9a64fbe4 1572 goto store_next;
2be0071f 1573 case EXCP_HDECR: /* 0x0980 */
76a66253
JM
1574 /* XXX: TODO */
1575 cpu_abort(env, "Hypervisor decrementer exception is not implemented "
1576 "yet !\n");
2be0071f
FB
1577 goto store_next;
1578 /* Implementation specific exceptions */
1579 case 0x0A00:
76a66253
JM
1580 if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
1581 env->spr[SPR_PVR] == CPU_PPC_G2LE)) {
2be0071f
FB
1582 /* Critical interrupt on G2 */
1583 /* XXX: TODO */
1584 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1585 goto store_next;
1586 } else {
1587 cpu_abort(env, "Invalid exception 0x0A00 !\n");
1588 }
9a64fbe4 1589 return;
2be0071f 1590 case 0x0F20:
c62db105 1591 idx = 9;
2be0071f
FB
1592 switch (PPC_EXCP(env)) {
1593 case PPC_FLAGS_EXCP_40x:
1594 /* APU unavailable on 405 */
1595 /* XXX: TODO */
1596 cpu_abort(env,
1597 "APU unavailable exception is not implemented yet !\n");
1598 goto store_next;
1599 case PPC_FLAGS_EXCP_74xx:
1600 /* Altivec unavailable */
1601 /* XXX: TODO */
1602 cpu_abort(env, "Altivec unavailable exception "
1603 "is not implemented yet !\n");
1604 goto store_next;
1605 default:
1606 cpu_abort(env, "Invalid exception 0x0F20 !\n");
1607 break;
1608 }
1609 return;
1610 case 0x1000:
c62db105 1611 idx = 10;
2be0071f
FB
1612 switch (PPC_EXCP(env)) {
1613 case PPC_FLAGS_EXCP_40x:
1614 /* PIT on 4xx */
c62db105 1615 msr &= ~0xFFFF0000;
a496775f 1616#if defined (DEBUG_EXCEPTIONS)
c62db105
JM
1617 if (loglevel != 0)
1618 fprintf(logfile, "PIT exception\n");
a496775f 1619#endif
2be0071f
FB
1620 goto store_next;
1621 case PPC_FLAGS_EXCP_602:
1622 case PPC_FLAGS_EXCP_603:
1623 /* ITLBMISS on 602/603 */
2be0071f 1624 goto store_gprs;
76a66253
JM
1625 case PPC_FLAGS_EXCP_7x5:
1626 /* ITLBMISS on 745/755 */
1627 goto tlb_miss;
2be0071f
FB
1628 default:
1629 cpu_abort(env, "Invalid exception 0x1000 !\n");
1630 break;
1631 }
1632 return;
1633 case 0x1010:
c62db105 1634 idx = 11;
2be0071f
FB
1635 switch (PPC_EXCP(env)) {
1636 case PPC_FLAGS_EXCP_40x:
1637 /* FIT on 4xx */
c62db105 1638 msr &= ~0xFFFF0000;
a496775f 1639#if defined (DEBUG_EXCEPTIONS)
c62db105
JM
1640 if (loglevel != 0)
1641 fprintf(logfile, "FIT exception\n");
a496775f 1642#endif
2be0071f
FB
1643 goto store_next;
1644 default:
1645 cpu_abort(env, "Invalid exception 0x1010 !\n");
1646 break;
1647 }
1648 return;
1649 case 0x1020:
c62db105 1650 idx = 12;
2be0071f
FB
1651 switch (PPC_EXCP(env)) {
1652 case PPC_FLAGS_EXCP_40x:
1653 /* Watchdog on 4xx */
c62db105 1654 msr &= ~0xFFFF0000;
a496775f 1655#if defined (DEBUG_EXCEPTIONS)
c62db105
JM
1656 if (loglevel != 0)
1657 fprintf(logfile, "WDT exception\n");
a496775f 1658#endif
2be0071f 1659 goto store_next;
c62db105
JM
1660 case PPC_FLAGS_EXCP_BOOKE:
1661 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1662 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1663 break;
2be0071f
FB
1664 default:
1665 cpu_abort(env, "Invalid exception 0x1020 !\n");
1666 break;
1667 }
1668 return;
1669 case 0x1100:
c62db105 1670 idx = 13;
2be0071f
FB
1671 switch (PPC_EXCP(env)) {
1672 case PPC_FLAGS_EXCP_40x:
1673 /* DTLBMISS on 4xx */
a8dea12f 1674 msr &= ~0xFFFF0000;
2be0071f
FB
1675 goto store_next;
1676 case PPC_FLAGS_EXCP_602:
1677 case PPC_FLAGS_EXCP_603:
1678 /* DLTLBMISS on 602/603 */
2be0071f 1679 goto store_gprs;
76a66253
JM
1680 case PPC_FLAGS_EXCP_7x5:
1681 /* DLTLBMISS on 745/755 */
1682 goto tlb_miss;
2be0071f
FB
1683 default:
1684 cpu_abort(env, "Invalid exception 0x1100 !\n");
1685 break;
1686 }
1687 return;
1688 case 0x1200:
c62db105 1689 idx = 14;
2be0071f
FB
1690 switch (PPC_EXCP(env)) {
1691 case PPC_FLAGS_EXCP_40x:
1692 /* ITLBMISS on 4xx */
a8dea12f 1693 msr &= ~0xFFFF0000;
2be0071f
FB
1694 goto store_next;
1695 case PPC_FLAGS_EXCP_602:
1696 case PPC_FLAGS_EXCP_603:
1697 /* DSTLBMISS on 602/603 */
2be0071f 1698 store_gprs:
76a66253
JM
1699 /* Swap temporary saved registers with GPRs */
1700 swap_gpr_tgpr(env);
1701 msr_tgpr = 1;
2be0071f
FB
1702#if defined (DEBUG_SOFTWARE_TLB)
1703 if (loglevel != 0) {
76a66253
JM
1704 const unsigned char *es;
1705 target_ulong *miss, *cmp;
1706 int en;
1707 if (excp == 0x1000) {
1708 es = "I";
1709 en = 'I';
1710 miss = &env->spr[SPR_IMISS];
1711 cmp = &env->spr[SPR_ICMP];
1712 } else {
1713 if (excp == 0x1100)
1714 es = "DL";
1715 else
1716 es = "DS";
1717 en = 'D';
1718 miss = &env->spr[SPR_DMISS];
1719 cmp = &env->spr[SPR_DCMP];
1720 }
1b9eb036
JM
1721 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
1722 " H1 " ADDRX " H2 " ADDRX " " ADDRX "\n",
1723 es, en, *miss, en, *cmp,
76a66253 1724 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2be0071f
FB
1725 env->error_code);
1726 }
9a64fbe4 1727#endif
76a66253
JM
1728 goto tlb_miss;
1729 case PPC_FLAGS_EXCP_7x5:
1730 /* DSTLBMISS on 745/755 */
1731 tlb_miss:
1732 msr &= ~0xF83F0000;
2be0071f
FB
1733 msr |= env->crf[0] << 28;
1734 msr |= env->error_code; /* key, D/I, S/L bits */
1735 /* Set way using a LRU mechanism */
76a66253 1736 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2be0071f
FB
1737 goto store_next;
1738 default:
1739 cpu_abort(env, "Invalid exception 0x1200 !\n");
1740 break;
1741 }
1742 return;
1743 case 0x1300:
1744 switch (PPC_EXCP(env)) {
1745 case PPC_FLAGS_EXCP_601:
1746 case PPC_FLAGS_EXCP_602:
1747 case PPC_FLAGS_EXCP_603:
1748 case PPC_FLAGS_EXCP_604:
1749 case PPC_FLAGS_EXCP_7x0:
1750 case PPC_FLAGS_EXCP_7x5:
1751 /* IABR on 6xx/7xx */
1752 /* XXX: TODO */
1753 cpu_abort(env, "IABR exception is not implemented yet !\n");
1754 goto store_next;
1755 default:
1756 cpu_abort(env, "Invalid exception 0x1300 !\n");
1757 break;
1758 }
1759 return;
1760 case 0x1400:
1761 switch (PPC_EXCP(env)) {
1762 case PPC_FLAGS_EXCP_601:
1763 case PPC_FLAGS_EXCP_602:
1764 case PPC_FLAGS_EXCP_603:
1765 case PPC_FLAGS_EXCP_604:
1766 case PPC_FLAGS_EXCP_7x0:
1767 case PPC_FLAGS_EXCP_7x5:
1768 /* SMI on 6xx/7xx */
1769 /* XXX: TODO */
1770 cpu_abort(env, "SMI exception is not implemented yet !\n");
1771 goto store_next;
1772 default:
1773 cpu_abort(env, "Invalid exception 0x1400 !\n");
1774 break;
1775 }
1776 return;
1777 case 0x1500:
1778 switch (PPC_EXCP(env)) {
1779 case PPC_FLAGS_EXCP_602:
1780 /* Watchdog on 602 */
76a66253 1781 /* XXX: TODO */
2be0071f
FB
1782 cpu_abort(env,
1783 "602 watchdog exception is not implemented yet !\n");
1784 goto store_next;
1785 case PPC_FLAGS_EXCP_970:
1786 /* Soft patch exception on 970 */
1787 /* XXX: TODO */
1788 cpu_abort(env,
1789 "970 soft-patch exception is not implemented yet !\n");
1790 goto store_next;
1791 case PPC_FLAGS_EXCP_74xx:
1792 /* VPU assist on 74xx */
1793 /* XXX: TODO */
1794 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1795 goto store_next;
1796 default:
1797 cpu_abort(env, "Invalid exception 0x1500 !\n");
1798 break;
1799 }
1800 return;
1801 case 0x1600:
1802 switch (PPC_EXCP(env)) {
1803 case PPC_FLAGS_EXCP_602:
1804 /* Emulation trap on 602 */
1805 /* XXX: TODO */
1806 cpu_abort(env, "602 emulation trap exception "
1807 "is not implemented yet !\n");
1808 goto store_next;
1809 case PPC_FLAGS_EXCP_970:
1810 /* Maintenance exception on 970 */
1811 /* XXX: TODO */
1812 cpu_abort(env,
1813 "970 maintenance exception is not implemented yet !\n");
1814 goto store_next;
1815 default:
1816 cpu_abort(env, "Invalid exception 0x1600 !\n");
1817 break;
1818 }
1819 return;
1820 case 0x1700:
1821 switch (PPC_EXCP(env)) {
1822 case PPC_FLAGS_EXCP_7x0:
1823 case PPC_FLAGS_EXCP_7x5:
1824 /* Thermal management interrupt on G3 */
1825 /* XXX: TODO */
1826 cpu_abort(env, "G3 thermal management exception "
1827 "is not implemented yet !\n");
1828 goto store_next;
1829 case PPC_FLAGS_EXCP_970:
1830 /* VPU assist on 970 */
1831 /* XXX: TODO */
1832 cpu_abort(env,
1833 "970 VPU assist exception is not implemented yet !\n");
1834 goto store_next;
1835 default:
1836 cpu_abort(env, "Invalid exception 0x1700 !\n");
1837 break;
1838 }
1839 return;
1840 case 0x1800:
1841 switch (PPC_EXCP(env)) {
1842 case PPC_FLAGS_EXCP_970:
1843 /* Thermal exception on 970 */
1844 /* XXX: TODO */
1845 cpu_abort(env, "970 thermal management exception "
1846 "is not implemented yet !\n");
1847 goto store_next;
1848 default:
1849 cpu_abort(env, "Invalid exception 0x1800 !\n");
1850 break;
1851 }
1852 return;
1853 case 0x2000:
1854 switch (PPC_EXCP(env)) {
1855 case PPC_FLAGS_EXCP_40x:
1856 /* DEBUG on 4xx */
1857 /* XXX: TODO */
1858 cpu_abort(env, "40x debug exception is not implemented yet !\n");
1859 goto store_next;
1860 case PPC_FLAGS_EXCP_601:
1861 /* Run mode exception on 601 */
1862 /* XXX: TODO */
1863 cpu_abort(env,
1864 "601 run mode exception is not implemented yet !\n");
1865 goto store_next;
c62db105
JM
1866 case PPC_FLAGS_EXCP_BOOKE:
1867 srr_0 = &env->spr[SPR_BOOKE_CSRR0];
1868 srr_1 = &env->spr[SPR_BOOKE_CSRR1];
1869 break;
2be0071f
FB
1870 default:
1871 cpu_abort(env, "Invalid exception 0x1800 !\n");
1872 break;
1873 }
1874 return;
1875 /* Other exceptions */
1876 /* Qemu internal exceptions:
1877 * we should never come here with those values: abort execution
1878 */
1879 default:
1880 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
9a64fbe4
FB
1881 return;
1882 store_current:
2be0071f 1883 /* save current instruction location */
c62db105 1884 *srr_0 = env->nip - 4;
9a64fbe4
FB
1885 break;
1886 store_next:
2be0071f 1887 /* save next instruction location */
c62db105 1888 *srr_0 = env->nip;
9a64fbe4
FB
1889 break;
1890 }
2be0071f
FB
1891 /* Save msr */
1892 *srr_1 = msr;
c62db105
JM
1893 if (asrr_0 != NULL)
1894 *asrr_0 = *srr_0;
1895 if (asrr_1 != NULL)
1896 *asrr_1 = *srr_1;
2be0071f
FB
1897 /* If we disactivated any translation, flush TLBs */
1898 if (msr_ir || msr_dr) {
1899 tlb_flush(env, 1);
1900 }
9a64fbe4 1901 /* reload MSR with correct bits */
9a64fbe4
FB
1902 msr_ee = 0;
1903 msr_pr = 0;
1904 msr_fp = 0;
1905 msr_fe0 = 0;
1906 msr_se = 0;
1907 msr_be = 0;
1908 msr_fe1 = 0;
1909 msr_ir = 0;
1910 msr_dr = 0;
1911 msr_ri = 0;
1912 msr_le = msr_ile;
c62db105
JM
1913 if (PPC_EXCP(env) == PPC_FLAGS_EXCP_BOOKE) {
1914 msr_cm = msr_icm;
1915 if (idx == -1 || (idx >= 16 && idx < 32)) {
1916 cpu_abort(env, "Invalid exception index for excp %d %08x idx %d\n",
1917 excp, excp, idx);
1918 }
1919#if defined(TARGET_PPC64)
1920 if (msr_cm)
1921 env->nip = (uint64_t)env->spr[SPR_BOOKE_IVPR];
1922 else
1923#endif
1924 env->nip = (uint32_t)env->spr[SPR_BOOKE_IVPR];
1925 if (idx < 16)
1926 env->nip |= env->spr[SPR_BOOKE_IVOR0 + idx];
1927 else if (idx < 38)
1928 env->nip |= env->spr[SPR_BOOKE_IVOR32 + idx - 32];
1929 } else {
1930 msr_sf = msr_isf;
1931 env->nip = excp;
1932 }
3fc6c082 1933 do_compute_hflags(env);
9a64fbe4 1934 /* Jump to handler */
9a64fbe4 1935 env->exception_index = EXCP_NONE;
fb0eaffc 1936}
47103572 1937
e9df014c 1938void ppc_hw_interrupt (CPUPPCState *env)
47103572
JM
1939{
1940 int raised = 0;
1941
a496775f
JM
1942#if 1
1943 if (loglevel & CPU_LOG_INT) {
1944 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
1945 __func__, env, env->pending_interrupts,
1946 env->interrupt_request, msr_me, msr_ee);
1947 }
47103572
JM
1948#endif
1949 /* Raise it */
1950 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
1951 /* External reset / critical input */
e9df014c
JM
1952 /* XXX: critical input should be handled another way.
1953 * This code is not correct !
1954 */
47103572
JM
1955 env->exception_index = EXCP_RESET;
1956 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
1957 raised = 1;
1958 }
1959 if (raised == 0 && msr_me != 0) {
1960 /* Machine check exception */
1961 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
1962 env->exception_index = EXCP_MACHINE_CHECK;
1963 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
1964 raised = 1;
1965 }
1966 }
1967 if (raised == 0 && msr_ee != 0) {
1968#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
1969 /* Hypervisor decrementer exception */
1970 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
1971 env->exception_index = EXCP_HDECR;
1972 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
1973 raised = 1;
1974 } else
1975#endif
1976 /* Decrementer exception */
1977 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
1978 env->exception_index = EXCP_DECR;
1979 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
1980 raised = 1;
1981 /* Programmable interval timer on embedded PowerPC */
1982 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
1983 env->exception_index = EXCP_40x_PIT;
1984 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
1985 raised = 1;
1986 /* Fixed interval timer on embedded PowerPC */
1987 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
1988 env->exception_index = EXCP_40x_FIT;
1989 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
1990 raised = 1;
1991 /* Watchdog timer on embedded PowerPC */
1992 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
1993 env->exception_index = EXCP_40x_WATCHDOG;
1994 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
1995 raised = 1;
1996 /* External interrupt */
1997 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
1998 env->exception_index = EXCP_EXTERNAL;
e9df014c
JM
1999 /* Taking an external interrupt does not clear the external
2000 * interrupt status
2001 */
2002#if 0
47103572 2003 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
e9df014c 2004#endif
47103572 2005 raised = 1;
d0dfae6e
JM
2006#if 0 // TODO
2007 /* Thermal interrupt */
2008 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2009 env->exception_index = EXCP_970_THRM;
2010 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2011 raised = 1;
2012#endif
47103572
JM
2013 }
2014#if 0 // TODO
2015 /* External debug exception */
2016 } else if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2017 env->exception_index = EXCP_xxx;
2018 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2019 raised = 1;
2020#endif
2021 }
2022 if (raised != 0) {
2023 env->error_code = 0;
2024 do_interrupt(env);
2025 }
47103572 2026}
18fba28c 2027#endif /* !CONFIG_USER_ONLY */
a496775f
JM
2028
2029void cpu_dump_EA (target_ulong EA)
2030{
2031 FILE *f;
2032
2033 if (logfile) {
2034 f = logfile;
2035 } else {
2036 f = stdout;
2037 return;
2038 }
2039 fprintf(f, "Memory access at address " TARGET_FMT_lx "\n", EA);
2040}
2041