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Solaris host compilation fix by Shaddy Baddah.
[mirror_qemu.git] / target-ppc / helper.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
79aceca5 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
fdabc366
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
27
28#include "cpu.h"
29#include "exec-all.h"
9a64fbe4
FB		 30
31//#define DEBUG_MMU
32//#define DEBUG_BATS
76a66253 33//#define DEBUG_SOFTWARE_TLB
9a64fbe4 34//#define DEBUG_EXCEPTIONS
fdabc366 35//#define FLUSH_ALL_TLBS
9a64fbe4 36
9a64fbe4 37/*****************************************************************************/
3fc6c082 38/* PowerPC MMU emulation */
a541f297 39
d9bce9d9 40#if defined(CONFIG_USER_ONLY)
24741ef3
FB		 41int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
42 int is_user, int is_softmmu)
43{
44 int exception, error_code;
d9bce9d9 45
24741ef3
FB		 46 if (rw == 2) {
47 exception = EXCP_ISI;
48 error_code = 0;
49 } else {
50 exception = EXCP_DSI;
51 error_code = 0;
52 if (rw)
53 error_code |= 0x02000000;
54 env->spr[SPR_DAR] = address;
55 env->spr[SPR_DSISR] = error_code;
56 }
57 env->exception_index = exception;
58 env->error_code = error_code;
76a66253 59
24741ef3
FB		 60 return 1;
61}
76a66253
JM		 62
63target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
24741ef3
FB		 64{
65 return addr;
66}
67#else
76a66253
JM		 68/* Common routines used by software and hardware TLBs emulation */
69static inline int pte_is_valid (target_ulong pte0)
70{
71 return pte0 & 0x80000000 ? 1 : 0;
72}
73
74static inline void pte_invalidate (target_ulong *pte0)
75{
76 *pte0 &= ~0x80000000;
77}
78
79#define PTE_PTEM_MASK 0x7FFFFFBF
80#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
81
82static int pte_check (mmu_ctx_t *ctx,
83 target_ulong pte0, target_ulong pte1, int h, int rw)
84{
85 int access, ret;
86
87 access = 0;
88 ret = -1;
89 /* Check validity and table match */
90 if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) {
91 /* Check vsid & api */
92 if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {
93 if (ctx->raddr != (target_ulong)-1) {
94 /* all matches should have equal RPN, WIMG & PP */
95 if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
96 if (loglevel > 0)
97 fprintf(logfile, "Bad RPN/WIMG/PP\n");
98 return -3;
99 }
100 }
101 /* Compute access rights */
102 if (ctx->key == 0) {
103 access = PAGE_READ;
104 if ((pte1 & 0x00000003) != 0x3)
105 access |= PAGE_WRITE;
106 } else {
107 switch (pte1 & 0x00000003) {
108 case 0x0:
109 access = 0;
110 break;
111 case 0x1:
112 case 0x3:
113 access = PAGE_READ;
114 break;
115 case 0x2:
116 access = PAGE_READ | PAGE_WRITE;
117 break;
118 }
119 }
120 /* Keep the matching PTE informations */
121 ctx->raddr = pte1;
122 ctx->prot = access;
123 if ((rw == 0 && (access & PAGE_READ)) ||
124 (rw == 1 && (access & PAGE_WRITE))) {
125 /* Access granted */
126#if defined (DEBUG_MMU)
127 if (loglevel > 0)
128 fprintf(logfile, "PTE access granted !\n");
129#endif
130 ret = 0;
131 } else {
132 /* Access right violation */
133#if defined (DEBUG_MMU)
134 if (loglevel > 0)
135 fprintf(logfile, "PTE access rejected\n");
136#endif
137 ret = -2;
138 }
139 }
140 }
141
142 return ret;
143}
144
145static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
146 int ret, int rw)
147{
148 int store = 0;
149
150 /* Update page flags */
151 if (!(*pte1p & 0x00000100)) {
152 /* Update accessed flag */
153 *pte1p |= 0x00000100;
154 store = 1;
155 }
156 if (!(*pte1p & 0x00000080)) {
157 if (rw == 1 && ret == 0) {
158 /* Update changed flag */
159 *pte1p |= 0x00000080;
160 store = 1;
161 } else {
162 /* Force page fault for first write access */
163 ctx->prot &= ~PAGE_WRITE;
164 }
165 }
166
167 return store;
168}
169
170/* Software driven TLB helpers */
171static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
172 int way, int is_code)
173{
174 int nr;
175
176 /* Select TLB num in a way from address */
177 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
178 /* Select TLB way */
179 nr += env->tlb_per_way * way;
180 /* 6xx have separate TLBs for instructions and data */
181 if (is_code && env->id_tlbs == 1)
182 nr += env->nb_tlb;
183
184 return nr;
185}
186
187void ppc6xx_tlb_invalidate_all (CPUState *env)
188{
189 ppc_tlb_t *tlb;
190 int nr, max;
191
192#if defined (DEBUG_SOFTWARE_TLB) && 0
193 if (loglevel != 0) {
194 fprintf(logfile, "Invalidate all TLBs\n");
195 }
196#endif
197 /* Invalidate all defined software TLB */
198 max = env->nb_tlb;
199 if (env->id_tlbs == 1)
200 max *= 2;
201 for (nr = 0; nr < max; nr++) {
202 tlb = &env->tlb[nr];
203#if !defined(FLUSH_ALL_TLBS)
204 tlb_flush_page(env, tlb->EPN);
205#endif
206 pte_invalidate(&tlb->pte0);
207 }
208#if defined(FLUSH_ALL_TLBS)
209 tlb_flush(env, 1);
210#endif
211}
212
213static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
214 target_ulong eaddr,
215 int is_code, int match_epn)
216{
217 ppc_tlb_t *tlb;
218 int way, nr;
219
220#if !defined(FLUSH_ALL_TLBS)
221 /* Invalidate ITLB + DTLB, all ways */
222 for (way = 0; way < env->nb_ways; way++) {
223 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
224 tlb = &env->tlb[nr];
225 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
226#if defined (DEBUG_SOFTWARE_TLB)
227 if (loglevel != 0) {
1b9eb036 228 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
76a66253
JM		 229 nr, env->nb_tlb, eaddr);
230 }
231#endif
232 pte_invalidate(&tlb->pte0);
233 tlb_flush_page(env, tlb->EPN);
234 }
235 }
236#else
237 /* XXX: PowerPC specification say this is valid as well */
238 ppc6xx_tlb_invalidate_all(env);
239#endif
240}
241
242void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
243 int is_code)
244{
245 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
246}
247
248void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
249 target_ulong pte0, target_ulong pte1)
250{
251 ppc_tlb_t *tlb;
252 int nr;
253
254 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
255 tlb = &env->tlb[nr];
256#if defined (DEBUG_SOFTWARE_TLB)
257 if (loglevel != 0) {
1b9eb036
JM		 258 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
259 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
76a66253
JM		 260 }
261#endif
262 /* Invalidate any pending reference in Qemu for this virtual address */
263 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
264 tlb->pte0 = pte0;
265 tlb->pte1 = pte1;
266 tlb->EPN = EPN;
267 tlb->PID = 0;
268 tlb->size = 1;
269 /* Store last way for LRU mechanism */
270 env->last_way = way;
271}
272
273static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
274 target_ulong eaddr, int rw, int access_type)
275{
276 ppc_tlb_t *tlb;
277 int nr, best, way;
278 int ret;
d9bce9d9 279
76a66253
JM		 280 best = -1;
281 ret = -1; /* No TLB found */
282 for (way = 0; way < env->nb_ways; way++) {
283 nr = ppc6xx_tlb_getnum(env, eaddr, way,
284 access_type == ACCESS_CODE ? 1 : 0);
285 tlb = &env->tlb[nr];
286 /* This test "emulates" the PTE index match for hardware TLBs */
287 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
288#if defined (DEBUG_SOFTWARE_TLB)
289 if (loglevel != 0) {
1b9eb036
JM		 290 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
291 "] <> " ADDRX "\n",
76a66253
JM		 292 nr, env->nb_tlb,
293 pte_is_valid(tlb->pte0) ? "valid" : "inval",
294 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
295 }
296#endif
297 continue;
298 }
299#if defined (DEBUG_SOFTWARE_TLB)
300 if (loglevel != 0) {
1b9eb036
JM		 301 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
302 " %c %c\n",
76a66253
JM		 303 nr, env->nb_tlb,
304 pte_is_valid(tlb->pte0) ? "valid" : "inval",
305 tlb->EPN, eaddr, tlb->pte1,
306 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
307 }
308#endif
309 switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
310 case -3:
311 /* TLB inconsistency */
312 return -1;
313 case -2:
314 /* Access violation */
315 ret = -2;
316 best = nr;
317 break;
318 case -1:
319 default:
320 /* No match */
321 break;
322 case 0:
323 /* access granted */
324 /* XXX: we should go on looping to check all TLBs consistency
325 * but we can speed-up the whole thing as the
326 * result would be undefined if TLBs are not consistent.
327 */
328 ret = 0;
329 best = nr;
330 goto done;
331 }
332 }
333 if (best != -1) {
334 done:
335#if defined (DEBUG_SOFTWARE_TLB)
336 if (loglevel > 0) {
337 fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
338 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
339 }
340#endif
341 /* Update page flags */
342 pte_update_flags(ctx, &env->tlb[best].pte1, ret, rw);
343 }
344
345 return ret;
346}
347
9a64fbe4 348/* Perform BAT hit & translation */
76a66253
JM		 349static int get_bat (CPUState *env, mmu_ctx_t *ctx,
350 target_ulong virtual, int rw, int type)
9a64fbe4 351{
76a66253
JM		 352 target_ulong *BATlt, *BATut, *BATu, *BATl;
353 target_ulong base, BEPIl, BEPIu, bl;
9a64fbe4
FB		 354 int i;
355 int ret = -1;
356
357#if defined (DEBUG_BATS)
358 if (loglevel > 0) {
1b9eb036 359 fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 360 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 361 }
9a64fbe4
FB		 362#endif
363 switch (type) {
364 case ACCESS_CODE:
365 BATlt = env->IBAT[1];
366 BATut = env->IBAT[0];
367 break;
368 default:
369 BATlt = env->DBAT[1];
370 BATut = env->DBAT[0];
371 break;
372 }
373#if defined (DEBUG_BATS)
374 if (loglevel > 0) {
1b9eb036 375 fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
76a66253 376 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 377 }
9a64fbe4
FB		 378#endif
379 base = virtual & 0xFFFC0000;
380 for (i = 0; i < 4; i++) {
381 BATu = &BATut[i];
382 BATl = &BATlt[i];
383 BEPIu = *BATu & 0xF0000000;
384 BEPIl = *BATu & 0x0FFE0000;
385 bl = (*BATu & 0x00001FFC) << 15;
386#if defined (DEBUG_BATS)
387 if (loglevel > 0) {
1b9eb036
JM		 388 fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
389 " BATl 0x" ADDRX "\n",
9a64fbe4
FB		 390 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
391 *BATu, *BATl);
9a64fbe4
FB		 392 }
393#endif
394 if ((virtual & 0xF0000000) == BEPIu &&
395 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
396 /* BAT matches */
397 if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
398 (msr_pr == 1 && (*BATu & 0x00000001))) {
399 /* Get physical address */
76a66253 400 ctx->raddr = (*BATl & 0xF0000000) |
9a64fbe4 401 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
a541f297 402 (virtual & 0x0001F000);
9a64fbe4 403 if (*BATl & 0x00000001)
76a66253 404 ctx->prot = PAGE_READ;
9a64fbe4 405 if (*BATl & 0x00000002)
76a66253 406 ctx->prot = PAGE_WRITE | PAGE_READ;
9a64fbe4
FB		 407#if defined (DEBUG_BATS)
408 if (loglevel > 0) {
1b9eb036
JM		 409 fprintf(logfile, "BAT %d match: r 0x" ADDRX
410 " prot=%c%c\n",
76a66253
JM		 411 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
412 ctx->prot & PAGE_WRITE ? 'W' : '-');
9a64fbe4
FB		 413 }
414#endif
415 ret = 0;
416 break;
417 }
418 }
419 }
420 if (ret < 0) {
421#if defined (DEBUG_BATS)
1b9eb036 422 printf("no BAT match for 0x" ADDRX ":\n", virtual);
9a64fbe4
FB		 423 for (i = 0; i < 4; i++) {
424 BATu = &BATut[i];
425 BATl = &BATlt[i];
426 BEPIu = *BATu & 0xF0000000;
427 BEPIl = *BATu & 0x0FFE0000;
428 bl = (*BATu & 0x00001FFC) << 15;
1b9eb036
JM		 429 printf("%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
430 " BATl 0x" ADDRX " \n\t"
431 "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
9a64fbe4
FB		 432 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
433 *BATu, *BATl, BEPIu, BEPIl, bl);
434 }
435#endif
9a64fbe4
FB		 436 }
437 /* No hit */
438 return ret;
439}
440
441/* PTE table lookup */
76a66253 442static int find_pte (mmu_ctx_t *ctx, int h, int rw)
9a64fbe4 443{
76a66253
JM		 444 target_ulong base, pte0, pte1;
445 int i, good = -1;
446 int ret;
9a64fbe4 447
76a66253
JM		 448 ret = -1; /* No entry found */
449 base = ctx->pg_addr[h];
9a64fbe4 450 for (i = 0; i < 8; i++) {
8df1cd07
FB		 451 pte0 = ldl_phys(base + (i * 8));
452 pte1 = ldl_phys(base + (i * 8) + 4);
9a64fbe4 453#if defined (DEBUG_MMU)
d094807b 454 if (loglevel > 0) {
1b9eb036
JM		 455 fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
456 " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
457 base + (i * 8), pte0, pte1,
76a66253
JM		 458 pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem);
459 }
9a64fbe4 460#endif
76a66253
JM		 461 switch (pte_check(ctx, pte0, pte1, h, rw)) {
462 case -3:
463 /* PTE inconsistency */
464 return -1;
465 case -2:
466 /* Access violation */
467 ret = -2;
468 good = i;
469 break;
470 case -1:
471 default:
472 /* No PTE match */
473 break;
474 case 0:
475 /* access granted */
476 /* XXX: we should go on looping to check all PTEs consistency
477 * but if we can speed-up the whole thing as the
478 * result would be undefined if PTEs are not consistent.
479 */
480 ret = 0;
481 good = i;
482 goto done;
9a64fbe4
FB		 483 }
484 }
485 if (good != -1) {
76a66253 486 done:
9a64fbe4 487#if defined (DEBUG_MMU)
d094807b 488 if (loglevel > 0) {
1b9eb036
JM		 489 fprintf(logfile, "found PTE at addr 0x" ADDRX " prot=0x%01x "
490 "ret=%d\n",
76a66253
JM		 491 ctx->raddr, ctx->prot, ret);
492 }
9a64fbe4
FB		 493#endif
494 /* Update page flags */
76a66253
JM		 495 pte1 = ctx->raddr;
496 if (pte_update_flags(ctx, &pte1, ret, rw) == 1)
497 stl_phys_notdirty(base + (good * 8) + 4, pte1);
9a64fbe4
FB		 498 }
499
500 return ret;
79aceca5
FB		 501}
502
76a66253
JM		 503static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
504 target_phys_addr_t hash,
505 target_phys_addr_t mask)
79aceca5 506{
9a64fbe4 507 return (sdr1 & 0xFFFF0000) | (hash & mask);
79aceca5
FB		 508}
509
9a64fbe4 510/* Perform segment based translation */
76a66253
JM		 511static int get_segment (CPUState *env, mmu_ctx_t *ctx,
512 target_ulong eaddr, int rw, int type)
79aceca5 513{
76a66253
JM		 514 target_phys_addr_t sdr, hash, mask;
515 target_ulong sr, vsid, pgidx;
9a64fbe4 516 int ret = -1, ret2;
79aceca5 517
76a66253 518 sr = env->sr[eaddr >> 28];
9a64fbe4 519#if defined (DEBUG_MMU)
a541f297 520 if (loglevel > 0) {
1b9eb036
JM		 521 fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x"
522 ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
76a66253
JM		 523 eaddr, eaddr >> 28, sr, env->nip,
524 env->lr, msr_ir, msr_dr, msr_pr, rw, type);
a541f297 525 }
9a64fbe4 526#endif
76a66253
JM		 527 ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
528 ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
9a64fbe4
FB		 529 if ((sr & 0x80000000) == 0) {
530#if defined (DEBUG_MMU)
76a66253 531 if (loglevel > 0)
1b9eb036 532 fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
76a66253 533 ctx->key, sr & 0x10000000);
9a64fbe4
FB		 534#endif
535 /* Check if instruction fetch is allowed, if needed */
536 if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
537 /* Page address translation */
76a66253 538 pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;
9a64fbe4 539 vsid = sr & 0x00FFFFFF;
a541f297 540 hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
76a66253
JM		 541 /* Primary table address */
542 sdr = env->sdr1;
9a64fbe4 543 mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
76a66253
JM		 544 ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);
545 /* Secondary table address */
546 hash = (~hash) & 0x01FFFFC0;
547 ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);
548 ctx->ptem = (vsid << 7) | (pgidx >> 10);
549 /* Initialize real address with an invalid value */
550 ctx->raddr = (target_ulong)-1;
551 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
552 /* Software TLB search */
553 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
554 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
555 /* XXX: TODO */
556 } else {
9a64fbe4 557#if defined (DEBUG_MMU)
76a66253 558 if (loglevel > 0) {
1b9eb036
JM		 559 fprintf(logfile, "0 sdr1=0x" ADDRX " vsid=0x%06x "
560 "api=0x%04x hash=0x%07x pg_addr=0x" ADDRX "\n",
561 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
76a66253 562 }
9a64fbe4 563#endif
76a66253
JM		 564 /* Primary table lookup */
565 ret = find_pte(ctx, 0, rw);
566 if (ret < 0) {
567 /* Secondary table lookup */
9a64fbe4 568#if defined (DEBUG_MMU)
76a66253
JM		 569 if (eaddr != 0xEFFFFFFF && loglevel > 0) {
570 fprintf(logfile,
1b9eb036
JM		 571 "1 sdr1=0x" ADDRX " vsid=0x%06x api=0x%04x "
572 "hash=0x%05x pg_addr=0x" ADDRX "\n",
573 sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
76a66253 574 }
9a64fbe4 575#endif
76a66253
JM		 576 ret2 = find_pte(ctx, 1, rw);
577 if (ret2 != -1)
578 ret = ret2;
579 }
9a64fbe4 580 }
9a64fbe4
FB		 581 } else {
582#if defined (DEBUG_MMU)
76a66253
JM		 583 if (loglevel > 0)
584 fprintf(logfile, "No access allowed\n");
9a64fbe4 585#endif
76a66253 586 ret = -3;
9a64fbe4
FB		 587 }
588 } else {
589#if defined (DEBUG_MMU)
a541f297 590 if (loglevel > 0)
76a66253 591 fprintf(logfile, "direct store...\n");
9a64fbe4
FB		 592#endif
593 /* Direct-store segment : absolutely *BUGGY* for now */
594 switch (type) {
595 case ACCESS_INT:
596 /* Integer load/store : only access allowed */
597 break;
598 case ACCESS_CODE:
599 /* No code fetch is allowed in direct-store areas */
600 return -4;
601 case ACCESS_FLOAT:
602 /* Floating point load/store */
603 return -4;
604 case ACCESS_RES:
605 /* lwarx, ldarx or srwcx. */
606 return -4;
607 case ACCESS_CACHE:
608 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
609 /* Should make the instruction do no-op.
610 * As it already do no-op, it's quite easy :-)
611 */
76a66253 612 ctx->raddr = eaddr;
9a64fbe4
FB		 613 return 0;
614 case ACCESS_EXT:
615 /* eciwx or ecowx */
616 return -4;
617 default:
618 if (logfile) {
619 fprintf(logfile, "ERROR: instruction should not need "
620 "address translation\n");
621 }
622 printf("ERROR: instruction should not need "
623 "address translation\n");
624 return -4;
625 }
76a66253
JM		 626 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
627 ctx->raddr = eaddr;
9a64fbe4
FB		 628 ret = 2;
629 } else {
630 ret = -2;
631 }
79aceca5 632 }
9a64fbe4
FB		 633
634 return ret;
79aceca5
FB		 635}
636
76a66253
JM		 637static int check_physical (CPUState *env, mmu_ctx_t *ctx,
638 target_ulong eaddr, int rw)
639{
640 int in_plb, ret;
641
642 ctx->raddr = eaddr;
643 ctx->prot = PAGE_READ;
644 ret = 0;
645 if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) {
646 /* 403 family add some particular protections,
647 * using PBL/PBU registers for accesses with no translation.
648 */
649 in_plb =
650 /* Check PLB validity */
651 (env->pb[0] < env->pb[1] &&
652 /* and address in plb area */
653 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
654 (env->pb[2] < env->pb[3] &&
655 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
656 if (in_plb ^ msr_px) {
657 /* Access in protected area */
658 if (rw == 1) {
659 /* Access is not allowed */
660 ret = -2;
661 }
662 } else {
663 /* Read-write access is allowed */
664 ctx->prot |= PAGE_WRITE;
665 }
666 } else {
667 ctx->prot |= PAGE_WRITE;
668 }
669
670 return ret;
671}
672
673int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
674 int rw, int access_type, int check_BATs)
9a64fbe4
FB		 675{
676 int ret;
514fb8c1 677#if 0
9a64fbe4
FB		 678 if (loglevel > 0) {
679 fprintf(logfile, "%s\n", __func__);
680 }
d9bce9d9 681#endif
4b3686fa
FB		 682 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
683 (access_type != ACCESS_CODE && msr_dr == 0)) {
9a64fbe4 684 /* No address translation */
76a66253 685 ret = check_physical(env, ctx, eaddr, rw);
9a64fbe4
FB		 686 } else {
687 /* Try to find a BAT */
76a66253
JM		 688 ret = -1;
689 if (check_BATs)
690 ret = get_bat(env, ctx, eaddr, rw, access_type);
9a64fbe4
FB		 691 if (ret < 0) {
692 /* We didn't match any BAT entry */
76a66253 693 ret = get_segment(env, ctx, eaddr, rw, access_type);
9a64fbe4
FB		 694 }
695 }
514fb8c1 696#if 0
a541f297 697 if (loglevel > 0) {
1b9eb036 698 fprintf(logfile, "%s address " ADDRX " => " ADDRX "\n",
76a66253 699 __func__, eaddr, ctx->raddr);
a541f297 700 }
76a66253 701#endif
d9bce9d9 702
9a64fbe4
FB		 703 return ret;
704}
705
76a66253 706target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
a6b025d3 707{
76a66253 708 mmu_ctx_t ctx;
a6b025d3 709
76a66253 710 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
a6b025d3 711 return -1;
76a66253
JM		 712
713 return ctx.raddr & TARGET_PAGE_MASK;
a6b025d3 714}
9a64fbe4 715
9a64fbe4
FB		 716/* Perform address translation */
717int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
a541f297 718 int is_user, int is_softmmu)
9a64fbe4 719{
76a66253 720 mmu_ctx_t ctx;
9a64fbe4 721 int exception = 0, error_code = 0;
a541f297 722 int access_type;
9a64fbe4 723 int ret = 0;
d9bce9d9 724
b769d8fe
FB		 725 if (rw == 2) {
726 /* code access */
727 rw = 0;
728 access_type = ACCESS_CODE;
729 } else {
730 /* data access */
731 /* XXX: put correct access by using cpu_restore_state()
732 correctly */
733 access_type = ACCESS_INT;
734 // access_type = env->access_type;
735 }
76a66253 736 ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
9a64fbe4 737 if (ret == 0) {
76a66253
JM		 738 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
739 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
740 is_user, is_softmmu);
9a64fbe4 741 } else if (ret < 0) {
9a64fbe4 742#if defined (DEBUG_MMU)
76a66253
JM		 743 if (loglevel > 0)
744 cpu_dump_state(env, logfile, fprintf, 0);
9a64fbe4
FB		 745#endif
746 if (access_type == ACCESS_CODE) {
747 exception = EXCP_ISI;
748 switch (ret) {
749 case -1:
76a66253
JM		 750 /* No matches in page tables or TLB */
751 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
752 exception = EXCP_I_TLBMISS;
753 env->spr[SPR_IMISS] = address;
754 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
755 error_code = 1 << 18;
756 goto tlb_miss;
757 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
758 /* XXX: TODO */
759 } else {
760 error_code = 0x40000000;
761 }
9a64fbe4
FB		 762 break;
763 case -2:
764 /* Access rights violation */
2be0071f 765 error_code = 0x08000000;
9a64fbe4
FB		 766 break;
767 case -3:
76a66253 768 /* No execute protection violation */
2be0071f 769 error_code = 0x10000000;
9a64fbe4
FB		 770 break;
771 case -4:
772 /* Direct store exception */
773 /* No code fetch is allowed in direct-store areas */
2be0071f
FB		 774 error_code = 0x10000000;
775 break;
776 case -5:
777 /* No match in segment table */
778 exception = EXCP_ISEG;
779 error_code = 0;
9a64fbe4
FB		 780 break;
781 }
782 } else {
783 exception = EXCP_DSI;
784 switch (ret) {
785 case -1:
76a66253
JM		 786 /* No matches in page tables or TLB */
787 if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
788 if (rw == 1) {
789 exception = EXCP_DS_TLBMISS;
790 error_code = 1 << 16;
791 } else {
792 exception = EXCP_DL_TLBMISS;
793 error_code = 0;
794 }
795 env->spr[SPR_DMISS] = address;
796 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
797 tlb_miss:
798 error_code |= ctx.key << 19;
799 env->spr[SPR_HASH1] = ctx.pg_addr[0];
800 env->spr[SPR_HASH2] = ctx.pg_addr[1];
801 /* Do not alter DAR nor DSISR */
802 goto out;
803 } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
804 /* XXX: TODO */
805 } else {
806 error_code = 0x40000000;
807 }
9a64fbe4
FB		 808 break;
809 case -2:
810 /* Access rights violation */
2be0071f 811 error_code = 0x08000000;
9a64fbe4
FB		 812 break;
813 case -4:
814 /* Direct store exception */
815 switch (access_type) {
816 case ACCESS_FLOAT:
817 /* Floating point load/store */
818 exception = EXCP_ALIGN;
819 error_code = EXCP_ALIGN_FP;
820 break;
821 case ACCESS_RES:
822 /* lwarx, ldarx or srwcx. */
2be0071f 823 error_code = 0x04000000;
9a64fbe4
FB		 824 break;
825 case ACCESS_EXT:
826 /* eciwx or ecowx */
2be0071f 827 error_code = 0x04100000;
9a64fbe4
FB		 828 break;
829 default:
76a66253 830 printf("DSI: invalid exception (%d)\n", ret);
9a64fbe4
FB		 831 exception = EXCP_PROGRAM;
832 error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
833 break;
834 }
fdabc366 835 break;
2be0071f
FB		 836 case -5:
837 /* No match in segment table */
838 exception = EXCP_DSEG;
839 error_code = 0;
840 break;
9a64fbe4 841 }
fdabc366 842 if (exception == EXCP_DSI && rw == 1)
2be0071f 843 error_code |= 0x02000000;
76a66253
JM		 844 /* Store fault address */
845 env->spr[SPR_DAR] = address;
2be0071f 846 env->spr[SPR_DSISR] = error_code;
9a64fbe4 847 }
76a66253 848 out:
9a64fbe4
FB		 849#if 0
850 printf("%s: set exception to %d %02x\n",
851 __func__, exception, error_code);
852#endif
853 env->exception_index = exception;
854 env->error_code = error_code;
9a64fbe4
FB		 855 ret = 1;
856 }
76a66253 857
9a64fbe4
FB		 858 return ret;
859}
860
3fc6c082
FB		 861/*****************************************************************************/
862/* BATs management */
863#if !defined(FLUSH_ALL_TLBS)
864static inline void do_invalidate_BAT (CPUPPCState *env,
865 target_ulong BATu, target_ulong mask)
866{
867 target_ulong base, end, page;
76a66253 868
3fc6c082
FB		 869 base = BATu & ~0x0001FFFF;
870 end = base + mask + 0x00020000;
871#if defined (DEBUG_BATS)
76a66253 872 if (loglevel != 0) {
1b9eb036 873 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
76a66253
JM		 874 base, end, mask);
875 }
3fc6c082
FB		 876#endif
877 for (page = base; page != end; page += TARGET_PAGE_SIZE)
878 tlb_flush_page(env, page);
879#if defined (DEBUG_BATS)
880 if (loglevel != 0)
881 fprintf(logfile, "Flush done\n");
882#endif
883}
884#endif
885
886static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
887 target_ulong value)
888{
889#if defined (DEBUG_BATS)
890 if (loglevel != 0) {
1b9eb036
JM		 891 fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
892 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
3fc6c082
FB		 893 }
894#endif
895}
896
897target_ulong do_load_ibatu (CPUPPCState *env, int nr)
898{
899 return env->IBAT[0][nr];
900}
901
902target_ulong do_load_ibatl (CPUPPCState *env, int nr)
903{
904 return env->IBAT[1][nr];
905}
906
907void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
908{
909 target_ulong mask;
910
911 dump_store_bat(env, 'I', 0, nr, value);
912 if (env->IBAT[0][nr] != value) {
913 mask = (value << 15) & 0x0FFE0000UL;
914#if !defined(FLUSH_ALL_TLBS)
915 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
916#endif
917 /* When storing valid upper BAT, mask BEPI and BRPN
918 * and invalidate all TLBs covered by this BAT
919 */
920 mask = (value << 15) & 0x0FFE0000UL;
921 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
922 (value & ~0x0001FFFFUL & ~mask);
923 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
924 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
925#if !defined(FLUSH_ALL_TLBS)
926 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
76a66253 927#else
3fc6c082
FB		 928 tlb_flush(env, 1);
929#endif
930 }
931}
932
933void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
934{
935 dump_store_bat(env, 'I', 1, nr, value);
936 env->IBAT[1][nr] = value;
937}
938
939target_ulong do_load_dbatu (CPUPPCState *env, int nr)
940{
941 return env->DBAT[0][nr];
942}
943
944target_ulong do_load_dbatl (CPUPPCState *env, int nr)
945{
946 return env->DBAT[1][nr];
947}
948
949void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
950{
951 target_ulong mask;
952
953 dump_store_bat(env, 'D', 0, nr, value);
954 if (env->DBAT[0][nr] != value) {
955 /* When storing valid upper BAT, mask BEPI and BRPN
956 * and invalidate all TLBs covered by this BAT
957 */
958 mask = (value << 15) & 0x0FFE0000UL;
959#if !defined(FLUSH_ALL_TLBS)
960 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
961#endif
962 mask = (value << 15) & 0x0FFE0000UL;
963 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
964 (value & ~0x0001FFFFUL & ~mask);
965 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
966 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
967#if !defined(FLUSH_ALL_TLBS)
968 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
969#else
970 tlb_flush(env, 1);
971#endif
972 }
973}
974
975void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
976{
977 dump_store_bat(env, 'D', 1, nr, value);
978 env->DBAT[1][nr] = value;
979}
980
3fc6c082
FB		 981/*****************************************************************************/
982/* Special registers manipulation */
d9bce9d9
JM		 983#if defined(TARGET_PPC64)
984target_ulong ppc_load_asr (CPUPPCState *env)
985{
986 return env->asr;
987}
988
989void ppc_store_asr (CPUPPCState *env, target_ulong value)
990{
991 if (env->asr != value) {
992 env->asr = value;
993 tlb_flush(env, 1);
994 }
995}
996#endif
997
3fc6c082
FB		 998target_ulong do_load_sdr1 (CPUPPCState *env)
999{
1000 return env->sdr1;
1001}
1002
1003void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1004{
1005#if defined (DEBUG_MMU)
1006 if (loglevel != 0) {
1b9eb036 1007 fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
3fc6c082
FB		 1008 }
1009#endif
1010 if (env->sdr1 != value) {
1011 env->sdr1 = value;
76a66253 1012 tlb_flush(env, 1);
3fc6c082
FB		 1013 }
1014}
1015
1016target_ulong do_load_sr (CPUPPCState *env, int srnum)
1017{
1018 return env->sr[srnum];
1019}
1020
1021void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1022{
1023#if defined (DEBUG_MMU)
1024 if (loglevel != 0) {
1b9eb036
JM		 1025 fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1026 __func__, srnum, value, env->sr[srnum]);
3fc6c082
FB		 1027 }
1028#endif
1029 if (env->sr[srnum] != value) {
1030 env->sr[srnum] = value;
1031#if !defined(FLUSH_ALL_TLBS) && 0
1032 {
1033 target_ulong page, end;
1034 /* Invalidate 256 MB of virtual memory */
1035 page = (16 << 20) * srnum;
1036 end = page + (16 << 20);
1037 for (; page != end; page += TARGET_PAGE_SIZE)
1038 tlb_flush_page(env, page);
1039 }
1040#else
76a66253 1041 tlb_flush(env, 1);
3fc6c082
FB		 1042#endif
1043 }
1044}
76a66253 1045#endif /* !defined (CONFIG_USER_ONLY) */
3fc6c082 1046
76a66253 1047uint32_t ppc_load_xer (CPUPPCState *env)
79aceca5
FB		 1048{
1049 return (xer_so << XER_SO) |
1050 (xer_ov << XER_OV) |
1051 (xer_ca << XER_CA) |
3fc6c082
FB		 1052 (xer_bc << XER_BC) |
1053 (xer_cmp << XER_CMP);
79aceca5
FB		 1054}
1055
76a66253 1056void ppc_store_xer (CPUPPCState *env, uint32_t value)
79aceca5
FB		 1057{
1058 xer_so = (value >> XER_SO) & 0x01;
1059 xer_ov = (value >> XER_OV) & 0x01;
1060 xer_ca = (value >> XER_CA) & 0x01;
3fc6c082 1061 xer_cmp = (value >> XER_CMP) & 0xFF;
d9bce9d9 1062 xer_bc = (value >> XER_BC) & 0x7F;
79aceca5
FB		 1063}
1064
76a66253
JM		 1065/* Swap temporary saved registers with GPRs */
1066static inline void swap_gpr_tgpr (CPUPPCState *env)
79aceca5 1067{
76a66253
JM		 1068 ppc_gpr_t tmp;
1069
1070 tmp = env->gpr[0];
1071 env->gpr[0] = env->tgpr[0];
1072 env->tgpr[0] = tmp;
1073 tmp = env->gpr[1];
1074 env->gpr[1] = env->tgpr[1];
1075 env->tgpr[1] = tmp;
1076 tmp = env->gpr[2];
1077 env->gpr[2] = env->tgpr[2];
1078 env->tgpr[2] = tmp;
1079 tmp = env->gpr[3];
1080 env->gpr[3] = env->tgpr[3];
1081 env->tgpr[3] = tmp;
79aceca5
FB		 1082}
1083
76a66253
JM		 1084/* GDBstub can read and write MSR... */
1085target_ulong do_load_msr (CPUPPCState *env)
79aceca5 1086{
76a66253
JM		 1087 return
1088#if defined (TARGET_PPC64)
d9bce9d9
JM		 1089 ((target_ulong)msr_sf << MSR_SF) |
1090 ((target_ulong)msr_isf << MSR_ISF) |
1091 ((target_ulong)msr_hv << MSR_HV) |
76a66253 1092#endif
d9bce9d9
JM		 1093 ((target_ulong)msr_ucle << MSR_UCLE) |
1094 ((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
1095 ((target_ulong)msr_ap << MSR_AP) |
1096 ((target_ulong)msr_sa << MSR_SA) |
1097 ((target_ulong)msr_key << MSR_KEY) |
1098 ((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
1099 ((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
1100 ((target_ulong)msr_ile << MSR_ILE) |
1101 ((target_ulong)msr_ee << MSR_EE) |
1102 ((target_ulong)msr_pr << MSR_PR) |
1103 ((target_ulong)msr_fp << MSR_FP) |
1104 ((target_ulong)msr_me << MSR_ME) |
1105 ((target_ulong)msr_fe0 << MSR_FE0) |
1106 ((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
1107 ((target_ulong)msr_be << MSR_BE) | /* BE / DE */
1108 ((target_ulong)msr_fe1 << MSR_FE1) |
1109 ((target_ulong)msr_al << MSR_AL) |
1110 ((target_ulong)msr_ip << MSR_IP) |
1111 ((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
1112 ((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
1113 ((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
1114 ((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
1115 ((target_ulong)msr_ri << MSR_RI) |
1116 ((target_ulong)msr_le << MSR_LE);
3fc6c082
FB		 1117}
1118
1119void do_store_msr (CPUPPCState *env, target_ulong value)
313adae9 1120{
50443c98
FB		 1121 int enter_pm;
1122
3fc6c082
FB		 1123 value &= env->msr_mask;
1124 if (((value >> MSR_IR) & 1) != msr_ir ||
1125 ((value >> MSR_DR) & 1) != msr_dr) {
76a66253 1126 /* Flush all tlb when changing translation mode */
d094807b 1127 tlb_flush(env, 1);
3fc6c082 1128 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
a541f297 1129 }
3fc6c082
FB		 1130#if 0
1131 if (loglevel != 0) {
1132 fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1133 }
1134#endif
76a66253
JM		 1135 switch (PPC_EXCP(env)) {
1136 case PPC_FLAGS_EXCP_602:
1137 case PPC_FLAGS_EXCP_603:
1138 if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1139 /* Swap temporary saved registers with GPRs */
1140 swap_gpr_tgpr(env);
1141 }
1142 break;
1143 default:
1144 break;
1145 }
1146#if defined (TARGET_PPC64)
1147 msr_sf = (value >> MSR_SF) & 1;
1148 msr_isf = (value >> MSR_ISF) & 1;
1149 msr_hv = (value >> MSR_HV) & 1;
1150#endif
1151 msr_ucle = (value >> MSR_UCLE) & 1;
1152 msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
1153 msr_ap = (value >> MSR_AP) & 1;
1154 msr_sa = (value >> MSR_SA) & 1;
1155 msr_key = (value >> MSR_KEY) & 1;
1156 msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
1157 msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
1158 msr_ile = (value >> MSR_ILE) & 1;
1159 msr_ee = (value >> MSR_EE) & 1;
1160 msr_pr = (value >> MSR_PR) & 1;
1161 msr_fp = (value >> MSR_FP) & 1;
1162 msr_me = (value >> MSR_ME) & 1;
1163 msr_fe0 = (value >> MSR_FE0) & 1;
1164 msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
1165 msr_be = (value >> MSR_BE) & 1; /* BE / DE */
1166 msr_fe1 = (value >> MSR_FE1) & 1;
1167 msr_al = (value >> MSR_AL) & 1;
1168 msr_ip = (value >> MSR_IP) & 1;
1169 msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
1170 msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
1171 msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
1172 msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
1173 msr_ri = (value >> MSR_RI) & 1;
1174 msr_le = (value >> MSR_LE) & 1;
3fc6c082 1175 do_compute_hflags(env);
50443c98
FB		 1176
1177 enter_pm = 0;
1178 switch (PPC_EXCP(env)) {
d9bce9d9
JM		 1179 case PPC_FLAGS_EXCP_603:
1180 /* Don't handle SLEEP mode: we should disable all clocks...
1181 * No dynamic power-management.
1182 */
1183 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1184 enter_pm = 1;
1185 break;
1186 case PPC_FLAGS_EXCP_604:
1187 if (msr_pow == 1)
1188 enter_pm = 1;
1189 break;
50443c98 1190 case PPC_FLAGS_EXCP_7x0:
76a66253 1191 if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
50443c98
FB		 1192 enter_pm = 1;
1193 break;
1194 default:
1195 break;
1196 }
1197 if (enter_pm) {
e80e1cc4 1198 /* power save: exit cpu loop */
50443c98 1199 env->halted = 1;
e80e1cc4
FB		 1200 env->exception_index = EXCP_HLT;
1201 cpu_loop_exit();
1202 }
3fc6c082
FB		 1203}
1204
d9bce9d9 1205#if defined(TARGET_PPC64)
426613db 1206void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
d9bce9d9 1207{
426613db
JM		 1208 do_store_msr(env,
1209 (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
d9bce9d9
JM		 1210}
1211#endif
1212
76a66253 1213void do_compute_hflags (CPUPPCState *env)
3fc6c082 1214{
76a66253
JM		 1215 /* Compute current hflags */
1216 env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |
1217 (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |
d9bce9d9 1218 (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
76a66253
JM		 1219 (msr_se << MSR_SE) | (msr_be << MSR_BE);
1220#if defined (TARGET_PPC64)
d9bce9d9 1221 env->hflags |= (msr_sf << (MSR_SF - 32)) | (msr_hv << (MSR_HV - 32));
4b3686fa 1222#endif
3fc6c082
FB		 1223}
1224
1225/*****************************************************************************/
1226/* Exception processing */
18fba28c 1227#if defined (CONFIG_USER_ONLY)
9a64fbe4 1228void do_interrupt (CPUState *env)
79aceca5 1229{
18fba28c
FB		 1230 env->exception_index = -1;
1231}
76a66253 1232#else /* defined (CONFIG_USER_ONLY) */
d094807b
FB		 1233static void dump_syscall(CPUState *env)
1234{
d9bce9d9 1235 fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1b9eb036 1236 " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
d094807b
FB		 1237 env->gpr[0], env->gpr[3], env->gpr[4],
1238 env->gpr[5], env->gpr[6], env->nip);
1239}
1240
18fba28c
FB		 1241void do_interrupt (CPUState *env)
1242{
76a66253 1243 target_ulong msr, *srr_0, *srr_1;
18fba28c 1244 int excp;
79aceca5 1245
18fba28c 1246 excp = env->exception_index;
3fc6c082 1247 msr = do_load_msr(env);
2be0071f
FB		 1248 /* The default is to use SRR0 & SRR1 to save the exception context */
1249 srr_0 = &env->spr[SPR_SRR0];
1250 srr_1 = &env->spr[SPR_SRR1];
9a64fbe4 1251#if defined (DEBUG_EXCEPTIONS)
2be0071f
FB		 1252 if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1) {
1253 if (loglevel != 0) {
1b9eb036
JM		 1254 fprintf(logfile,
1255 "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1256 env->nip, excp, env->error_code);
76a66253 1257 cpu_dump_state(env, logfile, fprintf, 0);
b769d8fe 1258 }
79aceca5 1259 }
9a64fbe4 1260#endif
b769d8fe 1261 if (loglevel & CPU_LOG_INT) {
1b9eb036
JM		 1262 fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1263 env->nip, excp, env->error_code);
b769d8fe 1264 }
2be0071f 1265 msr_pow = 0;
9a64fbe4
FB		 1266 /* Generate informations in save/restore registers */
1267 switch (excp) {
76a66253 1268 /* Generic PowerPC exceptions */
2be0071f
FB		 1269 case EXCP_RESET: /* 0x0100 */
1270 if (PPC_EXCP(env) != PPC_FLAGS_EXCP_40x) {
1271 if (msr_ip)
1272 excp += 0xFFC00;
1273 excp |= 0xFFC00000;
1274 } else {
1275 srr_0 = &env->spr[SPR_40x_SRR2];
1276 srr_1 = &env->spr[SPR_40x_SRR3];
1277 }
9a64fbe4 1278 goto store_next;
2be0071f 1279 case EXCP_MACHINE_CHECK: /* 0x0200 */
9a64fbe4 1280 if (msr_me == 0) {
4b3686fa 1281 cpu_abort(env, "Machine check exception while not allowed\n");
79aceca5 1282 }
76a66253 1283 if (unlikely(PPC_EXCP(env) == PPC_FLAGS_EXCP_40x)) {
2be0071f
FB		 1284 srr_0 = &env->spr[SPR_40x_SRR2];
1285 srr_1 = &env->spr[SPR_40x_SRR3];
1286 }
9a64fbe4
FB		 1287 msr_me = 0;
1288 break;
2be0071f 1289 case EXCP_DSI: /* 0x0300 */
9a64fbe4
FB		 1290 /* Store exception cause */
1291 /* data location address has been stored
1292 * when the fault has been detected
2be0071f 1293 */
76a66253 1294 msr &= ~0xFFFF0000;
a541f297 1295#if defined (DEBUG_EXCEPTIONS)
76a66253 1296 if (loglevel) {
1b9eb036
JM		 1297 fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
1298 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
76a66253 1299 } else {
1b9eb036 1300 printf("DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX "\n",
76a66253
JM		 1301 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1302 }
a541f297
FB		 1303#endif
1304 goto store_next;
2be0071f 1305 case EXCP_ISI: /* 0x0400 */
9a64fbe4 1306 /* Store exception cause */
76a66253 1307 msr &= ~0xFFFF0000;
2be0071f 1308 msr |= env->error_code;
a541f297 1309#if defined (DEBUG_EXCEPTIONS)
76a66253 1310 if (loglevel != 0) {
1b9eb036
JM		 1311 fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
1312 "\n", msr, env->nip);
76a66253 1313 }
a541f297 1314#endif
9a64fbe4 1315 goto store_next;
2be0071f 1316 case EXCP_EXTERNAL: /* 0x0500 */
9a64fbe4
FB		 1317 if (msr_ee == 0) {
1318#if defined (DEBUG_EXCEPTIONS)
1319 if (loglevel > 0) {
1320 fprintf(logfile, "Skipping hardware interrupt\n");
2be0071f 1321 }
9a64fbe4 1322#endif
a541f297 1323 /* Requeue it */
2be0071f 1324 env->interrupt_request |= CPU_INTERRUPT_HARD;
9a64fbe4 1325 return;
2be0071f 1326 }
9a64fbe4 1327 goto store_next;
2be0071f 1328 case EXCP_ALIGN: /* 0x0600 */
76a66253 1329 if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
2be0071f
FB		 1330 /* Store exception cause */
1331 /* Get rS/rD and rA from faulting opcode */
1332 env->spr[SPR_DSISR] |=
1333 (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
1334 /* data location address has been stored
1335 * when the fault has been detected
1336 */
1337 } else {
1338 /* IO error exception on PowerPC 601 */
1339 /* XXX: TODO */
1340 cpu_abort(env,
1341 "601 IO error exception is not implemented yet !\n");
1342 }
9a64fbe4 1343 goto store_current;
2be0071f 1344 case EXCP_PROGRAM: /* 0x0700 */
9a64fbe4
FB		 1345 msr &= ~0xFFFF0000;
1346 switch (env->error_code & ~0xF) {
1347 case EXCP_FP:
1348 if (msr_fe0 == 0 && msr_fe1 == 0) {
1349#if defined (DEBUG_EXCEPTIONS)
1350 printf("Ignore floating point exception\n");
1351#endif
1352 return;
76a66253 1353 }
9a64fbe4
FB		 1354 msr |= 0x00100000;
1355 /* Set FX */
1356 env->fpscr[7] |= 0x8;
1357 /* Finally, update FEX */
1358 if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
1359 ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
1360 env->fpscr[7] |= 0x4;
76a66253 1361 break;
9a64fbe4 1362 case EXCP_INVAL:
1b9eb036 1363 // printf("Invalid instruction at 0x" ADDRX "\n", env->nip);
9a64fbe4 1364 msr |= 0x00080000;
76a66253 1365 break;
9a64fbe4
FB		 1366 case EXCP_PRIV:
1367 msr |= 0x00040000;
76a66253 1368 break;
9a64fbe4
FB		 1369 case EXCP_TRAP:
1370 msr |= 0x00020000;
1371 break;
1372 default:
1373 /* Should never occur */
76a66253
JM		 1374 break;
1375 }
9a64fbe4
FB		 1376 msr |= 0x00010000;
1377 goto store_current;
2be0071f 1378 case EXCP_NO_FP: /* 0x0800 */
4ecc3190 1379 msr &= ~0xFFFF0000;
9a64fbe4
FB		 1380 goto store_current;
1381 case EXCP_DECR:
1382 if (msr_ee == 0) {
2be0071f 1383#if 1
9a64fbe4 1384 /* Requeue it */
2be0071f
FB		 1385 env->interrupt_request |= CPU_INTERRUPT_TIMER;
1386#endif
9a64fbe4
FB		 1387 return;
1388 }
1389 goto store_next;
2be0071f 1390 case EXCP_SYSCALL: /* 0x0C00 */
d094807b
FB		 1391 /* NOTE: this is a temporary hack to support graphics OSI
1392 calls from the MOL driver */
1393 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
1394 env->osi_call) {
1395 if (env->osi_call(env) != 0)
1396 return;
1397 }
b769d8fe 1398 if (loglevel & CPU_LOG_INT) {
d094807b 1399 dump_syscall(env);
b769d8fe 1400 }
9a64fbe4 1401 goto store_next;
2be0071f 1402 case EXCP_TRACE: /* 0x0D00 */
2be0071f
FB		 1403 goto store_next;
1404 case EXCP_PERF: /* 0x0F00 */
1405 /* XXX: TODO */
1406 cpu_abort(env,
1407 "Performance counter exception is not implemented yet !\n");
1408 goto store_next;
1409 /* 32 bits PowerPC specific exceptions */
1410 case EXCP_FP_ASSIST: /* 0x0E00 */
1411 /* XXX: TODO */
1412 cpu_abort(env, "Floating point assist exception "
1413 "is not implemented yet !\n");
1414 goto store_next;
76a66253 1415 /* 64 bits PowerPC exceptions */
2be0071f
FB		 1416 case EXCP_DSEG: /* 0x0380 */
1417 /* XXX: TODO */
1418 cpu_abort(env, "Data segment exception is not implemented yet !\n");
9a64fbe4 1419 goto store_next;
2be0071f
FB		 1420 case EXCP_ISEG: /* 0x0480 */
1421 /* XXX: TODO */
1422 cpu_abort(env,
1423 "Instruction segment exception is not implemented yet !\n");
9a64fbe4 1424 goto store_next;
2be0071f
FB		 1425 case EXCP_HDECR: /* 0x0980 */
1426 if (msr_ee == 0) {
1427#if 1
1428 /* Requeue it */
1429 env->interrupt_request |= CPU_INTERRUPT_TIMER;
1430#endif
76a66253 1431 return;
2be0071f 1432 }
76a66253
JM		 1433 /* XXX: TODO */
1434 cpu_abort(env, "Hypervisor decrementer exception is not implemented "
1435 "yet !\n");
2be0071f
FB		 1436 goto store_next;
1437 /* Implementation specific exceptions */
1438 case 0x0A00:
76a66253
JM		 1439 if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
1440 env->spr[SPR_PVR] == CPU_PPC_G2LE)) {
2be0071f
FB		 1441 /* Critical interrupt on G2 */
1442 /* XXX: TODO */
1443 cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
1444 goto store_next;
1445 } else {
1446 cpu_abort(env, "Invalid exception 0x0A00 !\n");
1447 }
9a64fbe4 1448 return;
2be0071f
FB		 1449 case 0x0F20:
1450 switch (PPC_EXCP(env)) {
1451 case PPC_FLAGS_EXCP_40x:
1452 /* APU unavailable on 405 */
1453 /* XXX: TODO */
1454 cpu_abort(env,
1455 "APU unavailable exception is not implemented yet !\n");
1456 goto store_next;
1457 case PPC_FLAGS_EXCP_74xx:
1458 /* Altivec unavailable */
1459 /* XXX: TODO */
1460 cpu_abort(env, "Altivec unavailable exception "
1461 "is not implemented yet !\n");
1462 goto store_next;
1463 default:
1464 cpu_abort(env, "Invalid exception 0x0F20 !\n");
1465 break;
1466 }
1467 return;
1468 case 0x1000:
1469 switch (PPC_EXCP(env)) {
1470 case PPC_FLAGS_EXCP_40x:
1471 /* PIT on 4xx */
1472 /* XXX: TODO */
1473 cpu_abort(env, "40x PIT exception is not implemented yet !\n");
1474 goto store_next;
1475 case PPC_FLAGS_EXCP_602:
1476 case PPC_FLAGS_EXCP_603:
1477 /* ITLBMISS on 602/603 */
2be0071f 1478 goto store_gprs;
76a66253
JM		 1479 case PPC_FLAGS_EXCP_7x5:
1480 /* ITLBMISS on 745/755 */
1481 goto tlb_miss;
2be0071f
FB		 1482 default:
1483 cpu_abort(env, "Invalid exception 0x1000 !\n");
1484 break;
1485 }
1486 return;
1487 case 0x1010:
1488 switch (PPC_EXCP(env)) {
1489 case PPC_FLAGS_EXCP_40x:
1490 /* FIT on 4xx */
2be0071f 1491 /* XXX: TODO */
76a66253 1492 cpu_abort(env, "40x FIT exception is not implemented yet !\n");
2be0071f
FB		 1493 goto store_next;
1494 default:
1495 cpu_abort(env, "Invalid exception 0x1010 !\n");
1496 break;
1497 }
1498 return;
1499 case 0x1020:
1500 switch (PPC_EXCP(env)) {
1501 case PPC_FLAGS_EXCP_40x:
1502 /* Watchdog on 4xx */
1503 /* XXX: TODO */
1504 cpu_abort(env,
1505 "40x watchdog exception is not implemented yet !\n");
1506 goto store_next;
1507 default:
1508 cpu_abort(env, "Invalid exception 0x1020 !\n");
1509 break;
1510 }
1511 return;
1512 case 0x1100:
1513 switch (PPC_EXCP(env)) {
1514 case PPC_FLAGS_EXCP_40x:
1515 /* DTLBMISS on 4xx */
1516 /* XXX: TODO */
1517 cpu_abort(env,
1518 "40x DTLBMISS exception is not implemented yet !\n");
1519 goto store_next;
1520 case PPC_FLAGS_EXCP_602:
1521 case PPC_FLAGS_EXCP_603:
1522 /* DLTLBMISS on 602/603 */
2be0071f 1523 goto store_gprs;
76a66253
JM		 1524 case PPC_FLAGS_EXCP_7x5:
1525 /* DLTLBMISS on 745/755 */
1526 goto tlb_miss;
2be0071f
FB		 1527 default:
1528 cpu_abort(env, "Invalid exception 0x1100 !\n");
1529 break;
1530 }
1531 return;
1532 case 0x1200:
1533 switch (PPC_EXCP(env)) {
1534 case PPC_FLAGS_EXCP_40x:
1535 /* ITLBMISS on 4xx */
1536 /* XXX: TODO */
1537 cpu_abort(env,
1538 "40x ITLBMISS exception is not implemented yet !\n");
1539 goto store_next;
1540 case PPC_FLAGS_EXCP_602:
1541 case PPC_FLAGS_EXCP_603:
1542 /* DSTLBMISS on 602/603 */
2be0071f 1543 store_gprs:
76a66253
JM		 1544 /* Swap temporary saved registers with GPRs */
1545 swap_gpr_tgpr(env);
1546 msr_tgpr = 1;
2be0071f
FB		 1547#if defined (DEBUG_SOFTWARE_TLB)
1548 if (loglevel != 0) {
76a66253
JM		 1549 const unsigned char *es;
1550 target_ulong *miss, *cmp;
1551 int en;
1552 if (excp == 0x1000) {
1553 es = "I";
1554 en = 'I';
1555 miss = &env->spr[SPR_IMISS];
1556 cmp = &env->spr[SPR_ICMP];
1557 } else {
1558 if (excp == 0x1100)
1559 es = "DL";
1560 else
1561 es = "DS";
1562 en = 'D';
1563 miss = &env->spr[SPR_DMISS];
1564 cmp = &env->spr[SPR_DCMP];
1565 }
1b9eb036
JM		 1566 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
1567 " H1 " ADDRX " H2 " ADDRX " " ADDRX "\n",
1568 es, en, *miss, en, *cmp,
76a66253 1569 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2be0071f
FB		 1570 env->error_code);
1571 }
9a64fbe4 1572#endif
76a66253
JM		 1573 goto tlb_miss;
1574 case PPC_FLAGS_EXCP_7x5:
1575 /* DSTLBMISS on 745/755 */
1576 tlb_miss:
1577 msr &= ~0xF83F0000;
2be0071f
FB		 1578 msr |= env->crf[0] << 28;
1579 msr |= env->error_code; /* key, D/I, S/L bits */
1580 /* Set way using a LRU mechanism */
76a66253 1581 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2be0071f
FB		 1582 goto store_next;
1583 default:
1584 cpu_abort(env, "Invalid exception 0x1200 !\n");
1585 break;
1586 }
1587 return;
1588 case 0x1300:
1589 switch (PPC_EXCP(env)) {
1590 case PPC_FLAGS_EXCP_601:
1591 case PPC_FLAGS_EXCP_602:
1592 case PPC_FLAGS_EXCP_603:
1593 case PPC_FLAGS_EXCP_604:
1594 case PPC_FLAGS_EXCP_7x0:
1595 case PPC_FLAGS_EXCP_7x5:
1596 /* IABR on 6xx/7xx */
1597 /* XXX: TODO */
1598 cpu_abort(env, "IABR exception is not implemented yet !\n");
1599 goto store_next;
1600 default:
1601 cpu_abort(env, "Invalid exception 0x1300 !\n");
1602 break;
1603 }
1604 return;
1605 case 0x1400:
1606 switch (PPC_EXCP(env)) {
1607 case PPC_FLAGS_EXCP_601:
1608 case PPC_FLAGS_EXCP_602:
1609 case PPC_FLAGS_EXCP_603:
1610 case PPC_FLAGS_EXCP_604:
1611 case PPC_FLAGS_EXCP_7x0:
1612 case PPC_FLAGS_EXCP_7x5:
1613 /* SMI on 6xx/7xx */
1614 /* XXX: TODO */
1615 cpu_abort(env, "SMI exception is not implemented yet !\n");
1616 goto store_next;
1617 default:
1618 cpu_abort(env, "Invalid exception 0x1400 !\n");
1619 break;
1620 }
1621 return;
1622 case 0x1500:
1623 switch (PPC_EXCP(env)) {
1624 case PPC_FLAGS_EXCP_602:
1625 /* Watchdog on 602 */
76a66253 1626 /* XXX: TODO */
2be0071f
FB		 1627 cpu_abort(env,
1628 "602 watchdog exception is not implemented yet !\n");
1629 goto store_next;
1630 case PPC_FLAGS_EXCP_970:
1631 /* Soft patch exception on 970 */
1632 /* XXX: TODO */
1633 cpu_abort(env,
1634 "970 soft-patch exception is not implemented yet !\n");
1635 goto store_next;
1636 case PPC_FLAGS_EXCP_74xx:
1637 /* VPU assist on 74xx */
1638 /* XXX: TODO */
1639 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
1640 goto store_next;
1641 default:
1642 cpu_abort(env, "Invalid exception 0x1500 !\n");
1643 break;
1644 }
1645 return;
1646 case 0x1600:
1647 switch (PPC_EXCP(env)) {
1648 case PPC_FLAGS_EXCP_602:
1649 /* Emulation trap on 602 */
1650 /* XXX: TODO */
1651 cpu_abort(env, "602 emulation trap exception "
1652 "is not implemented yet !\n");
1653 goto store_next;
1654 case PPC_FLAGS_EXCP_970:
1655 /* Maintenance exception on 970 */
1656 /* XXX: TODO */
1657 cpu_abort(env,
1658 "970 maintenance exception is not implemented yet !\n");
1659 goto store_next;
1660 default:
1661 cpu_abort(env, "Invalid exception 0x1600 !\n");
1662 break;
1663 }
1664 return;
1665 case 0x1700:
1666 switch (PPC_EXCP(env)) {
1667 case PPC_FLAGS_EXCP_7x0:
1668 case PPC_FLAGS_EXCP_7x5:
1669 /* Thermal management interrupt on G3 */
1670 /* XXX: TODO */
1671 cpu_abort(env, "G3 thermal management exception "
1672 "is not implemented yet !\n");
1673 goto store_next;
1674 case PPC_FLAGS_EXCP_970:
1675 /* VPU assist on 970 */
1676 /* XXX: TODO */
1677 cpu_abort(env,
1678 "970 VPU assist exception is not implemented yet !\n");
1679 goto store_next;
1680 default:
1681 cpu_abort(env, "Invalid exception 0x1700 !\n");
1682 break;
1683 }
1684 return;
1685 case 0x1800:
1686 switch (PPC_EXCP(env)) {
1687 case PPC_FLAGS_EXCP_970:
1688 /* Thermal exception on 970 */
1689 /* XXX: TODO */
1690 cpu_abort(env, "970 thermal management exception "
1691 "is not implemented yet !\n");
1692 goto store_next;
1693 default:
1694 cpu_abort(env, "Invalid exception 0x1800 !\n");
1695 break;
1696 }
1697 return;
1698 case 0x2000:
1699 switch (PPC_EXCP(env)) {
1700 case PPC_FLAGS_EXCP_40x:
1701 /* DEBUG on 4xx */
1702 /* XXX: TODO */
1703 cpu_abort(env, "40x debug exception is not implemented yet !\n");
1704 goto store_next;
1705 case PPC_FLAGS_EXCP_601:
1706 /* Run mode exception on 601 */
1707 /* XXX: TODO */
1708 cpu_abort(env,
1709 "601 run mode exception is not implemented yet !\n");
1710 goto store_next;
1711 default:
1712 cpu_abort(env, "Invalid exception 0x1800 !\n");
1713 break;
1714 }
1715 return;
1716 /* Other exceptions */
1717 /* Qemu internal exceptions:
1718 * we should never come here with those values: abort execution
1719 */
1720 default:
1721 cpu_abort(env, "Invalid exception: code %d (%04x)\n", excp, excp);
9a64fbe4
FB		 1722 return;
1723 store_current:
2be0071f
FB		 1724 /* save current instruction location */
1725 *srr_0 = (env->nip - 4) & 0xFFFFFFFFULL;
9a64fbe4
FB		 1726 break;
1727 store_next:
2be0071f
FB		 1728 /* save next instruction location */
1729 *srr_0 = env->nip & 0xFFFFFFFFULL;
9a64fbe4
FB		 1730 break;
1731 }
2be0071f
FB		 1732 /* Save msr */
1733 *srr_1 = msr;
1734 /* If we disactivated any translation, flush TLBs */
1735 if (msr_ir || msr_dr) {
1736 tlb_flush(env, 1);
1737 }
9a64fbe4 1738 /* reload MSR with correct bits */
9a64fbe4
FB		 1739 msr_ee = 0;
1740 msr_pr = 0;
1741 msr_fp = 0;
1742 msr_fe0 = 0;
1743 msr_se = 0;
1744 msr_be = 0;
1745 msr_fe1 = 0;
1746 msr_ir = 0;
1747 msr_dr = 0;
1748 msr_ri = 0;
1749 msr_le = msr_ile;
2be0071f 1750 msr_sf = msr_isf;
3fc6c082 1751 do_compute_hflags(env);
9a64fbe4 1752 /* Jump to handler */
2be0071f 1753 env->nip = excp;
9a64fbe4 1754 env->exception_index = EXCP_NONE;
fb0eaffc 1755}
18fba28c 1756#endif /* !CONFIG_USER_ONLY */
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