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1/*
2 * PPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include "exec.h"
21
22extern FILE *logfile;
23
24void cpu_loop_exit(void)
25{
26 longjmp(env->jmp_env, 1);
27}
28
29/* shortcuts to generate exceptions */
30void raise_exception_err (int exception_index, int error_code)
31{
32 env->exception_index = exception_index;
33 env->error_code = error_code;
34
35 cpu_loop_exit();
36}
37
38void raise_exception (int exception_index)
39{
40 env->exception_index = exception_index;
41 env->error_code = 0;
42
43 cpu_loop_exit();
44}
45
46/* Helpers for "fat" micro operations */
47uint32_t do_load_cr (void)
48{
49 return (env->crf[0] << 28) |
50 (env->crf[1] << 24) |
51 (env->crf[2] << 20) |
52 (env->crf[3] << 16) |
53 (env->crf[4] << 12) |
54 (env->crf[5] << 8) |
55 (env->crf[6] << 4) |
56 (env->crf[7] << 0);
57}
58
59void do_store_cr (uint32_t crn, uint32_t value)
60{
61 int i, sh;
62
63 for (i = 0, sh = 7; i < 8; i++, sh --) {
64 if (crn & (1 << sh))
65 env->crf[i] = (value >> (sh * 4)) & 0xF;
66 }
67}
68
69uint32_t do_load_xer (void)
70{
71 return (xer_so << XER_SO) |
72 (xer_ov << XER_OV) |
73 (xer_ca << XER_CA) |
74 (xer_bc << XER_BC);
75}
76
77void do_store_xer (uint32_t value)
78{
79 xer_so = (value >> XER_SO) & 0x01;
80 xer_ov = (value >> XER_OV) & 0x01;
81 xer_ca = (value >> XER_CA) & 0x01;
82 xer_bc = (value >> XER_BC) & 0x1f;
83}
84
85uint32_t do_load_msr (void)
86{
87 return (msr_pow << MSR_POW) |
88 (msr_ile << MSR_ILE) |
89 (msr_ee << MSR_EE) |
90 (msr_pr << MSR_PR) |
91 (msr_fp << MSR_FP) |
92 (msr_me << MSR_ME) |
93 (msr_fe0 << MSR_FE0) |
94 (msr_se << MSR_SE) |
95 (msr_be << MSR_BE) |
96 (msr_fe1 << MSR_FE1) |
97 (msr_ip << MSR_IP) |
98 (msr_ir << MSR_IR) |
99 (msr_dr << MSR_DR) |
100 (msr_ri << MSR_RI) |
101 (msr_le << MSR_LE);
102}
103
104void do_store_msr (uint32_t msr_value)
105{
106 msr_pow = (msr_value >> MSR_POW) & 0x03;
107 msr_ile = (msr_value >> MSR_ILE) & 0x01;
108 msr_ee = (msr_value >> MSR_EE) & 0x01;
109 msr_pr = (msr_value >> MSR_PR) & 0x01;
110 msr_fp = (msr_value >> MSR_FP) & 0x01;
111 msr_me = (msr_value >> MSR_ME) & 0x01;
112 msr_fe0 = (msr_value >> MSR_FE0) & 0x01;
113 msr_se = (msr_value >> MSR_SE) & 0x01;
114 msr_be = (msr_value >> MSR_BE) & 0x01;
115 msr_fe1 = (msr_value >> MSR_FE1) & 0x01;
116 msr_ip = (msr_value >> MSR_IP) & 0x01;
117 msr_ir = (msr_value >> MSR_IR) & 0x01;
118 msr_dr = (msr_value >> MSR_DR) & 0x01;
119 msr_ri = (msr_value >> MSR_RI) & 0x01;
120 msr_le = (msr_value >> MSR_LE) & 0x01;
121}
122
123/* The 32 MSB of the target fpr are undefined. They'll be zero... */
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124/* Floating point operations helpers */
125void do_load_fpscr (void)
79aceca5 126{
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127 /* The 32 MSB of the target fpr are undefined.
128 * They'll be zero...
129 */
130 union {
131 double d;
132 struct {
133 uint32_t u[2];
134 } s;
135 } u;
136 int i;
137
138 u.s.u[0] = 0;
139 u.s.u[1] = 0;
140 for (i = 0; i < 8; i++)
141 u.s.u[1] |= env->fpscr[i] << (4 * i);
142 FT0 = u.d;
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143}
144
fb0eaffc 145void do_store_fpscr (uint32_t mask)
79aceca5 146{
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147 /*
148 * We use only the 32 LSB of the incoming fpr
149 */
150 union {
151 double d;
152 struct {
153 uint32_t u[2];
154 } s;
155 } u;
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156 int i;
157
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158 u.d = FT0;
159 if (mask & 0x80)
160 env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[1] >> 28) & ~0x9);
161 for (i = 1; i < 7; i++) {
162 if (mask & (1 << (7 - i)))
163 env->fpscr[i] = (u.s.u[1] >> (4 * (7 - i))) & 0xF;
164 }
165 /* TODO: update FEX & VX */
166 /* Set rounding mode */
167 switch (env->fpscr[0] & 0x3) {
168 case 0:
169 /* Best approximation (round to nearest) */
170 fesetround(FE_TONEAREST);
171 break;
172 case 1:
173 /* Smaller magnitude (round toward zero) */
174 fesetround(FE_TOWARDZERO);
175 break;
176 case 2:
177 /* Round toward +infinite */
178 fesetround(FE_UPWARD);
179 break;
180 case 3:
181 /* Round toward -infinite */
182 fesetround(FE_DOWNWARD);
183 break;
79aceca5 184 }
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185}
186
187int32_t do_sraw(int32_t value, uint32_t shift)
188{
189 int32_t ret;
190
191 xer_ca = 0;
192 if (shift & 0x20) {
193 ret = (-1) * ((uint32_t)value >> 31);
194 if (ret < 0)
195 xer_ca = 1;
196 } else {
197 ret = value >> (shift & 0x1f);
198 if (ret < 0 && (value & ((1 << shift) - 1)) != 0)
199 xer_ca = 1;
200 }
201
202 return ret;
203}
204
205void do_lmw (int reg, uint32_t src)
206{
207 for (; reg <= 31; reg++, src += 4)
208 ugpr(reg) = ld32(src);
209}
210
211void do_stmw (int reg, uint32_t dest)
212{
213 for (; reg <= 31; reg++, dest += 4)
214 st32(dest, ugpr(reg));
215}
216
217void do_lsw (uint32_t reg, int count, uint32_t src)
218{
219 uint32_t tmp;
220 int sh;
221
222 for (; count > 3; count -= 4, src += 4) {
79aceca5 223 ugpr(reg++) = ld32(src);
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224 if (T2 == 32)
225 T2 = 0;
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226 }
227 if (count > 0) {
79aceca5 228 tmp = 0;
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229 for (sh = 24; count > 0; count--, src++, sh -= 8) {
230 tmp |= ld8(src) << sh;
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231 }
232 ugpr(reg) = tmp;
233 }
234}
235
236void do_stsw (uint32_t reg, int count, uint32_t dest)
237{
238 int sh;
239
240 for (; count > 3; count -= 4, dest += 4) {
fb0eaffc 241 st32(dest, ugpr(reg++));
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242 if (reg == 32)
243 reg = 0;
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244 }
245 if (count > 0) {
246 for (sh = 24; count > 0; count--, dest++, sh -= 8) {
79aceca5 247 st8(dest, (ugpr(reg) >> sh) & 0xFF);
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248 }
249 }
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250}
251
252void do_dcbz (void)
253{
254 int i;
255
256 /* Assume cache line size is 32 */
257 for (i = 0; i < 8; i++) {
258 st32(T0, 0);
259 T0 += 4;
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260 }
261}
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262
263/* Instruction cache invalidation helper */
264void do_icbi (void)
265{
17348a7f 266 // tb_invalidate_page(T0);
fb0eaffc 267}