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79aceca5 1/*
3fc6c082 2 * PowerPC emulation helpers for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
79aceca5 19 */
fdabc366
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25#include <signal.h>
26#include <assert.h>
27
28#include "cpu.h"
29#include "exec-all.h"
0411a972 30#include "helper_regs.h"
ca10f867 31#include "qemu-common.h"
d76d1650 32#include "kvm.h"
9a64fbe4
FB		 33
34//#define DEBUG_MMU
35//#define DEBUG_BATS
6b542af7 36//#define DEBUG_SLB
76a66253 37//#define DEBUG_SOFTWARE_TLB
0411a972 38//#define DUMP_PAGE_TABLES
9a64fbe4 39//#define DEBUG_EXCEPTIONS
fdabc366 40//#define FLUSH_ALL_TLBS
9a64fbe4 41
64adab3f 42/*****************************************************************************/
3fc6c082 43/* PowerPC MMU emulation */
a541f297 44
d9bce9d9 45#if defined(CONFIG_USER_ONLY)
e96efcfc 46int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 47 int mmu_idx, int is_softmmu)
24741ef3
FB		 48{
49 int exception, error_code;
d9bce9d9 50
24741ef3 51 if (rw == 2) {
e1833e1f 52 exception = POWERPC_EXCP_ISI;
8f793433 53 error_code = 0x40000000;
24741ef3 54 } else {
e1833e1f 55 exception = POWERPC_EXCP_DSI;
8f793433 56 error_code = 0x40000000;
24741ef3
FB		 57 if (rw)
58 error_code |= 0x02000000;
59 env->spr[SPR_DAR] = address;
60 env->spr[SPR_DSISR] = error_code;
61 }
62 env->exception_index = exception;
63 env->error_code = error_code;
76a66253 64
24741ef3
FB		 65 return 1;
66}
76a66253 67
9b3c35e0 68target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
24741ef3
FB		 69{
70 return addr;
71}
36081602 72
24741ef3 73#else
76a66253 74/* Common routines used by software and hardware TLBs emulation */
b068d6a7 75static always_inline int pte_is_valid (target_ulong pte0)
76a66253
JM		 76{
77 return pte0 & 0x80000000 ? 1 : 0;
78}
79
b068d6a7 80static always_inline void pte_invalidate (target_ulong *pte0)
76a66253
JM		 81{
82 *pte0 &= ~0x80000000;
83}
84
caa4039c 85#if defined(TARGET_PPC64)
b068d6a7 86static always_inline int pte64_is_valid (target_ulong pte0)
caa4039c
JM		 87{
88 return pte0 & 0x0000000000000001ULL ? 1 : 0;
89}
90
b068d6a7 91static always_inline void pte64_invalidate (target_ulong *pte0)
caa4039c
JM		 92{
93 *pte0 &= ~0x0000000000000001ULL;
94}
95#endif
96
76a66253
JM		 97#define PTE_PTEM_MASK 0x7FFFFFBF
98#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
caa4039c
JM		 99#if defined(TARGET_PPC64)
100#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
101#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
102#endif
76a66253 103
b227a8e9
JM		 104static always_inline int pp_check (int key, int pp, int nx)
105{
106 int access;
107
108 /* Compute access rights */
109 /* When pp is 3/7, the result is undefined. Set it to noaccess */
110 access = 0;
111 if (key == 0) {
112 switch (pp) {
113 case 0x0:
114 case 0x1:
115 case 0x2:
116 access |= PAGE_WRITE;
117 /* No break here */
118 case 0x3:
119 case 0x6:
120 access |= PAGE_READ;
121 break;
122 }
123 } else {
124 switch (pp) {
125 case 0x0:
126 case 0x6:
127 access = 0;
128 break;
129 case 0x1:
130 case 0x3:
131 access = PAGE_READ;
132 break;
133 case 0x2:
134 access = PAGE_READ | PAGE_WRITE;
135 break;
136 }
137 }
138 if (nx == 0)
139 access |= PAGE_EXEC;
140
141 return access;
142}
143
144static always_inline int check_prot (int prot, int rw, int access_type)
145{
146 int ret;
147
148 if (access_type == ACCESS_CODE) {
149 if (prot & PAGE_EXEC)
150 ret = 0;
151 else
152 ret = -2;
153 } else if (rw) {
154 if (prot & PAGE_WRITE)
155 ret = 0;
156 else
157 ret = -2;
158 } else {
159 if (prot & PAGE_READ)
160 ret = 0;
161 else
162 ret = -2;
163 }
164
165 return ret;
166}
167
b068d6a7
JM		 168static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
169 target_ulong pte0, target_ulong pte1,
b227a8e9 170 int h, int rw, int type)
76a66253 171{
caa4039c 172 target_ulong ptem, mmask;
b227a8e9 173 int access, ret, pteh, ptev, pp;
76a66253
JM		 174
175 access = 0;
176 ret = -1;
177 /* Check validity and table match */
caa4039c
JM		 178#if defined(TARGET_PPC64)
179 if (is_64b) {
180 ptev = pte64_is_valid(pte0);
181 pteh = (pte0 >> 1) & 1;
182 } else
183#endif
184 {
185 ptev = pte_is_valid(pte0);
186 pteh = (pte0 >> 6) & 1;
187 }
188 if (ptev && h == pteh) {
76a66253 189 /* Check vsid & api */
caa4039c
JM		 190#if defined(TARGET_PPC64)
191 if (is_64b) {
192 ptem = pte0 & PTE64_PTEM_MASK;
193 mmask = PTE64_CHECK_MASK;
b227a8e9
JM		 194 pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
195 ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */
196 ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
caa4039c
JM		 197 } else
198#endif
199 {
200 ptem = pte0 & PTE_PTEM_MASK;
201 mmask = PTE_CHECK_MASK;
b227a8e9 202 pp = pte1 & 0x00000003;
caa4039c
JM		 203 }
204 if (ptem == ctx->ptem) {
6f2d8978 205 if (ctx->raddr != (target_phys_addr_t)-1ULL) {
76a66253 206 /* all matches should have equal RPN, WIMG & PP */
caa4039c
JM		 207 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
208 if (loglevel != 0)
76a66253
JM		 209 fprintf(logfile, "Bad RPN/WIMG/PP\n");
210 return -3;
211 }
212 }
213 /* Compute access rights */
b227a8e9 214 access = pp_check(ctx->key, pp, ctx->nx);
76a66253
JM		 215 /* Keep the matching PTE informations */
216 ctx->raddr = pte1;
217 ctx->prot = access;
b227a8e9
JM		 218 ret = check_prot(ctx->prot, rw, type);
219 if (ret == 0) {
76a66253
JM		 220 /* Access granted */
221#if defined (DEBUG_MMU)
4a057712 222 if (loglevel != 0)
76a66253
JM		 223 fprintf(logfile, "PTE access granted !\n");
224#endif
76a66253
JM		 225 } else {
226 /* Access right violation */
227#if defined (DEBUG_MMU)
4a057712 228 if (loglevel != 0)
76a66253
JM		 229 fprintf(logfile, "PTE access rejected\n");
230#endif
76a66253
JM		 231 }
232 }
233 }
234
235 return ret;
236}
237
a11b8151
JM		 238static always_inline int pte32_check (mmu_ctx_t *ctx,
239 target_ulong pte0, target_ulong pte1,
240 int h, int rw, int type)
caa4039c 241{
b227a8e9 242 return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
caa4039c
JM		 243}
244
245#if defined(TARGET_PPC64)
a11b8151
JM		 246static always_inline int pte64_check (mmu_ctx_t *ctx,
247 target_ulong pte0, target_ulong pte1,
248 int h, int rw, int type)
caa4039c 249{
b227a8e9 250 return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
caa4039c
JM		 251}
252#endif
253
a11b8151
JM		 254static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
255 int ret, int rw)
76a66253
JM		 256{
257 int store = 0;
258
259 /* Update page flags */
260 if (!(*pte1p & 0x00000100)) {
261 /* Update accessed flag */
262 *pte1p |= 0x00000100;
263 store = 1;
264 }
265 if (!(*pte1p & 0x00000080)) {
266 if (rw == 1 && ret == 0) {
267 /* Update changed flag */
268 *pte1p |= 0x00000080;
269 store = 1;
270 } else {
271 /* Force page fault for first write access */
272 ctx->prot &= ~PAGE_WRITE;
273 }
274 }
275
276 return store;
277}
278
279/* Software driven TLB helpers */
a11b8151
JM		 280static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
281 int way, int is_code)
76a66253
JM		 282{
283 int nr;
284
285 /* Select TLB num in a way from address */
286 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
287 /* Select TLB way */
288 nr += env->tlb_per_way * way;
289 /* 6xx have separate TLBs for instructions and data */
290 if (is_code && env->id_tlbs == 1)
291 nr += env->nb_tlb;
292
293 return nr;
294}
295
a11b8151 296static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
76a66253 297{
1d0a48fb 298 ppc6xx_tlb_t *tlb;
76a66253
JM		 299 int nr, max;
300
301#if defined (DEBUG_SOFTWARE_TLB) && 0
302 if (loglevel != 0) {
303 fprintf(logfile, "Invalidate all TLBs\n");
304 }
305#endif
306 /* Invalidate all defined software TLB */
307 max = env->nb_tlb;
308 if (env->id_tlbs == 1)
309 max *= 2;
310 for (nr = 0; nr < max; nr++) {
1d0a48fb 311 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 312 pte_invalidate(&tlb->pte0);
313 }
76a66253 314 tlb_flush(env, 1);
76a66253
JM		 315}
316
b068d6a7
JM		 317static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
318 target_ulong eaddr,
319 int is_code,
320 int match_epn)
76a66253 321{
4a057712 322#if !defined(FLUSH_ALL_TLBS)
1d0a48fb 323 ppc6xx_tlb_t *tlb;
76a66253
JM		 324 int way, nr;
325
76a66253
JM		 326 /* Invalidate ITLB + DTLB, all ways */
327 for (way = 0; way < env->nb_ways; way++) {
328 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
1d0a48fb 329 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 330 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
331#if defined (DEBUG_SOFTWARE_TLB)
332 if (loglevel != 0) {
1b9eb036 333 fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
76a66253
JM		 334 nr, env->nb_tlb, eaddr);
335 }
336#endif
337 pte_invalidate(&tlb->pte0);
338 tlb_flush_page(env, tlb->EPN);
339 }
340 }
341#else
342 /* XXX: PowerPC specification say this is valid as well */
343 ppc6xx_tlb_invalidate_all(env);
344#endif
345}
346
a11b8151
JM		 347static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env,
348 target_ulong eaddr,
349 int is_code)
76a66253
JM		 350{
351 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
352}
353
354void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
355 target_ulong pte0, target_ulong pte1)
356{
1d0a48fb 357 ppc6xx_tlb_t *tlb;
76a66253
JM		 358 int nr;
359
360 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
1d0a48fb 361 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 362#if defined (DEBUG_SOFTWARE_TLB)
363 if (loglevel != 0) {
5fafdf24 364 fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
1b9eb036 365 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
76a66253
JM		 366 }
367#endif
368 /* Invalidate any pending reference in Qemu for this virtual address */
369 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
370 tlb->pte0 = pte0;
371 tlb->pte1 = pte1;
372 tlb->EPN = EPN;
76a66253
JM		 373 /* Store last way for LRU mechanism */
374 env->last_way = way;
375}
376
a11b8151
JM		 377static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
378 target_ulong eaddr, int rw,
379 int access_type)
76a66253 380{
1d0a48fb 381 ppc6xx_tlb_t *tlb;
76a66253
JM		 382 int nr, best, way;
383 int ret;
d9bce9d9 384
76a66253
JM		 385 best = -1;
386 ret = -1; /* No TLB found */
387 for (way = 0; way < env->nb_ways; way++) {
388 nr = ppc6xx_tlb_getnum(env, eaddr, way,
389 access_type == ACCESS_CODE ? 1 : 0);
1d0a48fb 390 tlb = &env->tlb[nr].tlb6;
76a66253
JM		 391 /* This test "emulates" the PTE index match for hardware TLBs */
392 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
393#if defined (DEBUG_SOFTWARE_TLB)
394 if (loglevel != 0) {
1b9eb036
JM		 395 fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
396 "] <> " ADDRX "\n",
76a66253
JM		 397 nr, env->nb_tlb,
398 pte_is_valid(tlb->pte0) ? "valid" : "inval",
399 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
400 }
401#endif
402 continue;
403 }
404#if defined (DEBUG_SOFTWARE_TLB)
405 if (loglevel != 0) {
1b9eb036
JM		 406 fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
407 " %c %c\n",
76a66253
JM		 408 nr, env->nb_tlb,
409 pte_is_valid(tlb->pte0) ? "valid" : "inval",
410 tlb->EPN, eaddr, tlb->pte1,
411 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
412 }
413#endif
b227a8e9 414 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
76a66253
JM		 415 case -3:
416 /* TLB inconsistency */
417 return -1;
418 case -2:
419 /* Access violation */
420 ret = -2;
421 best = nr;
422 break;
423 case -1:
424 default:
425 /* No match */
426 break;
427 case 0:
428 /* access granted */
429 /* XXX: we should go on looping to check all TLBs consistency
430 * but we can speed-up the whole thing as the
431 * result would be undefined if TLBs are not consistent.
432 */
433 ret = 0;
434 best = nr;
435 goto done;
436 }
437 }
438 if (best != -1) {
439 done:
440#if defined (DEBUG_SOFTWARE_TLB)
4a057712 441 if (loglevel != 0) {
6b542af7 442 fprintf(logfile, "found TLB at addr " PADDRX " prot=%01x ret=%d\n",
76a66253
JM		 443 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
444 }
445#endif
446 /* Update page flags */
1d0a48fb 447 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
76a66253
JM		 448 }
449
450 return ret;
451}
452
9a64fbe4 453/* Perform BAT hit & translation */
faadf50e
JM		 454static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
455 int *validp, int *protp,
456 target_ulong *BATu, target_ulong *BATl)
457{
458 target_ulong bl;
459 int pp, valid, prot;
460
461 bl = (*BATu & 0x00001FFC) << 15;
462 valid = 0;
463 prot = 0;
464 if (((msr_pr == 0) && (*BATu & 0x00000002)) ||
465 ((msr_pr != 0) && (*BATu & 0x00000001))) {
466 valid = 1;
467 pp = *BATl & 0x00000003;
468 if (pp != 0) {
469 prot = PAGE_READ | PAGE_EXEC;
470 if (pp == 0x2)
471 prot |= PAGE_WRITE;
472 }
473 }
474 *blp = bl;
475 *validp = valid;
476 *protp = prot;
477}
478
479static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
480 int *validp, int *protp,
481 target_ulong *BATu,
482 target_ulong *BATl)
483{
484 target_ulong bl;
485 int key, pp, valid, prot;
486
487 bl = (*BATl & 0x0000003F) << 17;
056401ea 488#if defined (DEBUG_BATS)
faadf50e 489 if (loglevel != 0) {
6b542af7
JM		 490 fprintf(logfile, "b %02x ==> bl " ADDRX " msk " ADDRX "\n",
491 (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
faadf50e 492 }
056401ea 493#endif
faadf50e
JM		 494 prot = 0;
495 valid = (*BATl >> 6) & 1;
496 if (valid) {
497 pp = *BATu & 0x00000003;
498 if (msr_pr == 0)
499 key = (*BATu >> 3) & 1;
500 else
501 key = (*BATu >> 2) & 1;
502 prot = pp_check(key, pp, 0);
503 }
504 *blp = bl;
505 *validp = valid;
506 *protp = prot;
507}
508
a11b8151
JM		 509static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
510 target_ulong virtual, int rw, int type)
9a64fbe4 511{
76a66253
JM		 512 target_ulong *BATlt, *BATut, *BATu, *BATl;
513 target_ulong base, BEPIl, BEPIu, bl;
faadf50e 514 int i, valid, prot;
9a64fbe4
FB		 515 int ret = -1;
516
517#if defined (DEBUG_BATS)
4a057712 518 if (loglevel != 0) {
6b542af7 519 fprintf(logfile, "%s: %cBAT v " ADDRX "\n", __func__,
76a66253 520 type == ACCESS_CODE ? 'I' : 'D', virtual);
9a64fbe4 521 }
9a64fbe4
FB		 522#endif
523 switch (type) {
524 case ACCESS_CODE:
525 BATlt = env->IBAT[1];
526 BATut = env->IBAT[0];
527 break;
528 default:
529 BATlt = env->DBAT[1];
530 BATut = env->DBAT[0];
531 break;
532 }
9a64fbe4 533 base = virtual & 0xFFFC0000;
faadf50e 534 for (i = 0; i < env->nb_BATs; i++) {
9a64fbe4
FB		 535 BATu = &BATut[i];
536 BATl = &BATlt[i];
537 BEPIu = *BATu & 0xF0000000;
538 BEPIl = *BATu & 0x0FFE0000;
faadf50e
JM		 539 if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
540 bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);
541 } else {
542 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
543 }
9a64fbe4 544#if defined (DEBUG_BATS)
4a057712 545 if (loglevel != 0) {
6b542af7
JM		 546 fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX
547 " BATl " ADDRX "\n", __func__,
548 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
9a64fbe4
FB		 549 }
550#endif
551 if ((virtual & 0xF0000000) == BEPIu &&
552 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
553 /* BAT matches */
faadf50e 554 if (valid != 0) {
9a64fbe4 555 /* Get physical address */
76a66253 556 ctx->raddr = (*BATl & 0xF0000000) |
9a64fbe4 557 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
a541f297 558 (virtual & 0x0001F000);
b227a8e9 559 /* Compute access rights */
faadf50e 560 ctx->prot = prot;
b227a8e9 561 ret = check_prot(ctx->prot, rw, type);
9a64fbe4 562#if defined (DEBUG_BATS)
b227a8e9 563 if (ret == 0 && loglevel != 0) {
6b542af7 564 fprintf(logfile, "BAT %d match: r " PADDRX " prot=%c%c\n",
76a66253
JM		 565 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
566 ctx->prot & PAGE_WRITE ? 'W' : '-');
9a64fbe4
FB		 567 }
568#endif
9a64fbe4
FB		 569 break;
570 }
571 }
572 }
573 if (ret < 0) {
574#if defined (DEBUG_BATS)
4a057712 575 if (loglevel != 0) {
6b542af7 576 fprintf(logfile, "no BAT match for " ADDRX ":\n", virtual);
4a057712
JM		 577 for (i = 0; i < 4; i++) {
578 BATu = &BATut[i];
579 BATl = &BATlt[i];
580 BEPIu = *BATu & 0xF0000000;
581 BEPIl = *BATu & 0x0FFE0000;
582 bl = (*BATu & 0x00001FFC) << 15;
6b542af7
JM		 583 fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX
584 " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n",
4a057712
JM		 585 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
586 *BATu, *BATl, BEPIu, BEPIl, bl);
587 }
9a64fbe4
FB		 588 }
589#endif
9a64fbe4 590 }
b227a8e9 591
9a64fbe4
FB		 592 /* No hit */
593 return ret;
594}
595
596/* PTE table lookup */
b227a8e9
JM		 597static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
598 int rw, int type)
9a64fbe4 599{
76a66253
JM		 600 target_ulong base, pte0, pte1;
601 int i, good = -1;
caa4039c 602 int ret, r;
9a64fbe4 603
76a66253
JM		 604 ret = -1; /* No entry found */
605 base = ctx->pg_addr[h];
9a64fbe4 606 for (i = 0; i < 8; i++) {
caa4039c
JM		 607#if defined(TARGET_PPC64)
608 if (is_64b) {
609 pte0 = ldq_phys(base + (i * 16));
610 pte1 = ldq_phys(base + (i * 16) + 8);
b227a8e9 611 r = pte64_check(ctx, pte0, pte1, h, rw, type);
12de9a39
JM		 612#if defined (DEBUG_MMU)
613 if (loglevel != 0) {
6b542af7
JM		 614 fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX
615 " %d %d %d " ADDRX "\n",
12de9a39
JM		 616 base + (i * 16), pte0, pte1,
617 (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
618 ctx->ptem);
619 }
620#endif
caa4039c
JM		 621 } else
622#endif
623 {
624 pte0 = ldl_phys(base + (i * 8));
625 pte1 = ldl_phys(base + (i * 8) + 4);
b227a8e9 626 r = pte32_check(ctx, pte0, pte1, h, rw, type);
9a64fbe4 627#if defined (DEBUG_MMU)
12de9a39 628 if (loglevel != 0) {
6b542af7
JM		 629 fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX
630 " %d %d %d " ADDRX "\n",
12de9a39
JM		 631 base + (i * 8), pte0, pte1,
632 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
633 ctx->ptem);
634 }
9a64fbe4 635#endif
12de9a39 636 }
caa4039c 637 switch (r) {
76a66253
JM		 638 case -3:
639 /* PTE inconsistency */
640 return -1;
641 case -2:
642 /* Access violation */
643 ret = -2;
644 good = i;
645 break;
646 case -1:
647 default:
648 /* No PTE match */
649 break;
650 case 0:
651 /* access granted */
652 /* XXX: we should go on looping to check all PTEs consistency
653 * but if we can speed-up the whole thing as the
654 * result would be undefined if PTEs are not consistent.
655 */
656 ret = 0;
657 good = i;
658 goto done;
9a64fbe4
FB		 659 }
660 }
661 if (good != -1) {
76a66253 662 done:
9a64fbe4 663#if defined (DEBUG_MMU)
4a057712 664 if (loglevel != 0) {
6b542af7 665 fprintf(logfile, "found PTE at addr " PADDRX " prot=%01x ret=%d\n",
76a66253
JM		 666 ctx->raddr, ctx->prot, ret);
667 }
9a64fbe4
FB		 668#endif
669 /* Update page flags */
76a66253 670 pte1 = ctx->raddr;
caa4039c
JM		 671 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
672#if defined(TARGET_PPC64)
673 if (is_64b) {
674 stq_phys_notdirty(base + (good * 16) + 8, pte1);
675 } else
676#endif
677 {
678 stl_phys_notdirty(base + (good * 8) + 4, pte1);
679 }
680 }
9a64fbe4
FB		 681 }
682
683 return ret;
79aceca5
FB		 684}
685
a11b8151 686static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type)
caa4039c 687{
b227a8e9 688 return _find_pte(ctx, 0, h, rw, type);
caa4039c
JM		 689}
690
691#if defined(TARGET_PPC64)
a11b8151 692static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type)
caa4039c 693{
b227a8e9 694 return _find_pte(ctx, 1, h, rw, type);
caa4039c
JM		 695}
696#endif
697
b068d6a7 698static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
b227a8e9 699 int h, int rw, int type)
caa4039c
JM		 700{
701#if defined(TARGET_PPC64)
add78955 702 if (env->mmu_model & POWERPC_MMU_64)
b227a8e9 703 return find_pte64(ctx, h, rw, type);
caa4039c
JM		 704#endif
705
b227a8e9 706 return find_pte32(ctx, h, rw, type);
caa4039c
JM		 707}
708
caa4039c 709#if defined(TARGET_PPC64)
a11b8151 710static always_inline int slb_is_valid (uint64_t slb64)
eacc3249
JM		 711{
712 return slb64 & 0x0000000008000000ULL ? 1 : 0;
713}
714
a11b8151 715static always_inline void slb_invalidate (uint64_t *slb64)
eacc3249
JM		 716{
717 *slb64 &= ~0x0000000008000000ULL;
718}
719
a11b8151
JM		 720static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
721 target_ulong *vsid,
722 target_ulong *page_mask, int *attr)
caa4039c
JM		 723{
724 target_phys_addr_t sr_base;
725 target_ulong mask;
726 uint64_t tmp64;
727 uint32_t tmp;
728 int n, ret;
caa4039c
JM		 729
730 ret = -5;
731 sr_base = env->spr[SPR_ASR];
12de9a39
JM		 732#if defined(DEBUG_SLB)
733 if (loglevel != 0) {
734 fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n",
735 __func__, eaddr, sr_base);
736 }
737#endif
caa4039c 738 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
eacc3249 739 for (n = 0; n < env->slb_nr; n++) {
caa4039c 740 tmp64 = ldq_phys(sr_base);
12de9a39
JM		 741 tmp = ldl_phys(sr_base + 8);
742#if defined(DEBUG_SLB)
743 if (loglevel != 0) {
b33c17e1
JM		 744 fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08"
745 PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
12de9a39
JM		 746 }
747#endif
eacc3249 748 if (slb_is_valid(tmp64)) {
caa4039c
JM		 749 /* SLB entry is valid */
750 switch (tmp64 & 0x0000000006000000ULL) {
751 case 0x0000000000000000ULL:
752 /* 256 MB segment */
753 mask = 0xFFFFFFFFF0000000ULL;
754 break;
755 case 0x0000000002000000ULL:
756 /* 1 TB segment */
757 mask = 0xFFFF000000000000ULL;
758 break;
759 case 0x0000000004000000ULL:
760 case 0x0000000006000000ULL:
761 /* Reserved => segment is invalid */
762 continue;
763 }
764 if ((eaddr & mask) == (tmp64 & mask)) {
765 /* SLB match */
caa4039c
JM		 766 *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
767 *page_mask = ~mask;
768 *attr = tmp & 0xFF;
eacc3249 769 ret = n;
caa4039c
JM		 770 break;
771 }
772 }
773 sr_base += 12;
774 }
775
776 return ret;
79aceca5 777}
12de9a39 778
eacc3249
JM		 779void ppc_slb_invalidate_all (CPUPPCState *env)
780{
781 target_phys_addr_t sr_base;
782 uint64_t tmp64;
783 int n, do_invalidate;
784
785 do_invalidate = 0;
786 sr_base = env->spr[SPR_ASR];
2c1ee068
JM		 787 /* XXX: Warning: slbia never invalidates the first segment */
788 for (n = 1; n < env->slb_nr; n++) {
eacc3249
JM		 789 tmp64 = ldq_phys(sr_base);
790 if (slb_is_valid(tmp64)) {
791 slb_invalidate(&tmp64);
792 stq_phys(sr_base, tmp64);
793 /* XXX: given the fact that segment size is 256 MB or 1TB,
794 * and we still don't have a tlb_flush_mask(env, n, mask)
795 * in Qemu, we just invalidate all TLBs
796 */
797 do_invalidate = 1;
798 }
799 sr_base += 12;
800 }
801 if (do_invalidate)
802 tlb_flush(env, 1);
803}
804
805void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
806{
807 target_phys_addr_t sr_base;
808 target_ulong vsid, page_mask;
809 uint64_t tmp64;
810 int attr;
811 int n;
812
813 n = slb_lookup(env, T0, &vsid, &page_mask, &attr);
814 if (n >= 0) {
815 sr_base = env->spr[SPR_ASR];
816 sr_base += 12 * n;
817 tmp64 = ldq_phys(sr_base);
818 if (slb_is_valid(tmp64)) {
819 slb_invalidate(&tmp64);
820 stq_phys(sr_base, tmp64);
821 /* XXX: given the fact that segment size is 256 MB or 1TB,
822 * and we still don't have a tlb_flush_mask(env, n, mask)
823 * in Qemu, we just invalidate all TLBs
824 */
825 tlb_flush(env, 1);
826 }
827 }
828}
829
12de9a39
JM		 830target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
831{
832 target_phys_addr_t sr_base;
833 target_ulong rt;
834 uint64_t tmp64;
835 uint32_t tmp;
836
837 sr_base = env->spr[SPR_ASR];
838 sr_base += 12 * slb_nr;
839 tmp64 = ldq_phys(sr_base);
840 tmp = ldl_phys(sr_base + 8);
841 if (tmp64 & 0x0000000008000000ULL) {
842 /* SLB entry is valid */
843 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
844 rt = tmp >> 8; /* 65:88 => 40:63 */
845 rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
846 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
847 rt |= ((tmp >> 4) & 0xF) << 27;
848 } else {
849 rt = 0;
850 }
851#if defined(DEBUG_SLB)
852 if (loglevel != 0) {
853 fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
854 ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
855 }
856#endif
857
858 return rt;
859}
860
861void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
862{
863 target_phys_addr_t sr_base;
864 uint64_t tmp64;
865 uint32_t tmp;
866
867 sr_base = env->spr[SPR_ASR];
868 sr_base += 12 * slb_nr;
869 /* Copy Rs bits 37:63 to SLB 62:88 */
870 tmp = rs << 8;
871 tmp64 = (rs >> 24) & 0x7;
872 /* Copy Rs bits 33:36 to SLB 89:92 */
873 tmp |= ((rs >> 27) & 0xF) << 4;
874 /* Set the valid bit */
875 tmp64 |= 1 << 27;
876 /* Set ESID */
877 tmp64 |= (uint32_t)slb_nr << 28;
878#if defined(DEBUG_SLB)
879 if (loglevel != 0) {
6b542af7
JM		 880 fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64
881 " %08" PRIx32 "\n", __func__,
882 slb_nr, rs, sr_base, tmp64, tmp);
12de9a39
JM		 883 }
884#endif
885 /* Write SLB entry to memory */
886 stq_phys(sr_base, tmp64);
887 stl_phys(sr_base + 8, tmp);
888}
caa4039c 889#endif /* defined(TARGET_PPC64) */
79aceca5 890
9a64fbe4 891/* Perform segment based translation */
b068d6a7
JM		 892static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
893 int sdr_sh,
894 target_phys_addr_t hash,
895 target_phys_addr_t mask)
12de9a39 896{
6f2d8978 897 return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
12de9a39
JM		 898}
899
a11b8151
JM		 900static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
901 target_ulong eaddr, int rw, int type)
79aceca5 902{
12de9a39 903 target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
caa4039c
JM		 904 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
905#if defined(TARGET_PPC64)
906 int attr;
9a64fbe4 907#endif
0411a972 908 int ds, vsid_sh, sdr_sh, pr;
caa4039c
JM		 909 int ret, ret2;
910
0411a972 911 pr = msr_pr;
caa4039c 912#if defined(TARGET_PPC64)
add78955 913 if (env->mmu_model & POWERPC_MMU_64) {
12de9a39
JM		 914#if defined (DEBUG_MMU)
915 if (loglevel != 0) {
916 fprintf(logfile, "Check SLBs\n");
917 }
918#endif
caa4039c
JM		 919 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
920 if (ret < 0)
921 return ret;
0411a972
JM		 922 ctx->key = ((attr & 0x40) && (pr != 0)) ||
923 ((attr & 0x80) && (pr == 0)) ? 1 : 0;
caa4039c 924 ds = 0;
b227a8e9 925 ctx->nx = attr & 0x20 ? 1 : 0;
caa4039c
JM		 926 vsid_mask = 0x00003FFFFFFFFF80ULL;
927 vsid_sh = 7;
928 sdr_sh = 18;
929 sdr_mask = 0x3FF80;
930 } else
931#endif /* defined(TARGET_PPC64) */
932 {
933 sr = env->sr[eaddr >> 28];
934 page_mask = 0x0FFFFFFF;
0411a972
JM		 935 ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
936 ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
caa4039c 937 ds = sr & 0x80000000 ? 1 : 0;
b227a8e9 938 ctx->nx = sr & 0x10000000 ? 1 : 0;
caa4039c
JM		 939 vsid = sr & 0x00FFFFFF;
940 vsid_mask = 0x01FFFFC0;
941 vsid_sh = 6;
942 sdr_sh = 16;
943 sdr_mask = 0xFFC0;
9a64fbe4 944#if defined (DEBUG_MMU)
caa4039c 945 if (loglevel != 0) {
6b542af7
JM		 946 fprintf(logfile, "Check segment v=" ADDRX " %d " ADDRX
947 " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
caa4039c 948 eaddr, (int)(eaddr >> 28), sr, env->nip,
0411a972
JM		 949 env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
950 rw, type);
caa4039c 951 }
9a64fbe4 952#endif
caa4039c 953 }
12de9a39
JM		 954#if defined (DEBUG_MMU)
955 if (loglevel != 0) {
956 fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
b227a8e9 957 ctx->key, ds, ctx->nx, vsid);
12de9a39
JM		 958 }
959#endif
caa4039c
JM		 960 ret = -1;
961 if (!ds) {
9a64fbe4 962 /* Check if instruction fetch is allowed, if needed */
b227a8e9 963 if (type != ACCESS_CODE || ctx->nx == 0) {
9a64fbe4 964 /* Page address translation */
76a66253
JM		 965 /* Primary table address */
966 sdr = env->sdr1;
12de9a39
JM		 967 pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
968#if defined(TARGET_PPC64)
add78955 969 if (env->mmu_model & POWERPC_MMU_64) {
12de9a39
JM		 970 htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
971 /* XXX: this is false for 1 TB segments */
972 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
973 } else
974#endif
975 {
976 htab_mask = sdr & 0x000001FF;
977 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
978 }
979 mask = (htab_mask << sdr_sh) | sdr_mask;
980#if defined (DEBUG_MMU)
981 if (loglevel != 0) {
6b542af7
JM		 982 fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX
983 " mask " PADDRX " " ADDRX "\n",
984 sdr, sdr_sh, hash, mask, page_mask);
12de9a39
JM		 985 }
986#endif
caa4039c 987 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
76a66253 988 /* Secondary table address */
caa4039c 989 hash = (~hash) & vsid_mask;
12de9a39
JM		 990#if defined (DEBUG_MMU)
991 if (loglevel != 0) {
6b542af7
JM		 992 fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX
993 " mask " PADDRX "\n",
994 sdr, sdr_sh, hash, mask);
12de9a39
JM		 995 }
996#endif
caa4039c
JM		 997 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
998#if defined(TARGET_PPC64)
add78955 999 if (env->mmu_model & POWERPC_MMU_64) {
caa4039c
JM		 1000 /* Only 5 bits of the page index are used in the AVPN */
1001 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
1002 } else
1003#endif
1004 {
1005 ctx->ptem = (vsid << 7) | (pgidx >> 10);
1006 }
76a66253 1007 /* Initialize real address with an invalid value */
6f2d8978 1008 ctx->raddr = (target_phys_addr_t)-1ULL;
7dbe11ac
JM		 1009 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
1010 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
76a66253
JM		 1011 /* Software TLB search */
1012 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
76a66253 1013 } else {
9a64fbe4 1014#if defined (DEBUG_MMU)
4a057712 1015 if (loglevel != 0) {
6b542af7
JM		 1016 fprintf(logfile, "0 sdr1=" PADDRX " vsid=" ADDRX " "
1017 "api=" ADDRX " hash=" PADDRX
1018 " pg_addr=" PADDRX "\n",
1019 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
76a66253 1020 }
9a64fbe4 1021#endif
76a66253 1022 /* Primary table lookup */
b227a8e9 1023 ret = find_pte(env, ctx, 0, rw, type);
76a66253
JM		 1024 if (ret < 0) {
1025 /* Secondary table lookup */
9a64fbe4 1026#if defined (DEBUG_MMU)
4a057712 1027 if (eaddr != 0xEFFFFFFF && loglevel != 0) {
6b542af7
JM		 1028 fprintf(logfile, "1 sdr1=" PADDRX " vsid=" ADDRX " "
1029 "api=" ADDRX " hash=" PADDRX
1030 " pg_addr=" PADDRX "\n",
1031 sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
76a66253 1032 }
9a64fbe4 1033#endif
b227a8e9 1034 ret2 = find_pte(env, ctx, 1, rw, type);
76a66253
JM		 1035 if (ret2 != -1)
1036 ret = ret2;
1037 }
9a64fbe4 1038 }
0411a972 1039#if defined (DUMP_PAGE_TABLES)
b33c17e1
JM		 1040 if (loglevel != 0) {
1041 target_phys_addr_t curaddr;
1042 uint32_t a0, a1, a2, a3;
6b542af7 1043 fprintf(logfile, "Page table: " PADDRX " len " PADDRX "\n",
b33c17e1
JM		 1044 sdr, mask + 0x80);
1045 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
1046 curaddr += 16) {
1047 a0 = ldl_phys(curaddr);
1048 a1 = ldl_phys(curaddr + 4);
1049 a2 = ldl_phys(curaddr + 8);
1050 a3 = ldl_phys(curaddr + 12);
1051 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
6b542af7 1052 fprintf(logfile, PADDRX ": %08x %08x %08x %08x\n",
b33c17e1 1053 curaddr, a0, a1, a2, a3);
12de9a39 1054 }
b33c17e1
JM		 1055 }
1056 }
12de9a39 1057#endif
9a64fbe4
FB		 1058 } else {
1059#if defined (DEBUG_MMU)
4a057712 1060 if (loglevel != 0)
76a66253 1061 fprintf(logfile, "No access allowed\n");
9a64fbe4 1062#endif
76a66253 1063 ret = -3;
9a64fbe4
FB		 1064 }
1065 } else {
1066#if defined (DEBUG_MMU)
4a057712 1067 if (loglevel != 0)
76a66253 1068 fprintf(logfile, "direct store...\n");
9a64fbe4
FB		 1069#endif
1070 /* Direct-store segment : absolutely *BUGGY* for now */
1071 switch (type) {
1072 case ACCESS_INT:
1073 /* Integer load/store : only access allowed */
1074 break;
1075 case ACCESS_CODE:
1076 /* No code fetch is allowed in direct-store areas */
1077 return -4;
1078 case ACCESS_FLOAT:
1079 /* Floating point load/store */
1080 return -4;
1081 case ACCESS_RES:
1082 /* lwarx, ldarx or srwcx. */
1083 return -4;
1084 case ACCESS_CACHE:
1085 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
1086 /* Should make the instruction do no-op.
1087 * As it already do no-op, it's quite easy :-)
1088 */
76a66253 1089 ctx->raddr = eaddr;
9a64fbe4
FB		 1090 return 0;
1091 case ACCESS_EXT:
1092 /* eciwx or ecowx */
1093 return -4;
1094 default:
1095 if (logfile) {
1096 fprintf(logfile, "ERROR: instruction should not need "
1097 "address translation\n");
1098 }
9a64fbe4
FB		 1099 return -4;
1100 }
76a66253
JM		 1101 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
1102 ctx->raddr = eaddr;
9a64fbe4
FB		 1103 ret = 2;
1104 } else {
1105 ret = -2;
1106 }
79aceca5 1107 }
9a64fbe4
FB		 1108
1109 return ret;
79aceca5
FB		 1110}
1111
c294fc58 1112/* Generic TLB check function for embedded PowerPC implementations */
a11b8151
JM		 1113static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
1114 target_phys_addr_t *raddrp,
1115 target_ulong address,
1116 uint32_t pid, int ext, int i)
c294fc58
JM		 1117{
1118 target_ulong mask;
1119
1120 /* Check valid flag */
1121 if (!(tlb->prot & PAGE_VALID)) {
1122 if (loglevel != 0)
1123 fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
1124 return -1;
1125 }
1126 mask = ~(tlb->size - 1);
daf4f96e 1127#if defined (DEBUG_SOFTWARE_TLB)
c294fc58 1128 if (loglevel != 0) {
6b542af7
JM		 1129 fprintf(logfile, "%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
1130 " " ADDRX " %u\n",
1131 __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID);
c294fc58 1132 }
daf4f96e 1133#endif
c294fc58 1134 /* Check PID */
36081602 1135 if (tlb->PID != 0 && tlb->PID != pid)
c294fc58
JM		 1136 return -1;
1137 /* Check effective address */
1138 if ((address & mask) != tlb->EPN)
1139 return -1;
1140 *raddrp = (tlb->RPN & mask) | (address & ~mask);
9706285b 1141#if (TARGET_PHYS_ADDR_BITS >= 36)
36081602
JM		 1142 if (ext) {
1143 /* Extend the physical address to 36 bits */
1144 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
1145 }
9706285b 1146#endif
c294fc58
JM		 1147
1148 return 0;
1149}
1150
1151/* Generic TLB search function for PowerPC embedded implementations */
36081602 1152int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
c294fc58
JM		 1153{
1154 ppcemb_tlb_t *tlb;
1155 target_phys_addr_t raddr;
1156 int i, ret;
1157
1158 /* Default return value is no match */
1159 ret = -1;
a750fc0b 1160 for (i = 0; i < env->nb_tlb; i++) {
c294fc58 1161 tlb = &env->tlb[i].tlbe;
36081602 1162 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
c294fc58
JM		 1163 ret = i;
1164 break;
1165 }
1166 }
1167
1168 return ret;
1169}
1170
daf4f96e 1171/* Helpers specific to PowerPC 40x implementations */
a11b8151 1172static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
a750fc0b
JM		 1173{
1174 ppcemb_tlb_t *tlb;
a750fc0b
JM		 1175 int i;
1176
1177 for (i = 0; i < env->nb_tlb; i++) {
1178 tlb = &env->tlb[i].tlbe;
daf4f96e 1179 tlb->prot &= ~PAGE_VALID;
a750fc0b 1180 }
daf4f96e 1181 tlb_flush(env, 1);
a750fc0b
JM		 1182}
1183
a11b8151
JM		 1184static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env,
1185 target_ulong eaddr,
1186 uint32_t pid)
0a032cbe 1187{
daf4f96e 1188#if !defined(FLUSH_ALL_TLBS)
0a032cbe 1189 ppcemb_tlb_t *tlb;
daf4f96e
JM		 1190 target_phys_addr_t raddr;
1191 target_ulong page, end;
0a032cbe
JM		 1192 int i;
1193
1194 for (i = 0; i < env->nb_tlb; i++) {
1195 tlb = &env->tlb[i].tlbe;
daf4f96e 1196 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
0a032cbe
JM		 1197 end = tlb->EPN + tlb->size;
1198 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1199 tlb_flush_page(env, page);
0a032cbe 1200 tlb->prot &= ~PAGE_VALID;
daf4f96e 1201 break;
0a032cbe
JM		 1202 }
1203 }
daf4f96e
JM		 1204#else
1205 ppc4xx_tlb_invalidate_all(env);
1206#endif
0a032cbe
JM		 1207}
1208
93220573 1209static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
e96efcfc 1210 target_ulong address, int rw, int access_type)
a8dea12f
JM		 1211{
1212 ppcemb_tlb_t *tlb;
1213 target_phys_addr_t raddr;
0411a972 1214 int i, ret, zsel, zpr, pr;
3b46e624 1215
c55e9aef 1216 ret = -1;
6f2d8978 1217 raddr = (target_phys_addr_t)-1ULL;
0411a972 1218 pr = msr_pr;
a8dea12f
JM		 1219 for (i = 0; i < env->nb_tlb; i++) {
1220 tlb = &env->tlb[i].tlbe;
36081602
JM		 1221 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1222 env->spr[SPR_40x_PID], 0, i) < 0)
a8dea12f 1223 continue;
a8dea12f
JM		 1224 zsel = (tlb->attr >> 4) & 0xF;
1225 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
daf4f96e 1226#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1227 if (loglevel != 0) {
a8dea12f
JM		 1228 fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1229 __func__, i, zsel, zpr, rw, tlb->attr);
1230 }
daf4f96e 1231#endif
b227a8e9
JM		 1232 /* Check execute enable bit */
1233 switch (zpr) {
1234 case 0x2:
0411a972 1235 if (pr != 0)
b227a8e9
JM		 1236 goto check_perms;
1237 /* No break here */
1238 case 0x3:
1239 /* All accesses granted */
1240 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1241 ret = 0;
1242 break;
1243 case 0x0:
0411a972 1244 if (pr != 0) {
b227a8e9
JM		 1245 ctx->prot = 0;
1246 ret = -2;
a8dea12f
JM		 1247 break;
1248 }
b227a8e9
JM		 1249 /* No break here */
1250 case 0x1:
1251 check_perms:
1252 /* Check from TLB entry */
1253 /* XXX: there is a problem here or in the TLB fill code... */
1254 ctx->prot = tlb->prot;
1255 ctx->prot |= PAGE_EXEC;
1256 ret = check_prot(ctx->prot, rw, access_type);
1257 break;
a8dea12f
JM		 1258 }
1259 if (ret >= 0) {
1260 ctx->raddr = raddr;
daf4f96e 1261#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1262 if (loglevel != 0) {
6b542af7 1263 fprintf(logfile, "%s: access granted " ADDRX " => " PADDRX
c55e9aef
JM		 1264 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1265 ret);
a8dea12f 1266 }
daf4f96e 1267#endif
c55e9aef 1268 return 0;
a8dea12f
JM		 1269 }
1270 }
daf4f96e 1271#if defined (DEBUG_SOFTWARE_TLB)
4a057712 1272 if (loglevel != 0) {
6b542af7 1273 fprintf(logfile, "%s: access refused " ADDRX " => " PADDRX
c55e9aef
JM		 1274 " %d %d\n", __func__, address, raddr, ctx->prot,
1275 ret);
1276 }
daf4f96e 1277#endif
3b46e624 1278
a8dea12f
JM		 1279 return ret;
1280}
1281
c294fc58
JM		 1282void store_40x_sler (CPUPPCState *env, uint32_t val)
1283{
1284 /* XXX: TO BE FIXED */
1285 if (val != 0x00000000) {
1286 cpu_abort(env, "Little-endian regions are not supported by now\n");
1287 }
1288 env->spr[SPR_405_SLER] = val;
1289}
1290
93220573
AJ		 1291static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1292 target_ulong address, int rw,
1293 int access_type)
5eb7995e
JM		 1294{
1295 ppcemb_tlb_t *tlb;
1296 target_phys_addr_t raddr;
1297 int i, prot, ret;
1298
1299 ret = -1;
6f2d8978 1300 raddr = (target_phys_addr_t)-1ULL;
5eb7995e
JM		 1301 for (i = 0; i < env->nb_tlb; i++) {
1302 tlb = &env->tlb[i].tlbe;
1303 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1304 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1305 continue;
0411a972 1306 if (msr_pr != 0)
5eb7995e
JM		 1307 prot = tlb->prot & 0xF;
1308 else
1309 prot = (tlb->prot >> 4) & 0xF;
1310 /* Check the address space */
1311 if (access_type == ACCESS_CODE) {
d26bfc9a 1312 if (msr_ir != (tlb->attr & 1))
5eb7995e
JM		 1313 continue;
1314 ctx->prot = prot;
1315 if (prot & PAGE_EXEC) {
1316 ret = 0;
1317 break;
1318 }
1319 ret = -3;
1320 } else {
d26bfc9a 1321 if (msr_dr != (tlb->attr & 1))
5eb7995e
JM		 1322 continue;
1323 ctx->prot = prot;
1324 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1325 ret = 0;
1326 break;
1327 }
1328 ret = -2;
1329 }
1330 }
1331 if (ret >= 0)
1332 ctx->raddr = raddr;
1333
1334 return ret;
1335}
1336
a11b8151
JM		 1337static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
1338 target_ulong eaddr, int rw)
76a66253
JM		 1339{
1340 int in_plb, ret;
3b46e624 1341
76a66253 1342 ctx->raddr = eaddr;
b227a8e9 1343 ctx->prot = PAGE_READ | PAGE_EXEC;
76a66253 1344 ret = 0;
a750fc0b
JM		 1345 switch (env->mmu_model) {
1346 case POWERPC_MMU_32B:
faadf50e 1347 case POWERPC_MMU_601:
a750fc0b 1348 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1349 case POWERPC_MMU_SOFT_74xx:
a750fc0b 1350 case POWERPC_MMU_SOFT_4xx:
b4095fed 1351 case POWERPC_MMU_REAL:
7dbe11ac 1352 case POWERPC_MMU_BOOKE:
caa4039c
JM		 1353 ctx->prot |= PAGE_WRITE;
1354 break;
1355#if defined(TARGET_PPC64)
add78955 1356 case POWERPC_MMU_620:
a750fc0b 1357 case POWERPC_MMU_64B:
caa4039c 1358 /* Real address are 60 bits long */
a750fc0b 1359 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
caa4039c
JM		 1360 ctx->prot |= PAGE_WRITE;
1361 break;
9706285b 1362#endif
a750fc0b 1363 case POWERPC_MMU_SOFT_4xx_Z:
caa4039c
JM		 1364 if (unlikely(msr_pe != 0)) {
1365 /* 403 family add some particular protections,
1366 * using PBL/PBU registers for accesses with no translation.
1367 */
1368 in_plb =
1369 /* Check PLB validity */
1370 (env->pb[0] < env->pb[1] &&
1371 /* and address in plb area */
1372 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1373 (env->pb[2] < env->pb[3] &&
1374 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1375 if (in_plb ^ msr_px) {
1376 /* Access in protected area */
1377 if (rw == 1) {
1378 /* Access is not allowed */
1379 ret = -2;
1380 }
1381 } else {
1382 /* Read-write access is allowed */
1383 ctx->prot |= PAGE_WRITE;
76a66253 1384 }
76a66253 1385 }
e1833e1f 1386 break;
b4095fed
JM		 1387 case POWERPC_MMU_MPC8xx:
1388 /* XXX: TODO */
1389 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1390 break;
a750fc0b 1391 case POWERPC_MMU_BOOKE_FSL:
caa4039c
JM		 1392 /* XXX: TODO */
1393 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1394 break;
1395 default:
1396 cpu_abort(env, "Unknown or invalid MMU model\n");
1397 return -1;
76a66253
JM		 1398 }
1399
1400 return ret;
1401}
1402
1403int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
faadf50e 1404 int rw, int access_type)
9a64fbe4
FB		 1405{
1406 int ret;
0411a972 1407
514fb8c1 1408#if 0
4a057712 1409 if (loglevel != 0) {
9a64fbe4
FB		 1410 fprintf(logfile, "%s\n", __func__);
1411 }
d9bce9d9 1412#endif
4b3686fa
FB		 1413 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1414 (access_type != ACCESS_CODE && msr_dr == 0)) {
9a64fbe4 1415 /* No address translation */
76a66253 1416 ret = check_physical(env, ctx, eaddr, rw);
9a64fbe4 1417 } else {
c55e9aef 1418 ret = -1;
a750fc0b
JM		 1419 switch (env->mmu_model) {
1420 case POWERPC_MMU_32B:
faadf50e 1421 case POWERPC_MMU_601:
a750fc0b 1422 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1423 case POWERPC_MMU_SOFT_74xx:
c55e9aef 1424#if defined(TARGET_PPC64)
add78955 1425 case POWERPC_MMU_620:
a750fc0b 1426 case POWERPC_MMU_64B:
c55e9aef 1427#endif
faadf50e
JM		 1428 /* Try to find a BAT */
1429 if (env->nb_BATs != 0)
1430 ret = get_bat(env, ctx, eaddr, rw, access_type);
a8dea12f 1431 if (ret < 0) {
c55e9aef 1432 /* We didn't match any BAT entry or don't have BATs */
a8dea12f
JM		 1433 ret = get_segment(env, ctx, eaddr, rw, access_type);
1434 }
1435 break;
a750fc0b
JM		 1436 case POWERPC_MMU_SOFT_4xx:
1437 case POWERPC_MMU_SOFT_4xx_Z:
36081602 1438 ret = mmu40x_get_physical_address(env, ctx, eaddr,
a8dea12f
JM		 1439 rw, access_type);
1440 break;
a750fc0b 1441 case POWERPC_MMU_BOOKE:
5eb7995e
JM		 1442 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1443 rw, access_type);
1444 break;
b4095fed
JM		 1445 case POWERPC_MMU_MPC8xx:
1446 /* XXX: TODO */
1447 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1448 break;
a750fc0b 1449 case POWERPC_MMU_BOOKE_FSL:
c55e9aef
JM		 1450 /* XXX: TODO */
1451 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1452 return -1;
b4095fed
JM		 1453 case POWERPC_MMU_REAL:
1454 cpu_abort(env, "PowerPC in real mode do not do any translation\n");
2662a059 1455 return -1;
c55e9aef
JM		 1456 default:
1457 cpu_abort(env, "Unknown or invalid MMU model\n");
a8dea12f 1458 return -1;
9a64fbe4
FB		 1459 }
1460 }
514fb8c1 1461#if 0
4a057712
JM		 1462 if (loglevel != 0) {
1463 fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
c55e9aef 1464 __func__, eaddr, ret, ctx->raddr);
a541f297 1465 }
76a66253 1466#endif
d9bce9d9 1467
9a64fbe4
FB		 1468 return ret;
1469}
1470
9b3c35e0 1471target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
a6b025d3 1472{
76a66253 1473 mmu_ctx_t ctx;
a6b025d3 1474
faadf50e 1475 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0))
a6b025d3 1476 return -1;
76a66253
JM		 1477
1478 return ctx.raddr & TARGET_PAGE_MASK;
a6b025d3 1479}
9a64fbe4 1480
9a64fbe4 1481/* Perform address translation */
e96efcfc 1482int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 1483 int mmu_idx, int is_softmmu)
9a64fbe4 1484{
76a66253 1485 mmu_ctx_t ctx;
a541f297 1486 int access_type;
9a64fbe4 1487 int ret = 0;
d9bce9d9 1488
b769d8fe
FB		 1489 if (rw == 2) {
1490 /* code access */
1491 rw = 0;
1492 access_type = ACCESS_CODE;
1493 } else {
1494 /* data access */
b4cec7b4 1495 access_type = env->access_type;
b769d8fe 1496 }
faadf50e 1497 ret = get_physical_address(env, &ctx, address, rw, access_type);
9a64fbe4 1498 if (ret == 0) {
b227a8e9
JM		 1499 ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK,
1500 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1501 mmu_idx, is_softmmu);
9a64fbe4 1502 } else if (ret < 0) {
9a64fbe4 1503#if defined (DEBUG_MMU)
4a057712 1504 if (loglevel != 0)
76a66253 1505 cpu_dump_state(env, logfile, fprintf, 0);
9a64fbe4
FB		 1506#endif
1507 if (access_type == ACCESS_CODE) {
9a64fbe4
FB		 1508 switch (ret) {
1509 case -1:
76a66253 1510 /* No matches in page tables or TLB */
a750fc0b
JM		 1511 switch (env->mmu_model) {
1512 case POWERPC_MMU_SOFT_6xx:
8f793433
JM		 1513 env->exception_index = POWERPC_EXCP_IFTLB;
1514 env->error_code = 1 << 18;
76a66253
JM		 1515 env->spr[SPR_IMISS] = address;
1516 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
76a66253 1517 goto tlb_miss;
7dbe11ac 1518 case POWERPC_MMU_SOFT_74xx:
8f793433 1519 env->exception_index = POWERPC_EXCP_IFTLB;
7dbe11ac 1520 goto tlb_miss_74xx;
a750fc0b
JM		 1521 case POWERPC_MMU_SOFT_4xx:
1522 case POWERPC_MMU_SOFT_4xx_Z:
8f793433
JM		 1523 env->exception_index = POWERPC_EXCP_ITLB;
1524 env->error_code = 0;
a8dea12f
JM		 1525 env->spr[SPR_40x_DEAR] = address;
1526 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef 1527 break;
a750fc0b 1528 case POWERPC_MMU_32B:
faadf50e 1529 case POWERPC_MMU_601:
c55e9aef 1530#if defined(TARGET_PPC64)
add78955 1531 case POWERPC_MMU_620:
a750fc0b 1532 case POWERPC_MMU_64B:
c55e9aef 1533#endif
8f793433
JM		 1534 env->exception_index = POWERPC_EXCP_ISI;
1535 env->error_code = 0x40000000;
1536 break;
a750fc0b 1537 case POWERPC_MMU_BOOKE:
c55e9aef 1538 /* XXX: TODO */
b4095fed 1539 cpu_abort(env, "BookE MMU model is not implemented\n");
c55e9aef 1540 return -1;
a750fc0b 1541 case POWERPC_MMU_BOOKE_FSL:
c55e9aef 1542 /* XXX: TODO */
b4095fed 1543 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
c55e9aef 1544 return -1;
b4095fed
JM		 1545 case POWERPC_MMU_MPC8xx:
1546 /* XXX: TODO */
1547 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1548 break;
1549 case POWERPC_MMU_REAL:
1550 cpu_abort(env, "PowerPC in real mode should never raise "
1551 "any MMU exceptions\n");
2662a059 1552 return -1;
c55e9aef
JM		 1553 default:
1554 cpu_abort(env, "Unknown or invalid MMU model\n");
1555 return -1;
76a66253 1556 }
9a64fbe4
FB		 1557 break;
1558 case -2:
1559 /* Access rights violation */
8f793433
JM		 1560 env->exception_index = POWERPC_EXCP_ISI;
1561 env->error_code = 0x08000000;
9a64fbe4
FB		 1562 break;
1563 case -3:
76a66253 1564 /* No execute protection violation */
8f793433
JM		 1565 env->exception_index = POWERPC_EXCP_ISI;
1566 env->error_code = 0x10000000;
9a64fbe4
FB		 1567 break;
1568 case -4:
1569 /* Direct store exception */
1570 /* No code fetch is allowed in direct-store areas */
8f793433
JM		 1571 env->exception_index = POWERPC_EXCP_ISI;
1572 env->error_code = 0x10000000;
2be0071f 1573 break;
e1833e1f 1574#if defined(TARGET_PPC64)
2be0071f
FB		 1575 case -5:
1576 /* No match in segment table */
add78955
JM		 1577 if (env->mmu_model == POWERPC_MMU_620) {
1578 env->exception_index = POWERPC_EXCP_ISI;
1579 /* XXX: this might be incorrect */
1580 env->error_code = 0x40000000;
1581 } else {
1582 env->exception_index = POWERPC_EXCP_ISEG;
1583 env->error_code = 0;
1584 }
9a64fbe4 1585 break;
e1833e1f 1586#endif
9a64fbe4
FB		 1587 }
1588 } else {
9a64fbe4
FB		 1589 switch (ret) {
1590 case -1:
76a66253 1591 /* No matches in page tables or TLB */
a750fc0b
JM		 1592 switch (env->mmu_model) {
1593 case POWERPC_MMU_SOFT_6xx:
76a66253 1594 if (rw == 1) {
8f793433
JM		 1595 env->exception_index = POWERPC_EXCP_DSTLB;
1596 env->error_code = 1 << 16;
76a66253 1597 } else {
8f793433
JM		 1598 env->exception_index = POWERPC_EXCP_DLTLB;
1599 env->error_code = 0;
76a66253
JM		 1600 }
1601 env->spr[SPR_DMISS] = address;
1602 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1603 tlb_miss:
8f793433 1604 env->error_code |= ctx.key << 19;
76a66253
JM		 1605 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1606 env->spr[SPR_HASH2] = ctx.pg_addr[1];
8f793433 1607 break;
7dbe11ac
JM		 1608 case POWERPC_MMU_SOFT_74xx:
1609 if (rw == 1) {
8f793433 1610 env->exception_index = POWERPC_EXCP_DSTLB;
7dbe11ac 1611 } else {
8f793433 1612 env->exception_index = POWERPC_EXCP_DLTLB;
7dbe11ac
JM		 1613 }
1614 tlb_miss_74xx:
1615 /* Implement LRU algorithm */
8f793433 1616 env->error_code = ctx.key << 19;
7dbe11ac
JM		 1617 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1618 ((env->last_way + 1) & (env->nb_ways - 1));
1619 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
7dbe11ac 1620 break;
a750fc0b
JM		 1621 case POWERPC_MMU_SOFT_4xx:
1622 case POWERPC_MMU_SOFT_4xx_Z:
8f793433
JM		 1623 env->exception_index = POWERPC_EXCP_DTLB;
1624 env->error_code = 0;
a8dea12f
JM		 1625 env->spr[SPR_40x_DEAR] = address;
1626 if (rw)
1627 env->spr[SPR_40x_ESR] = 0x00800000;
1628 else
1629 env->spr[SPR_40x_ESR] = 0x00000000;
c55e9aef 1630 break;
a750fc0b 1631 case POWERPC_MMU_32B:
faadf50e 1632 case POWERPC_MMU_601:
c55e9aef 1633#if defined(TARGET_PPC64)
add78955 1634 case POWERPC_MMU_620:
a750fc0b 1635 case POWERPC_MMU_64B:
c55e9aef 1636#endif
8f793433
JM		 1637 env->exception_index = POWERPC_EXCP_DSI;
1638 env->error_code = 0;
1639 env->spr[SPR_DAR] = address;
1640 if (rw == 1)
1641 env->spr[SPR_DSISR] = 0x42000000;
1642 else
1643 env->spr[SPR_DSISR] = 0x40000000;
1644 break;
b4095fed
JM		 1645 case POWERPC_MMU_MPC8xx:
1646 /* XXX: TODO */
1647 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1648 break;
a750fc0b 1649 case POWERPC_MMU_BOOKE:
c55e9aef 1650 /* XXX: TODO */
b4095fed 1651 cpu_abort(env, "BookE MMU model is not implemented\n");
c55e9aef 1652 return -1;
a750fc0b 1653 case POWERPC_MMU_BOOKE_FSL:
c55e9aef 1654 /* XXX: TODO */
b4095fed 1655 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
c55e9aef 1656 return -1;
b4095fed
JM		 1657 case POWERPC_MMU_REAL:
1658 cpu_abort(env, "PowerPC in real mode should never raise "
1659 "any MMU exceptions\n");
2662a059 1660 return -1;
c55e9aef
JM		 1661 default:
1662 cpu_abort(env, "Unknown or invalid MMU model\n");
1663 return -1;
76a66253 1664 }
9a64fbe4
FB		 1665 break;
1666 case -2:
1667 /* Access rights violation */
8f793433
JM		 1668 env->exception_index = POWERPC_EXCP_DSI;
1669 env->error_code = 0;
1670 env->spr[SPR_DAR] = address;
1671 if (rw == 1)
1672 env->spr[SPR_DSISR] = 0x0A000000;
1673 else
1674 env->spr[SPR_DSISR] = 0x08000000;
9a64fbe4
FB		 1675 break;
1676 case -4:
1677 /* Direct store exception */
1678 switch (access_type) {
1679 case ACCESS_FLOAT:
1680 /* Floating point load/store */
8f793433
JM		 1681 env->exception_index = POWERPC_EXCP_ALIGN;
1682 env->error_code = POWERPC_EXCP_ALIGN_FP;
1683 env->spr[SPR_DAR] = address;
9a64fbe4
FB		 1684 break;
1685 case ACCESS_RES:
8f793433
JM		 1686 /* lwarx, ldarx or stwcx. */
1687 env->exception_index = POWERPC_EXCP_DSI;
1688 env->error_code = 0;
1689 env->spr[SPR_DAR] = address;
1690 if (rw == 1)
1691 env->spr[SPR_DSISR] = 0x06000000;
1692 else
1693 env->spr[SPR_DSISR] = 0x04000000;
9a64fbe4
FB		 1694 break;
1695 case ACCESS_EXT:
1696 /* eciwx or ecowx */
8f793433
JM		 1697 env->exception_index = POWERPC_EXCP_DSI;
1698 env->error_code = 0;
1699 env->spr[SPR_DAR] = address;
1700 if (rw == 1)
1701 env->spr[SPR_DSISR] = 0x06100000;
1702 else
1703 env->spr[SPR_DSISR] = 0x04100000;
9a64fbe4
FB		 1704 break;
1705 default:
76a66253 1706 printf("DSI: invalid exception (%d)\n", ret);
8f793433
JM		 1707 env->exception_index = POWERPC_EXCP_PROGRAM;
1708 env->error_code =
1709 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1710 env->spr[SPR_DAR] = address;
9a64fbe4
FB		 1711 break;
1712 }
fdabc366 1713 break;
e1833e1f 1714#if defined(TARGET_PPC64)
2be0071f
FB		 1715 case -5:
1716 /* No match in segment table */
add78955
JM		 1717 if (env->mmu_model == POWERPC_MMU_620) {
1718 env->exception_index = POWERPC_EXCP_DSI;
1719 env->error_code = 0;
1720 env->spr[SPR_DAR] = address;
1721 /* XXX: this might be incorrect */
1722 if (rw == 1)
1723 env->spr[SPR_DSISR] = 0x42000000;
1724 else
1725 env->spr[SPR_DSISR] = 0x40000000;
1726 } else {
1727 env->exception_index = POWERPC_EXCP_DSEG;
1728 env->error_code = 0;
1729 env->spr[SPR_DAR] = address;
1730 }
2be0071f 1731 break;
e1833e1f 1732#endif
9a64fbe4 1733 }
9a64fbe4
FB		 1734 }
1735#if 0
8f793433
JM		 1736 printf("%s: set exception to %d %02x\n", __func__,
1737 env->exception, env->error_code);
9a64fbe4 1738#endif
9a64fbe4
FB		 1739 ret = 1;
1740 }
76a66253 1741
9a64fbe4
FB		 1742 return ret;
1743}
1744
3fc6c082
FB		 1745/*****************************************************************************/
1746/* BATs management */
1747#if !defined(FLUSH_ALL_TLBS)
b068d6a7
JM		 1748static always_inline void do_invalidate_BAT (CPUPPCState *env,
1749 target_ulong BATu,
1750 target_ulong mask)
3fc6c082
FB		 1751{
1752 target_ulong base, end, page;
76a66253 1753
3fc6c082
FB		 1754 base = BATu & ~0x0001FFFF;
1755 end = base + mask + 0x00020000;
1756#if defined (DEBUG_BATS)
76a66253 1757 if (loglevel != 0) {
1b9eb036 1758 fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
76a66253
JM		 1759 base, end, mask);
1760 }
3fc6c082
FB		 1761#endif
1762 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1763 tlb_flush_page(env, page);
1764#if defined (DEBUG_BATS)
1765 if (loglevel != 0)
1766 fprintf(logfile, "Flush done\n");
1767#endif
1768}
1769#endif
1770
b068d6a7
JM		 1771static always_inline void dump_store_bat (CPUPPCState *env, char ID,
1772 int ul, int nr, target_ulong value)
3fc6c082
FB		 1773{
1774#if defined (DEBUG_BATS)
1775 if (loglevel != 0) {
6b542af7 1776 fprintf(logfile, "Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
1b9eb036 1777 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
3fc6c082
FB		 1778 }
1779#endif
1780}
1781
45d827d2 1782void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
3fc6c082
FB		 1783{
1784 target_ulong mask;
1785
1786 dump_store_bat(env, 'I', 0, nr, value);
1787 if (env->IBAT[0][nr] != value) {
1788 mask = (value << 15) & 0x0FFE0000UL;
1789#if !defined(FLUSH_ALL_TLBS)
1790 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1791#endif
1792 /* When storing valid upper BAT, mask BEPI and BRPN
1793 * and invalidate all TLBs covered by this BAT
1794 */
1795 mask = (value << 15) & 0x0FFE0000UL;
1796 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1797 (value & ~0x0001FFFFUL & ~mask);
1798 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1799 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1800#if !defined(FLUSH_ALL_TLBS)
1801 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
76a66253 1802#else
3fc6c082
FB		 1803 tlb_flush(env, 1);
1804#endif
1805 }
1806}
1807
45d827d2 1808void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
3fc6c082
FB		 1809{
1810 dump_store_bat(env, 'I', 1, nr, value);
1811 env->IBAT[1][nr] = value;
1812}
1813
45d827d2 1814void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
3fc6c082
FB		 1815{
1816 target_ulong mask;
1817
1818 dump_store_bat(env, 'D', 0, nr, value);
1819 if (env->DBAT[0][nr] != value) {
1820 /* When storing valid upper BAT, mask BEPI and BRPN
1821 * and invalidate all TLBs covered by this BAT
1822 */
1823 mask = (value << 15) & 0x0FFE0000UL;
1824#if !defined(FLUSH_ALL_TLBS)
1825 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1826#endif
1827 mask = (value << 15) & 0x0FFE0000UL;
1828 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1829 (value & ~0x0001FFFFUL & ~mask);
1830 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1831 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1832#if !defined(FLUSH_ALL_TLBS)
1833 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1834#else
1835 tlb_flush(env, 1);
1836#endif
1837 }
1838}
1839
45d827d2 1840void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
3fc6c082
FB		 1841{
1842 dump_store_bat(env, 'D', 1, nr, value);
1843 env->DBAT[1][nr] = value;
1844}
1845
45d827d2 1846void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
056401ea
JM		 1847{
1848 target_ulong mask;
1849 int do_inval;
1850
1851 dump_store_bat(env, 'I', 0, nr, value);
1852 if (env->IBAT[0][nr] != value) {
1853 do_inval = 0;
1854 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1855 if (env->IBAT[1][nr] & 0x40) {
1856 /* Invalidate BAT only if it is valid */
1857#if !defined(FLUSH_ALL_TLBS)
1858 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1859#else
1860 do_inval = 1;
1861#endif
1862 }
1863 /* When storing valid upper BAT, mask BEPI and BRPN
1864 * and invalidate all TLBs covered by this BAT
1865 */
1866 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1867 (value & ~0x0001FFFFUL & ~mask);
1868 env->DBAT[0][nr] = env->IBAT[0][nr];
1869 if (env->IBAT[1][nr] & 0x40) {
1870#if !defined(FLUSH_ALL_TLBS)
1871 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1872#else
1873 do_inval = 1;
1874#endif
1875 }
1876#if defined(FLUSH_ALL_TLBS)
1877 if (do_inval)
1878 tlb_flush(env, 1);
1879#endif
1880 }
1881}
1882
45d827d2 1883void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
056401ea
JM		 1884{
1885 target_ulong mask;
1886 int do_inval;
1887
1888 dump_store_bat(env, 'I', 1, nr, value);
1889 if (env->IBAT[1][nr] != value) {
1890 do_inval = 0;
1891 if (env->IBAT[1][nr] & 0x40) {
1892#if !defined(FLUSH_ALL_TLBS)
1893 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1894 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1895#else
1896 do_inval = 1;
1897#endif
1898 }
1899 if (value & 0x40) {
1900#if !defined(FLUSH_ALL_TLBS)
1901 mask = (value << 17) & 0x0FFE0000UL;
1902 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1903#else
1904 do_inval = 1;
1905#endif
1906 }
1907 env->IBAT[1][nr] = value;
1908 env->DBAT[1][nr] = value;
1909#if defined(FLUSH_ALL_TLBS)
1910 if (do_inval)
1911 tlb_flush(env, 1);
1912#endif
1913 }
1914}
1915
0a032cbe
JM		 1916/*****************************************************************************/
1917/* TLB management */
1918void ppc_tlb_invalidate_all (CPUPPCState *env)
1919{
daf4f96e
JM		 1920 switch (env->mmu_model) {
1921 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1922 case POWERPC_MMU_SOFT_74xx:
0a032cbe 1923 ppc6xx_tlb_invalidate_all(env);
daf4f96e
JM		 1924 break;
1925 case POWERPC_MMU_SOFT_4xx:
1926 case POWERPC_MMU_SOFT_4xx_Z:
0a032cbe 1927 ppc4xx_tlb_invalidate_all(env);
daf4f96e 1928 break;
b4095fed 1929 case POWERPC_MMU_REAL:
7dbe11ac
JM		 1930 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1931 break;
b4095fed
JM		 1932 case POWERPC_MMU_MPC8xx:
1933 /* XXX: TODO */
1934 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1935 break;
7dbe11ac
JM		 1936 case POWERPC_MMU_BOOKE:
1937 /* XXX: TODO */
b4095fed 1938 cpu_abort(env, "BookE MMU model is not implemented\n");
7dbe11ac
JM		 1939 break;
1940 case POWERPC_MMU_BOOKE_FSL:
1941 /* XXX: TODO */
b4095fed 1942 cpu_abort(env, "BookE MMU model is not implemented\n");
7dbe11ac 1943 break;
7dbe11ac 1944 case POWERPC_MMU_32B:
faadf50e 1945 case POWERPC_MMU_601:
00af685f 1946#if defined(TARGET_PPC64)
add78955 1947 case POWERPC_MMU_620:
7dbe11ac 1948 case POWERPC_MMU_64B:
00af685f 1949#endif /* defined(TARGET_PPC64) */
0a032cbe 1950 tlb_flush(env, 1);
daf4f96e 1951 break;
00af685f
JM		 1952 default:
1953 /* XXX: TODO */
12de9a39 1954 cpu_abort(env, "Unknown MMU model\n");
00af685f 1955 break;
0a032cbe
JM		 1956 }
1957}
1958
daf4f96e
JM		 1959void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1960{
1961#if !defined(FLUSH_ALL_TLBS)
1962 addr &= TARGET_PAGE_MASK;
1963 switch (env->mmu_model) {
1964 case POWERPC_MMU_SOFT_6xx:
7dbe11ac 1965 case POWERPC_MMU_SOFT_74xx:
daf4f96e
JM		 1966 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1967 if (env->id_tlbs == 1)
1968 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1969 break;
1970 case POWERPC_MMU_SOFT_4xx:
1971 case POWERPC_MMU_SOFT_4xx_Z:
1972 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1973 break;
b4095fed 1974 case POWERPC_MMU_REAL:
7dbe11ac
JM		 1975 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1976 break;
b4095fed
JM		 1977 case POWERPC_MMU_MPC8xx:
1978 /* XXX: TODO */
1979 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1980 break;
7dbe11ac
JM		 1981 case POWERPC_MMU_BOOKE:
1982 /* XXX: TODO */
b4095fed 1983 cpu_abort(env, "BookE MMU model is not implemented\n");
7dbe11ac
JM		 1984 break;
1985 case POWERPC_MMU_BOOKE_FSL:
1986 /* XXX: TODO */
b4095fed 1987 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
7dbe11ac
JM		 1988 break;
1989 case POWERPC_MMU_32B:
faadf50e 1990 case POWERPC_MMU_601:
daf4f96e 1991 /* tlbie invalidate TLBs for all segments */
6f2d8978 1992 addr &= ~((target_ulong)-1ULL << 28);
daf4f96e
JM		 1993 /* XXX: this case should be optimized,
1994 * giving a mask to tlb_flush_page
1995 */
1996 tlb_flush_page(env, addr | (0x0 << 28));
1997 tlb_flush_page(env, addr | (0x1 << 28));
1998 tlb_flush_page(env, addr | (0x2 << 28));
1999 tlb_flush_page(env, addr | (0x3 << 28));
2000 tlb_flush_page(env, addr | (0x4 << 28));
2001 tlb_flush_page(env, addr | (0x5 << 28));
2002 tlb_flush_page(env, addr | (0x6 << 28));
2003 tlb_flush_page(env, addr | (0x7 << 28));
2004 tlb_flush_page(env, addr | (0x8 << 28));
2005 tlb_flush_page(env, addr | (0x9 << 28));
2006 tlb_flush_page(env, addr | (0xA << 28));
2007 tlb_flush_page(env, addr | (0xB << 28));
2008 tlb_flush_page(env, addr | (0xC << 28));
2009 tlb_flush_page(env, addr | (0xD << 28));
2010 tlb_flush_page(env, addr | (0xE << 28));
2011 tlb_flush_page(env, addr | (0xF << 28));
7dbe11ac 2012 break;
00af685f 2013#if defined(TARGET_PPC64)
add78955 2014 case POWERPC_MMU_620:
7dbe11ac 2015 case POWERPC_MMU_64B:
7dbe11ac
JM		 2016 /* tlbie invalidate TLBs for all segments */
2017 /* XXX: given the fact that there are too many segments to invalidate,
00af685f 2018 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
7dbe11ac
JM		 2019 * we just invalidate all TLBs
2020 */
2021 tlb_flush(env, 1);
2022 break;
00af685f
JM		 2023#endif /* defined(TARGET_PPC64) */
2024 default:
2025 /* XXX: TODO */
12de9a39 2026 cpu_abort(env, "Unknown MMU model\n");
00af685f 2027 break;
daf4f96e
JM		 2028 }
2029#else
2030 ppc_tlb_invalidate_all(env);
2031#endif
2032}
2033
3fc6c082
FB		 2034/*****************************************************************************/
2035/* Special registers manipulation */
d9bce9d9 2036#if defined(TARGET_PPC64)
d9bce9d9
JM		 2037void ppc_store_asr (CPUPPCState *env, target_ulong value)
2038{
2039 if (env->asr != value) {
2040 env->asr = value;
2041 tlb_flush(env, 1);
2042 }
2043}
2044#endif
2045
45d827d2 2046void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
3fc6c082
FB		 2047{
2048#if defined (DEBUG_MMU)
2049 if (loglevel != 0) {
6b542af7 2050 fprintf(logfile, "%s: " ADDRX "\n", __func__, value);
3fc6c082
FB		 2051 }
2052#endif
2053 if (env->sdr1 != value) {
12de9a39
JM		 2054 /* XXX: for PowerPC 64, should check that the HTABSIZE value
2055 * is <= 28
2056 */
3fc6c082 2057 env->sdr1 = value;
76a66253 2058 tlb_flush(env, 1);
3fc6c082
FB		 2059 }
2060}
2061
45d827d2 2062void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
3fc6c082
FB		 2063{
2064#if defined (DEBUG_MMU)
2065 if (loglevel != 0) {
6b542af7 2066 fprintf(logfile, "%s: reg=%d " ADDRX " " ADDRX "\n",
1b9eb036 2067 __func__, srnum, value, env->sr[srnum]);
3fc6c082
FB		 2068 }
2069#endif
2070 if (env->sr[srnum] != value) {
2071 env->sr[srnum] = value;
2072#if !defined(FLUSH_ALL_TLBS) && 0
2073 {
2074 target_ulong page, end;
2075 /* Invalidate 256 MB of virtual memory */
2076 page = (16 << 20) * srnum;
2077 end = page + (16 << 20);
2078 for (; page != end; page += TARGET_PAGE_SIZE)
2079 tlb_flush_page(env, page);
2080 }
2081#else
76a66253 2082 tlb_flush(env, 1);
3fc6c082
FB		 2083#endif
2084 }
2085}
76a66253 2086#endif /* !defined (CONFIG_USER_ONLY) */
3fc6c082 2087
76a66253 2088/* GDBstub can read and write MSR... */
0411a972 2089void ppc_store_msr (CPUPPCState *env, target_ulong value)
3fc6c082 2090{
a4f30719 2091 hreg_store_msr(env, value, 0);
3fc6c082
FB		 2092}
2093
2094/*****************************************************************************/
2095/* Exception processing */
18fba28c 2096#if defined (CONFIG_USER_ONLY)
9a64fbe4 2097void do_interrupt (CPUState *env)
79aceca5 2098{
e1833e1f
JM		 2099 env->exception_index = POWERPC_EXCP_NONE;
2100 env->error_code = 0;
18fba28c 2101}
47103572 2102
e9df014c 2103void ppc_hw_interrupt (CPUState *env)
47103572 2104{
e1833e1f
JM		 2105 env->exception_index = POWERPC_EXCP_NONE;
2106 env->error_code = 0;
47103572 2107}
76a66253 2108#else /* defined (CONFIG_USER_ONLY) */
a11b8151 2109static always_inline void dump_syscall (CPUState *env)
d094807b 2110{
6b542af7
JM		 2111 fprintf(logfile, "syscall r0=" REGX " r3=" REGX " r4=" REGX
2112 " r5=" REGX " r6=" REGX " nip=" ADDRX "\n",
2113 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
2114 ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip);
d094807b
FB		 2115}
2116
e1833e1f
JM		 2117/* Note that this function should be greatly optimized
2118 * when called with a constant excp, from ppc_hw_interrupt
2119 */
2120static always_inline void powerpc_excp (CPUState *env,
2121 int excp_model, int excp)
18fba28c 2122{
0411a972 2123 target_ulong msr, new_msr, vector;
e1833e1f 2124 int srr0, srr1, asrr0, asrr1;
a4f30719 2125 int lpes0, lpes1, lev;
79aceca5 2126
b172c56a
JM		 2127 if (0) {
2128 /* XXX: find a suitable condition to enable the hypervisor mode */
2129 lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
2130 lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
2131 } else {
2132 /* Those values ensure we won't enter the hypervisor mode */
2133 lpes0 = 0;
2134 lpes1 = 1;
2135 }
2136
b769d8fe 2137 if (loglevel & CPU_LOG_INT) {
6b542af7 2138 fprintf(logfile, "Raise exception at " ADDRX " => %08x (%02x)\n",
1b9eb036 2139 env->nip, excp, env->error_code);
b769d8fe 2140 }
0411a972
JM		 2141 msr = env->msr;
2142 new_msr = msr;
e1833e1f
JM		 2143 srr0 = SPR_SRR0;
2144 srr1 = SPR_SRR1;
2145 asrr0 = -1;
2146 asrr1 = -1;
2147 msr &= ~((target_ulong)0x783F0000);
9a64fbe4 2148 switch (excp) {
e1833e1f
JM		 2149 case POWERPC_EXCP_NONE:
2150 /* Should never happen */
2151 return;
2152 case POWERPC_EXCP_CRITICAL: /* Critical input */
0411a972 2153 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
e1833e1f 2154 switch (excp_model) {
a750fc0b 2155 case POWERPC_EXCP_40x:
e1833e1f
JM		 2156 srr0 = SPR_40x_SRR2;
2157 srr1 = SPR_40x_SRR3;
c62db105 2158 break;
a750fc0b 2159 case POWERPC_EXCP_BOOKE:
e1833e1f
JM		 2160 srr0 = SPR_BOOKE_CSRR0;
2161 srr1 = SPR_BOOKE_CSRR1;
c62db105 2162 break;
e1833e1f 2163 case POWERPC_EXCP_G2:
c62db105 2164 break;
e1833e1f
JM		 2165 default:
2166 goto excp_invalid;
2be0071f 2167 }
9a64fbe4 2168 goto store_next;
e1833e1f
JM		 2169 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2170 if (msr_me == 0) {
e63ecc6f
JM		 2171 /* Machine check exception is not enabled.
2172 * Enter checkstop state.
2173 */
2174 if (loglevel != 0) {
2175 fprintf(logfile, "Machine check while not allowed. "
2176 "Entering checkstop state\n");
2177 } else {
2178 fprintf(stderr, "Machine check while not allowed. "
2179 "Entering checkstop state\n");
2180 }
2181 env->halted = 1;
2182 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
e1833e1f 2183 }
0411a972
JM		 2184 new_msr &= ~((target_ulong)1 << MSR_RI);
2185 new_msr &= ~((target_ulong)1 << MSR_ME);
b172c56a
JM		 2186 if (0) {
2187 /* XXX: find a suitable condition to enable the hypervisor mode */
a4f30719 2188 new_msr |= (target_ulong)MSR_HVB;
b172c56a 2189 }
e1833e1f
JM		 2190 /* XXX: should also have something loaded in DAR / DSISR */
2191 switch (excp_model) {
a750fc0b 2192 case POWERPC_EXCP_40x:
e1833e1f
JM		 2193 srr0 = SPR_40x_SRR2;
2194 srr1 = SPR_40x_SRR3;
c62db105 2195 break;
a750fc0b 2196 case POWERPC_EXCP_BOOKE:
e1833e1f
JM		 2197 srr0 = SPR_BOOKE_MCSRR0;
2198 srr1 = SPR_BOOKE_MCSRR1;
2199 asrr0 = SPR_BOOKE_CSRR0;
2200 asrr1 = SPR_BOOKE_CSRR1;
c62db105
JM		 2201 break;
2202 default:
2203 break;
2be0071f 2204 }
e1833e1f
JM		 2205 goto store_next;
2206 case POWERPC_EXCP_DSI: /* Data storage exception */
a541f297 2207#if defined (DEBUG_EXCEPTIONS)
4a057712 2208 if (loglevel != 0) {
6b542af7
JM		 2209 fprintf(logfile, "DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
2210 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
76a66253 2211 }
e1833e1f 2212#endif
0411a972 2213 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2214 if (lpes1 == 0)
a4f30719 2215 new_msr |= (target_ulong)MSR_HVB;
a541f297 2216 goto store_next;
e1833e1f 2217 case POWERPC_EXCP_ISI: /* Instruction storage exception */
a541f297 2218#if defined (DEBUG_EXCEPTIONS)
76a66253 2219 if (loglevel != 0) {
6b542af7
JM		 2220 fprintf(logfile, "ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
2221 msr, env->nip);
76a66253 2222 }
a541f297 2223#endif
0411a972 2224 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2225 if (lpes1 == 0)
a4f30719 2226 new_msr |= (target_ulong)MSR_HVB;
e1833e1f 2227 msr |= env->error_code;
9a64fbe4 2228 goto store_next;
e1833e1f 2229 case POWERPC_EXCP_EXTERNAL: /* External input */
0411a972 2230 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2231 if (lpes0 == 1)
a4f30719 2232 new_msr |= (target_ulong)MSR_HVB;
9a64fbe4 2233 goto store_next;
e1833e1f 2234 case POWERPC_EXCP_ALIGN: /* Alignment exception */
0411a972 2235 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2236 if (lpes1 == 0)
a4f30719 2237 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2238 /* XXX: this is false */
2239 /* Get rS/rD and rA from faulting opcode */
2240 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
9a64fbe4 2241 goto store_current;
e1833e1f 2242 case POWERPC_EXCP_PROGRAM: /* Program exception */
9a64fbe4 2243 switch (env->error_code & ~0xF) {
e1833e1f
JM		 2244 case POWERPC_EXCP_FP:
2245 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
9a64fbe4 2246#if defined (DEBUG_EXCEPTIONS)
4a057712 2247 if (loglevel != 0) {
a496775f
JM		 2248 fprintf(logfile, "Ignore floating point exception\n");
2249 }
9a64fbe4 2250#endif
7c58044c
JM		 2251 env->exception_index = POWERPC_EXCP_NONE;
2252 env->error_code = 0;
9a64fbe4 2253 return;
76a66253 2254 }
0411a972 2255 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2256 if (lpes1 == 0)
a4f30719 2257 new_msr |= (target_ulong)MSR_HVB;
9a64fbe4 2258 msr |= 0x00100000;
5b52b991
JM		 2259 if (msr_fe0 == msr_fe1)
2260 goto store_next;
2261 msr |= 0x00010000;
76a66253 2262 break;
e1833e1f 2263 case POWERPC_EXCP_INVAL:
a496775f 2264#if defined (DEBUG_EXCEPTIONS)
4a057712 2265 if (loglevel != 0) {
6b542af7 2266 fprintf(logfile, "Invalid instruction at " ADDRX "\n",
a496775f
JM		 2267 env->nip);
2268 }
e1833e1f 2269#endif
0411a972 2270 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2271 if (lpes1 == 0)
a4f30719 2272 new_msr |= (target_ulong)MSR_HVB;
9a64fbe4 2273 msr |= 0x00080000;
76a66253 2274 break;
e1833e1f 2275 case POWERPC_EXCP_PRIV:
0411a972 2276 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2277 if (lpes1 == 0)
a4f30719 2278 new_msr |= (target_ulong)MSR_HVB;
9a64fbe4 2279 msr |= 0x00040000;
76a66253 2280 break;
e1833e1f 2281 case POWERPC_EXCP_TRAP:
0411a972 2282 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2283 if (lpes1 == 0)
a4f30719 2284 new_msr |= (target_ulong)MSR_HVB;
9a64fbe4
FB		 2285 msr |= 0x00020000;
2286 break;
2287 default:
2288 /* Should never occur */
e1833e1f
JM		 2289 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2290 env->error_code);
76a66253
JM		 2291 break;
2292 }
5b52b991 2293 goto store_current;
e1833e1f 2294 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
0411a972 2295 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2296 if (lpes1 == 0)
a4f30719 2297 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2298 goto store_current;
2299 case POWERPC_EXCP_SYSCALL: /* System call exception */
d094807b
FB		 2300 /* NOTE: this is a temporary hack to support graphics OSI
2301 calls from the MOL driver */
e1833e1f 2302 /* XXX: To be removed */
d094807b
FB		 2303 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2304 env->osi_call) {
7c58044c
JM		 2305 if (env->osi_call(env) != 0) {
2306 env->exception_index = POWERPC_EXCP_NONE;
2307 env->error_code = 0;
d094807b 2308 return;
7c58044c 2309 }
d094807b 2310 }
b769d8fe 2311 if (loglevel & CPU_LOG_INT) {
d094807b 2312 dump_syscall(env);
b769d8fe 2313 }
0411a972 2314 new_msr &= ~((target_ulong)1 << MSR_RI);
f9fdea6b 2315 lev = env->error_code;
e1833e1f 2316 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
a4f30719 2317 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2318 goto store_next;
2319 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
0411a972 2320 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f
JM		 2321 goto store_current;
2322 case POWERPC_EXCP_DECR: /* Decrementer exception */
0411a972 2323 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2324 if (lpes1 == 0)
a4f30719 2325 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2326 goto store_next;
2327 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2328 /* FIT on 4xx */
2329#if defined (DEBUG_EXCEPTIONS)
2330 if (loglevel != 0)
2331 fprintf(logfile, "FIT exception\n");
2332#endif
0411a972 2333 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
9a64fbe4 2334 goto store_next;
e1833e1f
JM		 2335 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2336#if defined (DEBUG_EXCEPTIONS)
2337 if (loglevel != 0)
2338 fprintf(logfile, "WDT exception\n");
2339#endif
2340 switch (excp_model) {
2341 case POWERPC_EXCP_BOOKE:
2342 srr0 = SPR_BOOKE_CSRR0;
2343 srr1 = SPR_BOOKE_CSRR1;
2344 break;
2345 default:
2346 break;
2347 }
0411a972 2348 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2be0071f 2349 goto store_next;
e1833e1f 2350 case POWERPC_EXCP_DTLB: /* Data TLB error */
0411a972 2351 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
e1833e1f
JM		 2352 goto store_next;
2353 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
0411a972 2354 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
e1833e1f
JM		 2355 goto store_next;
2356 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2357 switch (excp_model) {
2358 case POWERPC_EXCP_BOOKE:
2359 srr0 = SPR_BOOKE_DSRR0;
2360 srr1 = SPR_BOOKE_DSRR1;
2361 asrr0 = SPR_BOOKE_CSRR0;
2362 asrr1 = SPR_BOOKE_CSRR1;
2363 break;
2364 default:
2365 break;
2366 }
2be0071f 2367 /* XXX: TODO */
e1833e1f 2368 cpu_abort(env, "Debug exception is not implemented yet !\n");
2be0071f 2369 goto store_next;
e1833e1f 2370 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
0411a972 2371 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
e1833e1f
JM		 2372 goto store_current;
2373 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2be0071f 2374 /* XXX: TODO */
e1833e1f 2375 cpu_abort(env, "Embedded floating point data exception "
2be0071f
FB		 2376 "is not implemented yet !\n");
2377 goto store_next;
e1833e1f 2378 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2be0071f 2379 /* XXX: TODO */
e1833e1f
JM		 2380 cpu_abort(env, "Embedded floating point round exception "
2381 "is not implemented yet !\n");
9a64fbe4 2382 goto store_next;
e1833e1f 2383 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
0411a972 2384 new_msr &= ~((target_ulong)1 << MSR_RI);
2be0071f
FB		 2385 /* XXX: TODO */
2386 cpu_abort(env,
e1833e1f 2387 "Performance counter exception is not implemented yet !\n");
9a64fbe4 2388 goto store_next;
e1833e1f 2389 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
76a66253 2390 /* XXX: TODO */
e1833e1f
JM		 2391 cpu_abort(env,
2392 "Embedded doorbell interrupt is not implemented yet !\n");
2be0071f 2393 goto store_next;
e1833e1f
JM		 2394 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2395 switch (excp_model) {
2396 case POWERPC_EXCP_BOOKE:
2397 srr0 = SPR_BOOKE_CSRR0;
2398 srr1 = SPR_BOOKE_CSRR1;
a750fc0b 2399 break;
2be0071f 2400 default:
2be0071f
FB		 2401 break;
2402 }
e1833e1f
JM		 2403 /* XXX: TODO */
2404 cpu_abort(env, "Embedded doorbell critical interrupt "
2405 "is not implemented yet !\n");
2406 goto store_next;
e1833e1f 2407 case POWERPC_EXCP_RESET: /* System reset exception */
0411a972 2408 new_msr &= ~((target_ulong)1 << MSR_RI);
a4f30719
JM		 2409 if (0) {
2410 /* XXX: find a suitable condition to enable the hypervisor mode */
2411 new_msr |= (target_ulong)MSR_HVB;
2412 }
e1833e1f 2413 goto store_next;
e1833e1f 2414 case POWERPC_EXCP_DSEG: /* Data segment exception */
0411a972 2415 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2416 if (lpes1 == 0)
a4f30719 2417 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2418 goto store_next;
2419 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
0411a972 2420 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2421 if (lpes1 == 0)
a4f30719 2422 new_msr |= (target_ulong)MSR_HVB;
e1833e1f 2423 goto store_next;
e1833e1f
JM		 2424 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2425 srr0 = SPR_HSRR0;
f9fdea6b 2426 srr1 = SPR_HSRR1;
a4f30719 2427 new_msr |= (target_ulong)MSR_HVB;
b172c56a 2428 goto store_next;
e1833e1f 2429 case POWERPC_EXCP_TRACE: /* Trace exception */
0411a972 2430 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2431 if (lpes1 == 0)
a4f30719 2432 new_msr |= (target_ulong)MSR_HVB;
e1833e1f 2433 goto store_next;
e1833e1f
JM		 2434 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2435 srr0 = SPR_HSRR0;
f9fdea6b 2436 srr1 = SPR_HSRR1;
a4f30719 2437 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2438 goto store_next;
2439 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2440 srr0 = SPR_HSRR0;
f9fdea6b 2441 srr1 = SPR_HSRR1;
a4f30719 2442 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2443 goto store_next;
2444 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2445 srr0 = SPR_HSRR0;
f9fdea6b 2446 srr1 = SPR_HSRR1;
a4f30719 2447 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2448 goto store_next;
2449 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2450 srr0 = SPR_HSRR0;
f9fdea6b 2451 srr1 = SPR_HSRR1;
a4f30719 2452 new_msr |= (target_ulong)MSR_HVB;
e1833e1f 2453 goto store_next;
e1833e1f 2454 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
0411a972 2455 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2456 if (lpes1 == 0)
a4f30719 2457 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2458 goto store_current;
2459 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
a496775f 2460#if defined (DEBUG_EXCEPTIONS)
e1833e1f
JM		 2461 if (loglevel != 0)
2462 fprintf(logfile, "PIT exception\n");
2463#endif
0411a972 2464 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
e1833e1f
JM		 2465 goto store_next;
2466 case POWERPC_EXCP_IO: /* IO error exception */
2467 /* XXX: TODO */
2468 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2469 goto store_next;
2470 case POWERPC_EXCP_RUNM: /* Run mode exception */
2471 /* XXX: TODO */
2472 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2473 goto store_next;
2474 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2475 /* XXX: TODO */
2476 cpu_abort(env, "602 emulation trap exception "
2477 "is not implemented yet !\n");
2478 goto store_next;
2479 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
0411a972 2480 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
a4f30719
JM		 2481 if (lpes1 == 0) /* XXX: check this */
2482 new_msr |= (target_ulong)MSR_HVB;
e1833e1f 2483 switch (excp_model) {
a750fc0b
JM		 2484 case POWERPC_EXCP_602:
2485 case POWERPC_EXCP_603:
2486 case POWERPC_EXCP_603E:
2487 case POWERPC_EXCP_G2:
e1833e1f 2488 goto tlb_miss_tgpr;
a750fc0b 2489 case POWERPC_EXCP_7x5:
76a66253 2490 goto tlb_miss;
7dbe11ac
JM		 2491 case POWERPC_EXCP_74xx:
2492 goto tlb_miss_74xx;
2be0071f 2493 default:
e1833e1f 2494 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2be0071f
FB		 2495 break;
2496 }
e1833e1f
JM		 2497 break;
2498 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
0411a972 2499 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
a4f30719
JM		 2500 if (lpes1 == 0) /* XXX: check this */
2501 new_msr |= (target_ulong)MSR_HVB;
e1833e1f 2502 switch (excp_model) {
a750fc0b
JM		 2503 case POWERPC_EXCP_602:
2504 case POWERPC_EXCP_603:
2505 case POWERPC_EXCP_603E:
2506 case POWERPC_EXCP_G2:
e1833e1f 2507 goto tlb_miss_tgpr;
a750fc0b 2508 case POWERPC_EXCP_7x5:
76a66253 2509 goto tlb_miss;
7dbe11ac
JM		 2510 case POWERPC_EXCP_74xx:
2511 goto tlb_miss_74xx;
2be0071f 2512 default:
e1833e1f 2513 cpu_abort(env, "Invalid data load TLB miss exception\n");
2be0071f
FB		 2514 break;
2515 }
e1833e1f
JM		 2516 break;
2517 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
0411a972 2518 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
a4f30719
JM		 2519 if (lpes1 == 0) /* XXX: check this */
2520 new_msr |= (target_ulong)MSR_HVB;
e1833e1f 2521 switch (excp_model) {
a750fc0b
JM		 2522 case POWERPC_EXCP_602:
2523 case POWERPC_EXCP_603:
2524 case POWERPC_EXCP_603E:
2525 case POWERPC_EXCP_G2:
e1833e1f 2526 tlb_miss_tgpr:
76a66253 2527 /* Swap temporary saved registers with GPRs */
0411a972
JM		 2528 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
2529 new_msr |= (target_ulong)1 << MSR_TGPR;
2530 hreg_swap_gpr_tgpr(env);
2531 }
e1833e1f
JM		 2532 goto tlb_miss;
2533 case POWERPC_EXCP_7x5:
2534 tlb_miss:
2be0071f
FB		 2535#if defined (DEBUG_SOFTWARE_TLB)
2536 if (loglevel != 0) {
76a66253
JM		 2537 const unsigned char *es;
2538 target_ulong *miss, *cmp;
2539 int en;
1e6784f9 2540 if (excp == POWERPC_EXCP_IFTLB) {
76a66253
JM		 2541 es = "I";
2542 en = 'I';
2543 miss = &env->spr[SPR_IMISS];
2544 cmp = &env->spr[SPR_ICMP];
2545 } else {
1e6784f9 2546 if (excp == POWERPC_EXCP_DLTLB)
76a66253
JM		 2547 es = "DL";
2548 else
2549 es = "DS";
2550 en = 'D';
2551 miss = &env->spr[SPR_DMISS];
2552 cmp = &env->spr[SPR_DCMP];
2553 }
1b9eb036 2554 fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
4a057712 2555 " H1 " ADDRX " H2 " ADDRX " %08x\n",
1b9eb036 2556 es, en, *miss, en, *cmp,
76a66253 2557 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2be0071f
FB		 2558 env->error_code);
2559 }
9a64fbe4 2560#endif
2be0071f
FB		 2561 msr |= env->crf[0] << 28;
2562 msr |= env->error_code; /* key, D/I, S/L bits */
2563 /* Set way using a LRU mechanism */
76a66253 2564 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
c62db105 2565 break;
7dbe11ac
JM		 2566 case POWERPC_EXCP_74xx:
2567 tlb_miss_74xx:
2568#if defined (DEBUG_SOFTWARE_TLB)
2569 if (loglevel != 0) {
2570 const unsigned char *es;
2571 target_ulong *miss, *cmp;
2572 int en;
2573 if (excp == POWERPC_EXCP_IFTLB) {
2574 es = "I";
2575 en = 'I';
0411a972
JM		 2576 miss = &env->spr[SPR_TLBMISS];
2577 cmp = &env->spr[SPR_PTEHI];
7dbe11ac
JM		 2578 } else {
2579 if (excp == POWERPC_EXCP_DLTLB)
2580 es = "DL";
2581 else
2582 es = "DS";
2583 en = 'D';
2584 miss = &env->spr[SPR_TLBMISS];
2585 cmp = &env->spr[SPR_PTEHI];
2586 }
2587 fprintf(logfile, "74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2588 " %08x\n",
2589 es, en, *miss, en, *cmp, env->error_code);
2590 }
2591#endif
2592 msr |= env->error_code; /* key bit */
2593 break;
2be0071f 2594 default:
e1833e1f 2595 cpu_abort(env, "Invalid data store TLB miss exception\n");
2be0071f
FB		 2596 break;
2597 }
e1833e1f
JM		 2598 goto store_next;
2599 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2600 /* XXX: TODO */
2601 cpu_abort(env, "Floating point assist exception "
2602 "is not implemented yet !\n");
2603 goto store_next;
b4095fed
JM		 2604 case POWERPC_EXCP_DABR: /* Data address breakpoint */
2605 /* XXX: TODO */
2606 cpu_abort(env, "DABR exception is not implemented yet !\n");
2607 goto store_next;
e1833e1f
JM		 2608 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2609 /* XXX: TODO */
2610 cpu_abort(env, "IABR exception is not implemented yet !\n");
2611 goto store_next;
2612 case POWERPC_EXCP_SMI: /* System management interrupt */
2613 /* XXX: TODO */
2614 cpu_abort(env, "SMI exception is not implemented yet !\n");
2615 goto store_next;
2616 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2617 /* XXX: TODO */
2618 cpu_abort(env, "Thermal management exception "
2619 "is not implemented yet !\n");
2620 goto store_next;
2621 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
0411a972 2622 new_msr &= ~((target_ulong)1 << MSR_RI);
e1833e1f 2623 if (lpes1 == 0)
a4f30719 2624 new_msr |= (target_ulong)MSR_HVB;
e1833e1f
JM		 2625 /* XXX: TODO */
2626 cpu_abort(env,
2627 "Performance counter exception is not implemented yet !\n");
2628 goto store_next;
2629 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2630 /* XXX: TODO */
2631 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2632 goto store_next;
2633 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2634 /* XXX: TODO */
2635 cpu_abort(env,
2636 "970 soft-patch exception is not implemented yet !\n");
2637 goto store_next;
2638 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2639 /* XXX: TODO */
2640 cpu_abort(env,
2641 "970 maintenance exception is not implemented yet !\n");
2642 goto store_next;
b4095fed
JM		 2643 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
2644 /* XXX: TODO */
2645 cpu_abort(env, "Maskable external exception "
2646 "is not implemented yet !\n");
2647 goto store_next;
2648 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
2649 /* XXX: TODO */
2650 cpu_abort(env, "Non maskable external exception "
2651 "is not implemented yet !\n");
2652 goto store_next;
2be0071f 2653 default:
e1833e1f
JM		 2654 excp_invalid:
2655 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2656 break;
9a64fbe4 2657 store_current:
2be0071f 2658 /* save current instruction location */
e1833e1f 2659 env->spr[srr0] = env->nip - 4;
9a64fbe4
FB		 2660 break;
2661 store_next:
2be0071f 2662 /* save next instruction location */
e1833e1f 2663 env->spr[srr0] = env->nip;
9a64fbe4
FB		 2664 break;
2665 }
e1833e1f
JM		 2666 /* Save MSR */
2667 env->spr[srr1] = msr;
2668 /* If any alternate SRR register are defined, duplicate saved values */
2669 if (asrr0 != -1)
2670 env->spr[asrr0] = env->spr[srr0];
2671 if (asrr1 != -1)
2672 env->spr[asrr1] = env->spr[srr1];
2be0071f 2673 /* If we disactivated any translation, flush TLBs */
0411a972 2674 if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
2be0071f 2675 tlb_flush(env, 1);
9a64fbe4 2676 /* reload MSR with correct bits */
0411a972
JM		 2677 new_msr &= ~((target_ulong)1 << MSR_EE);
2678 new_msr &= ~((target_ulong)1 << MSR_PR);
2679 new_msr &= ~((target_ulong)1 << MSR_FP);
2680 new_msr &= ~((target_ulong)1 << MSR_FE0);
2681 new_msr &= ~((target_ulong)1 << MSR_SE);
2682 new_msr &= ~((target_ulong)1 << MSR_BE);
2683 new_msr &= ~((target_ulong)1 << MSR_FE1);
2684 new_msr &= ~((target_ulong)1 << MSR_IR);
2685 new_msr &= ~((target_ulong)1 << MSR_DR);
e1833e1f 2686#if 0 /* Fix this: not on all targets */
0411a972 2687 new_msr &= ~((target_ulong)1 << MSR_PMM);
e1833e1f 2688#endif
0411a972
JM		 2689 new_msr &= ~((target_ulong)1 << MSR_LE);
2690 if (msr_ile)
2691 new_msr |= (target_ulong)1 << MSR_LE;
2692 else
2693 new_msr &= ~((target_ulong)1 << MSR_LE);
e1833e1f
JM		 2694 /* Jump to handler */
2695 vector = env->excp_vectors[excp];
6f2d8978 2696 if (vector == (target_ulong)-1ULL) {
e1833e1f
JM		 2697 cpu_abort(env, "Raised an exception without defined vector %d\n",
2698 excp);
2699 }
2700 vector |= env->excp_prefix;
c62db105 2701#if defined(TARGET_PPC64)
e1833e1f 2702 if (excp_model == POWERPC_EXCP_BOOKE) {
0411a972
JM		 2703 if (!msr_icm) {
2704 new_msr &= ~((target_ulong)1 << MSR_CM);
e1833e1f 2705 vector = (uint32_t)vector;
0411a972
JM		 2706 } else {
2707 new_msr |= (target_ulong)1 << MSR_CM;
2708 }
c62db105 2709 } else {
0411a972
JM		 2710 if (!msr_isf) {
2711 new_msr &= ~((target_ulong)1 << MSR_SF);
e1833e1f 2712 vector = (uint32_t)vector;
0411a972
JM		 2713 } else {
2714 new_msr |= (target_ulong)1 << MSR_SF;
2715 }
c62db105 2716 }
e1833e1f 2717#endif
0411a972
JM		 2718 /* XXX: we don't use hreg_store_msr here as already have treated
2719 * any special case that could occur. Just store MSR and update hflags
2720 */
a4f30719 2721 env->msr = new_msr & env->msr_mask;
0411a972 2722 hreg_compute_hflags(env);
e1833e1f
JM		 2723 env->nip = vector;
2724 /* Reset exception state */
2725 env->exception_index = POWERPC_EXCP_NONE;
2726 env->error_code = 0;
fb0eaffc 2727}
47103572 2728
e1833e1f 2729void do_interrupt (CPUState *env)
47103572 2730{
e1833e1f
JM		 2731 powerpc_excp(env, env->excp_model, env->exception_index);
2732}
47103572 2733
e1833e1f
JM		 2734void ppc_hw_interrupt (CPUPPCState *env)
2735{
f9fdea6b 2736 int hdice;
f9fdea6b 2737
0411a972 2738#if 0
a496775f
JM		 2739 if (loglevel & CPU_LOG_INT) {
2740 fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2741 __func__, env, env->pending_interrupts,
0411a972 2742 env->interrupt_request, (int)msr_me, (int)msr_ee);
a496775f 2743 }
47103572 2744#endif
e1833e1f 2745 /* External reset */
47103572 2746 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
47103572 2747 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
e1833e1f
JM		 2748 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2749 return;
2750 }
2751 /* Machine check exception */
2752 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2753 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2754 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2755 return;
47103572 2756 }
e1833e1f
JM		 2757#if 0 /* TODO */
2758 /* External debug exception */
2759 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2760 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2761 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2762 return;
2763 }
2764#endif
b172c56a
JM		 2765 if (0) {
2766 /* XXX: find a suitable condition to enable the hypervisor mode */
2767 hdice = env->spr[SPR_LPCR] & 1;
2768 } else {
2769 hdice = 0;
2770 }
f9fdea6b 2771 if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
47103572
JM		 2772 /* Hypervisor decrementer exception */
2773 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
47103572 2774 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
e1833e1f
JM		 2775 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2776 return;
2777 }
2778 }
e1833e1f
JM		 2779 if (msr_ce != 0) {
2780 /* External critical interrupt */
2781 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2782 /* Taking a critical external interrupt does not clear the external
2783 * critical interrupt status
2784 */
2785#if 0
2786 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
47103572 2787#endif
e1833e1f
JM		 2788 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2789 return;
2790 }
2791 }
2792 if (msr_ee != 0) {
2793 /* Watchdog timer on embedded PowerPC */
2794 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2795 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2796 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2797 return;
2798 }
e1833e1f
JM		 2799 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2800 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2801 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2802 return;
2803 }
e1833e1f
JM		 2804 /* Fixed interval timer on embedded PowerPC */
2805 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2806 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2807 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2808 return;
2809 }
2810 /* Programmable interval timer on embedded PowerPC */
2811 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2812 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2813 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2814 return;
2815 }
47103572
JM		 2816 /* Decrementer exception */
2817 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
47103572 2818 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
e1833e1f
JM		 2819 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2820 return;
2821 }
47103572 2822 /* External interrupt */
e1833e1f 2823 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
e9df014c
JM		 2824 /* Taking an external interrupt does not clear the external
2825 * interrupt status
2826 */
2827#if 0
47103572 2828 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
e9df014c 2829#endif
e1833e1f
JM		 2830 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2831 return;
2832 }
e1833e1f
JM		 2833 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2834 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2835 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2836 return;
47103572 2837 }
e1833e1f
JM		 2838 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2839 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2840 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2841 return;
2842 }
2843 /* Thermal interrupt */
2844 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2845 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2846 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2847 return;
2848 }
47103572 2849 }
47103572 2850}
18fba28c 2851#endif /* !CONFIG_USER_ONLY */
a496775f 2852
4a057712
JM		 2853void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2854{
2855 FILE *f;
2856
2857 if (logfile) {
2858 f = logfile;
2859 } else {
2860 f = stdout;
2861 return;
2862 }
2863 fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2864 RA, msr);
a496775f
JM		 2865}
2866
0a032cbe
JM		 2867void cpu_ppc_reset (void *opaque)
2868{
2869 CPUPPCState *env;
0411a972 2870 target_ulong msr;
0a032cbe
JM		 2871
2872 env = opaque;
0411a972 2873 msr = (target_ulong)0;
a4f30719
JM		 2874 if (0) {
2875 /* XXX: find a suitable condition to enable the hypervisor mode */
2876 msr |= (target_ulong)MSR_HVB;
2877 }
0411a972
JM		 2878 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
2879 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
2880 msr |= (target_ulong)1 << MSR_EP;
0a032cbe
JM		 2881#if defined (DO_SINGLE_STEP) && 0
2882 /* Single step trace mode */
0411a972
JM		 2883 msr |= (target_ulong)1 << MSR_SE;
2884 msr |= (target_ulong)1 << MSR_BE;
0a032cbe
JM		 2885#endif
2886#if defined(CONFIG_USER_ONLY)
0411a972 2887 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
4c2ab988
AJ		 2888 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
2889 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
0411a972 2890 msr |= (target_ulong)1 << MSR_PR;
fe463b7d 2891 env->msr = msr & env->msr_mask;
fe33cc71 2892#else
1c27f8fb 2893 env->nip = env->hreset_vector | env->excp_prefix;
b4095fed 2894 if (env->mmu_model != POWERPC_MMU_REAL)
141c8ae2 2895 ppc_tlb_invalidate_all(env);
0a032cbe 2896#endif
0411a972 2897 hreg_compute_hflags(env);
6f2d8978 2898 env->reserve = (target_ulong)-1ULL;
5eb7995e
JM		 2899 /* Be sure no exception or interrupt is pending */
2900 env->pending_interrupts = 0;
e1833e1f
JM		 2901 env->exception_index = POWERPC_EXCP_NONE;
2902 env->error_code = 0;
5eb7995e
JM		 2903 /* Flush all TLBs */
2904 tlb_flush(env, 1);
0a032cbe
JM		 2905}
2906
aaed909a 2907CPUPPCState *cpu_ppc_init (const char *cpu_model)
0a032cbe
JM		 2908{
2909 CPUPPCState *env;
aaed909a
FB		 2910 const ppc_def_t *def;
2911
2912 def = cpu_ppc_find_by_name(cpu_model);
2913 if (!def)
2914 return NULL;
0a032cbe
JM		 2915
2916 env = qemu_mallocz(sizeof(CPUPPCState));
2917 if (!env)
2918 return NULL;
2919 cpu_exec_init(env);
2e70f6ef 2920 ppc_translate_init();
01ba9816 2921 env->cpu_model_str = cpu_model;
aaed909a
FB		 2922 cpu_ppc_register_internal(env, def);
2923 cpu_ppc_reset(env);
d76d1650
AJ		 2924
2925 if (kvm_enabled())
2926 kvm_init_vcpu(env);
2927
0a032cbe
JM		 2928 return env;
2929}
2930
2931void cpu_ppc_close (CPUPPCState *env)
2932{
2933 /* Should also remove all opcode tables... */
aaed909a 2934 qemu_free(env);
0a032cbe 2935}
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