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Commit | Line | Data |
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d76d1650 AJ |
1 | /* |
2 | * PowerPC implementation of KVM hooks | |
3 | * | |
4 | * Copyright IBM Corp. 2007 | |
5 | * | |
6 | * Authors: | |
7 | * Jerone Young <jyoung5@us.ibm.com> | |
8 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
9 | * Hollis Blanchard <hollisb@us.ibm.com> | |
10 | * | |
11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
12 | * See the COPYING file in the top-level directory. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <sys/types.h> | |
17 | #include <sys/ioctl.h> | |
18 | #include <sys/mman.h> | |
19 | ||
20 | #include <linux/kvm.h> | |
21 | ||
22 | #include "qemu-common.h" | |
23 | #include "qemu-timer.h" | |
24 | #include "sysemu.h" | |
25 | #include "kvm.h" | |
26 | #include "kvm_ppc.h" | |
27 | #include "cpu.h" | |
28 | #include "device_tree.h" | |
29 | ||
30 | //#define DEBUG_KVM | |
31 | ||
32 | #ifdef DEBUG_KVM | |
33 | #define dprintf(fmt, ...) \ | |
34 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) | |
35 | #else | |
36 | #define dprintf(fmt, ...) \ | |
37 | do { } while (0) | |
38 | #endif | |
39 | ||
94a8d39a JK |
40 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
41 | KVM_CAP_LAST_INFO | |
42 | }; | |
43 | ||
fc87e185 AG |
44 | static int cap_interrupt_unset = false; |
45 | static int cap_interrupt_level = false; | |
46 | ||
c821c2bd AG |
47 | /* XXX We have a race condition where we actually have a level triggered |
48 | * interrupt, but the infrastructure can't expose that yet, so the guest | |
49 | * takes but ignores it, goes to sleep and never gets notified that there's | |
50 | * still an interrupt pending. | |
c6a94ba5 | 51 | * |
c821c2bd AG |
52 | * As a quick workaround, let's just wake up again 20 ms after we injected |
53 | * an interrupt. That way we can assure that we're always reinjecting | |
54 | * interrupts in case the guest swallowed them. | |
c6a94ba5 AG |
55 | */ |
56 | static QEMUTimer *idle_timer; | |
57 | ||
c821c2bd | 58 | static void kvm_kick_env(void *env) |
c6a94ba5 | 59 | { |
c821c2bd | 60 | qemu_cpu_kick(env); |
c6a94ba5 AG |
61 | } |
62 | ||
cad1e282 | 63 | int kvm_arch_init(KVMState *s) |
d76d1650 | 64 | { |
fc87e185 AG |
65 | #ifdef KVM_CAP_PPC_UNSET_IRQ |
66 | cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); | |
67 | #endif | |
68 | #ifdef KVM_CAP_PPC_IRQ_LEVEL | |
69 | cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); | |
70 | #endif | |
71 | ||
72 | if (!cap_interrupt_level) { | |
73 | fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " | |
74 | "VM to stall at times!\n"); | |
75 | } | |
76 | ||
d76d1650 AJ |
77 | return 0; |
78 | } | |
79 | ||
80 | int kvm_arch_init_vcpu(CPUState *cenv) | |
81 | { | |
861bbc80 AG |
82 | int ret = 0; |
83 | struct kvm_sregs sregs; | |
84 | ||
85 | sregs.pvr = cenv->spr[SPR_PVR]; | |
86 | ret = kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); | |
87 | ||
74475455 | 88 | idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv); |
c821c2bd | 89 | |
861bbc80 | 90 | return ret; |
d76d1650 AJ |
91 | } |
92 | ||
caa5af0f JK |
93 | void kvm_arch_reset_vcpu(CPUState *env) |
94 | { | |
95 | } | |
96 | ||
ea375f9a | 97 | int kvm_arch_put_registers(CPUState *env, int level) |
d76d1650 AJ |
98 | { |
99 | struct kvm_regs regs; | |
100 | int ret; | |
101 | int i; | |
102 | ||
103 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
104 | if (ret < 0) | |
105 | return ret; | |
106 | ||
107 | regs.ctr = env->ctr; | |
108 | regs.lr = env->lr; | |
109 | regs.xer = env->xer; | |
110 | regs.msr = env->msr; | |
111 | regs.pc = env->nip; | |
112 | ||
113 | regs.srr0 = env->spr[SPR_SRR0]; | |
114 | regs.srr1 = env->spr[SPR_SRR1]; | |
115 | ||
116 | regs.sprg0 = env->spr[SPR_SPRG0]; | |
117 | regs.sprg1 = env->spr[SPR_SPRG1]; | |
118 | regs.sprg2 = env->spr[SPR_SPRG2]; | |
119 | regs.sprg3 = env->spr[SPR_SPRG3]; | |
120 | regs.sprg4 = env->spr[SPR_SPRG4]; | |
121 | regs.sprg5 = env->spr[SPR_SPRG5]; | |
122 | regs.sprg6 = env->spr[SPR_SPRG6]; | |
123 | regs.sprg7 = env->spr[SPR_SPRG7]; | |
124 | ||
125 | for (i = 0;i < 32; i++) | |
126 | regs.gpr[i] = env->gpr[i]; | |
127 | ||
128 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); | |
129 | if (ret < 0) | |
130 | return ret; | |
131 | ||
132 | return ret; | |
133 | } | |
134 | ||
135 | int kvm_arch_get_registers(CPUState *env) | |
136 | { | |
137 | struct kvm_regs regs; | |
ba5e5090 | 138 | struct kvm_sregs sregs; |
138b38b6 | 139 | int i, ret; |
d76d1650 AJ |
140 | |
141 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
142 | if (ret < 0) | |
143 | return ret; | |
144 | ||
ba5e5090 AG |
145 | ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); |
146 | if (ret < 0) | |
147 | return ret; | |
148 | ||
d76d1650 AJ |
149 | env->ctr = regs.ctr; |
150 | env->lr = regs.lr; | |
151 | env->xer = regs.xer; | |
152 | env->msr = regs.msr; | |
153 | env->nip = regs.pc; | |
154 | ||
155 | env->spr[SPR_SRR0] = regs.srr0; | |
156 | env->spr[SPR_SRR1] = regs.srr1; | |
157 | ||
158 | env->spr[SPR_SPRG0] = regs.sprg0; | |
159 | env->spr[SPR_SPRG1] = regs.sprg1; | |
160 | env->spr[SPR_SPRG2] = regs.sprg2; | |
161 | env->spr[SPR_SPRG3] = regs.sprg3; | |
162 | env->spr[SPR_SPRG4] = regs.sprg4; | |
163 | env->spr[SPR_SPRG5] = regs.sprg5; | |
164 | env->spr[SPR_SPRG6] = regs.sprg6; | |
165 | env->spr[SPR_SPRG7] = regs.sprg7; | |
166 | ||
167 | for (i = 0;i < 32; i++) | |
168 | env->gpr[i] = regs.gpr[i]; | |
169 | ||
ba5e5090 AG |
170 | #ifdef KVM_CAP_PPC_SEGSTATE |
171 | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) { | |
bb593904 | 172 | ppc_store_sdr1(env, sregs.u.s.sdr1); |
ba5e5090 AG |
173 | |
174 | /* Sync SLB */ | |
82c09f2f | 175 | #ifdef TARGET_PPC64 |
ba5e5090 AG |
176 | for (i = 0; i < 64; i++) { |
177 | ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe, | |
178 | sregs.u.s.ppc64.slb[i].slbv); | |
179 | } | |
82c09f2f | 180 | #endif |
ba5e5090 AG |
181 | |
182 | /* Sync SRs */ | |
183 | for (i = 0; i < 16; i++) { | |
184 | env->sr[i] = sregs.u.s.ppc32.sr[i]; | |
185 | } | |
186 | ||
187 | /* Sync BATs */ | |
188 | for (i = 0; i < 8; i++) { | |
189 | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; | |
190 | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; | |
191 | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; | |
192 | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; | |
193 | } | |
194 | } | |
195 | #endif | |
196 | ||
d76d1650 AJ |
197 | return 0; |
198 | } | |
199 | ||
fc87e185 AG |
200 | int kvmppc_set_interrupt(CPUState *env, int irq, int level) |
201 | { | |
202 | unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; | |
203 | ||
204 | if (irq != PPC_INTERRUPT_EXT) { | |
205 | return 0; | |
206 | } | |
207 | ||
208 | if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) { | |
209 | return 0; | |
210 | } | |
211 | ||
212 | kvm_vcpu_ioctl(env, KVM_INTERRUPT, &virq); | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
16415335 AG |
217 | #if defined(TARGET_PPCEMB) |
218 | #define PPC_INPUT_INT PPC40x_INPUT_INT | |
219 | #elif defined(TARGET_PPC64) | |
220 | #define PPC_INPUT_INT PPC970_INPUT_INT | |
221 | #else | |
222 | #define PPC_INPUT_INT PPC6xx_INPUT_INT | |
223 | #endif | |
224 | ||
bdcbd3e2 | 225 | void kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
d76d1650 AJ |
226 | { |
227 | int r; | |
228 | unsigned irq; | |
229 | ||
230 | /* PowerPC Qemu tracks the various core input pins (interrupt, critical | |
231 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */ | |
fc87e185 AG |
232 | if (!cap_interrupt_level && |
233 | run->ready_for_interrupt_injection && | |
d76d1650 | 234 | (env->interrupt_request & CPU_INTERRUPT_HARD) && |
16415335 | 235 | (env->irq_input_state & (1<<PPC_INPUT_INT))) |
d76d1650 AJ |
236 | { |
237 | /* For now KVM disregards the 'irq' argument. However, in the | |
238 | * future KVM could cache it in-kernel to avoid a heavyweight exit | |
239 | * when reading the UIC. | |
240 | */ | |
fc87e185 | 241 | irq = KVM_INTERRUPT_SET; |
d76d1650 AJ |
242 | |
243 | dprintf("injected interrupt %d\n", irq); | |
244 | r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq); | |
245 | if (r < 0) | |
246 | printf("cpu %d fail inject %x\n", env->cpu_index, irq); | |
c821c2bd AG |
247 | |
248 | /* Always wake up soon in case the interrupt was level based */ | |
74475455 | 249 | qemu_mod_timer(idle_timer, qemu_get_clock_ns(vm_clock) + |
c821c2bd | 250 | (get_ticks_per_sec() / 50)); |
d76d1650 AJ |
251 | } |
252 | ||
253 | /* We don't know if there are more interrupts pending after this. However, | |
254 | * the guest will return to userspace in the course of handling this one | |
255 | * anyways, so we will get a chance to deliver the rest. */ | |
d76d1650 AJ |
256 | } |
257 | ||
7a39fe58 | 258 | void kvm_arch_post_run(CPUState *env, struct kvm_run *run) |
d76d1650 | 259 | { |
d76d1650 AJ |
260 | } |
261 | ||
99036865 | 262 | int kvm_arch_process_async_events(CPUState *env) |
0af691d7 | 263 | { |
bdcbd3e2 | 264 | return 0; |
0af691d7 MT |
265 | } |
266 | ||
d76d1650 AJ |
267 | static int kvmppc_handle_halt(CPUState *env) |
268 | { | |
269 | if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { | |
270 | env->halted = 1; | |
271 | env->exception_index = EXCP_HLT; | |
272 | } | |
273 | ||
bb4ea393 | 274 | return 0; |
d76d1650 AJ |
275 | } |
276 | ||
277 | /* map dcr access to existing qemu dcr emulation */ | |
278 | static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data) | |
279 | { | |
280 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) | |
281 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); | |
282 | ||
bb4ea393 | 283 | return 0; |
d76d1650 AJ |
284 | } |
285 | ||
286 | static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data) | |
287 | { | |
288 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) | |
289 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); | |
290 | ||
bb4ea393 | 291 | return 0; |
d76d1650 AJ |
292 | } |
293 | ||
294 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
295 | { | |
bb4ea393 | 296 | int ret; |
d76d1650 AJ |
297 | |
298 | switch (run->exit_reason) { | |
299 | case KVM_EXIT_DCR: | |
300 | if (run->dcr.is_write) { | |
301 | dprintf("handle dcr write\n"); | |
302 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); | |
303 | } else { | |
304 | dprintf("handle dcr read\n"); | |
305 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); | |
306 | } | |
307 | break; | |
308 | case KVM_EXIT_HLT: | |
309 | dprintf("handle halt\n"); | |
310 | ret = kvmppc_handle_halt(env); | |
311 | break; | |
73aaec4a JK |
312 | default: |
313 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
314 | ret = -1; | |
315 | break; | |
d76d1650 AJ |
316 | } |
317 | ||
318 | return ret; | |
319 | } | |
320 | ||
dc333cd6 AG |
321 | static int read_cpuinfo(const char *field, char *value, int len) |
322 | { | |
323 | FILE *f; | |
324 | int ret = -1; | |
325 | int field_len = strlen(field); | |
326 | char line[512]; | |
327 | ||
328 | f = fopen("/proc/cpuinfo", "r"); | |
329 | if (!f) { | |
330 | return -1; | |
331 | } | |
332 | ||
333 | do { | |
334 | if(!fgets(line, sizeof(line), f)) { | |
335 | break; | |
336 | } | |
337 | if (!strncmp(line, field, field_len)) { | |
338 | strncpy(value, line, len); | |
339 | ret = 0; | |
340 | break; | |
341 | } | |
342 | } while(*line); | |
343 | ||
344 | fclose(f); | |
345 | ||
346 | return ret; | |
347 | } | |
348 | ||
349 | uint32_t kvmppc_get_tbfreq(void) | |
350 | { | |
351 | char line[512]; | |
352 | char *ns; | |
353 | uint32_t retval = get_ticks_per_sec(); | |
354 | ||
355 | if (read_cpuinfo("timebase", line, sizeof(line))) { | |
356 | return retval; | |
357 | } | |
358 | ||
359 | if (!(ns = strchr(line, ':'))) { | |
360 | return retval; | |
361 | } | |
362 | ||
363 | ns++; | |
364 | ||
365 | retval = atoi(ns); | |
366 | return retval; | |
367 | } | |
4513d923 | 368 | |
45024f09 AG |
369 | int kvmppc_get_hypercall(CPUState *env, uint8_t *buf, int buf_len) |
370 | { | |
371 | uint32_t *hc = (uint32_t*)buf; | |
372 | ||
373 | #ifdef KVM_CAP_PPC_GET_PVINFO | |
374 | struct kvm_ppc_pvinfo pvinfo; | |
375 | ||
376 | if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_GET_PVINFO) && | |
377 | !kvm_vm_ioctl(env->kvm_state, KVM_PPC_GET_PVINFO, &pvinfo)) { | |
378 | memcpy(buf, pvinfo.hcall, buf_len); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | #endif | |
383 | ||
384 | /* | |
385 | * Fallback to always fail hypercalls: | |
386 | * | |
387 | * li r3, -1 | |
388 | * nop | |
389 | * nop | |
390 | * nop | |
391 | */ | |
392 | ||
393 | hc[0] = 0x3860ffff; | |
394 | hc[1] = 0x60000000; | |
395 | hc[2] = 0x60000000; | |
396 | hc[3] = 0x60000000; | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
4513d923 GN |
401 | bool kvm_arch_stop_on_emulation_error(CPUState *env) |
402 | { | |
403 | return true; | |
404 | } | |
a1b87fe0 JK |
405 | |
406 | int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr) | |
407 | { | |
408 | return 1; | |
409 | } | |
410 | ||
411 | int kvm_arch_on_sigbus(int code, void *addr) | |
412 | { | |
413 | return 1; | |
414 | } |