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Commit | Line | Data |
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d76d1650 AJ |
1 | /* |
2 | * PowerPC implementation of KVM hooks | |
3 | * | |
4 | * Copyright IBM Corp. 2007 | |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
d76d1650 AJ |
6 | * |
7 | * Authors: | |
8 | * Jerone Young <jyoung5@us.ibm.com> | |
9 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
10 | * Hollis Blanchard <hollisb@us.ibm.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
13 | * See the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
eadaada1 | 17 | #include <dirent.h> |
d76d1650 AJ |
18 | #include <sys/types.h> |
19 | #include <sys/ioctl.h> | |
20 | #include <sys/mman.h> | |
4656e1f0 | 21 | #include <sys/vfs.h> |
d76d1650 AJ |
22 | |
23 | #include <linux/kvm.h> | |
24 | ||
25 | #include "qemu-common.h" | |
1de7afc9 | 26 | #include "qemu/timer.h" |
9c17d615 PB |
27 | #include "sysemu/sysemu.h" |
28 | #include "sysemu/kvm.h" | |
d76d1650 AJ |
29 | #include "kvm_ppc.h" |
30 | #include "cpu.h" | |
9c17d615 PB |
31 | #include "sysemu/cpus.h" |
32 | #include "sysemu/device_tree.h" | |
d5aea6f3 | 33 | #include "mmu-hash64.h" |
d76d1650 | 34 | |
f61b4bed | 35 | #include "hw/sysbus.h" |
0d09e41a PB |
36 | #include "hw/ppc/spapr.h" |
37 | #include "hw/ppc/spapr_vio.h" | |
98a8b524 | 38 | #include "hw/ppc/ppc.h" |
31f2cb8f | 39 | #include "sysemu/watchdog.h" |
b36f100e | 40 | #include "trace.h" |
88365d17 | 41 | #include "exec/gdbstub.h" |
4c663752 | 42 | #include "exec/memattrs.h" |
2d103aae | 43 | #include "sysemu/hostmem.h" |
f61b4bed | 44 | |
d76d1650 AJ |
45 | //#define DEBUG_KVM |
46 | ||
47 | #ifdef DEBUG_KVM | |
da56ff91 | 48 | #define DPRINTF(fmt, ...) \ |
d76d1650 AJ |
49 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
50 | #else | |
da56ff91 | 51 | #define DPRINTF(fmt, ...) \ |
d76d1650 AJ |
52 | do { } while (0) |
53 | #endif | |
54 | ||
eadaada1 AG |
55 | #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/" |
56 | ||
94a8d39a JK |
57 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
58 | KVM_CAP_LAST_INFO | |
59 | }; | |
60 | ||
fc87e185 AG |
61 | static int cap_interrupt_unset = false; |
62 | static int cap_interrupt_level = false; | |
90dc8812 | 63 | static int cap_segstate; |
90dc8812 | 64 | static int cap_booke_sregs; |
e97c3636 | 65 | static int cap_ppc_smt; |
354ac20a | 66 | static int cap_ppc_rma; |
0f5cb298 | 67 | static int cap_spapr_tce; |
da95324e | 68 | static int cap_spapr_multitce; |
9bb62a07 | 69 | static int cap_spapr_vfio; |
f1af19d7 | 70 | static int cap_hior; |
d67d40ea | 71 | static int cap_one_reg; |
3b961124 | 72 | static int cap_epr; |
31f2cb8f | 73 | static int cap_ppc_watchdog; |
9b00ea49 | 74 | static int cap_papr; |
e68cb8b4 | 75 | static int cap_htab_fd; |
87a91de6 | 76 | static int cap_fixup_hcalls; |
fc87e185 | 77 | |
3c902d44 BB |
78 | static uint32_t debug_inst_opcode; |
79 | ||
c821c2bd AG |
80 | /* XXX We have a race condition where we actually have a level triggered |
81 | * interrupt, but the infrastructure can't expose that yet, so the guest | |
82 | * takes but ignores it, goes to sleep and never gets notified that there's | |
83 | * still an interrupt pending. | |
c6a94ba5 | 84 | * |
c821c2bd AG |
85 | * As a quick workaround, let's just wake up again 20 ms after we injected |
86 | * an interrupt. That way we can assure that we're always reinjecting | |
87 | * interrupts in case the guest swallowed them. | |
c6a94ba5 AG |
88 | */ |
89 | static QEMUTimer *idle_timer; | |
90 | ||
d5a68146 | 91 | static void kvm_kick_cpu(void *opaque) |
c6a94ba5 | 92 | { |
d5a68146 | 93 | PowerPCCPU *cpu = opaque; |
d5a68146 | 94 | |
c08d7424 | 95 | qemu_cpu_kick(CPU(cpu)); |
c6a94ba5 AG |
96 | } |
97 | ||
5ba4576b AF |
98 | static int kvm_ppc_register_host_cpu_type(void); |
99 | ||
b16565b3 | 100 | int kvm_arch_init(MachineState *ms, KVMState *s) |
d76d1650 | 101 | { |
fc87e185 | 102 | cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ); |
fc87e185 | 103 | cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL); |
90dc8812 | 104 | cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE); |
90dc8812 | 105 | cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS); |
e97c3636 | 106 | cap_ppc_smt = kvm_check_extension(s, KVM_CAP_PPC_SMT); |
354ac20a | 107 | cap_ppc_rma = kvm_check_extension(s, KVM_CAP_PPC_RMA); |
0f5cb298 | 108 | cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE); |
da95324e | 109 | cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE); |
9bb62a07 | 110 | cap_spapr_vfio = false; |
d67d40ea | 111 | cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG); |
f1af19d7 | 112 | cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR); |
3b961124 | 113 | cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR); |
31f2cb8f | 114 | cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG); |
9b00ea49 DG |
115 | /* Note: we don't set cap_papr here, because this capability is |
116 | * only activated after this by kvmppc_set_papr() */ | |
e68cb8b4 | 117 | cap_htab_fd = kvm_check_extension(s, KVM_CAP_PPC_HTAB_FD); |
87a91de6 | 118 | cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL); |
fc87e185 AG |
119 | |
120 | if (!cap_interrupt_level) { | |
121 | fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the " | |
122 | "VM to stall at times!\n"); | |
123 | } | |
124 | ||
5ba4576b AF |
125 | kvm_ppc_register_host_cpu_type(); |
126 | ||
d76d1650 AJ |
127 | return 0; |
128 | } | |
129 | ||
1bc22652 | 130 | static int kvm_arch_sync_sregs(PowerPCCPU *cpu) |
d76d1650 | 131 | { |
1bc22652 AF |
132 | CPUPPCState *cenv = &cpu->env; |
133 | CPUState *cs = CPU(cpu); | |
861bbc80 | 134 | struct kvm_sregs sregs; |
5666ca4a SW |
135 | int ret; |
136 | ||
137 | if (cenv->excp_model == POWERPC_EXCP_BOOKE) { | |
64e07be5 AG |
138 | /* What we're really trying to say is "if we're on BookE, we use |
139 | the native PVR for now". This is the only sane way to check | |
140 | it though, so we potentially confuse users that they can run | |
141 | BookE guests on BookS. Let's hope nobody dares enough :) */ | |
5666ca4a SW |
142 | return 0; |
143 | } else { | |
90dc8812 | 144 | if (!cap_segstate) { |
64e07be5 AG |
145 | fprintf(stderr, "kvm error: missing PVR setting capability\n"); |
146 | return -ENOSYS; | |
5666ca4a | 147 | } |
5666ca4a SW |
148 | } |
149 | ||
1bc22652 | 150 | ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
5666ca4a SW |
151 | if (ret) { |
152 | return ret; | |
153 | } | |
861bbc80 AG |
154 | |
155 | sregs.pvr = cenv->spr[SPR_PVR]; | |
1bc22652 | 156 | return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); |
5666ca4a SW |
157 | } |
158 | ||
93dd5e85 | 159 | /* Set up a shared TLB array with KVM */ |
1bc22652 | 160 | static int kvm_booke206_tlb_init(PowerPCCPU *cpu) |
93dd5e85 | 161 | { |
1bc22652 AF |
162 | CPUPPCState *env = &cpu->env; |
163 | CPUState *cs = CPU(cpu); | |
93dd5e85 SW |
164 | struct kvm_book3e_206_tlb_params params = {}; |
165 | struct kvm_config_tlb cfg = {}; | |
93dd5e85 SW |
166 | unsigned int entries = 0; |
167 | int ret, i; | |
168 | ||
169 | if (!kvm_enabled() || | |
a60f24b5 | 170 | !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) { |
93dd5e85 SW |
171 | return 0; |
172 | } | |
173 | ||
174 | assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN); | |
175 | ||
176 | for (i = 0; i < BOOKE206_MAX_TLBN; i++) { | |
177 | params.tlb_sizes[i] = booke206_tlb_size(env, i); | |
178 | params.tlb_ways[i] = booke206_tlb_ways(env, i); | |
179 | entries += params.tlb_sizes[i]; | |
180 | } | |
181 | ||
182 | assert(entries == env->nb_tlb); | |
183 | assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t)); | |
184 | ||
185 | env->tlb_dirty = true; | |
186 | ||
187 | cfg.array = (uintptr_t)env->tlb.tlbm; | |
188 | cfg.array_len = sizeof(ppcmas_tlb_t) * entries; | |
189 | cfg.params = (uintptr_t)¶ms; | |
190 | cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV; | |
191 | ||
48add816 | 192 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg); |
93dd5e85 SW |
193 | if (ret < 0) { |
194 | fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n", | |
195 | __func__, strerror(-ret)); | |
196 | return ret; | |
197 | } | |
198 | ||
199 | env->kvm_sw_tlb = true; | |
200 | return 0; | |
201 | } | |
202 | ||
4656e1f0 BH |
203 | |
204 | #if defined(TARGET_PPC64) | |
a60f24b5 | 205 | static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, |
4656e1f0 BH |
206 | struct kvm_ppc_smmu_info *info) |
207 | { | |
a60f24b5 AF |
208 | CPUPPCState *env = &cpu->env; |
209 | CPUState *cs = CPU(cpu); | |
210 | ||
4656e1f0 BH |
211 | memset(info, 0, sizeof(*info)); |
212 | ||
213 | /* We don't have the new KVM_PPC_GET_SMMU_INFO ioctl, so | |
214 | * need to "guess" what the supported page sizes are. | |
215 | * | |
216 | * For that to work we make a few assumptions: | |
217 | * | |
218 | * - If KVM_CAP_PPC_GET_PVINFO is supported we are running "PR" | |
219 | * KVM which only supports 4K and 16M pages, but supports them | |
220 | * regardless of the backing store characteritics. We also don't | |
221 | * support 1T segments. | |
222 | * | |
223 | * This is safe as if HV KVM ever supports that capability or PR | |
224 | * KVM grows supports for more page/segment sizes, those versions | |
225 | * will have implemented KVM_CAP_PPC_GET_SMMU_INFO and thus we | |
226 | * will not hit this fallback | |
227 | * | |
228 | * - Else we are running HV KVM. This means we only support page | |
229 | * sizes that fit in the backing store. Additionally we only | |
230 | * advertize 64K pages if the processor is ARCH 2.06 and we assume | |
231 | * P7 encodings for the SLB and hash table. Here too, we assume | |
232 | * support for any newer processor will mean a kernel that | |
233 | * implements KVM_CAP_PPC_GET_SMMU_INFO and thus doesn't hit | |
234 | * this fallback. | |
235 | */ | |
a60f24b5 | 236 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO)) { |
4656e1f0 BH |
237 | /* No flags */ |
238 | info->flags = 0; | |
239 | info->slb_size = 64; | |
240 | ||
241 | /* Standard 4k base page size segment */ | |
242 | info->sps[0].page_shift = 12; | |
243 | info->sps[0].slb_enc = 0; | |
244 | info->sps[0].enc[0].page_shift = 12; | |
245 | info->sps[0].enc[0].pte_enc = 0; | |
246 | ||
247 | /* Standard 16M large page size segment */ | |
248 | info->sps[1].page_shift = 24; | |
249 | info->sps[1].slb_enc = SLB_VSID_L; | |
250 | info->sps[1].enc[0].page_shift = 24; | |
251 | info->sps[1].enc[0].pte_enc = 0; | |
252 | } else { | |
253 | int i = 0; | |
254 | ||
255 | /* HV KVM has backing store size restrictions */ | |
256 | info->flags = KVM_PPC_PAGE_SIZES_REAL; | |
257 | ||
258 | if (env->mmu_model & POWERPC_MMU_1TSEG) { | |
259 | info->flags |= KVM_PPC_1T_SEGMENTS; | |
260 | } | |
261 | ||
aa4bb587 BH |
262 | if (env->mmu_model == POWERPC_MMU_2_06 || |
263 | env->mmu_model == POWERPC_MMU_2_07) { | |
4656e1f0 BH |
264 | info->slb_size = 32; |
265 | } else { | |
266 | info->slb_size = 64; | |
267 | } | |
268 | ||
269 | /* Standard 4k base page size segment */ | |
270 | info->sps[i].page_shift = 12; | |
271 | info->sps[i].slb_enc = 0; | |
272 | info->sps[i].enc[0].page_shift = 12; | |
273 | info->sps[i].enc[0].pte_enc = 0; | |
274 | i++; | |
275 | ||
aa4bb587 BH |
276 | /* 64K on MMU 2.06 and later */ |
277 | if (env->mmu_model == POWERPC_MMU_2_06 || | |
278 | env->mmu_model == POWERPC_MMU_2_07) { | |
4656e1f0 BH |
279 | info->sps[i].page_shift = 16; |
280 | info->sps[i].slb_enc = 0x110; | |
281 | info->sps[i].enc[0].page_shift = 16; | |
282 | info->sps[i].enc[0].pte_enc = 1; | |
283 | i++; | |
284 | } | |
285 | ||
286 | /* Standard 16M large page size segment */ | |
287 | info->sps[i].page_shift = 24; | |
288 | info->sps[i].slb_enc = SLB_VSID_L; | |
289 | info->sps[i].enc[0].page_shift = 24; | |
290 | info->sps[i].enc[0].pte_enc = 0; | |
291 | } | |
292 | } | |
293 | ||
a60f24b5 | 294 | static void kvm_get_smmu_info(PowerPCCPU *cpu, struct kvm_ppc_smmu_info *info) |
4656e1f0 | 295 | { |
a60f24b5 | 296 | CPUState *cs = CPU(cpu); |
4656e1f0 BH |
297 | int ret; |
298 | ||
a60f24b5 AF |
299 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) { |
300 | ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_SMMU_INFO, info); | |
4656e1f0 BH |
301 | if (ret == 0) { |
302 | return; | |
303 | } | |
304 | } | |
305 | ||
a60f24b5 | 306 | kvm_get_fallback_smmu_info(cpu, info); |
4656e1f0 BH |
307 | } |
308 | ||
2d103aae | 309 | static long gethugepagesize(const char *mem_path) |
4656e1f0 BH |
310 | { |
311 | struct statfs fs; | |
312 | int ret; | |
313 | ||
4656e1f0 BH |
314 | do { |
315 | ret = statfs(mem_path, &fs); | |
316 | } while (ret != 0 && errno == EINTR); | |
317 | ||
318 | if (ret != 0) { | |
319 | fprintf(stderr, "Couldn't statfs() memory path: %s\n", | |
320 | strerror(errno)); | |
321 | exit(1); | |
322 | } | |
323 | ||
324 | #define HUGETLBFS_MAGIC 0x958458f6 | |
325 | ||
326 | if (fs.f_type != HUGETLBFS_MAGIC) { | |
327 | /* Explicit mempath, but it's ordinary pages */ | |
328 | return getpagesize(); | |
329 | } | |
330 | ||
331 | /* It's hugepage, return the huge page size */ | |
332 | return fs.f_bsize; | |
333 | } | |
334 | ||
2d103aae MR |
335 | static int find_max_supported_pagesize(Object *obj, void *opaque) |
336 | { | |
337 | char *mem_path; | |
338 | long *hpsize_min = opaque; | |
339 | ||
340 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
341 | mem_path = object_property_get_str(obj, "mem-path", NULL); | |
342 | if (mem_path) { | |
343 | long hpsize = gethugepagesize(mem_path); | |
344 | if (hpsize < *hpsize_min) { | |
345 | *hpsize_min = hpsize; | |
346 | } | |
347 | } else { | |
348 | *hpsize_min = getpagesize(); | |
349 | } | |
350 | } | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | static long getrampagesize(void) | |
356 | { | |
357 | long hpsize = LONG_MAX; | |
358 | Object *memdev_root; | |
359 | ||
360 | if (mem_path) { | |
361 | return gethugepagesize(mem_path); | |
362 | } | |
363 | ||
364 | /* it's possible we have memory-backend objects with | |
365 | * hugepage-backed RAM. these may get mapped into system | |
366 | * address space via -numa parameters or memory hotplug | |
367 | * hooks. we want to take these into account, but we | |
368 | * also want to make sure these supported hugepage | |
369 | * sizes are applicable across the entire range of memory | |
370 | * we may boot from, so we take the min across all | |
371 | * backends, and assume normal pages in cases where a | |
372 | * backend isn't backed by hugepages. | |
373 | */ | |
374 | memdev_root = object_resolve_path("/objects", NULL); | |
375 | if (!memdev_root) { | |
376 | return getpagesize(); | |
377 | } | |
378 | ||
379 | object_child_foreach(memdev_root, find_max_supported_pagesize, &hpsize); | |
380 | ||
381 | return (hpsize == LONG_MAX) ? getpagesize() : hpsize; | |
382 | } | |
383 | ||
4656e1f0 BH |
384 | static bool kvm_valid_page_size(uint32_t flags, long rampgsize, uint32_t shift) |
385 | { | |
386 | if (!(flags & KVM_PPC_PAGE_SIZES_REAL)) { | |
387 | return true; | |
388 | } | |
389 | ||
390 | return (1ul << shift) <= rampgsize; | |
391 | } | |
392 | ||
a60f24b5 | 393 | static void kvm_fixup_page_sizes(PowerPCCPU *cpu) |
4656e1f0 BH |
394 | { |
395 | static struct kvm_ppc_smmu_info smmu_info; | |
396 | static bool has_smmu_info; | |
a60f24b5 | 397 | CPUPPCState *env = &cpu->env; |
4656e1f0 BH |
398 | long rampagesize; |
399 | int iq, ik, jq, jk; | |
400 | ||
401 | /* We only handle page sizes for 64-bit server guests for now */ | |
402 | if (!(env->mmu_model & POWERPC_MMU_64)) { | |
403 | return; | |
404 | } | |
405 | ||
406 | /* Collect MMU info from kernel if not already */ | |
407 | if (!has_smmu_info) { | |
a60f24b5 | 408 | kvm_get_smmu_info(cpu, &smmu_info); |
4656e1f0 BH |
409 | has_smmu_info = true; |
410 | } | |
411 | ||
412 | rampagesize = getrampagesize(); | |
413 | ||
414 | /* Convert to QEMU form */ | |
415 | memset(&env->sps, 0, sizeof(env->sps)); | |
416 | ||
08215d8f AG |
417 | /* |
418 | * XXX This loop should be an entry wide AND of the capabilities that | |
419 | * the selected CPU has with the capabilities that KVM supports. | |
420 | */ | |
4656e1f0 BH |
421 | for (ik = iq = 0; ik < KVM_PPC_PAGE_SIZES_MAX_SZ; ik++) { |
422 | struct ppc_one_seg_page_size *qsps = &env->sps.sps[iq]; | |
423 | struct kvm_ppc_one_seg_page_size *ksps = &smmu_info.sps[ik]; | |
424 | ||
425 | if (!kvm_valid_page_size(smmu_info.flags, rampagesize, | |
426 | ksps->page_shift)) { | |
427 | continue; | |
428 | } | |
429 | qsps->page_shift = ksps->page_shift; | |
430 | qsps->slb_enc = ksps->slb_enc; | |
431 | for (jk = jq = 0; jk < KVM_PPC_PAGE_SIZES_MAX_SZ; jk++) { | |
432 | if (!kvm_valid_page_size(smmu_info.flags, rampagesize, | |
433 | ksps->enc[jk].page_shift)) { | |
434 | continue; | |
435 | } | |
436 | qsps->enc[jq].page_shift = ksps->enc[jk].page_shift; | |
437 | qsps->enc[jq].pte_enc = ksps->enc[jk].pte_enc; | |
438 | if (++jq >= PPC_PAGE_SIZES_MAX_SZ) { | |
439 | break; | |
440 | } | |
441 | } | |
442 | if (++iq >= PPC_PAGE_SIZES_MAX_SZ) { | |
443 | break; | |
444 | } | |
445 | } | |
446 | env->slb_nr = smmu_info.slb_size; | |
08215d8f | 447 | if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { |
4656e1f0 BH |
448 | env->mmu_model &= ~POWERPC_MMU_1TSEG; |
449 | } | |
450 | } | |
451 | #else /* defined (TARGET_PPC64) */ | |
452 | ||
a60f24b5 | 453 | static inline void kvm_fixup_page_sizes(PowerPCCPU *cpu) |
4656e1f0 BH |
454 | { |
455 | } | |
456 | ||
457 | #endif /* !defined (TARGET_PPC64) */ | |
458 | ||
b164e48e EH |
459 | unsigned long kvm_arch_vcpu_id(CPUState *cpu) |
460 | { | |
0f20ba62 | 461 | return ppc_get_vcpu_dt_id(POWERPC_CPU(cpu)); |
b164e48e EH |
462 | } |
463 | ||
88365d17 BB |
464 | /* e500 supports 2 h/w breakpoint and 2 watchpoint. |
465 | * book3s supports only 1 watchpoint, so array size | |
466 | * of 4 is sufficient for now. | |
467 | */ | |
468 | #define MAX_HW_BKPTS 4 | |
469 | ||
470 | static struct HWBreakpoint { | |
471 | target_ulong addr; | |
472 | int type; | |
473 | } hw_debug_points[MAX_HW_BKPTS]; | |
474 | ||
475 | static CPUWatchpoint hw_watchpoint; | |
476 | ||
477 | /* Default there is no breakpoint and watchpoint supported */ | |
478 | static int max_hw_breakpoint; | |
479 | static int max_hw_watchpoint; | |
480 | static int nb_hw_breakpoint; | |
481 | static int nb_hw_watchpoint; | |
482 | ||
483 | static void kvmppc_hw_debug_points_init(CPUPPCState *cenv) | |
484 | { | |
485 | if (cenv->excp_model == POWERPC_EXCP_BOOKE) { | |
486 | max_hw_breakpoint = 2; | |
487 | max_hw_watchpoint = 2; | |
488 | } | |
489 | ||
490 | if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) { | |
491 | fprintf(stderr, "Error initializing h/w breakpoints\n"); | |
492 | return; | |
493 | } | |
494 | } | |
495 | ||
20d695a9 | 496 | int kvm_arch_init_vcpu(CPUState *cs) |
5666ca4a | 497 | { |
20d695a9 AF |
498 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
499 | CPUPPCState *cenv = &cpu->env; | |
5666ca4a SW |
500 | int ret; |
501 | ||
4656e1f0 | 502 | /* Gather server mmu info from KVM and update the CPU state */ |
a60f24b5 | 503 | kvm_fixup_page_sizes(cpu); |
4656e1f0 BH |
504 | |
505 | /* Synchronize sregs with kvm */ | |
1bc22652 | 506 | ret = kvm_arch_sync_sregs(cpu); |
5666ca4a SW |
507 | if (ret) { |
508 | return ret; | |
509 | } | |
861bbc80 | 510 | |
bc72ad67 | 511 | idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu); |
c821c2bd | 512 | |
93dd5e85 SW |
513 | /* Some targets support access to KVM's guest TLB. */ |
514 | switch (cenv->mmu_model) { | |
515 | case POWERPC_MMU_BOOKE206: | |
1bc22652 | 516 | ret = kvm_booke206_tlb_init(cpu); |
93dd5e85 SW |
517 | break; |
518 | default: | |
519 | break; | |
520 | } | |
521 | ||
3c902d44 | 522 | kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); |
88365d17 | 523 | kvmppc_hw_debug_points_init(cenv); |
3c902d44 | 524 | |
861bbc80 | 525 | return ret; |
d76d1650 AJ |
526 | } |
527 | ||
1bc22652 | 528 | static void kvm_sw_tlb_put(PowerPCCPU *cpu) |
93dd5e85 | 529 | { |
1bc22652 AF |
530 | CPUPPCState *env = &cpu->env; |
531 | CPUState *cs = CPU(cpu); | |
93dd5e85 SW |
532 | struct kvm_dirty_tlb dirty_tlb; |
533 | unsigned char *bitmap; | |
534 | int ret; | |
535 | ||
536 | if (!env->kvm_sw_tlb) { | |
537 | return; | |
538 | } | |
539 | ||
540 | bitmap = g_malloc((env->nb_tlb + 7) / 8); | |
541 | memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8); | |
542 | ||
543 | dirty_tlb.bitmap = (uintptr_t)bitmap; | |
544 | dirty_tlb.num_dirty = env->nb_tlb; | |
545 | ||
1bc22652 | 546 | ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb); |
93dd5e85 SW |
547 | if (ret) { |
548 | fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n", | |
549 | __func__, strerror(-ret)); | |
550 | } | |
551 | ||
552 | g_free(bitmap); | |
553 | } | |
554 | ||
d67d40ea DG |
555 | static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr) |
556 | { | |
557 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
558 | CPUPPCState *env = &cpu->env; | |
559 | union { | |
560 | uint32_t u32; | |
561 | uint64_t u64; | |
562 | } val; | |
563 | struct kvm_one_reg reg = { | |
564 | .id = id, | |
565 | .addr = (uintptr_t) &val, | |
566 | }; | |
567 | int ret; | |
568 | ||
569 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
570 | if (ret != 0) { | |
b36f100e | 571 | trace_kvm_failed_spr_get(spr, strerror(errno)); |
d67d40ea DG |
572 | } else { |
573 | switch (id & KVM_REG_SIZE_MASK) { | |
574 | case KVM_REG_SIZE_U32: | |
575 | env->spr[spr] = val.u32; | |
576 | break; | |
577 | ||
578 | case KVM_REG_SIZE_U64: | |
579 | env->spr[spr] = val.u64; | |
580 | break; | |
581 | ||
582 | default: | |
583 | /* Don't handle this size yet */ | |
584 | abort(); | |
585 | } | |
586 | } | |
587 | } | |
588 | ||
589 | static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr) | |
590 | { | |
591 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
592 | CPUPPCState *env = &cpu->env; | |
593 | union { | |
594 | uint32_t u32; | |
595 | uint64_t u64; | |
596 | } val; | |
597 | struct kvm_one_reg reg = { | |
598 | .id = id, | |
599 | .addr = (uintptr_t) &val, | |
600 | }; | |
601 | int ret; | |
602 | ||
603 | switch (id & KVM_REG_SIZE_MASK) { | |
604 | case KVM_REG_SIZE_U32: | |
605 | val.u32 = env->spr[spr]; | |
606 | break; | |
607 | ||
608 | case KVM_REG_SIZE_U64: | |
609 | val.u64 = env->spr[spr]; | |
610 | break; | |
611 | ||
612 | default: | |
613 | /* Don't handle this size yet */ | |
614 | abort(); | |
615 | } | |
616 | ||
617 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
618 | if (ret != 0) { | |
b36f100e | 619 | trace_kvm_failed_spr_set(spr, strerror(errno)); |
d67d40ea DG |
620 | } |
621 | } | |
622 | ||
70b79849 DG |
623 | static int kvm_put_fp(CPUState *cs) |
624 | { | |
625 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
626 | CPUPPCState *env = &cpu->env; | |
627 | struct kvm_one_reg reg; | |
628 | int i; | |
629 | int ret; | |
630 | ||
631 | if (env->insns_flags & PPC_FLOAT) { | |
632 | uint64_t fpscr = env->fpscr; | |
633 | bool vsx = !!(env->insns_flags2 & PPC2_VSX); | |
634 | ||
635 | reg.id = KVM_REG_PPC_FPSCR; | |
636 | reg.addr = (uintptr_t)&fpscr; | |
637 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
638 | if (ret < 0) { | |
da56ff91 | 639 | DPRINTF("Unable to set FPSCR to KVM: %s\n", strerror(errno)); |
70b79849 DG |
640 | return ret; |
641 | } | |
642 | ||
643 | for (i = 0; i < 32; i++) { | |
644 | uint64_t vsr[2]; | |
645 | ||
646 | vsr[0] = float64_val(env->fpr[i]); | |
647 | vsr[1] = env->vsr[i]; | |
648 | reg.addr = (uintptr_t) &vsr; | |
649 | reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); | |
650 | ||
651 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
652 | if (ret < 0) { | |
da56ff91 | 653 | DPRINTF("Unable to set %s%d to KVM: %s\n", vsx ? "VSR" : "FPR", |
70b79849 DG |
654 | i, strerror(errno)); |
655 | return ret; | |
656 | } | |
657 | } | |
658 | } | |
659 | ||
660 | if (env->insns_flags & PPC_ALTIVEC) { | |
661 | reg.id = KVM_REG_PPC_VSCR; | |
662 | reg.addr = (uintptr_t)&env->vscr; | |
663 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
664 | if (ret < 0) { | |
da56ff91 | 665 | DPRINTF("Unable to set VSCR to KVM: %s\n", strerror(errno)); |
70b79849 DG |
666 | return ret; |
667 | } | |
668 | ||
669 | for (i = 0; i < 32; i++) { | |
670 | reg.id = KVM_REG_PPC_VR(i); | |
671 | reg.addr = (uintptr_t)&env->avr[i]; | |
672 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
673 | if (ret < 0) { | |
da56ff91 | 674 | DPRINTF("Unable to set VR%d to KVM: %s\n", i, strerror(errno)); |
70b79849 DG |
675 | return ret; |
676 | } | |
677 | } | |
678 | } | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | static int kvm_get_fp(CPUState *cs) | |
684 | { | |
685 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
686 | CPUPPCState *env = &cpu->env; | |
687 | struct kvm_one_reg reg; | |
688 | int i; | |
689 | int ret; | |
690 | ||
691 | if (env->insns_flags & PPC_FLOAT) { | |
692 | uint64_t fpscr; | |
693 | bool vsx = !!(env->insns_flags2 & PPC2_VSX); | |
694 | ||
695 | reg.id = KVM_REG_PPC_FPSCR; | |
696 | reg.addr = (uintptr_t)&fpscr; | |
697 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
698 | if (ret < 0) { | |
da56ff91 | 699 | DPRINTF("Unable to get FPSCR from KVM: %s\n", strerror(errno)); |
70b79849 DG |
700 | return ret; |
701 | } else { | |
702 | env->fpscr = fpscr; | |
703 | } | |
704 | ||
705 | for (i = 0; i < 32; i++) { | |
706 | uint64_t vsr[2]; | |
707 | ||
708 | reg.addr = (uintptr_t) &vsr; | |
709 | reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i); | |
710 | ||
711 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
712 | if (ret < 0) { | |
da56ff91 | 713 | DPRINTF("Unable to get %s%d from KVM: %s\n", |
70b79849 DG |
714 | vsx ? "VSR" : "FPR", i, strerror(errno)); |
715 | return ret; | |
716 | } else { | |
717 | env->fpr[i] = vsr[0]; | |
718 | if (vsx) { | |
719 | env->vsr[i] = vsr[1]; | |
720 | } | |
721 | } | |
722 | } | |
723 | } | |
724 | ||
725 | if (env->insns_flags & PPC_ALTIVEC) { | |
726 | reg.id = KVM_REG_PPC_VSCR; | |
727 | reg.addr = (uintptr_t)&env->vscr; | |
728 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
729 | if (ret < 0) { | |
da56ff91 | 730 | DPRINTF("Unable to get VSCR from KVM: %s\n", strerror(errno)); |
70b79849 DG |
731 | return ret; |
732 | } | |
733 | ||
734 | for (i = 0; i < 32; i++) { | |
735 | reg.id = KVM_REG_PPC_VR(i); | |
736 | reg.addr = (uintptr_t)&env->avr[i]; | |
737 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
738 | if (ret < 0) { | |
da56ff91 | 739 | DPRINTF("Unable to get VR%d from KVM: %s\n", |
70b79849 DG |
740 | i, strerror(errno)); |
741 | return ret; | |
742 | } | |
743 | } | |
744 | } | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
9b00ea49 DG |
749 | #if defined(TARGET_PPC64) |
750 | static int kvm_get_vpa(CPUState *cs) | |
751 | { | |
752 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
753 | CPUPPCState *env = &cpu->env; | |
754 | struct kvm_one_reg reg; | |
755 | int ret; | |
756 | ||
757 | reg.id = KVM_REG_PPC_VPA_ADDR; | |
758 | reg.addr = (uintptr_t)&env->vpa_addr; | |
759 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
760 | if (ret < 0) { | |
da56ff91 | 761 | DPRINTF("Unable to get VPA address from KVM: %s\n", strerror(errno)); |
9b00ea49 DG |
762 | return ret; |
763 | } | |
764 | ||
765 | assert((uintptr_t)&env->slb_shadow_size | |
766 | == ((uintptr_t)&env->slb_shadow_addr + 8)); | |
767 | reg.id = KVM_REG_PPC_VPA_SLB; | |
768 | reg.addr = (uintptr_t)&env->slb_shadow_addr; | |
769 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
770 | if (ret < 0) { | |
da56ff91 | 771 | DPRINTF("Unable to get SLB shadow state from KVM: %s\n", |
9b00ea49 DG |
772 | strerror(errno)); |
773 | return ret; | |
774 | } | |
775 | ||
776 | assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8)); | |
777 | reg.id = KVM_REG_PPC_VPA_DTL; | |
778 | reg.addr = (uintptr_t)&env->dtl_addr; | |
779 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); | |
780 | if (ret < 0) { | |
da56ff91 | 781 | DPRINTF("Unable to get dispatch trace log state from KVM: %s\n", |
9b00ea49 DG |
782 | strerror(errno)); |
783 | return ret; | |
784 | } | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
789 | static int kvm_put_vpa(CPUState *cs) | |
790 | { | |
791 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
792 | CPUPPCState *env = &cpu->env; | |
793 | struct kvm_one_reg reg; | |
794 | int ret; | |
795 | ||
796 | /* SLB shadow or DTL can't be registered unless a master VPA is | |
797 | * registered. That means when restoring state, if a VPA *is* | |
798 | * registered, we need to set that up first. If not, we need to | |
799 | * deregister the others before deregistering the master VPA */ | |
800 | assert(env->vpa_addr || !(env->slb_shadow_addr || env->dtl_addr)); | |
801 | ||
802 | if (env->vpa_addr) { | |
803 | reg.id = KVM_REG_PPC_VPA_ADDR; | |
804 | reg.addr = (uintptr_t)&env->vpa_addr; | |
805 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
806 | if (ret < 0) { | |
da56ff91 | 807 | DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno)); |
9b00ea49 DG |
808 | return ret; |
809 | } | |
810 | } | |
811 | ||
812 | assert((uintptr_t)&env->slb_shadow_size | |
813 | == ((uintptr_t)&env->slb_shadow_addr + 8)); | |
814 | reg.id = KVM_REG_PPC_VPA_SLB; | |
815 | reg.addr = (uintptr_t)&env->slb_shadow_addr; | |
816 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
817 | if (ret < 0) { | |
da56ff91 | 818 | DPRINTF("Unable to set SLB shadow state to KVM: %s\n", strerror(errno)); |
9b00ea49 DG |
819 | return ret; |
820 | } | |
821 | ||
822 | assert((uintptr_t)&env->dtl_size == ((uintptr_t)&env->dtl_addr + 8)); | |
823 | reg.id = KVM_REG_PPC_VPA_DTL; | |
824 | reg.addr = (uintptr_t)&env->dtl_addr; | |
825 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
826 | if (ret < 0) { | |
da56ff91 | 827 | DPRINTF("Unable to set dispatch trace log state to KVM: %s\n", |
9b00ea49 DG |
828 | strerror(errno)); |
829 | return ret; | |
830 | } | |
831 | ||
832 | if (!env->vpa_addr) { | |
833 | reg.id = KVM_REG_PPC_VPA_ADDR; | |
834 | reg.addr = (uintptr_t)&env->vpa_addr; | |
835 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
836 | if (ret < 0) { | |
da56ff91 | 837 | DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno)); |
9b00ea49 DG |
838 | return ret; |
839 | } | |
840 | } | |
841 | ||
842 | return 0; | |
843 | } | |
844 | #endif /* TARGET_PPC64 */ | |
845 | ||
20d695a9 | 846 | int kvm_arch_put_registers(CPUState *cs, int level) |
d76d1650 | 847 | { |
20d695a9 AF |
848 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
849 | CPUPPCState *env = &cpu->env; | |
d76d1650 AJ |
850 | struct kvm_regs regs; |
851 | int ret; | |
852 | int i; | |
853 | ||
1bc22652 AF |
854 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); |
855 | if (ret < 0) { | |
d76d1650 | 856 | return ret; |
1bc22652 | 857 | } |
d76d1650 AJ |
858 | |
859 | regs.ctr = env->ctr; | |
860 | regs.lr = env->lr; | |
da91a00f | 861 | regs.xer = cpu_read_xer(env); |
d76d1650 AJ |
862 | regs.msr = env->msr; |
863 | regs.pc = env->nip; | |
864 | ||
865 | regs.srr0 = env->spr[SPR_SRR0]; | |
866 | regs.srr1 = env->spr[SPR_SRR1]; | |
867 | ||
868 | regs.sprg0 = env->spr[SPR_SPRG0]; | |
869 | regs.sprg1 = env->spr[SPR_SPRG1]; | |
870 | regs.sprg2 = env->spr[SPR_SPRG2]; | |
871 | regs.sprg3 = env->spr[SPR_SPRG3]; | |
872 | regs.sprg4 = env->spr[SPR_SPRG4]; | |
873 | regs.sprg5 = env->spr[SPR_SPRG5]; | |
874 | regs.sprg6 = env->spr[SPR_SPRG6]; | |
875 | regs.sprg7 = env->spr[SPR_SPRG7]; | |
876 | ||
90dc8812 SW |
877 | regs.pid = env->spr[SPR_BOOKE_PID]; |
878 | ||
d76d1650 AJ |
879 | for (i = 0;i < 32; i++) |
880 | regs.gpr[i] = env->gpr[i]; | |
881 | ||
4bddaf55 AK |
882 | regs.cr = 0; |
883 | for (i = 0; i < 8; i++) { | |
884 | regs.cr |= (env->crf[i] & 15) << (4 * (7 - i)); | |
885 | } | |
886 | ||
1bc22652 | 887 | ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, ®s); |
d76d1650 AJ |
888 | if (ret < 0) |
889 | return ret; | |
890 | ||
70b79849 DG |
891 | kvm_put_fp(cs); |
892 | ||
93dd5e85 | 893 | if (env->tlb_dirty) { |
1bc22652 | 894 | kvm_sw_tlb_put(cpu); |
93dd5e85 SW |
895 | env->tlb_dirty = false; |
896 | } | |
897 | ||
f1af19d7 DG |
898 | if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) { |
899 | struct kvm_sregs sregs; | |
900 | ||
901 | sregs.pvr = env->spr[SPR_PVR]; | |
902 | ||
903 | sregs.u.s.sdr1 = env->spr[SPR_SDR1]; | |
904 | ||
905 | /* Sync SLB */ | |
906 | #ifdef TARGET_PPC64 | |
d83af167 | 907 | for (i = 0; i < ARRAY_SIZE(env->slb); i++) { |
f1af19d7 | 908 | sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid; |
69b31b90 AK |
909 | if (env->slb[i].esid & SLB_ESID_V) { |
910 | sregs.u.s.ppc64.slb[i].slbe |= i; | |
911 | } | |
f1af19d7 DG |
912 | sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid; |
913 | } | |
914 | #endif | |
915 | ||
916 | /* Sync SRs */ | |
917 | for (i = 0; i < 16; i++) { | |
918 | sregs.u.s.ppc32.sr[i] = env->sr[i]; | |
919 | } | |
920 | ||
921 | /* Sync BATs */ | |
922 | for (i = 0; i < 8; i++) { | |
ef8beb0e AG |
923 | /* Beware. We have to swap upper and lower bits here */ |
924 | sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32) | |
925 | | env->DBAT[1][i]; | |
926 | sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32) | |
927 | | env->IBAT[1][i]; | |
f1af19d7 DG |
928 | } |
929 | ||
1bc22652 | 930 | ret = kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); |
f1af19d7 DG |
931 | if (ret) { |
932 | return ret; | |
933 | } | |
934 | } | |
935 | ||
936 | if (cap_hior && (level >= KVM_PUT_RESET_STATE)) { | |
d67d40ea DG |
937 | kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); |
938 | } | |
f1af19d7 | 939 | |
d67d40ea DG |
940 | if (cap_one_reg) { |
941 | int i; | |
942 | ||
943 | /* We deliberately ignore errors here, for kernels which have | |
944 | * the ONE_REG calls, but don't support the specific | |
945 | * registers, there's a reasonable chance things will still | |
946 | * work, at least until we try to migrate. */ | |
947 | for (i = 0; i < 1024; i++) { | |
948 | uint64_t id = env->spr_cb[i].one_reg_id; | |
949 | ||
950 | if (id != 0) { | |
951 | kvm_put_one_spr(cs, id, i); | |
952 | } | |
f1af19d7 | 953 | } |
9b00ea49 DG |
954 | |
955 | #ifdef TARGET_PPC64 | |
80b3f79b AK |
956 | if (msr_ts) { |
957 | for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { | |
958 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); | |
959 | } | |
960 | for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { | |
961 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); | |
962 | } | |
963 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); | |
964 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); | |
965 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); | |
966 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); | |
967 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); | |
968 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); | |
969 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); | |
970 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); | |
971 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); | |
972 | kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); | |
973 | } | |
974 | ||
9b00ea49 DG |
975 | if (cap_papr) { |
976 | if (kvm_put_vpa(cs) < 0) { | |
da56ff91 | 977 | DPRINTF("Warning: Unable to set VPA information to KVM\n"); |
9b00ea49 DG |
978 | } |
979 | } | |
98a8b524 AK |
980 | |
981 | kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); | |
9b00ea49 | 982 | #endif /* TARGET_PPC64 */ |
f1af19d7 DG |
983 | } |
984 | ||
d76d1650 AJ |
985 | return ret; |
986 | } | |
987 | ||
c371c2e3 BB |
988 | static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor) |
989 | { | |
990 | env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR]; | |
991 | } | |
992 | ||
20d695a9 | 993 | int kvm_arch_get_registers(CPUState *cs) |
d76d1650 | 994 | { |
20d695a9 AF |
995 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
996 | CPUPPCState *env = &cpu->env; | |
d76d1650 | 997 | struct kvm_regs regs; |
ba5e5090 | 998 | struct kvm_sregs sregs; |
90dc8812 | 999 | uint32_t cr; |
138b38b6 | 1000 | int i, ret; |
d76d1650 | 1001 | |
1bc22652 | 1002 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, ®s); |
d76d1650 AJ |
1003 | if (ret < 0) |
1004 | return ret; | |
1005 | ||
90dc8812 SW |
1006 | cr = regs.cr; |
1007 | for (i = 7; i >= 0; i--) { | |
1008 | env->crf[i] = cr & 15; | |
1009 | cr >>= 4; | |
1010 | } | |
ba5e5090 | 1011 | |
d76d1650 AJ |
1012 | env->ctr = regs.ctr; |
1013 | env->lr = regs.lr; | |
da91a00f | 1014 | cpu_write_xer(env, regs.xer); |
d76d1650 AJ |
1015 | env->msr = regs.msr; |
1016 | env->nip = regs.pc; | |
1017 | ||
1018 | env->spr[SPR_SRR0] = regs.srr0; | |
1019 | env->spr[SPR_SRR1] = regs.srr1; | |
1020 | ||
1021 | env->spr[SPR_SPRG0] = regs.sprg0; | |
1022 | env->spr[SPR_SPRG1] = regs.sprg1; | |
1023 | env->spr[SPR_SPRG2] = regs.sprg2; | |
1024 | env->spr[SPR_SPRG3] = regs.sprg3; | |
1025 | env->spr[SPR_SPRG4] = regs.sprg4; | |
1026 | env->spr[SPR_SPRG5] = regs.sprg5; | |
1027 | env->spr[SPR_SPRG6] = regs.sprg6; | |
1028 | env->spr[SPR_SPRG7] = regs.sprg7; | |
1029 | ||
90dc8812 SW |
1030 | env->spr[SPR_BOOKE_PID] = regs.pid; |
1031 | ||
d76d1650 AJ |
1032 | for (i = 0;i < 32; i++) |
1033 | env->gpr[i] = regs.gpr[i]; | |
1034 | ||
70b79849 DG |
1035 | kvm_get_fp(cs); |
1036 | ||
90dc8812 | 1037 | if (cap_booke_sregs) { |
1bc22652 | 1038 | ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
90dc8812 SW |
1039 | if (ret < 0) { |
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | if (sregs.u.e.features & KVM_SREGS_E_BASE) { | |
1044 | env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; | |
1045 | env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; | |
1046 | env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr; | |
1047 | env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear; | |
1048 | env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr; | |
1049 | env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr; | |
1050 | env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr; | |
1051 | env->spr[SPR_DECR] = sregs.u.e.dec; | |
1052 | env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff; | |
1053 | env->spr[SPR_TBU] = sregs.u.e.tb >> 32; | |
1054 | env->spr[SPR_VRSAVE] = sregs.u.e.vrsave; | |
1055 | } | |
1056 | ||
1057 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { | |
1058 | env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir; | |
1059 | env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0; | |
1060 | env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1; | |
1061 | env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar; | |
1062 | env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr; | |
1063 | } | |
1064 | ||
1065 | if (sregs.u.e.features & KVM_SREGS_E_64) { | |
1066 | env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr; | |
1067 | } | |
1068 | ||
1069 | if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { | |
1070 | env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8; | |
1071 | } | |
1072 | ||
1073 | if (sregs.u.e.features & KVM_SREGS_E_IVOR) { | |
1074 | env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0]; | |
c371c2e3 | 1075 | kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); |
90dc8812 | 1076 | env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1]; |
c371c2e3 | 1077 | kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); |
90dc8812 | 1078 | env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2]; |
c371c2e3 | 1079 | kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); |
90dc8812 | 1080 | env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3]; |
c371c2e3 | 1081 | kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); |
90dc8812 | 1082 | env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4]; |
c371c2e3 | 1083 | kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); |
90dc8812 | 1084 | env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5]; |
c371c2e3 | 1085 | kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); |
90dc8812 | 1086 | env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6]; |
c371c2e3 | 1087 | kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); |
90dc8812 | 1088 | env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7]; |
c371c2e3 | 1089 | kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); |
90dc8812 | 1090 | env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8]; |
c371c2e3 | 1091 | kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); |
90dc8812 | 1092 | env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9]; |
c371c2e3 | 1093 | kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); |
90dc8812 | 1094 | env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10]; |
c371c2e3 | 1095 | kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); |
90dc8812 | 1096 | env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11]; |
c371c2e3 | 1097 | kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); |
90dc8812 | 1098 | env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12]; |
c371c2e3 | 1099 | kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); |
90dc8812 | 1100 | env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13]; |
c371c2e3 | 1101 | kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); |
90dc8812 | 1102 | env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14]; |
c371c2e3 | 1103 | kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); |
90dc8812 | 1104 | env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15]; |
c371c2e3 | 1105 | kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); |
90dc8812 SW |
1106 | |
1107 | if (sregs.u.e.features & KVM_SREGS_E_SPE) { | |
1108 | env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0]; | |
c371c2e3 | 1109 | kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); |
90dc8812 | 1110 | env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1]; |
c371c2e3 | 1111 | kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); |
90dc8812 | 1112 | env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2]; |
c371c2e3 | 1113 | kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); |
90dc8812 SW |
1114 | } |
1115 | ||
1116 | if (sregs.u.e.features & KVM_SREGS_E_PM) { | |
1117 | env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3]; | |
c371c2e3 | 1118 | kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); |
90dc8812 SW |
1119 | } |
1120 | ||
1121 | if (sregs.u.e.features & KVM_SREGS_E_PC) { | |
1122 | env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4]; | |
c371c2e3 | 1123 | kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); |
90dc8812 | 1124 | env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5]; |
c371c2e3 | 1125 | kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); |
90dc8812 SW |
1126 | } |
1127 | } | |
1128 | ||
1129 | if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { | |
1130 | env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0; | |
1131 | env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1; | |
1132 | env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2; | |
1133 | env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff; | |
1134 | env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4; | |
1135 | env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6; | |
1136 | env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32; | |
1137 | env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg; | |
1138 | env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0]; | |
1139 | env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1]; | |
1140 | } | |
1141 | ||
1142 | if (sregs.u.e.features & KVM_SREGS_EXP) { | |
1143 | env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr; | |
1144 | } | |
1145 | ||
1146 | if (sregs.u.e.features & KVM_SREGS_E_PD) { | |
1147 | env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc; | |
1148 | env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc; | |
1149 | } | |
1150 | ||
1151 | if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { | |
1152 | env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr; | |
1153 | env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar; | |
1154 | env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0; | |
1155 | ||
1156 | if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { | |
1157 | env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1; | |
1158 | env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; | |
1159 | } | |
1160 | } | |
fafc0b6a | 1161 | } |
90dc8812 | 1162 | |
90dc8812 | 1163 | if (cap_segstate) { |
1bc22652 | 1164 | ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); |
90dc8812 SW |
1165 | if (ret < 0) { |
1166 | return ret; | |
1167 | } | |
1168 | ||
f3c75d42 AK |
1169 | if (!env->external_htab) { |
1170 | ppc_store_sdr1(env, sregs.u.s.sdr1); | |
1171 | } | |
ba5e5090 AG |
1172 | |
1173 | /* Sync SLB */ | |
82c09f2f | 1174 | #ifdef TARGET_PPC64 |
4b4d4a21 AK |
1175 | /* |
1176 | * The packed SLB array we get from KVM_GET_SREGS only contains | |
1177 | * information about valid entries. So we flush our internal | |
1178 | * copy to get rid of stale ones, then put all valid SLB entries | |
1179 | * back in. | |
1180 | */ | |
1181 | memset(env->slb, 0, sizeof(env->slb)); | |
d83af167 | 1182 | for (i = 0; i < ARRAY_SIZE(env->slb); i++) { |
4b4d4a21 AK |
1183 | target_ulong rb = sregs.u.s.ppc64.slb[i].slbe; |
1184 | target_ulong rs = sregs.u.s.ppc64.slb[i].slbv; | |
1185 | /* | |
1186 | * Only restore valid entries | |
1187 | */ | |
1188 | if (rb & SLB_ESID_V) { | |
1189 | ppc_store_slb(env, rb, rs); | |
1190 | } | |
ba5e5090 | 1191 | } |
82c09f2f | 1192 | #endif |
ba5e5090 AG |
1193 | |
1194 | /* Sync SRs */ | |
1195 | for (i = 0; i < 16; i++) { | |
1196 | env->sr[i] = sregs.u.s.ppc32.sr[i]; | |
1197 | } | |
1198 | ||
1199 | /* Sync BATs */ | |
1200 | for (i = 0; i < 8; i++) { | |
1201 | env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff; | |
1202 | env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32; | |
1203 | env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; | |
1204 | env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; | |
1205 | } | |
fafc0b6a | 1206 | } |
ba5e5090 | 1207 | |
d67d40ea DG |
1208 | if (cap_hior) { |
1209 | kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR); | |
1210 | } | |
1211 | ||
1212 | if (cap_one_reg) { | |
1213 | int i; | |
1214 | ||
1215 | /* We deliberately ignore errors here, for kernels which have | |
1216 | * the ONE_REG calls, but don't support the specific | |
1217 | * registers, there's a reasonable chance things will still | |
1218 | * work, at least until we try to migrate. */ | |
1219 | for (i = 0; i < 1024; i++) { | |
1220 | uint64_t id = env->spr_cb[i].one_reg_id; | |
1221 | ||
1222 | if (id != 0) { | |
1223 | kvm_get_one_spr(cs, id, i); | |
1224 | } | |
1225 | } | |
9b00ea49 DG |
1226 | |
1227 | #ifdef TARGET_PPC64 | |
80b3f79b AK |
1228 | if (msr_ts) { |
1229 | for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) { | |
1230 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]); | |
1231 | } | |
1232 | for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) { | |
1233 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]); | |
1234 | } | |
1235 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr); | |
1236 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr); | |
1237 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr); | |
1238 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr); | |
1239 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr); | |
1240 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr); | |
1241 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave); | |
1242 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr); | |
1243 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr); | |
1244 | kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar); | |
1245 | } | |
1246 | ||
9b00ea49 DG |
1247 | if (cap_papr) { |
1248 | if (kvm_get_vpa(cs) < 0) { | |
da56ff91 | 1249 | DPRINTF("Warning: Unable to get VPA information from KVM\n"); |
9b00ea49 DG |
1250 | } |
1251 | } | |
98a8b524 AK |
1252 | |
1253 | kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset); | |
9b00ea49 | 1254 | #endif |
d67d40ea DG |
1255 | } |
1256 | ||
d76d1650 AJ |
1257 | return 0; |
1258 | } | |
1259 | ||
1bc22652 | 1260 | int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) |
fc87e185 AG |
1261 | { |
1262 | unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET; | |
1263 | ||
1264 | if (irq != PPC_INTERRUPT_EXT) { | |
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) { | |
1269 | return 0; | |
1270 | } | |
1271 | ||
1bc22652 | 1272 | kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); |
fc87e185 AG |
1273 | |
1274 | return 0; | |
1275 | } | |
1276 | ||
16415335 AG |
1277 | #if defined(TARGET_PPCEMB) |
1278 | #define PPC_INPUT_INT PPC40x_INPUT_INT | |
1279 | #elif defined(TARGET_PPC64) | |
1280 | #define PPC_INPUT_INT PPC970_INPUT_INT | |
1281 | #else | |
1282 | #define PPC_INPUT_INT PPC6xx_INPUT_INT | |
1283 | #endif | |
1284 | ||
20d695a9 | 1285 | void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) |
d76d1650 | 1286 | { |
20d695a9 AF |
1287 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
1288 | CPUPPCState *env = &cpu->env; | |
d76d1650 AJ |
1289 | int r; |
1290 | unsigned irq; | |
1291 | ||
4b8523ee JK |
1292 | qemu_mutex_lock_iothread(); |
1293 | ||
5cbdb3a3 | 1294 | /* PowerPC QEMU tracks the various core input pins (interrupt, critical |
d76d1650 | 1295 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */ |
fc87e185 AG |
1296 | if (!cap_interrupt_level && |
1297 | run->ready_for_interrupt_injection && | |
259186a7 | 1298 | (cs->interrupt_request & CPU_INTERRUPT_HARD) && |
16415335 | 1299 | (env->irq_input_state & (1<<PPC_INPUT_INT))) |
d76d1650 AJ |
1300 | { |
1301 | /* For now KVM disregards the 'irq' argument. However, in the | |
1302 | * future KVM could cache it in-kernel to avoid a heavyweight exit | |
1303 | * when reading the UIC. | |
1304 | */ | |
fc87e185 | 1305 | irq = KVM_INTERRUPT_SET; |
d76d1650 | 1306 | |
da56ff91 | 1307 | DPRINTF("injected interrupt %d\n", irq); |
1bc22652 | 1308 | r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq); |
55e5c285 AF |
1309 | if (r < 0) { |
1310 | printf("cpu %d fail inject %x\n", cs->cpu_index, irq); | |
1311 | } | |
c821c2bd AG |
1312 | |
1313 | /* Always wake up soon in case the interrupt was level based */ | |
bc72ad67 | 1314 | timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
c821c2bd | 1315 | (get_ticks_per_sec() / 50)); |
d76d1650 AJ |
1316 | } |
1317 | ||
1318 | /* We don't know if there are more interrupts pending after this. However, | |
1319 | * the guest will return to userspace in the course of handling this one | |
1320 | * anyways, so we will get a chance to deliver the rest. */ | |
4b8523ee JK |
1321 | |
1322 | qemu_mutex_unlock_iothread(); | |
d76d1650 AJ |
1323 | } |
1324 | ||
4c663752 | 1325 | MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) |
d76d1650 | 1326 | { |
4c663752 | 1327 | return MEMTXATTRS_UNSPECIFIED; |
d76d1650 AJ |
1328 | } |
1329 | ||
20d695a9 | 1330 | int kvm_arch_process_async_events(CPUState *cs) |
0af691d7 | 1331 | { |
259186a7 | 1332 | return cs->halted; |
0af691d7 MT |
1333 | } |
1334 | ||
259186a7 | 1335 | static int kvmppc_handle_halt(PowerPCCPU *cpu) |
d76d1650 | 1336 | { |
259186a7 AF |
1337 | CPUState *cs = CPU(cpu); |
1338 | CPUPPCState *env = &cpu->env; | |
1339 | ||
1340 | if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { | |
1341 | cs->halted = 1; | |
27103424 | 1342 | cs->exception_index = EXCP_HLT; |
d76d1650 AJ |
1343 | } |
1344 | ||
bb4ea393 | 1345 | return 0; |
d76d1650 AJ |
1346 | } |
1347 | ||
1348 | /* map dcr access to existing qemu dcr emulation */ | |
1328c2bf | 1349 | static int kvmppc_handle_dcr_read(CPUPPCState *env, uint32_t dcrn, uint32_t *data) |
d76d1650 AJ |
1350 | { |
1351 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) | |
1352 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); | |
1353 | ||
bb4ea393 | 1354 | return 0; |
d76d1650 AJ |
1355 | } |
1356 | ||
1328c2bf | 1357 | static int kvmppc_handle_dcr_write(CPUPPCState *env, uint32_t dcrn, uint32_t data) |
d76d1650 AJ |
1358 | { |
1359 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) | |
1360 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); | |
1361 | ||
bb4ea393 | 1362 | return 0; |
d76d1650 AJ |
1363 | } |
1364 | ||
8a0548f9 BB |
1365 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
1366 | { | |
1367 | /* Mixed endian case is not handled */ | |
1368 | uint32_t sc = debug_inst_opcode; | |
1369 | ||
1370 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, | |
1371 | sizeof(sc), 0) || | |
1372 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) { | |
1373 | return -EINVAL; | |
1374 | } | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) | |
1380 | { | |
1381 | uint32_t sc; | |
1382 | ||
1383 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) || | |
1384 | sc != debug_inst_opcode || | |
1385 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, | |
1386 | sizeof(sc), 1)) { | |
1387 | return -EINVAL; | |
1388 | } | |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | ||
88365d17 BB |
1393 | static int find_hw_breakpoint(target_ulong addr, int type) |
1394 | { | |
1395 | int n; | |
1396 | ||
1397 | assert((nb_hw_breakpoint + nb_hw_watchpoint) | |
1398 | <= ARRAY_SIZE(hw_debug_points)); | |
1399 | ||
1400 | for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { | |
1401 | if (hw_debug_points[n].addr == addr && | |
1402 | hw_debug_points[n].type == type) { | |
1403 | return n; | |
1404 | } | |
1405 | } | |
1406 | ||
1407 | return -1; | |
1408 | } | |
1409 | ||
1410 | static int find_hw_watchpoint(target_ulong addr, int *flag) | |
1411 | { | |
1412 | int n; | |
1413 | ||
1414 | n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS); | |
1415 | if (n >= 0) { | |
1416 | *flag = BP_MEM_ACCESS; | |
1417 | return n; | |
1418 | } | |
1419 | ||
1420 | n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE); | |
1421 | if (n >= 0) { | |
1422 | *flag = BP_MEM_WRITE; | |
1423 | return n; | |
1424 | } | |
1425 | ||
1426 | n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ); | |
1427 | if (n >= 0) { | |
1428 | *flag = BP_MEM_READ; | |
1429 | return n; | |
1430 | } | |
1431 | ||
1432 | return -1; | |
1433 | } | |
1434 | ||
1435 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
1436 | target_ulong len, int type) | |
1437 | { | |
1438 | if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) { | |
1439 | return -ENOBUFS; | |
1440 | } | |
1441 | ||
1442 | hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr; | |
1443 | hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type; | |
1444 | ||
1445 | switch (type) { | |
1446 | case GDB_BREAKPOINT_HW: | |
1447 | if (nb_hw_breakpoint >= max_hw_breakpoint) { | |
1448 | return -ENOBUFS; | |
1449 | } | |
1450 | ||
1451 | if (find_hw_breakpoint(addr, type) >= 0) { | |
1452 | return -EEXIST; | |
1453 | } | |
1454 | ||
1455 | nb_hw_breakpoint++; | |
1456 | break; | |
1457 | ||
1458 | case GDB_WATCHPOINT_WRITE: | |
1459 | case GDB_WATCHPOINT_READ: | |
1460 | case GDB_WATCHPOINT_ACCESS: | |
1461 | if (nb_hw_watchpoint >= max_hw_watchpoint) { | |
1462 | return -ENOBUFS; | |
1463 | } | |
1464 | ||
1465 | if (find_hw_breakpoint(addr, type) >= 0) { | |
1466 | return -EEXIST; | |
1467 | } | |
1468 | ||
1469 | nb_hw_watchpoint++; | |
1470 | break; | |
1471 | ||
1472 | default: | |
1473 | return -ENOSYS; | |
1474 | } | |
1475 | ||
1476 | return 0; | |
1477 | } | |
1478 | ||
1479 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
1480 | target_ulong len, int type) | |
1481 | { | |
1482 | int n; | |
1483 | ||
1484 | n = find_hw_breakpoint(addr, type); | |
1485 | if (n < 0) { | |
1486 | return -ENOENT; | |
1487 | } | |
1488 | ||
1489 | switch (type) { | |
1490 | case GDB_BREAKPOINT_HW: | |
1491 | nb_hw_breakpoint--; | |
1492 | break; | |
1493 | ||
1494 | case GDB_WATCHPOINT_WRITE: | |
1495 | case GDB_WATCHPOINT_READ: | |
1496 | case GDB_WATCHPOINT_ACCESS: | |
1497 | nb_hw_watchpoint--; | |
1498 | break; | |
1499 | ||
1500 | default: | |
1501 | return -ENOSYS; | |
1502 | } | |
1503 | hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint]; | |
1504 | ||
1505 | return 0; | |
1506 | } | |
1507 | ||
1508 | void kvm_arch_remove_all_hw_breakpoints(void) | |
1509 | { | |
1510 | nb_hw_breakpoint = nb_hw_watchpoint = 0; | |
1511 | } | |
1512 | ||
8a0548f9 BB |
1513 | void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) |
1514 | { | |
88365d17 BB |
1515 | int n; |
1516 | ||
8a0548f9 BB |
1517 | /* Software Breakpoint updates */ |
1518 | if (kvm_sw_breakpoints_active(cs)) { | |
1519 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; | |
1520 | } | |
88365d17 BB |
1521 | |
1522 | assert((nb_hw_breakpoint + nb_hw_watchpoint) | |
1523 | <= ARRAY_SIZE(hw_debug_points)); | |
1524 | assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp)); | |
1525 | ||
1526 | if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { | |
1527 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
1528 | memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp)); | |
1529 | for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) { | |
1530 | switch (hw_debug_points[n].type) { | |
1531 | case GDB_BREAKPOINT_HW: | |
1532 | dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT; | |
1533 | break; | |
1534 | case GDB_WATCHPOINT_WRITE: | |
1535 | dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE; | |
1536 | break; | |
1537 | case GDB_WATCHPOINT_READ: | |
1538 | dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ; | |
1539 | break; | |
1540 | case GDB_WATCHPOINT_ACCESS: | |
1541 | dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE | | |
1542 | KVMPPC_DEBUG_WATCH_READ; | |
1543 | break; | |
1544 | default: | |
1545 | cpu_abort(cs, "Unsupported breakpoint type\n"); | |
1546 | } | |
1547 | dbg->arch.bp[n].addr = hw_debug_points[n].addr; | |
1548 | } | |
1549 | } | |
8a0548f9 BB |
1550 | } |
1551 | ||
1552 | static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) | |
1553 | { | |
1554 | CPUState *cs = CPU(cpu); | |
1555 | CPUPPCState *env = &cpu->env; | |
1556 | struct kvm_debug_exit_arch *arch_info = &run->debug.arch; | |
1557 | int handle = 0; | |
88365d17 BB |
1558 | int n; |
1559 | int flag = 0; | |
8a0548f9 | 1560 | |
88365d17 BB |
1561 | if (cs->singlestep_enabled) { |
1562 | handle = 1; | |
1563 | } else if (arch_info->status) { | |
1564 | if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { | |
1565 | if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) { | |
1566 | n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW); | |
1567 | if (n >= 0) { | |
1568 | handle = 1; | |
1569 | } | |
1570 | } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ | | |
1571 | KVMPPC_DEBUG_WATCH_WRITE)) { | |
1572 | n = find_hw_watchpoint(arch_info->address, &flag); | |
1573 | if (n >= 0) { | |
1574 | handle = 1; | |
1575 | cs->watchpoint_hit = &hw_watchpoint; | |
1576 | hw_watchpoint.vaddr = hw_debug_points[n].addr; | |
1577 | hw_watchpoint.flags = flag; | |
1578 | } | |
1579 | } | |
1580 | } | |
1581 | } else if (kvm_find_sw_breakpoint(cs, arch_info->address)) { | |
8a0548f9 BB |
1582 | handle = 1; |
1583 | } else { | |
1584 | /* QEMU is not able to handle debug exception, so inject | |
1585 | * program exception to guest; | |
1586 | * Yes program exception NOT debug exception !! | |
88365d17 BB |
1587 | * When QEMU is using debug resources then debug exception must |
1588 | * be always set. To achieve this we set MSR_DE and also set | |
1589 | * MSRP_DEP so guest cannot change MSR_DE. | |
1590 | * When emulating debug resource for guest we want guest | |
1591 | * to control MSR_DE (enable/disable debug interrupt on need). | |
1592 | * Supporting both configurations are NOT possible. | |
1593 | * So the result is that we cannot share debug resources | |
1594 | * between QEMU and Guest on BOOKE architecture. | |
1595 | * In the current design QEMU gets the priority over guest, | |
1596 | * this means that if QEMU is using debug resources then guest | |
1597 | * cannot use them; | |
8a0548f9 BB |
1598 | * For software breakpoint QEMU uses a privileged instruction; |
1599 | * So there cannot be any reason that we are here for guest | |
1600 | * set debug exception, only possibility is guest executed a | |
1601 | * privileged / illegal instruction and that's why we are | |
1602 | * injecting a program interrupt. | |
1603 | */ | |
1604 | ||
1605 | cpu_synchronize_state(cs); | |
1606 | /* env->nip is PC, so increment this by 4 to use | |
1607 | * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4. | |
1608 | */ | |
1609 | env->nip += 4; | |
1610 | cs->exception_index = POWERPC_EXCP_PROGRAM; | |
1611 | env->error_code = POWERPC_EXCP_INVAL; | |
1612 | ppc_cpu_do_interrupt(cs); | |
1613 | } | |
1614 | ||
1615 | return handle; | |
1616 | } | |
1617 | ||
20d695a9 | 1618 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
d76d1650 | 1619 | { |
20d695a9 AF |
1620 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
1621 | CPUPPCState *env = &cpu->env; | |
bb4ea393 | 1622 | int ret; |
d76d1650 | 1623 | |
4b8523ee JK |
1624 | qemu_mutex_lock_iothread(); |
1625 | ||
d76d1650 AJ |
1626 | switch (run->exit_reason) { |
1627 | case KVM_EXIT_DCR: | |
1628 | if (run->dcr.is_write) { | |
da56ff91 | 1629 | DPRINTF("handle dcr write\n"); |
d76d1650 AJ |
1630 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); |
1631 | } else { | |
da56ff91 | 1632 | DPRINTF("handle dcr read\n"); |
d76d1650 AJ |
1633 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); |
1634 | } | |
1635 | break; | |
1636 | case KVM_EXIT_HLT: | |
da56ff91 | 1637 | DPRINTF("handle halt\n"); |
259186a7 | 1638 | ret = kvmppc_handle_halt(cpu); |
d76d1650 | 1639 | break; |
c6304a4a | 1640 | #if defined(TARGET_PPC64) |
f61b4bed | 1641 | case KVM_EXIT_PAPR_HCALL: |
da56ff91 | 1642 | DPRINTF("handle PAPR hypercall\n"); |
20d695a9 | 1643 | run->papr_hcall.ret = spapr_hypercall(cpu, |
aa100fa4 | 1644 | run->papr_hcall.nr, |
f61b4bed | 1645 | run->papr_hcall.args); |
78e8fde2 | 1646 | ret = 0; |
f61b4bed AG |
1647 | break; |
1648 | #endif | |
5b95b8b9 | 1649 | case KVM_EXIT_EPR: |
da56ff91 | 1650 | DPRINTF("handle epr\n"); |
933b19ea | 1651 | run->epr.epr = ldl_phys(cs->as, env->mpic_iack); |
5b95b8b9 AG |
1652 | ret = 0; |
1653 | break; | |
31f2cb8f | 1654 | case KVM_EXIT_WATCHDOG: |
da56ff91 | 1655 | DPRINTF("handle watchdog expiry\n"); |
31f2cb8f BB |
1656 | watchdog_perform_action(); |
1657 | ret = 0; | |
1658 | break; | |
1659 | ||
8a0548f9 BB |
1660 | case KVM_EXIT_DEBUG: |
1661 | DPRINTF("handle debug exception\n"); | |
1662 | if (kvm_handle_debug(cpu, run)) { | |
1663 | ret = EXCP_DEBUG; | |
1664 | break; | |
1665 | } | |
1666 | /* re-enter, this exception was guest-internal */ | |
1667 | ret = 0; | |
1668 | break; | |
1669 | ||
73aaec4a JK |
1670 | default: |
1671 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
1672 | ret = -1; | |
1673 | break; | |
d76d1650 AJ |
1674 | } |
1675 | ||
4b8523ee | 1676 | qemu_mutex_unlock_iothread(); |
d76d1650 AJ |
1677 | return ret; |
1678 | } | |
1679 | ||
31f2cb8f BB |
1680 | int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) |
1681 | { | |
1682 | CPUState *cs = CPU(cpu); | |
1683 | uint32_t bits = tsr_bits; | |
1684 | struct kvm_one_reg reg = { | |
1685 | .id = KVM_REG_PPC_OR_TSR, | |
1686 | .addr = (uintptr_t) &bits, | |
1687 | }; | |
1688 | ||
1689 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
1690 | } | |
1691 | ||
1692 | int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits) | |
1693 | { | |
1694 | ||
1695 | CPUState *cs = CPU(cpu); | |
1696 | uint32_t bits = tsr_bits; | |
1697 | struct kvm_one_reg reg = { | |
1698 | .id = KVM_REG_PPC_CLEAR_TSR, | |
1699 | .addr = (uintptr_t) &bits, | |
1700 | }; | |
1701 | ||
1702 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
1703 | } | |
1704 | ||
1705 | int kvmppc_set_tcr(PowerPCCPU *cpu) | |
1706 | { | |
1707 | CPUState *cs = CPU(cpu); | |
1708 | CPUPPCState *env = &cpu->env; | |
1709 | uint32_t tcr = env->spr[SPR_BOOKE_TCR]; | |
1710 | ||
1711 | struct kvm_one_reg reg = { | |
1712 | .id = KVM_REG_PPC_TCR, | |
1713 | .addr = (uintptr_t) &tcr, | |
1714 | }; | |
1715 | ||
1716 | return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); | |
1717 | } | |
1718 | ||
1719 | int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu) | |
1720 | { | |
1721 | CPUState *cs = CPU(cpu); | |
31f2cb8f BB |
1722 | int ret; |
1723 | ||
1724 | if (!kvm_enabled()) { | |
1725 | return -1; | |
1726 | } | |
1727 | ||
1728 | if (!cap_ppc_watchdog) { | |
1729 | printf("warning: KVM does not support watchdog"); | |
1730 | return -1; | |
1731 | } | |
1732 | ||
48add816 | 1733 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0); |
31f2cb8f BB |
1734 | if (ret < 0) { |
1735 | fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n", | |
1736 | __func__, strerror(-ret)); | |
1737 | return ret; | |
1738 | } | |
1739 | ||
1740 | return ret; | |
1741 | } | |
1742 | ||
dc333cd6 AG |
1743 | static int read_cpuinfo(const char *field, char *value, int len) |
1744 | { | |
1745 | FILE *f; | |
1746 | int ret = -1; | |
1747 | int field_len = strlen(field); | |
1748 | char line[512]; | |
1749 | ||
1750 | f = fopen("/proc/cpuinfo", "r"); | |
1751 | if (!f) { | |
1752 | return -1; | |
1753 | } | |
1754 | ||
1755 | do { | |
ef951443 | 1756 | if (!fgets(line, sizeof(line), f)) { |
dc333cd6 AG |
1757 | break; |
1758 | } | |
1759 | if (!strncmp(line, field, field_len)) { | |
ae215068 | 1760 | pstrcpy(value, len, line); |
dc333cd6 AG |
1761 | ret = 0; |
1762 | break; | |
1763 | } | |
1764 | } while(*line); | |
1765 | ||
1766 | fclose(f); | |
1767 | ||
1768 | return ret; | |
1769 | } | |
1770 | ||
1771 | uint32_t kvmppc_get_tbfreq(void) | |
1772 | { | |
1773 | char line[512]; | |
1774 | char *ns; | |
1775 | uint32_t retval = get_ticks_per_sec(); | |
1776 | ||
1777 | if (read_cpuinfo("timebase", line, sizeof(line))) { | |
1778 | return retval; | |
1779 | } | |
1780 | ||
1781 | if (!(ns = strchr(line, ':'))) { | |
1782 | return retval; | |
1783 | } | |
1784 | ||
1785 | ns++; | |
1786 | ||
f9b8e7f6 | 1787 | return atoi(ns); |
dc333cd6 | 1788 | } |
4513d923 | 1789 | |
ef951443 ND |
1790 | bool kvmppc_get_host_serial(char **value) |
1791 | { | |
1792 | return g_file_get_contents("/proc/device-tree/system-id", value, NULL, | |
1793 | NULL); | |
1794 | } | |
1795 | ||
1796 | bool kvmppc_get_host_model(char **value) | |
1797 | { | |
1798 | return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL); | |
1799 | } | |
1800 | ||
eadaada1 AG |
1801 | /* Try to find a device tree node for a CPU with clock-frequency property */ |
1802 | static int kvmppc_find_cpu_dt(char *buf, int buf_len) | |
1803 | { | |
1804 | struct dirent *dirp; | |
1805 | DIR *dp; | |
1806 | ||
1807 | if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) { | |
1808 | printf("Can't open directory " PROC_DEVTREE_CPU "\n"); | |
1809 | return -1; | |
1810 | } | |
1811 | ||
1812 | buf[0] = '\0'; | |
1813 | while ((dirp = readdir(dp)) != NULL) { | |
1814 | FILE *f; | |
1815 | snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU, | |
1816 | dirp->d_name); | |
1817 | f = fopen(buf, "r"); | |
1818 | if (f) { | |
1819 | snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name); | |
1820 | fclose(f); | |
1821 | break; | |
1822 | } | |
1823 | buf[0] = '\0'; | |
1824 | } | |
1825 | closedir(dp); | |
1826 | if (buf[0] == '\0') { | |
1827 | printf("Unknown host!\n"); | |
1828 | return -1; | |
1829 | } | |
1830 | ||
1831 | return 0; | |
1832 | } | |
1833 | ||
9bc884b7 DG |
1834 | /* Read a CPU node property from the host device tree that's a single |
1835 | * integer (32-bit or 64-bit). Returns 0 if anything goes wrong | |
1836 | * (can't find or open the property, or doesn't understand the | |
1837 | * format) */ | |
1838 | static uint64_t kvmppc_read_int_cpu_dt(const char *propname) | |
eadaada1 | 1839 | { |
cc64b1a1 | 1840 | char buf[PATH_MAX], *tmp; |
9bc884b7 DG |
1841 | union { |
1842 | uint32_t v32; | |
1843 | uint64_t v64; | |
1844 | } u; | |
eadaada1 AG |
1845 | FILE *f; |
1846 | int len; | |
1847 | ||
1848 | if (kvmppc_find_cpu_dt(buf, sizeof(buf))) { | |
9bc884b7 | 1849 | return -1; |
eadaada1 AG |
1850 | } |
1851 | ||
cc64b1a1 | 1852 | tmp = g_strdup_printf("%s/%s", buf, propname); |
eadaada1 | 1853 | |
cc64b1a1 CG |
1854 | f = fopen(tmp, "rb"); |
1855 | g_free(tmp); | |
eadaada1 AG |
1856 | if (!f) { |
1857 | return -1; | |
1858 | } | |
1859 | ||
9bc884b7 | 1860 | len = fread(&u, 1, sizeof(u), f); |
eadaada1 AG |
1861 | fclose(f); |
1862 | switch (len) { | |
9bc884b7 DG |
1863 | case 4: |
1864 | /* property is a 32-bit quantity */ | |
1865 | return be32_to_cpu(u.v32); | |
1866 | case 8: | |
1867 | return be64_to_cpu(u.v64); | |
eadaada1 AG |
1868 | } |
1869 | ||
1870 | return 0; | |
1871 | } | |
1872 | ||
9bc884b7 DG |
1873 | uint64_t kvmppc_get_clockfreq(void) |
1874 | { | |
1875 | return kvmppc_read_int_cpu_dt("clock-frequency"); | |
1876 | } | |
1877 | ||
6659394f DG |
1878 | uint32_t kvmppc_get_vmx(void) |
1879 | { | |
1880 | return kvmppc_read_int_cpu_dt("ibm,vmx"); | |
1881 | } | |
1882 | ||
1883 | uint32_t kvmppc_get_dfp(void) | |
1884 | { | |
1885 | return kvmppc_read_int_cpu_dt("ibm,dfp"); | |
1886 | } | |
1887 | ||
1a61a9ae SY |
1888 | static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo) |
1889 | { | |
1890 | PowerPCCPU *cpu = ppc_env_get_cpu(env); | |
1891 | CPUState *cs = CPU(cpu); | |
1892 | ||
6fd33a75 | 1893 | if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) && |
1a61a9ae SY |
1894 | !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) { |
1895 | return 0; | |
1896 | } | |
1897 | ||
1898 | return 1; | |
1899 | } | |
1900 | ||
1901 | int kvmppc_get_hasidle(CPUPPCState *env) | |
1902 | { | |
1903 | struct kvm_ppc_pvinfo pvinfo; | |
1904 | ||
1905 | if (!kvmppc_get_pvinfo(env, &pvinfo) && | |
1906 | (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) { | |
1907 | return 1; | |
1908 | } | |
1909 | ||
1910 | return 0; | |
1911 | } | |
1912 | ||
1328c2bf | 1913 | int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len) |
45024f09 AG |
1914 | { |
1915 | uint32_t *hc = (uint32_t*)buf; | |
45024f09 AG |
1916 | struct kvm_ppc_pvinfo pvinfo; |
1917 | ||
1a61a9ae | 1918 | if (!kvmppc_get_pvinfo(env, &pvinfo)) { |
45024f09 | 1919 | memcpy(buf, pvinfo.hcall, buf_len); |
45024f09 AG |
1920 | return 0; |
1921 | } | |
45024f09 AG |
1922 | |
1923 | /* | |
d13fc32e | 1924 | * Fallback to always fail hypercalls regardless of endianness: |
45024f09 | 1925 | * |
d13fc32e | 1926 | * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian) |
45024f09 | 1927 | * li r3, -1 |
d13fc32e AG |
1928 | * b .+8 (becomes nop in wrong endian) |
1929 | * bswap32(li r3, -1) | |
45024f09 AG |
1930 | */ |
1931 | ||
d13fc32e AG |
1932 | hc[0] = cpu_to_be32(0x08000048); |
1933 | hc[1] = cpu_to_be32(0x3860ffff); | |
1934 | hc[2] = cpu_to_be32(0x48000008); | |
1935 | hc[3] = cpu_to_be32(bswap32(0x3860ffff)); | |
45024f09 AG |
1936 | |
1937 | return 0; | |
1938 | } | |
1939 | ||
026bfd89 DG |
1940 | static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall) |
1941 | { | |
1942 | return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1); | |
1943 | } | |
1944 | ||
1945 | void kvmppc_enable_logical_ci_hcalls(void) | |
1946 | { | |
1947 | /* | |
1948 | * FIXME: it would be nice if we could detect the cases where | |
1949 | * we're using a device which requires the in kernel | |
1950 | * implementation of these hcalls, but the kernel lacks them and | |
1951 | * produce a warning. | |
1952 | */ | |
1953 | kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD); | |
1954 | kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE); | |
1955 | } | |
1956 | ||
ef9971dd AK |
1957 | void kvmppc_enable_set_mode_hcall(void) |
1958 | { | |
1959 | kvmppc_enable_hcall(kvm_state, H_SET_MODE); | |
1960 | } | |
1961 | ||
1bc22652 | 1962 | void kvmppc_set_papr(PowerPCCPU *cpu) |
f61b4bed | 1963 | { |
1bc22652 | 1964 | CPUState *cs = CPU(cpu); |
f61b4bed AG |
1965 | int ret; |
1966 | ||
48add816 | 1967 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0); |
f61b4bed | 1968 | if (ret) { |
a47dddd7 | 1969 | cpu_abort(cs, "This KVM version does not support PAPR\n"); |
94135e81 | 1970 | } |
9b00ea49 DG |
1971 | |
1972 | /* Update the capability flag so we sync the right information | |
1973 | * with kvm */ | |
1974 | cap_papr = 1; | |
f61b4bed AG |
1975 | } |
1976 | ||
6db5bb0f AK |
1977 | int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version) |
1978 | { | |
1979 | return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &cpu_version); | |
1980 | } | |
1981 | ||
5b95b8b9 AG |
1982 | void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy) |
1983 | { | |
5b95b8b9 | 1984 | CPUState *cs = CPU(cpu); |
5b95b8b9 AG |
1985 | int ret; |
1986 | ||
48add816 | 1987 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy); |
5b95b8b9 | 1988 | if (ret && mpic_proxy) { |
a47dddd7 | 1989 | cpu_abort(cs, "This KVM version does not support EPR\n"); |
5b95b8b9 AG |
1990 | } |
1991 | } | |
1992 | ||
e97c3636 DG |
1993 | int kvmppc_smt_threads(void) |
1994 | { | |
1995 | return cap_ppc_smt ? cap_ppc_smt : 1; | |
1996 | } | |
1997 | ||
7f763a5d | 1998 | #ifdef TARGET_PPC64 |
658fa66b | 1999 | off_t kvmppc_alloc_rma(void **rma) |
354ac20a | 2000 | { |
354ac20a DG |
2001 | off_t size; |
2002 | int fd; | |
2003 | struct kvm_allocate_rma ret; | |
354ac20a DG |
2004 | |
2005 | /* If cap_ppc_rma == 0, contiguous RMA allocation is not supported | |
2006 | * if cap_ppc_rma == 1, contiguous RMA allocation is supported, but | |
2007 | * not necessary on this hardware | |
2008 | * if cap_ppc_rma == 2, contiguous RMA allocation is needed on this hardware | |
2009 | * | |
2010 | * FIXME: We should allow the user to force contiguous RMA | |
2011 | * allocation in the cap_ppc_rma==1 case. | |
2012 | */ | |
2013 | if (cap_ppc_rma < 2) { | |
2014 | return 0; | |
2015 | } | |
2016 | ||
2017 | fd = kvm_vm_ioctl(kvm_state, KVM_ALLOCATE_RMA, &ret); | |
2018 | if (fd < 0) { | |
2019 | fprintf(stderr, "KVM: Error on KVM_ALLOCATE_RMA: %s\n", | |
2020 | strerror(errno)); | |
2021 | return -1; | |
2022 | } | |
2023 | ||
2024 | size = MIN(ret.rma_size, 256ul << 20); | |
2025 | ||
658fa66b AK |
2026 | *rma = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); |
2027 | if (*rma == MAP_FAILED) { | |
354ac20a DG |
2028 | fprintf(stderr, "KVM: Error mapping RMA: %s\n", strerror(errno)); |
2029 | return -1; | |
2030 | }; | |
2031 | ||
354ac20a DG |
2032 | return size; |
2033 | } | |
2034 | ||
7f763a5d DG |
2035 | uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift) |
2036 | { | |
f36951c1 DG |
2037 | struct kvm_ppc_smmu_info info; |
2038 | long rampagesize, best_page_shift; | |
2039 | int i; | |
2040 | ||
7f763a5d DG |
2041 | if (cap_ppc_rma >= 2) { |
2042 | return current_size; | |
2043 | } | |
f36951c1 DG |
2044 | |
2045 | /* Find the largest hardware supported page size that's less than | |
2046 | * or equal to the (logical) backing page size of guest RAM */ | |
182735ef | 2047 | kvm_get_smmu_info(POWERPC_CPU(first_cpu), &info); |
f36951c1 DG |
2048 | rampagesize = getrampagesize(); |
2049 | best_page_shift = 0; | |
2050 | ||
2051 | for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) { | |
2052 | struct kvm_ppc_one_seg_page_size *sps = &info.sps[i]; | |
2053 | ||
2054 | if (!sps->page_shift) { | |
2055 | continue; | |
2056 | } | |
2057 | ||
2058 | if ((sps->page_shift > best_page_shift) | |
2059 | && ((1UL << sps->page_shift) <= rampagesize)) { | |
2060 | best_page_shift = sps->page_shift; | |
2061 | } | |
2062 | } | |
2063 | ||
7f763a5d | 2064 | return MIN(current_size, |
f36951c1 | 2065 | 1ULL << (best_page_shift + hash_shift - 7)); |
7f763a5d DG |
2066 | } |
2067 | #endif | |
2068 | ||
da95324e AK |
2069 | bool kvmppc_spapr_use_multitce(void) |
2070 | { | |
2071 | return cap_spapr_multitce; | |
2072 | } | |
2073 | ||
9bb62a07 | 2074 | void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t window_size, int *pfd, |
6a81dd17 | 2075 | bool need_vfio) |
0f5cb298 DG |
2076 | { |
2077 | struct kvm_create_spapr_tce args = { | |
2078 | .liobn = liobn, | |
2079 | .window_size = window_size, | |
2080 | }; | |
2081 | long len; | |
2082 | int fd; | |
2083 | void *table; | |
2084 | ||
b5aec396 DG |
2085 | /* Must set fd to -1 so we don't try to munmap when called for |
2086 | * destroying the table, which the upper layers -will- do | |
2087 | */ | |
2088 | *pfd = -1; | |
6a81dd17 | 2089 | if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) { |
0f5cb298 DG |
2090 | return NULL; |
2091 | } | |
2092 | ||
2093 | fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args); | |
2094 | if (fd < 0) { | |
b5aec396 DG |
2095 | fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n", |
2096 | liobn); | |
0f5cb298 DG |
2097 | return NULL; |
2098 | } | |
2099 | ||
a83000f5 | 2100 | len = (window_size / SPAPR_TCE_PAGE_SIZE) * sizeof(uint64_t); |
0f5cb298 DG |
2101 | /* FIXME: round this up to page size */ |
2102 | ||
74b41e56 | 2103 | table = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); |
0f5cb298 | 2104 | if (table == MAP_FAILED) { |
b5aec396 DG |
2105 | fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n", |
2106 | liobn); | |
0f5cb298 DG |
2107 | close(fd); |
2108 | return NULL; | |
2109 | } | |
2110 | ||
2111 | *pfd = fd; | |
2112 | return table; | |
2113 | } | |
2114 | ||
523e7b8a | 2115 | int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table) |
0f5cb298 DG |
2116 | { |
2117 | long len; | |
2118 | ||
2119 | if (fd < 0) { | |
2120 | return -1; | |
2121 | } | |
2122 | ||
523e7b8a | 2123 | len = nb_table * sizeof(uint64_t); |
0f5cb298 DG |
2124 | if ((munmap(table, len) < 0) || |
2125 | (close(fd) < 0)) { | |
b5aec396 DG |
2126 | fprintf(stderr, "KVM: Unexpected error removing TCE table: %s", |
2127 | strerror(errno)); | |
0f5cb298 DG |
2128 | /* Leak the table */ |
2129 | } | |
2130 | ||
2131 | return 0; | |
2132 | } | |
2133 | ||
7f763a5d DG |
2134 | int kvmppc_reset_htab(int shift_hint) |
2135 | { | |
2136 | uint32_t shift = shift_hint; | |
2137 | ||
ace9a2cb DG |
2138 | if (!kvm_enabled()) { |
2139 | /* Full emulation, tell caller to allocate htab itself */ | |
2140 | return 0; | |
2141 | } | |
2142 | if (kvm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) { | |
7f763a5d DG |
2143 | int ret; |
2144 | ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift); | |
ace9a2cb DG |
2145 | if (ret == -ENOTTY) { |
2146 | /* At least some versions of PR KVM advertise the | |
2147 | * capability, but don't implement the ioctl(). Oops. | |
2148 | * Return 0 so that we allocate the htab in qemu, as is | |
2149 | * correct for PR. */ | |
2150 | return 0; | |
2151 | } else if (ret < 0) { | |
7f763a5d DG |
2152 | return ret; |
2153 | } | |
2154 | return shift; | |
2155 | } | |
2156 | ||
ace9a2cb DG |
2157 | /* We have a kernel that predates the htab reset calls. For PR |
2158 | * KVM, we need to allocate the htab ourselves, for an HV KVM of | |
2159 | * this era, it has allocated a 16MB fixed size hash table | |
2160 | * already. Kernels of this era have the GET_PVINFO capability | |
2161 | * only on PR, so we use this hack to determine the right | |
2162 | * answer */ | |
2163 | if (kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_PVINFO)) { | |
2164 | /* PR - tell caller to allocate htab */ | |
2165 | return 0; | |
2166 | } else { | |
2167 | /* HV - assume 16MB kernel allocated htab */ | |
2168 | return 24; | |
2169 | } | |
7f763a5d DG |
2170 | } |
2171 | ||
a1e98583 DG |
2172 | static inline uint32_t mfpvr(void) |
2173 | { | |
2174 | uint32_t pvr; | |
2175 | ||
2176 | asm ("mfpvr %0" | |
2177 | : "=r"(pvr)); | |
2178 | return pvr; | |
2179 | } | |
2180 | ||
a7342588 DG |
2181 | static void alter_insns(uint64_t *word, uint64_t flags, bool on) |
2182 | { | |
2183 | if (on) { | |
2184 | *word |= flags; | |
2185 | } else { | |
2186 | *word &= ~flags; | |
2187 | } | |
2188 | } | |
2189 | ||
2985b86b | 2190 | static void kvmppc_host_cpu_initfn(Object *obj) |
a1e98583 | 2191 | { |
2985b86b AF |
2192 | assert(kvm_enabled()); |
2193 | } | |
2194 | ||
2195 | static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data) | |
2196 | { | |
4c315c27 | 2197 | DeviceClass *dc = DEVICE_CLASS(oc); |
2985b86b | 2198 | PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); |
a7342588 DG |
2199 | uint32_t vmx = kvmppc_get_vmx(); |
2200 | uint32_t dfp = kvmppc_get_dfp(); | |
0cbad81f DG |
2201 | uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size"); |
2202 | uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size"); | |
a1e98583 | 2203 | |
cfe34f44 | 2204 | /* Now fix up the class with information we can query from the host */ |
3bc9ccc0 | 2205 | pcc->pvr = mfpvr(); |
a7342588 | 2206 | |
70bca53f AG |
2207 | if (vmx != -1) { |
2208 | /* Only override when we know what the host supports */ | |
cfe34f44 AF |
2209 | alter_insns(&pcc->insns_flags, PPC_ALTIVEC, vmx > 0); |
2210 | alter_insns(&pcc->insns_flags2, PPC2_VSX, vmx > 1); | |
70bca53f AG |
2211 | } |
2212 | if (dfp != -1) { | |
2213 | /* Only override when we know what the host supports */ | |
cfe34f44 | 2214 | alter_insns(&pcc->insns_flags2, PPC2_DFP, dfp); |
70bca53f | 2215 | } |
0cbad81f DG |
2216 | |
2217 | if (dcache_size != -1) { | |
2218 | pcc->l1_dcache_size = dcache_size; | |
2219 | } | |
2220 | ||
2221 | if (icache_size != -1) { | |
2222 | pcc->l1_icache_size = icache_size; | |
2223 | } | |
4c315c27 MA |
2224 | |
2225 | /* Reason: kvmppc_host_cpu_initfn() dies when !kvm_enabled() */ | |
2226 | dc->cannot_destroy_with_object_finalize_yet = true; | |
a1e98583 DG |
2227 | } |
2228 | ||
3b961124 SY |
2229 | bool kvmppc_has_cap_epr(void) |
2230 | { | |
2231 | return cap_epr; | |
2232 | } | |
2233 | ||
7c43bca0 AK |
2234 | bool kvmppc_has_cap_htab_fd(void) |
2235 | { | |
2236 | return cap_htab_fd; | |
2237 | } | |
2238 | ||
87a91de6 AG |
2239 | bool kvmppc_has_cap_fixup_hcalls(void) |
2240 | { | |
2241 | return cap_fixup_hcalls; | |
2242 | } | |
2243 | ||
5b79b1ca AK |
2244 | static PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) |
2245 | { | |
2246 | ObjectClass *oc = OBJECT_CLASS(pcc); | |
2247 | ||
2248 | while (oc && !object_class_is_abstract(oc)) { | |
2249 | oc = object_class_get_parent(oc); | |
2250 | } | |
2251 | assert(oc); | |
2252 | ||
2253 | return POWERPC_CPU_CLASS(oc); | |
2254 | } | |
2255 | ||
5ba4576b AF |
2256 | static int kvm_ppc_register_host_cpu_type(void) |
2257 | { | |
2258 | TypeInfo type_info = { | |
2259 | .name = TYPE_HOST_POWERPC_CPU, | |
2260 | .instance_init = kvmppc_host_cpu_initfn, | |
2261 | .class_init = kvmppc_host_cpu_class_init, | |
2262 | }; | |
2263 | uint32_t host_pvr = mfpvr(); | |
2264 | PowerPCCPUClass *pvr_pcc; | |
5b79b1ca | 2265 | DeviceClass *dc; |
5ba4576b AF |
2266 | |
2267 | pvr_pcc = ppc_cpu_class_by_pvr(host_pvr); | |
3bc9ccc0 AK |
2268 | if (pvr_pcc == NULL) { |
2269 | pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr); | |
2270 | } | |
5ba4576b AF |
2271 | if (pvr_pcc == NULL) { |
2272 | return -1; | |
2273 | } | |
2274 | type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); | |
2275 | type_register(&type_info); | |
5b79b1ca AK |
2276 | |
2277 | /* Register generic family CPU class for a family */ | |
2278 | pvr_pcc = ppc_cpu_get_family_class(pvr_pcc); | |
2279 | dc = DEVICE_CLASS(pvr_pcc); | |
2280 | type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc)); | |
2281 | type_info.name = g_strdup_printf("%s-"TYPE_POWERPC_CPU, dc->desc); | |
2282 | type_register(&type_info); | |
2283 | ||
5ba4576b AF |
2284 | return 0; |
2285 | } | |
2286 | ||
feaa64c4 DG |
2287 | int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function) |
2288 | { | |
2289 | struct kvm_rtas_token_args args = { | |
2290 | .token = token, | |
2291 | }; | |
2292 | ||
2293 | if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) { | |
2294 | return -ENOENT; | |
2295 | } | |
2296 | ||
2297 | strncpy(args.name, function, sizeof(args.name)); | |
2298 | ||
2299 | return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args); | |
2300 | } | |
12b1143b | 2301 | |
e68cb8b4 AK |
2302 | int kvmppc_get_htab_fd(bool write) |
2303 | { | |
2304 | struct kvm_get_htab_fd s = { | |
2305 | .flags = write ? KVM_GET_HTAB_WRITE : 0, | |
2306 | .start_index = 0, | |
2307 | }; | |
2308 | ||
2309 | if (!cap_htab_fd) { | |
2310 | fprintf(stderr, "KVM version doesn't support saving the hash table\n"); | |
2311 | return -1; | |
2312 | } | |
2313 | ||
2314 | return kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s); | |
2315 | } | |
2316 | ||
2317 | int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns) | |
2318 | { | |
bc72ad67 | 2319 | int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); |
e68cb8b4 AK |
2320 | uint8_t buf[bufsize]; |
2321 | ssize_t rc; | |
2322 | ||
2323 | do { | |
2324 | rc = read(fd, buf, bufsize); | |
2325 | if (rc < 0) { | |
2326 | fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n", | |
2327 | strerror(errno)); | |
2328 | return rc; | |
2329 | } else if (rc) { | |
e094c4c1 CLG |
2330 | uint8_t *buffer = buf; |
2331 | ssize_t n = rc; | |
2332 | while (n) { | |
2333 | struct kvm_get_htab_header *head = | |
2334 | (struct kvm_get_htab_header *) buffer; | |
2335 | size_t chunksize = sizeof(*head) + | |
2336 | HASH_PTE_SIZE_64 * head->n_valid; | |
2337 | ||
2338 | qemu_put_be32(f, head->index); | |
2339 | qemu_put_be16(f, head->n_valid); | |
2340 | qemu_put_be16(f, head->n_invalid); | |
2341 | qemu_put_buffer(f, (void *)(head + 1), | |
2342 | HASH_PTE_SIZE_64 * head->n_valid); | |
2343 | ||
2344 | buffer += chunksize; | |
2345 | n -= chunksize; | |
2346 | } | |
e68cb8b4 AK |
2347 | } |
2348 | } while ((rc != 0) | |
2349 | && ((max_ns < 0) | |
bc72ad67 | 2350 | || ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns))); |
e68cb8b4 AK |
2351 | |
2352 | return (rc == 0) ? 1 : 0; | |
2353 | } | |
2354 | ||
2355 | int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index, | |
2356 | uint16_t n_valid, uint16_t n_invalid) | |
2357 | { | |
2358 | struct kvm_get_htab_header *buf; | |
2359 | size_t chunksize = sizeof(*buf) + n_valid*HASH_PTE_SIZE_64; | |
2360 | ssize_t rc; | |
2361 | ||
2362 | buf = alloca(chunksize); | |
e68cb8b4 AK |
2363 | buf->index = index; |
2364 | buf->n_valid = n_valid; | |
2365 | buf->n_invalid = n_invalid; | |
2366 | ||
2367 | qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64*n_valid); | |
2368 | ||
2369 | rc = write(fd, buf, chunksize); | |
2370 | if (rc < 0) { | |
2371 | fprintf(stderr, "Error writing KVM hash table: %s\n", | |
2372 | strerror(errno)); | |
2373 | return rc; | |
2374 | } | |
2375 | if (rc != chunksize) { | |
2376 | /* We should never get a short write on a single chunk */ | |
2377 | fprintf(stderr, "Short write, restoring KVM hash table\n"); | |
2378 | return -1; | |
2379 | } | |
2380 | return 0; | |
2381 | } | |
2382 | ||
20d695a9 | 2383 | bool kvm_arch_stop_on_emulation_error(CPUState *cpu) |
4513d923 GN |
2384 | { |
2385 | return true; | |
2386 | } | |
a1b87fe0 | 2387 | |
20d695a9 | 2388 | int kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr) |
a1b87fe0 JK |
2389 | { |
2390 | return 1; | |
2391 | } | |
2392 | ||
2393 | int kvm_arch_on_sigbus(int code, void *addr) | |
2394 | { | |
2395 | return 1; | |
2396 | } | |
82169660 SW |
2397 | |
2398 | void kvm_arch_init_irq_routing(KVMState *s) | |
2399 | { | |
2400 | } | |
c65f9a07 | 2401 | |
7c43bca0 AK |
2402 | struct kvm_get_htab_buf { |
2403 | struct kvm_get_htab_header header; | |
2404 | /* | |
2405 | * We require one extra byte for read | |
2406 | */ | |
2407 | target_ulong hpte[(HPTES_PER_GROUP * 2) + 1]; | |
2408 | }; | |
2409 | ||
2410 | uint64_t kvmppc_hash64_read_pteg(PowerPCCPU *cpu, target_ulong pte_index) | |
2411 | { | |
2412 | int htab_fd; | |
2413 | struct kvm_get_htab_fd ghf; | |
2414 | struct kvm_get_htab_buf *hpte_buf; | |
2415 | ||
2416 | ghf.flags = 0; | |
2417 | ghf.start_index = pte_index; | |
2418 | htab_fd = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &ghf); | |
2419 | if (htab_fd < 0) { | |
2420 | goto error_out; | |
2421 | } | |
2422 | ||
2423 | hpte_buf = g_malloc0(sizeof(*hpte_buf)); | |
2424 | /* | |
2425 | * Read the hpte group | |
2426 | */ | |
2427 | if (read(htab_fd, hpte_buf, sizeof(*hpte_buf)) < 0) { | |
2428 | goto out_close; | |
2429 | } | |
2430 | ||
2431 | close(htab_fd); | |
2432 | return (uint64_t)(uintptr_t) hpte_buf->hpte; | |
2433 | ||
2434 | out_close: | |
2435 | g_free(hpte_buf); | |
2436 | close(htab_fd); | |
2437 | error_out: | |
2438 | return 0; | |
2439 | } | |
2440 | ||
2441 | void kvmppc_hash64_free_pteg(uint64_t token) | |
2442 | { | |
2443 | struct kvm_get_htab_buf *htab_buf; | |
2444 | ||
2445 | htab_buf = container_of((void *)(uintptr_t) token, struct kvm_get_htab_buf, | |
2446 | hpte); | |
2447 | g_free(htab_buf); | |
2448 | return; | |
2449 | } | |
c1385933 AK |
2450 | |
2451 | void kvmppc_hash64_write_pte(CPUPPCState *env, target_ulong pte_index, | |
2452 | target_ulong pte0, target_ulong pte1) | |
2453 | { | |
2454 | int htab_fd; | |
2455 | struct kvm_get_htab_fd ghf; | |
2456 | struct kvm_get_htab_buf hpte_buf; | |
2457 | ||
2458 | ghf.flags = 0; | |
2459 | ghf.start_index = 0; /* Ignored */ | |
2460 | htab_fd = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &ghf); | |
2461 | if (htab_fd < 0) { | |
2462 | goto error_out; | |
2463 | } | |
2464 | ||
2465 | hpte_buf.header.n_valid = 1; | |
2466 | hpte_buf.header.n_invalid = 0; | |
2467 | hpte_buf.header.index = pte_index; | |
2468 | hpte_buf.hpte[0] = pte0; | |
2469 | hpte_buf.hpte[1] = pte1; | |
2470 | /* | |
2471 | * Write the hpte entry. | |
2472 | * CAUTION: write() has the warn_unused_result attribute. Hence we | |
2473 | * need to check the return value, even though we do nothing. | |
2474 | */ | |
2475 | if (write(htab_fd, &hpte_buf, sizeof(hpte_buf)) < 0) { | |
2476 | goto out_close; | |
2477 | } | |
2478 | ||
2479 | out_close: | |
2480 | close(htab_fd); | |
2481 | return; | |
2482 | ||
2483 | error_out: | |
2484 | return; | |
2485 | } | |
9e03a040 FB |
2486 | |
2487 | int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, | |
dc9f06ca | 2488 | uint64_t address, uint32_t data, PCIDevice *dev) |
9e03a040 FB |
2489 | { |
2490 | return 0; | |
2491 | } | |
1850b6b7 EA |
2492 | |
2493 | int kvm_arch_msi_data_to_gsi(uint32_t data) | |
2494 | { | |
2495 | return data & 0xffff; | |
2496 | } | |
4d9392be TH |
2497 | |
2498 | int kvmppc_enable_hwrng(void) | |
2499 | { | |
2500 | if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) { | |
2501 | return -1; | |
2502 | } | |
2503 | ||
2504 | return kvmppc_enable_hcall(kvm_state, H_RANDOM); | |
2505 | } |