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d76d1650 AJ |
1 | /* |
2 | * PowerPC implementation of KVM hooks | |
3 | * | |
4 | * Copyright IBM Corp. 2007 | |
5 | * | |
6 | * Authors: | |
7 | * Jerone Young <jyoung5@us.ibm.com> | |
8 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com> | |
9 | * Hollis Blanchard <hollisb@us.ibm.com> | |
10 | * | |
11 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
12 | * See the COPYING file in the top-level directory. | |
13 | * | |
14 | */ | |
15 | ||
16 | #include <sys/types.h> | |
17 | #include <sys/ioctl.h> | |
18 | #include <sys/mman.h> | |
19 | ||
20 | #include <linux/kvm.h> | |
21 | ||
22 | #include "qemu-common.h" | |
23 | #include "qemu-timer.h" | |
24 | #include "sysemu.h" | |
25 | #include "kvm.h" | |
26 | #include "kvm_ppc.h" | |
27 | #include "cpu.h" | |
28 | #include "device_tree.h" | |
29 | ||
30 | //#define DEBUG_KVM | |
31 | ||
32 | #ifdef DEBUG_KVM | |
33 | #define dprintf(fmt, ...) \ | |
34 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) | |
35 | #else | |
36 | #define dprintf(fmt, ...) \ | |
37 | do { } while (0) | |
38 | #endif | |
39 | ||
40 | int kvm_arch_init(KVMState *s, int smp_cpus) | |
41 | { | |
42 | return 0; | |
43 | } | |
44 | ||
45 | int kvm_arch_init_vcpu(CPUState *cenv) | |
46 | { | |
861bbc80 AG |
47 | int ret = 0; |
48 | struct kvm_sregs sregs; | |
49 | ||
50 | sregs.pvr = cenv->spr[SPR_PVR]; | |
51 | ret = kvm_vcpu_ioctl(cenv, KVM_SET_SREGS, &sregs); | |
52 | ||
53 | return ret; | |
d76d1650 AJ |
54 | } |
55 | ||
caa5af0f JK |
56 | void kvm_arch_reset_vcpu(CPUState *env) |
57 | { | |
58 | } | |
59 | ||
d76d1650 AJ |
60 | int kvm_arch_put_registers(CPUState *env) |
61 | { | |
62 | struct kvm_regs regs; | |
63 | int ret; | |
64 | int i; | |
65 | ||
66 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
67 | if (ret < 0) | |
68 | return ret; | |
69 | ||
70 | regs.ctr = env->ctr; | |
71 | regs.lr = env->lr; | |
72 | regs.xer = env->xer; | |
73 | regs.msr = env->msr; | |
74 | regs.pc = env->nip; | |
75 | ||
76 | regs.srr0 = env->spr[SPR_SRR0]; | |
77 | regs.srr1 = env->spr[SPR_SRR1]; | |
78 | ||
79 | regs.sprg0 = env->spr[SPR_SPRG0]; | |
80 | regs.sprg1 = env->spr[SPR_SPRG1]; | |
81 | regs.sprg2 = env->spr[SPR_SPRG2]; | |
82 | regs.sprg3 = env->spr[SPR_SPRG3]; | |
83 | regs.sprg4 = env->spr[SPR_SPRG4]; | |
84 | regs.sprg5 = env->spr[SPR_SPRG5]; | |
85 | regs.sprg6 = env->spr[SPR_SPRG6]; | |
86 | regs.sprg7 = env->spr[SPR_SPRG7]; | |
87 | ||
88 | for (i = 0;i < 32; i++) | |
89 | regs.gpr[i] = env->gpr[i]; | |
90 | ||
91 | ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, ®s); | |
92 | if (ret < 0) | |
93 | return ret; | |
94 | ||
95 | return ret; | |
96 | } | |
97 | ||
98 | int kvm_arch_get_registers(CPUState *env) | |
99 | { | |
100 | struct kvm_regs regs; | |
101 | uint32_t i, ret; | |
102 | ||
103 | ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s); | |
104 | if (ret < 0) | |
105 | return ret; | |
106 | ||
107 | env->ctr = regs.ctr; | |
108 | env->lr = regs.lr; | |
109 | env->xer = regs.xer; | |
110 | env->msr = regs.msr; | |
111 | env->nip = regs.pc; | |
112 | ||
113 | env->spr[SPR_SRR0] = regs.srr0; | |
114 | env->spr[SPR_SRR1] = regs.srr1; | |
115 | ||
116 | env->spr[SPR_SPRG0] = regs.sprg0; | |
117 | env->spr[SPR_SPRG1] = regs.sprg1; | |
118 | env->spr[SPR_SPRG2] = regs.sprg2; | |
119 | env->spr[SPR_SPRG3] = regs.sprg3; | |
120 | env->spr[SPR_SPRG4] = regs.sprg4; | |
121 | env->spr[SPR_SPRG5] = regs.sprg5; | |
122 | env->spr[SPR_SPRG6] = regs.sprg6; | |
123 | env->spr[SPR_SPRG7] = regs.sprg7; | |
124 | ||
125 | for (i = 0;i < 32; i++) | |
126 | env->gpr[i] = regs.gpr[i]; | |
127 | ||
128 | return 0; | |
129 | } | |
130 | ||
16415335 AG |
131 | #if defined(TARGET_PPCEMB) |
132 | #define PPC_INPUT_INT PPC40x_INPUT_INT | |
133 | #elif defined(TARGET_PPC64) | |
134 | #define PPC_INPUT_INT PPC970_INPUT_INT | |
135 | #else | |
136 | #define PPC_INPUT_INT PPC6xx_INPUT_INT | |
137 | #endif | |
138 | ||
d76d1650 AJ |
139 | int kvm_arch_pre_run(CPUState *env, struct kvm_run *run) |
140 | { | |
141 | int r; | |
142 | unsigned irq; | |
143 | ||
144 | /* PowerPC Qemu tracks the various core input pins (interrupt, critical | |
145 | * interrupt, reset, etc) in PPC-specific env->irq_input_state. */ | |
146 | if (run->ready_for_interrupt_injection && | |
147 | (env->interrupt_request & CPU_INTERRUPT_HARD) && | |
16415335 | 148 | (env->irq_input_state & (1<<PPC_INPUT_INT))) |
d76d1650 AJ |
149 | { |
150 | /* For now KVM disregards the 'irq' argument. However, in the | |
151 | * future KVM could cache it in-kernel to avoid a heavyweight exit | |
152 | * when reading the UIC. | |
153 | */ | |
154 | irq = -1U; | |
155 | ||
156 | dprintf("injected interrupt %d\n", irq); | |
157 | r = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &irq); | |
158 | if (r < 0) | |
159 | printf("cpu %d fail inject %x\n", env->cpu_index, irq); | |
160 | } | |
161 | ||
162 | /* We don't know if there are more interrupts pending after this. However, | |
163 | * the guest will return to userspace in the course of handling this one | |
164 | * anyways, so we will get a chance to deliver the rest. */ | |
165 | return 0; | |
166 | } | |
167 | ||
168 | int kvm_arch_post_run(CPUState *env, struct kvm_run *run) | |
169 | { | |
170 | return 0; | |
171 | } | |
172 | ||
173 | static int kvmppc_handle_halt(CPUState *env) | |
174 | { | |
175 | if (!(env->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { | |
176 | env->halted = 1; | |
177 | env->exception_index = EXCP_HLT; | |
178 | } | |
179 | ||
180 | return 1; | |
181 | } | |
182 | ||
183 | /* map dcr access to existing qemu dcr emulation */ | |
184 | static int kvmppc_handle_dcr_read(CPUState *env, uint32_t dcrn, uint32_t *data) | |
185 | { | |
186 | if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) | |
187 | fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn); | |
188 | ||
189 | return 1; | |
190 | } | |
191 | ||
192 | static int kvmppc_handle_dcr_write(CPUState *env, uint32_t dcrn, uint32_t data) | |
193 | { | |
194 | if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) | |
195 | fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn); | |
196 | ||
197 | return 1; | |
198 | } | |
199 | ||
200 | int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run) | |
201 | { | |
202 | int ret = 0; | |
203 | ||
204 | switch (run->exit_reason) { | |
205 | case KVM_EXIT_DCR: | |
206 | if (run->dcr.is_write) { | |
207 | dprintf("handle dcr write\n"); | |
208 | ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data); | |
209 | } else { | |
210 | dprintf("handle dcr read\n"); | |
211 | ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data); | |
212 | } | |
213 | break; | |
214 | case KVM_EXIT_HLT: | |
215 | dprintf("handle halt\n"); | |
216 | ret = kvmppc_handle_halt(env); | |
217 | break; | |
218 | } | |
219 | ||
220 | return ret; | |
221 | } | |
222 |