[mirror_qemu.git] / target-ppc / machine.c

#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "sysemu/kvm.h"
#include "helper_regs.h"
#include "mmu-hash64.h"
#include "migration/cpu.h"

static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    unsigned int i, j;
    target_ulong sdr1;
    uint32_t fpscr;
    target_ulong xer;

    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gpr[i]);
#if !defined(TARGET_PPC64)
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gprh[i]);
#endif
    qemu_get_betls(f, &env->lr);
    qemu_get_betls(f, &env->ctr);
    for (i = 0; i < 8; i++)
        qemu_get_be32s(f, &env->crf[i]);
    qemu_get_betls(f, &xer);
    cpu_write_xer(env, xer);
    qemu_get_betls(f, &env->reserve_addr);
    qemu_get_betls(f, &env->msr);
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->tgpr[i]);
    for (i = 0; i < 32; i++) {
        union {
            float64 d;
            uint64_t l;
        } u;
        u.l = qemu_get_be64(f);
        env->fpr[i] = u.d;
    }
    qemu_get_be32s(f, &fpscr);
    env->fpscr = fpscr;
    qemu_get_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
    qemu_get_betls(f, &env->spr[SPR_ASR]);
    qemu_get_sbe32s(f, &env->slb_nr);
#endif
    qemu_get_betls(f, &sdr1);
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->sr[i]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->DBAT[i][j]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->IBAT[i][j]);
    qemu_get_sbe32s(f, &env->nb_tlb);
    qemu_get_sbe32s(f, &env->tlb_per_way);
    qemu_get_sbe32s(f, &env->nb_ways);
    qemu_get_sbe32s(f, &env->last_way);
    qemu_get_sbe32s(f, &env->id_tlbs);
    qemu_get_sbe32s(f, &env->nb_pids);
    if (env->tlb.tlb6) {
        // XXX assumes 6xx
        for (i = 0; i < env->nb_tlb; i++) {
            qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
            qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
            qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
        }
    }
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->pb[i]);
    for (i = 0; i < 1024; i++)
        qemu_get_betls(f, &env->spr[i]);
    if (!env->external_htab) {
        ppc_store_sdr1(env, sdr1);
    }
    qemu_get_be32s(f, &env->vscr);
    qemu_get_be64s(f, &env->spe_acc);
    qemu_get_be32s(f, &env->spe_fscr);
    qemu_get_betls(f, &env->msr_mask);
    qemu_get_be32s(f, &env->flags);
    qemu_get_sbe32s(f, &env->error_code);
    qemu_get_be32s(f, &env->pending_interrupts);
    qemu_get_be32s(f, &env->irq_input_state);
    for (i = 0; i < POWERPC_EXCP_NB; i++)
        qemu_get_betls(f, &env->excp_vectors[i]);
    qemu_get_betls(f, &env->excp_prefix);
    qemu_get_betls(f, &env->ivor_mask);
    qemu_get_betls(f, &env->ivpr_mask);
    qemu_get_betls(f, &env->hreset_vector);
    qemu_get_betls(f, &env->nip);
    qemu_get_betls(f, &env->hflags);
    qemu_get_betls(f, &env->hflags_nmsr);
    qemu_get_sbe32s(f, &env->mmu_idx);
    qemu_get_sbe32(f); /* Discard unused power_mode */

    return 0;
}

static int get_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    v->u64[0] = qemu_get_be64(f);
    v->u64[1] = qemu_get_be64(f);

    return 0;
}

static void put_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    qemu_put_be64(f, v->u64[0]);
    qemu_put_be64(f, v->u64[1]);
}

static const VMStateInfo vmstate_info_avr = {
    .name = "avr",
    .get  = get_avr,
    .put  = put_avr,
};

#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)

#define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
    VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)

static void cpu_pre_save(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;

    env->spr[SPR_LR] = env->lr;
    env->spr[SPR_CTR] = env->ctr;
    env->spr[SPR_XER] = cpu_read_xer(env);
#if defined(TARGET_PPC64)
    env->spr[SPR_CFAR] = env->cfar;
#endif
    env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
        env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
        env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
        env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
        env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
        env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
        env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
    }
}

static int cpu_post_load(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;
    target_ulong msr;

    /*
     * We always ignore the source PVR. The user or management
     * software has to take care of running QEMU in a compatible mode.
     */
    env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
    env->lr = env->spr[SPR_LR];
    env->ctr = env->spr[SPR_CTR];
    cpu_write_xer(env, env->spr[SPR_XER]);
#if defined(TARGET_PPC64)
    env->cfar = env->spr[SPR_CFAR];
#endif
    env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
        env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
        env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
        env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
        env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
        env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
        env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
    }

    if (!env->external_htab) {
        /* Restore htab_base and htab_mask variables */
        ppc_store_sdr1(env, env->spr[SPR_SDR1]);
    }

    /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
    msr = env->msr;
    env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
    ppc_store_msr(env, msr);

    hreg_compute_mem_idx(env);

    return 0;
}

static bool fpu_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_FLOAT);
}

static const VMStateDescription vmstate_fpu = {
    .name = "cpu/fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = fpu_needed,
    .fields = (VMStateField[]) {
        VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
        VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool altivec_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_ALTIVEC);
}

static const VMStateDescription vmstate_altivec = {
    .name = "cpu/altivec",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = altivec_needed,
    .fields = (VMStateField[]) {
        VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
        VMSTATE_UINT32(env.vscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool vsx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags2 & PPC2_VSX);
}

static const VMStateDescription vmstate_vsx = {
    .name = "cpu/vsx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = vsx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
/* Transactional memory state */
static bool tm_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    return msr_ts;
}

static const VMStateDescription vmstate_tm = {
    .name = "cpu/tm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .needed = tm_needed,
    .fields      = (VMStateField []) {
        VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
        VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
        VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
        VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};
#endif

static bool sr_needed(void *opaque)
{
#ifdef TARGET_PPC64
    PowerPCCPU *cpu = opaque;

    return !(cpu->env.mmu_model & POWERPC_MMU_64);
#else
    return true;
#endif
}

static const VMStateDescription vmstate_sr = {
    .name = "cpu/sr",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = sr_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
static int get_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    v->esid = qemu_get_be64(f);
    v->vsid = qemu_get_be64(f);

    return 0;
}

static void put_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    qemu_put_be64(f, v->esid);
    qemu_put_be64(f, v->vsid);
}

static const VMStateInfo vmstate_info_slbe = {
    .name = "slbe",
    .get  = get_slbe,
    .put  = put_slbe,
};

#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)

#define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
    VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)

static bool slb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    /* We don't support any of the old segment table based 64-bit CPUs */
    return (cpu->env.mmu_model & POWERPC_MMU_64);
}

static int slb_post_load(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;

    /* We've pulled in the raw esid and vsid values from the migration
     * stream, but we need to recompute the page size pointers */
    for (i = 0; i < env->slb_nr; i++) {
        if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
            /* Migration source had bad values in its SLB */
            return -1;
        }
    }

    return 0;
}

static const VMStateDescription vmstate_slb = {
    .name = "cpu/slb",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = slb_needed,
    .post_load = slb_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
        VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
        VMSTATE_END_OF_LIST()
    }
};
#endif /* TARGET_PPC64 */

static const VMStateDescription vmstate_tlb6xx_entry = {
    .name = "cpu/tlb6xx_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
        VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
        VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlb6xx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_6XX);
}

static const VMStateDescription vmstate_tlb6xx = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlb6xx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlb6xx_entry,
                                            ppc6xx_tlb_t),
        VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_tlbemb_entry = {
    .name = "cpu/tlbemb_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(RPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(PID, ppcemb_tlb_t),
        VMSTATE_UINTTL(size, ppcemb_tlb_t),
        VMSTATE_UINT32(prot, ppcemb_tlb_t),
        VMSTATE_UINT32(attr, ppcemb_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbemb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_EMB);
}

static bool pbr403_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    uint32_t pvr = cpu->env.spr[SPR_PVR];

    return (pvr & 0xffff0000) == 0x00200000;
}

static const VMStateDescription vmstate_pbr403 = {
    .name = "cpu/pbr403",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pbr403_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    },
};

static const VMStateDescription vmstate_tlbemb = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbemb_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbemb_entry,
                                            ppcemb_tlb_t),
        /* 403 protection registers */
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_pbr403,
        NULL
    }
};

static const VMStateDescription vmstate_tlbmas_entry = {
    .name = "cpu/tlbmas_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(mas8, ppcmas_tlb_t),
        VMSTATE_UINT32(mas1, ppcmas_tlb_t),
        VMSTATE_UINT64(mas2, ppcmas_tlb_t),
        VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbmas_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_MAS);
}

static const VMStateDescription vmstate_tlbmas = {
    .name = "cpu/tlbmas",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbmas_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbmas_entry,
                                            ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_ppc_cpu = {
    .name = "cpu",
    .version_id = 5,
    .minimum_version_id = 5,
    .minimum_version_id_old = 4,
    .load_state_old = cpu_load_old,
    .pre_save = cpu_pre_save,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */

        /* User mode architected state */
        VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
#if !defined(TARGET_PPC64)
        VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
#endif
        VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
        VMSTATE_UINTTL(env.nip, PowerPCCPU),

        /* SPRs */
        VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
        VMSTATE_UINT64(env.spe_acc, PowerPCCPU),

        /* Reservation */
        VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),

        /* Supervisor mode architected state */
        VMSTATE_UINTTL(env.msr, PowerPCCPU),

        /* Internal state */
        VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
        /* FIXME: access_type? */

        /* Sanity checking */
        VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
        VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
        VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
        VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_fpu,
        &vmstate_altivec,
        &vmstate_vsx,
        &vmstate_sr,
#ifdef TARGET_PPC64
        &vmstate_tm,
        &vmstate_slb,
#endif /* TARGET_PPC64 */
        &vmstate_tlb6xx,
        &vmstate_tlbemb,
        &vmstate_tlbmas,
        NULL
    }
};
Commit	Line	Data
0d75590d	1	#include "qemu/osdep.h"
33c11879 PB	2	#include "qemu-common.h"
33c11879 PB	3	#include "cpu.h"
8dd3dca3 AJ	4	#include "hw/hw.h"
8dd3dca3 AJ	5	#include "hw/boards.h"
9c17d615	6	#include "sysemu/kvm.h"
a90db158	7	#include "helper_regs.h"
cd6a9bb6	8	#include "mmu-hash64.h"
1e00b8d5	9	#include "migration/cpu.h"
8dd3dca3	10
a90db158	11	static int cpu_load_old(QEMUFile f, void opaque, int version_id)
8dd3dca3	12	{
a90db158 AK	13	PowerPCCPU *cpu = opaque;
a90db158 AK	14	CPUPPCState *env = &cpu->env;
a456d59c	15	unsigned int i, j;
bb593904	16	target_ulong sdr1;
30304420	17	uint32_t fpscr;
da91a00f	18	target_ulong xer;
a456d59c BS	19
	20	for (i = 0; i < 32; i++)
	21	qemu_get_betls(f, &env->gpr[i]);
	22	#if !defined(TARGET_PPC64)
	23	for (i = 0; i < 32; i++)
	24	qemu_get_betls(f, &env->gprh[i]);
	25	#endif
	26	qemu_get_betls(f, &env->lr);
	27	qemu_get_betls(f, &env->ctr);
	28	for (i = 0; i < 8; i++)
	29	qemu_get_be32s(f, &env->crf[i]);
da91a00f RH	30	qemu_get_betls(f, &xer);
da91a00f RH	31	cpu_write_xer(env, xer);
18b21a2f	32	qemu_get_betls(f, &env->reserve_addr);
a456d59c BS	33	qemu_get_betls(f, &env->msr);
	34	for (i = 0; i < 4; i++)
	35	qemu_get_betls(f, &env->tgpr[i]);
	36	for (i = 0; i < 32; i++) {
	37	union {
	38	float64 d;
	39	uint64_t l;
	40	} u;
	41	u.l = qemu_get_be64(f);
	42	env->fpr[i] = u.d;
	43	}
30304420 DG	44	qemu_get_be32s(f, &fpscr);
30304420 DG	45	env->fpscr = fpscr;
a456d59c	46	qemu_get_sbe32s(f, &env->access_type);
a456d59c	47	#if defined(TARGET_PPC64)
9baea4a3	48	qemu_get_betls(f, &env->spr[SPR_ASR]);
a456d59c BS	49	qemu_get_sbe32s(f, &env->slb_nr);
a456d59c BS	50	#endif
bb593904	51	qemu_get_betls(f, &sdr1);
a456d59c BS	52	for (i = 0; i < 32; i++)
	53	qemu_get_betls(f, &env->sr[i]);
	54	for (i = 0; i < 2; i++)
	55	for (j = 0; j < 8; j++)
	56	qemu_get_betls(f, &env->DBAT[i][j]);
	57	for (i = 0; i < 2; i++)
	58	for (j = 0; j < 8; j++)
	59	qemu_get_betls(f, &env->IBAT[i][j]);
	60	qemu_get_sbe32s(f, &env->nb_tlb);
	61	qemu_get_sbe32s(f, &env->tlb_per_way);
	62	qemu_get_sbe32s(f, &env->nb_ways);
	63	qemu_get_sbe32s(f, &env->last_way);
	64	qemu_get_sbe32s(f, &env->id_tlbs);
	65	qemu_get_sbe32s(f, &env->nb_pids);
1c53accc	66	if (env->tlb.tlb6) {
a456d59c BS	67	// XXX assumes 6xx
a456d59c BS	68	for (i = 0; i < env->nb_tlb; i++) {
1c53accc AG	69	qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
	70	qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
	71	qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
a456d59c BS	72	}
	73	}
	74	for (i = 0; i < 4; i++)
	75	qemu_get_betls(f, &env->pb[i]);
a456d59c BS	76	for (i = 0; i < 1024; i++)
a456d59c BS	77	qemu_get_betls(f, &env->spr[i]);
f3c75d42 AK	78	if (!env->external_htab) {
	79	ppc_store_sdr1(env, sdr1);
	80	}
a456d59c BS	81	qemu_get_be32s(f, &env->vscr);
	82	qemu_get_be64s(f, &env->spe_acc);
	83	qemu_get_be32s(f, &env->spe_fscr);
	84	qemu_get_betls(f, &env->msr_mask);
	85	qemu_get_be32s(f, &env->flags);
	86	qemu_get_sbe32s(f, &env->error_code);
	87	qemu_get_be32s(f, &env->pending_interrupts);
a456d59c BS	88	qemu_get_be32s(f, &env->irq_input_state);
	89	for (i = 0; i < POWERPC_EXCP_NB; i++)
	90	qemu_get_betls(f, &env->excp_vectors[i]);
	91	qemu_get_betls(f, &env->excp_prefix);
	92	qemu_get_betls(f, &env->ivor_mask);
	93	qemu_get_betls(f, &env->ivpr_mask);
	94	qemu_get_betls(f, &env->hreset_vector);
a456d59c BS	95	qemu_get_betls(f, &env->nip);
	96	qemu_get_betls(f, &env->hflags);
	97	qemu_get_betls(f, &env->hflags_nmsr);
	98	qemu_get_sbe32s(f, &env->mmu_idx);
011aba24	99	qemu_get_sbe32(f); /* Discard unused power_mode */
a456d59c	100
8dd3dca3 AJ	101	return 0;
8dd3dca3 AJ	102	}
a90db158 AK	103
	104	static int get_avr(QEMUFile f, void pv, size_t size)
	105	{
	106	ppc_avr_t *v = pv;
	107
	108	v->u64[0] = qemu_get_be64(f);
	109	v->u64[1] = qemu_get_be64(f);
	110
	111	return 0;
	112	}
	113
	114	static void put_avr(QEMUFile f, void pv, size_t size)
	115	{
	116	ppc_avr_t *v = pv;
	117
	118	qemu_put_be64(f, v->u64[0]);
	119	qemu_put_be64(f, v->u64[1]);
	120	}
	121
cfd54a04	122	static const VMStateInfo vmstate_info_avr = {
a90db158 AK	123	.name = "avr",
	124	.get = get_avr,
	125	.put = put_avr,
	126	};
	127
	128	#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
	129	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
	130
	131	#define VMSTATE_AVR_ARRAY(_f, _s, _n) \
	132	VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
	133
	134	static void cpu_pre_save(void *opaque)
	135	{
	136	PowerPCCPU *cpu = opaque;
	137	CPUPPCState *env = &cpu->env;
	138	int i;
	139
	140	env->spr[SPR_LR] = env->lr;
	141	env->spr[SPR_CTR] = env->ctr;
aa378598	142	env->spr[SPR_XER] = cpu_read_xer(env);
a90db158 AK	143	#if defined(TARGET_PPC64)
	144	env->spr[SPR_CFAR] = env->cfar;
	145	#endif
	146	env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
	147
	148	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	149	env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
	150	env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
	151	env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
	152	env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
	153	}
	154	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	155	env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
	156	env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
	157	env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
	158	env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
	159	}
	160	}
	161
	162	static int cpu_post_load(void *opaque, int version_id)
	163	{
	164	PowerPCCPU *cpu = opaque;
	165	CPUPPCState *env = &cpu->env;
	166	int i;
2360b6e8	167	target_ulong msr;
a90db158	168
569be9f0 AK	169	/*
	170	* We always ignore the source PVR. The user or management
	171	* software has to take care of running QEMU in a compatible mode.
	172	*/
	173	env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
a90db158 AK	174	env->lr = env->spr[SPR_LR];
a90db158 AK	175	env->ctr = env->spr[SPR_CTR];
6a9620e6	176	cpu_write_xer(env, env->spr[SPR_XER]);
a90db158 AK	177	#if defined(TARGET_PPC64)
	178	env->cfar = env->spr[SPR_CFAR];
	179	#endif
	180	env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
	181
	182	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	183	env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
	184	env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
	185	env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
	186	env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
	187	}
	188	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	189	env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
	190	env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
	191	env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
	192	env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
	193	}
	194
f3c75d42 AK	195	if (!env->external_htab) {
	196	/* Restore htab_base and htab_mask variables */
	197	ppc_store_sdr1(env, env->spr[SPR_SDR1]);
	198	}
2360b6e8	199
993ebe4a	200	/* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
2360b6e8	201	msr = env->msr;
993ebe4a	202	env->msr ^= ~((1ULL << MSR_TGPR) \| MSR_HVB);
2360b6e8 MCA	203	ppc_store_msr(env, msr);
2360b6e8 MCA	204
a90db158 AK	205	hreg_compute_mem_idx(env);
	206
	207	return 0;
	208	}
	209
	210	static bool fpu_needed(void *opaque)
	211	{
	212	PowerPCCPU *cpu = opaque;
	213
	214	return (cpu->env.insns_flags & PPC_FLOAT);
	215	}
	216
	217	static const VMStateDescription vmstate_fpu = {
	218	.name = "cpu/fpu",
	219	.version_id = 1,
	220	.minimum_version_id = 1,
5cd8cada	221	.needed = fpu_needed,
3aff6c2f	222	.fields = (VMStateField[]) {
a90db158 AK	223	VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
	224	VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
	225	VMSTATE_END_OF_LIST()
	226	},
	227	};
	228
	229	static bool altivec_needed(void *opaque)
	230	{
	231	PowerPCCPU *cpu = opaque;
	232
	233	return (cpu->env.insns_flags & PPC_ALTIVEC);
	234	}
	235
	236	static const VMStateDescription vmstate_altivec = {
	237	.name = "cpu/altivec",
	238	.version_id = 1,
	239	.minimum_version_id = 1,
5cd8cada	240	.needed = altivec_needed,
3aff6c2f	241	.fields = (VMStateField[]) {
a90db158 AK	242	VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
	243	VMSTATE_UINT32(env.vscr, PowerPCCPU),
	244	VMSTATE_END_OF_LIST()
	245	},
	246	};
	247
	248	static bool vsx_needed(void *opaque)
	249	{
	250	PowerPCCPU *cpu = opaque;
	251
	252	return (cpu->env.insns_flags2 & PPC2_VSX);
	253	}
	254
	255	static const VMStateDescription vmstate_vsx = {
	256	.name = "cpu/vsx",
	257	.version_id = 1,
	258	.minimum_version_id = 1,
5cd8cada	259	.needed = vsx_needed,
3aff6c2f	260	.fields = (VMStateField[]) {
a90db158 AK	261	VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
	262	VMSTATE_END_OF_LIST()
	263	},
	264	};
	265
80b3f79b AK	266	#ifdef TARGET_PPC64
	267	/* Transactional memory state */
	268	static bool tm_needed(void *opaque)
	269	{
	270	PowerPCCPU *cpu = opaque;
	271	CPUPPCState *env = &cpu->env;
	272	return msr_ts;
	273	}
	274
	275	static const VMStateDescription vmstate_tm = {
	276	.name = "cpu/tm",
	277	.version_id = 1,
	278	.minimum_version_id = 1,
	279	.minimum_version_id_old = 1,
5cd8cada	280	.needed = tm_needed,
80b3f79b AK	281	.fields = (VMStateField []) {
	282	VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
	283	VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
	284	VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
	285	VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
	286	VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
	287	VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
	288	VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
	289	VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
	290	VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
	291	VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
	292	VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
	293	VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
	294	VMSTATE_END_OF_LIST()
	295	},
	296	};
	297	#endif
	298
a90db158 AK	299	static bool sr_needed(void *opaque)
	300	{
	301	#ifdef TARGET_PPC64
	302	PowerPCCPU *cpu = opaque;
	303
	304	return !(cpu->env.mmu_model & POWERPC_MMU_64);
	305	#else
	306	return true;
	307	#endif
	308	}
	309
	310	static const VMStateDescription vmstate_sr = {
	311	.name = "cpu/sr",
	312	.version_id = 1,
	313	.minimum_version_id = 1,
5cd8cada	314	.needed = sr_needed,
3aff6c2f	315	.fields = (VMStateField[]) {
a90db158 AK	316	VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
	317	VMSTATE_END_OF_LIST()
	318	},
	319	};
	320
	321	#ifdef TARGET_PPC64
	322	static int get_slbe(QEMUFile f, void pv, size_t size)
	323	{
	324	ppc_slb_t *v = pv;
	325
	326	v->esid = qemu_get_be64(f);
	327	v->vsid = qemu_get_be64(f);
	328
	329	return 0;
	330	}
	331
	332	static void put_slbe(QEMUFile f, void pv, size_t size)
	333	{
	334	ppc_slb_t *v = pv;
	335
	336	qemu_put_be64(f, v->esid);
	337	qemu_put_be64(f, v->vsid);
	338	}
	339
cfd54a04	340	static const VMStateInfo vmstate_info_slbe = {
a90db158 AK	341	.name = "slbe",
	342	.get = get_slbe,
	343	.put = put_slbe,
	344	};
	345
	346	#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
	347	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
	348
	349	#define VMSTATE_SLB_ARRAY(_f, _s, _n) \
	350	VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
	351
	352	static bool slb_needed(void *opaque)
	353	{
	354	PowerPCCPU *cpu = opaque;
	355
	356	/* We don't support any of the old segment table based 64-bit CPUs */
	357	return (cpu->env.mmu_model & POWERPC_MMU_64);
	358	}
	359
cd6a9bb6 DG	360	static int slb_post_load(void *opaque, int version_id)
	361	{
	362	PowerPCCPU *cpu = opaque;
	363	CPUPPCState *env = &cpu->env;
	364	int i;
	365
	366	/* We've pulled in the raw esid and vsid values from the migration
	367	* stream, but we need to recompute the page size pointers */
	368	for (i = 0; i < env->slb_nr; i++) {
	369	if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
	370	/* Migration source had bad values in its SLB */
	371	return -1;
	372	}
	373	}
	374
	375	return 0;
	376	}
	377
a90db158 AK	378	static const VMStateDescription vmstate_slb = {
	379	.name = "cpu/slb",
	380	.version_id = 1,
	381	.minimum_version_id = 1,
5cd8cada	382	.needed = slb_needed,
cd6a9bb6	383	.post_load = slb_post_load,
3aff6c2f	384	.fields = (VMStateField[]) {
a90db158	385	VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
d83af167	386	VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
a90db158 AK	387	VMSTATE_END_OF_LIST()
	388	}
	389	};
	390	#endif /* TARGET_PPC64 */
	391
	392	static const VMStateDescription vmstate_tlb6xx_entry = {
	393	.name = "cpu/tlb6xx_entry",
	394	.version_id = 1,
	395	.minimum_version_id = 1,
3aff6c2f	396	.fields = (VMStateField[]) {
a90db158 AK	397	VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
	398	VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
	399	VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
	400	VMSTATE_END_OF_LIST()
	401	},
	402	};
	403
	404	static bool tlb6xx_needed(void *opaque)
	405	{
	406	PowerPCCPU *cpu = opaque;
	407	CPUPPCState *env = &cpu->env;
	408
	409	return env->nb_tlb && (env->tlb_type == TLB_6XX);
	410	}
	411
	412	static const VMStateDescription vmstate_tlb6xx = {
	413	.name = "cpu/tlb6xx",
	414	.version_id = 1,
	415	.minimum_version_id = 1,
5cd8cada	416	.needed = tlb6xx_needed,
3aff6c2f	417	.fields = (VMStateField[]) {
a90db158 AK	418	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	419	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
	420	env.nb_tlb,
	421	vmstate_tlb6xx_entry,
	422	ppc6xx_tlb_t),
	423	VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
	424	VMSTATE_END_OF_LIST()
	425	}
	426	};
	427
	428	static const VMStateDescription vmstate_tlbemb_entry = {
	429	.name = "cpu/tlbemb_entry",
	430	.version_id = 1,
	431	.minimum_version_id = 1,
3aff6c2f	432	.fields = (VMStateField[]) {
a90db158 AK	433	VMSTATE_UINT64(RPN, ppcemb_tlb_t),
	434	VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
	435	VMSTATE_UINTTL(PID, ppcemb_tlb_t),
	436	VMSTATE_UINTTL(size, ppcemb_tlb_t),
	437	VMSTATE_UINT32(prot, ppcemb_tlb_t),
	438	VMSTATE_UINT32(attr, ppcemb_tlb_t),
	439	VMSTATE_END_OF_LIST()
	440	},
	441	};
	442
	443	static bool tlbemb_needed(void *opaque)
	444	{
	445	PowerPCCPU *cpu = opaque;
	446	CPUPPCState *env = &cpu->env;
	447
	448	return env->nb_tlb && (env->tlb_type == TLB_EMB);
	449	}
	450
	451	static bool pbr403_needed(void *opaque)
	452	{
	453	PowerPCCPU *cpu = opaque;
	454	uint32_t pvr = cpu->env.spr[SPR_PVR];
	455
	456	return (pvr & 0xffff0000) == 0x00200000;
	457	}
	458
	459	static const VMStateDescription vmstate_pbr403 = {
	460	.name = "cpu/pbr403",
	461	.version_id = 1,
	462	.minimum_version_id = 1,
5cd8cada	463	.needed = pbr403_needed,
3aff6c2f	464	.fields = (VMStateField[]) {
a90db158 AK	465	VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
	466	VMSTATE_END_OF_LIST()
	467	},
	468	};
	469
	470	static const VMStateDescription vmstate_tlbemb = {
	471	.name = "cpu/tlb6xx",
	472	.version_id = 1,
	473	.minimum_version_id = 1,
5cd8cada	474	.needed = tlbemb_needed,
3aff6c2f	475	.fields = (VMStateField[]) {
a90db158 AK	476	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	477	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
	478	env.nb_tlb,
	479	vmstate_tlbemb_entry,
	480	ppcemb_tlb_t),
	481	/* 403 protection registers */
	482	VMSTATE_END_OF_LIST()
	483	},
5cd8cada JQ	484	.subsections = (const VMStateDescription*[]) {
	485	&vmstate_pbr403,
	486	NULL
a90db158 AK	487	}
	488	};
	489
	490	static const VMStateDescription vmstate_tlbmas_entry = {
	491	.name = "cpu/tlbmas_entry",
	492	.version_id = 1,
	493	.minimum_version_id = 1,
3aff6c2f	494	.fields = (VMStateField[]) {
a90db158 AK	495	VMSTATE_UINT32(mas8, ppcmas_tlb_t),
	496	VMSTATE_UINT32(mas1, ppcmas_tlb_t),
	497	VMSTATE_UINT64(mas2, ppcmas_tlb_t),
	498	VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
	499	VMSTATE_END_OF_LIST()
	500	},
	501	};
	502
	503	static bool tlbmas_needed(void *opaque)
	504	{
	505	PowerPCCPU *cpu = opaque;
	506	CPUPPCState *env = &cpu->env;
	507
	508	return env->nb_tlb && (env->tlb_type == TLB_MAS);
	509	}
	510
	511	static const VMStateDescription vmstate_tlbmas = {
	512	.name = "cpu/tlbmas",
	513	.version_id = 1,
	514	.minimum_version_id = 1,
5cd8cada	515	.needed = tlbmas_needed,
3aff6c2f	516	.fields = (VMStateField[]) {
a90db158 AK	517	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	518	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
	519	env.nb_tlb,
	520	vmstate_tlbmas_entry,
	521	ppcmas_tlb_t),
	522	VMSTATE_END_OF_LIST()
	523	}
	524	};
	525
	526	const VMStateDescription vmstate_ppc_cpu = {
	527	.name = "cpu",
	528	.version_id = 5,
	529	.minimum_version_id = 5,
	530	.minimum_version_id_old = 4,
	531	.load_state_old = cpu_load_old,
	532	.pre_save = cpu_pre_save,
	533	.post_load = cpu_post_load,
3aff6c2f	534	.fields = (VMStateField[]) {
569be9f0	535	VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
a90db158 AK	536
	537	/* User mode architected state */
	538	VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
	539	#if !defined(TARGET_PPC64)
	540	VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
	541	#endif
	542	VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
	543	VMSTATE_UINTTL(env.nip, PowerPCCPU),
	544
	545	/* SPRs */
	546	VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
	547	VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
	548
	549	/* Reservation */
	550	VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
	551
	552	/* Supervisor mode architected state */
	553	VMSTATE_UINTTL(env.msr, PowerPCCPU),
	554
	555	/* Internal state */
	556	VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
	557	/* FIXME: access_type? */
	558
	559	/* Sanity checking */
	560	VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
	561	VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
	562	VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
	563	VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
	564	VMSTATE_END_OF_LIST()
	565	},
5cd8cada JQ	566	.subsections = (const VMStateDescription*[]) {
	567	&vmstate_fpu,
	568	&vmstate_altivec,
	569	&vmstate_vsx,
	570	&vmstate_sr,
a90db158	571	#ifdef TARGET_PPC64
5cd8cada JQ	572	&vmstate_tm,
5cd8cada JQ	573	&vmstate_slb,
a90db158	574	#endif /* TARGET_PPC64 */
5cd8cada JQ	575	&vmstate_tlb6xx,
	576	&vmstate_tlbemb,
	577	&vmstate_tlbmas,
	578	NULL
a90db158 AK	579	}
a90db158 AK	580	};