[mirror_qemu.git] / target-ppc / machine.c

#include "hw/hw.h"
#include "hw/boards.h"
#include "sysemu/kvm.h"
#include "helper_regs.h"

static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    unsigned int i, j;
    target_ulong sdr1;
    uint32_t fpscr;
    target_ulong xer;

    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gpr[i]);
#if !defined(TARGET_PPC64)
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gprh[i]);
#endif
    qemu_get_betls(f, &env->lr);
    qemu_get_betls(f, &env->ctr);
    for (i = 0; i < 8; i++)
        qemu_get_be32s(f, &env->crf[i]);
    qemu_get_betls(f, &xer);
    cpu_write_xer(env, xer);
    qemu_get_betls(f, &env->reserve_addr);
    qemu_get_betls(f, &env->msr);
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->tgpr[i]);
    for (i = 0; i < 32; i++) {
        union {
            float64 d;
            uint64_t l;
        } u;
        u.l = qemu_get_be64(f);
        env->fpr[i] = u.d;
    }
    qemu_get_be32s(f, &fpscr);
    env->fpscr = fpscr;
    qemu_get_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
    qemu_get_betls(f, &env->spr[SPR_ASR]);
    qemu_get_sbe32s(f, &env->slb_nr);
#endif
    qemu_get_betls(f, &sdr1);
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->sr[i]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->DBAT[i][j]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->IBAT[i][j]);
    qemu_get_sbe32s(f, &env->nb_tlb);
    qemu_get_sbe32s(f, &env->tlb_per_way);
    qemu_get_sbe32s(f, &env->nb_ways);
    qemu_get_sbe32s(f, &env->last_way);
    qemu_get_sbe32s(f, &env->id_tlbs);
    qemu_get_sbe32s(f, &env->nb_pids);
    if (env->tlb.tlb6) {
        // XXX assumes 6xx
        for (i = 0; i < env->nb_tlb; i++) {
            qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
            qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
            qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
        }
    }
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->pb[i]);
    for (i = 0; i < 1024; i++)
        qemu_get_betls(f, &env->spr[i]);
    if (!env->external_htab) {
        ppc_store_sdr1(env, sdr1);
    }
    qemu_get_be32s(f, &env->vscr);
    qemu_get_be64s(f, &env->spe_acc);
    qemu_get_be32s(f, &env->spe_fscr);
    qemu_get_betls(f, &env->msr_mask);
    qemu_get_be32s(f, &env->flags);
    qemu_get_sbe32s(f, &env->error_code);
    qemu_get_be32s(f, &env->pending_interrupts);
    qemu_get_be32s(f, &env->irq_input_state);
    for (i = 0; i < POWERPC_EXCP_NB; i++)
        qemu_get_betls(f, &env->excp_vectors[i]);
    qemu_get_betls(f, &env->excp_prefix);
    qemu_get_betls(f, &env->ivor_mask);
    qemu_get_betls(f, &env->ivpr_mask);
    qemu_get_betls(f, &env->hreset_vector);
    qemu_get_betls(f, &env->nip);
    qemu_get_betls(f, &env->hflags);
    qemu_get_betls(f, &env->hflags_nmsr);
    qemu_get_sbe32s(f, &env->mmu_idx);
    qemu_get_sbe32(f); /* Discard unused power_mode */

    return 0;
}

static int get_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    v->u64[0] = qemu_get_be64(f);
    v->u64[1] = qemu_get_be64(f);

    return 0;
}

static void put_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    qemu_put_be64(f, v->u64[0]);
    qemu_put_be64(f, v->u64[1]);
}

static const VMStateInfo vmstate_info_avr = {
    .name = "avr",
    .get  = get_avr,
    .put  = put_avr,
};

#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)

#define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
    VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)

static void cpu_pre_save(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;

    env->spr[SPR_LR] = env->lr;
    env->spr[SPR_CTR] = env->ctr;
    env->spr[SPR_XER] = env->xer;
#if defined(TARGET_PPC64)
    env->spr[SPR_CFAR] = env->cfar;
#endif
    env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
        env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
        env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
        env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
        env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
        env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
        env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
    }
}

static int cpu_post_load(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;
    target_ulong msr;

    /*
     * We always ignore the source PVR. The user or management
     * software has to take care of running QEMU in a compatible mode.
     */
    env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
    env->lr = env->spr[SPR_LR];
    env->ctr = env->spr[SPR_CTR];
    env->xer = env->spr[SPR_XER];
#if defined(TARGET_PPC64)
    env->cfar = env->spr[SPR_CFAR];
#endif
    env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
        env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
        env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
        env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
        env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
        env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
        env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
    }

    if (!env->external_htab) {
        /* Restore htab_base and htab_mask variables */
        ppc_store_sdr1(env, env->spr[SPR_SDR1]);
    }

    /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
    msr = env->msr;
    env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
    ppc_store_msr(env, msr);

    hreg_compute_mem_idx(env);

    return 0;
}

static bool fpu_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_FLOAT);
}

static const VMStateDescription vmstate_fpu = {
    .name = "cpu/fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = fpu_needed,
    .fields = (VMStateField[]) {
        VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
        VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool altivec_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_ALTIVEC);
}

static const VMStateDescription vmstate_altivec = {
    .name = "cpu/altivec",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = altivec_needed,
    .fields = (VMStateField[]) {
        VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
        VMSTATE_UINT32(env.vscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool vsx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags2 & PPC2_VSX);
}

static const VMStateDescription vmstate_vsx = {
    .name = "cpu/vsx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = vsx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
/* Transactional memory state */
static bool tm_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    return msr_ts;
}

static const VMStateDescription vmstate_tm = {
    .name = "cpu/tm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .needed = tm_needed,
    .fields      = (VMStateField []) {
        VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
        VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
        VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
        VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};
#endif

static bool sr_needed(void *opaque)
{
#ifdef TARGET_PPC64
    PowerPCCPU *cpu = opaque;

    return !(cpu->env.mmu_model & POWERPC_MMU_64);
#else
    return true;
#endif
}

static const VMStateDescription vmstate_sr = {
    .name = "cpu/sr",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = sr_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
static int get_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    v->esid = qemu_get_be64(f);
    v->vsid = qemu_get_be64(f);

    return 0;
}

static void put_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    qemu_put_be64(f, v->esid);
    qemu_put_be64(f, v->vsid);
}

static const VMStateInfo vmstate_info_slbe = {
    .name = "slbe",
    .get  = get_slbe,
    .put  = put_slbe,
};

#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)

#define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
    VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)

static bool slb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    /* We don't support any of the old segment table based 64-bit CPUs */
    return (cpu->env.mmu_model & POWERPC_MMU_64);
}

static const VMStateDescription vmstate_slb = {
    .name = "cpu/slb",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = slb_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
        VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
        VMSTATE_END_OF_LIST()
    }
};
#endif /* TARGET_PPC64 */

static const VMStateDescription vmstate_tlb6xx_entry = {
    .name = "cpu/tlb6xx_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
        VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
        VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlb6xx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_6XX);
}

static const VMStateDescription vmstate_tlb6xx = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlb6xx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlb6xx_entry,
                                            ppc6xx_tlb_t),
        VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_tlbemb_entry = {
    .name = "cpu/tlbemb_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(RPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(PID, ppcemb_tlb_t),
        VMSTATE_UINTTL(size, ppcemb_tlb_t),
        VMSTATE_UINT32(prot, ppcemb_tlb_t),
        VMSTATE_UINT32(attr, ppcemb_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbemb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_EMB);
}

static bool pbr403_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    uint32_t pvr = cpu->env.spr[SPR_PVR];

    return (pvr & 0xffff0000) == 0x00200000;
}

static const VMStateDescription vmstate_pbr403 = {
    .name = "cpu/pbr403",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pbr403_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    },
};

static const VMStateDescription vmstate_tlbemb = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbemb_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbemb_entry,
                                            ppcemb_tlb_t),
        /* 403 protection registers */
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_pbr403,
        NULL
    }
};

static const VMStateDescription vmstate_tlbmas_entry = {
    .name = "cpu/tlbmas_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(mas8, ppcmas_tlb_t),
        VMSTATE_UINT32(mas1, ppcmas_tlb_t),
        VMSTATE_UINT64(mas2, ppcmas_tlb_t),
        VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbmas_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_MAS);
}

static const VMStateDescription vmstate_tlbmas = {
    .name = "cpu/tlbmas",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbmas_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbmas_entry,
                                            ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_ppc_cpu = {
    .name = "cpu",
    .version_id = 5,
    .minimum_version_id = 5,
    .minimum_version_id_old = 4,
    .load_state_old = cpu_load_old,
    .pre_save = cpu_pre_save,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */

        /* User mode architected state */
        VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
#if !defined(TARGET_PPC64)
        VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
#endif
        VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
        VMSTATE_UINTTL(env.nip, PowerPCCPU),

        /* SPRs */
        VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
        VMSTATE_UINT64(env.spe_acc, PowerPCCPU),

        /* Reservation */
        VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),

        /* Supervisor mode architected state */
        VMSTATE_UINTTL(env.msr, PowerPCCPU),

        /* Internal state */
        VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
        /* FIXME: access_type? */

        /* Sanity checking */
        VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
        VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
        VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
        VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_fpu,
        &vmstate_altivec,
        &vmstate_vsx,
        &vmstate_sr,
#ifdef TARGET_PPC64
        &vmstate_tm,
        &vmstate_slb,
#endif /* TARGET_PPC64 */
        &vmstate_tlb6xx,
        &vmstate_tlbemb,
        &vmstate_tlbmas,
        NULL
    }
};
Commit	Line	Data
8dd3dca3 AJ	1	#include "hw/hw.h"
8dd3dca3 AJ	2	#include "hw/boards.h"
9c17d615	3	#include "sysemu/kvm.h"
a90db158	4	#include "helper_regs.h"
8dd3dca3	5
a90db158	6	static int cpu_load_old(QEMUFile f, void opaque, int version_id)
8dd3dca3	7	{
a90db158 AK	8	PowerPCCPU *cpu = opaque;
a90db158 AK	9	CPUPPCState *env = &cpu->env;
a456d59c	10	unsigned int i, j;
bb593904	11	target_ulong sdr1;
30304420	12	uint32_t fpscr;
da91a00f	13	target_ulong xer;
a456d59c BS	14
	15	for (i = 0; i < 32; i++)
	16	qemu_get_betls(f, &env->gpr[i]);
	17	#if !defined(TARGET_PPC64)
	18	for (i = 0; i < 32; i++)
	19	qemu_get_betls(f, &env->gprh[i]);
	20	#endif
	21	qemu_get_betls(f, &env->lr);
	22	qemu_get_betls(f, &env->ctr);
	23	for (i = 0; i < 8; i++)
	24	qemu_get_be32s(f, &env->crf[i]);
da91a00f RH	25	qemu_get_betls(f, &xer);
da91a00f RH	26	cpu_write_xer(env, xer);
18b21a2f	27	qemu_get_betls(f, &env->reserve_addr);
a456d59c BS	28	qemu_get_betls(f, &env->msr);
	29	for (i = 0; i < 4; i++)
	30	qemu_get_betls(f, &env->tgpr[i]);
	31	for (i = 0; i < 32; i++) {
	32	union {
	33	float64 d;
	34	uint64_t l;
	35	} u;
	36	u.l = qemu_get_be64(f);
	37	env->fpr[i] = u.d;
	38	}
30304420 DG	39	qemu_get_be32s(f, &fpscr);
30304420 DG	40	env->fpscr = fpscr;
a456d59c	41	qemu_get_sbe32s(f, &env->access_type);
a456d59c	42	#if defined(TARGET_PPC64)
9baea4a3	43	qemu_get_betls(f, &env->spr[SPR_ASR]);
a456d59c BS	44	qemu_get_sbe32s(f, &env->slb_nr);
a456d59c BS	45	#endif
bb593904	46	qemu_get_betls(f, &sdr1);
a456d59c BS	47	for (i = 0; i < 32; i++)
	48	qemu_get_betls(f, &env->sr[i]);
	49	for (i = 0; i < 2; i++)
	50	for (j = 0; j < 8; j++)
	51	qemu_get_betls(f, &env->DBAT[i][j]);
	52	for (i = 0; i < 2; i++)
	53	for (j = 0; j < 8; j++)
	54	qemu_get_betls(f, &env->IBAT[i][j]);
	55	qemu_get_sbe32s(f, &env->nb_tlb);
	56	qemu_get_sbe32s(f, &env->tlb_per_way);
	57	qemu_get_sbe32s(f, &env->nb_ways);
	58	qemu_get_sbe32s(f, &env->last_way);
	59	qemu_get_sbe32s(f, &env->id_tlbs);
	60	qemu_get_sbe32s(f, &env->nb_pids);
1c53accc	61	if (env->tlb.tlb6) {
a456d59c BS	62	// XXX assumes 6xx
a456d59c BS	63	for (i = 0; i < env->nb_tlb; i++) {
1c53accc AG	64	qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
	65	qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
	66	qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
a456d59c BS	67	}
	68	}
	69	for (i = 0; i < 4; i++)
	70	qemu_get_betls(f, &env->pb[i]);
a456d59c BS	71	for (i = 0; i < 1024; i++)
a456d59c BS	72	qemu_get_betls(f, &env->spr[i]);
f3c75d42 AK	73	if (!env->external_htab) {
	74	ppc_store_sdr1(env, sdr1);
	75	}
a456d59c BS	76	qemu_get_be32s(f, &env->vscr);
	77	qemu_get_be64s(f, &env->spe_acc);
	78	qemu_get_be32s(f, &env->spe_fscr);
	79	qemu_get_betls(f, &env->msr_mask);
	80	qemu_get_be32s(f, &env->flags);
	81	qemu_get_sbe32s(f, &env->error_code);
	82	qemu_get_be32s(f, &env->pending_interrupts);
a456d59c BS	83	qemu_get_be32s(f, &env->irq_input_state);
	84	for (i = 0; i < POWERPC_EXCP_NB; i++)
	85	qemu_get_betls(f, &env->excp_vectors[i]);
	86	qemu_get_betls(f, &env->excp_prefix);
	87	qemu_get_betls(f, &env->ivor_mask);
	88	qemu_get_betls(f, &env->ivpr_mask);
	89	qemu_get_betls(f, &env->hreset_vector);
a456d59c BS	90	qemu_get_betls(f, &env->nip);
	91	qemu_get_betls(f, &env->hflags);
	92	qemu_get_betls(f, &env->hflags_nmsr);
	93	qemu_get_sbe32s(f, &env->mmu_idx);
011aba24	94	qemu_get_sbe32(f); /* Discard unused power_mode */
a456d59c	95
8dd3dca3 AJ	96	return 0;
8dd3dca3 AJ	97	}
a90db158 AK	98
	99	static int get_avr(QEMUFile f, void pv, size_t size)
	100	{
	101	ppc_avr_t *v = pv;
	102
	103	v->u64[0] = qemu_get_be64(f);
	104	v->u64[1] = qemu_get_be64(f);
	105
	106	return 0;
	107	}
	108
	109	static void put_avr(QEMUFile f, void pv, size_t size)
	110	{
	111	ppc_avr_t *v = pv;
	112
	113	qemu_put_be64(f, v->u64[0]);
	114	qemu_put_be64(f, v->u64[1]);
	115	}
	116
cfd54a04	117	static const VMStateInfo vmstate_info_avr = {
a90db158 AK	118	.name = "avr",
	119	.get = get_avr,
	120	.put = put_avr,
	121	};
	122
	123	#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
	124	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
	125
	126	#define VMSTATE_AVR_ARRAY(_f, _s, _n) \
	127	VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
	128
	129	static void cpu_pre_save(void *opaque)
	130	{
	131	PowerPCCPU *cpu = opaque;
	132	CPUPPCState *env = &cpu->env;
	133	int i;
	134
	135	env->spr[SPR_LR] = env->lr;
	136	env->spr[SPR_CTR] = env->ctr;
	137	env->spr[SPR_XER] = env->xer;
	138	#if defined(TARGET_PPC64)
	139	env->spr[SPR_CFAR] = env->cfar;
	140	#endif
	141	env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
	142
	143	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	144	env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
	145	env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
	146	env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
	147	env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
	148	}
	149	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	150	env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
	151	env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
	152	env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
	153	env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
	154	}
	155	}
	156
	157	static int cpu_post_load(void *opaque, int version_id)
	158	{
	159	PowerPCCPU *cpu = opaque;
	160	CPUPPCState *env = &cpu->env;
	161	int i;
2360b6e8	162	target_ulong msr;
a90db158	163
569be9f0 AK	164	/*
	165	* We always ignore the source PVR. The user or management
	166	* software has to take care of running QEMU in a compatible mode.
	167	*/
	168	env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
a90db158 AK	169	env->lr = env->spr[SPR_LR];
	170	env->ctr = env->spr[SPR_CTR];
	171	env->xer = env->spr[SPR_XER];
	172	#if defined(TARGET_PPC64)
	173	env->cfar = env->spr[SPR_CFAR];
	174	#endif
	175	env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
	176
	177	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	178	env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
	179	env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
	180	env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
	181	env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
	182	}
	183	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	184	env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
	185	env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
	186	env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
	187	env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
	188	}
	189
f3c75d42 AK	190	if (!env->external_htab) {
	191	/* Restore htab_base and htab_mask variables */
	192	ppc_store_sdr1(env, env->spr[SPR_SDR1]);
	193	}
2360b6e8	194
993ebe4a	195	/* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
2360b6e8	196	msr = env->msr;
993ebe4a	197	env->msr ^= ~((1ULL << MSR_TGPR) \| MSR_HVB);
2360b6e8 MCA	198	ppc_store_msr(env, msr);
2360b6e8 MCA	199
a90db158 AK	200	hreg_compute_mem_idx(env);
	201
	202	return 0;
	203	}
	204
	205	static bool fpu_needed(void *opaque)
	206	{
	207	PowerPCCPU *cpu = opaque;
	208
	209	return (cpu->env.insns_flags & PPC_FLOAT);
	210	}
	211
	212	static const VMStateDescription vmstate_fpu = {
	213	.name = "cpu/fpu",
	214	.version_id = 1,
	215	.minimum_version_id = 1,
5cd8cada	216	.needed = fpu_needed,
3aff6c2f	217	.fields = (VMStateField[]) {
a90db158 AK	218	VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
	219	VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
	220	VMSTATE_END_OF_LIST()
	221	},
	222	};
	223
	224	static bool altivec_needed(void *opaque)
	225	{
	226	PowerPCCPU *cpu = opaque;
	227
	228	return (cpu->env.insns_flags & PPC_ALTIVEC);
	229	}
	230
	231	static const VMStateDescription vmstate_altivec = {
	232	.name = "cpu/altivec",
	233	.version_id = 1,
	234	.minimum_version_id = 1,
5cd8cada	235	.needed = altivec_needed,
3aff6c2f	236	.fields = (VMStateField[]) {
a90db158 AK	237	VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
	238	VMSTATE_UINT32(env.vscr, PowerPCCPU),
	239	VMSTATE_END_OF_LIST()
	240	},
	241	};
	242
	243	static bool vsx_needed(void *opaque)
	244	{
	245	PowerPCCPU *cpu = opaque;
	246
	247	return (cpu->env.insns_flags2 & PPC2_VSX);
	248	}
	249
	250	static const VMStateDescription vmstate_vsx = {
	251	.name = "cpu/vsx",
	252	.version_id = 1,
	253	.minimum_version_id = 1,
5cd8cada	254	.needed = vsx_needed,
3aff6c2f	255	.fields = (VMStateField[]) {
a90db158 AK	256	VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
	257	VMSTATE_END_OF_LIST()
	258	},
	259	};
	260
80b3f79b AK	261	#ifdef TARGET_PPC64
	262	/* Transactional memory state */
	263	static bool tm_needed(void *opaque)
	264	{
	265	PowerPCCPU *cpu = opaque;
	266	CPUPPCState *env = &cpu->env;
	267	return msr_ts;
	268	}
	269
	270	static const VMStateDescription vmstate_tm = {
	271	.name = "cpu/tm",
	272	.version_id = 1,
	273	.minimum_version_id = 1,
	274	.minimum_version_id_old = 1,
5cd8cada	275	.needed = tm_needed,
80b3f79b AK	276	.fields = (VMStateField []) {
	277	VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
	278	VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
	279	VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
	280	VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
	281	VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
	282	VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
	283	VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
	284	VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
	285	VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
	286	VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
	287	VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
	288	VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
	289	VMSTATE_END_OF_LIST()
	290	},
	291	};
	292	#endif
	293
a90db158 AK	294	static bool sr_needed(void *opaque)
	295	{
	296	#ifdef TARGET_PPC64
	297	PowerPCCPU *cpu = opaque;
	298
	299	return !(cpu->env.mmu_model & POWERPC_MMU_64);
	300	#else
	301	return true;
	302	#endif
	303	}
	304
	305	static const VMStateDescription vmstate_sr = {
	306	.name = "cpu/sr",
	307	.version_id = 1,
	308	.minimum_version_id = 1,
5cd8cada	309	.needed = sr_needed,
3aff6c2f	310	.fields = (VMStateField[]) {
a90db158 AK	311	VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
	312	VMSTATE_END_OF_LIST()
	313	},
	314	};
	315
	316	#ifdef TARGET_PPC64
	317	static int get_slbe(QEMUFile f, void pv, size_t size)
	318	{
	319	ppc_slb_t *v = pv;
	320
	321	v->esid = qemu_get_be64(f);
	322	v->vsid = qemu_get_be64(f);
	323
	324	return 0;
	325	}
	326
	327	static void put_slbe(QEMUFile f, void pv, size_t size)
	328	{
	329	ppc_slb_t *v = pv;
	330
	331	qemu_put_be64(f, v->esid);
	332	qemu_put_be64(f, v->vsid);
	333	}
	334
cfd54a04	335	static const VMStateInfo vmstate_info_slbe = {
a90db158 AK	336	.name = "slbe",
	337	.get = get_slbe,
	338	.put = put_slbe,
	339	};
	340
	341	#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
	342	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
	343
	344	#define VMSTATE_SLB_ARRAY(_f, _s, _n) \
	345	VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
	346
	347	static bool slb_needed(void *opaque)
	348	{
	349	PowerPCCPU *cpu = opaque;
	350
	351	/* We don't support any of the old segment table based 64-bit CPUs */
	352	return (cpu->env.mmu_model & POWERPC_MMU_64);
	353	}
	354
	355	static const VMStateDescription vmstate_slb = {
	356	.name = "cpu/slb",
	357	.version_id = 1,
	358	.minimum_version_id = 1,
5cd8cada	359	.needed = slb_needed,
3aff6c2f	360	.fields = (VMStateField[]) {
a90db158	361	VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
d83af167	362	VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
a90db158 AK	363	VMSTATE_END_OF_LIST()
	364	}
	365	};
	366	#endif /* TARGET_PPC64 */
	367
	368	static const VMStateDescription vmstate_tlb6xx_entry = {
	369	.name = "cpu/tlb6xx_entry",
	370	.version_id = 1,
	371	.minimum_version_id = 1,
3aff6c2f	372	.fields = (VMStateField[]) {
a90db158 AK	373	VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
	374	VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
	375	VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
	376	VMSTATE_END_OF_LIST()
	377	},
	378	};
	379
	380	static bool tlb6xx_needed(void *opaque)
	381	{
	382	PowerPCCPU *cpu = opaque;
	383	CPUPPCState *env = &cpu->env;
	384
	385	return env->nb_tlb && (env->tlb_type == TLB_6XX);
	386	}
	387
	388	static const VMStateDescription vmstate_tlb6xx = {
	389	.name = "cpu/tlb6xx",
	390	.version_id = 1,
	391	.minimum_version_id = 1,
5cd8cada	392	.needed = tlb6xx_needed,
3aff6c2f	393	.fields = (VMStateField[]) {
a90db158 AK	394	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	395	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
	396	env.nb_tlb,
	397	vmstate_tlb6xx_entry,
	398	ppc6xx_tlb_t),
	399	VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
	400	VMSTATE_END_OF_LIST()
	401	}
	402	};
	403
	404	static const VMStateDescription vmstate_tlbemb_entry = {
	405	.name = "cpu/tlbemb_entry",
	406	.version_id = 1,
	407	.minimum_version_id = 1,
3aff6c2f	408	.fields = (VMStateField[]) {
a90db158 AK	409	VMSTATE_UINT64(RPN, ppcemb_tlb_t),
	410	VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
	411	VMSTATE_UINTTL(PID, ppcemb_tlb_t),
	412	VMSTATE_UINTTL(size, ppcemb_tlb_t),
	413	VMSTATE_UINT32(prot, ppcemb_tlb_t),
	414	VMSTATE_UINT32(attr, ppcemb_tlb_t),
	415	VMSTATE_END_OF_LIST()
	416	},
	417	};
	418
	419	static bool tlbemb_needed(void *opaque)
	420	{
	421	PowerPCCPU *cpu = opaque;
	422	CPUPPCState *env = &cpu->env;
	423
	424	return env->nb_tlb && (env->tlb_type == TLB_EMB);
	425	}
	426
	427	static bool pbr403_needed(void *opaque)
	428	{
	429	PowerPCCPU *cpu = opaque;
	430	uint32_t pvr = cpu->env.spr[SPR_PVR];
	431
	432	return (pvr & 0xffff0000) == 0x00200000;
	433	}
	434
	435	static const VMStateDescription vmstate_pbr403 = {
	436	.name = "cpu/pbr403",
	437	.version_id = 1,
	438	.minimum_version_id = 1,
5cd8cada	439	.needed = pbr403_needed,
3aff6c2f	440	.fields = (VMStateField[]) {
a90db158 AK	441	VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
	442	VMSTATE_END_OF_LIST()
	443	},
	444	};
	445
	446	static const VMStateDescription vmstate_tlbemb = {
	447	.name = "cpu/tlb6xx",
	448	.version_id = 1,
	449	.minimum_version_id = 1,
5cd8cada	450	.needed = tlbemb_needed,
3aff6c2f	451	.fields = (VMStateField[]) {
a90db158 AK	452	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	453	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
	454	env.nb_tlb,
	455	vmstate_tlbemb_entry,
	456	ppcemb_tlb_t),
	457	/* 403 protection registers */
	458	VMSTATE_END_OF_LIST()
	459	},
5cd8cada JQ	460	.subsections = (const VMStateDescription*[]) {
	461	&vmstate_pbr403,
	462	NULL
a90db158 AK	463	}
	464	};
	465
	466	static const VMStateDescription vmstate_tlbmas_entry = {
	467	.name = "cpu/tlbmas_entry",
	468	.version_id = 1,
	469	.minimum_version_id = 1,
3aff6c2f	470	.fields = (VMStateField[]) {
a90db158 AK	471	VMSTATE_UINT32(mas8, ppcmas_tlb_t),
	472	VMSTATE_UINT32(mas1, ppcmas_tlb_t),
	473	VMSTATE_UINT64(mas2, ppcmas_tlb_t),
	474	VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
	475	VMSTATE_END_OF_LIST()
	476	},
	477	};
	478
	479	static bool tlbmas_needed(void *opaque)
	480	{
	481	PowerPCCPU *cpu = opaque;
	482	CPUPPCState *env = &cpu->env;
	483
	484	return env->nb_tlb && (env->tlb_type == TLB_MAS);
	485	}
	486
	487	static const VMStateDescription vmstate_tlbmas = {
	488	.name = "cpu/tlbmas",
	489	.version_id = 1,
	490	.minimum_version_id = 1,
5cd8cada	491	.needed = tlbmas_needed,
3aff6c2f	492	.fields = (VMStateField[]) {
a90db158 AK	493	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	494	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
	495	env.nb_tlb,
	496	vmstate_tlbmas_entry,
	497	ppcmas_tlb_t),
	498	VMSTATE_END_OF_LIST()
	499	}
	500	};
	501
	502	const VMStateDescription vmstate_ppc_cpu = {
	503	.name = "cpu",
	504	.version_id = 5,
	505	.minimum_version_id = 5,
	506	.minimum_version_id_old = 4,
	507	.load_state_old = cpu_load_old,
	508	.pre_save = cpu_pre_save,
	509	.post_load = cpu_post_load,
3aff6c2f	510	.fields = (VMStateField[]) {
569be9f0	511	VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
a90db158 AK	512
	513	/* User mode architected state */
	514	VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
	515	#if !defined(TARGET_PPC64)
	516	VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
	517	#endif
	518	VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
	519	VMSTATE_UINTTL(env.nip, PowerPCCPU),
	520
	521	/* SPRs */
	522	VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
	523	VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
	524
	525	/* Reservation */
	526	VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
	527
	528	/* Supervisor mode architected state */
	529	VMSTATE_UINTTL(env.msr, PowerPCCPU),
	530
	531	/* Internal state */
	532	VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
	533	/* FIXME: access_type? */
	534
	535	/* Sanity checking */
	536	VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
	537	VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
	538	VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
	539	VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
	540	VMSTATE_END_OF_LIST()
	541	},
5cd8cada JQ	542	.subsections = (const VMStateDescription*[]) {
	543	&vmstate_fpu,
	544	&vmstate_altivec,
	545	&vmstate_vsx,
	546	&vmstate_sr,
a90db158	547	#ifdef TARGET_PPC64
5cd8cada JQ	548	&vmstate_tm,
5cd8cada JQ	549	&vmstate_slb,
a90db158	550	#endif /* TARGET_PPC64 */
5cd8cada JQ	551	&vmstate_tlb6xx,
	552	&vmstate_tlbemb,
	553	&vmstate_tlbmas,
	554	NULL
a90db158 AK	555	}
a90db158 AK	556	};