[mirror_qemu.git] / target-ppc / machine.c

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "sysemu/kvm.h"
#include "helper_regs.h"
#include "mmu-hash64.h"

static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    unsigned int i, j;
    target_ulong sdr1;
    uint32_t fpscr;
    target_ulong xer;

    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gpr[i]);
#if !defined(TARGET_PPC64)
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->gprh[i]);
#endif
    qemu_get_betls(f, &env->lr);
    qemu_get_betls(f, &env->ctr);
    for (i = 0; i < 8; i++)
        qemu_get_be32s(f, &env->crf[i]);
    qemu_get_betls(f, &xer);
    cpu_write_xer(env, xer);
    qemu_get_betls(f, &env->reserve_addr);
    qemu_get_betls(f, &env->msr);
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->tgpr[i]);
    for (i = 0; i < 32; i++) {
        union {
            float64 d;
            uint64_t l;
        } u;
        u.l = qemu_get_be64(f);
        env->fpr[i] = u.d;
    }
    qemu_get_be32s(f, &fpscr);
    env->fpscr = fpscr;
    qemu_get_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
    qemu_get_betls(f, &env->spr[SPR_ASR]);
    qemu_get_sbe32s(f, &env->slb_nr);
#endif
    qemu_get_betls(f, &sdr1);
    for (i = 0; i < 32; i++)
        qemu_get_betls(f, &env->sr[i]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->DBAT[i][j]);
    for (i = 0; i < 2; i++)
        for (j = 0; j < 8; j++)
            qemu_get_betls(f, &env->IBAT[i][j]);
    qemu_get_sbe32s(f, &env->nb_tlb);
    qemu_get_sbe32s(f, &env->tlb_per_way);
    qemu_get_sbe32s(f, &env->nb_ways);
    qemu_get_sbe32s(f, &env->last_way);
    qemu_get_sbe32s(f, &env->id_tlbs);
    qemu_get_sbe32s(f, &env->nb_pids);
    if (env->tlb.tlb6) {
        // XXX assumes 6xx
        for (i = 0; i < env->nb_tlb; i++) {
            qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
            qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
            qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
        }
    }
    for (i = 0; i < 4; i++)
        qemu_get_betls(f, &env->pb[i]);
    for (i = 0; i < 1024; i++)
        qemu_get_betls(f, &env->spr[i]);
    if (!env->external_htab) {
        ppc_store_sdr1(env, sdr1);
    }
    qemu_get_be32s(f, &env->vscr);
    qemu_get_be64s(f, &env->spe_acc);
    qemu_get_be32s(f, &env->spe_fscr);
    qemu_get_betls(f, &env->msr_mask);
    qemu_get_be32s(f, &env->flags);
    qemu_get_sbe32s(f, &env->error_code);
    qemu_get_be32s(f, &env->pending_interrupts);
    qemu_get_be32s(f, &env->irq_input_state);
    for (i = 0; i < POWERPC_EXCP_NB; i++)
        qemu_get_betls(f, &env->excp_vectors[i]);
    qemu_get_betls(f, &env->excp_prefix);
    qemu_get_betls(f, &env->ivor_mask);
    qemu_get_betls(f, &env->ivpr_mask);
    qemu_get_betls(f, &env->hreset_vector);
    qemu_get_betls(f, &env->nip);
    qemu_get_betls(f, &env->hflags);
    qemu_get_betls(f, &env->hflags_nmsr);
    qemu_get_sbe32s(f, &env->mmu_idx);
    qemu_get_sbe32(f); /* Discard unused power_mode */

    return 0;
}

static int get_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    v->u64[0] = qemu_get_be64(f);
    v->u64[1] = qemu_get_be64(f);

    return 0;
}

static void put_avr(QEMUFile *f, void *pv, size_t size)
{
    ppc_avr_t *v = pv;

    qemu_put_be64(f, v->u64[0]);
    qemu_put_be64(f, v->u64[1]);
}

static const VMStateInfo vmstate_info_avr = {
    .name = "avr",
    .get  = get_avr,
    .put  = put_avr,
};

#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)

#define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
    VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)

static void cpu_pre_save(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;

    env->spr[SPR_LR] = env->lr;
    env->spr[SPR_CTR] = env->ctr;
    env->spr[SPR_XER] = cpu_read_xer(env);
#if defined(TARGET_PPC64)
    env->spr[SPR_CFAR] = env->cfar;
#endif
    env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
        env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
        env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
        env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
        env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
        env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
        env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
    }
}

static int cpu_post_load(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;
    target_ulong msr;

    /*
     * We always ignore the source PVR. The user or management
     * software has to take care of running QEMU in a compatible mode.
     */
    env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
    env->lr = env->spr[SPR_LR];
    env->ctr = env->spr[SPR_CTR];
    cpu_write_xer(env, env->spr[SPR_XER]);
#if defined(TARGET_PPC64)
    env->cfar = env->spr[SPR_CFAR];
#endif
    env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];

    for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
        env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
        env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
        env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
        env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
    }
    for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
        env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
        env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
        env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
        env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
    }

    if (!env->external_htab) {
        /* Restore htab_base and htab_mask variables */
        ppc_store_sdr1(env, env->spr[SPR_SDR1]);
    }

    /* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
    msr = env->msr;
    env->msr ^= ~((1ULL << MSR_TGPR) | MSR_HVB);
    ppc_store_msr(env, msr);

    hreg_compute_mem_idx(env);

    return 0;
}

static bool fpu_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_FLOAT);
}

static const VMStateDescription vmstate_fpu = {
    .name = "cpu/fpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = fpu_needed,
    .fields = (VMStateField[]) {
        VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
        VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool altivec_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags & PPC_ALTIVEC);
}

static const VMStateDescription vmstate_altivec = {
    .name = "cpu/altivec",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = altivec_needed,
    .fields = (VMStateField[]) {
        VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
        VMSTATE_UINT32(env.vscr, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};

static bool vsx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    return (cpu->env.insns_flags2 & PPC2_VSX);
}

static const VMStateDescription vmstate_vsx = {
    .name = "cpu/vsx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = vsx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
/* Transactional memory state */
static bool tm_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    return msr_ts;
}

static const VMStateDescription vmstate_tm = {
    .name = "cpu/tm",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .needed = tm_needed,
    .fields      = (VMStateField []) {
        VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
        VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
        VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
        VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
        VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
};
#endif

static bool sr_needed(void *opaque)
{
#ifdef TARGET_PPC64
    PowerPCCPU *cpu = opaque;

    return !(cpu->env.mmu_model & POWERPC_MMU_64);
#else
    return true;
#endif
}

static const VMStateDescription vmstate_sr = {
    .name = "cpu/sr",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = sr_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
        VMSTATE_END_OF_LIST()
    },
};

#ifdef TARGET_PPC64
static int get_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    v->esid = qemu_get_be64(f);
    v->vsid = qemu_get_be64(f);

    return 0;
}

static void put_slbe(QEMUFile *f, void *pv, size_t size)
{
    ppc_slb_t *v = pv;

    qemu_put_be64(f, v->esid);
    qemu_put_be64(f, v->vsid);
}

static const VMStateInfo vmstate_info_slbe = {
    .name = "slbe",
    .get  = get_slbe,
    .put  = put_slbe,
};

#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
    VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)

#define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
    VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)

static bool slb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    /* We don't support any of the old segment table based 64-bit CPUs */
    return (cpu->env.mmu_model & POWERPC_MMU_64);
}

static int slb_post_load(void *opaque, int version_id)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    int i;

    /* We've pulled in the raw esid and vsid values from the migration
     * stream, but we need to recompute the page size pointers */
    for (i = 0; i < env->slb_nr; i++) {
        if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
            /* Migration source had bad values in its SLB */
            return -1;
        }
    }

    return 0;
}

static const VMStateDescription vmstate_slb = {
    .name = "cpu/slb",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = slb_needed,
    .post_load = slb_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
        VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
        VMSTATE_END_OF_LIST()
    }
};
#endif /* TARGET_PPC64 */

static const VMStateDescription vmstate_tlb6xx_entry = {
    .name = "cpu/tlb6xx_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
        VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
        VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlb6xx_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_6XX);
}

static const VMStateDescription vmstate_tlb6xx = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlb6xx_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlb6xx_entry,
                                            ppc6xx_tlb_t),
        VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_tlbemb_entry = {
    .name = "cpu/tlbemb_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(RPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
        VMSTATE_UINTTL(PID, ppcemb_tlb_t),
        VMSTATE_UINTTL(size, ppcemb_tlb_t),
        VMSTATE_UINT32(prot, ppcemb_tlb_t),
        VMSTATE_UINT32(attr, ppcemb_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbemb_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_EMB);
}

static bool pbr403_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    uint32_t pvr = cpu->env.spr[SPR_PVR];

    return (pvr & 0xffff0000) == 0x00200000;
}

static const VMStateDescription vmstate_pbr403 = {
    .name = "cpu/pbr403",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = pbr403_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
        VMSTATE_END_OF_LIST()
    },
};

static const VMStateDescription vmstate_tlbemb = {
    .name = "cpu/tlb6xx",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbemb_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbemb_entry,
                                            ppcemb_tlb_t),
        /* 403 protection registers */
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_pbr403,
        NULL
    }
};

static const VMStateDescription vmstate_tlbmas_entry = {
    .name = "cpu/tlbmas_entry",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(mas8, ppcmas_tlb_t),
        VMSTATE_UINT32(mas1, ppcmas_tlb_t),
        VMSTATE_UINT64(mas2, ppcmas_tlb_t),
        VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    },
};

static bool tlbmas_needed(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    return env->nb_tlb && (env->tlb_type == TLB_MAS);
}

static const VMStateDescription vmstate_tlbmas = {
    .name = "cpu/tlbmas",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = tlbmas_needed,
    .fields = (VMStateField[]) {
        VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
        VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
                                            env.nb_tlb,
                                            vmstate_tlbmas_entry,
                                            ppcmas_tlb_t),
        VMSTATE_END_OF_LIST()
    }
};

const VMStateDescription vmstate_ppc_cpu = {
    .name = "cpu",
    .version_id = 5,
    .minimum_version_id = 5,
    .minimum_version_id_old = 4,
    .load_state_old = cpu_load_old,
    .pre_save = cpu_pre_save,
    .post_load = cpu_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */

        /* User mode architected state */
        VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
#if !defined(TARGET_PPC64)
        VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
#endif
        VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
        VMSTATE_UINTTL(env.nip, PowerPCCPU),

        /* SPRs */
        VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
        VMSTATE_UINT64(env.spe_acc, PowerPCCPU),

        /* Reservation */
        VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),

        /* Supervisor mode architected state */
        VMSTATE_UINTTL(env.msr, PowerPCCPU),

        /* Internal state */
        VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
        /* FIXME: access_type? */

        /* Sanity checking */
        VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
        VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
        VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
        VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription*[]) {
        &vmstate_fpu,
        &vmstate_altivec,
        &vmstate_vsx,
        &vmstate_sr,
#ifdef TARGET_PPC64
        &vmstate_tm,
        &vmstate_slb,
#endif /* TARGET_PPC64 */
        &vmstate_tlb6xx,
        &vmstate_tlbemb,
        &vmstate_tlbmas,
        NULL
    }
};
Commit	Line	Data
0d75590d	1	#include "qemu/osdep.h"
8dd3dca3 AJ	2	#include "hw/hw.h"
8dd3dca3 AJ	3	#include "hw/boards.h"
9c17d615	4	#include "sysemu/kvm.h"
a90db158	5	#include "helper_regs.h"
cd6a9bb6	6	#include "mmu-hash64.h"
8dd3dca3	7
a90db158	8	static int cpu_load_old(QEMUFile f, void opaque, int version_id)
8dd3dca3	9	{
a90db158 AK	10	PowerPCCPU *cpu = opaque;
a90db158 AK	11	CPUPPCState *env = &cpu->env;
a456d59c	12	unsigned int i, j;
bb593904	13	target_ulong sdr1;
30304420	14	uint32_t fpscr;
da91a00f	15	target_ulong xer;
a456d59c BS	16
	17	for (i = 0; i < 32; i++)
	18	qemu_get_betls(f, &env->gpr[i]);
	19	#if !defined(TARGET_PPC64)
	20	for (i = 0; i < 32; i++)
	21	qemu_get_betls(f, &env->gprh[i]);
	22	#endif
	23	qemu_get_betls(f, &env->lr);
	24	qemu_get_betls(f, &env->ctr);
	25	for (i = 0; i < 8; i++)
	26	qemu_get_be32s(f, &env->crf[i]);
da91a00f RH	27	qemu_get_betls(f, &xer);
da91a00f RH	28	cpu_write_xer(env, xer);
18b21a2f	29	qemu_get_betls(f, &env->reserve_addr);
a456d59c BS	30	qemu_get_betls(f, &env->msr);
	31	for (i = 0; i < 4; i++)
	32	qemu_get_betls(f, &env->tgpr[i]);
	33	for (i = 0; i < 32; i++) {
	34	union {
	35	float64 d;
	36	uint64_t l;
	37	} u;
	38	u.l = qemu_get_be64(f);
	39	env->fpr[i] = u.d;
	40	}
30304420 DG	41	qemu_get_be32s(f, &fpscr);
30304420 DG	42	env->fpscr = fpscr;
a456d59c	43	qemu_get_sbe32s(f, &env->access_type);
a456d59c	44	#if defined(TARGET_PPC64)
9baea4a3	45	qemu_get_betls(f, &env->spr[SPR_ASR]);
a456d59c BS	46	qemu_get_sbe32s(f, &env->slb_nr);
a456d59c BS	47	#endif
bb593904	48	qemu_get_betls(f, &sdr1);
a456d59c BS	49	for (i = 0; i < 32; i++)
	50	qemu_get_betls(f, &env->sr[i]);
	51	for (i = 0; i < 2; i++)
	52	for (j = 0; j < 8; j++)
	53	qemu_get_betls(f, &env->DBAT[i][j]);
	54	for (i = 0; i < 2; i++)
	55	for (j = 0; j < 8; j++)
	56	qemu_get_betls(f, &env->IBAT[i][j]);
	57	qemu_get_sbe32s(f, &env->nb_tlb);
	58	qemu_get_sbe32s(f, &env->tlb_per_way);
	59	qemu_get_sbe32s(f, &env->nb_ways);
	60	qemu_get_sbe32s(f, &env->last_way);
	61	qemu_get_sbe32s(f, &env->id_tlbs);
	62	qemu_get_sbe32s(f, &env->nb_pids);
1c53accc	63	if (env->tlb.tlb6) {
a456d59c BS	64	// XXX assumes 6xx
a456d59c BS	65	for (i = 0; i < env->nb_tlb; i++) {
1c53accc AG	66	qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
	67	qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
	68	qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
a456d59c BS	69	}
	70	}
	71	for (i = 0; i < 4; i++)
	72	qemu_get_betls(f, &env->pb[i]);
a456d59c BS	73	for (i = 0; i < 1024; i++)
a456d59c BS	74	qemu_get_betls(f, &env->spr[i]);
f3c75d42 AK	75	if (!env->external_htab) {
	76	ppc_store_sdr1(env, sdr1);
	77	}
a456d59c BS	78	qemu_get_be32s(f, &env->vscr);
	79	qemu_get_be64s(f, &env->spe_acc);
	80	qemu_get_be32s(f, &env->spe_fscr);
	81	qemu_get_betls(f, &env->msr_mask);
	82	qemu_get_be32s(f, &env->flags);
	83	qemu_get_sbe32s(f, &env->error_code);
	84	qemu_get_be32s(f, &env->pending_interrupts);
a456d59c BS	85	qemu_get_be32s(f, &env->irq_input_state);
	86	for (i = 0; i < POWERPC_EXCP_NB; i++)
	87	qemu_get_betls(f, &env->excp_vectors[i]);
	88	qemu_get_betls(f, &env->excp_prefix);
	89	qemu_get_betls(f, &env->ivor_mask);
	90	qemu_get_betls(f, &env->ivpr_mask);
	91	qemu_get_betls(f, &env->hreset_vector);
a456d59c BS	92	qemu_get_betls(f, &env->nip);
	93	qemu_get_betls(f, &env->hflags);
	94	qemu_get_betls(f, &env->hflags_nmsr);
	95	qemu_get_sbe32s(f, &env->mmu_idx);
011aba24	96	qemu_get_sbe32(f); /* Discard unused power_mode */
a456d59c	97
8dd3dca3 AJ	98	return 0;
8dd3dca3 AJ	99	}
a90db158 AK	100
	101	static int get_avr(QEMUFile f, void pv, size_t size)
	102	{
	103	ppc_avr_t *v = pv;
	104
	105	v->u64[0] = qemu_get_be64(f);
	106	v->u64[1] = qemu_get_be64(f);
	107
	108	return 0;
	109	}
	110
	111	static void put_avr(QEMUFile f, void pv, size_t size)
	112	{
	113	ppc_avr_t *v = pv;
	114
	115	qemu_put_be64(f, v->u64[0]);
	116	qemu_put_be64(f, v->u64[1]);
	117	}
	118
cfd54a04	119	static const VMStateInfo vmstate_info_avr = {
a90db158 AK	120	.name = "avr",
	121	.get = get_avr,
	122	.put = put_avr,
	123	};
	124
	125	#define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v) \
	126	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
	127
	128	#define VMSTATE_AVR_ARRAY(_f, _s, _n) \
	129	VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
	130
	131	static void cpu_pre_save(void *opaque)
	132	{
	133	PowerPCCPU *cpu = opaque;
	134	CPUPPCState *env = &cpu->env;
	135	int i;
	136
	137	env->spr[SPR_LR] = env->lr;
	138	env->spr[SPR_CTR] = env->ctr;
aa378598	139	env->spr[SPR_XER] = cpu_read_xer(env);
a90db158 AK	140	#if defined(TARGET_PPC64)
	141	env->spr[SPR_CFAR] = env->cfar;
	142	#endif
	143	env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
	144
	145	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	146	env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
	147	env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
	148	env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
	149	env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
	150	}
	151	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	152	env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
	153	env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
	154	env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
	155	env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
	156	}
	157	}
	158
	159	static int cpu_post_load(void *opaque, int version_id)
	160	{
	161	PowerPCCPU *cpu = opaque;
	162	CPUPPCState *env = &cpu->env;
	163	int i;
2360b6e8	164	target_ulong msr;
a90db158	165
569be9f0 AK	166	/*
	167	* We always ignore the source PVR. The user or management
	168	* software has to take care of running QEMU in a compatible mode.
	169	*/
	170	env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
a90db158 AK	171	env->lr = env->spr[SPR_LR];
a90db158 AK	172	env->ctr = env->spr[SPR_CTR];
6a9620e6	173	cpu_write_xer(env, env->spr[SPR_XER]);
a90db158 AK	174	#if defined(TARGET_PPC64)
	175	env->cfar = env->spr[SPR_CFAR];
	176	#endif
	177	env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
	178
	179	for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
	180	env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
	181	env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
	182	env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
	183	env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
	184	}
	185	for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
	186	env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
	187	env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
	188	env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
	189	env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
	190	}
	191
f3c75d42 AK	192	if (!env->external_htab) {
	193	/* Restore htab_base and htab_mask variables */
	194	ppc_store_sdr1(env, env->spr[SPR_SDR1]);
	195	}
2360b6e8	196
993ebe4a	197	/* Invalidate all msr bits except MSR_TGPR/MSR_HVB before restoring */
2360b6e8	198	msr = env->msr;
993ebe4a	199	env->msr ^= ~((1ULL << MSR_TGPR) \| MSR_HVB);
2360b6e8 MCA	200	ppc_store_msr(env, msr);
2360b6e8 MCA	201
a90db158 AK	202	hreg_compute_mem_idx(env);
	203
	204	return 0;
	205	}
	206
	207	static bool fpu_needed(void *opaque)
	208	{
	209	PowerPCCPU *cpu = opaque;
	210
	211	return (cpu->env.insns_flags & PPC_FLOAT);
	212	}
	213
	214	static const VMStateDescription vmstate_fpu = {
	215	.name = "cpu/fpu",
	216	.version_id = 1,
	217	.minimum_version_id = 1,
5cd8cada	218	.needed = fpu_needed,
3aff6c2f	219	.fields = (VMStateField[]) {
a90db158 AK	220	VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
	221	VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
	222	VMSTATE_END_OF_LIST()
	223	},
	224	};
	225
	226	static bool altivec_needed(void *opaque)
	227	{
	228	PowerPCCPU *cpu = opaque;
	229
	230	return (cpu->env.insns_flags & PPC_ALTIVEC);
	231	}
	232
	233	static const VMStateDescription vmstate_altivec = {
	234	.name = "cpu/altivec",
	235	.version_id = 1,
	236	.minimum_version_id = 1,
5cd8cada	237	.needed = altivec_needed,
3aff6c2f	238	.fields = (VMStateField[]) {
a90db158 AK	239	VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
	240	VMSTATE_UINT32(env.vscr, PowerPCCPU),
	241	VMSTATE_END_OF_LIST()
	242	},
	243	};
	244
	245	static bool vsx_needed(void *opaque)
	246	{
	247	PowerPCCPU *cpu = opaque;
	248
	249	return (cpu->env.insns_flags2 & PPC2_VSX);
	250	}
	251
	252	static const VMStateDescription vmstate_vsx = {
	253	.name = "cpu/vsx",
	254	.version_id = 1,
	255	.minimum_version_id = 1,
5cd8cada	256	.needed = vsx_needed,
3aff6c2f	257	.fields = (VMStateField[]) {
a90db158 AK	258	VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
	259	VMSTATE_END_OF_LIST()
	260	},
	261	};
	262
80b3f79b AK	263	#ifdef TARGET_PPC64
	264	/* Transactional memory state */
	265	static bool tm_needed(void *opaque)
	266	{
	267	PowerPCCPU *cpu = opaque;
	268	CPUPPCState *env = &cpu->env;
	269	return msr_ts;
	270	}
	271
	272	static const VMStateDescription vmstate_tm = {
	273	.name = "cpu/tm",
	274	.version_id = 1,
	275	.minimum_version_id = 1,
	276	.minimum_version_id_old = 1,
5cd8cada	277	.needed = tm_needed,
80b3f79b AK	278	.fields = (VMStateField []) {
	279	VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
	280	VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
	281	VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
	282	VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
	283	VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
	284	VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
	285	VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
	286	VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
	287	VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
	288	VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
	289	VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
	290	VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
	291	VMSTATE_END_OF_LIST()
	292	},
	293	};
	294	#endif
	295
a90db158 AK	296	static bool sr_needed(void *opaque)
	297	{
	298	#ifdef TARGET_PPC64
	299	PowerPCCPU *cpu = opaque;
	300
	301	return !(cpu->env.mmu_model & POWERPC_MMU_64);
	302	#else
	303	return true;
	304	#endif
	305	}
	306
	307	static const VMStateDescription vmstate_sr = {
	308	.name = "cpu/sr",
	309	.version_id = 1,
	310	.minimum_version_id = 1,
5cd8cada	311	.needed = sr_needed,
3aff6c2f	312	.fields = (VMStateField[]) {
a90db158 AK	313	VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
	314	VMSTATE_END_OF_LIST()
	315	},
	316	};
	317
	318	#ifdef TARGET_PPC64
	319	static int get_slbe(QEMUFile f, void pv, size_t size)
	320	{
	321	ppc_slb_t *v = pv;
	322
	323	v->esid = qemu_get_be64(f);
	324	v->vsid = qemu_get_be64(f);
	325
	326	return 0;
	327	}
	328
	329	static void put_slbe(QEMUFile f, void pv, size_t size)
	330	{
	331	ppc_slb_t *v = pv;
	332
	333	qemu_put_be64(f, v->esid);
	334	qemu_put_be64(f, v->vsid);
	335	}
	336
cfd54a04	337	static const VMStateInfo vmstate_info_slbe = {
a90db158 AK	338	.name = "slbe",
	339	.get = get_slbe,
	340	.put = put_slbe,
	341	};
	342
	343	#define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v) \
	344	VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
	345
	346	#define VMSTATE_SLB_ARRAY(_f, _s, _n) \
	347	VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
	348
	349	static bool slb_needed(void *opaque)
	350	{
	351	PowerPCCPU *cpu = opaque;
	352
	353	/* We don't support any of the old segment table based 64-bit CPUs */
	354	return (cpu->env.mmu_model & POWERPC_MMU_64);
	355	}
	356
cd6a9bb6 DG	357	static int slb_post_load(void *opaque, int version_id)
	358	{
	359	PowerPCCPU *cpu = opaque;
	360	CPUPPCState *env = &cpu->env;
	361	int i;
	362
	363	/* We've pulled in the raw esid and vsid values from the migration
	364	* stream, but we need to recompute the page size pointers */
	365	for (i = 0; i < env->slb_nr; i++) {
	366	if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
	367	/* Migration source had bad values in its SLB */
	368	return -1;
	369	}
	370	}
	371
	372	return 0;
	373	}
	374
a90db158 AK	375	static const VMStateDescription vmstate_slb = {
	376	.name = "cpu/slb",
	377	.version_id = 1,
	378	.minimum_version_id = 1,
5cd8cada	379	.needed = slb_needed,
cd6a9bb6	380	.post_load = slb_post_load,
3aff6c2f	381	.fields = (VMStateField[]) {
a90db158	382	VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
d83af167	383	VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
a90db158 AK	384	VMSTATE_END_OF_LIST()
	385	}
	386	};
	387	#endif /* TARGET_PPC64 */
	388
	389	static const VMStateDescription vmstate_tlb6xx_entry = {
	390	.name = "cpu/tlb6xx_entry",
	391	.version_id = 1,
	392	.minimum_version_id = 1,
3aff6c2f	393	.fields = (VMStateField[]) {
a90db158 AK	394	VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
	395	VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
	396	VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
	397	VMSTATE_END_OF_LIST()
	398	},
	399	};
	400
	401	static bool tlb6xx_needed(void *opaque)
	402	{
	403	PowerPCCPU *cpu = opaque;
	404	CPUPPCState *env = &cpu->env;
	405
	406	return env->nb_tlb && (env->tlb_type == TLB_6XX);
	407	}
	408
	409	static const VMStateDescription vmstate_tlb6xx = {
	410	.name = "cpu/tlb6xx",
	411	.version_id = 1,
	412	.minimum_version_id = 1,
5cd8cada	413	.needed = tlb6xx_needed,
3aff6c2f	414	.fields = (VMStateField[]) {
a90db158 AK	415	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	416	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
	417	env.nb_tlb,
	418	vmstate_tlb6xx_entry,
	419	ppc6xx_tlb_t),
	420	VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
	421	VMSTATE_END_OF_LIST()
	422	}
	423	};
	424
	425	static const VMStateDescription vmstate_tlbemb_entry = {
	426	.name = "cpu/tlbemb_entry",
	427	.version_id = 1,
	428	.minimum_version_id = 1,
3aff6c2f	429	.fields = (VMStateField[]) {
a90db158 AK	430	VMSTATE_UINT64(RPN, ppcemb_tlb_t),
	431	VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
	432	VMSTATE_UINTTL(PID, ppcemb_tlb_t),
	433	VMSTATE_UINTTL(size, ppcemb_tlb_t),
	434	VMSTATE_UINT32(prot, ppcemb_tlb_t),
	435	VMSTATE_UINT32(attr, ppcemb_tlb_t),
	436	VMSTATE_END_OF_LIST()
	437	},
	438	};
	439
	440	static bool tlbemb_needed(void *opaque)
	441	{
	442	PowerPCCPU *cpu = opaque;
	443	CPUPPCState *env = &cpu->env;
	444
	445	return env->nb_tlb && (env->tlb_type == TLB_EMB);
	446	}
	447
	448	static bool pbr403_needed(void *opaque)
	449	{
	450	PowerPCCPU *cpu = opaque;
	451	uint32_t pvr = cpu->env.spr[SPR_PVR];
	452
	453	return (pvr & 0xffff0000) == 0x00200000;
	454	}
	455
	456	static const VMStateDescription vmstate_pbr403 = {
	457	.name = "cpu/pbr403",
	458	.version_id = 1,
	459	.minimum_version_id = 1,
5cd8cada	460	.needed = pbr403_needed,
3aff6c2f	461	.fields = (VMStateField[]) {
a90db158 AK	462	VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
	463	VMSTATE_END_OF_LIST()
	464	},
	465	};
	466
	467	static const VMStateDescription vmstate_tlbemb = {
	468	.name = "cpu/tlb6xx",
	469	.version_id = 1,
	470	.minimum_version_id = 1,
5cd8cada	471	.needed = tlbemb_needed,
3aff6c2f	472	.fields = (VMStateField[]) {
a90db158 AK	473	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	474	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
	475	env.nb_tlb,
	476	vmstate_tlbemb_entry,
	477	ppcemb_tlb_t),
	478	/* 403 protection registers */
	479	VMSTATE_END_OF_LIST()
	480	},
5cd8cada JQ	481	.subsections = (const VMStateDescription*[]) {
	482	&vmstate_pbr403,
	483	NULL
a90db158 AK	484	}
	485	};
	486
	487	static const VMStateDescription vmstate_tlbmas_entry = {
	488	.name = "cpu/tlbmas_entry",
	489	.version_id = 1,
	490	.minimum_version_id = 1,
3aff6c2f	491	.fields = (VMStateField[]) {
a90db158 AK	492	VMSTATE_UINT32(mas8, ppcmas_tlb_t),
	493	VMSTATE_UINT32(mas1, ppcmas_tlb_t),
	494	VMSTATE_UINT64(mas2, ppcmas_tlb_t),
	495	VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
	496	VMSTATE_END_OF_LIST()
	497	},
	498	};
	499
	500	static bool tlbmas_needed(void *opaque)
	501	{
	502	PowerPCCPU *cpu = opaque;
	503	CPUPPCState *env = &cpu->env;
	504
	505	return env->nb_tlb && (env->tlb_type == TLB_MAS);
	506	}
	507
	508	static const VMStateDescription vmstate_tlbmas = {
	509	.name = "cpu/tlbmas",
	510	.version_id = 1,
	511	.minimum_version_id = 1,
5cd8cada	512	.needed = tlbmas_needed,
3aff6c2f	513	.fields = (VMStateField[]) {
a90db158 AK	514	VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
	515	VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
	516	env.nb_tlb,
	517	vmstate_tlbmas_entry,
	518	ppcmas_tlb_t),
	519	VMSTATE_END_OF_LIST()
	520	}
	521	};
	522
	523	const VMStateDescription vmstate_ppc_cpu = {
	524	.name = "cpu",
	525	.version_id = 5,
	526	.minimum_version_id = 5,
	527	.minimum_version_id_old = 4,
	528	.load_state_old = cpu_load_old,
	529	.pre_save = cpu_pre_save,
	530	.post_load = cpu_post_load,
3aff6c2f	531	.fields = (VMStateField[]) {
569be9f0	532	VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
a90db158 AK	533
	534	/* User mode architected state */
	535	VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
	536	#if !defined(TARGET_PPC64)
	537	VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
	538	#endif
	539	VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
	540	VMSTATE_UINTTL(env.nip, PowerPCCPU),
	541
	542	/* SPRs */
	543	VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
	544	VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
	545
	546	/* Reservation */
	547	VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
	548
	549	/* Supervisor mode architected state */
	550	VMSTATE_UINTTL(env.msr, PowerPCCPU),
	551
	552	/* Internal state */
	553	VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
	554	/* FIXME: access_type? */
	555
	556	/* Sanity checking */
	557	VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
	558	VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
	559	VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
	560	VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
	561	VMSTATE_END_OF_LIST()
	562	},
5cd8cada JQ	563	.subsections = (const VMStateDescription*[]) {
	564	&vmstate_fpu,
	565	&vmstate_altivec,
	566	&vmstate_vsx,
	567	&vmstate_sr,
a90db158	568	#ifdef TARGET_PPC64
5cd8cada JQ	569	&vmstate_tm,
5cd8cada JQ	570	&vmstate_slb,
a90db158	571	#endif /* TARGET_PPC64 */
5cd8cada JQ	572	&vmstate_tlb6xx,
	573	&vmstate_tlbemb,
	574	&vmstate_tlbmas,
	575	NULL
a90db158 AK	576	}
a90db158 AK	577	};