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Commit | Line | Data |
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9a64fbe4 | 1 | /* |
2f5a189c | 2 | * PowerPC memory access emulation helpers for QEMU. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
9a64fbe4 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
9a64fbe4 | 18 | */ |
0d75590d | 19 | #include "qemu/osdep.h" |
3e457172 | 20 | #include "cpu.h" |
63c91552 | 21 | #include "exec/exec-all.h" |
1de7afc9 | 22 | #include "qemu/host-utils.h" |
2ef6175a | 23 | #include "exec/helper-proto.h" |
9a64fbe4 | 24 | |
0411a972 | 25 | #include "helper_regs.h" |
63c91552 | 26 | #include "exec/exec-all.h" |
f08b6170 | 27 | #include "exec/cpu_ldst.h" |
3e457172 | 28 | |
fdabc366 | 29 | //#define DEBUG_OP |
d12d51d5 | 30 | |
e22c357b DK |
31 | static inline bool needs_byteswap(const CPUPPCState *env) |
32 | { | |
33 | #if defined(TARGET_WORDS_BIGENDIAN) | |
34 | return msr_le; | |
35 | #else | |
36 | return !msr_le; | |
37 | #endif | |
38 | } | |
39 | ||
ff4a62cd AJ |
40 | /*****************************************************************************/ |
41 | /* Memory load and stores */ | |
42 | ||
2f5a189c BS |
43 | static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr, |
44 | target_long arg) | |
ff4a62cd AJ |
45 | { |
46 | #if defined(TARGET_PPC64) | |
e42a61f1 | 47 | if (!msr_is_64bit(env, env->msr)) { |
b327c654 BS |
48 | return (uint32_t)(addr + arg); |
49 | } else | |
ff4a62cd | 50 | #endif |
b327c654 BS |
51 | { |
52 | return addr + arg; | |
53 | } | |
ff4a62cd AJ |
54 | } |
55 | ||
2f5a189c | 56 | void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg) |
ff4a62cd | 57 | { |
76db3ba4 | 58 | for (; reg < 32; reg++) { |
e22c357b | 59 | if (needs_byteswap(env)) { |
2f5a189c | 60 | env->gpr[reg] = bswap32(cpu_ldl_data(env, addr)); |
b327c654 | 61 | } else { |
2f5a189c | 62 | env->gpr[reg] = cpu_ldl_data(env, addr); |
b327c654 | 63 | } |
2f5a189c | 64 | addr = addr_add(env, addr, 4); |
ff4a62cd AJ |
65 | } |
66 | } | |
67 | ||
2f5a189c | 68 | void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg) |
ff4a62cd | 69 | { |
76db3ba4 | 70 | for (; reg < 32; reg++) { |
e22c357b | 71 | if (needs_byteswap(env)) { |
2f5a189c | 72 | cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg])); |
b327c654 | 73 | } else { |
2f5a189c | 74 | cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]); |
b327c654 | 75 | } |
2f5a189c | 76 | addr = addr_add(env, addr, 4); |
ff4a62cd AJ |
77 | } |
78 | } | |
79 | ||
2f5a189c | 80 | void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg) |
dfbc799d AJ |
81 | { |
82 | int sh; | |
b327c654 | 83 | |
76db3ba4 | 84 | for (; nb > 3; nb -= 4) { |
2f5a189c | 85 | env->gpr[reg] = cpu_ldl_data(env, addr); |
dfbc799d | 86 | reg = (reg + 1) % 32; |
2f5a189c | 87 | addr = addr_add(env, addr, 4); |
dfbc799d AJ |
88 | } |
89 | if (unlikely(nb > 0)) { | |
90 | env->gpr[reg] = 0; | |
76db3ba4 | 91 | for (sh = 24; nb > 0; nb--, sh -= 8) { |
2f5a189c BS |
92 | env->gpr[reg] |= cpu_ldub_data(env, addr) << sh; |
93 | addr = addr_add(env, addr, 1); | |
dfbc799d AJ |
94 | } |
95 | } | |
96 | } | |
97 | /* PPC32 specification says we must generate an exception if | |
98 | * rA is in the range of registers to be loaded. | |
99 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
100 | * For now, I'll follow the spec... | |
101 | */ | |
2f5a189c BS |
102 | void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg, |
103 | uint32_t ra, uint32_t rb) | |
dfbc799d AJ |
104 | { |
105 | if (likely(xer_bc != 0)) { | |
488661ee | 106 | int num_used_regs = (xer_bc + 3) / 4; |
537d3e8e TH |
107 | if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) || |
108 | lsw_reg_in_range(reg, num_used_regs, rb))) { | |
109 | env->nip += 4; /* Compensate the "nip - 4" from gen_lswx() */ | |
e5f17ac6 | 110 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
e06fcd75 AJ |
111 | POWERPC_EXCP_INVAL | |
112 | POWERPC_EXCP_INVAL_LSWX); | |
dfbc799d | 113 | } else { |
2f5a189c | 114 | helper_lsw(env, addr, xer_bc, reg); |
dfbc799d AJ |
115 | } |
116 | } | |
117 | } | |
118 | ||
2f5a189c BS |
119 | void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb, |
120 | uint32_t reg) | |
dfbc799d AJ |
121 | { |
122 | int sh; | |
b327c654 | 123 | |
76db3ba4 | 124 | for (; nb > 3; nb -= 4) { |
2f5a189c | 125 | cpu_stl_data(env, addr, env->gpr[reg]); |
dfbc799d | 126 | reg = (reg + 1) % 32; |
2f5a189c | 127 | addr = addr_add(env, addr, 4); |
dfbc799d AJ |
128 | } |
129 | if (unlikely(nb > 0)) { | |
a16b45e7 | 130 | for (sh = 24; nb > 0; nb--, sh -= 8) { |
2f5a189c BS |
131 | cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF); |
132 | addr = addr_add(env, addr, 1); | |
a16b45e7 | 133 | } |
dfbc799d AJ |
134 | } |
135 | } | |
136 | ||
2f5a189c | 137 | static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size) |
799a8c8d | 138 | { |
799a8c8d | 139 | int i; |
b327c654 BS |
140 | |
141 | addr &= ~(dcache_line_size - 1); | |
142 | for (i = 0; i < dcache_line_size; i += 4) { | |
2f5a189c | 143 | cpu_stl_data(env, addr + i, 0); |
799a8c8d | 144 | } |
b327c654 | 145 | if (env->reserve_addr == addr) { |
18b21a2f | 146 | env->reserve_addr = (target_ulong)-1ULL; |
b327c654 | 147 | } |
799a8c8d AJ |
148 | } |
149 | ||
8e33944f | 150 | void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl) |
799a8c8d | 151 | { |
8e33944f | 152 | int dcbz_size = env->dcache_line_size; |
799a8c8d | 153 | |
414f5d14 | 154 | #if defined(TARGET_PPC64) |
8e33944f AG |
155 | if (!is_dcbzl && |
156 | (env->excp_model == POWERPC_EXCP_970) && | |
157 | ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { | |
158 | dcbz_size = 32; | |
b327c654 | 159 | } |
8e33944f AG |
160 | #endif |
161 | ||
162 | /* XXX add e500mc support */ | |
163 | ||
164 | do_dcbz(env, addr, dcbz_size); | |
799a8c8d AJ |
165 | } |
166 | ||
2f5a189c | 167 | void helper_icbi(CPUPPCState *env, target_ulong addr) |
37d269df | 168 | { |
76db3ba4 | 169 | addr &= ~(env->dcache_line_size - 1); |
37d269df AJ |
170 | /* Invalidate one cache line : |
171 | * PowerPC specification says this is to be treated like a load | |
172 | * (not a fetch) by the MMU. To be sure it will be so, | |
173 | * do the load "by hand". | |
174 | */ | |
2f5a189c | 175 | cpu_ldl_data(env, addr); |
37d269df AJ |
176 | } |
177 | ||
b327c654 | 178 | /* XXX: to be tested */ |
2f5a189c BS |
179 | target_ulong helper_lscbx(CPUPPCState *env, target_ulong addr, uint32_t reg, |
180 | uint32_t ra, uint32_t rb) | |
bdb4b689 AJ |
181 | { |
182 | int i, c, d; | |
b327c654 | 183 | |
bdb4b689 AJ |
184 | d = 24; |
185 | for (i = 0; i < xer_bc; i++) { | |
2f5a189c BS |
186 | c = cpu_ldub_data(env, addr); |
187 | addr = addr_add(env, addr, 1); | |
bdb4b689 AJ |
188 | /* ra (if not 0) and rb are never modified */ |
189 | if (likely(reg != rb && (ra == 0 || reg != ra))) { | |
190 | env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d); | |
191 | } | |
b327c654 | 192 | if (unlikely(c == xer_cmp)) { |
bdb4b689 | 193 | break; |
b327c654 | 194 | } |
bdb4b689 AJ |
195 | if (likely(d != 0)) { |
196 | d -= 8; | |
197 | } else { | |
198 | d = 24; | |
199 | reg++; | |
200 | reg = reg & 0x1F; | |
201 | } | |
202 | } | |
203 | return i; | |
204 | } | |
205 | ||
d6a46fe8 AJ |
206 | /*****************************************************************************/ |
207 | /* Altivec extension helpers */ | |
e2542fe2 | 208 | #if defined(HOST_WORDS_BIGENDIAN) |
d6a46fe8 AJ |
209 | #define HI_IDX 0 |
210 | #define LO_IDX 1 | |
211 | #else | |
212 | #define HI_IDX 1 | |
213 | #define LO_IDX 0 | |
214 | #endif | |
215 | ||
e22c357b DK |
216 | /* We use msr_le to determine index ordering in a vector. However, |
217 | byteswapping is not simply controlled by msr_le. We also need to take | |
218 | into account endianness of the target. This is done for the little-endian | |
219 | PPC64 user-mode target. */ | |
220 | ||
cbfb6ae9 | 221 | #define LVE(name, access, swap, element) \ |
2f5a189c BS |
222 | void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ |
223 | target_ulong addr) \ | |
cbfb6ae9 AJ |
224 | { \ |
225 | size_t n_elems = ARRAY_SIZE(r->element); \ | |
b327c654 | 226 | int adjust = HI_IDX*(n_elems - 1); \ |
cbfb6ae9 AJ |
227 | int sh = sizeof(r->element[0]) >> 1; \ |
228 | int index = (addr & 0xf) >> sh; \ | |
b327c654 | 229 | if (msr_le) { \ |
bbfb6f13 | 230 | index = n_elems - index - 1; \ |
e22c357b DK |
231 | } \ |
232 | \ | |
233 | if (needs_byteswap(env)) { \ | |
b327c654 | 234 | r->element[LO_IDX ? index : (adjust - index)] = \ |
bcd510b1 | 235 | swap(access(env, addr, GETPC())); \ |
b327c654 BS |
236 | } else { \ |
237 | r->element[LO_IDX ? index : (adjust - index)] = \ | |
bcd510b1 | 238 | access(env, addr, GETPC()); \ |
b327c654 | 239 | } \ |
cbfb6ae9 AJ |
240 | } |
241 | #define I(x) (x) | |
bcd510b1 BH |
242 | LVE(lvebx, cpu_ldub_data_ra, I, u8) |
243 | LVE(lvehx, cpu_lduw_data_ra, bswap16, u16) | |
244 | LVE(lvewx, cpu_ldl_data_ra, bswap32, u32) | |
cbfb6ae9 AJ |
245 | #undef I |
246 | #undef LVE | |
247 | ||
b327c654 | 248 | #define STVE(name, access, swap, element) \ |
2f5a189c BS |
249 | void helper_##name(CPUPPCState *env, ppc_avr_t *r, \ |
250 | target_ulong addr) \ | |
b327c654 BS |
251 | { \ |
252 | size_t n_elems = ARRAY_SIZE(r->element); \ | |
253 | int adjust = HI_IDX * (n_elems - 1); \ | |
254 | int sh = sizeof(r->element[0]) >> 1; \ | |
255 | int index = (addr & 0xf) >> sh; \ | |
b327c654 | 256 | if (msr_le) { \ |
bbfb6f13 | 257 | index = n_elems - index - 1; \ |
e22c357b DK |
258 | } \ |
259 | \ | |
260 | if (needs_byteswap(env)) { \ | |
2f5a189c | 261 | access(env, addr, swap(r->element[LO_IDX ? index : \ |
bcd510b1 BH |
262 | (adjust - index)]), \ |
263 | GETPC()); \ | |
cbfb6ae9 | 264 | } else { \ |
2f5a189c | 265 | access(env, addr, r->element[LO_IDX ? index : \ |
bcd510b1 | 266 | (adjust - index)], GETPC()); \ |
cbfb6ae9 AJ |
267 | } \ |
268 | } | |
269 | #define I(x) (x) | |
bcd510b1 BH |
270 | STVE(stvebx, cpu_stb_data_ra, I, u8) |
271 | STVE(stvehx, cpu_stw_data_ra, bswap16, u16) | |
272 | STVE(stvewx, cpu_stl_data_ra, bswap32, u32) | |
cbfb6ae9 AJ |
273 | #undef I |
274 | #undef LVE | |
275 | ||
d6a46fe8 AJ |
276 | #undef HI_IDX |
277 | #undef LO_IDX | |
0ff93d11 TM |
278 | |
279 | void helper_tbegin(CPUPPCState *env) | |
280 | { | |
281 | /* As a degenerate implementation, always fail tbegin. The reason | |
282 | * given is "Nesting overflow". The "persistent" bit is set, | |
283 | * providing a hint to the error handler to not retry. The TFIAR | |
284 | * captures the address of the failure, which is this tbegin | |
285 | * instruction. Instruction execution will continue with the | |
286 | * next instruction in memory, which is precisely what we want. | |
287 | */ | |
288 | ||
289 | env->spr[SPR_TEXASR] = | |
290 | (1ULL << TEXASR_FAILURE_PERSISTENT) | | |
291 | (1ULL << TEXASR_NESTING_OVERFLOW) | | |
292 | (msr_hv << TEXASR_PRIVILEGE_HV) | | |
293 | (msr_pr << TEXASR_PRIVILEGE_PR) | | |
294 | (1ULL << TEXASR_FAILURE_SUMMARY) | | |
295 | (1ULL << TEXASR_TFIAR_EXACT); | |
296 | env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr; | |
297 | env->spr[SPR_TFHAR] = env->nip + 4; | |
298 | env->crf[0] = 0xB; /* 0b1010 = transaction failure */ | |
299 | } |