[mirror_qemu.git] / target-ppc / mmu-hash32.c

/*
 *  PowerPC MMU, TLB and BAT emulation helpers for QEMU.
 *
 *  Copyright (c) 2003-2007 Jocelyn Mayer
 *  Copyright (c) 2013 David Gibson, IBM Corporation
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "exec/helper-proto.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
#include "mmu-hash32.h"

//#define DEBUG_MMU
//#define DEBUG_BAT

#ifdef DEBUG_MMU
#  define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
#else
#  define LOG_MMU_STATE(cpu) do { } while (0)
#endif

#ifdef DEBUG_BATS
#  define LOG_BATS(...) qemu_log(__VA_ARGS__)
#else
#  define LOG_BATS(...) do { } while (0)
#endif

struct mmu_ctx_hash32 {
    hwaddr raddr;      /* Real address              */
    int prot;                      /* Protection bits           */
    int key;                       /* Access key                */
};

static int ppc_hash32_pp_prot(int key, int pp, int nx)
{
    int prot;

    if (key == 0) {
        switch (pp) {
        case 0x0:
        case 0x1:
        case 0x2:
            prot = PAGE_READ | PAGE_WRITE;
            break;

        case 0x3:
            prot = PAGE_READ;
            break;

        default:
            abort();
        }
    } else {
        switch (pp) {
        case 0x0:
            prot = 0;
            break;

        case 0x1:
        case 0x3:
            prot = PAGE_READ;
            break;

        case 0x2:
            prot = PAGE_READ | PAGE_WRITE;
            break;

        default:
            abort();
        }
    }
    if (nx == 0) {
        prot |= PAGE_EXEC;
    }

    return prot;
}

static int ppc_hash32_pte_prot(CPUPPCState *env,
                               target_ulong sr, ppc_hash_pte32_t pte)
{
    unsigned pp, key;

    key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
    pp = pte.pte1 & HPTE32_R_PP;

    return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
}

static target_ulong hash32_bat_size(CPUPPCState *env,
                                    target_ulong batu, target_ulong batl)
{
    if ((msr_pr && !(batu & BATU32_VP))
        || (!msr_pr && !(batu & BATU32_VS))) {
        return 0;
    }

    return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
}

static int hash32_bat_prot(CPUPPCState *env,
                           target_ulong batu, target_ulong batl)
{
    int pp, prot;

    prot = 0;
    pp = batl & BATL32_PP;
    if (pp != 0) {
        prot = PAGE_READ | PAGE_EXEC;
        if (pp == 0x2) {
            prot |= PAGE_WRITE;
        }
    }
    return prot;
}

static target_ulong hash32_bat_601_size(CPUPPCState *env,
                                target_ulong batu, target_ulong batl)
{
    if (!(batl & BATL32_601_V)) {
        return 0;
    }

    return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
}

static int hash32_bat_601_prot(CPUPPCState *env,
                               target_ulong batu, target_ulong batl)
{
    int key, pp;

    pp = batu & BATU32_601_PP;
    if (msr_pr == 0) {
        key = !!(batu & BATU32_601_KS);
    } else {
        key = !!(batu & BATU32_601_KP);
    }
    return ppc_hash32_pp_prot(key, pp, 0);
}

static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
                                    int *prot)
{
    target_ulong *BATlt, *BATut;
    int i;

    LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
             rwx == 2 ? 'I' : 'D', ea);
    if (rwx == 2) {
        BATlt = env->IBAT[1];
        BATut = env->IBAT[0];
    } else {
        BATlt = env->DBAT[1];
        BATut = env->DBAT[0];
    }
    for (i = 0; i < env->nb_BATs; i++) {
        target_ulong batu = BATut[i];
        target_ulong batl = BATlt[i];
        target_ulong mask;

        if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
            mask = hash32_bat_601_size(env, batu, batl);
        } else {
            mask = hash32_bat_size(env, batu, batl);
        }
        LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
                 " BATl " TARGET_FMT_lx "\n", __func__,
                 type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl);

        if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
            hwaddr raddr = (batl & mask) | (ea & ~mask);

            if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
                *prot = hash32_bat_601_prot(env, batu, batl);
            } else {
                *prot = hash32_bat_prot(env, batu, batl);
            }

            return raddr & TARGET_PAGE_MASK;
        }
    }

    /* No hit */
#if defined(DEBUG_BATS)
    if (qemu_log_enabled()) {
        LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
        for (i = 0; i < 4; i++) {
            BATu = &BATut[i];
            BATl = &BATlt[i];
            BEPIu = *BATu & BATU32_BEPIU;
            BEPIl = *BATu & BATU32_BEPIL;
            bl = (*BATu & 0x00001FFC) << 15;
            LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
                     " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
                     TARGET_FMT_lx " " TARGET_FMT_lx "\n",
                     __func__, type == ACCESS_CODE ? 'I' : 'D', i, ea,
                     *BATu, *BATl, BEPIu, BEPIl, bl);
        }
    }
#endif

    return -1;
}

static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
                                   target_ulong eaddr, int rwx,
                                   hwaddr *raddr, int *prot)
{
    CPUState *cs = CPU(ppc_env_get_cpu(env));
    int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));

    qemu_log_mask(CPU_LOG_MMU, "direct store...\n");

    if ((sr & 0x1FF00000) >> 20 == 0x07f) {
        /* Memory-forced I/O controller interface access */
        /* If T=1 and BUID=x'07F', the 601 performs a memory access
         * to SR[28-31] LA[4-31], bypassing all protection mechanisms.
         */
        *raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
        *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
        return 0;
    }

    if (rwx == 2) {
        /* No code fetch is allowed in direct-store areas */
        cs->exception_index = POWERPC_EXCP_ISI;
        env->error_code = 0x10000000;
        return 1;
    }

    switch (env->access_type) {
    case ACCESS_INT:
        /* Integer load/store : only access allowed */
        break;
    case ACCESS_FLOAT:
        /* Floating point load/store */
        cs->exception_index = POWERPC_EXCP_ALIGN;
        env->error_code = POWERPC_EXCP_ALIGN_FP;
        env->spr[SPR_DAR] = eaddr;
        return 1;
    case ACCESS_RES:
        /* lwarx, ldarx or srwcx. */
        env->error_code = 0;
        env->spr[SPR_DAR] = eaddr;
        if (rwx == 1) {
            env->spr[SPR_DSISR] = 0x06000000;
        } else {
            env->spr[SPR_DSISR] = 0x04000000;
        }
        return 1;
    case ACCESS_CACHE:
        /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
        /* Should make the instruction do no-op.
         * As it already do no-op, it's quite easy :-)
         */
        *raddr = eaddr;
        return 0;
    case ACCESS_EXT:
        /* eciwx or ecowx */
        cs->exception_index = POWERPC_EXCP_DSI;
        env->error_code = 0;
        env->spr[SPR_DAR] = eaddr;
        if (rwx == 1) {
            env->spr[SPR_DSISR] = 0x06100000;
        } else {
            env->spr[SPR_DSISR] = 0x04100000;
        }
        return 1;
    default:
        qemu_log("ERROR: instruction should not need "
                 "address translation\n");
        abort();
    }
    if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
        *raddr = eaddr;
        return 0;
    } else {
        cs->exception_index = POWERPC_EXCP_DSI;
        env->error_code = 0;
        env->spr[SPR_DAR] = eaddr;
        if (rwx == 1) {
            env->spr[SPR_DSISR] = 0x0a000000;
        } else {
            env->spr[SPR_DSISR] = 0x08000000;
        }
        return 1;
    }
}

hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
{
    return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
}

static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
                                     bool secondary, target_ulong ptem,
                                     ppc_hash_pte32_t *pte)
{
    hwaddr pte_offset = pteg_off;
    target_ulong pte0, pte1;
    int i;

    for (i = 0; i < HPTES_PER_GROUP; i++) {
        pte0 = ppc_hash32_load_hpte0(env, pte_offset);
        pte1 = ppc_hash32_load_hpte1(env, pte_offset);

        if ((pte0 & HPTE32_V_VALID)
            && (secondary == !!(pte0 & HPTE32_V_SECONDARY))
            && HPTE32_V_COMPARE(pte0, ptem)) {
            pte->pte0 = pte0;
            pte->pte1 = pte1;
            return pte_offset;
        }

        pte_offset += HASH_PTE_SIZE_32;
    }

    return -1;
}

static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
                                     target_ulong sr, target_ulong eaddr,
                                     ppc_hash_pte32_t *pte)
{
    hwaddr pteg_off, pte_offset;
    hwaddr hash;
    uint32_t vsid, pgidx, ptem;

    vsid = sr & SR32_VSID;
    pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
    hash = vsid ^ pgidx;
    ptem = (vsid << 7) | (pgidx >> 10);

    /* Page address translation */
    qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
            " htab_mask " TARGET_FMT_plx
            " hash " TARGET_FMT_plx "\n",
            env->htab_base, env->htab_mask, hash);

    /* Primary PTEG lookup */
    qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
            " vsid=%" PRIx32 " ptem=%" PRIx32
            " hash=" TARGET_FMT_plx "\n",
            env->htab_base, env->htab_mask, vsid, ptem, hash);
    pteg_off = get_pteg_offset32(env, hash);
    pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
    if (pte_offset == -1) {
        /* Secondary PTEG lookup */
        qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
                " vsid=%" PRIx32 " api=%" PRIx32
                " hash=" TARGET_FMT_plx "\n", env->htab_base,
                env->htab_mask, vsid, ptem, ~hash);
        pteg_off = get_pteg_offset32(env, ~hash);
        pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
    }

    return pte_offset;
}

static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
                                   target_ulong eaddr)
{
    hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
    hwaddr mask = ~TARGET_PAGE_MASK;

    return (rpn & ~mask) | (eaddr & mask);
}

int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
                                int mmu_idx)
{
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;
    target_ulong sr;
    hwaddr pte_offset;
    ppc_hash_pte32_t pte;
    int prot;
    uint32_t new_pte1;
    const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
    hwaddr raddr;

    assert((rwx == 0) || (rwx == 1) || (rwx == 2));

    /* 1. Handle real mode accesses */
    if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
        /* Translation is off */
        raddr = eaddr;
        tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
                     PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
                     TARGET_PAGE_SIZE);
        return 0;
    }

    /* 2. Check Block Address Translation entries (BATs) */
    if (env->nb_BATs != 0) {
        raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
        if (raddr != -1) {
            if (need_prot[rwx] & ~prot) {
                if (rwx == 2) {
                    cs->exception_index = POWERPC_EXCP_ISI;
                    env->error_code = 0x08000000;
                } else {
                    cs->exception_index = POWERPC_EXCP_DSI;
                    env->error_code = 0;
                    env->spr[SPR_DAR] = eaddr;
                    if (rwx == 1) {
                        env->spr[SPR_DSISR] = 0x0a000000;
                    } else {
                        env->spr[SPR_DSISR] = 0x08000000;
                    }
                }
                return 1;
            }

            tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
                         raddr & TARGET_PAGE_MASK, prot, mmu_idx,
                         TARGET_PAGE_SIZE);
            return 0;
        }
    }

    /* 3. Look up the Segment Register */
    sr = env->sr[eaddr >> 28];

    /* 4. Handle direct store segments */
    if (sr & SR32_T) {
        if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
                                    &raddr, &prot) == 0) {
            tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
                         raddr & TARGET_PAGE_MASK, prot, mmu_idx,
                         TARGET_PAGE_SIZE);
            return 0;
        } else {
            return 1;
        }
    }

    /* 5. Check for segment level no-execute violation */
    if ((rwx == 2) && (sr & SR32_NX)) {
        cs->exception_index = POWERPC_EXCP_ISI;
        env->error_code = 0x10000000;
        return 1;
    }

    /* 6. Locate the PTE in the hash table */
    pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
    if (pte_offset == -1) {
        if (rwx == 2) {
            cs->exception_index = POWERPC_EXCP_ISI;
            env->error_code = 0x40000000;
        } else {
            cs->exception_index = POWERPC_EXCP_DSI;
            env->error_code = 0;
            env->spr[SPR_DAR] = eaddr;
            if (rwx == 1) {
                env->spr[SPR_DSISR] = 0x42000000;
            } else {
                env->spr[SPR_DSISR] = 0x40000000;
            }
        }

        return 1;
    }
    qemu_log_mask(CPU_LOG_MMU,
                "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);

    /* 7. Check access permissions */

    prot = ppc_hash32_pte_prot(env, sr, pte);

    if (need_prot[rwx] & ~prot) {
        /* Access right violation */
        qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
        if (rwx == 2) {
            cs->exception_index = POWERPC_EXCP_ISI;
            env->error_code = 0x08000000;
        } else {
            cs->exception_index = POWERPC_EXCP_DSI;
            env->error_code = 0;
            env->spr[SPR_DAR] = eaddr;
            if (rwx == 1) {
                env->spr[SPR_DSISR] = 0x0a000000;
            } else {
                env->spr[SPR_DSISR] = 0x08000000;
            }
        }
        return 1;
    }

    qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");

    /* 8. Update PTE referenced and changed bits if necessary */

    new_pte1 = pte.pte1 | HPTE32_R_R; /* set referenced bit */
    if (rwx == 1) {
        new_pte1 |= HPTE32_R_C; /* set changed (dirty) bit */
    } else {
        /* Treat the page as read-only for now, so that a later write
         * will pass through this function again to set the C bit */
        prot &= ~PAGE_WRITE;
    }

    if (new_pte1 != pte.pte1) {
        ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
    }

    /* 9. Determine the real address from the PTE */

    raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);

    tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
                 prot, mmu_idx, TARGET_PAGE_SIZE);

    return 0;
}

hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
{
    target_ulong sr;
    hwaddr pte_offset;
    ppc_hash_pte32_t pte;
    int prot;

    if (msr_dr == 0) {
        /* Translation is off */
        return eaddr;
    }

    if (env->nb_BATs != 0) {
        hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
        if (raddr != -1) {
            return raddr;
        }
    }

    sr = env->sr[eaddr >> 28];

    if (sr & SR32_T) {
        /* FIXME: Add suitable debug support for Direct Store segments */
        return -1;
    }

    pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
    if (pte_offset == -1) {
        return -1;
    }

    return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
}
Commit	Line	Data
9d7c3f4a DG	1	/*
	2	* PowerPC MMU, TLB and BAT emulation helpers for QEMU.
	3	*
	4	* Copyright (c) 2003-2007 Jocelyn Mayer
	5	* Copyright (c) 2013 David Gibson, IBM Corporation
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include "cpu.h"
2ef6175a	22	#include "exec/helper-proto.h"
9d7c3f4a DG	23	#include "sysemu/kvm.h"
	24	#include "kvm_ppc.h"
	25	#include "mmu-hash32.h"
	26
	27	//#define DEBUG_MMU
98132796	28	//#define DEBUG_BAT
9d7c3f4a DG	29
9d7c3f4a DG	30	#ifdef DEBUG_MMU
77710e7a	31	# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
9d7c3f4a	32	#else
77710e7a	33	# define LOG_MMU_STATE(cpu) do { } while (0)
9d7c3f4a DG	34	#endif
9d7c3f4a DG	35
98132796 DG	36	#ifdef DEBUG_BATS
	37	# define LOG_BATS(...) qemu_log(__VA_ARGS__)
	38	#else
	39	# define LOG_BATS(...) do { } while (0)
	40	#endif
	41
5dc68eb0 DG	42	struct mmu_ctx_hash32 {
5dc68eb0 DG	43	hwaddr raddr; /* Real address */
5dc68eb0	44	int prot; /* Protection bits */
5dc68eb0	45	int key; /* Access key */
5dc68eb0 DG	46	};
5dc68eb0 DG	47
e01b4445	48	static int ppc_hash32_pp_prot(int key, int pp, int nx)
496272a7	49	{
e01b4445	50	int prot;
496272a7	51
496272a7 DG	52	if (key == 0) {
	53	switch (pp) {
	54	case 0x0:
	55	case 0x1:
	56	case 0x2:
e01b4445 DG	57	prot = PAGE_READ \| PAGE_WRITE;
	58	break;
	59
496272a7	60	case 0x3:
e01b4445	61	prot = PAGE_READ;
496272a7	62	break;
e01b4445 DG	63
	64	default:
	65	abort();
496272a7 DG	66	}
	67	} else {
	68	switch (pp) {
	69	case 0x0:
e01b4445	70	prot = 0;
496272a7	71	break;
e01b4445	72
496272a7 DG	73	case 0x1:
496272a7 DG	74	case 0x3:
e01b4445	75	prot = PAGE_READ;
496272a7	76	break;
e01b4445	77
496272a7	78	case 0x2:
e01b4445	79	prot = PAGE_READ \| PAGE_WRITE;
496272a7	80	break;
e01b4445 DG	81
	82	default:
	83	abort();
496272a7 DG	84	}
	85	}
	86	if (nx == 0) {
e01b4445	87	prot \|= PAGE_EXEC;
496272a7 DG	88	}
496272a7 DG	89
e01b4445	90	return prot;
496272a7 DG	91	}
496272a7 DG	92
e01b4445 DG	93	static int ppc_hash32_pte_prot(CPUPPCState *env,
e01b4445 DG	94	target_ulong sr, ppc_hash_pte32_t pte)
496272a7	95	{
e01b4445	96	unsigned pp, key;
496272a7	97
e01b4445 DG	98	key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
e01b4445 DG	99	pp = pte.pte1 & HPTE32_R_PP;
496272a7	100
e01b4445	101	return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
496272a7 DG	102	}
496272a7 DG	103
6fc76aa9 DG	104	static target_ulong hash32_bat_size(CPUPPCState *env,
6fc76aa9 DG	105	target_ulong batu, target_ulong batl)
98132796	106	{
6fc76aa9 DG	107	if ((msr_pr && !(batu & BATU32_VP))
	108	\|\| (!msr_pr && !(batu & BATU32_VS))) {
	109	return 0;
98132796	110	}
6fc76aa9 DG	111
6fc76aa9 DG	112	return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
98132796 DG	113	}
98132796 DG	114
e1d49515 DG	115	static int hash32_bat_prot(CPUPPCState *env,
	116	target_ulong batu, target_ulong batl)
	117	{
	118	int pp, prot;
	119
	120	prot = 0;
	121	pp = batl & BATL32_PP;
	122	if (pp != 0) {
	123	prot = PAGE_READ \| PAGE_EXEC;
	124	if (pp == 0x2) {
	125	prot \|= PAGE_WRITE;
	126	}
	127	}
	128	return prot;
	129	}
	130
6fc76aa9	131	static target_ulong hash32_bat_601_size(CPUPPCState *env,
e1d49515	132	target_ulong batu, target_ulong batl)
98132796	133	{
6fc76aa9 DG	134	if (!(batl & BATL32_601_V)) {
	135	return 0;
	136	}
	137
	138	return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
e1d49515 DG	139	}
	140
	141	static int hash32_bat_601_prot(CPUPPCState *env,
	142	target_ulong batu, target_ulong batl)
	143	{
	144	int key, pp;
	145
	146	pp = batu & BATU32_601_PP;
	147	if (msr_pr == 0) {
	148	key = !!(batu & BATU32_601_KS);
	149	} else {
	150	key = !!(batu & BATU32_601_KP);
	151	}
e01b4445	152	return ppc_hash32_pp_prot(key, pp, 0);
98132796 DG	153	}
98132796 DG	154
145e52f3 DG	155	static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
145e52f3 DG	156	int *prot)
98132796	157	{
9986ed1e	158	target_ulong BATlt, BATut;
145e52f3	159	int i;
98132796 DG	160
98132796 DG	161	LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
145e52f3	162	rwx == 2 ? 'I' : 'D', ea);
91cda45b	163	if (rwx == 2) {
98132796 DG	164	BATlt = env->IBAT[1];
98132796 DG	165	BATut = env->IBAT[0];
91cda45b	166	} else {
98132796 DG	167	BATlt = env->DBAT[1];
98132796 DG	168	BATut = env->DBAT[0];
98132796 DG	169	}
98132796 DG	170	for (i = 0; i < env->nb_BATs; i++) {
9986ed1e DG	171	target_ulong batu = BATut[i];
9986ed1e DG	172	target_ulong batl = BATlt[i];
6fc76aa9	173	target_ulong mask;
9986ed1e	174
98132796	175	if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
6fc76aa9	176	mask = hash32_bat_601_size(env, batu, batl);
98132796	177	} else {
6fc76aa9	178	mask = hash32_bat_size(env, batu, batl);
98132796 DG	179	}
	180	LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
	181	" BATl " TARGET_FMT_lx "\n", __func__,
145e52f3 DG	182	type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl);
	183
	184	if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
	185	hwaddr raddr = (batl & mask) \| (ea & ~mask);
	186
	187	if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
	188	*prot = hash32_bat_601_prot(env, batu, batl);
	189	} else {
	190	*prot = hash32_bat_prot(env, batu, batl);
98132796	191	}
145e52f3 DG	192
145e52f3 DG	193	return raddr & TARGET_PAGE_MASK;
98132796 DG	194	}
98132796 DG	195	}
145e52f3 DG	196
145e52f3 DG	197	/* No hit */
98132796	198	#if defined(DEBUG_BATS)
145e52f3 DG	199	if (qemu_log_enabled()) {
	200	LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
	201	for (i = 0; i < 4; i++) {
	202	BATu = &BATut[i];
	203	BATl = &BATlt[i];
	204	BEPIu = *BATu & BATU32_BEPIU;
	205	BEPIl = *BATu & BATU32_BEPIL;
	206	bl = (*BATu & 0x00001FFC) << 15;
	207	LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
	208	" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
	209	TARGET_FMT_lx " " TARGET_FMT_lx "\n",
	210	__func__, type == ACCESS_CODE ? 'I' : 'D', i, ea,
	211	BATu, BATl, BEPIu, BEPIl, bl);
98132796	212	}
98132796	213	}
145e52f3 DG	214	#endif
	215
	216	return -1;
98132796 DG	217	}
98132796 DG	218
723ed73a DG	219	static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
	220	target_ulong eaddr, int rwx,
	221	hwaddr raddr, int prot)
	222	{
27103424	223	CPUState *cs = CPU(ppc_env_get_cpu(env));
723ed73a DG	224	int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
723ed73a DG	225
339aaf5b	226	qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
723ed73a DG	227
	228	if ((sr & 0x1FF00000) >> 20 == 0x07f) {
	229	/* Memory-forced I/O controller interface access */
	230	/* If T=1 and BUID=x'07F', the 601 performs a memory access
	231	* to SR[28-31] LA[4-31], bypassing all protection mechanisms.
	232	*/
	233	*raddr = ((sr & 0xF) << 28) \| (eaddr & 0x0FFFFFFF);
	234	*prot = PAGE_READ \| PAGE_WRITE \| PAGE_EXEC;
	235	return 0;
	236	}
	237
	238	if (rwx == 2) {
	239	/* No code fetch is allowed in direct-store areas */
27103424	240	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	241	env->error_code = 0x10000000;
caa597bd DG	242	return 1;
723ed73a DG	243	}
	244
	245	switch (env->access_type) {
	246	case ACCESS_INT:
	247	/* Integer load/store : only access allowed */
	248	break;
	249	case ACCESS_FLOAT:
	250	/* Floating point load/store */
27103424	251	cs->exception_index = POWERPC_EXCP_ALIGN;
caa597bd DG	252	env->error_code = POWERPC_EXCP_ALIGN_FP;
	253	env->spr[SPR_DAR] = eaddr;
	254	return 1;
723ed73a DG	255	case ACCESS_RES:
723ed73a DG	256	/* lwarx, ldarx or srwcx. */
caa597bd DG	257	env->error_code = 0;
	258	env->spr[SPR_DAR] = eaddr;
	259	if (rwx == 1) {
	260	env->spr[SPR_DSISR] = 0x06000000;
	261	} else {
	262	env->spr[SPR_DSISR] = 0x04000000;
	263	}
	264	return 1;
723ed73a DG	265	case ACCESS_CACHE:
	266	/* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
	267	/* Should make the instruction do no-op.
	268	* As it already do no-op, it's quite easy :-)
	269	*/
	270	*raddr = eaddr;
	271	return 0;
	272	case ACCESS_EXT:
	273	/* eciwx or ecowx */
27103424	274	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	275	env->error_code = 0;
	276	env->spr[SPR_DAR] = eaddr;
	277	if (rwx == 1) {
	278	env->spr[SPR_DSISR] = 0x06100000;
	279	} else {
	280	env->spr[SPR_DSISR] = 0x04100000;
	281	}
	282	return 1;
723ed73a DG	283	default:
	284	qemu_log("ERROR: instruction should not need "
	285	"address translation\n");
caa597bd	286	abort();
723ed73a DG	287	}
	288	if ((rwx == 1 \|\| key != 1) && (rwx == 0 \|\| key != 0)) {
	289	*raddr = eaddr;
caa597bd	290	return 0;
723ed73a	291	} else {
27103424	292	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	293	env->error_code = 0;
	294	env->spr[SPR_DAR] = eaddr;
	295	if (rwx == 1) {
	296	env->spr[SPR_DSISR] = 0x0a000000;
	297	} else {
	298	env->spr[SPR_DSISR] = 0x08000000;
	299	}
	300	return 1;
723ed73a DG	301	}
	302	}
	303
59191721 DG	304	hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
59191721 DG	305	{
d5aea6f3	306	return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
59191721 DG	307	}
59191721 DG	308
aea390e4 DG	309	static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
	310	bool secondary, target_ulong ptem,
	311	ppc_hash_pte32_t *pte)
	312	{
	313	hwaddr pte_offset = pteg_off;
	314	target_ulong pte0, pte1;
	315	int i;
	316
	317	for (i = 0; i < HPTES_PER_GROUP; i++) {
	318	pte0 = ppc_hash32_load_hpte0(env, pte_offset);
	319	pte1 = ppc_hash32_load_hpte1(env, pte_offset);
	320
	321	if ((pte0 & HPTE32_V_VALID)
	322	&& (secondary == !!(pte0 & HPTE32_V_SECONDARY))
	323	&& HPTE32_V_COMPARE(pte0, ptem)) {
	324	pte->pte0 = pte0;
	325	pte->pte1 = pte1;
	326	return pte_offset;
	327	}
	328
	329	pte_offset += HASH_PTE_SIZE_32;
	330	}
	331
	332	return -1;
	333	}
	334
7f3bdc2d DG	335	static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
	336	target_ulong sr, target_ulong eaddr,
	337	ppc_hash_pte32_t *pte)
c69b6151	338	{
aea390e4	339	hwaddr pteg_off, pte_offset;
a1ff751a DG	340	hwaddr hash;
a1ff751a DG	341	uint32_t vsid, pgidx, ptem;
c69b6151	342
a1ff751a	343	vsid = sr & SR32_VSID;
a1ff751a DG	344	pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
	345	hash = vsid ^ pgidx;
	346	ptem = (vsid << 7) \| (pgidx >> 10);
	347
	348	/* Page address translation */
339aaf5b AP	349	qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
339aaf5b AP	350	" htab_mask " TARGET_FMT_plx
a1ff751a DG	351	" hash " TARGET_FMT_plx "\n",
	352	env->htab_base, env->htab_mask, hash);
	353
	354	/* Primary PTEG lookup */
339aaf5b	355	qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
a1ff751a DG	356	" vsid=%" PRIx32 " ptem=%" PRIx32
	357	" hash=" TARGET_FMT_plx "\n",
	358	env->htab_base, env->htab_mask, vsid, ptem, hash);
	359	pteg_off = get_pteg_offset32(env, hash);
7f3bdc2d	360	pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
a1ff751a DG	361	if (pte_offset == -1) {
a1ff751a DG	362	/* Secondary PTEG lookup */
339aaf5b	363	qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
a1ff751a DG	364	" vsid=%" PRIx32 " api=%" PRIx32
	365	" hash=" TARGET_FMT_plx "\n", env->htab_base,
	366	env->htab_mask, vsid, ptem, ~hash);
	367	pteg_off = get_pteg_offset32(env, ~hash);
7f3bdc2d	368	pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
a1ff751a DG	369	}
a1ff751a DG	370
7f3bdc2d	371	return pte_offset;
c69b6151	372	}
0480884f	373
6d11d998 DG	374	static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
	375	target_ulong eaddr)
	376	{
75d5ec89	377	hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
6d11d998 DG	378	hwaddr mask = ~TARGET_PAGE_MASK;
	379
	380	return (rpn & ~mask) \| (eaddr & mask);
	381	}
	382
d0e39c5d	383	int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
caa597bd	384	int mmu_idx)
0480884f	385	{
d0e39c5d AF	386	CPUState *cs = CPU(cpu);
d0e39c5d AF	387	CPUPPCState *env = &cpu->env;
a1ff751a	388	target_ulong sr;
7f3bdc2d DG	389	hwaddr pte_offset;
7f3bdc2d DG	390	ppc_hash_pte32_t pte;
caa597bd	391	int prot;
b3440746	392	uint32_t new_pte1;
e01b4445	393	const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
caa597bd	394	hwaddr raddr;
0480884f	395
6a980110 DG	396	assert((rwx == 0) \|\| (rwx == 1) \|\| (rwx == 2));
6a980110 DG	397
65d61643 DG	398	/* 1. Handle real mode accesses */
	399	if (((rwx == 2) && (msr_ir == 0)) \|\| ((rwx != 2) && (msr_dr == 0))) {
	400	/* Translation is off */
caa597bd	401	raddr = eaddr;
0c591eb0	402	tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
caa597bd DG	403	PAGE_READ \| PAGE_WRITE \| PAGE_EXEC, mmu_idx,
caa597bd DG	404	TARGET_PAGE_SIZE);
65d61643 DG	405	return 0;
	406	}
	407
	408	/* 2. Check Block Address Translation entries (BATs) */
	409	if (env->nb_BATs != 0) {
caa597bd DG	410	raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
	411	if (raddr != -1) {
	412	if (need_prot[rwx] & ~prot) {
	413	if (rwx == 2) {
27103424	414	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	415	env->error_code = 0x08000000;
caa597bd DG	416	} else {
27103424	417	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	418	env->error_code = 0;
	419	env->spr[SPR_DAR] = eaddr;
	420	if (rwx == 1) {
	421	env->spr[SPR_DSISR] = 0x0a000000;
	422	} else {
	423	env->spr[SPR_DSISR] = 0x08000000;
	424	}
	425	}
	426	return 1;
e01b4445	427	}
caa597bd	428
0c591eb0	429	tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
caa597bd DG	430	raddr & TARGET_PAGE_MASK, prot, mmu_idx,
caa597bd DG	431	TARGET_PAGE_SIZE);
e01b4445	432	return 0;
65d61643 DG	433	}
	434	}
	435
4b9605a5	436	/* 3. Look up the Segment Register */
0480884f	437	sr = env->sr[eaddr >> 28];
4b9605a5	438
4b9605a5 DG	439	/* 4. Handle direct store segments */
4b9605a5 DG	440	if (sr & SR32_T) {
caa597bd DG	441	if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
caa597bd DG	442	&raddr, &prot) == 0) {
0c591eb0	443	tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
caa597bd DG	444	raddr & TARGET_PAGE_MASK, prot, mmu_idx,
	445	TARGET_PAGE_SIZE);
	446	return 0;
	447	} else {
	448	return 1;
	449	}
4b9605a5 DG	450	}
4b9605a5 DG	451
bb218042	452	/* 5. Check for segment level no-execute violation */
e01b4445	453	if ((rwx == 2) && (sr & SR32_NX)) {
27103424	454	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	455	env->error_code = 0x10000000;
caa597bd DG	456	return 1;
bb218042	457	}
7f3bdc2d DG	458
	459	/* 6. Locate the PTE in the hash table */
	460	pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
	461	if (pte_offset == -1) {
caa597bd	462	if (rwx == 2) {
27103424	463	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	464	env->error_code = 0x40000000;
caa597bd DG	465	} else {
27103424	466	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	467	env->error_code = 0;
	468	env->spr[SPR_DAR] = eaddr;
	469	if (rwx == 1) {
	470	env->spr[SPR_DSISR] = 0x42000000;
	471	} else {
	472	env->spr[SPR_DSISR] = 0x40000000;
	473	}
	474	}
	475
	476	return 1;
7f3bdc2d	477	}
339aaf5b AP	478	qemu_log_mask(CPU_LOG_MMU,
339aaf5b AP	479	"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
7f3bdc2d DG	480
7f3bdc2d DG	481	/* 7. Check access permissions */
6a980110	482
caa597bd	483	prot = ppc_hash32_pte_prot(env, sr, pte);
6a980110	484
caa597bd	485	if (need_prot[rwx] & ~prot) {
6a980110	486	/* Access right violation */
339aaf5b	487	qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
caa597bd	488	if (rwx == 2) {
27103424	489	cs->exception_index = POWERPC_EXCP_ISI;
caa597bd DG	490	env->error_code = 0x08000000;
caa597bd DG	491	} else {
27103424	492	cs->exception_index = POWERPC_EXCP_DSI;
caa597bd DG	493	env->error_code = 0;
	494	env->spr[SPR_DAR] = eaddr;
	495	if (rwx == 1) {
	496	env->spr[SPR_DSISR] = 0x0a000000;
	497	} else {
	498	env->spr[SPR_DSISR] = 0x08000000;
	499	}
	500	}
	501	return 1;
6a980110 DG	502	}
6a980110 DG	503
339aaf5b	504	qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
87dc3fd1 DG	505
	506	/* 8. Update PTE referenced and changed bits if necessary */
	507
b3440746 DG	508	new_pte1 = pte.pte1 \| HPTE32_R_R; /* set referenced bit */
	509	if (rwx == 1) {
	510	new_pte1 \|= HPTE32_R_C; /* set changed (dirty) bit */
	511	} else {
	512	/* Treat the page as read-only for now, so that a later write
	513	* will pass through this function again to set the C bit */
caa597bd	514	prot &= ~PAGE_WRITE;
b3440746 DG	515	}
	516
	517	if (new_pte1 != pte.pte1) {
	518	ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
7f3bdc2d	519	}
0480884f	520
6d11d998 DG	521	/* 9. Determine the real address from the PTE */
6d11d998 DG	522
caa597bd DG	523	raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
caa597bd DG	524
0c591eb0	525	tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
caa597bd	526	prot, mmu_idx, TARGET_PAGE_SIZE);
e01b4445 DG	527
e01b4445 DG	528	return 0;
0480884f	529	}
629bd516	530
5883d8b2	531	hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
f2ad6be8	532	{
5883d8b2 DG	533	target_ulong sr;
	534	hwaddr pte_offset;
	535	ppc_hash_pte32_t pte;
	536	int prot;
	537
	538	if (msr_dr == 0) {
	539	/* Translation is off */
	540	return eaddr;
	541	}
f2ad6be8	542
5883d8b2 DG	543	if (env->nb_BATs != 0) {
	544	hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
	545	if (raddr != -1) {
	546	return raddr;
	547	}
	548	}
	549
	550	sr = env->sr[eaddr >> 28];
	551
	552	if (sr & SR32_T) {
	553	/* FIXME: Add suitable debug support for Direct Store segments */
	554	return -1;
	555	}
	556
	557	pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
	558	if (pte_offset == -1) {
f2ad6be8 DG	559	return -1;
	560	}
	561
5883d8b2	562	return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
f2ad6be8	563	}