]>
Commit | Line | Data |
---|---|---|
10b46525 DG |
1 | /* |
2 | * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * Copyright (c) 2013 David Gibson, IBM Corporation | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
0d75590d | 20 | #include "qemu/osdep.h" |
da34e65c | 21 | #include "qapi/error.h" |
10b46525 | 22 | #include "cpu.h" |
63c91552 | 23 | #include "exec/exec-all.h" |
2ef6175a | 24 | #include "exec/helper-proto.h" |
cd6a9bb6 | 25 | #include "qemu/error-report.h" |
10b46525 | 26 | #include "sysemu/kvm.h" |
be18b2b5 | 27 | #include "qemu/error-report.h" |
10b46525 DG |
28 | #include "kvm_ppc.h" |
29 | #include "mmu-hash64.h" | |
508127e2 | 30 | #include "exec/log.h" |
10b46525 DG |
31 | |
32 | //#define DEBUG_SLB | |
33 | ||
34 | #ifdef DEBUG_SLB | |
48880da6 | 35 | # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) |
10b46525 DG |
36 | #else |
37 | # define LOG_SLB(...) do { } while (0) | |
38 | #endif | |
39 | ||
7c43bca0 | 40 | /* |
c18ad9a5 DG |
41 | * Used to indicate that a CPU has its hash page table (HPT) managed |
42 | * within the host kernel | |
7c43bca0 | 43 | */ |
c18ad9a5 DG |
44 | #define MMU_HASH64_KVM_MANAGED_HPT ((void *)-1) |
45 | ||
10b46525 DG |
46 | /* |
47 | * SLB handling | |
48 | */ | |
49 | ||
7ef23068 | 50 | static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr) |
10b46525 | 51 | { |
7ef23068 | 52 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
53 | uint64_t esid_256M, esid_1T; |
54 | int n; | |
55 | ||
56 | LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); | |
57 | ||
58 | esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; | |
59 | esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; | |
60 | ||
61 | for (n = 0; n < env->slb_nr; n++) { | |
62 | ppc_slb_t *slb = &env->slb[n]; | |
63 | ||
64 | LOG_SLB("%s: slot %d %016" PRIx64 " %016" | |
65 | PRIx64 "\n", __func__, n, slb->esid, slb->vsid); | |
66 | /* We check for 1T matches on all MMUs here - if the MMU | |
67 | * doesn't have 1T segment support, we will have prevented 1T | |
68 | * entries from being inserted in the slbmte code. */ | |
69 | if (((slb->esid == esid_256M) && | |
70 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M)) | |
71 | || ((slb->esid == esid_1T) && | |
72 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) { | |
73 | return slb; | |
74 | } | |
75 | } | |
76 | ||
77 | return NULL; | |
78 | } | |
79 | ||
7ef23068 | 80 | void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu) |
10b46525 | 81 | { |
7ef23068 | 82 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
83 | int i; |
84 | uint64_t slbe, slbv; | |
85 | ||
7ef23068 | 86 | cpu_synchronize_state(CPU(cpu)); |
10b46525 DG |
87 | |
88 | cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n"); | |
89 | for (i = 0; i < env->slb_nr; i++) { | |
90 | slbe = env->slb[i].esid; | |
91 | slbv = env->slb[i].vsid; | |
92 | if (slbe == 0 && slbv == 0) { | |
93 | continue; | |
94 | } | |
95 | cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", | |
96 | i, slbe, slbv); | |
97 | } | |
98 | } | |
99 | ||
100 | void helper_slbia(CPUPPCState *env) | |
101 | { | |
cd0c6f47 | 102 | int n; |
10b46525 | 103 | |
10b46525 DG |
104 | /* XXX: Warning: slbia never invalidates the first segment */ |
105 | for (n = 1; n < env->slb_nr; n++) { | |
106 | ppc_slb_t *slb = &env->slb[n]; | |
107 | ||
108 | if (slb->esid & SLB_ESID_V) { | |
109 | slb->esid &= ~SLB_ESID_V; | |
110 | /* XXX: given the fact that segment size is 256 MB or 1TB, | |
111 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
112 | * in QEMU, we just invalidate all TLBs | |
113 | */ | |
cd0c6f47 | 114 | env->tlb_need_flush = 1; |
10b46525 DG |
115 | } |
116 | } | |
10b46525 DG |
117 | } |
118 | ||
119 | void helper_slbie(CPUPPCState *env, target_ulong addr) | |
120 | { | |
00c8cb0a | 121 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
10b46525 DG |
122 | ppc_slb_t *slb; |
123 | ||
7ef23068 | 124 | slb = slb_lookup(cpu, addr); |
10b46525 DG |
125 | if (!slb) { |
126 | return; | |
127 | } | |
128 | ||
129 | if (slb->esid & SLB_ESID_V) { | |
130 | slb->esid &= ~SLB_ESID_V; | |
131 | ||
132 | /* XXX: given the fact that segment size is 256 MB or 1TB, | |
133 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
134 | * in QEMU, we just invalidate all TLBs | |
135 | */ | |
cd0c6f47 | 136 | env->tlb_need_flush = 1; |
10b46525 DG |
137 | } |
138 | } | |
139 | ||
bcd81230 DG |
140 | int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, |
141 | target_ulong esid, target_ulong vsid) | |
10b46525 | 142 | { |
7ef23068 | 143 | CPUPPCState *env = &cpu->env; |
10b46525 | 144 | ppc_slb_t *slb = &env->slb[slot]; |
cd6a9bb6 DG |
145 | const struct ppc_one_seg_page_size *sps = NULL; |
146 | int i; | |
10b46525 | 147 | |
bcd81230 DG |
148 | if (slot >= env->slb_nr) { |
149 | return -1; /* Bad slot number */ | |
150 | } | |
151 | if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) { | |
152 | return -1; /* Reserved bits set */ | |
10b46525 | 153 | } |
bcd81230 | 154 | if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { |
10b46525 DG |
155 | return -1; /* Bad segment size */ |
156 | } | |
bcd81230 | 157 | if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) { |
10b46525 DG |
158 | return -1; /* 1T segment on MMU that doesn't support it */ |
159 | } | |
160 | ||
cd6a9bb6 DG |
161 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
162 | const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i]; | |
163 | ||
164 | if (!sps1->page_shift) { | |
165 | break; | |
166 | } | |
167 | ||
168 | if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { | |
169 | sps = sps1; | |
170 | break; | |
171 | } | |
172 | } | |
173 | ||
174 | if (!sps) { | |
175 | error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu | |
176 | " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx, | |
177 | slot, esid, vsid); | |
178 | return -1; | |
179 | } | |
180 | ||
bcd81230 DG |
181 | slb->esid = esid; |
182 | slb->vsid = vsid; | |
cd6a9bb6 | 183 | slb->sps = sps; |
10b46525 DG |
184 | |
185 | LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64 | |
bcd81230 | 186 | " %016" PRIx64 "\n", __func__, slot, esid, vsid, |
10b46525 DG |
187 | slb->esid, slb->vsid); |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
7ef23068 | 192 | static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb, |
10b46525 DG |
193 | target_ulong *rt) |
194 | { | |
7ef23068 | 195 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
196 | int slot = rb & 0xfff; |
197 | ppc_slb_t *slb = &env->slb[slot]; | |
198 | ||
199 | if (slot >= env->slb_nr) { | |
200 | return -1; | |
201 | } | |
202 | ||
203 | *rt = slb->esid; | |
204 | return 0; | |
205 | } | |
206 | ||
7ef23068 | 207 | static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
10b46525 DG |
208 | target_ulong *rt) |
209 | { | |
7ef23068 | 210 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
211 | int slot = rb & 0xfff; |
212 | ppc_slb_t *slb = &env->slb[slot]; | |
213 | ||
214 | if (slot >= env->slb_nr) { | |
215 | return -1; | |
216 | } | |
217 | ||
218 | *rt = slb->vsid; | |
219 | return 0; | |
220 | } | |
221 | ||
c76c22d5 BH |
222 | static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
223 | target_ulong *rt) | |
224 | { | |
225 | CPUPPCState *env = &cpu->env; | |
226 | ppc_slb_t *slb; | |
227 | ||
228 | if (!msr_is_64bit(env, env->msr)) { | |
229 | rb &= 0xffffffff; | |
230 | } | |
231 | slb = slb_lookup(cpu, rb); | |
232 | if (slb == NULL) { | |
233 | *rt = (target_ulong)-1ul; | |
234 | } else { | |
235 | *rt = slb->vsid; | |
236 | } | |
237 | return 0; | |
238 | } | |
239 | ||
10b46525 DG |
240 | void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) |
241 | { | |
7ef23068 DG |
242 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
243 | ||
bcd81230 | 244 | if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { |
10b46525 DG |
245 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
246 | POWERPC_EXCP_INVAL); | |
247 | } | |
248 | } | |
249 | ||
250 | target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) | |
251 | { | |
7ef23068 | 252 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
10b46525 DG |
253 | target_ulong rt = 0; |
254 | ||
7ef23068 | 255 | if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { |
10b46525 DG |
256 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
257 | POWERPC_EXCP_INVAL); | |
258 | } | |
259 | return rt; | |
260 | } | |
261 | ||
c76c22d5 BH |
262 | target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) |
263 | { | |
264 | PowerPCCPU *cpu = ppc_env_get_cpu(env); | |
265 | target_ulong rt = 0; | |
266 | ||
267 | if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { | |
268 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, | |
269 | POWERPC_EXCP_INVAL); | |
270 | } | |
271 | return rt; | |
272 | } | |
273 | ||
10b46525 DG |
274 | target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) |
275 | { | |
7ef23068 | 276 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
10b46525 DG |
277 | target_ulong rt = 0; |
278 | ||
7ef23068 | 279 | if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { |
10b46525 DG |
280 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
281 | POWERPC_EXCP_INVAL); | |
282 | } | |
283 | return rt; | |
284 | } | |
9d7c3f4a DG |
285 | |
286 | /* | |
287 | * 64-bit hash table MMU handling | |
288 | */ | |
e5c0d3ce DG |
289 | void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value, |
290 | Error **errp) | |
291 | { | |
292 | CPUPPCState *env = &cpu->env; | |
293 | target_ulong htabsize = value & SDR_64_HTABSIZE; | |
294 | ||
295 | env->spr[SPR_SDR1] = value; | |
296 | if (htabsize > 28) { | |
297 | error_setg(errp, | |
298 | "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1", | |
299 | htabsize); | |
300 | htabsize = 28; | |
301 | } | |
302 | env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1; | |
303 | env->htab_base = value & SDR_64_HTABORG; | |
304 | } | |
305 | ||
306 | void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift, | |
307 | Error **errp) | |
308 | { | |
309 | CPUPPCState *env = &cpu->env; | |
310 | Error *local_err = NULL; | |
311 | ||
c18ad9a5 DG |
312 | if (hpt) { |
313 | env->external_htab = hpt; | |
314 | } else { | |
315 | env->external_htab = MMU_HASH64_KVM_MANAGED_HPT; | |
316 | } | |
e5c0d3ce DG |
317 | ppc_hash64_set_sdr1(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18), |
318 | &local_err); | |
319 | if (local_err) { | |
320 | error_propagate(errp, local_err); | |
321 | return; | |
322 | } | |
323 | ||
324 | /* Not strictly necessary, but makes it clearer that an external | |
325 | * htab is in use when debugging */ | |
326 | env->htab_base = -1; | |
327 | ||
328 | if (kvm_enabled()) { | |
329 | if (kvmppc_put_books_sregs(cpu) < 0) { | |
330 | error_setg(errp, "Unable to update SDR1 in KVM"); | |
331 | } | |
332 | } | |
333 | } | |
9d7c3f4a | 334 | |
7ef23068 | 335 | static int ppc_hash64_pte_prot(PowerPCCPU *cpu, |
e01b4445 | 336 | ppc_slb_t *slb, ppc_hash_pte64_t pte) |
496272a7 | 337 | { |
7ef23068 | 338 | CPUPPCState *env = &cpu->env; |
e01b4445 DG |
339 | unsigned pp, key; |
340 | /* Some pp bit combinations have undefined behaviour, so default | |
341 | * to no access in those cases */ | |
342 | int prot = 0; | |
343 | ||
344 | key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP) | |
345 | : (slb->vsid & SLB_VSID_KS)); | |
346 | pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61); | |
496272a7 | 347 | |
496272a7 DG |
348 | if (key == 0) { |
349 | switch (pp) { | |
350 | case 0x0: | |
351 | case 0x1: | |
352 | case 0x2: | |
e01b4445 DG |
353 | prot = PAGE_READ | PAGE_WRITE; |
354 | break; | |
355 | ||
496272a7 DG |
356 | case 0x3: |
357 | case 0x6: | |
e01b4445 | 358 | prot = PAGE_READ; |
496272a7 DG |
359 | break; |
360 | } | |
361 | } else { | |
362 | switch (pp) { | |
363 | case 0x0: | |
364 | case 0x6: | |
e01b4445 | 365 | prot = 0; |
496272a7 | 366 | break; |
e01b4445 | 367 | |
496272a7 DG |
368 | case 0x1: |
369 | case 0x3: | |
e01b4445 | 370 | prot = PAGE_READ; |
496272a7 | 371 | break; |
e01b4445 | 372 | |
496272a7 | 373 | case 0x2: |
e01b4445 | 374 | prot = PAGE_READ | PAGE_WRITE; |
496272a7 DG |
375 | break; |
376 | } | |
377 | } | |
496272a7 | 378 | |
e01b4445 | 379 | /* No execute if either noexec or guarded bits set */ |
57d0a39d DG |
380 | if (!(pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) |
381 | || (slb->vsid & SLB_VSID_N)) { | |
e01b4445 | 382 | prot |= PAGE_EXEC; |
496272a7 DG |
383 | } |
384 | ||
e01b4445 | 385 | return prot; |
496272a7 DG |
386 | } |
387 | ||
7ef23068 | 388 | static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte) |
f80872e2 | 389 | { |
7ef23068 | 390 | CPUPPCState *env = &cpu->env; |
f80872e2 | 391 | int key, amrbits; |
363248e8 | 392 | int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
f80872e2 | 393 | |
f80872e2 DG |
394 | /* Only recent MMUs implement Virtual Page Class Key Protection */ |
395 | if (!(env->mmu_model & POWERPC_MMU_AMR)) { | |
363248e8 | 396 | return prot; |
f80872e2 DG |
397 | } |
398 | ||
399 | key = HPTE64_R_KEY(pte.pte1); | |
400 | amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3; | |
401 | ||
402 | /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */ | |
403 | /* env->spr[SPR_AMR]); */ | |
404 | ||
363248e8 CLG |
405 | /* |
406 | * A store is permitted if the AMR bit is 0. Remove write | |
407 | * protection if it is set. | |
408 | */ | |
f80872e2 | 409 | if (amrbits & 0x2) { |
363248e8 | 410 | prot &= ~PAGE_WRITE; |
f80872e2 | 411 | } |
363248e8 CLG |
412 | /* |
413 | * A load is permitted if the AMR bit is 0. Remove read | |
414 | * protection if it is set. | |
415 | */ | |
f80872e2 | 416 | if (amrbits & 0x1) { |
363248e8 | 417 | prot &= ~PAGE_READ; |
f80872e2 DG |
418 | } |
419 | ||
420 | return prot; | |
421 | } | |
422 | ||
7c43bca0 AK |
423 | uint64_t ppc_hash64_start_access(PowerPCCPU *cpu, target_ulong pte_index) |
424 | { | |
425 | uint64_t token = 0; | |
426 | hwaddr pte_offset; | |
427 | ||
428 | pte_offset = pte_index * HASH_PTE_SIZE_64; | |
c18ad9a5 | 429 | if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) { |
7c43bca0 AK |
430 | /* |
431 | * HTAB is controlled by KVM. Fetch the PTEG into a new buffer. | |
432 | */ | |
433 | token = kvmppc_hash64_read_pteg(cpu, pte_index); | |
c18ad9a5 | 434 | } else if (cpu->env.external_htab) { |
7c43bca0 | 435 | /* |
c18ad9a5 DG |
436 | * HTAB is controlled by QEMU. Just point to the internally |
437 | * accessible PTEG. | |
7c43bca0 | 438 | */ |
7c43bca0 AK |
439 | token = (uint64_t)(uintptr_t) cpu->env.external_htab + pte_offset; |
440 | } else if (cpu->env.htab_base) { | |
441 | token = cpu->env.htab_base + pte_offset; | |
442 | } | |
443 | return token; | |
444 | } | |
445 | ||
c18ad9a5 | 446 | void ppc_hash64_stop_access(PowerPCCPU *cpu, uint64_t token) |
7c43bca0 | 447 | { |
c18ad9a5 | 448 | if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) { |
a9ab06d1 | 449 | kvmppc_hash64_free_pteg(token); |
7c43bca0 AK |
450 | } |
451 | } | |
452 | ||
651060ab DG |
453 | static unsigned hpte_page_shift(const struct ppc_one_seg_page_size *sps, |
454 | uint64_t pte0, uint64_t pte1) | |
4322e8ce | 455 | { |
651060ab DG |
456 | int i; |
457 | ||
458 | if (!(pte0 & HPTE64_V_LARGE)) { | |
459 | if (sps->page_shift != 12) { | |
460 | /* 4kiB page in a non 4kiB segment */ | |
461 | return 0; | |
462 | } | |
463 | /* Normal 4kiB page */ | |
4322e8ce | 464 | return 12; |
651060ab DG |
465 | } |
466 | ||
467 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
468 | const struct ppc_one_page_size *ps = &sps->enc[i]; | |
469 | uint64_t mask; | |
470 | ||
471 | if (!ps->page_shift) { | |
472 | break; | |
4322e8ce | 473 | } |
651060ab DG |
474 | |
475 | if (ps->page_shift == 12) { | |
476 | /* L bit is set so this can't be a 4kiB page */ | |
477 | continue; | |
478 | } | |
479 | ||
480 | mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN; | |
481 | ||
482 | if ((pte1 & mask) == (ps->pte_enc << HPTE64_R_RPN_SHIFT)) { | |
483 | return ps->page_shift; | |
4322e8ce | 484 | } |
4322e8ce | 485 | } |
651060ab DG |
486 | |
487 | return 0; /* Bad page size encoding */ | |
4322e8ce BH |
488 | } |
489 | ||
7ef23068 | 490 | static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash, |
073de86a | 491 | ppc_slb_t *slb, target_ulong ptem, |
94986863 | 492 | ppc_hash_pte64_t *pte, unsigned *pshift) |
aea390e4 | 493 | { |
7ef23068 | 494 | CPUPPCState *env = &cpu->env; |
aea390e4 | 495 | int i; |
7c43bca0 AK |
496 | uint64_t token; |
497 | target_ulong pte0, pte1; | |
498 | target_ulong pte_index; | |
aea390e4 | 499 | |
7c43bca0 | 500 | pte_index = (hash & env->htab_mask) * HPTES_PER_GROUP; |
7ef23068 | 501 | token = ppc_hash64_start_access(cpu, pte_index); |
7c43bca0 AK |
502 | if (!token) { |
503 | return -1; | |
504 | } | |
aea390e4 | 505 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
7ef23068 DG |
506 | pte0 = ppc_hash64_load_hpte0(cpu, token, i); |
507 | pte1 = ppc_hash64_load_hpte1(cpu, token, i); | |
aea390e4 | 508 | |
073de86a DG |
509 | /* This compares V, B, H (secondary) and the AVPN */ |
510 | if (HPTE64_V_COMPARE(pte0, ptem)) { | |
94986863 | 511 | *pshift = hpte_page_shift(slb->sps, pte0, pte1); |
651060ab DG |
512 | /* |
513 | * If there is no match, ignore the PTE, it could simply | |
514 | * be for a different segment size encoding and the | |
515 | * architecture specifies we should not match. Linux will | |
516 | * potentially leave behind PTEs for the wrong base page | |
517 | * size when demoting segments. | |
518 | */ | |
94986863 | 519 | if (*pshift == 0) { |
4322e8ce BH |
520 | continue; |
521 | } | |
522 | /* We don't do anything with pshift yet as qemu TLB only deals | |
523 | * with 4K pages anyway | |
524 | */ | |
aea390e4 DG |
525 | pte->pte0 = pte0; |
526 | pte->pte1 = pte1; | |
c18ad9a5 | 527 | ppc_hash64_stop_access(cpu, token); |
7c43bca0 | 528 | return (pte_index + i) * HASH_PTE_SIZE_64; |
aea390e4 | 529 | } |
aea390e4 | 530 | } |
c18ad9a5 | 531 | ppc_hash64_stop_access(cpu, token); |
7c43bca0 AK |
532 | /* |
533 | * We didn't find a valid entry. | |
534 | */ | |
aea390e4 DG |
535 | return -1; |
536 | } | |
537 | ||
7ef23068 | 538 | static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, |
7f3bdc2d | 539 | ppc_slb_t *slb, target_ulong eaddr, |
94986863 | 540 | ppc_hash_pte64_t *pte, unsigned *pshift) |
c69b6151 | 541 | { |
7ef23068 | 542 | CPUPPCState *env = &cpu->env; |
7c43bca0 | 543 | hwaddr pte_offset; |
a1ff751a | 544 | hwaddr hash; |
cd6a9bb6 DG |
545 | uint64_t vsid, epnmask, epn, ptem; |
546 | ||
547 | /* The SLB store path should prevent any bad page size encodings | |
548 | * getting in there, so: */ | |
549 | assert(slb->sps); | |
a1ff751a | 550 | |
cd6a9bb6 | 551 | epnmask = ~((1ULL << slb->sps->page_shift) - 1); |
a1ff751a | 552 | |
a1ff751a | 553 | if (slb->vsid & SLB_VSID_B) { |
18148898 DG |
554 | /* 1TB segment */ |
555 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T; | |
556 | epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask; | |
cd6a9bb6 | 557 | hash = vsid ^ (vsid << 25) ^ (epn >> slb->sps->page_shift); |
a1ff751a | 558 | } else { |
18148898 DG |
559 | /* 256M segment */ |
560 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; | |
561 | epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask; | |
cd6a9bb6 | 562 | hash = vsid ^ (epn >> slb->sps->page_shift); |
a1ff751a | 563 | } |
18148898 | 564 | ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN); |
073de86a | 565 | ptem |= HPTE64_V_VALID; |
a1ff751a | 566 | |
a1ff751a | 567 | /* Page address translation */ |
339aaf5b AP |
568 | qemu_log_mask(CPU_LOG_MMU, |
569 | "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx | |
a1ff751a DG |
570 | " hash " TARGET_FMT_plx "\n", |
571 | env->htab_base, env->htab_mask, hash); | |
572 | ||
a1ff751a | 573 | /* Primary PTEG lookup */ |
339aaf5b AP |
574 | qemu_log_mask(CPU_LOG_MMU, |
575 | "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
a1ff751a DG |
576 | " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx |
577 | " hash=" TARGET_FMT_plx "\n", | |
578 | env->htab_base, env->htab_mask, vsid, ptem, hash); | |
94986863 | 579 | pte_offset = ppc_hash64_pteg_search(cpu, hash, slb, ptem, pte, pshift); |
7f3bdc2d | 580 | |
a1ff751a DG |
581 | if (pte_offset == -1) { |
582 | /* Secondary PTEG lookup */ | |
073de86a | 583 | ptem |= HPTE64_V_SECONDARY; |
339aaf5b AP |
584 | qemu_log_mask(CPU_LOG_MMU, |
585 | "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
a1ff751a DG |
586 | " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx |
587 | " hash=" TARGET_FMT_plx "\n", env->htab_base, | |
588 | env->htab_mask, vsid, ptem, ~hash); | |
589 | ||
94986863 | 590 | pte_offset = ppc_hash64_pteg_search(cpu, ~hash, slb, ptem, pte, pshift); |
a1ff751a DG |
591 | } |
592 | ||
7f3bdc2d | 593 | return pte_offset; |
c69b6151 | 594 | } |
0480884f | 595 | |
1114e712 | 596 | unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, |
1f0252e6 | 597 | uint64_t pte0, uint64_t pte1) |
1114e712 DG |
598 | { |
599 | CPUPPCState *env = &cpu->env; | |
600 | int i; | |
601 | ||
602 | if (!(pte0 & HPTE64_V_LARGE)) { | |
1114e712 DG |
603 | return 12; |
604 | } | |
605 | ||
606 | /* | |
607 | * The encodings in env->sps need to be carefully chosen so that | |
608 | * this gives an unambiguous result. | |
609 | */ | |
610 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
611 | const struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; | |
612 | unsigned shift; | |
613 | ||
614 | if (!sps->page_shift) { | |
615 | break; | |
616 | } | |
617 | ||
618 | shift = hpte_page_shift(sps, pte0, pte1); | |
619 | if (shift) { | |
1114e712 DG |
620 | return shift; |
621 | } | |
622 | } | |
623 | ||
1114e712 DG |
624 | return 0; |
625 | } | |
626 | ||
33595dc9 BH |
627 | static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env, |
628 | uint64_t error_code) | |
629 | { | |
630 | bool vpm; | |
631 | ||
632 | if (msr_ir) { | |
633 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); | |
634 | } else { | |
635 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); | |
636 | } | |
637 | if (vpm && !msr_hv) { | |
638 | cs->exception_index = POWERPC_EXCP_HISI; | |
639 | } else { | |
640 | cs->exception_index = POWERPC_EXCP_ISI; | |
641 | } | |
642 | env->error_code = error_code; | |
643 | } | |
644 | ||
645 | static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar, | |
646 | uint64_t dsisr) | |
647 | { | |
648 | bool vpm; | |
649 | ||
650 | if (msr_dr) { | |
651 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); | |
652 | } else { | |
653 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); | |
654 | } | |
655 | if (vpm && !msr_hv) { | |
656 | cs->exception_index = POWERPC_EXCP_HDSI; | |
657 | env->spr[SPR_HDAR] = dar; | |
658 | env->spr[SPR_HDSISR] = dsisr; | |
659 | } else { | |
660 | cs->exception_index = POWERPC_EXCP_DSI; | |
661 | env->spr[SPR_DAR] = dar; | |
662 | env->spr[SPR_DSISR] = dsisr; | |
663 | } | |
664 | env->error_code = 0; | |
665 | } | |
666 | ||
667 | ||
b2305601 | 668 | int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, |
caa597bd | 669 | int rwx, int mmu_idx) |
0480884f | 670 | { |
d0e39c5d AF |
671 | CPUState *cs = CPU(cpu); |
672 | CPUPPCState *env = &cpu->env; | |
0480884f | 673 | ppc_slb_t *slb; |
be18b2b5 | 674 | unsigned apshift; |
7f3bdc2d DG |
675 | hwaddr pte_offset; |
676 | ppc_hash_pte64_t pte; | |
f80872e2 | 677 | int pp_prot, amr_prot, prot; |
33595dc9 | 678 | uint64_t new_pte1, dsisr; |
e01b4445 | 679 | const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; |
caa597bd | 680 | hwaddr raddr; |
0480884f | 681 | |
6a980110 DG |
682 | assert((rwx == 0) || (rwx == 1) || (rwx == 2)); |
683 | ||
912acdf4 BH |
684 | /* Note on LPCR usage: 970 uses HID4, but our special variant |
685 | * of store_spr copies relevant fields into env->spr[SPR_LPCR]. | |
686 | * Similarily we filter unimplemented bits when storing into | |
687 | * LPCR depending on the MMU version. This code can thus just | |
688 | * use the LPCR "as-is". | |
689 | */ | |
690 | ||
65d61643 DG |
691 | /* 1. Handle real mode accesses */ |
692 | if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { | |
912acdf4 BH |
693 | /* Translation is supposedly "off" */ |
694 | /* In real mode the top 4 effective address bits are (mostly) ignored */ | |
caa597bd | 695 | raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; |
912acdf4 BH |
696 | |
697 | /* In HV mode, add HRMOR if top EA bit is clear */ | |
698 | if (msr_hv || !env->has_hv_mode) { | |
699 | if (!(eaddr >> 63)) { | |
700 | raddr |= env->spr[SPR_HRMOR]; | |
701 | } | |
702 | } else { | |
703 | /* Otherwise, check VPM for RMA vs VRMA */ | |
704 | if (env->spr[SPR_LPCR] & LPCR_VPM0) { | |
705 | slb = &env->vrma_slb; | |
706 | if (slb->sps) { | |
707 | goto skip_slb_search; | |
708 | } | |
709 | /* Not much else to do here */ | |
710 | cs->exception_index = POWERPC_EXCP_MCHECK; | |
711 | env->error_code = 0; | |
712 | return 1; | |
713 | } else if (raddr < env->rmls) { | |
714 | /* RMA. Check bounds in RMLS */ | |
715 | raddr |= env->spr[SPR_RMOR]; | |
716 | } else { | |
717 | /* The access failed, generate the approriate interrupt */ | |
718 | if (rwx == 2) { | |
719 | ppc_hash64_set_isi(cs, env, 0x08000000); | |
720 | } else { | |
721 | dsisr = 0x08000000; | |
722 | if (rwx == 1) { | |
723 | dsisr |= 0x02000000; | |
724 | } | |
725 | ppc_hash64_set_dsi(cs, env, eaddr, dsisr); | |
726 | } | |
727 | return 1; | |
728 | } | |
729 | } | |
0c591eb0 | 730 | tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
caa597bd DG |
731 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, |
732 | TARGET_PAGE_SIZE); | |
65d61643 DG |
733 | return 0; |
734 | } | |
735 | ||
bb218042 | 736 | /* 2. Translation is on, so look up the SLB */ |
7ef23068 | 737 | slb = slb_lookup(cpu, eaddr); |
0480884f | 738 | if (!slb) { |
caa597bd | 739 | if (rwx == 2) { |
27103424 | 740 | cs->exception_index = POWERPC_EXCP_ISEG; |
caa597bd DG |
741 | env->error_code = 0; |
742 | } else { | |
27103424 | 743 | cs->exception_index = POWERPC_EXCP_DSEG; |
caa597bd DG |
744 | env->error_code = 0; |
745 | env->spr[SPR_DAR] = eaddr; | |
746 | } | |
747 | return 1; | |
0480884f DG |
748 | } |
749 | ||
912acdf4 BH |
750 | skip_slb_search: |
751 | ||
bb218042 DG |
752 | /* 3. Check for segment level no-execute violation */ |
753 | if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { | |
33595dc9 | 754 | ppc_hash64_set_isi(cs, env, 0x10000000); |
caa597bd | 755 | return 1; |
bb218042 DG |
756 | } |
757 | ||
7f3bdc2d | 758 | /* 4. Locate the PTE in the hash table */ |
94986863 | 759 | pte_offset = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); |
7f3bdc2d | 760 | if (pte_offset == -1) { |
33595dc9 | 761 | dsisr = 0x40000000; |
caa597bd | 762 | if (rwx == 2) { |
33595dc9 | 763 | ppc_hash64_set_isi(cs, env, dsisr); |
caa597bd | 764 | } else { |
caa597bd | 765 | if (rwx == 1) { |
33595dc9 | 766 | dsisr |= 0x02000000; |
caa597bd | 767 | } |
33595dc9 | 768 | ppc_hash64_set_dsi(cs, env, eaddr, dsisr); |
caa597bd DG |
769 | } |
770 | return 1; | |
7f3bdc2d | 771 | } |
339aaf5b AP |
772 | qemu_log_mask(CPU_LOG_MMU, |
773 | "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); | |
7f3bdc2d DG |
774 | |
775 | /* 5. Check access permissions */ | |
7f3bdc2d | 776 | |
7ef23068 DG |
777 | pp_prot = ppc_hash64_pte_prot(cpu, slb, pte); |
778 | amr_prot = ppc_hash64_amr_prot(cpu, pte); | |
f80872e2 | 779 | prot = pp_prot & amr_prot; |
6a980110 | 780 | |
caa597bd | 781 | if ((need_prot[rwx] & ~prot) != 0) { |
6a980110 | 782 | /* Access right violation */ |
339aaf5b | 783 | qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); |
caa597bd | 784 | if (rwx == 2) { |
33595dc9 | 785 | ppc_hash64_set_isi(cs, env, 0x08000000); |
caa597bd | 786 | } else { |
33595dc9 | 787 | dsisr = 0; |
f80872e2 DG |
788 | if (need_prot[rwx] & ~pp_prot) { |
789 | dsisr |= 0x08000000; | |
790 | } | |
caa597bd | 791 | if (rwx == 1) { |
f80872e2 DG |
792 | dsisr |= 0x02000000; |
793 | } | |
794 | if (need_prot[rwx] & ~amr_prot) { | |
795 | dsisr |= 0x00200000; | |
caa597bd | 796 | } |
33595dc9 | 797 | ppc_hash64_set_dsi(cs, env, eaddr, dsisr); |
caa597bd DG |
798 | } |
799 | return 1; | |
6a980110 DG |
800 | } |
801 | ||
339aaf5b | 802 | qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); |
87dc3fd1 DG |
803 | |
804 | /* 6. Update PTE referenced and changed bits if necessary */ | |
805 | ||
b3440746 DG |
806 | new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */ |
807 | if (rwx == 1) { | |
808 | new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */ | |
809 | } else { | |
810 | /* Treat the page as read-only for now, so that a later write | |
811 | * will pass through this function again to set the C bit */ | |
caa597bd | 812 | prot &= ~PAGE_WRITE; |
b3440746 DG |
813 | } |
814 | ||
815 | if (new_pte1 != pte.pte1) { | |
7ef23068 | 816 | ppc_hash64_store_hpte(cpu, pte_offset / HASH_PTE_SIZE_64, |
3f94170b | 817 | pte.pte0, new_pte1); |
7f3bdc2d | 818 | } |
0480884f | 819 | |
6d11d998 DG |
820 | /* 7. Determine the real address from the PTE */ |
821 | ||
be18b2b5 | 822 | raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); |
caa597bd | 823 | |
0c591eb0 | 824 | tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
be18b2b5 | 825 | prot, mmu_idx, 1ULL << apshift); |
e01b4445 | 826 | |
e01b4445 | 827 | return 0; |
0480884f | 828 | } |
629bd516 | 829 | |
7ef23068 | 830 | hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) |
f2ad6be8 | 831 | { |
7ef23068 | 832 | CPUPPCState *env = &cpu->env; |
5883d8b2 | 833 | ppc_slb_t *slb; |
912acdf4 | 834 | hwaddr pte_offset, raddr; |
5883d8b2 | 835 | ppc_hash_pte64_t pte; |
be18b2b5 | 836 | unsigned apshift; |
5883d8b2 | 837 | |
912acdf4 | 838 | /* Handle real mode */ |
5883d8b2 DG |
839 | if (msr_dr == 0) { |
840 | /* In real mode the top 4 effective address bits are ignored */ | |
912acdf4 | 841 | raddr = addr & 0x0FFFFFFFFFFFFFFFULL; |
f2ad6be8 | 842 | |
912acdf4 BH |
843 | /* In HV mode, add HRMOR if top EA bit is clear */ |
844 | if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { | |
845 | return raddr | env->spr[SPR_HRMOR]; | |
846 | } | |
847 | ||
848 | /* Otherwise, check VPM for RMA vs VRMA */ | |
849 | if (env->spr[SPR_LPCR] & LPCR_VPM0) { | |
850 | slb = &env->vrma_slb; | |
851 | if (!slb->sps) { | |
852 | return -1; | |
853 | } | |
854 | } else if (raddr < env->rmls) { | |
855 | /* RMA. Check bounds in RMLS */ | |
856 | return raddr | env->spr[SPR_RMOR]; | |
857 | } else { | |
858 | return -1; | |
859 | } | |
860 | } else { | |
861 | slb = slb_lookup(cpu, addr); | |
862 | if (!slb) { | |
863 | return -1; | |
864 | } | |
5883d8b2 DG |
865 | } |
866 | ||
94986863 | 867 | pte_offset = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift); |
5883d8b2 | 868 | if (pte_offset == -1) { |
f2ad6be8 DG |
869 | return -1; |
870 | } | |
871 | ||
be18b2b5 | 872 | return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr) |
cd6a9bb6 | 873 | & TARGET_PAGE_MASK; |
f2ad6be8 | 874 | } |
c1385933 | 875 | |
7ef23068 | 876 | void ppc_hash64_store_hpte(PowerPCCPU *cpu, |
c1385933 AK |
877 | target_ulong pte_index, |
878 | target_ulong pte0, target_ulong pte1) | |
879 | { | |
7ef23068 | 880 | CPUPPCState *env = &cpu->env; |
c1385933 | 881 | |
c18ad9a5 | 882 | if (env->external_htab == MMU_HASH64_KVM_MANAGED_HPT) { |
a9ab06d1 SW |
883 | kvmppc_hash64_write_pte(env, pte_index, pte0, pte1); |
884 | return; | |
c1385933 AK |
885 | } |
886 | ||
887 | pte_index *= HASH_PTE_SIZE_64; | |
888 | if (env->external_htab) { | |
889 | stq_p(env->external_htab + pte_index, pte0); | |
7ef23068 | 890 | stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64 / 2, pte1); |
c1385933 | 891 | } else { |
7ef23068 DG |
892 | stq_phys(CPU(cpu)->as, env->htab_base + pte_index, pte0); |
893 | stq_phys(CPU(cpu)->as, | |
894 | env->htab_base + pte_index + HASH_PTE_SIZE_64 / 2, pte1); | |
c1385933 AK |
895 | } |
896 | } | |
61a36c9b DG |
897 | |
898 | void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, | |
899 | target_ulong pte_index, | |
900 | target_ulong pte0, target_ulong pte1) | |
901 | { | |
902 | /* | |
903 | * XXX: given the fact that there are too many segments to | |
904 | * invalidate, and we still don't have a tlb_flush_mask(env, n, | |
905 | * mask) in QEMU, we just invalidate all TLBs | |
906 | */ | |
907 | tlb_flush(CPU(cpu), 1); | |
908 | } | |
4b3fc377 | 909 | |
912acdf4 BH |
910 | void ppc_hash64_update_rmls(CPUPPCState *env) |
911 | { | |
912 | uint64_t lpcr = env->spr[SPR_LPCR]; | |
913 | ||
914 | /* | |
915 | * This is the full 4 bits encoding of POWER8. Previous | |
916 | * CPUs only support a subset of these but the filtering | |
917 | * is done when writing LPCR | |
918 | */ | |
919 | switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { | |
920 | case 0x8: /* 32MB */ | |
921 | env->rmls = 0x2000000ull; | |
922 | break; | |
923 | case 0x3: /* 64MB */ | |
924 | env->rmls = 0x4000000ull; | |
925 | break; | |
926 | case 0x7: /* 128MB */ | |
927 | env->rmls = 0x8000000ull; | |
928 | break; | |
929 | case 0x4: /* 256MB */ | |
930 | env->rmls = 0x10000000ull; | |
931 | break; | |
932 | case 0x2: /* 1GB */ | |
933 | env->rmls = 0x40000000ull; | |
934 | break; | |
935 | case 0x1: /* 16GB */ | |
936 | env->rmls = 0x400000000ull; | |
937 | break; | |
938 | default: | |
939 | /* What to do here ??? */ | |
940 | env->rmls = 0; | |
941 | } | |
942 | } | |
943 | ||
944 | void ppc_hash64_update_vrma(CPUPPCState *env) | |
945 | { | |
946 | const struct ppc_one_seg_page_size *sps = NULL; | |
947 | target_ulong esid, vsid, lpcr; | |
948 | ppc_slb_t *slb = &env->vrma_slb; | |
949 | uint32_t vrmasd; | |
950 | int i; | |
951 | ||
952 | /* First clear it */ | |
953 | slb->esid = slb->vsid = 0; | |
954 | slb->sps = NULL; | |
955 | ||
956 | /* Is VRMA enabled ? */ | |
957 | lpcr = env->spr[SPR_LPCR]; | |
958 | if (!(lpcr & LPCR_VPM0)) { | |
959 | return; | |
960 | } | |
961 | ||
962 | /* Make one up. Mostly ignore the ESID which will not be | |
963 | * needed for translation | |
964 | */ | |
965 | vsid = SLB_VSID_VRMA; | |
966 | vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; | |
967 | vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); | |
968 | esid = SLB_ESID_V; | |
969 | ||
970 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
971 | const struct ppc_one_seg_page_size *sps1 = &env->sps.sps[i]; | |
972 | ||
973 | if (!sps1->page_shift) { | |
974 | break; | |
975 | } | |
976 | ||
977 | if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { | |
978 | sps = sps1; | |
979 | break; | |
980 | } | |
981 | } | |
982 | ||
983 | if (!sps) { | |
984 | error_report("Bad page size encoding esid 0x"TARGET_FMT_lx | |
985 | " vsid 0x"TARGET_FMT_lx, esid, vsid); | |
986 | return; | |
987 | } | |
988 | ||
989 | slb->vsid = vsid; | |
990 | slb->esid = esid; | |
991 | slb->sps = sps; | |
992 | } | |
993 | ||
4b3fc377 BH |
994 | void helper_store_lpcr(CPUPPCState *env, target_ulong val) |
995 | { | |
996 | uint64_t lpcr = 0; | |
997 | ||
998 | /* Filter out bits */ | |
999 | switch (env->mmu_model) { | |
1000 | case POWERPC_MMU_64B: /* 970 */ | |
1001 | if (val & 0x40) { | |
1002 | lpcr |= LPCR_LPES0; | |
1003 | } | |
1004 | if (val & 0x8000000000000000ull) { | |
1005 | lpcr |= LPCR_LPES1; | |
1006 | } | |
1007 | if (val & 0x20) { | |
1008 | lpcr |= (0x4ull << LPCR_RMLS_SHIFT); | |
1009 | } | |
1010 | if (val & 0x4000000000000000ull) { | |
1011 | lpcr |= (0x2ull << LPCR_RMLS_SHIFT); | |
1012 | } | |
1013 | if (val & 0x2000000000000000ull) { | |
1014 | lpcr |= (0x1ull << LPCR_RMLS_SHIFT); | |
1015 | } | |
1016 | env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26; | |
1017 | ||
1018 | /* XXX We could also write LPID from HID4 here | |
1019 | * but since we don't tag any translation on it | |
1020 | * it doesn't actually matter | |
1021 | */ | |
1022 | /* XXX For proper emulation of 970 we also need | |
1023 | * to dig HRMOR out of HID5 | |
1024 | */ | |
1025 | break; | |
1026 | case POWERPC_MMU_2_03: /* P5p */ | |
1027 | lpcr = val & (LPCR_RMLS | LPCR_ILE | | |
1028 | LPCR_LPES0 | LPCR_LPES1 | | |
1029 | LPCR_RMI | LPCR_HDICE); | |
1030 | break; | |
1031 | case POWERPC_MMU_2_06: /* P7 */ | |
1032 | lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | | |
1033 | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | | |
1034 | LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | | |
1035 | LPCR_MER | LPCR_TC | | |
1036 | LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); | |
1037 | break; | |
1038 | case POWERPC_MMU_2_07: /* P8 */ | |
1039 | lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | | |
1040 | LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | | |
1041 | LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | | |
1042 | LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | | |
1043 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); | |
1044 | break; | |
1045 | default: | |
1046 | ; | |
1047 | } | |
1048 | env->spr[SPR_LPCR] = lpcr; | |
912acdf4 BH |
1049 | ppc_hash64_update_rmls(env); |
1050 | ppc_hash64_update_vrma(env); | |
4b3fc377 | 1051 | } |