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mmu-hash*: Add hash pte load/store helpers
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CommitLineData
10b46525
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1/*
2 * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2013 David Gibson, IBM Corporation
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20#include "cpu.h"
21#include "helper.h"
22#include "sysemu/kvm.h"
23#include "kvm_ppc.h"
24#include "mmu-hash64.h"
25
9d7c3f4a 26//#define DEBUG_MMU
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27//#define DEBUG_SLB
28
9d7c3f4a
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29#ifdef DEBUG_MMU
30# define LOG_MMU(...) qemu_log(__VA_ARGS__)
31# define LOG_MMU_STATE(env) log_cpu_state((env), 0)
32#else
33# define LOG_MMU(...) do { } while (0)
34# define LOG_MMU_STATE(...) do { } while (0)
35#endif
36
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37#ifdef DEBUG_SLB
38# define LOG_SLB(...) qemu_log(__VA_ARGS__)
39#else
40# define LOG_SLB(...) do { } while (0)
41#endif
42
5dc68eb0
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43struct mmu_ctx_hash64 {
44 hwaddr raddr; /* Real address */
45 hwaddr eaddr; /* Effective address */
46 int prot; /* Protection bits */
47 hwaddr hash[2]; /* Pagetable hash values */
48 target_ulong ptem; /* Virtual segment ID | API */
49 int key; /* Access key */
50 int nx; /* Non-execute area */
51};
52
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53/*
54 * SLB handling
55 */
56
0480884f 57static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
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58{
59 uint64_t esid_256M, esid_1T;
60 int n;
61
62 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
63
64 esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
65 esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
66
67 for (n = 0; n < env->slb_nr; n++) {
68 ppc_slb_t *slb = &env->slb[n];
69
70 LOG_SLB("%s: slot %d %016" PRIx64 " %016"
71 PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
72 /* We check for 1T matches on all MMUs here - if the MMU
73 * doesn't have 1T segment support, we will have prevented 1T
74 * entries from being inserted in the slbmte code. */
75 if (((slb->esid == esid_256M) &&
76 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
77 || ((slb->esid == esid_1T) &&
78 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
79 return slb;
80 }
81 }
82
83 return NULL;
84}
85
86void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
87{
88 int i;
89 uint64_t slbe, slbv;
90
91 cpu_synchronize_state(env);
92
93 cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
94 for (i = 0; i < env->slb_nr; i++) {
95 slbe = env->slb[i].esid;
96 slbv = env->slb[i].vsid;
97 if (slbe == 0 && slbv == 0) {
98 continue;
99 }
100 cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
101 i, slbe, slbv);
102 }
103}
104
105void helper_slbia(CPUPPCState *env)
106{
107 int n, do_invalidate;
108
109 do_invalidate = 0;
110 /* XXX: Warning: slbia never invalidates the first segment */
111 for (n = 1; n < env->slb_nr; n++) {
112 ppc_slb_t *slb = &env->slb[n];
113
114 if (slb->esid & SLB_ESID_V) {
115 slb->esid &= ~SLB_ESID_V;
116 /* XXX: given the fact that segment size is 256 MB or 1TB,
117 * and we still don't have a tlb_flush_mask(env, n, mask)
118 * in QEMU, we just invalidate all TLBs
119 */
120 do_invalidate = 1;
121 }
122 }
123 if (do_invalidate) {
124 tlb_flush(env, 1);
125 }
126}
127
128void helper_slbie(CPUPPCState *env, target_ulong addr)
129{
130 ppc_slb_t *slb;
131
132 slb = slb_lookup(env, addr);
133 if (!slb) {
134 return;
135 }
136
137 if (slb->esid & SLB_ESID_V) {
138 slb->esid &= ~SLB_ESID_V;
139
140 /* XXX: given the fact that segment size is 256 MB or 1TB,
141 * and we still don't have a tlb_flush_mask(env, n, mask)
142 * in QEMU, we just invalidate all TLBs
143 */
144 tlb_flush(env, 1);
145 }
146}
147
148int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
149{
150 int slot = rb & 0xfff;
151 ppc_slb_t *slb = &env->slb[slot];
152
153 if (rb & (0x1000 - env->slb_nr)) {
154 return -1; /* Reserved bits set or slot too high */
155 }
156 if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
157 return -1; /* Bad segment size */
158 }
159 if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
160 return -1; /* 1T segment on MMU that doesn't support it */
161 }
162
163 /* Mask out the slot number as we store the entry */
164 slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
165 slb->vsid = rs;
166
167 LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
168 " %016" PRIx64 "\n", __func__, slot, rb, rs,
169 slb->esid, slb->vsid);
170
171 return 0;
172}
173
174static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
175 target_ulong *rt)
176{
177 int slot = rb & 0xfff;
178 ppc_slb_t *slb = &env->slb[slot];
179
180 if (slot >= env->slb_nr) {
181 return -1;
182 }
183
184 *rt = slb->esid;
185 return 0;
186}
187
188static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
189 target_ulong *rt)
190{
191 int slot = rb & 0xfff;
192 ppc_slb_t *slb = &env->slb[slot];
193
194 if (slot >= env->slb_nr) {
195 return -1;
196 }
197
198 *rt = slb->vsid;
199 return 0;
200}
201
202void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
203{
204 if (ppc_store_slb(env, rb, rs) < 0) {
205 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
206 POWERPC_EXCP_INVAL);
207 }
208}
209
210target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
211{
212 target_ulong rt = 0;
213
214 if (ppc_load_slb_esid(env, rb, &rt) < 0) {
215 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
216 POWERPC_EXCP_INVAL);
217 }
218 return rt;
219}
220
221target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
222{
223 target_ulong rt = 0;
224
225 if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
226 helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
227 POWERPC_EXCP_INVAL);
228 }
229 return rt;
230}
9d7c3f4a
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231
232/*
233 * 64-bit hash table MMU handling
234 */
235
9d7c3f4a
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236#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
237
496272a7
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238static int ppc_hash64_pp_check(int key, int pp, int nx)
239{
240 int access;
241
242 /* Compute access rights */
243 /* When pp is 4, 5 or 7, the result is undefined. Set it to noaccess */
244 access = 0;
245 if (key == 0) {
246 switch (pp) {
247 case 0x0:
248 case 0x1:
249 case 0x2:
250 access |= PAGE_WRITE;
251 /* No break here */
252 case 0x3:
253 case 0x6:
254 access |= PAGE_READ;
255 break;
256 }
257 } else {
258 switch (pp) {
259 case 0x0:
260 case 0x6:
261 access = 0;
262 break;
263 case 0x1:
264 case 0x3:
265 access = PAGE_READ;
266 break;
267 case 0x2:
268 access = PAGE_READ | PAGE_WRITE;
269 break;
270 }
271 }
272 if (nx == 0) {
273 access |= PAGE_EXEC;
274 }
275
276 return access;
277}
278
279static int ppc_hash64_check_prot(int prot, int rw, int access_type)
280{
281 int ret;
282
283 if (access_type == ACCESS_CODE) {
284 if (prot & PAGE_EXEC) {
285 ret = 0;
286 } else {
287 ret = -2;
288 }
289 } else if (rw) {
290 if (prot & PAGE_WRITE) {
291 ret = 0;
292 } else {
293 ret = -2;
294 }
295 } else {
296 if (prot & PAGE_READ) {
297 ret = 0;
298 } else {
299 ret = -2;
300 }
301 }
302
303 return ret;
304}
305
5dc68eb0 306static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0,
c69b6151 307 target_ulong pte1, int h, int rw, int type)
9d7c3f4a 308{
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309 target_ulong mmask;
310 int access, ret, pp;
9d7c3f4a
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311
312 ret = -1;
313 /* Check validity and table match */
d5aea6f3 314 if ((pte0 & HPTE64_V_VALID) && (h == !!(pte0 & HPTE64_V_SECONDARY))) {
9d7c3f4a 315 /* Check vsid & api */
9d7c3f4a 316 mmask = PTE64_CHECK_MASK;
d5aea6f3
DG
317 pp = (pte1 & HPTE64_R_PP) | ((pte1 & HPTE64_R_PP0) >> 61);
318 /* No execute if either noexec or guarded bits set */
319 ctx->nx = (pte1 & HPTE64_R_N) || (pte1 & HPTE64_R_G);
320 if (HPTE64_V_COMPARE(pte0, ctx->ptem)) {
9d7c3f4a
DG
321 if (ctx->raddr != (hwaddr)-1ULL) {
322 /* all matches should have equal RPN, WIMG & PP */
323 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
324 qemu_log("Bad RPN/WIMG/PP\n");
325 return -3;
326 }
327 }
328 /* Compute access rights */
496272a7 329 access = ppc_hash64_pp_check(ctx->key, pp, ctx->nx);
9d7c3f4a
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330 /* Keep the matching PTE informations */
331 ctx->raddr = pte1;
332 ctx->prot = access;
496272a7 333 ret = ppc_hash64_check_prot(ctx->prot, rw, type);
9d7c3f4a
DG
334 if (ret == 0) {
335 /* Access granted */
336 LOG_MMU("PTE access granted !\n");
337 } else {
338 /* Access right violation */
339 LOG_MMU("PTE access rejected\n");
340 }
341 }
342 }
343
344 return ret;
345}
c69b6151 346
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347static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx,
348 target_ulong *pte1p,
496272a7
DG
349 int ret, int rw)
350{
351 int store = 0;
352
353 /* Update page flags */
d5aea6f3 354 if (!(*pte1p & HPTE64_R_R)) {
496272a7 355 /* Update accessed flag */
d5aea6f3 356 *pte1p |= HPTE64_R_R;
496272a7
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357 store = 1;
358 }
d5aea6f3 359 if (!(*pte1p & HPTE64_R_C)) {
496272a7
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360 if (rw == 1 && ret == 0) {
361 /* Update changed flag */
d5aea6f3 362 *pte1p |= HPTE64_R_C;
496272a7
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363 store = 1;
364 } else {
365 /* Force page fault for first write access */
366 ctx->prot &= ~PAGE_WRITE;
367 }
368 }
369
370 return store;
371}
372
c69b6151 373/* PTE table lookup */
5dc68eb0 374static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, int h,
0480884f 375 int rw, int type, int target_page_bits)
c69b6151
DG
376{
377 hwaddr pteg_off;
378 target_ulong pte0, pte1;
379 int i, good = -1;
380 int ret, r;
381
382 ret = -1; /* No entry found */
d5aea6f3
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383 pteg_off = (ctx->hash[h] * HASH_PTEG_SIZE_64) & env->htab_mask;
384 for (i = 0; i < HPTES_PER_GROUP; i++) {
dffdaf61
DG
385 pte0 = ppc_hash64_load_hpte0(env, pteg_off + i*HASH_PTE_SIZE_64);
386 pte1 = ppc_hash64_load_hpte1(env, pteg_off + i*HASH_PTE_SIZE_64);
c69b6151
DG
387
388 r = pte64_check(ctx, pte0, pte1, h, rw, type);
389 LOG_MMU("Load pte from %016" HWADDR_PRIx " => " TARGET_FMT_lx " "
390 TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
391 pteg_off + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
392 (int)((pte0 >> 1) & 1), ctx->ptem);
393 switch (r) {
394 case -3:
395 /* PTE inconsistency */
396 return -1;
397 case -2:
398 /* Access violation */
399 ret = -2;
400 good = i;
401 break;
402 case -1:
403 default:
404 /* No PTE match */
405 break;
406 case 0:
407 /* access granted */
408 /* XXX: we should go on looping to check all PTEs consistency
409 * but if we can speed-up the whole thing as the
410 * result would be undefined if PTEs are not consistent.
411 */
412 ret = 0;
413 good = i;
414 goto done;
415 }
416 }
417 if (good != -1) {
418 done:
419 LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
420 ctx->raddr, ctx->prot, ret);
421 /* Update page flags */
422 pte1 = ctx->raddr;
496272a7 423 if (ppc_hash64_pte_update_flags(ctx, &pte1, ret, rw) == 1) {
dffdaf61 424 ppc_hash64_store_hpte1(env, pteg_off + good * HASH_PTE_SIZE_64, pte1);
c69b6151
DG
425 }
426 }
427
428 /* We have a TLB that saves 4K pages, so let's
429 * split a huge page to 4k chunks */
430 if (target_page_bits != TARGET_PAGE_BITS) {
431 ctx->raddr |= (ctx->eaddr & ((1 << target_page_bits) - 1))
432 & TARGET_PAGE_MASK;
433 }
434 return ret;
435}
0480884f 436
5dc68eb0 437static int get_segment64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
629bd516 438 target_ulong eaddr, int rw, int type)
0480884f
DG
439{
440 hwaddr hash;
441 target_ulong vsid;
442 int pr, target_page_bits;
443 int ret, ret2;
444
445 pr = msr_pr;
446 ctx->eaddr = eaddr;
447 ppc_slb_t *slb;
448 target_ulong pageaddr;
449 int segment_bits;
450
451 LOG_MMU("Check SLBs\n");
452 slb = slb_lookup(env, eaddr);
453 if (!slb) {
454 return -5;
455 }
456
457 if (slb->vsid & SLB_VSID_B) {
458 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
459 segment_bits = 40;
460 } else {
461 vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
462 segment_bits = 28;
463 }
464
465 target_page_bits = (slb->vsid & SLB_VSID_L)
466 ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
467 ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)
468 : (slb->vsid & SLB_VSID_KS));
469 ctx->nx = !!(slb->vsid & SLB_VSID_N);
470
471 pageaddr = eaddr & ((1ULL << segment_bits)
472 - (1ULL << target_page_bits));
473 if (slb->vsid & SLB_VSID_B) {
474 hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits);
475 } else {
476 hash = vsid ^ (pageaddr >> target_page_bits);
477 }
478 /* Only 5 bits of the page index are used in the AVPN */
479 ctx->ptem = (slb->vsid & SLB_VSID_PTEM) |
480 ((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
481
482 LOG_MMU("pte segment: key=%d nx %d vsid " TARGET_FMT_lx "\n",
483 ctx->key, ctx->nx, vsid);
484 ret = -1;
485
486 /* Check if instruction fetch is allowed, if needed */
487 if (type != ACCESS_CODE || ctx->nx == 0) {
488 /* Page address translation */
489 LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
490 " hash " TARGET_FMT_plx "\n",
491 env->htab_base, env->htab_mask, hash);
492 ctx->hash[0] = hash;
493 ctx->hash[1] = ~hash;
494
495 /* Initialize real address with an invalid value */
496 ctx->raddr = (hwaddr)-1ULL;
497 LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
498 " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
499 " hash=" TARGET_FMT_plx "\n",
500 env->htab_base, env->htab_mask, vsid, ctx->ptem,
501 ctx->hash[0]);
502 /* Primary table lookup */
503 ret = find_pte64(env, ctx, 0, rw, type, target_page_bits);
504 if (ret < 0) {
505 /* Secondary table lookup */
506 LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
507 " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
508 " hash=" TARGET_FMT_plx "\n", env->htab_base,
509 env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
510 ret2 = find_pte64(env, ctx, 1, rw, type, target_page_bits);
511 if (ret2 != -1) {
512 ret = ret2;
513 }
514 }
515 } else {
516 LOG_MMU("No access allowed\n");
517 ret = -3;
518 }
519
520 return ret;
521}
629bd516 522
5dc68eb0
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523static int ppc_hash64_get_physical_address(CPUPPCState *env,
524 struct mmu_ctx_hash64 *ctx,
f2ad6be8
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525 target_ulong eaddr, int rw,
526 int access_type)
629bd516
DG
527{
528 bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
529 || (access_type != ACCESS_CODE && msr_dr == 0);
530
531 if (real_mode) {
532 ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
533 ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
534 return 0;
535 } else {
536 return get_segment64(env, ctx, eaddr, rw, access_type);
537 }
538}
25de24ab 539
f2ad6be8
DG
540hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
541{
5dc68eb0 542 struct mmu_ctx_hash64 ctx;
f2ad6be8
DG
543
544 if (unlikely(ppc_hash64_get_physical_address(env, &ctx, addr, 0, ACCESS_INT)
545 != 0)) {
546 return -1;
547 }
548
549 return ctx.raddr & TARGET_PAGE_MASK;
550}
551
25de24ab
DG
552int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
553 int mmu_idx)
554{
5dc68eb0 555 struct mmu_ctx_hash64 ctx;
25de24ab
DG
556 int access_type;
557 int ret = 0;
558
559 if (rw == 2) {
560 /* code access */
561 rw = 0;
562 access_type = ACCESS_CODE;
563 } else {
564 /* data access */
565 access_type = env->access_type;
566 }
567 ret = ppc_hash64_get_physical_address(env, &ctx, address, rw, access_type);
568 if (ret == 0) {
569 tlb_set_page(env, address & TARGET_PAGE_MASK,
570 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
571 mmu_idx, TARGET_PAGE_SIZE);
572 ret = 0;
573 } else if (ret < 0) {
574 LOG_MMU_STATE(env);
575 if (access_type == ACCESS_CODE) {
576 switch (ret) {
577 case -1:
578 env->exception_index = POWERPC_EXCP_ISI;
579 env->error_code = 0x40000000;
580 break;
581 case -2:
582 /* Access rights violation */
583 env->exception_index = POWERPC_EXCP_ISI;
584 env->error_code = 0x08000000;
585 break;
586 case -3:
587 /* No execute protection violation */
588 env->exception_index = POWERPC_EXCP_ISI;
589 env->error_code = 0x10000000;
590 break;
591 case -5:
592 /* No match in segment table */
593 env->exception_index = POWERPC_EXCP_ISEG;
594 env->error_code = 0;
595 break;
596 }
597 } else {
598 switch (ret) {
599 case -1:
600 /* No matches in page tables or TLB */
601 env->exception_index = POWERPC_EXCP_DSI;
602 env->error_code = 0;
603 env->spr[SPR_DAR] = address;
604 if (rw == 1) {
605 env->spr[SPR_DSISR] = 0x42000000;
606 } else {
607 env->spr[SPR_DSISR] = 0x40000000;
608 }
609 break;
610 case -2:
611 /* Access rights violation */
612 env->exception_index = POWERPC_EXCP_DSI;
613 env->error_code = 0;
614 env->spr[SPR_DAR] = address;
615 if (rw == 1) {
616 env->spr[SPR_DSISR] = 0x0A000000;
617 } else {
618 env->spr[SPR_DSISR] = 0x08000000;
619 }
620 break;
621 case -5:
622 /* No match in segment table */
623 env->exception_index = POWERPC_EXCP_DSEG;
624 env->error_code = 0;
625 env->spr[SPR_DAR] = address;
626 break;
627 }
628 }
629#if 0
630 printf("%s: set exception to %d %02x\n", __func__,
631 env->exception, env->error_code);
632#endif
633 ret = 1;
634 }
635
636 return ret;
637}