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PowerPC 601 need specific callbacks for its BATs setup.
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CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation micro-operations for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
a541f297
FB
21//#define DEBUG_OP
22
79aceca5
FB
23#include "config.h"
24#include "exec.h"
603fccce 25#include "host-utils.h"
0411a972 26#include "helper_regs.h"
76a66253 27#include "op_helper.h"
79aceca5 28
28b6751f
FB
29#define REG 0
30#include "op_template.h"
31
32#define REG 1
33#include "op_template.h"
34
35#define REG 2
36#include "op_template.h"
37
38#define REG 3
39#include "op_template.h"
40
41#define REG 4
42#include "op_template.h"
43
44#define REG 5
45#include "op_template.h"
46
47#define REG 6
48#include "op_template.h"
49
50#define REG 7
51#include "op_template.h"
52
53#define REG 8
54#include "op_template.h"
55
56#define REG 9
57#include "op_template.h"
58
59#define REG 10
60#include "op_template.h"
61
62#define REG 11
63#include "op_template.h"
64
65#define REG 12
66#include "op_template.h"
67
68#define REG 13
69#include "op_template.h"
70
71#define REG 14
72#include "op_template.h"
73
74#define REG 15
75#include "op_template.h"
76
77#define REG 16
78#include "op_template.h"
79
80#define REG 17
81#include "op_template.h"
82
83#define REG 18
84#include "op_template.h"
85
86#define REG 19
87#include "op_template.h"
88
89#define REG 20
90#include "op_template.h"
91
92#define REG 21
93#include "op_template.h"
94
95#define REG 22
96#include "op_template.h"
97
98#define REG 23
99#include "op_template.h"
100
101#define REG 24
102#include "op_template.h"
103
104#define REG 25
105#include "op_template.h"
106
107#define REG 26
108#include "op_template.h"
109
110#define REG 27
111#include "op_template.h"
112
113#define REG 28
114#include "op_template.h"
115
116#define REG 29
117#include "op_template.h"
118
119#define REG 30
120#include "op_template.h"
121
122#define REG 31
123#include "op_template.h"
124
a496775f
JM
125void OPPROTO op_print_mem_EA (void)
126{
127 do_print_mem_EA(T0);
128 RETURN();
129}
130
3fc6c082 131/* PowerPC state maintenance operations */
79aceca5 132/* set_Rc0 */
36081602 133void OPPROTO op_set_Rc0 (void)
79aceca5 134{
966439a6 135 env->crf[0] = T0 | xer_so;
79aceca5
FB
136 RETURN();
137}
138
9a64fbe4 139/* Constants load */
76a66253
JM
140void OPPROTO op_reset_T0 (void)
141{
142 T0 = 0;
143 RETURN();
144}
145
36081602 146void OPPROTO op_set_T0 (void)
79aceca5 147{
d9bce9d9 148 T0 = (uint32_t)PARAM1;
79aceca5
FB
149 RETURN();
150}
151
d9bce9d9
JM
152#if defined(TARGET_PPC64)
153void OPPROTO op_set_T0_64 (void)
154{
155 T0 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
156 RETURN();
157}
158#endif
159
36081602 160void OPPROTO op_set_T1 (void)
79aceca5 161{
d9bce9d9
JM
162 T1 = (uint32_t)PARAM1;
163 RETURN();
164}
165
166#if defined(TARGET_PPC64)
167void OPPROTO op_set_T1_64 (void)
168{
169 T1 = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
79aceca5
FB
170 RETURN();
171}
d9bce9d9 172#endif
79aceca5 173
76a66253 174#if 0 // unused
36081602 175void OPPROTO op_set_T2 (void)
79aceca5 176{
2f401176 177 T2 = (uint32_t)PARAM1;
79aceca5
FB
178 RETURN();
179}
76a66253 180#endif
79aceca5 181
76a66253 182void OPPROTO op_move_T1_T0 (void)
79aceca5 183{
76a66253
JM
184 T1 = T0;
185 RETURN();
9a64fbe4
FB
186}
187
d9bce9d9
JM
188void OPPROTO op_move_T2_T0 (void)
189{
190 T2 = T0;
191 RETURN();
192}
193
76a66253 194/* Generate exceptions */
36081602 195void OPPROTO op_raise_exception_err (void)
9a64fbe4 196{
36081602 197 do_raise_exception_err(PARAM1, PARAM2);
9a64fbe4
FB
198}
199
36081602 200void OPPROTO op_update_nip (void)
9a64fbe4 201{
d9bce9d9 202 env->nip = (uint32_t)PARAM1;
76a66253 203 RETURN();
9a64fbe4
FB
204}
205
d9bce9d9
JM
206#if defined(TARGET_PPC64)
207void OPPROTO op_update_nip_64 (void)
208{
209 env->nip = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
210 RETURN();
211}
212#endif
213
36081602 214void OPPROTO op_debug (void)
ea4e754f
FB
215{
216 do_raise_exception(EXCP_DEBUG);
217}
218
36081602 219void OPPROTO op_exit_tb (void)
9a64fbe4 220{
76a66253 221 EXIT_TB();
9a64fbe4
FB
222}
223
76a66253 224/* Load/store special registers */
36081602 225void OPPROTO op_load_cr (void)
9a64fbe4 226{
76a66253 227 do_load_cr();
79aceca5
FB
228 RETURN();
229}
230
36081602 231void OPPROTO op_store_cr (void)
79aceca5 232{
36081602 233 do_store_cr(PARAM1);
79aceca5
FB
234 RETURN();
235}
236
76a66253 237void OPPROTO op_load_cro (void)
79aceca5 238{
76a66253 239 T0 = env->crf[PARAM1];
79aceca5
FB
240 RETURN();
241}
242
76a66253 243void OPPROTO op_store_cro (void)
79aceca5 244{
76a66253 245 env->crf[PARAM1] = T0;
79aceca5
FB
246 RETURN();
247}
248
36081602 249void OPPROTO op_load_xer_cr (void)
79aceca5
FB
250{
251 T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1);
252 RETURN();
253}
254
36081602 255void OPPROTO op_clear_xer_ov (void)
79aceca5
FB
256{
257 xer_so = 0;
258 xer_ov = 0;
e864cabd
JM
259 RETURN();
260}
261
36081602 262void OPPROTO op_clear_xer_ca (void)
e864cabd 263{
79aceca5
FB
264 xer_ca = 0;
265 RETURN();
266}
267
36081602 268void OPPROTO op_load_xer_bc (void)
79aceca5 269{
9a64fbe4 270 T1 = xer_bc;
79aceca5
FB
271 RETURN();
272}
273
76a66253
JM
274void OPPROTO op_store_xer_bc (void)
275{
276 xer_bc = T0;
277 RETURN();
278}
279
36081602 280void OPPROTO op_load_xer (void)
79aceca5 281{
0411a972 282 T0 = hreg_load_xer(env);
79aceca5
FB
283 RETURN();
284}
285
36081602 286void OPPROTO op_store_xer (void)
79aceca5 287{
0411a972 288 hreg_store_xer(env, T0);
76a66253
JM
289 RETURN();
290}
291
c80f84e3
JM
292#if defined(TARGET_PPC64)
293void OPPROTO op_store_pri (void)
294{
295 do_store_pri(PARAM1);
296 RETURN();
297}
298#endif
299
76a66253
JM
300#if !defined(CONFIG_USER_ONLY)
301/* Segment registers load and store */
36081602 302void OPPROTO op_load_sr (void)
76a66253 303{
36081602 304 T0 = env->sr[T1];
76a66253
JM
305 RETURN();
306}
307
36081602 308void OPPROTO op_store_sr (void)
76a66253
JM
309{
310 do_store_sr(env, T1, T0);
311 RETURN();
312}
313
12de9a39
JM
314#if defined(TARGET_PPC64)
315void OPPROTO op_load_slb (void)
316{
317 T0 = ppc_load_slb(env, T1);
318 RETURN();
319}
320
321void OPPROTO op_store_slb (void)
322{
323 ppc_store_slb(env, T1, T0);
324 RETURN();
325}
326#endif /* defined(TARGET_PPC64) */
327
36081602 328void OPPROTO op_load_sdr1 (void)
76a66253 329{
36081602 330 T0 = env->sdr1;
76a66253
JM
331 RETURN();
332}
333
36081602 334void OPPROTO op_store_sdr1 (void)
76a66253
JM
335{
336 do_store_sdr1(env, T0);
79aceca5
FB
337 RETURN();
338}
339
d9bce9d9
JM
340#if defined (TARGET_PPC64)
341void OPPROTO op_load_asr (void)
342{
343 T0 = env->asr;
344 RETURN();
345}
346
347void OPPROTO op_store_asr (void)
348{
349 ppc_store_asr(env, T0);
350 RETURN();
351}
352#endif
353
36081602 354void OPPROTO op_load_msr (void)
79aceca5 355{
0411a972 356 T0 = env->msr;
79aceca5
FB
357 RETURN();
358}
359
36081602 360void OPPROTO op_store_msr (void)
79aceca5 361{
0411a972 362 do_store_msr();
9a64fbe4
FB
363 RETURN();
364}
d9bce9d9 365
0411a972
JM
366#if defined (TARGET_PPC64)
367void OPPROTO op_store_msr_32 (void)
be147d08 368{
0411a972
JM
369 T0 = (env->msr & ~0xFFFFFFFFULL) | (T0 & 0xFFFFFFFF);
370 do_store_msr();
be147d08
JM
371 RETURN();
372}
0411a972 373#endif
be147d08 374
0411a972 375void OPPROTO op_update_riee (void)
d9bce9d9 376{
0411a972
JM
377 /* We don't call do_store_msr here as we won't trigger
378 * any special case nor change hflags
379 */
380 T0 &= (1 << MSR_RI) | (1 << MSR_EE);
381 env->msr &= ~(1 << MSR_RI) | (1 << MSR_EE);
382 env->msr |= T0;
d9bce9d9
JM
383 RETURN();
384}
385#endif
9a64fbe4
FB
386
387/* SPR */
a496775f
JM
388void OPPROTO op_load_spr (void)
389{
390 T0 = env->spr[PARAM1];
391 RETURN();
392}
393
394void OPPROTO op_store_spr (void)
395{
396 env->spr[PARAM1] = T0;
397 RETURN();
398}
399
400void OPPROTO op_load_dump_spr (void)
401{
402 T0 = ppc_load_dump_spr(PARAM1);
403 RETURN();
404}
405
406void OPPROTO op_store_dump_spr (void)
9a64fbe4 407{
a496775f 408 ppc_store_dump_spr(PARAM1, T0);
9a64fbe4
FB
409 RETURN();
410}
411
a496775f 412void OPPROTO op_mask_spr (void)
9a64fbe4 413{
a496775f 414 env->spr[PARAM1] &= ~T0;
79aceca5
FB
415 RETURN();
416}
417
36081602 418void OPPROTO op_load_lr (void)
79aceca5 419{
36081602 420 T0 = env->lr;
9a64fbe4
FB
421 RETURN();
422}
423
36081602 424void OPPROTO op_store_lr (void)
9a64fbe4 425{
36081602 426 env->lr = T0;
9a64fbe4
FB
427 RETURN();
428}
429
36081602 430void OPPROTO op_load_ctr (void)
9a64fbe4 431{
36081602 432 T0 = env->ctr;
9a64fbe4
FB
433 RETURN();
434}
435
36081602 436void OPPROTO op_store_ctr (void)
9a64fbe4 437{
36081602 438 env->ctr = T0;
9a64fbe4
FB
439 RETURN();
440}
441
36081602 442void OPPROTO op_load_tbl (void)
9a64fbe4 443{
36081602 444 T0 = cpu_ppc_load_tbl(env);
9a64fbe4
FB
445 RETURN();
446}
447
36081602 448void OPPROTO op_load_tbu (void)
9a64fbe4 449{
36081602 450 T0 = cpu_ppc_load_tbu(env);
9a64fbe4
FB
451 RETURN();
452}
453
a062e36c
JM
454void OPPROTO op_load_atbl (void)
455{
456 T0 = cpu_ppc_load_atbl(env);
457 RETURN();
458}
459
460void OPPROTO op_load_atbu (void)
461{
462 T0 = cpu_ppc_load_atbu(env);
463 RETURN();
464}
465
76a66253 466#if !defined(CONFIG_USER_ONLY)
36081602 467void OPPROTO op_store_tbl (void)
9a64fbe4 468{
36081602 469 cpu_ppc_store_tbl(env, T0);
79aceca5
FB
470 RETURN();
471}
472
36081602 473void OPPROTO op_store_tbu (void)
9a64fbe4 474{
36081602 475 cpu_ppc_store_tbu(env, T0);
9a64fbe4
FB
476 RETURN();
477}
478
a062e36c
JM
479void OPPROTO op_store_atbl (void)
480{
481 cpu_ppc_store_atbl(env, T0);
482 RETURN();
483}
484
485void OPPROTO op_store_atbu (void)
486{
487 cpu_ppc_store_atbu(env, T0);
488 RETURN();
489}
490
36081602 491void OPPROTO op_load_decr (void)
9a64fbe4 492{
36081602 493 T0 = cpu_ppc_load_decr(env);
76a66253
JM
494 RETURN();
495}
9fddaa0c 496
36081602 497void OPPROTO op_store_decr (void)
9fddaa0c 498{
36081602 499 cpu_ppc_store_decr(env, T0);
9a64fbe4
FB
500 RETURN();
501}
502
36081602 503void OPPROTO op_load_ibat (void)
9a64fbe4 504{
36081602 505 T0 = env->IBAT[PARAM1][PARAM2];
76a66253 506 RETURN();
9a64fbe4
FB
507}
508
76a66253 509void OPPROTO op_store_ibatu (void)
9a64fbe4 510{
3fc6c082
FB
511 do_store_ibatu(env, PARAM1, T0);
512 RETURN();
513}
514
76a66253 515void OPPROTO op_store_ibatl (void)
3fc6c082
FB
516{
517#if 1
518 env->IBAT[1][PARAM1] = T0;
519#else
520 do_store_ibatl(env, PARAM1, T0);
521#endif
522 RETURN();
9a64fbe4
FB
523}
524
36081602 525void OPPROTO op_load_dbat (void)
9a64fbe4 526{
36081602 527 T0 = env->DBAT[PARAM1][PARAM2];
76a66253 528 RETURN();
9a64fbe4
FB
529}
530
76a66253 531void OPPROTO op_store_dbatu (void)
3fc6c082
FB
532{
533 do_store_dbatu(env, PARAM1, T0);
534 RETURN();
535}
536
76a66253 537void OPPROTO op_store_dbatl (void)
9a64fbe4 538{
3fc6c082
FB
539#if 1
540 env->DBAT[1][PARAM1] = T0;
541#else
542 do_store_dbatl(env, PARAM1, T0);
543#endif
544 RETURN();
9a64fbe4 545}
76a66253 546#endif /* !defined(CONFIG_USER_ONLY) */
9a64fbe4 547
fb0eaffc 548/* FPSCR */
7c58044c
JM
549#ifdef CONFIG_SOFTFLOAT
550void OPPROTO op_reset_fpstatus (void)
fb0eaffc 551{
7c58044c 552 env->fp_status.float_exception_flags = 0;
fb0eaffc
FB
553 RETURN();
554}
7c58044c 555#endif
fb0eaffc 556
7c58044c 557void OPPROTO op_compute_fprf (void)
fb0eaffc 558{
7c58044c
JM
559 do_compute_fprf(PARAM1);
560 RETURN();
561}
562
563#ifdef CONFIG_SOFTFLOAT
564void OPPROTO op_float_check_status (void)
565{
566 do_float_check_status();
567 RETURN();
568}
569#else
570void OPPROTO op_float_check_status (void)
571{
572 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
573 (env->error_code & POWERPC_EXCP_FP)) {
574 /* Differred floating-point exception after target FPR update */
575 if (msr_fe0 != 0 || msr_fe1 != 0)
576 do_raise_exception_err(env->exception_index, env->error_code);
577 }
fb0eaffc
FB
578 RETURN();
579}
7c58044c
JM
580#endif
581
582#if defined(WORDS_BIGENDIAN)
583#define WORD0 0
584#define WORD1 1
585#else
586#define WORD0 1
587#define WORD1 0
588#endif
589void OPPROTO op_load_fpscr_FT0 (void)
590{
591 /* The 32 MSB of the target fpr are undefined.
592 * They'll be zero...
593 */
594 union {
595 float64 d;
596 struct {
597 uint32_t u[2];
598 } s;
599 } u;
600
601 u.s.u[WORD0] = 0;
602 u.s.u[WORD1] = env->fpscr;
603 FT0 = u.d;
604 RETURN();
605}
606
607void OPPROTO op_set_FT0 (void)
608{
609 union {
610 float64 d;
611 struct {
612 uint32_t u[2];
613 } s;
614 } u;
615
616 u.s.u[WORD0] = 0;
617 u.s.u[WORD1] = PARAM1;
618 FT0 = u.d;
619 RETURN();
620}
621#undef WORD0
622#undef WORD1
fb0eaffc 623
7c58044c 624void OPPROTO op_load_fpscr_T0 (void)
fb0eaffc 625{
7c58044c
JM
626 T0 = (env->fpscr >> PARAM1) & 0xF;
627 RETURN();
628}
629
630void OPPROTO op_load_fpcc (void)
631{
632 T0 = fpscr_fpcc;
633 RETURN();
634}
635
636void OPPROTO op_fpscr_resetbit (void)
637{
638 env->fpscr &= PARAM1;
639 RETURN();
640}
641
642void OPPROTO op_fpscr_setbit (void)
643{
644 do_fpscr_setbit(PARAM1);
645 RETURN();
646}
647
648void OPPROTO op_store_fpscr (void)
649{
650 do_store_fpscr(PARAM1);
fb0eaffc
FB
651 RETURN();
652}
653
79aceca5 654/* Branch */
36081602 655#define EIP env->nip
9a64fbe4 656
36081602 657void OPPROTO op_setlr (void)
e98a6e40 658{
36081602 659 env->lr = (uint32_t)PARAM1;
76a66253 660 RETURN();
e98a6e40
FB
661}
662
d9bce9d9
JM
663#if defined (TARGET_PPC64)
664void OPPROTO op_setlr_64 (void)
665{
36081602 666 env->lr = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
d9bce9d9
JM
667 RETURN();
668}
669#endif
670
36081602 671void OPPROTO op_goto_tb0 (void)
e98a6e40 672{
c53be334
FB
673 GOTO_TB(op_goto_tb0, PARAM1, 0);
674}
675
36081602 676void OPPROTO op_goto_tb1 (void)
c53be334
FB
677{
678 GOTO_TB(op_goto_tb1, PARAM1, 1);
e98a6e40
FB
679}
680
d9bce9d9 681void OPPROTO op_b_T1 (void)
e98a6e40 682{
36081602 683 env->nip = (uint32_t)(T1 & ~3);
76a66253 684 RETURN();
e98a6e40
FB
685}
686
d9bce9d9
JM
687#if defined (TARGET_PPC64)
688void OPPROTO op_b_T1_64 (void)
689{
36081602 690 env->nip = (uint64_t)(T1 & ~3);
d9bce9d9
JM
691 RETURN();
692}
693#endif
694
36081602 695void OPPROTO op_jz_T0 (void)
e98a6e40 696{
c53be334
FB
697 if (!T0)
698 GOTO_LABEL_PARAM(1);
e98a6e40
FB
699 RETURN();
700}
701
d9bce9d9 702void OPPROTO op_btest_T1 (void)
e98a6e40
FB
703{
704 if (T0) {
36081602 705 env->nip = (uint32_t)(T1 & ~3);
e98a6e40 706 } else {
36081602 707 env->nip = (uint32_t)PARAM1;
e98a6e40
FB
708 }
709 RETURN();
710}
711
d9bce9d9
JM
712#if defined (TARGET_PPC64)
713void OPPROTO op_btest_T1_64 (void)
714{
715 if (T0) {
36081602 716 env->nip = (uint64_t)(T1 & ~3);
d9bce9d9 717 } else {
36081602 718 env->nip = ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
d9bce9d9
JM
719 }
720 RETURN();
721}
722#endif
723
36081602 724void OPPROTO op_movl_T1_ctr (void)
e98a6e40 725{
36081602 726 T1 = env->ctr;
76a66253 727 RETURN();
e98a6e40
FB
728}
729
36081602 730void OPPROTO op_movl_T1_lr (void)
e98a6e40 731{
36081602 732 T1 = env->lr;
76a66253 733 RETURN();
e98a6e40
FB
734}
735
736/* tests with result in T0 */
d9bce9d9
JM
737void OPPROTO op_test_ctr (void)
738{
36081602 739 T0 = (uint32_t)env->ctr;
d9bce9d9
JM
740 RETURN();
741}
e98a6e40 742
d9bce9d9
JM
743#if defined(TARGET_PPC64)
744void OPPROTO op_test_ctr_64 (void)
e98a6e40 745{
36081602 746 T0 = (uint64_t)env->ctr;
d9bce9d9
JM
747 RETURN();
748}
749#endif
750
751void OPPROTO op_test_ctr_true (void)
752{
36081602 753 T0 = ((uint32_t)env->ctr != 0 && (T0 & PARAM1) != 0);
76a66253 754 RETURN();
e98a6e40
FB
755}
756
d9bce9d9
JM
757#if defined(TARGET_PPC64)
758void OPPROTO op_test_ctr_true_64 (void)
e98a6e40 759{
36081602 760 T0 = ((uint64_t)env->ctr != 0 && (T0 & PARAM1) != 0);
76a66253 761 RETURN();
e98a6e40 762}
d9bce9d9 763#endif
e98a6e40 764
d9bce9d9 765void OPPROTO op_test_ctr_false (void)
e98a6e40 766{
36081602 767 T0 = ((uint32_t)env->ctr != 0 && (T0 & PARAM1) == 0);
76a66253 768 RETURN();
e98a6e40
FB
769}
770
d9bce9d9
JM
771#if defined(TARGET_PPC64)
772void OPPROTO op_test_ctr_false_64 (void)
e98a6e40 773{
36081602 774 T0 = ((uint64_t)env->ctr != 0 && (T0 & PARAM1) == 0);
76a66253 775 RETURN();
e98a6e40 776}
d9bce9d9
JM
777#endif
778
779void OPPROTO op_test_ctrz (void)
780{
36081602 781 T0 = ((uint32_t)env->ctr == 0);
d9bce9d9
JM
782 RETURN();
783}
784
785#if defined(TARGET_PPC64)
786void OPPROTO op_test_ctrz_64 (void)
787{
36081602 788 T0 = ((uint64_t)env->ctr == 0);
d9bce9d9
JM
789 RETURN();
790}
791#endif
792
793void OPPROTO op_test_ctrz_true (void)
794{
36081602 795 T0 = ((uint32_t)env->ctr == 0 && (T0 & PARAM1) != 0);
d9bce9d9
JM
796 RETURN();
797}
798
799#if defined(TARGET_PPC64)
800void OPPROTO op_test_ctrz_true_64 (void)
801{
36081602 802 T0 = ((uint64_t)env->ctr == 0 && (T0 & PARAM1) != 0);
d9bce9d9
JM
803 RETURN();
804}
805#endif
e98a6e40 806
d9bce9d9 807void OPPROTO op_test_ctrz_false (void)
e98a6e40 808{
36081602 809 T0 = ((uint32_t)env->ctr == 0 && (T0 & PARAM1) == 0);
76a66253 810 RETURN();
e98a6e40
FB
811}
812
d9bce9d9
JM
813#if defined(TARGET_PPC64)
814void OPPROTO op_test_ctrz_false_64 (void)
e98a6e40 815{
36081602 816 T0 = ((uint64_t)env->ctr == 0 && (T0 & PARAM1) == 0);
76a66253 817 RETURN();
e98a6e40 818}
d9bce9d9 819#endif
e98a6e40 820
36081602 821void OPPROTO op_test_true (void)
e98a6e40 822{
36081602 823 T0 = (T0 & PARAM1);
76a66253 824 RETURN();
e98a6e40
FB
825}
826
36081602 827void OPPROTO op_test_false (void)
e98a6e40 828{
36081602 829 T0 = ((T0 & PARAM1) == 0);
76a66253 830 RETURN();
e98a6e40 831}
79aceca5
FB
832
833/* CTR maintenance */
36081602 834void OPPROTO op_dec_ctr (void)
79aceca5 835{
36081602 836 env->ctr--;
79aceca5
FB
837 RETURN();
838}
839
840/*** Integer arithmetic ***/
841/* add */
36081602 842void OPPROTO op_add (void)
79aceca5
FB
843{
844 T0 += T1;
845 RETURN();
846}
847
d9bce9d9 848void OPPROTO op_check_addo (void)
79aceca5 849{
d9bce9d9
JM
850 if (likely(!(((uint32_t)T2 ^ (uint32_t)T1 ^ UINT32_MAX) &
851 ((uint32_t)T2 ^ (uint32_t)T0) & (1UL << 31)))) {
852 xer_ov = 0;
853 } else {
d9bce9d9 854 xer_ov = 1;
966439a6 855 xer_so = 1;
d9bce9d9 856 }
e864cabd 857 RETURN();
79aceca5
FB
858}
859
d9bce9d9
JM
860#if defined(TARGET_PPC64)
861void OPPROTO op_check_addo_64 (void)
79aceca5 862{
d9bce9d9 863 if (likely(!(((uint64_t)T2 ^ (uint64_t)T1 ^ UINT64_MAX) &
1698b741 864 ((uint64_t)T2 ^ (uint64_t)T0) & (1ULL << 63)))) {
d9bce9d9 865 xer_ov = 0;
79aceca5 866 } else {
d9bce9d9 867 xer_ov = 1;
966439a6 868 xer_so = 1;
d9bce9d9 869 }
e864cabd 870 RETURN();
d9bce9d9
JM
871}
872#endif
873
874/* add carrying */
875void OPPROTO op_check_addc (void)
876{
877 if (likely((uint32_t)T0 >= (uint32_t)T2)) {
79aceca5 878 xer_ca = 0;
d9bce9d9
JM
879 } else {
880 xer_ca = 1;
79aceca5
FB
881 }
882 RETURN();
883}
884
d9bce9d9
JM
885#if defined(TARGET_PPC64)
886void OPPROTO op_check_addc_64 (void)
79aceca5 887{
d9bce9d9
JM
888 if (likely((uint64_t)T0 >= (uint64_t)T2)) {
889 xer_ca = 0;
890 } else {
891 xer_ca = 1;
892 }
79aceca5
FB
893 RETURN();
894}
d9bce9d9 895#endif
79aceca5
FB
896
897/* add extended */
76a66253 898void OPPROTO op_adde (void)
79aceca5 899{
fdabc366 900 do_adde();
76a66253 901 RETURN();
79aceca5
FB
902}
903
d9bce9d9
JM
904#if defined(TARGET_PPC64)
905void OPPROTO op_adde_64 (void)
79aceca5 906{
d9bce9d9 907 do_adde_64();
79aceca5
FB
908 RETURN();
909}
d9bce9d9 910#endif
79aceca5
FB
911
912/* add immediate */
36081602 913void OPPROTO op_addi (void)
79aceca5 914{
36081602 915 T0 += (int32_t)PARAM1;
79aceca5
FB
916 RETURN();
917}
918
d9bce9d9
JM
919/* add to minus one extended */
920void OPPROTO op_add_me (void)
79aceca5 921{
d9bce9d9
JM
922 T0 += xer_ca + (-1);
923 if (likely((uint32_t)T1 != 0))
79aceca5 924 xer_ca = 1;
79aceca5
FB
925 RETURN();
926}
927
d9bce9d9
JM
928#if defined(TARGET_PPC64)
929void OPPROTO op_add_me_64 (void)
79aceca5 930{
79aceca5 931 T0 += xer_ca + (-1);
d9bce9d9 932 if (likely((uint64_t)T1 != 0))
79aceca5
FB
933 xer_ca = 1;
934 RETURN();
935}
d9bce9d9 936#endif
79aceca5 937
76a66253 938void OPPROTO op_addmeo (void)
79aceca5 939{
fdabc366 940 do_addmeo();
79aceca5
FB
941 RETURN();
942}
943
d9bce9d9
JM
944void OPPROTO op_addmeo_64 (void)
945{
946 do_addmeo();
947 RETURN();
948}
949
79aceca5 950/* add to zero extended */
d9bce9d9 951void OPPROTO op_add_ze (void)
79aceca5 952{
79aceca5 953 T0 += xer_ca;
79aceca5
FB
954 RETURN();
955}
956
d9bce9d9
JM
957/* divide word */
958void OPPROTO op_divw (void)
79aceca5 959{
d9bce9d9
JM
960 if (unlikely(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
961 (int32_t)T1 == 0)) {
962 T0 = (int32_t)((-1) * ((uint32_t)T0 >> 31));
963 } else {
964 T0 = (int32_t)T0 / (int32_t)T1;
965 }
79aceca5
FB
966 RETURN();
967}
968
d9bce9d9
JM
969#if defined(TARGET_PPC64)
970void OPPROTO op_divd (void)
79aceca5 971{
d9bce9d9
JM
972 if (unlikely(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1) ||
973 (int64_t)T1 == 0)) {
974 T0 = (int64_t)((-1ULL) * ((uint64_t)T0 >> 63));
79aceca5 975 } else {
d9bce9d9 976 T0 = (int64_t)T0 / (int64_t)T1;
79aceca5
FB
977 }
978 RETURN();
979}
d9bce9d9 980#endif
79aceca5 981
76a66253 982void OPPROTO op_divwo (void)
79aceca5 983{
fdabc366 984 do_divwo();
79aceca5
FB
985 RETURN();
986}
987
d9bce9d9
JM
988#if defined(TARGET_PPC64)
989void OPPROTO op_divdo (void)
990{
991 do_divdo();
992 RETURN();
993}
994#endif
995
79aceca5 996/* divide word unsigned */
d9bce9d9
JM
997void OPPROTO op_divwu (void)
998{
999 if (unlikely(T1 == 0)) {
1000 T0 = 0;
1001 } else {
1002 T0 = (uint32_t)T0 / (uint32_t)T1;
1003 }
1004 RETURN();
1005}
1006
1007#if defined(TARGET_PPC64)
1008void OPPROTO op_divdu (void)
79aceca5 1009{
d9bce9d9 1010 if (unlikely(T1 == 0)) {
79aceca5
FB
1011 T0 = 0;
1012 } else {
1013 T0 /= T1;
1014 }
1015 RETURN();
1016}
d9bce9d9 1017#endif
79aceca5 1018
76a66253 1019void OPPROTO op_divwuo (void)
79aceca5 1020{
fdabc366 1021 do_divwuo();
79aceca5
FB
1022 RETURN();
1023}
1024
d9bce9d9
JM
1025#if defined(TARGET_PPC64)
1026void OPPROTO op_divduo (void)
1027{
1028 do_divduo();
1029 RETURN();
1030}
1031#endif
1032
79aceca5 1033/* multiply high word */
d9bce9d9 1034void OPPROTO op_mulhw (void)
79aceca5 1035{
d9bce9d9 1036 T0 = ((int64_t)((int32_t)T0) * (int64_t)((int32_t)T1)) >> 32;
79aceca5
FB
1037 RETURN();
1038}
1039
d9bce9d9
JM
1040#if defined(TARGET_PPC64)
1041void OPPROTO op_mulhd (void)
1042{
1043 uint64_t tl, th;
1044
9d901a20 1045 muls64(&tl, &th, T0, T1);
d9bce9d9
JM
1046 T0 = th;
1047 RETURN();
1048}
1049#endif
1050
79aceca5 1051/* multiply high word unsigned */
d9bce9d9 1052void OPPROTO op_mulhwu (void)
79aceca5 1053{
d9bce9d9 1054 T0 = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1) >> 32;
79aceca5
FB
1055 RETURN();
1056}
1057
d9bce9d9
JM
1058#if defined(TARGET_PPC64)
1059void OPPROTO op_mulhdu (void)
1060{
1061 uint64_t tl, th;
1062
9d901a20 1063 mulu64(&tl, &th, T0, T1);
d9bce9d9
JM
1064 T0 = th;
1065 RETURN();
1066}
1067#endif
1068
79aceca5 1069/* multiply low immediate */
36081602 1070void OPPROTO op_mulli (void)
79aceca5 1071{
d9bce9d9 1072 T0 = ((int32_t)T0 * (int32_t)PARAM1);
79aceca5
FB
1073 RETURN();
1074}
1075
1076/* multiply low word */
36081602 1077void OPPROTO op_mullw (void)
d9bce9d9
JM
1078{
1079 T0 = (int32_t)(T0 * T1);
1080 RETURN();
1081}
1082
1083#if defined(TARGET_PPC64)
1084void OPPROTO op_mulld (void)
79aceca5
FB
1085{
1086 T0 *= T1;
1087 RETURN();
1088}
d9bce9d9 1089#endif
79aceca5 1090
76a66253 1091void OPPROTO op_mullwo (void)
79aceca5 1092{
fdabc366 1093 do_mullwo();
79aceca5
FB
1094 RETURN();
1095}
1096
d9bce9d9
JM
1097#if defined(TARGET_PPC64)
1098void OPPROTO op_mulldo (void)
1099{
1100 do_mulldo();
1101 RETURN();
1102}
1103#endif
1104
79aceca5 1105/* negate */
d9bce9d9 1106void OPPROTO op_neg (void)
79aceca5 1107{
d9bce9d9
JM
1108 if (likely(T0 != INT32_MIN)) {
1109 T0 = -(int32_t)T0;
79aceca5
FB
1110 }
1111 RETURN();
1112}
1113
d9bce9d9
JM
1114#if defined(TARGET_PPC64)
1115void OPPROTO op_neg_64 (void)
1116{
1117 if (likely(T0 != INT64_MIN)) {
1118 T0 = -(int64_t)T0;
1119 }
1120 RETURN();
1121}
1122#endif
1123
76a66253 1124void OPPROTO op_nego (void)
79aceca5 1125{
fdabc366 1126 do_nego();
79aceca5
FB
1127 RETURN();
1128}
1129
d9bce9d9
JM
1130#if defined(TARGET_PPC64)
1131void OPPROTO op_nego_64 (void)
1132{
1133 do_nego_64();
1134 RETURN();
1135}
1136#endif
1137
0cfec834 1138/* subtract from */
36081602 1139void OPPROTO op_subf (void)
79aceca5
FB
1140{
1141 T0 = T1 - T0;
1142 RETURN();
1143}
1144
d9bce9d9
JM
1145void OPPROTO op_check_subfo (void)
1146{
1147 if (likely(!(((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1148 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)))) {
1149 xer_ov = 0;
1150 } else {
d9bce9d9 1151 xer_ov = 1;
966439a6 1152 xer_so = 1;
d9bce9d9
JM
1153 }
1154 RETURN();
1155}
1156
1157#if defined(TARGET_PPC64)
1158void OPPROTO op_check_subfo_64 (void)
79aceca5 1159{
d9bce9d9
JM
1160 if (likely(!(((uint64_t)(~T2) ^ (uint64_t)T1 ^ UINT64_MAX) &
1161 ((uint64_t)(~T2) ^ (uint64_t)T0) & (1ULL << 63)))) {
1162 xer_ov = 0;
1163 } else {
d9bce9d9 1164 xer_ov = 1;
966439a6 1165 xer_so = 1;
d9bce9d9 1166 }
79aceca5
FB
1167 RETURN();
1168}
d9bce9d9 1169#endif
79aceca5 1170
0cfec834 1171/* subtract from carrying */
d9bce9d9 1172void OPPROTO op_check_subfc (void)
79aceca5 1173{
d9bce9d9 1174 if (likely((uint32_t)T0 > (uint32_t)T1)) {
79aceca5 1175 xer_ca = 0;
d9bce9d9
JM
1176 } else {
1177 xer_ca = 1;
79aceca5
FB
1178 }
1179 RETURN();
1180}
1181
d9bce9d9
JM
1182#if defined(TARGET_PPC64)
1183void OPPROTO op_check_subfc_64 (void)
79aceca5 1184{
d9bce9d9
JM
1185 if (likely((uint64_t)T0 > (uint64_t)T1)) {
1186 xer_ca = 0;
1187 } else {
1188 xer_ca = 1;
1189 }
79aceca5
FB
1190 RETURN();
1191}
d9bce9d9 1192#endif
79aceca5 1193
0cfec834 1194/* subtract from extended */
76a66253 1195void OPPROTO op_subfe (void)
79aceca5 1196{
fdabc366 1197 do_subfe();
79aceca5
FB
1198 RETURN();
1199}
1200
d9bce9d9
JM
1201#if defined(TARGET_PPC64)
1202void OPPROTO op_subfe_64 (void)
79aceca5 1203{
d9bce9d9 1204 do_subfe_64();
79aceca5
FB
1205 RETURN();
1206}
d9bce9d9 1207#endif
79aceca5 1208
0cfec834 1209/* subtract from immediate carrying */
d9bce9d9 1210void OPPROTO op_subfic (void)
79aceca5 1211{
b6e27ab8 1212 T0 = (int32_t)PARAM1 + ~T0 + 1;
d9bce9d9 1213 if ((uint32_t)T0 <= (uint32_t)PARAM1) {
79aceca5
FB
1214 xer_ca = 1;
1215 } else {
1216 xer_ca = 0;
1217 }
1218 RETURN();
1219}
1220
d9bce9d9
JM
1221#if defined(TARGET_PPC64)
1222void OPPROTO op_subfic_64 (void)
1223{
2f401176 1224 T0 = (int64_t)PARAM1 + ~T0 + 1;
d9bce9d9
JM
1225 if ((uint64_t)T0 <= (uint64_t)PARAM1) {
1226 xer_ca = 1;
1227 } else {
1228 xer_ca = 0;
1229 }
1230 RETURN();
1231}
1232#endif
1233
0cfec834 1234/* subtract from minus one extended */
d9bce9d9 1235void OPPROTO op_subfme (void)
79aceca5
FB
1236{
1237 T0 = ~T0 + xer_ca - 1;
d9bce9d9
JM
1238 if (likely((uint32_t)T0 != (uint32_t)-1))
1239 xer_ca = 1;
1240 RETURN();
1241}
79aceca5 1242
d9bce9d9
JM
1243#if defined(TARGET_PPC64)
1244void OPPROTO op_subfme_64 (void)
1245{
1246 T0 = ~T0 + xer_ca - 1;
1247 if (likely((uint64_t)T0 != (uint64_t)-1))
79aceca5
FB
1248 xer_ca = 1;
1249 RETURN();
1250}
d9bce9d9 1251#endif
79aceca5 1252
76a66253 1253void OPPROTO op_subfmeo (void)
79aceca5 1254{
fdabc366 1255 do_subfmeo();
79aceca5
FB
1256 RETURN();
1257}
1258
d9bce9d9
JM
1259#if defined(TARGET_PPC64)
1260void OPPROTO op_subfmeo_64 (void)
1261{
1262 do_subfmeo_64();
1263 RETURN();
1264}
1265#endif
1266
0cfec834 1267/* subtract from zero extended */
d9bce9d9 1268void OPPROTO op_subfze (void)
79aceca5
FB
1269{
1270 T1 = ~T0;
1271 T0 = T1 + xer_ca;
d9bce9d9 1272 if ((uint32_t)T0 < (uint32_t)T1) {
79aceca5
FB
1273 xer_ca = 1;
1274 } else {
1275 xer_ca = 0;
1276 }
1277 RETURN();
1278}
1279
d9bce9d9
JM
1280#if defined(TARGET_PPC64)
1281void OPPROTO op_subfze_64 (void)
1282{
1283 T1 = ~T0;
1284 T0 = T1 + xer_ca;
1285 if ((uint64_t)T0 < (uint64_t)T1) {
1286 xer_ca = 1;
1287 } else {
1288 xer_ca = 0;
1289 }
1290 RETURN();
1291}
1292#endif
1293
76a66253 1294void OPPROTO op_subfzeo (void)
79aceca5 1295{
fdabc366 1296 do_subfzeo();
79aceca5
FB
1297 RETURN();
1298}
1299
d9bce9d9
JM
1300#if defined(TARGET_PPC64)
1301void OPPROTO op_subfzeo_64 (void)
1302{
1303 do_subfzeo_64();
1304 RETURN();
1305}
1306#endif
1307
79aceca5
FB
1308/*** Integer comparison ***/
1309/* compare */
d9bce9d9
JM
1310void OPPROTO op_cmp (void)
1311{
1312 if ((int32_t)T0 < (int32_t)T1) {
1313 T0 = 0x08;
1314 } else if ((int32_t)T0 > (int32_t)T1) {
1315 T0 = 0x04;
1316 } else {
1317 T0 = 0x02;
1318 }
966439a6 1319 T0 |= xer_so;
d9bce9d9
JM
1320 RETURN();
1321}
1322
1323#if defined(TARGET_PPC64)
1324void OPPROTO op_cmp_64 (void)
79aceca5 1325{
d9bce9d9 1326 if ((int64_t)T0 < (int64_t)T1) {
79aceca5 1327 T0 = 0x08;
d9bce9d9 1328 } else if ((int64_t)T0 > (int64_t)T1) {
79aceca5
FB
1329 T0 = 0x04;
1330 } else {
1331 T0 = 0x02;
1332 }
966439a6 1333 T0 |= xer_so;
79aceca5
FB
1334 RETURN();
1335}
d9bce9d9 1336#endif
79aceca5
FB
1337
1338/* compare immediate */
d9bce9d9 1339void OPPROTO op_cmpi (void)
79aceca5 1340{
d9bce9d9 1341 if ((int32_t)T0 < (int32_t)PARAM1) {
79aceca5 1342 T0 = 0x08;
d9bce9d9 1343 } else if ((int32_t)T0 > (int32_t)PARAM1) {
79aceca5
FB
1344 T0 = 0x04;
1345 } else {
1346 T0 = 0x02;
1347 }
966439a6 1348 T0 |= xer_so;
79aceca5
FB
1349 RETURN();
1350}
1351
d9bce9d9
JM
1352#if defined(TARGET_PPC64)
1353void OPPROTO op_cmpi_64 (void)
1354{
1355 if ((int64_t)T0 < (int64_t)((int32_t)PARAM1)) {
1356 T0 = 0x08;
1357 } else if ((int64_t)T0 > (int64_t)((int32_t)PARAM1)) {
1358 T0 = 0x04;
1359 } else {
1360 T0 = 0x02;
1361 }
966439a6 1362 T0 |= xer_so;
d9bce9d9
JM
1363 RETURN();
1364}
1365#endif
1366
79aceca5 1367/* compare logical */
d9bce9d9 1368void OPPROTO op_cmpl (void)
79aceca5 1369{
d9bce9d9 1370 if ((uint32_t)T0 < (uint32_t)T1) {
79aceca5 1371 T0 = 0x08;
d9bce9d9 1372 } else if ((uint32_t)T0 > (uint32_t)T1) {
79aceca5
FB
1373 T0 = 0x04;
1374 } else {
1375 T0 = 0x02;
1376 }
966439a6 1377 T0 |= xer_so;
79aceca5
FB
1378 RETURN();
1379}
1380
d9bce9d9
JM
1381#if defined(TARGET_PPC64)
1382void OPPROTO op_cmpl_64 (void)
1383{
1384 if ((uint64_t)T0 < (uint64_t)T1) {
1385 T0 = 0x08;
1386 } else if ((uint64_t)T0 > (uint64_t)T1) {
1387 T0 = 0x04;
1388 } else {
1389 T0 = 0x02;
1390 }
966439a6 1391 T0 |= xer_so;
d9bce9d9
JM
1392 RETURN();
1393}
1394#endif
1395
79aceca5 1396/* compare logical immediate */
d9bce9d9
JM
1397void OPPROTO op_cmpli (void)
1398{
1399 if ((uint32_t)T0 < (uint32_t)PARAM1) {
1400 T0 = 0x08;
1401 } else if ((uint32_t)T0 > (uint32_t)PARAM1) {
1402 T0 = 0x04;
1403 } else {
1404 T0 = 0x02;
1405 }
966439a6 1406 T0 |= xer_so;
d9bce9d9
JM
1407 RETURN();
1408}
1409
1410#if defined(TARGET_PPC64)
1411void OPPROTO op_cmpli_64 (void)
79aceca5 1412{
d9bce9d9 1413 if ((uint64_t)T0 < (uint64_t)PARAM1) {
79aceca5 1414 T0 = 0x08;
d9bce9d9 1415 } else if ((uint64_t)T0 > (uint64_t)PARAM1) {
79aceca5
FB
1416 T0 = 0x04;
1417 } else {
1418 T0 = 0x02;
1419 }
966439a6 1420 T0 |= xer_so;
79aceca5
FB
1421 RETURN();
1422}
d9bce9d9
JM
1423#endif
1424
1425void OPPROTO op_isel (void)
1426{
1427 if (T0)
1428 T0 = T1;
1429 else
1430 T0 = T2;
1431 RETURN();
1432}
1433
1434void OPPROTO op_popcntb (void)
1435{
1436 do_popcntb();
1437 RETURN();
1438}
1439
1440#if defined(TARGET_PPC64)
1441void OPPROTO op_popcntb_64 (void)
1442{
1443 do_popcntb_64();
1444 RETURN();
1445}
1446#endif
79aceca5
FB
1447
1448/*** Integer logical ***/
1449/* and */
36081602 1450void OPPROTO op_and (void)
79aceca5
FB
1451{
1452 T0 &= T1;
1453 RETURN();
1454}
1455
1456/* andc */
36081602 1457void OPPROTO op_andc (void)
79aceca5
FB
1458{
1459 T0 &= ~T1;
1460 RETURN();
1461}
1462
1463/* andi. */
76a66253 1464void OPPROTO op_andi_T0 (void)
79aceca5 1465{
2f401176 1466 T0 &= (uint32_t)PARAM1;
79aceca5
FB
1467 RETURN();
1468}
1469
76a66253
JM
1470void OPPROTO op_andi_T1 (void)
1471{
2f401176 1472 T1 &= (uint32_t)PARAM1;
76a66253
JM
1473 RETURN();
1474}
1475
40d0591e
JM
1476#if defined(TARGET_PPC64)
1477void OPPROTO op_andi_T0_64 (void)
1478{
2f401176 1479 T0 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
40d0591e
JM
1480 RETURN();
1481}
1482
1483void OPPROTO op_andi_T1_64 (void)
1484{
2f401176 1485 T1 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
40d0591e
JM
1486 RETURN();
1487}
1488#endif
1489
79aceca5 1490/* count leading zero */
76a66253 1491void OPPROTO op_cntlzw (void)
79aceca5 1492{
603fccce 1493 do_cntlzw();
79aceca5
FB
1494 RETURN();
1495}
1496
d9bce9d9
JM
1497#if defined(TARGET_PPC64)
1498void OPPROTO op_cntlzd (void)
1499{
603fccce 1500 do_cntlzd();
d9bce9d9
JM
1501 RETURN();
1502}
1503#endif
1504
79aceca5 1505/* eqv */
36081602 1506void OPPROTO op_eqv (void)
79aceca5
FB
1507{
1508 T0 = ~(T0 ^ T1);
1509 RETURN();
1510}
1511
1512/* extend sign byte */
d9bce9d9 1513void OPPROTO op_extsb (void)
79aceca5 1514{
d9bce9d9
JM
1515#if defined (TARGET_PPC64)
1516 T0 = (int64_t)((int8_t)T0);
1517#else
1518 T0 = (int32_t)((int8_t)T0);
1519#endif
79aceca5
FB
1520 RETURN();
1521}
1522
1523/* extend sign half word */
d9bce9d9 1524void OPPROTO op_extsh (void)
79aceca5 1525{
d9bce9d9
JM
1526#if defined (TARGET_PPC64)
1527 T0 = (int64_t)((int16_t)T0);
1528#else
1529 T0 = (int32_t)((int16_t)T0);
1530#endif
79aceca5
FB
1531 RETURN();
1532}
1533
d9bce9d9
JM
1534#if defined (TARGET_PPC64)
1535void OPPROTO op_extsw (void)
1536{
1537 T0 = (int64_t)((int32_t)T0);
1538 RETURN();
1539}
1540#endif
1541
79aceca5 1542/* nand */
36081602 1543void OPPROTO op_nand (void)
79aceca5
FB
1544{
1545 T0 = ~(T0 & T1);
1546 RETURN();
1547}
1548
1549/* nor */
36081602 1550void OPPROTO op_nor (void)
79aceca5
FB
1551{
1552 T0 = ~(T0 | T1);
1553 RETURN();
1554}
1555
1556/* or */
36081602 1557void OPPROTO op_or (void)
79aceca5
FB
1558{
1559 T0 |= T1;
1560 RETURN();
1561}
1562
1563/* orc */
36081602 1564void OPPROTO op_orc (void)
79aceca5
FB
1565{
1566 T0 |= ~T1;
1567 RETURN();
1568}
1569
1570/* ori */
36081602 1571void OPPROTO op_ori (void)
79aceca5 1572{
2f401176 1573 T0 |= (uint32_t)PARAM1;
79aceca5
FB
1574 RETURN();
1575}
1576
1577/* xor */
36081602 1578void OPPROTO op_xor (void)
79aceca5
FB
1579{
1580 T0 ^= T1;
1581 RETURN();
1582}
1583
1584/* xori */
36081602 1585void OPPROTO op_xori (void)
79aceca5 1586{
2f401176 1587 T0 ^= (uint32_t)PARAM1;
79aceca5
FB
1588 RETURN();
1589}
1590
1591/*** Integer rotate ***/
76a66253 1592void OPPROTO op_rotl32_T0_T1 (void)
79aceca5 1593{
76a66253 1594 T0 = rotl32(T0, T1 & 0x1F);
79aceca5
FB
1595 RETURN();
1596}
1597
76a66253 1598void OPPROTO op_rotli32_T0 (void)
79aceca5 1599{
76a66253 1600 T0 = rotl32(T0, PARAM1);
79aceca5
FB
1601 RETURN();
1602}
1603
51789c41
JM
1604#if defined(TARGET_PPC64)
1605void OPPROTO op_rotl64_T0_T1 (void)
1606{
1607 T0 = rotl64(T0, T1 & 0x3F);
1608 RETURN();
1609}
1610
1611void OPPROTO op_rotli64_T0 (void)
1612{
1613 T0 = rotl64(T0, PARAM1);
1614 RETURN();
1615}
1616#endif
1617
79aceca5
FB
1618/*** Integer shift ***/
1619/* shift left word */
d9bce9d9 1620void OPPROTO op_slw (void)
79aceca5
FB
1621{
1622 if (T1 & 0x20) {
1623 T0 = 0;
d9bce9d9
JM
1624 } else {
1625 T0 = (uint32_t)(T0 << T1);
1626 }
1627 RETURN();
1628}
1629
1630#if defined(TARGET_PPC64)
1631void OPPROTO op_sld (void)
1632{
1633 if (T1 & 0x40) {
1634 T0 = 0;
79aceca5
FB
1635 } else {
1636 T0 = T0 << T1;
1637 }
1638 RETURN();
1639}
d9bce9d9 1640#endif
79aceca5
FB
1641
1642/* shift right algebraic word */
76a66253 1643void OPPROTO op_sraw (void)
79aceca5 1644{
9a64fbe4 1645 do_sraw();
79aceca5
FB
1646 RETURN();
1647}
1648
d9bce9d9
JM
1649#if defined(TARGET_PPC64)
1650void OPPROTO op_srad (void)
1651{
1652 do_srad();
1653 RETURN();
1654}
1655#endif
1656
79aceca5 1657/* shift right algebraic word immediate */
d9bce9d9 1658void OPPROTO op_srawi (void)
79aceca5 1659{
d9bce9d9
JM
1660 uint32_t mask = (uint32_t)PARAM2;
1661
1662 T0 = (int32_t)T0 >> PARAM1;
1663 if ((int32_t)T1 < 0 && (T1 & mask) != 0) {
79aceca5
FB
1664 xer_ca = 1;
1665 } else {
1666 xer_ca = 0;
1667 }
1668 RETURN();
1669}
1670
d9bce9d9
JM
1671#if defined(TARGET_PPC64)
1672void OPPROTO op_sradi (void)
1673{
1674 uint64_t mask = ((uint64_t)PARAM2 << 32) | (uint64_t)PARAM3;
1675
1676 T0 = (int64_t)T0 >> PARAM1;
1677 if ((int64_t)T1 < 0 && ((uint64_t)T1 & mask) != 0) {
1678 xer_ca = 1;
1679 } else {
1680 xer_ca = 0;
1681 }
1682 RETURN();
1683}
1684#endif
1685
79aceca5 1686/* shift right word */
d9bce9d9 1687void OPPROTO op_srw (void)
79aceca5
FB
1688{
1689 if (T1 & 0x20) {
1690 T0 = 0;
1691 } else {
d9bce9d9
JM
1692 T0 = (uint32_t)T0 >> T1;
1693 }
1694 RETURN();
1695}
1696
1697#if defined(TARGET_PPC64)
1698void OPPROTO op_srd (void)
1699{
1700 if (T1 & 0x40) {
1701 T0 = 0;
1702 } else {
1703 T0 = (uint64_t)T0 >> T1;
79aceca5
FB
1704 }
1705 RETURN();
1706}
d9bce9d9 1707#endif
79aceca5 1708
76a66253
JM
1709void OPPROTO op_sl_T0_T1 (void)
1710{
1711 T0 = T0 << T1;
1712 RETURN();
1713}
1714
1715void OPPROTO op_sli_T0 (void)
1716{
1717 T0 = T0 << PARAM1;
1718 RETURN();
1719}
1720
fc0d441e
JM
1721void OPPROTO op_sli_T1 (void)
1722{
1723 T1 = T1 << PARAM1;
1724 RETURN();
1725}
1726
76a66253
JM
1727void OPPROTO op_srl_T0_T1 (void)
1728{
d9bce9d9
JM
1729 T0 = (uint32_t)T0 >> T1;
1730 RETURN();
1731}
1732
1733#if defined(TARGET_PPC64)
1734void OPPROTO op_srl_T0_T1_64 (void)
1735{
1736 T0 = (uint32_t)T0 >> T1;
76a66253
JM
1737 RETURN();
1738}
d9bce9d9 1739#endif
76a66253
JM
1740
1741void OPPROTO op_srli_T0 (void)
1742{
d9bce9d9 1743 T0 = (uint32_t)T0 >> PARAM1;
76a66253
JM
1744 RETURN();
1745}
1746
d9bce9d9
JM
1747#if defined(TARGET_PPC64)
1748void OPPROTO op_srli_T0_64 (void)
1749{
1750 T0 = (uint64_t)T0 >> PARAM1;
1751 RETURN();
1752}
1753#endif
1754
76a66253
JM
1755void OPPROTO op_srli_T1 (void)
1756{
d9bce9d9 1757 T1 = (uint32_t)T1 >> PARAM1;
76a66253
JM
1758 RETURN();
1759}
1760
d9bce9d9
JM
1761#if defined(TARGET_PPC64)
1762void OPPROTO op_srli_T1_64 (void)
1763{
1764 T1 = (uint64_t)T1 >> PARAM1;
1765 RETURN();
1766}
1767#endif
1768
79aceca5 1769/*** Floating-Point arithmetic ***/
9a64fbe4 1770/* fadd - fadd. */
36081602 1771void OPPROTO op_fadd (void)
79aceca5 1772{
7c58044c
JM
1773#if USE_PRECISE_EMULATION
1774 do_fadd();
1775#else
76a66253 1776 FT0 = float64_add(FT0, FT1, &env->fp_status);
7c58044c 1777#endif
79aceca5
FB
1778 RETURN();
1779}
1780
9a64fbe4 1781/* fsub - fsub. */
36081602 1782void OPPROTO op_fsub (void)
79aceca5 1783{
7c58044c
JM
1784#if USE_PRECISE_EMULATION
1785 do_fsub();
1786#else
76a66253 1787 FT0 = float64_sub(FT0, FT1, &env->fp_status);
7c58044c 1788#endif
79aceca5
FB
1789 RETURN();
1790}
1791
9a64fbe4 1792/* fmul - fmul. */
36081602 1793void OPPROTO op_fmul (void)
79aceca5 1794{
7c58044c
JM
1795#if USE_PRECISE_EMULATION
1796 do_fmul();
1797#else
76a66253 1798 FT0 = float64_mul(FT0, FT1, &env->fp_status);
7c58044c 1799#endif
79aceca5
FB
1800 RETURN();
1801}
1802
9a64fbe4 1803/* fdiv - fdiv. */
36081602 1804void OPPROTO op_fdiv (void)
79aceca5 1805{
7c58044c
JM
1806#if USE_PRECISE_EMULATION
1807 do_fdiv();
1808#else
fdabc366 1809 FT0 = float64_div(FT0, FT1, &env->fp_status);
7c58044c 1810#endif
79aceca5
FB
1811 RETURN();
1812}
28b6751f 1813
9a64fbe4 1814/* fsqrt - fsqrt. */
36081602 1815void OPPROTO op_fsqrt (void)
28b6751f 1816{
9a64fbe4
FB
1817 do_fsqrt();
1818 RETURN();
28b6751f
FB
1819}
1820
d7e4b87e
JM
1821/* fre - fre. */
1822void OPPROTO op_fre (void)
1823{
1824 do_fre();
1825 RETURN();
1826}
1827
9a64fbe4 1828/* fres - fres. */
36081602 1829void OPPROTO op_fres (void)
28b6751f 1830{
9a64fbe4
FB
1831 do_fres();
1832 RETURN();
28b6751f
FB
1833}
1834
9a64fbe4 1835/* frsqrte - frsqrte. */
36081602 1836void OPPROTO op_frsqrte (void)
28b6751f 1837{
4ecc3190 1838 do_frsqrte();
9a64fbe4 1839 RETURN();
28b6751f
FB
1840}
1841
9a64fbe4 1842/* fsel - fsel. */
36081602 1843void OPPROTO op_fsel (void)
28b6751f 1844{
9a64fbe4
FB
1845 do_fsel();
1846 RETURN();
28b6751f
FB
1847}
1848
9a64fbe4
FB
1849/*** Floating-Point multiply-and-add ***/
1850/* fmadd - fmadd. */
36081602 1851void OPPROTO op_fmadd (void)
28b6751f 1852{
e864cabd
JM
1853#if USE_PRECISE_EMULATION
1854 do_fmadd();
1855#else
76a66253
JM
1856 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1857 FT0 = float64_add(FT0, FT2, &env->fp_status);
e864cabd 1858#endif
9a64fbe4 1859 RETURN();
28b6751f
FB
1860}
1861
9a64fbe4 1862/* fmsub - fmsub. */
36081602 1863void OPPROTO op_fmsub (void)
28b6751f 1864{
e864cabd
JM
1865#if USE_PRECISE_EMULATION
1866 do_fmsub();
1867#else
76a66253
JM
1868 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1869 FT0 = float64_sub(FT0, FT2, &env->fp_status);
e864cabd 1870#endif
9a64fbe4 1871 RETURN();
28b6751f
FB
1872}
1873
9a64fbe4 1874/* fnmadd - fnmadd. - fnmadds - fnmadds. */
36081602 1875void OPPROTO op_fnmadd (void)
28b6751f 1876{
4b3686fa 1877 do_fnmadd();
9a64fbe4 1878 RETURN();
28b6751f
FB
1879}
1880
9a64fbe4 1881/* fnmsub - fnmsub. */
36081602 1882void OPPROTO op_fnmsub (void)
28b6751f 1883{
4b3686fa 1884 do_fnmsub();
9a64fbe4 1885 RETURN();
28b6751f
FB
1886}
1887
9a64fbe4
FB
1888/*** Floating-Point round & convert ***/
1889/* frsp - frsp. */
36081602 1890void OPPROTO op_frsp (void)
28b6751f 1891{
7c58044c
JM
1892#if USE_PRECISE_EMULATION
1893 do_frsp();
1894#else
76a66253 1895 FT0 = float64_to_float32(FT0, &env->fp_status);
7c58044c 1896#endif
9a64fbe4 1897 RETURN();
28b6751f
FB
1898}
1899
9a64fbe4 1900/* fctiw - fctiw. */
36081602 1901void OPPROTO op_fctiw (void)
28b6751f 1902{
9a64fbe4
FB
1903 do_fctiw();
1904 RETURN();
28b6751f
FB
1905}
1906
9a64fbe4 1907/* fctiwz - fctiwz. */
36081602 1908void OPPROTO op_fctiwz (void)
28b6751f 1909{
9a64fbe4
FB
1910 do_fctiwz();
1911 RETURN();
28b6751f
FB
1912}
1913
426613db
JM
1914#if defined(TARGET_PPC64)
1915/* fcfid - fcfid. */
36081602 1916void OPPROTO op_fcfid (void)
426613db
JM
1917{
1918 do_fcfid();
1919 RETURN();
1920}
1921
1922/* fctid - fctid. */
36081602 1923void OPPROTO op_fctid (void)
426613db
JM
1924{
1925 do_fctid();
1926 RETURN();
1927}
1928
1929/* fctidz - fctidz. */
36081602 1930void OPPROTO op_fctidz (void)
426613db
JM
1931{
1932 do_fctidz();
1933 RETURN();
1934}
1935#endif
1936
d7e4b87e
JM
1937void OPPROTO op_frin (void)
1938{
1939 do_frin();
1940 RETURN();
1941}
1942
1943void OPPROTO op_friz (void)
1944{
1945 do_friz();
1946 RETURN();
1947}
1948
1949void OPPROTO op_frip (void)
1950{
1951 do_frip();
1952 RETURN();
1953}
1954
1955void OPPROTO op_frim (void)
1956{
1957 do_frim();
1958 RETURN();
1959}
1960
9a64fbe4
FB
1961/*** Floating-Point compare ***/
1962/* fcmpu */
36081602 1963void OPPROTO op_fcmpu (void)
28b6751f 1964{
9a64fbe4
FB
1965 do_fcmpu();
1966 RETURN();
28b6751f
FB
1967}
1968
9a64fbe4 1969/* fcmpo */
36081602 1970void OPPROTO op_fcmpo (void)
fb0eaffc 1971{
9a64fbe4
FB
1972 do_fcmpo();
1973 RETURN();
fb0eaffc
FB
1974}
1975
9a64fbe4
FB
1976/*** Floating-point move ***/
1977/* fabs */
36081602 1978void OPPROTO op_fabs (void)
fb0eaffc 1979{
fdabc366 1980 FT0 = float64_abs(FT0);
fb0eaffc
FB
1981 RETURN();
1982}
1983
9a64fbe4 1984/* fnabs */
36081602 1985void OPPROTO op_fnabs (void)
fb0eaffc 1986{
fdabc366
FB
1987 FT0 = float64_abs(FT0);
1988 FT0 = float64_chs(FT0);
fb0eaffc
FB
1989 RETURN();
1990}
1991
9a64fbe4 1992/* fneg */
36081602 1993void OPPROTO op_fneg (void)
fb0eaffc 1994{
fdabc366 1995 FT0 = float64_chs(FT0);
fb0eaffc
FB
1996 RETURN();
1997}
1998
9a64fbe4 1999/* Load and store */
9a64fbe4 2000#define MEMSUFFIX _raw
76a66253 2001#include "op_helper.h"
9a64fbe4 2002#include "op_mem.h"
a541f297 2003#if !defined(CONFIG_USER_ONLY)
9a64fbe4 2004#define MEMSUFFIX _user
76a66253 2005#include "op_helper.h"
9a64fbe4 2006#include "op_mem.h"
9a64fbe4 2007#define MEMSUFFIX _kernel
76a66253 2008#include "op_helper.h"
9a64fbe4 2009#include "op_mem.h"
1e42b8f0
JM
2010#if defined(TARGET_PPC64H)
2011#define MEMSUFFIX _hypv
2012#include "op_helper.h"
2013#include "op_mem.h"
2014#endif
9a64fbe4
FB
2015#endif
2016
4b3686fa 2017/* Special op to check and maybe clear reservation */
d9bce9d9 2018void OPPROTO op_check_reservation (void)
4b3686fa 2019{
fdabc366
FB
2020 if ((uint32_t)env->reserve == (uint32_t)(T0 & ~0x00000003))
2021 env->reserve = -1;
4b3686fa
FB
2022 RETURN();
2023}
2024
d9bce9d9
JM
2025#if defined(TARGET_PPC64)
2026void OPPROTO op_check_reservation_64 (void)
2027{
2028 if ((uint64_t)env->reserve == (uint64_t)(T0 & ~0x00000003))
2029 env->reserve = -1;
2030 RETURN();
2031}
2032#endif
2033
be147d08
JM
2034void OPPROTO op_wait (void)
2035{
2036 env->halted = 1;
2037 RETURN();
2038}
2039
9a64fbe4 2040/* Return from interrupt */
76a66253
JM
2041#if !defined(CONFIG_USER_ONLY)
2042void OPPROTO op_rfi (void)
28b6751f 2043{
fdabc366 2044 do_rfi();
fb0eaffc
FB
2045 RETURN();
2046}
d9bce9d9
JM
2047
2048#if defined(TARGET_PPC64)
426613db
JM
2049void OPPROTO op_rfid (void)
2050{
2051 do_rfid();
2052 RETURN();
2053}
d9bce9d9 2054#endif
be147d08
JM
2055
2056#if defined(TARGET_PPC64H)
2057void OPPROTO op_hrfid (void)
2058{
2059 do_hrfid();
2060 RETURN();
2061}
2062#endif
6f5d427d
JM
2063
2064/* Exception vectors */
2065void OPPROTO op_store_excp_prefix (void)
2066{
2067 T0 &= env->ivpr_mask;
2068 env->excp_prefix = T0;
2069 RETURN();
2070}
2071
2072void OPPROTO op_store_excp_vector (void)
2073{
2074 T0 &= env->ivor_mask;
2075 env->excp_vectors[PARAM1] = T0;
2076 RETURN();
2077}
76a66253 2078#endif
fb0eaffc 2079
9a64fbe4 2080/* Trap word */
76a66253 2081void OPPROTO op_tw (void)
fb0eaffc 2082{
76a66253 2083 do_tw(PARAM1);
fb0eaffc
FB
2084 RETURN();
2085}
2086
d9bce9d9
JM
2087#if defined(TARGET_PPC64)
2088void OPPROTO op_td (void)
2089{
2090 do_td(PARAM1);
2091 RETURN();
2092}
2093#endif
2094
76a66253 2095#if !defined(CONFIG_USER_ONLY)
9a64fbe4 2096/* tlbia */
36081602 2097void OPPROTO op_tlbia (void)
fb0eaffc 2098{
daf4f96e 2099 ppc_tlb_invalidate_all(env);
9a64fbe4
FB
2100 RETURN();
2101}
2102
2103/* tlbie */
d9bce9d9 2104void OPPROTO op_tlbie (void)
9a64fbe4 2105{
daf4f96e 2106 ppc_tlb_invalidate_one(env, (uint32_t)T0);
fb0eaffc 2107 RETURN();
28b6751f 2108}
d9bce9d9
JM
2109
2110#if defined(TARGET_PPC64)
2111void OPPROTO op_tlbie_64 (void)
2112{
daf4f96e 2113 ppc_tlb_invalidate_one(env, T0);
d9bce9d9
JM
2114 RETURN();
2115}
2116#endif
2117
2118#if defined(TARGET_PPC64)
2119void OPPROTO op_slbia (void)
2120{
daf4f96e 2121 ppc_slb_invalidate_all(env);
d9bce9d9
JM
2122 RETURN();
2123}
2124
2125void OPPROTO op_slbie (void)
2126{
daf4f96e
JM
2127 ppc_slb_invalidate_one(env, (uint32_t)T0);
2128 RETURN();
2129}
2130
2131void OPPROTO op_slbie_64 (void)
2132{
2133 ppc_slb_invalidate_one(env, T0);
d9bce9d9
JM
2134 RETURN();
2135}
2136#endif
76a66253 2137#endif
3fc6c082 2138
76a66253 2139#if !defined(CONFIG_USER_ONLY)
7dbe11ac 2140/* PowerPC 602/603/755 software TLB load instructions */
76a66253
JM
2141void OPPROTO op_6xx_tlbld (void)
2142{
2143 do_load_6xx_tlb(0);
2144 RETURN();
2145}
2146
2147void OPPROTO op_6xx_tlbli (void)
2148{
2149 do_load_6xx_tlb(1);
2150 RETURN();
2151}
7dbe11ac
JM
2152
2153/* PowerPC 74xx software TLB load instructions */
2154void OPPROTO op_74xx_tlbld (void)
2155{
2156 do_load_74xx_tlb(0);
2157 RETURN();
2158}
2159
2160void OPPROTO op_74xx_tlbli (void)
2161{
2162 do_load_74xx_tlb(1);
2163 RETURN();
2164}
76a66253
JM
2165#endif
2166
2167/* 601 specific */
76a66253
JM
2168void OPPROTO op_load_601_rtcl (void)
2169{
2170 T0 = cpu_ppc601_load_rtcl(env);
2171 RETURN();
2172}
2173
76a66253
JM
2174void OPPROTO op_load_601_rtcu (void)
2175{
2176 T0 = cpu_ppc601_load_rtcu(env);
2177 RETURN();
2178}
2179
2180#if !defined(CONFIG_USER_ONLY)
76a66253
JM
2181void OPPROTO op_store_601_rtcl (void)
2182{
2183 cpu_ppc601_store_rtcl(env, T0);
2184 RETURN();
2185}
2186
76a66253
JM
2187void OPPROTO op_store_601_rtcu (void)
2188{
2189 cpu_ppc601_store_rtcu(env, T0);
2190 RETURN();
2191}
2192
056401ea
JM
2193void OPPROTO op_store_hid0_601 (void)
2194{
2195 do_store_hid0_601();
2196 RETURN();
2197}
2198
76a66253
JM
2199void OPPROTO op_load_601_bat (void)
2200{
2201 T0 = env->IBAT[PARAM1][PARAM2];
2202 RETURN();
2203}
76a66253 2204
76a66253
JM
2205void OPPROTO op_store_601_batl (void)
2206{
056401ea 2207 do_store_ibatl_601(env, PARAM1, T0);
76a66253
JM
2208 RETURN();
2209}
2210
2211void OPPROTO op_store_601_batu (void)
2212{
056401ea 2213 do_store_ibatu_601(env, PARAM1, T0);
76a66253
JM
2214 RETURN();
2215}
2216#endif /* !defined(CONFIG_USER_ONLY) */
2217
2218/* PowerPC 601 specific instructions (POWER bridge) */
2219/* XXX: those micro-ops need tests ! */
2220void OPPROTO op_POWER_abs (void)
2221{
2222 if (T0 == INT32_MIN)
2223 T0 = INT32_MAX;
2224 else if (T0 < 0)
2225 T0 = -T0;
2226 RETURN();
2227}
2228
2229void OPPROTO op_POWER_abso (void)
2230{
2231 do_POWER_abso();
2232 RETURN();
2233}
2234
2235void OPPROTO op_POWER_clcs (void)
2236{
2237 do_POWER_clcs();
2238 RETURN();
2239}
2240
2241void OPPROTO op_POWER_div (void)
2242{
2243 do_POWER_div();
2244 RETURN();
2245}
2246
2247void OPPROTO op_POWER_divo (void)
2248{
2249 do_POWER_divo();
2250 RETURN();
2251}
2252
2253void OPPROTO op_POWER_divs (void)
2254{
2255 do_POWER_divs();
2256 RETURN();
2257}
2258
2259void OPPROTO op_POWER_divso (void)
2260{
2261 do_POWER_divso();
2262 RETURN();
2263}
2264
2265void OPPROTO op_POWER_doz (void)
2266{
d9bce9d9 2267 if ((int32_t)T1 > (int32_t)T0)
76a66253
JM
2268 T0 = T1 - T0;
2269 else
2270 T0 = 0;
2271 RETURN();
2272}
2273
2274void OPPROTO op_POWER_dozo (void)
2275{
2276 do_POWER_dozo();
2277 RETURN();
2278}
2279
2280void OPPROTO op_load_xer_cmp (void)
2281{
2282 T2 = xer_cmp;
2283 RETURN();
2284}
2285
2286void OPPROTO op_POWER_maskg (void)
2287{
2288 do_POWER_maskg();
2289 RETURN();
2290}
2291
2292void OPPROTO op_POWER_maskir (void)
2293{
2294 T0 = (T0 & ~T2) | (T1 & T2);
2295 RETURN();
2296}
2297
2298void OPPROTO op_POWER_mul (void)
2299{
2300 uint64_t tmp;
2301
2302 tmp = (uint64_t)T0 * (uint64_t)T1;
2303 env->spr[SPR_MQ] = tmp >> 32;
2304 T0 = tmp;
2305 RETURN();
2306}
2307
2308void OPPROTO op_POWER_mulo (void)
2309{
2310 do_POWER_mulo();
2311 RETURN();
2312}
2313
2314void OPPROTO op_POWER_nabs (void)
2315{
2316 if (T0 > 0)
2317 T0 = -T0;
2318 RETURN();
2319}
2320
2321void OPPROTO op_POWER_nabso (void)
2322{
2323 /* nabs never overflows */
2324 if (T0 > 0)
2325 T0 = -T0;
2326 xer_ov = 0;
2327 RETURN();
2328}
2329
2330/* XXX: factorise POWER rotates... */
2331void OPPROTO op_POWER_rlmi (void)
2332{
2333 T0 = rotl32(T0, T2) & PARAM1;
2f401176 2334 T0 |= T1 & (uint32_t)PARAM2;
76a66253
JM
2335 RETURN();
2336}
2337
2338void OPPROTO op_POWER_rrib (void)
2339{
2340 T2 &= 0x1FUL;
2341 T0 = rotl32(T0 & INT32_MIN, T2);
2342 T0 |= T1 & ~rotl32(INT32_MIN, T2);
2343 RETURN();
2344}
2345
2346void OPPROTO op_POWER_sle (void)
2347{
2348 T1 &= 0x1FUL;
2349 env->spr[SPR_MQ] = rotl32(T0, T1);
2350 T0 = T0 << T1;
2351 RETURN();
2352}
2353
2354void OPPROTO op_POWER_sleq (void)
2355{
2356 uint32_t tmp = env->spr[SPR_MQ];
2357
2358 T1 &= 0x1FUL;
2359 env->spr[SPR_MQ] = rotl32(T0, T1);
2360 T0 = T0 << T1;
2361 T0 |= tmp >> (32 - T1);
2362 RETURN();
2363}
2364
2365void OPPROTO op_POWER_sllq (void)
2366{
2367 uint32_t msk = -1;
2368
2369 msk = msk << (T1 & 0x1FUL);
2370 if (T1 & 0x20UL)
2371 msk = ~msk;
2372 T1 &= 0x1FUL;
2373 T0 = (T0 << T1) & msk;
2374 T0 |= env->spr[SPR_MQ] & ~msk;
2375 RETURN();
2376}
2377
2378void OPPROTO op_POWER_slq (void)
2379{
2380 uint32_t msk = -1, tmp;
2381
2382 msk = msk << (T1 & 0x1FUL);
2383 if (T1 & 0x20UL)
2384 msk = ~msk;
2385 T1 &= 0x1FUL;
2386 tmp = rotl32(T0, T1);
2387 T0 = tmp & msk;
2388 env->spr[SPR_MQ] = tmp;
2389 RETURN();
2390}
2391
2392void OPPROTO op_POWER_sraq (void)
2393{
2394 env->spr[SPR_MQ] = rotl32(T0, 32 - (T1 & 0x1FUL));
2395 if (T1 & 0x20UL)
2396 T0 = -1L;
2397 else
d9bce9d9 2398 T0 = (int32_t)T0 >> T1;
76a66253
JM
2399 RETURN();
2400}
2401
2402void OPPROTO op_POWER_sre (void)
2403{
2404 T1 &= 0x1FUL;
2405 env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
d9bce9d9 2406 T0 = (int32_t)T0 >> T1;
76a66253
JM
2407 RETURN();
2408}
2409
2410void OPPROTO op_POWER_srea (void)
2411{
2412 T1 &= 0x1FUL;
2413 env->spr[SPR_MQ] = T0 >> T1;
d9bce9d9 2414 T0 = (int32_t)T0 >> T1;
76a66253
JM
2415 RETURN();
2416}
2417
2418void OPPROTO op_POWER_sreq (void)
2419{
2420 uint32_t tmp;
2421 int32_t msk;
2422
2423 T1 &= 0x1FUL;
2424 msk = INT32_MIN >> T1;
2425 tmp = env->spr[SPR_MQ];
2426 env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
2427 T0 = T0 >> T1;
2428 T0 |= tmp & msk;
2429 RETURN();
2430}
2431
2432void OPPROTO op_POWER_srlq (void)
2433{
2434 uint32_t tmp;
2435 int32_t msk;
2436
2437 msk = INT32_MIN >> (T1 & 0x1FUL);
2438 if (T1 & 0x20UL)
2439 msk = ~msk;
2440 T1 &= 0x1FUL;
2441 tmp = env->spr[SPR_MQ];
2442 env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
2443 T0 = T0 >> T1;
2444 T0 &= msk;
2445 T0 |= tmp & ~msk;
2446 RETURN();
2447}
2448
2449void OPPROTO op_POWER_srq (void)
2450{
2451 T1 &= 0x1FUL;
2452 env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
2453 T0 = T0 >> T1;
2454 RETURN();
2455}
2456
2457/* POWER instructions not implemented in PowerPC 601 */
2458#if !defined(CONFIG_USER_ONLY)
2459void OPPROTO op_POWER_mfsri (void)
2460{
2461 T1 = T0 >> 28;
2462 T0 = env->sr[T1];
2463 RETURN();
2464}
2465
2466void OPPROTO op_POWER_rac (void)
2467{
2468 do_POWER_rac();
2469 RETURN();
2470}
2471
2472void OPPROTO op_POWER_rfsvc (void)
2473{
2474 do_POWER_rfsvc();
2475 RETURN();
2476}
2477#endif
2478
2479/* PowerPC 602 specific instruction */
2480#if !defined(CONFIG_USER_ONLY)
2481void OPPROTO op_602_mfrom (void)
2482{
2483 do_op_602_mfrom();
2484 RETURN();
2485}
2486#endif
2487
2488/* PowerPC 4xx specific micro-ops */
2489void OPPROTO op_405_add_T0_T2 (void)
2490{
2491 T0 = (int32_t)T0 + (int32_t)T2;
2492 RETURN();
2493}
2494
2495void OPPROTO op_405_mulchw (void)
2496{
2497 T0 = ((int16_t)T0) * ((int16_t)(T1 >> 16));
2498 RETURN();
2499}
2500
2501void OPPROTO op_405_mulchwu (void)
2502{
2503 T0 = ((uint16_t)T0) * ((uint16_t)(T1 >> 16));
2504 RETURN();
2505}
2506
2507void OPPROTO op_405_mulhhw (void)
2508{
2509 T0 = ((int16_t)(T0 >> 16)) * ((int16_t)(T1 >> 16));
2510 RETURN();
2511}
2512
2513void OPPROTO op_405_mulhhwu (void)
2514{
2515 T0 = ((uint16_t)(T0 >> 16)) * ((uint16_t)(T1 >> 16));
2516 RETURN();
2517}
2518
2519void OPPROTO op_405_mullhw (void)
2520{
2521 T0 = ((int16_t)T0) * ((int16_t)T1);
2522 RETURN();
2523}
2524
2525void OPPROTO op_405_mullhwu (void)
2526{
2527 T0 = ((uint16_t)T0) * ((uint16_t)T1);
2528 RETURN();
2529}
2530
2531void OPPROTO op_405_check_ov (void)
2532{
2533 do_405_check_ov();
2534 RETURN();
2535}
2536
2537void OPPROTO op_405_check_sat (void)
2538{
2539 do_405_check_sat();
2540 RETURN();
2541}
2542
2543void OPPROTO op_405_check_ovu (void)
2544{
2545 if (likely(T0 >= T2)) {
2546 xer_ov = 0;
2547 } else {
2548 xer_ov = 1;
2549 xer_so = 1;
2550 }
2551 RETURN();
2552}
2553
2554void OPPROTO op_405_check_satu (void)
2555{
2556 if (unlikely(T0 < T2)) {
2557 /* Saturate result */
2558 T0 = -1;
2559 }
2560 RETURN();
2561}
2562
a42bd6cc 2563void OPPROTO op_load_dcr (void)
76a66253 2564{
a42bd6cc 2565 do_load_dcr();
76a66253
JM
2566 RETURN();
2567}
2568
a42bd6cc 2569void OPPROTO op_store_dcr (void)
76a66253 2570{
a42bd6cc 2571 do_store_dcr();
76a66253
JM
2572 RETURN();
2573}
2574
a750fc0b 2575#if !defined(CONFIG_USER_ONLY)
76a66253
JM
2576/* Return from critical interrupt :
2577 * same as rfi, except nip & MSR are loaded from SRR2/3 instead of SRR0/1
2578 */
a42bd6cc
JM
2579void OPPROTO op_40x_rfci (void)
2580{
2581 do_40x_rfci();
2582 RETURN();
2583}
2584
2585void OPPROTO op_rfci (void)
2586{
2587 do_rfci();
2588 RETURN();
2589}
2590
2591void OPPROTO op_rfdi (void)
2592{
2593 do_rfdi();
2594 RETURN();
2595}
2596
2597void OPPROTO op_rfmci (void)
76a66253 2598{
a42bd6cc 2599 do_rfmci();
76a66253
JM
2600 RETURN();
2601}
2602
a42bd6cc 2603void OPPROTO op_wrte (void)
76a66253 2604{
0411a972
JM
2605 /* We don't call do_store_msr here as we won't trigger
2606 * any special case nor change hflags
2607 */
2608 T0 &= 1 << MSR_EE;
2609 env->msr &= ~(1 << MSR_EE);
2610 env->msr |= T0;
76a66253
JM
2611 RETURN();
2612}
2613
a4bb6c3e 2614void OPPROTO op_440_tlbre (void)
5eb7995e 2615{
a4bb6c3e 2616 do_440_tlbre(PARAM1);
5eb7995e
JM
2617 RETURN();
2618}
2619
a4bb6c3e 2620void OPPROTO op_440_tlbsx (void)
5eb7995e 2621{
daf4f96e 2622 T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_440_MMUCR] & 0xFF);
5eb7995e
JM
2623 RETURN();
2624}
2625
daf4f96e 2626void OPPROTO op_4xx_tlbsx_check (void)
5eb7995e 2627{
daf4f96e
JM
2628 int tmp;
2629
2630 tmp = xer_so;
2631 if (T0 != -1)
2632 tmp |= 0x02;
2633 env->crf[0] = tmp;
5eb7995e
JM
2634 RETURN();
2635}
2636
a4bb6c3e 2637void OPPROTO op_440_tlbwe (void)
5eb7995e 2638{
a4bb6c3e 2639 do_440_tlbwe(PARAM1);
5eb7995e
JM
2640 RETURN();
2641}
2642
76a66253
JM
2643void OPPROTO op_4xx_tlbre_lo (void)
2644{
2645 do_4xx_tlbre_lo();
2646 RETURN();
2647}
2648
2649void OPPROTO op_4xx_tlbre_hi (void)
2650{
2651 do_4xx_tlbre_hi();
2652 RETURN();
2653}
2654
2655void OPPROTO op_4xx_tlbsx (void)
2656{
daf4f96e 2657 T0 = ppcemb_tlb_search(env, T0, env->spr[SPR_40x_PID]);
76a66253
JM
2658 RETURN();
2659}
2660
2661void OPPROTO op_4xx_tlbwe_lo (void)
2662{
2663 do_4xx_tlbwe_lo();
2664 RETURN();
2665}
2666
2667void OPPROTO op_4xx_tlbwe_hi (void)
2668{
2669 do_4xx_tlbwe_hi();
2670 RETURN();
2671}
2672#endif
2673
2674/* SPR micro-ops */
2675/* 440 specific */
2676void OPPROTO op_440_dlmzb (void)
2677{
2678 do_440_dlmzb();
2679 RETURN();
2680}
2681
2682void OPPROTO op_440_dlmzb_update_Rc (void)
2683{
2684 if (T0 == 8)
2685 T0 = 0x2;
2686 else if (T0 < 4)
2687 T0 = 0x4;
2688 else
2689 T0 = 0x8;
2690 RETURN();
2691}
2692
2693#if !defined(CONFIG_USER_ONLY)
2694void OPPROTO op_store_pir (void)
3fc6c082
FB
2695{
2696 env->spr[SPR_PIR] = T0 & 0x0000000FUL;
2697 RETURN();
2698}
76a66253
JM
2699
2700void OPPROTO op_load_403_pb (void)
2701{
2702 do_load_403_pb(PARAM1);
2703 RETURN();
2704}
2705
2706void OPPROTO op_store_403_pb (void)
2707{
2708 do_store_403_pb(PARAM1);
2709 RETURN();
2710}
2711
76a66253
JM
2712void OPPROTO op_load_40x_pit (void)
2713{
2714 T0 = load_40x_pit(env);
2715 RETURN();
2716}
2717
76a66253
JM
2718void OPPROTO op_store_40x_pit (void)
2719{
2720 store_40x_pit(env, T0);
2721 RETURN();
2722}
2723
8ecc7913
JM
2724void OPPROTO op_store_40x_dbcr0 (void)
2725{
2726 store_40x_dbcr0(env, T0);
be147d08 2727 RETURN();
8ecc7913
JM
2728}
2729
c294fc58
JM
2730void OPPROTO op_store_40x_sler (void)
2731{
2732 store_40x_sler(env, T0);
2733 RETURN();
2734}
2735
76a66253
JM
2736void OPPROTO op_store_booke_tcr (void)
2737{
2738 store_booke_tcr(env, T0);
2739 RETURN();
2740}
2741
76a66253
JM
2742void OPPROTO op_store_booke_tsr (void)
2743{
2744 store_booke_tsr(env, T0);
2745 RETURN();
2746}
2747#endif /* !defined(CONFIG_USER_ONLY) */
0487d6a8 2748
35cdaad6 2749#if defined(TARGET_PPCEMB)
0487d6a8
JM
2750/* SPE extension */
2751void OPPROTO op_splatw_T1_64 (void)
2752{
2753 T1_64 = (T1_64 << 32) | (T1_64 & 0x00000000FFFFFFFFULL);
e864cabd 2754 RETURN();
0487d6a8
JM
2755}
2756
2757void OPPROTO op_splatwi_T0_64 (void)
2758{
2759 uint64_t tmp = PARAM1;
2760
2761 T0_64 = (tmp << 32) | tmp;
e864cabd 2762 RETURN();
0487d6a8
JM
2763}
2764
2765void OPPROTO op_splatwi_T1_64 (void)
2766{
2767 uint64_t tmp = PARAM1;
2768
2769 T1_64 = (tmp << 32) | tmp;
e864cabd 2770 RETURN();
0487d6a8
JM
2771}
2772
2773void OPPROTO op_extsh_T1_64 (void)
2774{
2775 T1_64 = (int32_t)((int16_t)T1_64);
2776 RETURN();
2777}
2778
2779void OPPROTO op_sli16_T1_64 (void)
2780{
2781 T1_64 = T1_64 << 16;
2782 RETURN();
2783}
2784
2785void OPPROTO op_sli32_T1_64 (void)
2786{
2787 T1_64 = T1_64 << 32;
2788 RETURN();
2789}
2790
2791void OPPROTO op_srli32_T1_64 (void)
2792{
2793 T1_64 = T1_64 >> 32;
2794 RETURN();
2795}
2796
2797void OPPROTO op_evsel (void)
2798{
2799 do_evsel();
2800 RETURN();
2801}
2802
2803void OPPROTO op_evaddw (void)
2804{
2805 do_evaddw();
2806 RETURN();
2807}
2808
2809void OPPROTO op_evsubfw (void)
2810{
2811 do_evsubfw();
2812 RETURN();
2813}
2814
2815void OPPROTO op_evneg (void)
2816{
2817 do_evneg();
2818 RETURN();
2819}
2820
2821void OPPROTO op_evabs (void)
2822{
2823 do_evabs();
2824 RETURN();
2825}
2826
2827void OPPROTO op_evextsh (void)
2828{
2829 T0_64 = ((uint64_t)((int32_t)(int16_t)(T0_64 >> 32)) << 32) |
2830 (uint64_t)((int32_t)(int16_t)T0_64);
2831 RETURN();
2832}
2833
2834void OPPROTO op_evextsb (void)
2835{
2836 T0_64 = ((uint64_t)((int32_t)(int8_t)(T0_64 >> 32)) << 32) |
2837 (uint64_t)((int32_t)(int8_t)T0_64);
2838 RETURN();
2839}
2840
2841void OPPROTO op_evcntlzw (void)
2842{
2843 do_evcntlzw();
2844 RETURN();
2845}
2846
2847void OPPROTO op_evrndw (void)
2848{
2849 do_evrndw();
2850 RETURN();
2851}
2852
2853void OPPROTO op_brinc (void)
2854{
2855 do_brinc();
2856 RETURN();
2857}
2858
2859void OPPROTO op_evcntlsw (void)
2860{
2861 do_evcntlsw();
2862 RETURN();
2863}
2864
2865void OPPROTO op_evand (void)
2866{
2867 T0_64 &= T1_64;
2868 RETURN();
2869}
2870
2871void OPPROTO op_evandc (void)
2872{
2873 T0_64 &= ~T1_64;
2874 RETURN();
2875}
2876
2877void OPPROTO op_evor (void)
2878{
2879 T0_64 |= T1_64;
2880 RETURN();
2881}
2882
2883void OPPROTO op_evxor (void)
2884{
2885 T0_64 ^= T1_64;
2886 RETURN();
2887}
2888
2889void OPPROTO op_eveqv (void)
2890{
2891 T0_64 = ~(T0_64 ^ T1_64);
2892 RETURN();
2893}
2894
2895void OPPROTO op_evnor (void)
2896{
2897 T0_64 = ~(T0_64 | T1_64);
2898 RETURN();
2899}
2900
2901void OPPROTO op_evorc (void)
2902{
2903 T0_64 |= ~T1_64;
2904 RETURN();
2905}
2906
2907void OPPROTO op_evnand (void)
2908{
2909 T0_64 = ~(T0_64 & T1_64);
2910 RETURN();
2911}
2912
2913void OPPROTO op_evsrws (void)
2914{
2915 do_evsrws();
2916 RETURN();
2917}
2918
2919void OPPROTO op_evsrwu (void)
2920{
2921 do_evsrwu();
2922 RETURN();
2923}
2924
2925void OPPROTO op_evslw (void)
2926{
2927 do_evslw();
2928 RETURN();
2929}
2930
2931void OPPROTO op_evrlw (void)
2932{
2933 do_evrlw();
2934 RETURN();
2935}
2936
2937void OPPROTO op_evmergelo (void)
2938{
2939 T0_64 = (T0_64 << 32) | (T1_64 & 0x00000000FFFFFFFFULL);
2940 RETURN();
2941}
2942
2943void OPPROTO op_evmergehi (void)
2944{
2945 T0_64 = (T0_64 & 0xFFFFFFFF00000000ULL) | (T1_64 >> 32);
2946 RETURN();
2947}
2948
2949void OPPROTO op_evmergelohi (void)
2950{
2951 T0_64 = (T0_64 << 32) | (T1_64 >> 32);
2952 RETURN();
2953}
2954
2955void OPPROTO op_evmergehilo (void)
2956{
2957 T0_64 = (T0_64 & 0xFFFFFFFF00000000ULL) | (T1_64 & 0x00000000FFFFFFFFULL);
2958 RETURN();
2959}
2960
2961void OPPROTO op_evcmpgts (void)
2962{
2963 do_evcmpgts();
2964 RETURN();
2965}
2966
2967void OPPROTO op_evcmpgtu (void)
2968{
2969 do_evcmpgtu();
2970 RETURN();
2971}
2972
2973void OPPROTO op_evcmplts (void)
2974{
2975 do_evcmplts();
2976 RETURN();
2977}
2978
2979void OPPROTO op_evcmpltu (void)
2980{
2981 do_evcmpltu();
2982 RETURN();
2983}
2984
2985void OPPROTO op_evcmpeq (void)
2986{
2987 do_evcmpeq();
2988 RETURN();
2989}
2990
2991void OPPROTO op_evfssub (void)
2992{
2993 do_evfssub();
2994 RETURN();
2995}
2996
2997void OPPROTO op_evfsadd (void)
2998{
2999 do_evfsadd();
3000 RETURN();
3001}
3002
3003void OPPROTO op_evfsnabs (void)
3004{
3005 do_evfsnabs();
3006 RETURN();
3007}
3008
3009void OPPROTO op_evfsabs (void)
3010{
3011 do_evfsabs();
3012 RETURN();
3013}
3014
3015void OPPROTO op_evfsneg (void)
3016{
3017 do_evfsneg();
3018 RETURN();
3019}
3020
3021void OPPROTO op_evfsdiv (void)
3022{
3023 do_evfsdiv();
3024 RETURN();
3025}
3026
3027void OPPROTO op_evfsmul (void)
3028{
3029 do_evfsmul();
3030 RETURN();
3031}
3032
3033void OPPROTO op_evfscmplt (void)
3034{
3035 do_evfscmplt();
3036 RETURN();
3037}
3038
3039void OPPROTO op_evfscmpgt (void)
3040{
3041 do_evfscmpgt();
3042 RETURN();
3043}
3044
3045void OPPROTO op_evfscmpeq (void)
3046{
3047 do_evfscmpeq();
3048 RETURN();
3049}
3050
3051void OPPROTO op_evfscfsi (void)
3052{
3053 do_evfscfsi();
3054 RETURN();
3055}
3056
3057void OPPROTO op_evfscfui (void)
3058{
3059 do_evfscfui();
3060 RETURN();
3061}
3062
3063void OPPROTO op_evfscfsf (void)
3064{
3065 do_evfscfsf();
3066 RETURN();
3067}
3068
3069void OPPROTO op_evfscfuf (void)
3070{
3071 do_evfscfuf();
3072 RETURN();
3073}
3074
3075void OPPROTO op_evfsctsi (void)
3076{
3077 do_evfsctsi();
3078 RETURN();
3079}
3080
3081void OPPROTO op_evfsctui (void)
3082{
3083 do_evfsctui();
3084 RETURN();
3085}
3086
3087void OPPROTO op_evfsctsf (void)
3088{
3089 do_evfsctsf();
3090 RETURN();
3091}
3092
3093void OPPROTO op_evfsctuf (void)
3094{
3095 do_evfsctuf();
3096 RETURN();
3097}
3098
3099void OPPROTO op_evfsctuiz (void)
3100{
3101 do_evfsctuiz();
3102 RETURN();
3103}
3104
3105void OPPROTO op_evfsctsiz (void)
3106{
3107 do_evfsctsiz();
3108 RETURN();
3109}
3110
3111void OPPROTO op_evfststlt (void)
3112{
3113 do_evfststlt();
3114 RETURN();
3115}
3116
3117void OPPROTO op_evfststgt (void)
3118{
3119 do_evfststgt();
3120 RETURN();
3121}
3122
3123void OPPROTO op_evfststeq (void)
3124{
3125 do_evfststeq();
3126 RETURN();
3127}
3128
3129void OPPROTO op_efssub (void)
3130{
3131 T0_64 = _do_efssub(T0_64, T1_64);
3132 RETURN();
3133}
3134
3135void OPPROTO op_efsadd (void)
3136{
3137 T0_64 = _do_efsadd(T0_64, T1_64);
3138 RETURN();
3139}
3140
3141void OPPROTO op_efsnabs (void)
3142{
3143 T0_64 = _do_efsnabs(T0_64);
3144 RETURN();
3145}
3146
3147void OPPROTO op_efsabs (void)
3148{
3149 T0_64 = _do_efsabs(T0_64);
3150 RETURN();
3151}
3152
3153void OPPROTO op_efsneg (void)
3154{
3155 T0_64 = _do_efsneg(T0_64);
3156 RETURN();
3157}
3158
3159void OPPROTO op_efsdiv (void)
3160{
3161 T0_64 = _do_efsdiv(T0_64, T1_64);
3162 RETURN();
3163}
3164
3165void OPPROTO op_efsmul (void)
3166{
3167 T0_64 = _do_efsmul(T0_64, T1_64);
3168 RETURN();
3169}
3170
3171void OPPROTO op_efscmplt (void)
3172{
3173 do_efscmplt();
3174 RETURN();
3175}
3176
3177void OPPROTO op_efscmpgt (void)
3178{
3179 do_efscmpgt();
3180 RETURN();
3181}
3182
3183void OPPROTO op_efscfd (void)
3184{
3185 do_efscfd();
3186 RETURN();
3187}
3188
3189void OPPROTO op_efscmpeq (void)
3190{
3191 do_efscmpeq();
3192 RETURN();
3193}
3194
3195void OPPROTO op_efscfsi (void)
3196{
3197 do_efscfsi();
3198 RETURN();
3199}
3200
3201void OPPROTO op_efscfui (void)
3202{
3203 do_efscfui();
3204 RETURN();
3205}
3206
3207void OPPROTO op_efscfsf (void)
3208{
3209 do_efscfsf();
3210 RETURN();
3211}
3212
3213void OPPROTO op_efscfuf (void)
3214{
3215 do_efscfuf();
3216 RETURN();
3217}
3218
3219void OPPROTO op_efsctsi (void)
3220{
3221 do_efsctsi();
3222 RETURN();
3223}
3224
3225void OPPROTO op_efsctui (void)
3226{
3227 do_efsctui();
3228 RETURN();
3229}
3230
3231void OPPROTO op_efsctsf (void)
3232{
3233 do_efsctsf();
3234 RETURN();
3235}
3236
3237void OPPROTO op_efsctuf (void)
3238{
3239 do_efsctuf();
3240 RETURN();
3241}
3242
3243void OPPROTO op_efsctsiz (void)
3244{
3245 do_efsctsiz();
3246 RETURN();
3247}
3248
3249void OPPROTO op_efsctuiz (void)
3250{
3251 do_efsctuiz();
3252 RETURN();
3253}
3254
3255void OPPROTO op_efststlt (void)
3256{
3257 T0 = _do_efststlt(T0_64, T1_64);
3258 RETURN();
3259}
3260
3261void OPPROTO op_efststgt (void)
3262{
3263 T0 = _do_efststgt(T0_64, T1_64);
3264 RETURN();
3265}
3266
3267void OPPROTO op_efststeq (void)
3268{
3269 T0 = _do_efststeq(T0_64, T1_64);
3270 RETURN();
3271}
3272
3273void OPPROTO op_efdsub (void)
3274{
3275 union {
3276 uint64_t u;
3277 float64 f;
3278 } u1, u2;
3279 u1.u = T0_64;
3280 u2.u = T1_64;
3281 u1.f = float64_sub(u1.f, u2.f, &env->spe_status);
3282 T0_64 = u1.u;
3283 RETURN();
3284}
3285
3286void OPPROTO op_efdadd (void)
3287{
3288 union {
3289 uint64_t u;
3290 float64 f;
3291 } u1, u2;
3292 u1.u = T0_64;
3293 u2.u = T1_64;
3294 u1.f = float64_add(u1.f, u2.f, &env->spe_status);
3295 T0_64 = u1.u;
3296 RETURN();
3297}
3298
3299void OPPROTO op_efdcfsid (void)
3300{
3301 do_efdcfsi();
3302 RETURN();
3303}
3304
3305void OPPROTO op_efdcfuid (void)
3306{
3307 do_efdcfui();
3308 RETURN();
3309}
3310
3311void OPPROTO op_efdnabs (void)
3312{
3313 T0_64 |= 0x8000000000000000ULL;
3314 RETURN();
3315}
3316
3317void OPPROTO op_efdabs (void)
3318{
3319 T0_64 &= ~0x8000000000000000ULL;
3320 RETURN();
3321}
3322
3323void OPPROTO op_efdneg (void)
3324{
3325 T0_64 ^= 0x8000000000000000ULL;
3326 RETURN();
3327}
3328
3329void OPPROTO op_efddiv (void)
3330{
3331 union {
3332 uint64_t u;
3333 float64 f;
3334 } u1, u2;
3335 u1.u = T0_64;
3336 u2.u = T1_64;
3337 u1.f = float64_div(u1.f, u2.f, &env->spe_status);
3338 T0_64 = u1.u;
3339 RETURN();
3340}
3341
3342void OPPROTO op_efdmul (void)
3343{
3344 union {
3345 uint64_t u;
3346 float64 f;
3347 } u1, u2;
3348 u1.u = T0_64;
3349 u2.u = T1_64;
3350 u1.f = float64_mul(u1.f, u2.f, &env->spe_status);
3351 T0_64 = u1.u;
3352 RETURN();
3353}
3354
3355void OPPROTO op_efdctsidz (void)
3356{
3357 do_efdctsiz();
3358 RETURN();
3359}
3360
3361void OPPROTO op_efdctuidz (void)
3362{
3363 do_efdctuiz();
3364 RETURN();
3365}
3366
3367void OPPROTO op_efdcmplt (void)
3368{
3369 do_efdcmplt();
3370 RETURN();
3371}
3372
3373void OPPROTO op_efdcmpgt (void)
3374{
3375 do_efdcmpgt();
3376 RETURN();
3377}
3378
3379void OPPROTO op_efdcfs (void)
3380{
3381 do_efdcfs();
3382 RETURN();
3383}
3384
3385void OPPROTO op_efdcmpeq (void)
3386{
3387 do_efdcmpeq();
3388 RETURN();
3389}
3390
3391void OPPROTO op_efdcfsi (void)
3392{
3393 do_efdcfsi();
3394 RETURN();
3395}
3396
3397void OPPROTO op_efdcfui (void)
3398{
3399 do_efdcfui();
3400 RETURN();
3401}
3402
3403void OPPROTO op_efdcfsf (void)
3404{
3405 do_efdcfsf();
3406 RETURN();
3407}
3408
3409void OPPROTO op_efdcfuf (void)
3410{
3411 do_efdcfuf();
3412 RETURN();
3413}
3414
3415void OPPROTO op_efdctsi (void)
3416{
3417 do_efdctsi();
3418 RETURN();
3419}
3420
3421void OPPROTO op_efdctui (void)
3422{
3423 do_efdctui();
3424 RETURN();
3425}
3426
3427void OPPROTO op_efdctsf (void)
3428{
3429 do_efdctsf();
3430 RETURN();
3431}
3432
3433void OPPROTO op_efdctuf (void)
3434{
3435 do_efdctuf();
3436 RETURN();
3437}
3438
3439void OPPROTO op_efdctuiz (void)
3440{
3441 do_efdctuiz();
3442 RETURN();
3443}
3444
3445void OPPROTO op_efdctsiz (void)
3446{
3447 do_efdctsiz();
3448 RETURN();
3449}
3450
3451void OPPROTO op_efdtstlt (void)
3452{
3453 T0 = _do_efdtstlt(T0_64, T1_64);
3454 RETURN();
3455}
3456
3457void OPPROTO op_efdtstgt (void)
3458{
3459 T0 = _do_efdtstgt(T0_64, T1_64);
3460 RETURN();
3461}
3462
3463void OPPROTO op_efdtsteq (void)
3464{
3465 T0 = _do_efdtsteq(T0_64, T1_64);
3466 RETURN();
3467}
35cdaad6 3468#endif /* defined(TARGET_PPCEMB) */