[mirror_qemu.git] / target-ppc / op_helper.c

/*
 *  PPC emulation helpers for qemu.
 * 
 *  Copyright (c) 2003 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <math.h>
#include "exec.h"

#define MEMSUFFIX _raw
#include "op_helper_mem.h"
#if !defined(CONFIG_USER_ONLY)
#define MEMSUFFIX _user
#include "op_helper_mem.h"
#define MEMSUFFIX _kernel
#include "op_helper_mem.h"
#endif

/*****************************************************************************/
/* Exceptions processing helpers */
void cpu_loop_exit(void)
{
    longjmp(env->jmp_env, 1);
}

void do_raise_exception_err (uint32_t exception, int error_code)
{
#if 0
    printf("Raise exception %3x code : %d\n", exception, error_code);
#endif
    switch (exception) {
    case EXCP_EXTERNAL:
    case EXCP_DECR:
	printf("DECREMENTER & EXTERNAL exceptions should be hard interrupts !\n");
	if (msr_ee == 0)
	    return;
	break;
    case EXCP_PROGRAM:
	if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
	    return;
	break;
    default:
	break;
}
    env->exception_index = exception;
    env->error_code = error_code;
        cpu_loop_exit();
    }

void do_raise_exception (uint32_t exception)
{
    do_raise_exception_err(exception, 0);
}

/*****************************************************************************/
/* Helpers for "fat" micro operations */
/* Special registers load and store */
void do_load_cr (void)
{
    T0 = (env->crf[0] << 28) |
        (env->crf[1] << 24) |
        (env->crf[2] << 20) |
        (env->crf[3] << 16) |
        (env->crf[4] << 12) |
        (env->crf[5] << 8) |
        (env->crf[6] << 4) |
        (env->crf[7] << 0);
}

void do_store_cr (uint32_t mask)
{
    int i, sh;

    for (i = 0, sh = 7; i < 8; i++, sh --) {
        if (mask & (1 << sh))
            env->crf[i] = (T0 >> (sh * 4)) & 0xF;
    }
}

void do_load_xer (void)
{
    T0 = (xer_so << XER_SO) |
        (xer_ov << XER_OV) |
        (xer_ca << XER_CA) |
        (xer_bc << XER_BC);
}

void do_store_xer (void)
{
    xer_so = (T0 >> XER_SO) & 0x01;
    xer_ov = (T0 >> XER_OV) & 0x01;
    xer_ca = (T0 >> XER_CA) & 0x01;
    xer_bc = (T0 >> XER_BC) & 0x1f;
}

void do_load_msr (void)
{
    T0 = (msr_pow << MSR_POW) |
        (msr_ile << MSR_ILE) |
        (msr_ee << MSR_EE) |
        (msr_pr << MSR_PR) |
        (msr_fp << MSR_FP) |
        (msr_me << MSR_ME) |
        (msr_fe0 << MSR_FE0) |
        (msr_se << MSR_SE) |
        (msr_be << MSR_BE) |
        (msr_fe1 << MSR_FE1) |
        (msr_ip << MSR_IP) |
        (msr_ir << MSR_IR) |
        (msr_dr << MSR_DR) |
        (msr_ri << MSR_RI) |
        (msr_le << MSR_LE);
}

void do_store_msr (void)
{
#if 1 // TRY
    if (((T0 >> MSR_IR) & 0x01) != msr_ir ||
        ((T0 >> MSR_DR) & 0x01) != msr_dr ||
        ((T0 >> MSR_PR) & 0x01) != msr_pr)
    {
        do_tlbia();
    }
#endif
    msr_pow = (T0 >> MSR_POW) & 0x03;
    msr_ile = (T0 >> MSR_ILE) & 0x01;
    msr_ee = (T0 >> MSR_EE) & 0x01;
    msr_pr = (T0 >> MSR_PR) & 0x01;
    msr_fp = (T0 >> MSR_FP) & 0x01;
    msr_me = (T0 >> MSR_ME) & 0x01;
    msr_fe0 = (T0 >> MSR_FE0) & 0x01;
    msr_se = (T0 >> MSR_SE) & 0x01;
    msr_be = (T0 >> MSR_BE) & 0x01;
    msr_fe1 = (T0 >> MSR_FE1) & 0x01;
    msr_ip = (T0 >> MSR_IP) & 0x01;
    msr_ir = (T0 >> MSR_IR) & 0x01;
    msr_dr = (T0 >> MSR_DR) & 0x01;
    msr_ri = (T0 >> MSR_RI) & 0x01;
    msr_le = (T0 >> MSR_LE) & 0x01;
}

/* shift right arithmetic helper */
void do_sraw (void)
{
    int32_t ret;

    xer_ca = 0;
    if (T1 & 0x20) {
        ret = (-1) * (T0 >> 31);
        if (ret < 0 && (T0 & ~0x80000000) != 0)
            xer_ca = 1;
#if 1 // TRY
    } else if (T1 == 0) {
        ret = T0;
#endif
    } else {
        ret = (int32_t)T0 >> (T1 & 0x1f);
        if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0)
            xer_ca = 1;
    }
    T0 = ret;
}

/* Floating point operations helpers */
void do_load_fpscr (void)
{
    /* The 32 MSB of the target fpr are undefined.
     * They'll be zero...
     */
    union {
        double d;
        struct {
            uint32_t u[2];
        } s;
    } u;
    int i;

#ifdef WORDS_BIGENDIAN
#define WORD0 0
#define WORD1 1
#else
#define WORD0 1
#define WORD1 0
#endif
    u.s.u[WORD0] = 0;
    u.s.u[WORD1] = 0;
    for (i = 0; i < 8; i++)
        u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
    FT0 = u.d;
}

void do_store_fpscr (uint32_t mask)
{
    /*
     * We use only the 32 LSB of the incoming fpr
     */
    union {
        double d;
        struct {
            uint32_t u[2];
        } s;
    } u;
    int i;

    u.d = FT0;
    if (mask & 0x80)
        env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
    for (i = 1; i < 7; i++) {
        if (mask & (1 << (7 - i)))
            env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
    }
    /* TODO: update FEX & VX */
    /* Set rounding mode */
    switch (env->fpscr[0] & 0x3) {
    case 0:
        /* Best approximation (round to nearest) */
        fesetround(FE_TONEAREST);
        break;
    case 1:
        /* Smaller magnitude (round toward zero) */
        fesetround(FE_TOWARDZERO);
        break;
    case 2:
        /* Round toward +infinite */
        fesetround(FE_UPWARD);
        break;
    case 3:
        /* Round toward -infinite */
        fesetround(FE_DOWNWARD);
        break;
    }
}

void do_fctiw (void)
{
    union {
        double d;
        uint64_t i;
    } *p = (void *)&FT1;

    if (FT0 > (double)0x7FFFFFFF)
        p->i = 0x7FFFFFFFULL << 32;
    else if (FT0 < -(double)0x80000000)
        p->i = 0x80000000ULL << 32;
    else
        p->i = 0;
    p->i |= (uint32_t)FT0;
    FT0 = p->d;
}

void do_fctiwz (void)
{
    union {
        double d;
        uint64_t i;
    } *p = (void *)&FT1;
    int cround = fegetround();

    fesetround(FE_TOWARDZERO);
    if (FT0 > (double)0x7FFFFFFF)
        p->i = 0x7FFFFFFFULL << 32;
    else if (FT0 < -(double)0x80000000)
        p->i = 0x80000000ULL << 32;
    else
        p->i = 0;
    p->i |= (uint32_t)FT0;
    FT0 = p->d;
    fesetround(cround);
}

void do_fnmadd (void)
{
    FT0 = -((FT0 * FT1) + FT2);
}

void do_fnmsub (void)
{
    FT0 = -((FT0 * FT1) - FT2);
}

void do_fnmadds (void)
{
    FT0 = -((FTS0 * FTS1) + FTS2);
}

void do_fnmsubs (void)
{
    FT0 = -((FTS0 * FTS1) - FTS2);
}

void do_fsqrt (void)
{
    FT0 = sqrt(FT0);
}

void do_fsqrts (void)
{
    FT0 = (float)sqrt((float)FT0);
}

void do_fres (void)
{
    FT0 = 1.0 / FT0;
}

void do_fsqrte (void)
{
    FT0 = 1.0 / sqrt(FT0);
}

void do_fsel (void)
{
    if (FT0 >= 0)
        FT0 = FT2;
    else
        FT0 = FT1;
}

void do_fcmpu (void)
{
    if (isnan(FT0) || isnan(FT1)) {
        T0 = 0x01;
        env->fpscr[4] |= 0x1;
        env->fpscr[6] |= 0x1;
    } else if (FT0 < FT1) {
        T0 = 0x08;
    } else if (FT0 > FT1) {
        T0 = 0x04;
    } else {
        T0 = 0x02;
    }
    env->fpscr[3] = T0;
}

void do_fcmpo (void)
{
    env->fpscr[4] &= ~0x1;
    if (isnan(FT0) || isnan(FT1)) {
        T0 = 0x01;
        env->fpscr[4] |= 0x1;
        /* I don't know how to test "quiet" nan... */
        if (0 /* || ! quiet_nan(...) */) {
            env->fpscr[6] |= 0x1;
            if (!(env->fpscr[1] & 0x8))
                env->fpscr[4] |= 0x8;
        } else {
            env->fpscr[4] |= 0x8;
        }
    } else if (FT0 < FT1) {
        T0 = 0x08;
    } else if (FT0 > FT1) {
        T0 = 0x04;
    } else {
        T0 = 0x02;
    }
    env->fpscr[3] = T0;
}

void do_fabs (void)
{
    FT0 = fabsl(FT0);
}

void do_fnabs (void)
{
    FT0 = -fabsl(FT0);
}

/* Instruction cache invalidation helper */
#define ICACHE_LINE_SIZE 32

void do_check_reservation (void)
{
    if ((env->reserve & ~0x03) == T0)
        env->reserve = -1;
}

void do_icbi (void)
{
    /* Invalidate one cache line */
    T0 &= ~(ICACHE_LINE_SIZE - 1);
    tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE);
}

/* TLB invalidation helpers */
void do_tlbia (void)
{
    tlb_flush(env, 1);
}

void do_tlbie (void)
{
    tlb_flush_page(env, T0);
}

void do_store_sr (uint32_t srnum)
{
#if defined (DEBUG_OP)
    dump_store_sr(srnum);
#endif
#if 0 // TRY
    {
        uint32_t base, page;
        
        base = srnum << 28;
        for (page = base; page != base + 0x100000000; page += 0x1000)
            tlb_flush_page(env, page);
    }
#else
    tlb_flush(env, 1);
#endif
    env->sr[srnum] = T0;
}

/* For BATs, we may not invalidate any TLBs if the change is only on
 * protection bits for user mode.
 */
void do_store_ibat (int ul, int nr)
{
#if defined (DEBUG_OP)
    dump_store_ibat(ul, nr);
#endif
#if 0 // TRY
    {
        uint32_t base, length, page;

        base = env->IBAT[0][nr];
        length = (((base >> 2) & 0x000007FF) + 1) << 17;
        base &= 0xFFFC0000;
        for (page = base; page != base + length; page += 0x1000)
            tlb_flush_page(env, page);
    }
#else
    tlb_flush(env, 1);
#endif
    env->IBAT[ul][nr] = T0;
}

void do_store_dbat (int ul, int nr)
{
#if defined (DEBUG_OP)
    dump_store_dbat(ul, nr);
#endif
#if 0 // TRY
    {
        uint32_t base, length, page;
        base = env->DBAT[0][nr];
        length = (((base >> 2) & 0x000007FF) + 1) << 17;
        base &= 0xFFFC0000;
        for (page = base; page != base + length; page += 0x1000)
            tlb_flush_page(env, page);
    }
#else
    tlb_flush(env, 1);
#endif
    env->DBAT[ul][nr] = T0;
}

/*****************************************************************************/
/* Special helpers for debug */
void dump_state (void)
{
    //    cpu_dump_state(env, stdout, fprintf, 0);
}

void dump_rfi (void)
{
#if 0
    printf("Return from interrupt => 0x%08x\n", env->nip);
    //    cpu_dump_state(env, stdout, fprintf, 0);
#endif
}

void dump_store_sr (int srnum)
{
#if 0
    printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
#endif
}

static void _dump_store_bat (char ID, int ul, int nr)
{
    printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
           ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip);
}

void dump_store_ibat (int ul, int nr)
{
    _dump_store_bat('I', ul, nr);
}

void dump_store_dbat (int ul, int nr)
{
    _dump_store_bat('D', ul, nr);
}

void dump_store_tb (int ul)
{
    printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0);
}

void dump_update_tb(uint32_t param)
{
#if 0
    printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
#endif
}
Commit	Line	Data
9a64fbe4 FB	1	/*
	2	* PPC emulation helpers for qemu.
	3	*
	4	* Copyright (c) 2003 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#include <math.h>
	21	#include "exec.h"
	22
9a64fbe4 FB	23	#define MEMSUFFIX _raw
9a64fbe4 FB	24	#include "op_helper_mem.h"
a541f297	25	#if !defined(CONFIG_USER_ONLY)
9a64fbe4 FB	26	#define MEMSUFFIX _user
	27	#include "op_helper_mem.h"
	28	#define MEMSUFFIX _kernel
	29	#include "op_helper_mem.h"
	30	#endif
	31
	32	/*****************************************************************************/
	33	/* Exceptions processing helpers */
9fddaa0c	34	void cpu_loop_exit(void)
9a64fbe4	35	{
9fddaa0c	36	longjmp(env->jmp_env, 1);
9a64fbe4 FB	37	}
9a64fbe4 FB	38
9fddaa0c	39	void do_raise_exception_err (uint32_t exception, int error_code)
9a64fbe4	40	{
9fddaa0c FB	41	#if 0
	42	printf("Raise exception %3x code : %d\n", exception, error_code);
	43	#endif
	44	switch (exception) {
	45	case EXCP_EXTERNAL:
	46	case EXCP_DECR:
	47	printf("DECREMENTER & EXTERNAL exceptions should be hard interrupts !\n");
	48	if (msr_ee == 0)
	49	return;
	50	break;
	51	case EXCP_PROGRAM:
	52	if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
	53	return;
	54	break;
	55	default:
	56	break;
9a64fbe4	57	}
9fddaa0c FB	58	env->exception_index = exception;
9fddaa0c FB	59	env->error_code = error_code;
9a64fbe4 FB	60	cpu_loop_exit();
9a64fbe4 FB	61	}
9fddaa0c FB	62
	63	void do_raise_exception (uint32_t exception)
	64	{
	65	do_raise_exception_err(exception, 0);
9a64fbe4 FB	66	}
	67
	68	/*****************************************************************************/
	69	/* Helpers for "fat" micro operations */
	70	/* Special registers load and store */
	71	void do_load_cr (void)
	72	{
	73	T0 = (env->crf[0] << 28) \|
	74	(env->crf[1] << 24) \|
	75	(env->crf[2] << 20) \|
	76	(env->crf[3] << 16) \|
	77	(env->crf[4] << 12) \|
	78	(env->crf[5] << 8) \|
	79	(env->crf[6] << 4) \|
	80	(env->crf[7] << 0);
	81	}
	82
	83	void do_store_cr (uint32_t mask)
	84	{
	85	int i, sh;
	86
	87	for (i = 0, sh = 7; i < 8; i++, sh --) {
	88	if (mask & (1 << sh))
	89	env->crf[i] = (T0 >> (sh * 4)) & 0xF;
	90	}
	91	}
	92
	93	void do_load_xer (void)
	94	{
	95	T0 = (xer_so << XER_SO) \|
	96	(xer_ov << XER_OV) \|
	97	(xer_ca << XER_CA) \|
	98	(xer_bc << XER_BC);
	99	}
	100
	101	void do_store_xer (void)
	102	{
	103	xer_so = (T0 >> XER_SO) & 0x01;
	104	xer_ov = (T0 >> XER_OV) & 0x01;
	105	xer_ca = (T0 >> XER_CA) & 0x01;
	106	xer_bc = (T0 >> XER_BC) & 0x1f;
	107	}
	108
	109	void do_load_msr (void)
	110	{
	111	T0 = (msr_pow << MSR_POW) \|
	112	(msr_ile << MSR_ILE) \|
	113	(msr_ee << MSR_EE) \|
	114	(msr_pr << MSR_PR) \|
	115	(msr_fp << MSR_FP) \|
	116	(msr_me << MSR_ME) \|
	117	(msr_fe0 << MSR_FE0) \|
	118	(msr_se << MSR_SE) \|
	119	(msr_be << MSR_BE) \|
	120	(msr_fe1 << MSR_FE1) \|
	121	(msr_ip << MSR_IP) \|
	122	(msr_ir << MSR_IR) \|
	123	(msr_dr << MSR_DR) \|
	124	(msr_ri << MSR_RI) \|
	125	(msr_le << MSR_LE);
	126	}
	127
	128	void do_store_msr (void)
	129	{
4b3686fa	130	#if 1 // TRY
9a64fbe4	131	if (((T0 >> MSR_IR) & 0x01) != msr_ir \|\|
4b3686fa FB	132	((T0 >> MSR_DR) & 0x01) != msr_dr \|\|
	133	((T0 >> MSR_PR) & 0x01) != msr_pr)
	134	{
9a64fbe4 FB	135	do_tlbia();
9a64fbe4 FB	136	}
4b3686fa	137	#endif
9a64fbe4 FB	138	msr_pow = (T0 >> MSR_POW) & 0x03;
	139	msr_ile = (T0 >> MSR_ILE) & 0x01;
	140	msr_ee = (T0 >> MSR_EE) & 0x01;
	141	msr_pr = (T0 >> MSR_PR) & 0x01;
	142	msr_fp = (T0 >> MSR_FP) & 0x01;
	143	msr_me = (T0 >> MSR_ME) & 0x01;
	144	msr_fe0 = (T0 >> MSR_FE0) & 0x01;
	145	msr_se = (T0 >> MSR_SE) & 0x01;
	146	msr_be = (T0 >> MSR_BE) & 0x01;
	147	msr_fe1 = (T0 >> MSR_FE1) & 0x01;
	148	msr_ip = (T0 >> MSR_IP) & 0x01;
	149	msr_ir = (T0 >> MSR_IR) & 0x01;
	150	msr_dr = (T0 >> MSR_DR) & 0x01;
	151	msr_ri = (T0 >> MSR_RI) & 0x01;
	152	msr_le = (T0 >> MSR_LE) & 0x01;
	153	}
	154
	155	/* shift right arithmetic helper */
	156	void do_sraw (void)
	157	{
	158	int32_t ret;
	159
	160	xer_ca = 0;
	161	if (T1 & 0x20) {
	162	ret = (-1) * (T0 >> 31);
4b3686fa	163	if (ret < 0 && (T0 & ~0x80000000) != 0)
9a64fbe4	164	xer_ca = 1;
4b3686fa FB	165	#if 1 // TRY
	166	} else if (T1 == 0) {
	167	ret = T0;
	168	#endif
9a64fbe4 FB	169	} else {
	170	ret = (int32_t)T0 >> (T1 & 0x1f);
	171	if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0)
	172	xer_ca = 1;
	173	}
4b3686fa	174	T0 = ret;
9a64fbe4 FB	175	}
	176
	177	/* Floating point operations helpers */
	178	void do_load_fpscr (void)
	179	{
	180	/* The 32 MSB of the target fpr are undefined.
	181	* They'll be zero...
	182	*/
	183	union {
	184	double d;
	185	struct {
	186	uint32_t u[2];
	187	} s;
	188	} u;
	189	int i;
	190
3cc62370 FB	191	#ifdef WORDS_BIGENDIAN
	192	#define WORD0 0
	193	#define WORD1 1
	194	#else
	195	#define WORD0 1
	196	#define WORD1 0
	197	#endif
	198	u.s.u[WORD0] = 0;
	199	u.s.u[WORD1] = 0;
9a64fbe4	200	for (i = 0; i < 8; i++)
3cc62370	201	u.s.u[WORD1] \|= env->fpscr[i] << (4 * i);
9a64fbe4 FB	202	FT0 = u.d;
	203	}
	204
	205	void do_store_fpscr (uint32_t mask)
	206	{
	207	/*
	208	* We use only the 32 LSB of the incoming fpr
	209	*/
	210	union {
	211	double d;
	212	struct {
	213	uint32_t u[2];
	214	} s;
	215	} u;
	216	int i;
	217
	218	u.d = FT0;
	219	if (mask & 0x80)
3cc62370	220	env->fpscr[0] = (env->fpscr[0] & 0x9) \| ((u.s.u[WORD1] >> 28) & ~0x9);
9a64fbe4 FB	221	for (i = 1; i < 7; i++) {
9a64fbe4 FB	222	if (mask & (1 << (7 - i)))
3cc62370	223	env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
9a64fbe4 FB	224	}
	225	/* TODO: update FEX & VX */
	226	/* Set rounding mode */
	227	switch (env->fpscr[0] & 0x3) {
	228	case 0:
	229	/* Best approximation (round to nearest) */
	230	fesetround(FE_TONEAREST);
	231	break;
	232	case 1:
	233	/* Smaller magnitude (round toward zero) */
	234	fesetround(FE_TOWARDZERO);
	235	break;
	236	case 2:
	237	/* Round toward +infinite */
	238	fesetround(FE_UPWARD);
	239	break;
	240	case 3:
	241	/* Round toward -infinite */
	242	fesetround(FE_DOWNWARD);
	243	break;
	244	}
	245	}
	246
	247	void do_fctiw (void)
	248	{
	249	union {
	250	double d;
	251	uint64_t i;
	252	} p = (void )&FT1;
	253
	254	if (FT0 > (double)0x7FFFFFFF)
	255	p->i = 0x7FFFFFFFULL << 32;
	256	else if (FT0 < -(double)0x80000000)
	257	p->i = 0x80000000ULL << 32;
	258	else
	259	p->i = 0;
	260	p->i \|= (uint32_t)FT0;
	261	FT0 = p->d;
	262	}
	263
	264	void do_fctiwz (void)
	265	{
	266	union {
	267	double d;
	268	uint64_t i;
	269	} p = (void )&FT1;
	270	int cround = fegetround();
	271
	272	fesetround(FE_TOWARDZERO);
	273	if (FT0 > (double)0x7FFFFFFF)
	274	p->i = 0x7FFFFFFFULL << 32;
	275	else if (FT0 < -(double)0x80000000)
	276	p->i = 0x80000000ULL << 32;
	277	else
	278	p->i = 0;
	279	p->i \|= (uint32_t)FT0;
	280	FT0 = p->d;
	281	fesetround(cround);
	282	}
	283
4b3686fa FB	284	void do_fnmadd (void)
	285	{
	286	FT0 = -((FT0 * FT1) + FT2);
	287	}
	288
	289	void do_fnmsub (void)
	290	{
	291	FT0 = -((FT0 * FT1) - FT2);
	292	}
	293
1ef59d0a FB	294	void do_fnmadds (void)
1ef59d0a FB	295	{
4b3686fa	296	FT0 = -((FTS0 * FTS1) + FTS2);
1ef59d0a FB	297	}
	298
	299	void do_fnmsubs (void)
	300	{
4b3686fa	301	FT0 = -((FTS0 * FTS1) - FTS2);
1ef59d0a FB	302	}
1ef59d0a FB	303
9a64fbe4 FB	304	void do_fsqrt (void)
	305	{
	306	FT0 = sqrt(FT0);
	307	}
	308
	309	void do_fsqrts (void)
	310	{
	311	FT0 = (float)sqrt((float)FT0);
	312	}
	313
	314	void do_fres (void)
	315	{
	316	FT0 = 1.0 / FT0;
	317	}
	318
	319	void do_fsqrte (void)
	320	{
	321	FT0 = 1.0 / sqrt(FT0);
	322	}
	323
	324	void do_fsel (void)
	325	{
	326	if (FT0 >= 0)
	327	FT0 = FT2;
	328	else
	329	FT0 = FT1;
	330	}
	331
	332	void do_fcmpu (void)
	333	{
9a64fbe4 FB	334	if (isnan(FT0) \|\| isnan(FT1)) {
	335	T0 = 0x01;
	336	env->fpscr[4] \|= 0x1;
	337	env->fpscr[6] \|= 0x1;
	338	} else if (FT0 < FT1) {
	339	T0 = 0x08;
	340	} else if (FT0 > FT1) {
	341	T0 = 0x04;
	342	} else {
	343	T0 = 0x02;
	344	}
4b3686fa	345	env->fpscr[3] = T0;
9a64fbe4 FB	346	}
	347
	348	void do_fcmpo (void)
	349	{
	350	env->fpscr[4] &= ~0x1;
	351	if (isnan(FT0) \|\| isnan(FT1)) {
	352	T0 = 0x01;
	353	env->fpscr[4] \|= 0x1;
	354	/* I don't know how to test "quiet" nan... */
	355	if (0 /* \|\| ! quiet_nan(...) */) {
	356	env->fpscr[6] \|= 0x1;
	357	if (!(env->fpscr[1] & 0x8))
	358	env->fpscr[4] \|= 0x8;
	359	} else {
	360	env->fpscr[4] \|= 0x8;
	361	}
	362	} else if (FT0 < FT1) {
	363	T0 = 0x08;
	364	} else if (FT0 > FT1) {
	365	T0 = 0x04;
	366	} else {
	367	T0 = 0x02;
	368	}
4b3686fa	369	env->fpscr[3] = T0;
9a64fbe4 FB	370	}
	371
	372	void do_fabs (void)
	373	{
	374	FT0 = fabsl(FT0);
	375	}
	376
	377	void do_fnabs (void)
	378	{
	379	FT0 = -fabsl(FT0);
	380	}
	381
	382	/* Instruction cache invalidation helper */
985a19d6 FB	383	#define ICACHE_LINE_SIZE 32
985a19d6 FB	384
4b3686fa FB	385	void do_check_reservation (void)
4b3686fa FB	386	{
18fba28c	387	if ((env->reserve & ~0x03) == T0)
4b3686fa FB	388	env->reserve = -1;
	389	}
	390
9a64fbe4 FB	391	void do_icbi (void)
9a64fbe4 FB	392	{
985a19d6 FB	393	/* Invalidate one cache line */
	394	T0 &= ~(ICACHE_LINE_SIZE - 1);
	395	tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE);
9a64fbe4 FB	396	}
	397
	398	/* TLB invalidation helpers */
	399	void do_tlbia (void)
	400	{
ad081323	401	tlb_flush(env, 1);
9a64fbe4 FB	402	}
	403
	404	void do_tlbie (void)
	405	{
	406	tlb_flush_page(env, T0);
	407	}
	408
4b3686fa FB	409	void do_store_sr (uint32_t srnum)
	410	{
	411	#if defined (DEBUG_OP)
	412	dump_store_sr(srnum);
	413	#endif
	414	#if 0 // TRY
	415	{
	416	uint32_t base, page;
	417
	418	base = srnum << 28;
	419	for (page = base; page != base + 0x100000000; page += 0x1000)
	420	tlb_flush_page(env, page);
	421	}
	422	#else
	423	tlb_flush(env, 1);
	424	#endif
	425	env->sr[srnum] = T0;
	426	}
	427
	428	/* For BATs, we may not invalidate any TLBs if the change is only on
	429	* protection bits for user mode.
	430	*/
	431	void do_store_ibat (int ul, int nr)
	432	{
	433	#if defined (DEBUG_OP)
	434	dump_store_ibat(ul, nr);
	435	#endif
	436	#if 0 // TRY
	437	{
	438	uint32_t base, length, page;
	439
	440	base = env->IBAT[0][nr];
	441	length = (((base >> 2) & 0x000007FF) + 1) << 17;
	442	base &= 0xFFFC0000;
	443	for (page = base; page != base + length; page += 0x1000)
	444	tlb_flush_page(env, page);
	445	}
	446	#else
	447	tlb_flush(env, 1);
	448	#endif
	449	env->IBAT[ul][nr] = T0;
	450	}
	451
	452	void do_store_dbat (int ul, int nr)
	453	{
	454	#if defined (DEBUG_OP)
	455	dump_store_dbat(ul, nr);
	456	#endif
	457	#if 0 // TRY
	458	{
	459	uint32_t base, length, page;
	460	base = env->DBAT[0][nr];
	461	length = (((base >> 2) & 0x000007FF) + 1) << 17;
	462	base &= 0xFFFC0000;
	463	for (page = base; page != base + length; page += 0x1000)
	464	tlb_flush_page(env, page);
	465	}
	466	#else
	467	tlb_flush(env, 1);
	468	#endif
	469	env->DBAT[ul][nr] = T0;
	470	}
	471
9a64fbe4 FB	472	/*****************************************************************************/
9a64fbe4 FB	473	/* Special helpers for debug */
a541f297 FB	474	void dump_state (void)
a541f297 FB	475	{
7fe48483	476	// cpu_dump_state(env, stdout, fprintf, 0);
a541f297 FB	477	}
a541f297 FB	478
9a64fbe4 FB	479	void dump_rfi (void)
	480	{
	481	#if 0
4b3686fa	482	printf("Return from interrupt => 0x%08x\n", env->nip);
7fe48483	483	// cpu_dump_state(env, stdout, fprintf, 0);
9a64fbe4 FB	484	#endif
	485	}
	486
	487	void dump_store_sr (int srnum)
	488	{
	489	#if 0
	490	printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
	491	#endif
	492	}
	493
	494	static void _dump_store_bat (char ID, int ul, int nr)
	495	{
	496	printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
	497	ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip);
	498	}
	499
	500	void dump_store_ibat (int ul, int nr)
	501	{
	502	_dump_store_bat('I', ul, nr);
	503	}
	504
	505	void dump_store_dbat (int ul, int nr)
	506	{
	507	_dump_store_bat('D', ul, nr);
	508	}
	509
	510	void dump_store_tb (int ul)
	511	{
	512	printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0);
	513	}
	514
	515	void dump_update_tb(uint32_t param)
	516	{
	517	#if 0
	518	printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
	519	#endif
	520	}
	521