]>
Commit | Line | Data |
---|---|---|
6de673d4 BS |
1 | /* |
2 | * PowerPC emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0d75590d | 19 | #include "qemu/osdep.h" |
6de673d4 | 20 | #include "cpu.h" |
2ef6175a | 21 | #include "exec/helper-proto.h" |
63c91552 | 22 | #include "qemu/log.h" |
6de673d4 BS |
23 | |
24 | /*****************************************************************************/ | |
25 | /* SPR accesses */ | |
26 | ||
d0f1562d | 27 | target_ulong helper_load_tbl(CPUPPCState *env) |
6de673d4 BS |
28 | { |
29 | return (target_ulong)cpu_ppc_load_tbl(env); | |
30 | } | |
31 | ||
d0f1562d | 32 | target_ulong helper_load_tbu(CPUPPCState *env) |
6de673d4 BS |
33 | { |
34 | return cpu_ppc_load_tbu(env); | |
35 | } | |
36 | ||
d0f1562d | 37 | target_ulong helper_load_atbl(CPUPPCState *env) |
6de673d4 BS |
38 | { |
39 | return (target_ulong)cpu_ppc_load_atbl(env); | |
40 | } | |
41 | ||
d0f1562d | 42 | target_ulong helper_load_atbu(CPUPPCState *env) |
6de673d4 BS |
43 | { |
44 | return cpu_ppc_load_atbu(env); | |
45 | } | |
46 | ||
47 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) | |
d0f1562d | 48 | target_ulong helper_load_purr(CPUPPCState *env) |
6de673d4 BS |
49 | { |
50 | return (target_ulong)cpu_ppc_load_purr(env); | |
51 | } | |
52 | #endif | |
53 | ||
d0f1562d | 54 | target_ulong helper_load_601_rtcl(CPUPPCState *env) |
6de673d4 BS |
55 | { |
56 | return cpu_ppc601_load_rtcl(env); | |
57 | } | |
58 | ||
d0f1562d | 59 | target_ulong helper_load_601_rtcu(CPUPPCState *env) |
6de673d4 BS |
60 | { |
61 | return cpu_ppc601_load_rtcu(env); | |
62 | } | |
63 | ||
64 | #if !defined(CONFIG_USER_ONLY) | |
d0f1562d | 65 | void helper_store_tbl(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
66 | { |
67 | cpu_ppc_store_tbl(env, val); | |
68 | } | |
69 | ||
d0f1562d | 70 | void helper_store_tbu(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
71 | { |
72 | cpu_ppc_store_tbu(env, val); | |
73 | } | |
74 | ||
d0f1562d | 75 | void helper_store_atbl(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
76 | { |
77 | cpu_ppc_store_atbl(env, val); | |
78 | } | |
79 | ||
d0f1562d | 80 | void helper_store_atbu(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
81 | { |
82 | cpu_ppc_store_atbu(env, val); | |
83 | } | |
84 | ||
d0f1562d | 85 | void helper_store_601_rtcl(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
86 | { |
87 | cpu_ppc601_store_rtcl(env, val); | |
88 | } | |
89 | ||
d0f1562d | 90 | void helper_store_601_rtcu(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
91 | { |
92 | cpu_ppc601_store_rtcu(env, val); | |
93 | } | |
94 | ||
d0f1562d | 95 | target_ulong helper_load_decr(CPUPPCState *env) |
6de673d4 BS |
96 | { |
97 | return cpu_ppc_load_decr(env); | |
98 | } | |
99 | ||
d0f1562d | 100 | void helper_store_decr(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
101 | { |
102 | cpu_ppc_store_decr(env, val); | |
103 | } | |
104 | ||
d0f1562d | 105 | target_ulong helper_load_40x_pit(CPUPPCState *env) |
6de673d4 BS |
106 | { |
107 | return load_40x_pit(env); | |
108 | } | |
109 | ||
d0f1562d | 110 | void helper_store_40x_pit(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
111 | { |
112 | store_40x_pit(env, val); | |
113 | } | |
114 | ||
d0f1562d | 115 | void helper_store_booke_tcr(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
116 | { |
117 | store_booke_tcr(env, val); | |
118 | } | |
119 | ||
d0f1562d | 120 | void helper_store_booke_tsr(CPUPPCState *env, target_ulong val) |
6de673d4 BS |
121 | { |
122 | store_booke_tsr(env, val); | |
123 | } | |
124 | #endif | |
125 | ||
126 | /*****************************************************************************/ | |
127 | /* Embedded PowerPC specific helpers */ | |
128 | ||
129 | /* XXX: to be improved to check access rights when in user-mode */ | |
d0f1562d | 130 | target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn) |
6de673d4 BS |
131 | { |
132 | uint32_t val = 0; | |
133 | ||
134 | if (unlikely(env->dcr_env == NULL)) { | |
48880da6 | 135 | qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); |
6de673d4 BS |
136 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
137 | POWERPC_EXCP_INVAL | | |
138 | POWERPC_EXCP_INVAL_INVAL); | |
139 | } else if (unlikely(ppc_dcr_read(env->dcr_env, | |
140 | (uint32_t)dcrn, &val) != 0)) { | |
48880da6 PB |
141 | qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n", |
142 | (uint32_t)dcrn, (uint32_t)dcrn); | |
6de673d4 BS |
143 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
144 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); | |
145 | } | |
146 | return val; | |
147 | } | |
148 | ||
d0f1562d | 149 | void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val) |
6de673d4 BS |
150 | { |
151 | if (unlikely(env->dcr_env == NULL)) { | |
48880da6 | 152 | qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n"); |
6de673d4 BS |
153 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
154 | POWERPC_EXCP_INVAL | | |
155 | POWERPC_EXCP_INVAL_INVAL); | |
156 | } else if (unlikely(ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, | |
157 | (uint32_t)val) != 0)) { | |
48880da6 PB |
158 | qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n", |
159 | (uint32_t)dcrn, (uint32_t)dcrn); | |
6de673d4 BS |
160 | helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, |
161 | POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG); | |
162 | } | |
163 | } |