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target-ppc: add vector extract instructions
[mirror_qemu.git] / target-ppc / translate / vmx-impl.inc.c
CommitLineData
0304af89
BH		 1/*
2 * translate/vmx-impl.c
3 *
4 * Altivec/VMX translation
5 */
6
7/*** Altivec vector extension ***/
8/* Altivec registers moves */
9
10static inline TCGv_ptr gen_avr_ptr(int reg)
11{
12 TCGv_ptr r = tcg_temp_new_ptr();
13 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
14 return r;
15}
16
17#define GEN_VR_LDX(name, opc2, opc3) \
18static void glue(gen_, name)(DisasContext *ctx) \
19{ \
20 TCGv EA; \
21 if (unlikely(!ctx->altivec_enabled)) { \
22 gen_exception(ctx, POWERPC_EXCP_VPU); \
23 return; \
24 } \
25 gen_set_access_type(ctx, ACCESS_INT); \
26 EA = tcg_temp_new(); \
27 gen_addr_reg_index(ctx, EA); \
28 tcg_gen_andi_tl(EA, EA, ~0xf); \
29 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
30 64-bit byteswap already. */ \
31 if (ctx->le_mode) { \
32 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
33 tcg_gen_addi_tl(EA, EA, 8); \
34 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
35 } else { \
36 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
37 tcg_gen_addi_tl(EA, EA, 8); \
38 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
39 } \
40 tcg_temp_free(EA); \
41}
42
43#define GEN_VR_STX(name, opc2, opc3) \
44static void gen_st##name(DisasContext *ctx) \
45{ \
46 TCGv EA; \
47 if (unlikely(!ctx->altivec_enabled)) { \
48 gen_exception(ctx, POWERPC_EXCP_VPU); \
49 return; \
50 } \
51 gen_set_access_type(ctx, ACCESS_INT); \
52 EA = tcg_temp_new(); \
53 gen_addr_reg_index(ctx, EA); \
54 tcg_gen_andi_tl(EA, EA, ~0xf); \
55 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
56 64-bit byteswap already. */ \
57 if (ctx->le_mode) { \
58 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
59 tcg_gen_addi_tl(EA, EA, 8); \
60 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
61 } else { \
62 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
63 tcg_gen_addi_tl(EA, EA, 8); \
64 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
65 } \
66 tcg_temp_free(EA); \
67}
68
69#define GEN_VR_LVE(name, opc2, opc3, size) \
70static void gen_lve##name(DisasContext *ctx) \
71 { \
72 TCGv EA; \
73 TCGv_ptr rs; \
74 if (unlikely(!ctx->altivec_enabled)) { \
75 gen_exception(ctx, POWERPC_EXCP_VPU); \
76 return; \
77 } \
78 gen_set_access_type(ctx, ACCESS_INT); \
79 EA = tcg_temp_new(); \
80 gen_addr_reg_index(ctx, EA); \
81 if (size > 1) { \
82 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
83 } \
84 rs = gen_avr_ptr(rS(ctx->opcode)); \
85 gen_helper_lve##name(cpu_env, rs, EA); \
86 tcg_temp_free(EA); \
87 tcg_temp_free_ptr(rs); \
88 }
89
90#define GEN_VR_STVE(name, opc2, opc3, size) \
91static void gen_stve##name(DisasContext *ctx) \
92 { \
93 TCGv EA; \
94 TCGv_ptr rs; \
95 if (unlikely(!ctx->altivec_enabled)) { \
96 gen_exception(ctx, POWERPC_EXCP_VPU); \
97 return; \
98 } \
99 gen_set_access_type(ctx, ACCESS_INT); \
100 EA = tcg_temp_new(); \
101 gen_addr_reg_index(ctx, EA); \
102 if (size > 1) { \
103 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
104 } \
105 rs = gen_avr_ptr(rS(ctx->opcode)); \
106 gen_helper_stve##name(cpu_env, rs, EA); \
107 tcg_temp_free(EA); \
108 tcg_temp_free_ptr(rs); \
109 }
110
111GEN_VR_LDX(lvx, 0x07, 0x03);
112/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
113GEN_VR_LDX(lvxl, 0x07, 0x0B);
114
115GEN_VR_LVE(bx, 0x07, 0x00, 1);
116GEN_VR_LVE(hx, 0x07, 0x01, 2);
117GEN_VR_LVE(wx, 0x07, 0x02, 4);
118
119GEN_VR_STX(svx, 0x07, 0x07);
120/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
121GEN_VR_STX(svxl, 0x07, 0x0F);
122
123GEN_VR_STVE(bx, 0x07, 0x04, 1);
124GEN_VR_STVE(hx, 0x07, 0x05, 2);
125GEN_VR_STVE(wx, 0x07, 0x06, 4);
126
127static void gen_lvsl(DisasContext *ctx)
128{
129 TCGv_ptr rd;
130 TCGv EA;
131 if (unlikely(!ctx->altivec_enabled)) {
132 gen_exception(ctx, POWERPC_EXCP_VPU);
133 return;
134 }
135 EA = tcg_temp_new();
136 gen_addr_reg_index(ctx, EA);
137 rd = gen_avr_ptr(rD(ctx->opcode));
138 gen_helper_lvsl(rd, EA);
139 tcg_temp_free(EA);
140 tcg_temp_free_ptr(rd);
141}
142
143static void gen_lvsr(DisasContext *ctx)
144{
145 TCGv_ptr rd;
146 TCGv EA;
147 if (unlikely(!ctx->altivec_enabled)) {
148 gen_exception(ctx, POWERPC_EXCP_VPU);
149 return;
150 }
151 EA = tcg_temp_new();
152 gen_addr_reg_index(ctx, EA);
153 rd = gen_avr_ptr(rD(ctx->opcode));
154 gen_helper_lvsr(rd, EA);
155 tcg_temp_free(EA);
156 tcg_temp_free_ptr(rd);
157}
158
159static void gen_mfvscr(DisasContext *ctx)
160{
161 TCGv_i32 t;
162 if (unlikely(!ctx->altivec_enabled)) {
163 gen_exception(ctx, POWERPC_EXCP_VPU);
164 return;
165 }
166 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
167 t = tcg_temp_new_i32();
168 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
169 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
170 tcg_temp_free_i32(t);
171}
172
173static void gen_mtvscr(DisasContext *ctx)
174{
175 TCGv_ptr p;
176 if (unlikely(!ctx->altivec_enabled)) {
177 gen_exception(ctx, POWERPC_EXCP_VPU);
178 return;
179 }
180 p = gen_avr_ptr(rB(ctx->opcode));
181 gen_helper_mtvscr(cpu_env, p);
182 tcg_temp_free_ptr(p);
183}
184
185/* Logical operations */
186#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
187static void glue(gen_, name)(DisasContext *ctx) \
188{ \
189 if (unlikely(!ctx->altivec_enabled)) { \
190 gen_exception(ctx, POWERPC_EXCP_VPU); \
191 return; \
192 } \
193 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
194 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
195}
196
197GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
198GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
199GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
200GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
201GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
202GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
203GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
204GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
205
206#define GEN_VXFORM(name, opc2, opc3) \
207static void glue(gen_, name)(DisasContext *ctx) \
208{ \
209 TCGv_ptr ra, rb, rd; \
210 if (unlikely(!ctx->altivec_enabled)) { \
211 gen_exception(ctx, POWERPC_EXCP_VPU); \
212 return; \
213 } \
214 ra = gen_avr_ptr(rA(ctx->opcode)); \
215 rb = gen_avr_ptr(rB(ctx->opcode)); \
216 rd = gen_avr_ptr(rD(ctx->opcode)); \
217 gen_helper_##name (rd, ra, rb); \
218 tcg_temp_free_ptr(ra); \
219 tcg_temp_free_ptr(rb); \
220 tcg_temp_free_ptr(rd); \
221}
222
223#define GEN_VXFORM_ENV(name, opc2, opc3) \
224static void glue(gen_, name)(DisasContext *ctx) \
225{ \
226 TCGv_ptr ra, rb, rd; \
227 if (unlikely(!ctx->altivec_enabled)) { \
228 gen_exception(ctx, POWERPC_EXCP_VPU); \
229 return; \
230 } \
231 ra = gen_avr_ptr(rA(ctx->opcode)); \
232 rb = gen_avr_ptr(rB(ctx->opcode)); \
233 rd = gen_avr_ptr(rD(ctx->opcode)); \
234 gen_helper_##name(cpu_env, rd, ra, rb); \
235 tcg_temp_free_ptr(ra); \
236 tcg_temp_free_ptr(rb); \
237 tcg_temp_free_ptr(rd); \
238}
239
240#define GEN_VXFORM3(name, opc2, opc3) \
241static void glue(gen_, name)(DisasContext *ctx) \
242{ \
243 TCGv_ptr ra, rb, rc, rd; \
244 if (unlikely(!ctx->altivec_enabled)) { \
245 gen_exception(ctx, POWERPC_EXCP_VPU); \
246 return; \
247 } \
248 ra = gen_avr_ptr(rA(ctx->opcode)); \
249 rb = gen_avr_ptr(rB(ctx->opcode)); \
250 rc = gen_avr_ptr(rC(ctx->opcode)); \
251 rd = gen_avr_ptr(rD(ctx->opcode)); \
252 gen_helper_##name(rd, ra, rb, rc); \
253 tcg_temp_free_ptr(ra); \
254 tcg_temp_free_ptr(rb); \
255 tcg_temp_free_ptr(rc); \
256 tcg_temp_free_ptr(rd); \
257}
258
259/*
260 * Support for Altivec instruction pairs that use bit 31 (Rc) as
261 * an opcode bit. In general, these pairs come from different
262 * versions of the ISA, so we must also support a pair of flags for
263 * each instruction.
264 */
265#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
266static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
267{ \
268 if ((Rc(ctx->opcode) == 0) && \
269 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
270 gen_##name0(ctx); \
271 } else if ((Rc(ctx->opcode) == 1) && \
272 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
273 gen_##name1(ctx); \
274 } else { \
275 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
276 } \
277}
278
279GEN_VXFORM(vaddubm, 0, 0);
280GEN_VXFORM(vadduhm, 0, 1);
281GEN_VXFORM(vadduwm, 0, 2);
282GEN_VXFORM(vaddudm, 0, 3);
283GEN_VXFORM(vsububm, 0, 16);
284GEN_VXFORM(vsubuhm, 0, 17);
285GEN_VXFORM(vsubuwm, 0, 18);
286GEN_VXFORM(vsubudm, 0, 19);
287GEN_VXFORM(vmaxub, 1, 0);
288GEN_VXFORM(vmaxuh, 1, 1);
289GEN_VXFORM(vmaxuw, 1, 2);
290GEN_VXFORM(vmaxud, 1, 3);
291GEN_VXFORM(vmaxsb, 1, 4);
292GEN_VXFORM(vmaxsh, 1, 5);
293GEN_VXFORM(vmaxsw, 1, 6);
294GEN_VXFORM(vmaxsd, 1, 7);
295GEN_VXFORM(vminub, 1, 8);
296GEN_VXFORM(vminuh, 1, 9);
297GEN_VXFORM(vminuw, 1, 10);
298GEN_VXFORM(vminud, 1, 11);
299GEN_VXFORM(vminsb, 1, 12);
300GEN_VXFORM(vminsh, 1, 13);
301GEN_VXFORM(vminsw, 1, 14);
302GEN_VXFORM(vminsd, 1, 15);
303GEN_VXFORM(vavgub, 1, 16);
37707059
SD		 304GEN_VXFORM(vabsdub, 1, 16);
305GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
306 vabsdub, PPC_NONE, PPC2_ISA300)
0304af89 307GEN_VXFORM(vavguh, 1, 17);
37707059
SD		 308GEN_VXFORM(vabsduh, 1, 17);
309GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
310 vabsduh, PPC_NONE, PPC2_ISA300)
0304af89 311GEN_VXFORM(vavguw, 1, 18);
37707059
SD		 312GEN_VXFORM(vabsduw, 1, 18);
313GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
314 vabsduw, PPC_NONE, PPC2_ISA300)
0304af89
BH		 315GEN_VXFORM(vavgsb, 1, 20);
316GEN_VXFORM(vavgsh, 1, 21);
317GEN_VXFORM(vavgsw, 1, 22);
318GEN_VXFORM(vmrghb, 6, 0);
319GEN_VXFORM(vmrghh, 6, 1);
320GEN_VXFORM(vmrghw, 6, 2);
321GEN_VXFORM(vmrglb, 6, 4);
322GEN_VXFORM(vmrglh, 6, 5);
323GEN_VXFORM(vmrglw, 6, 6);
324
325static void gen_vmrgew(DisasContext *ctx)
326{
327 TCGv_i64 tmp;
328 int VT, VA, VB;
329 if (unlikely(!ctx->altivec_enabled)) {
330 gen_exception(ctx, POWERPC_EXCP_VPU);
331 return;
332 }
333 VT = rD(ctx->opcode);
334 VA = rA(ctx->opcode);
335 VB = rB(ctx->opcode);
336 tmp = tcg_temp_new_i64();
337 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
338 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
339 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
340 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
341 tcg_temp_free_i64(tmp);
342}
343
344static void gen_vmrgow(DisasContext *ctx)
345{
346 int VT, VA, VB;
347 if (unlikely(!ctx->altivec_enabled)) {
348 gen_exception(ctx, POWERPC_EXCP_VPU);
349 return;
350 }
351 VT = rD(ctx->opcode);
352 VA = rA(ctx->opcode);
353 VB = rB(ctx->opcode);
354
355 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
356 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
357}
358
359GEN_VXFORM(vmuloub, 4, 0);
360GEN_VXFORM(vmulouh, 4, 1);
361GEN_VXFORM(vmulouw, 4, 2);
362GEN_VXFORM(vmuluwm, 4, 2);
363GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
364 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
365GEN_VXFORM(vmulosb, 4, 4);
366GEN_VXFORM(vmulosh, 4, 5);
367GEN_VXFORM(vmulosw, 4, 6);
368GEN_VXFORM(vmuleub, 4, 8);
369GEN_VXFORM(vmuleuh, 4, 9);
370GEN_VXFORM(vmuleuw, 4, 10);
371GEN_VXFORM(vmulesb, 4, 12);
372GEN_VXFORM(vmulesh, 4, 13);
373GEN_VXFORM(vmulesw, 4, 14);
374GEN_VXFORM(vslb, 2, 4);
375GEN_VXFORM(vslh, 2, 5);
376GEN_VXFORM(vslw, 2, 6);
377GEN_VXFORM(vsld, 2, 23);
378GEN_VXFORM(vsrb, 2, 8);
379GEN_VXFORM(vsrh, 2, 9);
380GEN_VXFORM(vsrw, 2, 10);
381GEN_VXFORM(vsrd, 2, 27);
382GEN_VXFORM(vsrab, 2, 12);
383GEN_VXFORM(vsrah, 2, 13);
384GEN_VXFORM(vsraw, 2, 14);
385GEN_VXFORM(vsrad, 2, 15);
4004c1db 386GEN_VXFORM(vsrv, 2, 28);
5644a175 387GEN_VXFORM(vslv, 2, 29);
0304af89
BH		 388GEN_VXFORM(vslo, 6, 16);
389GEN_VXFORM(vsro, 6, 17);
390GEN_VXFORM(vaddcuw, 0, 6);
391GEN_VXFORM(vsubcuw, 0, 22);
392GEN_VXFORM_ENV(vaddubs, 0, 8);
393GEN_VXFORM_ENV(vadduhs, 0, 9);
394GEN_VXFORM_ENV(vadduws, 0, 10);
395GEN_VXFORM_ENV(vaddsbs, 0, 12);
396GEN_VXFORM_ENV(vaddshs, 0, 13);
397GEN_VXFORM_ENV(vaddsws, 0, 14);
398GEN_VXFORM_ENV(vsububs, 0, 24);
399GEN_VXFORM_ENV(vsubuhs, 0, 25);
400GEN_VXFORM_ENV(vsubuws, 0, 26);
401GEN_VXFORM_ENV(vsubsbs, 0, 28);
402GEN_VXFORM_ENV(vsubshs, 0, 29);
403GEN_VXFORM_ENV(vsubsws, 0, 30);
404GEN_VXFORM(vadduqm, 0, 4);
405GEN_VXFORM(vaddcuq, 0, 5);
406GEN_VXFORM3(vaddeuqm, 30, 0);
407GEN_VXFORM3(vaddecuq, 30, 0);
408GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
409 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
410GEN_VXFORM(vsubuqm, 0, 20);
411GEN_VXFORM(vsubcuq, 0, 21);
412GEN_VXFORM3(vsubeuqm, 31, 0);
413GEN_VXFORM3(vsubecuq, 31, 0);
414GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
415 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
416GEN_VXFORM(vrlb, 2, 0);
417GEN_VXFORM(vrlh, 2, 1);
418GEN_VXFORM(vrlw, 2, 2);
419GEN_VXFORM(vrld, 2, 3);
420GEN_VXFORM(vsl, 2, 7);
421GEN_VXFORM(vsr, 2, 11);
422GEN_VXFORM_ENV(vpkuhum, 7, 0);
423GEN_VXFORM_ENV(vpkuwum, 7, 1);
424GEN_VXFORM_ENV(vpkudum, 7, 17);
425GEN_VXFORM_ENV(vpkuhus, 7, 2);
426GEN_VXFORM_ENV(vpkuwus, 7, 3);
427GEN_VXFORM_ENV(vpkudus, 7, 19);
428GEN_VXFORM_ENV(vpkshus, 7, 4);
429GEN_VXFORM_ENV(vpkswus, 7, 5);
430GEN_VXFORM_ENV(vpksdus, 7, 21);
431GEN_VXFORM_ENV(vpkshss, 7, 6);
432GEN_VXFORM_ENV(vpkswss, 7, 7);
433GEN_VXFORM_ENV(vpksdss, 7, 23);
434GEN_VXFORM(vpkpx, 7, 12);
435GEN_VXFORM_ENV(vsum4ubs, 4, 24);
436GEN_VXFORM_ENV(vsum4sbs, 4, 28);
437GEN_VXFORM_ENV(vsum4shs, 4, 25);
438GEN_VXFORM_ENV(vsum2sws, 4, 26);
439GEN_VXFORM_ENV(vsumsws, 4, 30);
440GEN_VXFORM_ENV(vaddfp, 5, 0);
441GEN_VXFORM_ENV(vsubfp, 5, 1);
442GEN_VXFORM_ENV(vmaxfp, 5, 16);
443GEN_VXFORM_ENV(vminfp, 5, 17);
444
445#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
446static void glue(gen_, name)(DisasContext *ctx) \
447 { \
448 TCGv_ptr ra, rb, rd; \
449 if (unlikely(!ctx->altivec_enabled)) { \
450 gen_exception(ctx, POWERPC_EXCP_VPU); \
451 return; \
452 } \
453 ra = gen_avr_ptr(rA(ctx->opcode)); \
454 rb = gen_avr_ptr(rB(ctx->opcode)); \
455 rd = gen_avr_ptr(rD(ctx->opcode)); \
456 gen_helper_##opname(cpu_env, rd, ra, rb); \
457 tcg_temp_free_ptr(ra); \
458 tcg_temp_free_ptr(rb); \
459 tcg_temp_free_ptr(rd); \
460 }
461
462#define GEN_VXRFORM(name, opc2, opc3) \
463 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
464 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
465
466/*
467 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
468 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
469 * come from different versions of the ISA, so we must also support a
470 * pair of flags for each instruction.
471 */
472#define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
473static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
474{ \
475 if ((Rc(ctx->opcode) == 0) && \
476 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
477 if (Rc21(ctx->opcode) == 0) { \
478 gen_##name0(ctx); \
479 } else { \
480 gen_##name0##_(ctx); \
481 } \
482 } else if ((Rc(ctx->opcode) == 1) && \
483 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
484 if (Rc21(ctx->opcode) == 0) { \
485 gen_##name1(ctx); \
486 } else { \
487 gen_##name1##_(ctx); \
488 } \
489 } else { \
490 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
491 } \
492}
493
494GEN_VXRFORM(vcmpequb, 3, 0)
495GEN_VXRFORM(vcmpequh, 3, 1)
496GEN_VXRFORM(vcmpequw, 3, 2)
497GEN_VXRFORM(vcmpequd, 3, 3)
f7cc8466
SB		 498GEN_VXRFORM(vcmpnezb, 3, 4)
499GEN_VXRFORM(vcmpnezh, 3, 5)
500GEN_VXRFORM(vcmpnezw, 3, 6)
0304af89
BH		 501GEN_VXRFORM(vcmpgtsb, 3, 12)
502GEN_VXRFORM(vcmpgtsh, 3, 13)
503GEN_VXRFORM(vcmpgtsw, 3, 14)
504GEN_VXRFORM(vcmpgtsd, 3, 15)
505GEN_VXRFORM(vcmpgtub, 3, 8)
506GEN_VXRFORM(vcmpgtuh, 3, 9)
507GEN_VXRFORM(vcmpgtuw, 3, 10)
508GEN_VXRFORM(vcmpgtud, 3, 11)
509GEN_VXRFORM(vcmpeqfp, 3, 3)
510GEN_VXRFORM(vcmpgefp, 3, 7)
511GEN_VXRFORM(vcmpgtfp, 3, 11)
512GEN_VXRFORM(vcmpbfp, 3, 15)
513
514GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
515 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
516GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
517 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
518GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
519 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
520
521#define GEN_VXFORM_SIMM(name, opc2, opc3) \
522static void glue(gen_, name)(DisasContext *ctx) \
523 { \
524 TCGv_ptr rd; \
525 TCGv_i32 simm; \
526 if (unlikely(!ctx->altivec_enabled)) { \
527 gen_exception(ctx, POWERPC_EXCP_VPU); \
528 return; \
529 } \
530 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
531 rd = gen_avr_ptr(rD(ctx->opcode)); \
532 gen_helper_##name (rd, simm); \
533 tcg_temp_free_i32(simm); \
534 tcg_temp_free_ptr(rd); \
535 }
536
537GEN_VXFORM_SIMM(vspltisb, 6, 12);
538GEN_VXFORM_SIMM(vspltish, 6, 13);
539GEN_VXFORM_SIMM(vspltisw, 6, 14);
540
541#define GEN_VXFORM_NOA(name, opc2, opc3) \
542static void glue(gen_, name)(DisasContext *ctx) \
543 { \
544 TCGv_ptr rb, rd; \
545 if (unlikely(!ctx->altivec_enabled)) { \
546 gen_exception(ctx, POWERPC_EXCP_VPU); \
547 return; \
548 } \
549 rb = gen_avr_ptr(rB(ctx->opcode)); \
550 rd = gen_avr_ptr(rD(ctx->opcode)); \
551 gen_helper_##name (rd, rb); \
552 tcg_temp_free_ptr(rb); \
553 tcg_temp_free_ptr(rd); \
554 }
555
556#define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
557static void glue(gen_, name)(DisasContext *ctx) \
558 { \
559 TCGv_ptr rb, rd; \
560 \
561 if (unlikely(!ctx->altivec_enabled)) { \
562 gen_exception(ctx, POWERPC_EXCP_VPU); \
563 return; \
564 } \
565 rb = gen_avr_ptr(rB(ctx->opcode)); \
566 rd = gen_avr_ptr(rD(ctx->opcode)); \
567 gen_helper_##name(cpu_env, rd, rb); \
568 tcg_temp_free_ptr(rb); \
569 tcg_temp_free_ptr(rd); \
570 }
571
572GEN_VXFORM_NOA(vupkhsb, 7, 8);
573GEN_VXFORM_NOA(vupkhsh, 7, 9);
574GEN_VXFORM_NOA(vupkhsw, 7, 25);
575GEN_VXFORM_NOA(vupklsb, 7, 10);
576GEN_VXFORM_NOA(vupklsh, 7, 11);
577GEN_VXFORM_NOA(vupklsw, 7, 27);
578GEN_VXFORM_NOA(vupkhpx, 7, 13);
579GEN_VXFORM_NOA(vupklpx, 7, 15);
580GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
581GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
582GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
583GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
584GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
585GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
586GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
587GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
588
589#define GEN_VXFORM_SIMM(name, opc2, opc3) \
590static void glue(gen_, name)(DisasContext *ctx) \
591 { \
592 TCGv_ptr rd; \
593 TCGv_i32 simm; \
594 if (unlikely(!ctx->altivec_enabled)) { \
595 gen_exception(ctx, POWERPC_EXCP_VPU); \
596 return; \
597 } \
598 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
599 rd = gen_avr_ptr(rD(ctx->opcode)); \
600 gen_helper_##name (rd, simm); \
601 tcg_temp_free_i32(simm); \
602 tcg_temp_free_ptr(rd); \
603 }
604
605#define GEN_VXFORM_UIMM(name, opc2, opc3) \
606static void glue(gen_, name)(DisasContext *ctx) \
607 { \
608 TCGv_ptr rb, rd; \
609 TCGv_i32 uimm; \
610 if (unlikely(!ctx->altivec_enabled)) { \
611 gen_exception(ctx, POWERPC_EXCP_VPU); \
612 return; \
613 } \
614 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
615 rb = gen_avr_ptr(rB(ctx->opcode)); \
616 rd = gen_avr_ptr(rD(ctx->opcode)); \
617 gen_helper_##name (rd, rb, uimm); \
618 tcg_temp_free_i32(uimm); \
619 tcg_temp_free_ptr(rb); \
620 tcg_temp_free_ptr(rd); \
621 }
622
623#define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
624static void glue(gen_, name)(DisasContext *ctx) \
625 { \
626 TCGv_ptr rb, rd; \
627 TCGv_i32 uimm; \
628 \
629 if (unlikely(!ctx->altivec_enabled)) { \
630 gen_exception(ctx, POWERPC_EXCP_VPU); \
631 return; \
632 } \
633 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
634 rb = gen_avr_ptr(rB(ctx->opcode)); \
635 rd = gen_avr_ptr(rD(ctx->opcode)); \
636 gen_helper_##name(cpu_env, rd, rb, uimm); \
637 tcg_temp_free_i32(uimm); \
638 tcg_temp_free_ptr(rb); \
639 tcg_temp_free_ptr(rd); \
640 }
641
e7b1e06f
RS		 642#define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \
643static void glue(gen_, name)(DisasContext *ctx) \
644 { \
645 TCGv_ptr rb, rd; \
646 uint8_t uimm = UIMM4(ctx->opcode); \
647 TCGv_i32 t0 = tcg_temp_new_i32(); \
648 if (unlikely(!ctx->altivec_enabled)) { \
649 gen_exception(ctx, POWERPC_EXCP_VPU); \
650 return; \
651 } \
652 if (uimm > splat_max) { \
653 uimm = 0; \
654 } \
655 tcg_gen_movi_i32(t0, uimm); \
656 rb = gen_avr_ptr(rB(ctx->opcode)); \
657 rd = gen_avr_ptr(rD(ctx->opcode)); \
658 gen_helper_##name(rd, rb, t0); \
659 tcg_temp_free_i32(t0); \
660 tcg_temp_free_ptr(rb); \
661 tcg_temp_free_ptr(rd); \
662 }
663
0304af89
BH		 664GEN_VXFORM_UIMM(vspltb, 6, 8);
665GEN_VXFORM_UIMM(vsplth, 6, 9);
666GEN_VXFORM_UIMM(vspltw, 6, 10);
b5d569a1
RS		 667GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15);
668GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14);
669GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12);
670GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8);
e7b1e06f
RS		 671GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15);
672GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14);
673GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12);
674GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8);
0304af89
BH		 675GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
676GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
677GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
678GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
b5d569a1
RS		 679GEN_VXFORM_DUAL(vspltb, PPC_NONE, PPC2_ALTIVEC_207,
680 vextractub, PPC_NONE, PPC2_ISA300);
681GEN_VXFORM_DUAL(vsplth, PPC_NONE, PPC2_ALTIVEC_207,
682 vextractuh, PPC_NONE, PPC2_ISA300);
683GEN_VXFORM_DUAL(vspltw, PPC_NONE, PPC2_ALTIVEC_207,
684 vextractuw, PPC_NONE, PPC2_ISA300);
e7b1e06f
RS		 685GEN_VXFORM_DUAL(vspltisb, PPC_NONE, PPC2_ALTIVEC_207,
686 vinsertb, PPC_NONE, PPC2_ISA300);
687GEN_VXFORM_DUAL(vspltish, PPC_NONE, PPC2_ALTIVEC_207,
688 vinserth, PPC_NONE, PPC2_ISA300);
689GEN_VXFORM_DUAL(vspltisw, PPC_NONE, PPC2_ALTIVEC_207,
690 vinsertw, PPC_NONE, PPC2_ISA300);
0304af89
BH		 691
692static void gen_vsldoi(DisasContext *ctx)
693{
694 TCGv_ptr ra, rb, rd;
695 TCGv_i32 sh;
696 if (unlikely(!ctx->altivec_enabled)) {
697 gen_exception(ctx, POWERPC_EXCP_VPU);
698 return;
699 }
700 ra = gen_avr_ptr(rA(ctx->opcode));
701 rb = gen_avr_ptr(rB(ctx->opcode));
702 rd = gen_avr_ptr(rD(ctx->opcode));
703 sh = tcg_const_i32(VSH(ctx->opcode));
704 gen_helper_vsldoi (rd, ra, rb, sh);
705 tcg_temp_free_ptr(ra);
706 tcg_temp_free_ptr(rb);
707 tcg_temp_free_ptr(rd);
708 tcg_temp_free_i32(sh);
709}
710
711#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
712static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
713 { \
714 TCGv_ptr ra, rb, rc, rd; \
715 if (unlikely(!ctx->altivec_enabled)) { \
716 gen_exception(ctx, POWERPC_EXCP_VPU); \
717 return; \
718 } \
719 ra = gen_avr_ptr(rA(ctx->opcode)); \
720 rb = gen_avr_ptr(rB(ctx->opcode)); \
721 rc = gen_avr_ptr(rC(ctx->opcode)); \
722 rd = gen_avr_ptr(rD(ctx->opcode)); \
723 if (Rc(ctx->opcode)) { \
724 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
725 } else { \
726 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
727 } \
728 tcg_temp_free_ptr(ra); \
729 tcg_temp_free_ptr(rb); \
730 tcg_temp_free_ptr(rc); \
731 tcg_temp_free_ptr(rd); \
732 }
733
734GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
735
736static void gen_vmladduhm(DisasContext *ctx)
737{
738 TCGv_ptr ra, rb, rc, rd;
739 if (unlikely(!ctx->altivec_enabled)) {
740 gen_exception(ctx, POWERPC_EXCP_VPU);
741 return;
742 }
743 ra = gen_avr_ptr(rA(ctx->opcode));
744 rb = gen_avr_ptr(rB(ctx->opcode));
745 rc = gen_avr_ptr(rC(ctx->opcode));
746 rd = gen_avr_ptr(rD(ctx->opcode));
747 gen_helper_vmladduhm(rd, ra, rb, rc);
748 tcg_temp_free_ptr(ra);
749 tcg_temp_free_ptr(rb);
750 tcg_temp_free_ptr(rc);
751 tcg_temp_free_ptr(rd);
752}
753
754GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
755GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
756GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
757GEN_VAFORM_PAIRED(vsel, vperm, 21)
758GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
759
760GEN_VXFORM_NOA(vclzb, 1, 28)
761GEN_VXFORM_NOA(vclzh, 1, 29)
762GEN_VXFORM_NOA(vclzw, 1, 30)
763GEN_VXFORM_NOA(vclzd, 1, 31)
764GEN_VXFORM_NOA(vpopcntb, 1, 28)
765GEN_VXFORM_NOA(vpopcnth, 1, 29)
766GEN_VXFORM_NOA(vpopcntw, 1, 30)
767GEN_VXFORM_NOA(vpopcntd, 1, 31)
768GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
769 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
770GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
771 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
772GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
773 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
774GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
775 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
776GEN_VXFORM(vbpermq, 6, 21);
777GEN_VXFORM_NOA(vgbbd, 6, 20);
778GEN_VXFORM(vpmsumb, 4, 16)
779GEN_VXFORM(vpmsumh, 4, 17)
780GEN_VXFORM(vpmsumw, 4, 18)
781GEN_VXFORM(vpmsumd, 4, 19)
782
783#define GEN_BCD(op) \
784static void gen_##op(DisasContext *ctx) \
785{ \
786 TCGv_ptr ra, rb, rd; \
787 TCGv_i32 ps; \
788 \
789 if (unlikely(!ctx->altivec_enabled)) { \
790 gen_exception(ctx, POWERPC_EXCP_VPU); \
791 return; \
792 } \
793 \
794 ra = gen_avr_ptr(rA(ctx->opcode)); \
795 rb = gen_avr_ptr(rB(ctx->opcode)); \
796 rd = gen_avr_ptr(rD(ctx->opcode)); \
797 \
798 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
799 \
800 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
801 \
802 tcg_temp_free_ptr(ra); \
803 tcg_temp_free_ptr(rb); \
804 tcg_temp_free_ptr(rd); \
805 tcg_temp_free_i32(ps); \
806}
807
808GEN_BCD(bcdadd)
809GEN_BCD(bcdsub)
810
811GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
812 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
813GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
814 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
815GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
816 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
817GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
818 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
819
820static void gen_vsbox(DisasContext *ctx)
821{
822 TCGv_ptr ra, rd;
823 if (unlikely(!ctx->altivec_enabled)) {
824 gen_exception(ctx, POWERPC_EXCP_VPU);
825 return;
826 }
827 ra = gen_avr_ptr(rA(ctx->opcode));
828 rd = gen_avr_ptr(rD(ctx->opcode));
829 gen_helper_vsbox(rd, ra);
830 tcg_temp_free_ptr(ra);
831 tcg_temp_free_ptr(rd);
832}
833
834GEN_VXFORM(vcipher, 4, 20)
835GEN_VXFORM(vcipherlast, 4, 20)
836GEN_VXFORM(vncipher, 4, 21)
837GEN_VXFORM(vncipherlast, 4, 21)
838
839GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
840 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
841GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
842 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
843
844#define VSHASIGMA(op) \
845static void gen_##op(DisasContext *ctx) \
846{ \
847 TCGv_ptr ra, rd; \
848 TCGv_i32 st_six; \
849 if (unlikely(!ctx->altivec_enabled)) { \
850 gen_exception(ctx, POWERPC_EXCP_VPU); \
851 return; \
852 } \
853 ra = gen_avr_ptr(rA(ctx->opcode)); \
854 rd = gen_avr_ptr(rD(ctx->opcode)); \
855 st_six = tcg_const_i32(rB(ctx->opcode)); \
856 gen_helper_##op(rd, ra, st_six); \
857 tcg_temp_free_ptr(ra); \
858 tcg_temp_free_ptr(rd); \
859 tcg_temp_free_i32(st_six); \
860}
861
862VSHASIGMA(vshasigmaw)
863VSHASIGMA(vshasigmad)
864
865GEN_VXFORM3(vpermxor, 22, 0xFF)
866GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
867 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
868
869#undef GEN_VR_LDX
870#undef GEN_VR_STX
871#undef GEN_VR_LVE
872#undef GEN_VR_STVE
873
874#undef GEN_VX_LOGICAL
875#undef GEN_VX_LOGICAL_207
876#undef GEN_VXFORM
877#undef GEN_VXFORM_207
878#undef GEN_VXFORM_DUAL
879#undef GEN_VXRFORM_DUAL
880#undef GEN_VXRFORM1
881#undef GEN_VXRFORM
882#undef GEN_VXFORM_SIMM
883#undef GEN_VXFORM_NOA
884#undef GEN_VXFORM_UIMM
885#undef GEN_VAFORM_PAIRED
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