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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
79aceca5 | 21 | #include "cpu.h" |
76cad711 | 22 | #include "disas/disas.h" |
57fec1fe | 23 | #include "tcg-op.h" |
1de7afc9 | 24 | #include "qemu/host-utils.h" |
f08b6170 | 25 | #include "exec/cpu_ldst.h" |
79aceca5 | 26 | |
2ef6175a RH |
27 | #include "exec/helper-proto.h" |
28 | #include "exec/helper-gen.h" | |
a7812ae4 | 29 | |
8cbcb4fa AJ |
30 | #define CPU_SINGLE_STEP 0x1 |
31 | #define CPU_BRANCH_STEP 0x2 | |
32 | #define GDBSTUB_SINGLE_STEP 0x4 | |
33 | ||
a750fc0b | 34 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 35 | //#define PPC_DEBUG_DISAS |
76a66253 | 36 | //#define DO_PPC_STATISTICS |
79aceca5 | 37 | |
d12d51d5 | 38 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 39 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
40 | #else |
41 | # define LOG_DISAS(...) do { } while (0) | |
42 | #endif | |
a750fc0b JM |
43 | /*****************************************************************************/ |
44 | /* Code translation helpers */ | |
c53be334 | 45 | |
f78fb44e | 46 | /* global register indexes */ |
a7812ae4 | 47 | static TCGv_ptr cpu_env; |
1d542695 | 48 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
1d542695 | 49 | + 10*4 + 22*5 /* SPE GPRh */ |
a5e26afa | 50 | + 10*4 + 22*5 /* FPR */ |
47e4661c | 51 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
472b24ce | 52 | + 10*5 + 22*6 /* VSR */ |
47e4661c | 53 | + 8*5 /* CRF */]; |
f78fb44e | 54 | static TCGv cpu_gpr[32]; |
f78fb44e | 55 | static TCGv cpu_gprh[32]; |
a7812ae4 PB |
56 | static TCGv_i64 cpu_fpr[32]; |
57 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
472b24ce | 58 | static TCGv_i64 cpu_vsr[32]; |
a7812ae4 | 59 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 60 | static TCGv cpu_nip; |
6527f6ea | 61 | static TCGv cpu_msr; |
cfdcd37a AJ |
62 | static TCGv cpu_ctr; |
63 | static TCGv cpu_lr; | |
697ab892 DG |
64 | #if defined(TARGET_PPC64) |
65 | static TCGv cpu_cfar; | |
66 | #endif | |
da91a00f | 67 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 68 | static TCGv cpu_reserve; |
30304420 | 69 | static TCGv cpu_fpscr; |
a7859e89 | 70 | static TCGv_i32 cpu_access_type; |
f78fb44e | 71 | |
022c62cb | 72 | #include "exec/gen-icount.h" |
2e70f6ef PB |
73 | |
74 | void ppc_translate_init(void) | |
75 | { | |
f78fb44e AJ |
76 | int i; |
77 | char* p; | |
2dc766da | 78 | size_t cpu_reg_names_size; |
b2437bf2 | 79 | static int done_init = 0; |
f78fb44e | 80 | |
2e70f6ef PB |
81 | if (done_init) |
82 | return; | |
f78fb44e | 83 | |
a7812ae4 | 84 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 85 | |
f78fb44e | 86 | p = cpu_reg_names; |
2dc766da | 87 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
88 | |
89 | for (i = 0; i < 8; i++) { | |
2dc766da | 90 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 | 91 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 92 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 93 | p += 5; |
2dc766da | 94 | cpu_reg_names_size -= 5; |
47e4661c AJ |
95 | } |
96 | ||
f78fb44e | 97 | for (i = 0; i < 32; i++) { |
2dc766da | 98 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 99 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 100 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 101 | p += (i < 10) ? 3 : 4; |
2dc766da | 102 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 103 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
13b6a455 AG |
104 | cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0, |
105 | offsetof(CPUPPCState, gprh[i]), p); | |
f78fb44e | 106 | p += (i < 10) ? 4 : 5; |
2dc766da | 107 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
1d542695 | 108 | |
2dc766da | 109 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 | 110 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 111 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 112 | p += (i < 10) ? 4 : 5; |
2dc766da | 113 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 114 | |
2dc766da | 115 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 116 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 117 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 118 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 119 | #else |
a7812ae4 | 120 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 121 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 122 | #endif |
1d542695 | 123 | p += (i < 10) ? 6 : 7; |
2dc766da | 124 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 125 | |
2dc766da | 126 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 127 | #ifdef HOST_WORDS_BIGENDIAN |
fe1e5c53 | 128 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 129 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 130 | #else |
a7812ae4 | 131 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
1328c2bf | 132 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 133 | #endif |
1d542695 | 134 | p += (i < 10) ? 6 : 7; |
2dc766da | 135 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
472b24ce TM |
136 | snprintf(p, cpu_reg_names_size, "vsr%d", i); |
137 | cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
138 | offsetof(CPUPPCState, vsr[i]), p); | |
139 | p += (i < 10) ? 5 : 6; | |
140 | cpu_reg_names_size -= (i < 10) ? 5 : 6; | |
f78fb44e | 141 | } |
f10dc08e | 142 | |
a7812ae4 | 143 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 144 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 145 | |
6527f6ea | 146 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 147 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 148 | |
a7812ae4 | 149 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 150 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 151 | |
a7812ae4 | 152 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 153 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 154 | |
697ab892 DG |
155 | #if defined(TARGET_PPC64) |
156 | cpu_cfar = tcg_global_mem_new(TCG_AREG0, | |
1328c2bf | 157 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
158 | #endif |
159 | ||
a7812ae4 | 160 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 161 | offsetof(CPUPPCState, xer), "xer"); |
da91a00f RH |
162 | cpu_so = tcg_global_mem_new(TCG_AREG0, |
163 | offsetof(CPUPPCState, so), "SO"); | |
164 | cpu_ov = tcg_global_mem_new(TCG_AREG0, | |
165 | offsetof(CPUPPCState, ov), "OV"); | |
166 | cpu_ca = tcg_global_mem_new(TCG_AREG0, | |
167 | offsetof(CPUPPCState, ca), "CA"); | |
3d7b417e | 168 | |
cf360a32 | 169 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
1328c2bf | 170 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 171 | "reserve_addr"); |
cf360a32 | 172 | |
30304420 DG |
173 | cpu_fpscr = tcg_global_mem_new(TCG_AREG0, |
174 | offsetof(CPUPPCState, fpscr), "fpscr"); | |
e1571908 | 175 | |
a7859e89 | 176 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
1328c2bf | 177 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 178 | |
2e70f6ef PB |
179 | done_init = 1; |
180 | } | |
181 | ||
79aceca5 FB |
182 | /* internal defines */ |
183 | typedef struct DisasContext { | |
184 | struct TranslationBlock *tb; | |
0fa85d43 | 185 | target_ulong nip; |
79aceca5 | 186 | uint32_t opcode; |
9a64fbe4 | 187 | uint32_t exception; |
3cc62370 FB |
188 | /* Routine used to access memory */ |
189 | int mem_idx; | |
76db3ba4 | 190 | int access_type; |
3cc62370 | 191 | /* Translation flags */ |
76db3ba4 | 192 | int le_mode; |
e22c357b | 193 | TCGMemOp default_tcg_memop_mask; |
d9bce9d9 JM |
194 | #if defined(TARGET_PPC64) |
195 | int sf_mode; | |
697ab892 | 196 | int has_cfar; |
9a64fbe4 | 197 | #endif |
3cc62370 | 198 | int fpu_enabled; |
a9d9eb8f | 199 | int altivec_enabled; |
1f29871c | 200 | int vsx_enabled; |
0487d6a8 | 201 | int spe_enabled; |
c227f099 | 202 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 203 | int singlestep_enabled; |
7d08d856 AJ |
204 | uint64_t insns_flags; |
205 | uint64_t insns_flags2; | |
79aceca5 FB |
206 | } DisasContext; |
207 | ||
e22c357b DK |
208 | /* Return true iff byteswap is needed in a scalar memop */ |
209 | static inline bool need_byteswap(const DisasContext *ctx) | |
210 | { | |
211 | #if defined(TARGET_WORDS_BIGENDIAN) | |
212 | return ctx->le_mode; | |
213 | #else | |
214 | return !ctx->le_mode; | |
215 | #endif | |
216 | } | |
217 | ||
79482e5a RH |
218 | /* True when active word size < size of target_long. */ |
219 | #ifdef TARGET_PPC64 | |
220 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
221 | #else | |
222 | # define NARROW_MODE(C) 0 | |
223 | #endif | |
224 | ||
c227f099 | 225 | struct opc_handler_t { |
70560da7 FC |
226 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
227 | uint32_t inval1; | |
228 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
229 | uint32_t inval2; | |
9a64fbe4 | 230 | /* instruction type */ |
0487d6a8 | 231 | uint64_t type; |
a5858d7a AG |
232 | /* extended instruction type */ |
233 | uint64_t type2; | |
79aceca5 FB |
234 | /* handler */ |
235 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 236 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 237 | const char *oname; |
a750fc0b JM |
238 | #endif |
239 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
240 | uint64_t count; |
241 | #endif | |
3fc6c082 | 242 | }; |
79aceca5 | 243 | |
636aa200 | 244 | static inline void gen_reset_fpstatus(void) |
7c58044c | 245 | { |
8e703949 | 246 | gen_helper_reset_fpstatus(cpu_env); |
7c58044c JM |
247 | } |
248 | ||
636aa200 | 249 | static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 250 | { |
0f2f39c2 | 251 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 252 | |
7c58044c JM |
253 | if (set_fprf != 0) { |
254 | /* This case might be optimized later */ | |
0f2f39c2 | 255 | tcg_gen_movi_i32(t0, 1); |
8e703949 | 256 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
a7812ae4 | 257 | if (unlikely(set_rc)) { |
0f2f39c2 | 258 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 259 | } |
8e703949 | 260 | gen_helper_float_check_status(cpu_env); |
7c58044c JM |
261 | } else if (unlikely(set_rc)) { |
262 | /* We always need to compute fpcc */ | |
0f2f39c2 | 263 | tcg_gen_movi_i32(t0, 0); |
8e703949 | 264 | gen_helper_compute_fprf(t0, cpu_env, arg, t0); |
0f2f39c2 | 265 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 266 | } |
af12906f | 267 | |
0f2f39c2 | 268 | tcg_temp_free_i32(t0); |
7c58044c JM |
269 | } |
270 | ||
636aa200 | 271 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 272 | { |
76db3ba4 AJ |
273 | if (ctx->access_type != access_type) { |
274 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
275 | ctx->access_type = access_type; | |
276 | } | |
a7859e89 AJ |
277 | } |
278 | ||
636aa200 | 279 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 280 | { |
e0c8f9ce RH |
281 | if (NARROW_MODE(ctx)) { |
282 | nip = (uint32_t)nip; | |
283 | } | |
284 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
285 | } |
286 | ||
7019cb3d AK |
287 | void gen_update_current_nip(void *opaque) |
288 | { | |
289 | DisasContext *ctx = opaque; | |
290 | ||
291 | tcg_gen_movi_tl(cpu_nip, ctx->nip); | |
292 | } | |
293 | ||
636aa200 | 294 | static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
295 | { |
296 | TCGv_i32 t0, t1; | |
297 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
298 | gen_update_nip(ctx, ctx->nip); | |
299 | } | |
300 | t0 = tcg_const_i32(excp); | |
301 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 302 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
303 | tcg_temp_free_i32(t0); |
304 | tcg_temp_free_i32(t1); | |
305 | ctx->exception = (excp); | |
306 | } | |
e1833e1f | 307 | |
636aa200 | 308 | static inline void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
309 | { |
310 | TCGv_i32 t0; | |
311 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
312 | gen_update_nip(ctx, ctx->nip); | |
313 | } | |
314 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 315 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
316 | tcg_temp_free_i32(t0); |
317 | ctx->exception = (excp); | |
318 | } | |
e1833e1f | 319 | |
636aa200 | 320 | static inline void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
321 | { |
322 | TCGv_i32 t0; | |
5518f3a6 | 323 | |
ee2b3994 SB |
324 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
325 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
5518f3a6 | 326 | gen_update_nip(ctx, ctx->nip); |
ee2b3994 | 327 | } |
e06fcd75 | 328 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 329 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
330 | tcg_temp_free_i32(t0); |
331 | } | |
9a64fbe4 | 332 | |
636aa200 | 333 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 AJ |
334 | { |
335 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
336 | } | |
a9d9eb8f | 337 | |
f24e5695 | 338 | /* Stop translation */ |
636aa200 | 339 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 340 | { |
d9bce9d9 | 341 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 342 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
343 | } |
344 | ||
f24e5695 | 345 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 346 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 347 | { |
e1833e1f | 348 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
349 | } |
350 | ||
79aceca5 | 351 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
352 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
353 | ||
354 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
355 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 356 | |
c7697e1f | 357 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
358 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
359 | ||
360 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
361 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 362 | |
c227f099 | 363 | typedef struct opcode_t { |
79aceca5 | 364 | unsigned char opc1, opc2, opc3; |
1235fc06 | 365 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
366 | unsigned char pad[5]; |
367 | #else | |
368 | unsigned char pad[1]; | |
369 | #endif | |
c227f099 | 370 | opc_handler_t handler; |
b55266b5 | 371 | const char *oname; |
c227f099 | 372 | } opcode_t; |
79aceca5 | 373 | |
a750fc0b | 374 | /*****************************************************************************/ |
79aceca5 FB |
375 | /*** Instruction decoding ***/ |
376 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 377 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
378 | { \ |
379 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
380 | } | |
381 | ||
382 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 383 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 384 | { \ |
18fba28c | 385 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
386 | } |
387 | ||
f9fc6d81 TM |
388 | #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \ |
389 | static inline uint32_t name(uint32_t opcode) \ | |
390 | { \ | |
391 | return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \ | |
392 | ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \ | |
393 | } | |
79aceca5 FB |
394 | /* Opcode part 1 */ |
395 | EXTRACT_HELPER(opc1, 26, 6); | |
396 | /* Opcode part 2 */ | |
397 | EXTRACT_HELPER(opc2, 1, 5); | |
398 | /* Opcode part 3 */ | |
399 | EXTRACT_HELPER(opc3, 6, 5); | |
400 | /* Update Cr0 flags */ | |
401 | EXTRACT_HELPER(Rc, 0, 1); | |
a737d3eb TM |
402 | /* Update Cr6 flags (Altivec) */ |
403 | EXTRACT_HELPER(Rc21, 10, 1); | |
79aceca5 FB |
404 | /* Destination */ |
405 | EXTRACT_HELPER(rD, 21, 5); | |
406 | /* Source */ | |
407 | EXTRACT_HELPER(rS, 21, 5); | |
408 | /* First operand */ | |
409 | EXTRACT_HELPER(rA, 16, 5); | |
410 | /* Second operand */ | |
411 | EXTRACT_HELPER(rB, 11, 5); | |
412 | /* Third operand */ | |
413 | EXTRACT_HELPER(rC, 6, 5); | |
414 | /*** Get CRn ***/ | |
415 | EXTRACT_HELPER(crfD, 23, 3); | |
416 | EXTRACT_HELPER(crfS, 18, 3); | |
417 | EXTRACT_HELPER(crbD, 21, 5); | |
418 | EXTRACT_HELPER(crbA, 16, 5); | |
419 | EXTRACT_HELPER(crbB, 11, 5); | |
420 | /* SPR / TBL */ | |
3fc6c082 | 421 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 422 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
423 | { |
424 | uint32_t sprn = _SPR(opcode); | |
425 | ||
426 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
427 | } | |
79aceca5 FB |
428 | /*** Get constants ***/ |
429 | EXTRACT_HELPER(IMM, 12, 8); | |
430 | /* 16 bits signed immediate value */ | |
431 | EXTRACT_SHELPER(SIMM, 0, 16); | |
432 | /* 16 bits unsigned immediate value */ | |
433 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
434 | /* 5 bits signed immediate value */ |
435 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
436 | /* 5 bits signed immediate value */ |
437 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
438 | /* Bit count */ |
439 | EXTRACT_HELPER(NB, 11, 5); | |
440 | /* Shift count */ | |
441 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
442 | /* Vector shift count */ |
443 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
444 | /* Mask start */ |
445 | EXTRACT_HELPER(MB, 6, 5); | |
446 | /* Mask end */ | |
447 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
448 | /* Trap operand */ |
449 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
450 | |
451 | EXTRACT_HELPER(CRM, 12, 8); | |
79aceca5 | 452 | EXTRACT_HELPER(SR, 16, 4); |
7d08d856 AJ |
453 | |
454 | /* mtfsf/mtfsfi */ | |
779f6590 | 455 | EXTRACT_HELPER(FPBF, 23, 3); |
e4bb997e | 456 | EXTRACT_HELPER(FPIMM, 12, 4); |
779f6590 | 457 | EXTRACT_HELPER(FPL, 25, 1); |
7d08d856 AJ |
458 | EXTRACT_HELPER(FPFLM, 17, 8); |
459 | EXTRACT_HELPER(FPW, 16, 1); | |
fb0eaffc | 460 | |
79aceca5 FB |
461 | /*** Jump target decoding ***/ |
462 | /* Displacement */ | |
463 | EXTRACT_SHELPER(d, 0, 16); | |
464 | /* Immediate address */ | |
636aa200 | 465 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
466 | { |
467 | return (opcode >> 0) & 0x03FFFFFC; | |
468 | } | |
469 | ||
636aa200 | 470 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
471 | { |
472 | return (opcode >> 0) & 0xFFFC; | |
473 | } | |
474 | ||
475 | EXTRACT_HELPER(BO, 21, 5); | |
476 | EXTRACT_HELPER(BI, 16, 5); | |
477 | /* Absolute/relative address */ | |
478 | EXTRACT_HELPER(AA, 1, 1); | |
479 | /* Link */ | |
480 | EXTRACT_HELPER(LK, 0, 1); | |
481 | ||
f0b01f02 TM |
482 | /* DFP Z22-form */ |
483 | EXTRACT_HELPER(DCM, 10, 6) | |
484 | ||
485 | /* DFP Z23-form */ | |
486 | EXTRACT_HELPER(RMC, 9, 2) | |
487 | ||
79aceca5 | 488 | /* Create a mask between <start> and <end> bits */ |
636aa200 | 489 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 490 | { |
76a66253 | 491 | target_ulong ret; |
79aceca5 | 492 | |
76a66253 JM |
493 | #if defined(TARGET_PPC64) |
494 | if (likely(start == 0)) { | |
6f2d8978 | 495 | ret = UINT64_MAX << (63 - end); |
76a66253 | 496 | } else if (likely(end == 63)) { |
6f2d8978 | 497 | ret = UINT64_MAX >> start; |
76a66253 JM |
498 | } |
499 | #else | |
500 | if (likely(start == 0)) { | |
6f2d8978 | 501 | ret = UINT32_MAX << (31 - end); |
76a66253 | 502 | } else if (likely(end == 31)) { |
6f2d8978 | 503 | ret = UINT32_MAX >> start; |
76a66253 JM |
504 | } |
505 | #endif | |
506 | else { | |
507 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
508 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
509 | if (unlikely(start > end)) | |
510 | return ~ret; | |
511 | } | |
79aceca5 FB |
512 | |
513 | return ret; | |
514 | } | |
515 | ||
f9fc6d81 TM |
516 | EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5); |
517 | EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5); | |
518 | EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5); | |
519 | EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5); | |
551e3ef7 | 520 | EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5); |
f9fc6d81 | 521 | EXTRACT_HELPER(DM, 8, 2); |
76c15fe0 | 522 | EXTRACT_HELPER(UIM, 16, 2); |
acc42968 | 523 | EXTRACT_HELPER(SHW, 8, 2); |
f0b01f02 | 524 | EXTRACT_HELPER(SP, 19, 2); |
a750fc0b | 525 | /*****************************************************************************/ |
a750fc0b | 526 | /* PowerPC instructions table */ |
933dc6eb | 527 | |
76a66253 | 528 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 529 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 530 | { \ |
79aceca5 FB |
531 | .opc1 = op1, \ |
532 | .opc2 = op2, \ | |
533 | .opc3 = op3, \ | |
18fba28c | 534 | .pad = { 0, }, \ |
79aceca5 | 535 | .handler = { \ |
70560da7 FC |
536 | .inval1 = invl, \ |
537 | .type = _typ, \ | |
538 | .type2 = _typ2, \ | |
539 | .handler = &gen_##name, \ | |
540 | .oname = stringify(name), \ | |
541 | }, \ | |
542 | .oname = stringify(name), \ | |
543 | } | |
544 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
545 | { \ | |
546 | .opc1 = op1, \ | |
547 | .opc2 = op2, \ | |
548 | .opc3 = op3, \ | |
549 | .pad = { 0, }, \ | |
550 | .handler = { \ | |
551 | .inval1 = invl1, \ | |
552 | .inval2 = invl2, \ | |
9a64fbe4 | 553 | .type = _typ, \ |
a5858d7a | 554 | .type2 = _typ2, \ |
79aceca5 | 555 | .handler = &gen_##name, \ |
76a66253 | 556 | .oname = stringify(name), \ |
79aceca5 | 557 | }, \ |
3fc6c082 | 558 | .oname = stringify(name), \ |
79aceca5 | 559 | } |
a5858d7a | 560 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 561 | { \ |
c7697e1f JM |
562 | .opc1 = op1, \ |
563 | .opc2 = op2, \ | |
564 | .opc3 = op3, \ | |
565 | .pad = { 0, }, \ | |
566 | .handler = { \ | |
70560da7 | 567 | .inval1 = invl, \ |
c7697e1f | 568 | .type = _typ, \ |
a5858d7a | 569 | .type2 = _typ2, \ |
c7697e1f JM |
570 | .handler = &gen_##name, \ |
571 | .oname = onam, \ | |
572 | }, \ | |
573 | .oname = onam, \ | |
574 | } | |
76a66253 | 575 | #else |
a5858d7a | 576 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 577 | { \ |
c7697e1f JM |
578 | .opc1 = op1, \ |
579 | .opc2 = op2, \ | |
580 | .opc3 = op3, \ | |
581 | .pad = { 0, }, \ | |
582 | .handler = { \ | |
70560da7 FC |
583 | .inval1 = invl, \ |
584 | .type = _typ, \ | |
585 | .type2 = _typ2, \ | |
586 | .handler = &gen_##name, \ | |
587 | }, \ | |
588 | .oname = stringify(name), \ | |
589 | } | |
590 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
591 | { \ | |
592 | .opc1 = op1, \ | |
593 | .opc2 = op2, \ | |
594 | .opc3 = op3, \ | |
595 | .pad = { 0, }, \ | |
596 | .handler = { \ | |
597 | .inval1 = invl1, \ | |
598 | .inval2 = invl2, \ | |
c7697e1f | 599 | .type = _typ, \ |
a5858d7a | 600 | .type2 = _typ2, \ |
c7697e1f | 601 | .handler = &gen_##name, \ |
5c55ff99 BS |
602 | }, \ |
603 | .oname = stringify(name), \ | |
604 | } | |
a5858d7a | 605 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
606 | { \ |
607 | .opc1 = op1, \ | |
608 | .opc2 = op2, \ | |
609 | .opc3 = op3, \ | |
610 | .pad = { 0, }, \ | |
611 | .handler = { \ | |
70560da7 | 612 | .inval1 = invl, \ |
5c55ff99 | 613 | .type = _typ, \ |
a5858d7a | 614 | .type2 = _typ2, \ |
5c55ff99 BS |
615 | .handler = &gen_##name, \ |
616 | }, \ | |
617 | .oname = onam, \ | |
618 | } | |
619 | #endif | |
2e610050 | 620 | |
5c55ff99 | 621 | /* SPR load/store helpers */ |
636aa200 | 622 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 623 | { |
1328c2bf | 624 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 625 | } |
2e610050 | 626 | |
636aa200 | 627 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 628 | { |
1328c2bf | 629 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 630 | } |
2e610050 | 631 | |
54623277 | 632 | /* Invalid instruction */ |
99e300ef | 633 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 634 | { |
e06fcd75 | 635 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
636 | } |
637 | ||
c227f099 | 638 | static opc_handler_t invalid_handler = { |
70560da7 FC |
639 | .inval1 = 0xFFFFFFFF, |
640 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 641 | .type = PPC_NONE, |
a5858d7a | 642 | .type2 = PPC_NONE, |
79aceca5 FB |
643 | .handler = gen_invalid, |
644 | }; | |
645 | ||
71a8c019 TM |
646 | #if defined(TARGET_PPC64) |
647 | /* NOTE: as this time, the only use of is_user_mode() is in 64 bit code. And */ | |
648 | /* so the function is wrapped in the standard 64-bit ifdef in order to */ | |
649 | /* avoid compiler warnings in 32-bit implementations. */ | |
650 | static bool is_user_mode(DisasContext *ctx) | |
651 | { | |
652 | #if defined(CONFIG_USER_ONLY) | |
653 | return true; | |
654 | #else | |
655 | return ctx->mem_idx == 0; | |
656 | #endif | |
657 | } | |
658 | #endif | |
659 | ||
e1571908 AJ |
660 | /*** Integer comparison ***/ |
661 | ||
636aa200 | 662 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 663 | { |
2fdcb629 RH |
664 | TCGv t0 = tcg_temp_new(); |
665 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 666 | |
da91a00f | 667 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 668 | |
2fdcb629 RH |
669 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
670 | tcg_gen_trunc_tl_i32(t1, t0); | |
671 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
672 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
673 | ||
674 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
675 | tcg_gen_trunc_tl_i32(t1, t0); | |
676 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
677 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
678 | ||
679 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
680 | tcg_gen_trunc_tl_i32(t1, t0); | |
681 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
682 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
683 | ||
684 | tcg_temp_free(t0); | |
685 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
686 | } |
687 | ||
636aa200 | 688 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 689 | { |
2fdcb629 | 690 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
691 | gen_op_cmp(arg0, t0, s, crf); |
692 | tcg_temp_free(t0); | |
e1571908 AJ |
693 | } |
694 | ||
636aa200 | 695 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 696 | { |
ea363694 | 697 | TCGv t0, t1; |
2fdcb629 RH |
698 | t0 = tcg_temp_new(); |
699 | t1 = tcg_temp_new(); | |
e1571908 | 700 | if (s) { |
ea363694 AJ |
701 | tcg_gen_ext32s_tl(t0, arg0); |
702 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 703 | } else { |
ea363694 AJ |
704 | tcg_gen_ext32u_tl(t0, arg0); |
705 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 706 | } |
ea363694 AJ |
707 | gen_op_cmp(t0, t1, s, crf); |
708 | tcg_temp_free(t1); | |
709 | tcg_temp_free(t0); | |
e1571908 AJ |
710 | } |
711 | ||
636aa200 | 712 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 713 | { |
2fdcb629 | 714 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
715 | gen_op_cmp32(arg0, t0, s, crf); |
716 | tcg_temp_free(t0); | |
e1571908 | 717 | } |
e1571908 | 718 | |
636aa200 | 719 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 720 | { |
02765534 | 721 | if (NARROW_MODE(ctx)) { |
e1571908 | 722 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 723 | } else { |
e1571908 | 724 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 725 | } |
e1571908 AJ |
726 | } |
727 | ||
728 | /* cmp */ | |
99e300ef | 729 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 730 | { |
36f48d9c | 731 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
732 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
733 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
734 | } else { |
735 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
736 | 1, crfD(ctx->opcode)); | |
02765534 | 737 | } |
e1571908 AJ |
738 | } |
739 | ||
740 | /* cmpi */ | |
99e300ef | 741 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 742 | { |
36f48d9c | 743 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
744 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
745 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
746 | } else { |
747 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
748 | 1, crfD(ctx->opcode)); | |
02765534 | 749 | } |
e1571908 AJ |
750 | } |
751 | ||
752 | /* cmpl */ | |
99e300ef | 753 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 754 | { |
36f48d9c | 755 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
756 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
757 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
758 | } else { |
759 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
760 | 0, crfD(ctx->opcode)); | |
02765534 | 761 | } |
e1571908 AJ |
762 | } |
763 | ||
764 | /* cmpli */ | |
99e300ef | 765 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 766 | { |
36f48d9c | 767 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
768 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
769 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
770 | } else { |
771 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
772 | 0, crfD(ctx->opcode)); | |
02765534 | 773 | } |
e1571908 AJ |
774 | } |
775 | ||
776 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 777 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
778 | { |
779 | int l1, l2; | |
780 | uint32_t bi = rC(ctx->opcode); | |
781 | uint32_t mask; | |
a7812ae4 | 782 | TCGv_i32 t0; |
e1571908 AJ |
783 | |
784 | l1 = gen_new_label(); | |
785 | l2 = gen_new_label(); | |
786 | ||
787 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 788 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
789 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
790 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
791 | if (rA(ctx->opcode) == 0) |
792 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
793 | else | |
794 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
795 | tcg_gen_br(l2); | |
796 | gen_set_label(l1); | |
797 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
798 | gen_set_label(l2); | |
a7812ae4 | 799 | tcg_temp_free_i32(t0); |
e1571908 AJ |
800 | } |
801 | ||
fcfda20f AJ |
802 | /* cmpb: PowerPC 2.05 specification */ |
803 | static void gen_cmpb(DisasContext *ctx) | |
804 | { | |
805 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
806 | cpu_gpr[rB(ctx->opcode)]); | |
807 | } | |
808 | ||
79aceca5 | 809 | /*** Integer arithmetic ***/ |
79aceca5 | 810 | |
636aa200 BS |
811 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
812 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 813 | { |
ffe30937 | 814 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 815 | |
8e7a6db9 | 816 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 817 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
818 | if (sub) { |
819 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
820 | } else { | |
821 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
822 | } | |
823 | tcg_temp_free(t0); | |
02765534 | 824 | if (NARROW_MODE(ctx)) { |
ffe30937 RH |
825 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
826 | } | |
ffe30937 RH |
827 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
828 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
829 | } |
830 | ||
74637406 | 831 | /* Common add function */ |
636aa200 | 832 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
833 | TCGv arg2, bool add_ca, bool compute_ca, |
834 | bool compute_ov, bool compute_rc0) | |
74637406 | 835 | { |
b5a73f8d | 836 | TCGv t0 = ret; |
d9bce9d9 | 837 | |
752d634e | 838 | if (compute_ca || compute_ov) { |
146de60d | 839 | t0 = tcg_temp_new(); |
74637406 | 840 | } |
79aceca5 | 841 | |
da91a00f | 842 | if (compute_ca) { |
79482e5a | 843 | if (NARROW_MODE(ctx)) { |
752d634e RH |
844 | /* Caution: a non-obvious corner case of the spec is that we |
845 | must produce the *entire* 64-bit addition, but produce the | |
846 | carry into bit 32. */ | |
79482e5a | 847 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
848 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
849 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
850 | if (add_ca) { |
851 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
852 | } | |
752d634e RH |
853 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
854 | tcg_temp_free(t1); | |
855 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
856 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
b5a73f8d | 857 | } else { |
79482e5a RH |
858 | TCGv zero = tcg_const_tl(0); |
859 | if (add_ca) { | |
860 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
861 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
862 | } else { | |
863 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
864 | } | |
865 | tcg_temp_free(zero); | |
b5a73f8d | 866 | } |
b5a73f8d RH |
867 | } else { |
868 | tcg_gen_add_tl(t0, arg1, arg2); | |
869 | if (add_ca) { | |
870 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
871 | } | |
da91a00f | 872 | } |
79aceca5 | 873 | |
74637406 AJ |
874 | if (compute_ov) { |
875 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
876 | } | |
b5a73f8d | 877 | if (unlikely(compute_rc0)) { |
74637406 | 878 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 879 | } |
74637406 | 880 | |
a7812ae4 | 881 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
882 | tcg_gen_mov_tl(ret, t0); |
883 | tcg_temp_free(t0); | |
884 | } | |
39dd32ee | 885 | } |
74637406 AJ |
886 | /* Add functions with two operands */ |
887 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 888 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
889 | { \ |
890 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
891 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 892 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
893 | } |
894 | /* Add functions with one operand and one immediate */ | |
895 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
896 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 897 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 898 | { \ |
b5a73f8d | 899 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
900 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
901 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 902 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
903 | tcg_temp_free(t0); \ |
904 | } | |
905 | ||
906 | /* add add. addo addo. */ | |
907 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
908 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
909 | /* addc addc. addco addco. */ | |
910 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
911 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
912 | /* adde adde. addeo addeo. */ | |
913 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
914 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
915 | /* addme addme. addmeo addmeo. */ | |
916 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
917 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
918 | /* addze addze. addzeo addzeo.*/ | |
919 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
920 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
921 | /* addi */ | |
99e300ef | 922 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 923 | { |
74637406 AJ |
924 | target_long simm = SIMM(ctx->opcode); |
925 | ||
926 | if (rA(ctx->opcode) == 0) { | |
927 | /* li case */ | |
928 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
929 | } else { | |
b5a73f8d RH |
930 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
931 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 932 | } |
d9bce9d9 | 933 | } |
74637406 | 934 | /* addic addic.*/ |
b5a73f8d | 935 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 936 | { |
b5a73f8d RH |
937 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
938 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
939 | c, 0, 1, 0, compute_rc0); | |
940 | tcg_temp_free(c); | |
d9bce9d9 | 941 | } |
99e300ef BS |
942 | |
943 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 944 | { |
b5a73f8d | 945 | gen_op_addic(ctx, 0); |
d9bce9d9 | 946 | } |
e8eaa2c0 BS |
947 | |
948 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 949 | { |
b5a73f8d | 950 | gen_op_addic(ctx, 1); |
d9bce9d9 | 951 | } |
99e300ef | 952 | |
54623277 | 953 | /* addis */ |
99e300ef | 954 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 955 | { |
74637406 AJ |
956 | target_long simm = SIMM(ctx->opcode); |
957 | ||
958 | if (rA(ctx->opcode) == 0) { | |
959 | /* lis case */ | |
960 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
961 | } else { | |
b5a73f8d RH |
962 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
963 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 964 | } |
d9bce9d9 | 965 | } |
74637406 | 966 | |
636aa200 BS |
967 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
968 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 969 | { |
2ef1b120 AJ |
970 | int l1 = gen_new_label(); |
971 | int l2 = gen_new_label(); | |
a7812ae4 PB |
972 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
973 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 974 | |
2ef1b120 AJ |
975 | tcg_gen_trunc_tl_i32(t0, arg1); |
976 | tcg_gen_trunc_tl_i32(t1, arg2); | |
977 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 978 | if (sign) { |
2ef1b120 AJ |
979 | int l3 = gen_new_label(); |
980 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
981 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 982 | gen_set_label(l3); |
2ef1b120 | 983 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 984 | } else { |
2ef1b120 | 985 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
986 | } |
987 | if (compute_ov) { | |
da91a00f | 988 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
989 | } |
990 | tcg_gen_br(l2); | |
991 | gen_set_label(l1); | |
992 | if (sign) { | |
2ef1b120 | 993 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
994 | } else { |
995 | tcg_gen_movi_i32(t0, 0); | |
996 | } | |
997 | if (compute_ov) { | |
da91a00f RH |
998 | tcg_gen_movi_tl(cpu_ov, 1); |
999 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
1000 | } |
1001 | gen_set_label(l2); | |
2ef1b120 | 1002 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
1003 | tcg_temp_free_i32(t0); |
1004 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1005 | if (unlikely(Rc(ctx->opcode) != 0)) |
1006 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1007 | } |
74637406 AJ |
1008 | /* Div functions */ |
1009 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 1010 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1011 | { \ |
1012 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1013 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1014 | sign, compute_ov); \ | |
1015 | } | |
1016 | /* divwu divwu. divwuo divwuo. */ | |
1017 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1018 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1019 | /* divw divw. divwo divwo. */ | |
1020 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1021 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
1022 | |
1023 | /* div[wd]eu[o][.] */ | |
1024 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1025 | static void gen_##name(DisasContext *ctx) \ | |
1026 | { \ | |
1027 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ | |
1028 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ | |
1029 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1030 | tcg_temp_free_i32(t0); \ | |
1031 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1032 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1033 | } \ | |
1034 | } | |
1035 | ||
6a4fda33 TM |
1036 | GEN_DIVE(divweu, divweu, 0); |
1037 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1038 | GEN_DIVE(divwe, divwe, 0); |
1039 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1040 | |
d9bce9d9 | 1041 | #if defined(TARGET_PPC64) |
636aa200 BS |
1042 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1043 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1044 | { |
2ef1b120 AJ |
1045 | int l1 = gen_new_label(); |
1046 | int l2 = gen_new_label(); | |
74637406 AJ |
1047 | |
1048 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
1049 | if (sign) { | |
2ef1b120 | 1050 | int l3 = gen_new_label(); |
74637406 AJ |
1051 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
1052 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
1053 | gen_set_label(l3); | |
74637406 AJ |
1054 | tcg_gen_div_i64(ret, arg1, arg2); |
1055 | } else { | |
1056 | tcg_gen_divu_i64(ret, arg1, arg2); | |
1057 | } | |
1058 | if (compute_ov) { | |
da91a00f | 1059 | tcg_gen_movi_tl(cpu_ov, 0); |
74637406 AJ |
1060 | } |
1061 | tcg_gen_br(l2); | |
1062 | gen_set_label(l1); | |
1063 | if (sign) { | |
1064 | tcg_gen_sari_i64(ret, arg1, 63); | |
1065 | } else { | |
1066 | tcg_gen_movi_i64(ret, 0); | |
1067 | } | |
1068 | if (compute_ov) { | |
da91a00f RH |
1069 | tcg_gen_movi_tl(cpu_ov, 1); |
1070 | tcg_gen_movi_tl(cpu_so, 1); | |
74637406 AJ |
1071 | } |
1072 | gen_set_label(l2); | |
1073 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1074 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1075 | } |
74637406 | 1076 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1077 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1078 | { \ |
2ef1b120 AJ |
1079 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1080 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1081 | sign, compute_ov); \ | |
74637406 AJ |
1082 | } |
1083 | /* divwu divwu. divwuo divwuo. */ | |
1084 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1085 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1086 | /* divw divw. divwo divwo. */ | |
1087 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1088 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1089 | |
1090 | GEN_DIVE(divdeu, divdeu, 0); | |
1091 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1092 | GEN_DIVE(divde, divde, 0); |
1093 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1094 | #endif |
74637406 AJ |
1095 | |
1096 | /* mulhw mulhw. */ | |
99e300ef | 1097 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1098 | { |
23ad1d5d RH |
1099 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1100 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1101 | |
23ad1d5d RH |
1102 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1103 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1104 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1105 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1106 | tcg_temp_free_i32(t0); | |
1107 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1108 | if (unlikely(Rc(ctx->opcode) != 0)) |
1109 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1110 | } |
99e300ef | 1111 | |
54623277 | 1112 | /* mulhwu mulhwu. */ |
99e300ef | 1113 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1114 | { |
23ad1d5d RH |
1115 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1116 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1117 | |
23ad1d5d RH |
1118 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1119 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1120 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1121 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1122 | tcg_temp_free_i32(t0); | |
1123 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1124 | if (unlikely(Rc(ctx->opcode) != 0)) |
1125 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1126 | } |
99e300ef | 1127 | |
54623277 | 1128 | /* mullw mullw. */ |
99e300ef | 1129 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1130 | { |
74637406 AJ |
1131 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1132 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1133 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
74637406 AJ |
1134 | if (unlikely(Rc(ctx->opcode) != 0)) |
1135 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1136 | } |
99e300ef | 1137 | |
54623277 | 1138 | /* mullwo mullwo. */ |
99e300ef | 1139 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1140 | { |
e4a2c846 RH |
1141 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1142 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1143 | |
e4a2c846 RH |
1144 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1145 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1146 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1147 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1148 | ||
1149 | tcg_gen_sari_i32(t0, t0, 31); | |
1150 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1151 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
1152 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1153 | ||
1154 | tcg_temp_free_i32(t0); | |
1155 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1156 | if (unlikely(Rc(ctx->opcode) != 0)) |
1157 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1158 | } |
99e300ef | 1159 | |
54623277 | 1160 | /* mulli */ |
99e300ef | 1161 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1162 | { |
74637406 AJ |
1163 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1164 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1165 | } |
23ad1d5d | 1166 | |
d9bce9d9 | 1167 | #if defined(TARGET_PPC64) |
74637406 | 1168 | /* mulhd mulhd. */ |
23ad1d5d RH |
1169 | static void gen_mulhd(DisasContext *ctx) |
1170 | { | |
1171 | TCGv lo = tcg_temp_new(); | |
1172 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1173 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1174 | tcg_temp_free(lo); | |
1175 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1176 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1177 | } | |
1178 | } | |
1179 | ||
74637406 | 1180 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1181 | static void gen_mulhdu(DisasContext *ctx) |
1182 | { | |
1183 | TCGv lo = tcg_temp_new(); | |
1184 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1185 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1186 | tcg_temp_free(lo); | |
1187 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1188 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1189 | } | |
1190 | } | |
99e300ef | 1191 | |
54623277 | 1192 | /* mulld mulld. */ |
99e300ef | 1193 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1194 | { |
74637406 AJ |
1195 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1196 | cpu_gpr[rB(ctx->opcode)]); | |
1197 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1198 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1199 | } |
d15f74fb | 1200 | |
74637406 | 1201 | /* mulldo mulldo. */ |
d15f74fb BS |
1202 | static void gen_mulldo(DisasContext *ctx) |
1203 | { | |
1204 | gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env, | |
1205 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1206 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1207 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1208 | } | |
1209 | } | |
d9bce9d9 | 1210 | #endif |
74637406 | 1211 | |
74637406 | 1212 | /* Common subf function */ |
636aa200 | 1213 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1214 | TCGv arg2, bool add_ca, bool compute_ca, |
1215 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1216 | { |
b5a73f8d | 1217 | TCGv t0 = ret; |
79aceca5 | 1218 | |
752d634e | 1219 | if (compute_ca || compute_ov) { |
b5a73f8d | 1220 | t0 = tcg_temp_new(); |
da91a00f | 1221 | } |
74637406 | 1222 | |
79482e5a RH |
1223 | if (compute_ca) { |
1224 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1225 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1226 | /* Caution: a non-obvious corner case of the spec is that we |
1227 | must produce the *entire* 64-bit addition, but produce the | |
1228 | carry into bit 32. */ | |
79482e5a | 1229 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1230 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1231 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1232 | if (add_ca) { |
752d634e | 1233 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1234 | } else { |
752d634e | 1235 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1236 | } |
752d634e | 1237 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1238 | tcg_gen_add_tl(t0, t0, inv1); |
c80d1df5 | 1239 | tcg_temp_free(inv1); |
752d634e RH |
1240 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1241 | tcg_temp_free(t1); | |
1242 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
1243 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
79482e5a | 1244 | } else if (add_ca) { |
08f4a0f7 RH |
1245 | TCGv zero, inv1 = tcg_temp_new(); |
1246 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1247 | zero = tcg_const_tl(0); |
1248 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1249 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
b5a73f8d | 1250 | tcg_temp_free(zero); |
08f4a0f7 | 1251 | tcg_temp_free(inv1); |
b5a73f8d | 1252 | } else { |
79482e5a | 1253 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1254 | tcg_gen_sub_tl(t0, arg2, arg1); |
b5a73f8d | 1255 | } |
79482e5a RH |
1256 | } else if (add_ca) { |
1257 | /* Since we're ignoring carry-out, we can simplify the | |
1258 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1259 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1260 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1261 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1262 | } else { |
b5a73f8d | 1263 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1264 | } |
b5a73f8d | 1265 | |
74637406 AJ |
1266 | if (compute_ov) { |
1267 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1268 | } | |
b5a73f8d | 1269 | if (unlikely(compute_rc0)) { |
74637406 | 1270 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1271 | } |
74637406 | 1272 | |
a7812ae4 | 1273 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1274 | tcg_gen_mov_tl(ret, t0); |
1275 | tcg_temp_free(t0); | |
79aceca5 | 1276 | } |
79aceca5 | 1277 | } |
74637406 AJ |
1278 | /* Sub functions with Two operands functions */ |
1279 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1280 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1281 | { \ |
1282 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1283 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1284 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1285 | } |
1286 | /* Sub functions with one operand and one immediate */ | |
1287 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1288 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1289 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1290 | { \ |
b5a73f8d | 1291 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1292 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1293 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1294 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1295 | tcg_temp_free(t0); \ |
1296 | } | |
1297 | /* subf subf. subfo subfo. */ | |
1298 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1299 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1300 | /* subfc subfc. subfco subfco. */ | |
1301 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1302 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1303 | /* subfe subfe. subfeo subfo. */ | |
1304 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1305 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1306 | /* subfme subfme. subfmeo subfmeo. */ | |
1307 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1308 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1309 | /* subfze subfze. subfzeo subfzeo.*/ | |
1310 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1311 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1312 | |
54623277 | 1313 | /* subfic */ |
99e300ef | 1314 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1315 | { |
b5a73f8d RH |
1316 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1317 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1318 | c, 0, 1, 0, 0); | |
1319 | tcg_temp_free(c); | |
79aceca5 FB |
1320 | } |
1321 | ||
fd3f0081 RH |
1322 | /* neg neg. nego nego. */ |
1323 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1324 | { | |
1325 | TCGv zero = tcg_const_tl(0); | |
1326 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1327 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1328 | tcg_temp_free(zero); | |
1329 | } | |
1330 | ||
1331 | static void gen_neg(DisasContext *ctx) | |
1332 | { | |
1333 | gen_op_arith_neg(ctx, 0); | |
1334 | } | |
1335 | ||
1336 | static void gen_nego(DisasContext *ctx) | |
1337 | { | |
1338 | gen_op_arith_neg(ctx, 1); | |
1339 | } | |
1340 | ||
79aceca5 | 1341 | /*** Integer logical ***/ |
26d67362 | 1342 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1343 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1344 | { \ |
26d67362 AJ |
1345 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1346 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1347 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1348 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1349 | } |
79aceca5 | 1350 | |
26d67362 | 1351 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1352 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1353 | { \ |
26d67362 | 1354 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1355 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1356 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1357 | } |
1358 | ||
1359 | /* and & and. */ | |
26d67362 | 1360 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1361 | /* andc & andc. */ |
26d67362 | 1362 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1363 | |
54623277 | 1364 | /* andi. */ |
e8eaa2c0 | 1365 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1366 | { |
26d67362 AJ |
1367 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1368 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1369 | } |
e8eaa2c0 | 1370 | |
54623277 | 1371 | /* andis. */ |
e8eaa2c0 | 1372 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1373 | { |
26d67362 AJ |
1374 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1375 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1376 | } |
99e300ef | 1377 | |
54623277 | 1378 | /* cntlzw */ |
99e300ef | 1379 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1380 | { |
a7812ae4 | 1381 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1382 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1383 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1384 | } |
79aceca5 | 1385 | /* eqv & eqv. */ |
26d67362 | 1386 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1387 | /* extsb & extsb. */ |
26d67362 | 1388 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1389 | /* extsh & extsh. */ |
26d67362 | 1390 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1391 | /* nand & nand. */ |
26d67362 | 1392 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1393 | /* nor & nor. */ |
26d67362 | 1394 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1395 | |
54623277 | 1396 | /* or & or. */ |
99e300ef | 1397 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1398 | { |
76a66253 JM |
1399 | int rs, ra, rb; |
1400 | ||
1401 | rs = rS(ctx->opcode); | |
1402 | ra = rA(ctx->opcode); | |
1403 | rb = rB(ctx->opcode); | |
1404 | /* Optimisation for mr. ri case */ | |
1405 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1406 | if (rs != rb) |
1407 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1408 | else | |
1409 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1410 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1411 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1412 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1413 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1414 | #if defined(TARGET_PPC64) |
1415 | } else { | |
26d67362 AJ |
1416 | int prio = 0; |
1417 | ||
c80f84e3 JM |
1418 | switch (rs) { |
1419 | case 1: | |
1420 | /* Set process priority to low */ | |
26d67362 | 1421 | prio = 2; |
c80f84e3 JM |
1422 | break; |
1423 | case 6: | |
1424 | /* Set process priority to medium-low */ | |
26d67362 | 1425 | prio = 3; |
c80f84e3 JM |
1426 | break; |
1427 | case 2: | |
1428 | /* Set process priority to normal */ | |
26d67362 | 1429 | prio = 4; |
c80f84e3 | 1430 | break; |
be147d08 JM |
1431 | #if !defined(CONFIG_USER_ONLY) |
1432 | case 31: | |
76db3ba4 | 1433 | if (ctx->mem_idx > 0) { |
be147d08 | 1434 | /* Set process priority to very low */ |
26d67362 | 1435 | prio = 1; |
be147d08 JM |
1436 | } |
1437 | break; | |
1438 | case 5: | |
76db3ba4 | 1439 | if (ctx->mem_idx > 0) { |
be147d08 | 1440 | /* Set process priority to medium-hight */ |
26d67362 | 1441 | prio = 5; |
be147d08 JM |
1442 | } |
1443 | break; | |
1444 | case 3: | |
76db3ba4 | 1445 | if (ctx->mem_idx > 0) { |
be147d08 | 1446 | /* Set process priority to high */ |
26d67362 | 1447 | prio = 6; |
be147d08 JM |
1448 | } |
1449 | break; | |
be147d08 | 1450 | case 7: |
76db3ba4 | 1451 | if (ctx->mem_idx > 1) { |
be147d08 | 1452 | /* Set process priority to very high */ |
26d67362 | 1453 | prio = 7; |
be147d08 JM |
1454 | } |
1455 | break; | |
be147d08 | 1456 | #endif |
c80f84e3 JM |
1457 | default: |
1458 | /* nop */ | |
1459 | break; | |
1460 | } | |
26d67362 | 1461 | if (prio) { |
a7812ae4 | 1462 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1463 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1464 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1465 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1466 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1467 | tcg_temp_free(t0); |
26d67362 | 1468 | } |
c80f84e3 | 1469 | #endif |
9a64fbe4 | 1470 | } |
9a64fbe4 | 1471 | } |
79aceca5 | 1472 | /* orc & orc. */ |
26d67362 | 1473 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1474 | |
54623277 | 1475 | /* xor & xor. */ |
99e300ef | 1476 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1477 | { |
9a64fbe4 | 1478 | /* Optimisation for "set to zero" case */ |
26d67362 | 1479 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1480 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1481 | else |
1482 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1483 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1484 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1485 | } |
99e300ef | 1486 | |
54623277 | 1487 | /* ori */ |
99e300ef | 1488 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1489 | { |
76a66253 | 1490 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1491 | |
9a64fbe4 FB |
1492 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1493 | /* NOP */ | |
76a66253 | 1494 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1495 | return; |
76a66253 | 1496 | } |
26d67362 | 1497 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1498 | } |
99e300ef | 1499 | |
54623277 | 1500 | /* oris */ |
99e300ef | 1501 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1502 | { |
76a66253 | 1503 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1504 | |
9a64fbe4 FB |
1505 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1506 | /* NOP */ | |
1507 | return; | |
76a66253 | 1508 | } |
26d67362 | 1509 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1510 | } |
99e300ef | 1511 | |
54623277 | 1512 | /* xori */ |
99e300ef | 1513 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1514 | { |
76a66253 | 1515 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1516 | |
1517 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1518 | /* NOP */ | |
1519 | return; | |
1520 | } | |
26d67362 | 1521 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1522 | } |
99e300ef | 1523 | |
54623277 | 1524 | /* xoris */ |
99e300ef | 1525 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1526 | { |
76a66253 | 1527 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1528 | |
1529 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1530 | /* NOP */ | |
1531 | return; | |
1532 | } | |
26d67362 | 1533 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1534 | } |
99e300ef | 1535 | |
54623277 | 1536 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1537 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1538 | { |
eaabeef2 DG |
1539 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1540 | } | |
1541 | ||
1542 | static void gen_popcntw(DisasContext *ctx) | |
1543 | { | |
1544 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1545 | } | |
1546 | ||
d9bce9d9 | 1547 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1548 | /* popcntd: PowerPC 2.06 specification */ |
1549 | static void gen_popcntd(DisasContext *ctx) | |
1550 | { | |
1551 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1552 | } |
eaabeef2 | 1553 | #endif |
d9bce9d9 | 1554 | |
725bcec2 AJ |
1555 | /* prtyw: PowerPC 2.05 specification */ |
1556 | static void gen_prtyw(DisasContext *ctx) | |
1557 | { | |
1558 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1559 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1560 | TCGv t0 = tcg_temp_new(); | |
1561 | tcg_gen_shri_tl(t0, rs, 16); | |
1562 | tcg_gen_xor_tl(ra, rs, t0); | |
1563 | tcg_gen_shri_tl(t0, ra, 8); | |
1564 | tcg_gen_xor_tl(ra, ra, t0); | |
1565 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1566 | tcg_temp_free(t0); | |
1567 | } | |
1568 | ||
1569 | #if defined(TARGET_PPC64) | |
1570 | /* prtyd: PowerPC 2.05 specification */ | |
1571 | static void gen_prtyd(DisasContext *ctx) | |
1572 | { | |
1573 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1574 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1575 | TCGv t0 = tcg_temp_new(); | |
1576 | tcg_gen_shri_tl(t0, rs, 32); | |
1577 | tcg_gen_xor_tl(ra, rs, t0); | |
1578 | tcg_gen_shri_tl(t0, ra, 16); | |
1579 | tcg_gen_xor_tl(ra, ra, t0); | |
1580 | tcg_gen_shri_tl(t0, ra, 8); | |
1581 | tcg_gen_xor_tl(ra, ra, t0); | |
1582 | tcg_gen_andi_tl(ra, ra, 1); | |
1583 | tcg_temp_free(t0); | |
1584 | } | |
1585 | #endif | |
1586 | ||
86ba37ed TM |
1587 | #if defined(TARGET_PPC64) |
1588 | /* bpermd */ | |
1589 | static void gen_bpermd(DisasContext *ctx) | |
1590 | { | |
1591 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
1592 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1593 | } | |
1594 | #endif | |
1595 | ||
d9bce9d9 JM |
1596 | #if defined(TARGET_PPC64) |
1597 | /* extsw & extsw. */ | |
26d67362 | 1598 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1599 | |
54623277 | 1600 | /* cntlzd */ |
99e300ef | 1601 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1602 | { |
a7812ae4 | 1603 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1604 | if (unlikely(Rc(ctx->opcode) != 0)) |
1605 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1606 | } | |
d9bce9d9 JM |
1607 | #endif |
1608 | ||
79aceca5 | 1609 | /*** Integer rotate ***/ |
99e300ef | 1610 | |
54623277 | 1611 | /* rlwimi & rlwimi. */ |
99e300ef | 1612 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1613 | { |
76a66253 | 1614 | uint32_t mb, me, sh; |
79aceca5 FB |
1615 | |
1616 | mb = MB(ctx->opcode); | |
1617 | me = ME(ctx->opcode); | |
76a66253 | 1618 | sh = SH(ctx->opcode); |
d03ef511 AJ |
1619 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1620 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1621 | } else { | |
d03ef511 | 1622 | target_ulong mask; |
a7812ae4 PB |
1623 | TCGv t1; |
1624 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1625 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1626 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1627 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1628 | tcg_gen_rotli_i32(t2, t2, sh); | |
1629 | tcg_gen_extu_i32_i64(t0, t2); | |
1630 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1631 | #else |
1632 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1633 | #endif | |
76a66253 | 1634 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1635 | mb += 32; |
1636 | me += 32; | |
76a66253 | 1637 | #endif |
d03ef511 | 1638 | mask = MASK(mb, me); |
a7812ae4 | 1639 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1640 | tcg_gen_andi_tl(t0, t0, mask); |
1641 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1642 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1643 | tcg_temp_free(t0); | |
1644 | tcg_temp_free(t1); | |
1645 | } | |
76a66253 | 1646 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1647 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1648 | } |
99e300ef | 1649 | |
54623277 | 1650 | /* rlwinm & rlwinm. */ |
99e300ef | 1651 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1652 | { |
1653 | uint32_t mb, me, sh; | |
3b46e624 | 1654 | |
79aceca5 FB |
1655 | sh = SH(ctx->opcode); |
1656 | mb = MB(ctx->opcode); | |
1657 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1658 | |
1659 | if (likely(mb == 0 && me == (31 - sh))) { | |
1660 | if (likely(sh == 0)) { | |
1661 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1662 | } else { | |
a7812ae4 | 1663 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1664 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1665 | tcg_gen_shli_tl(t0, t0, sh); | |
1666 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1667 | tcg_temp_free(t0); | |
79aceca5 | 1668 | } |
d03ef511 | 1669 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1670 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1671 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1672 | tcg_gen_shri_tl(t0, t0, mb); | |
1673 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1674 | tcg_temp_free(t0); | |
1675 | } else { | |
a7812ae4 | 1676 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1677 | #if defined(TARGET_PPC64) |
a7812ae4 | 1678 | TCGv_i32 t1 = tcg_temp_new_i32(); |
54843a58 AJ |
1679 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1680 | tcg_gen_rotli_i32(t1, t1, sh); | |
1681 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 | 1682 | tcg_temp_free_i32(t1); |
54843a58 AJ |
1683 | #else |
1684 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1685 | #endif | |
76a66253 | 1686 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1687 | mb += 32; |
1688 | me += 32; | |
76a66253 | 1689 | #endif |
d03ef511 AJ |
1690 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1691 | tcg_temp_free(t0); | |
1692 | } | |
76a66253 | 1693 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1694 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1695 | } |
99e300ef | 1696 | |
54623277 | 1697 | /* rlwnm & rlwnm. */ |
99e300ef | 1698 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1699 | { |
1700 | uint32_t mb, me; | |
54843a58 AJ |
1701 | TCGv t0; |
1702 | #if defined(TARGET_PPC64) | |
a7812ae4 | 1703 | TCGv_i32 t1, t2; |
54843a58 | 1704 | #endif |
79aceca5 FB |
1705 | |
1706 | mb = MB(ctx->opcode); | |
1707 | me = ME(ctx->opcode); | |
a7812ae4 | 1708 | t0 = tcg_temp_new(); |
d03ef511 | 1709 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1710 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1711 | t1 = tcg_temp_new_i32(); |
1712 | t2 = tcg_temp_new_i32(); | |
54843a58 AJ |
1713 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1714 | tcg_gen_trunc_i64_i32(t2, t0); | |
1715 | tcg_gen_rotl_i32(t1, t1, t2); | |
1716 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 PB |
1717 | tcg_temp_free_i32(t1); |
1718 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1719 | #else |
1720 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1721 | #endif | |
76a66253 JM |
1722 | if (unlikely(mb != 0 || me != 31)) { |
1723 | #if defined(TARGET_PPC64) | |
1724 | mb += 32; | |
1725 | me += 32; | |
1726 | #endif | |
54843a58 | 1727 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1728 | } else { |
54843a58 | 1729 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1730 | } |
54843a58 | 1731 | tcg_temp_free(t0); |
76a66253 | 1732 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1733 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1734 | } |
1735 | ||
d9bce9d9 JM |
1736 | #if defined(TARGET_PPC64) |
1737 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 1738 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1739 | { \ |
1740 | gen_##name(ctx, 0); \ | |
1741 | } \ | |
e8eaa2c0 BS |
1742 | \ |
1743 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1744 | { \ |
1745 | gen_##name(ctx, 1); \ | |
1746 | } | |
1747 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 1748 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
1749 | { \ |
1750 | gen_##name(ctx, 0, 0); \ | |
1751 | } \ | |
e8eaa2c0 BS |
1752 | \ |
1753 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1754 | { \ |
1755 | gen_##name(ctx, 0, 1); \ | |
1756 | } \ | |
e8eaa2c0 BS |
1757 | \ |
1758 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1759 | { \ |
1760 | gen_##name(ctx, 1, 0); \ | |
1761 | } \ | |
e8eaa2c0 BS |
1762 | \ |
1763 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1764 | { \ |
1765 | gen_##name(ctx, 1, 1); \ | |
1766 | } | |
51789c41 | 1767 | |
636aa200 BS |
1768 | static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me, |
1769 | uint32_t sh) | |
51789c41 | 1770 | { |
d03ef511 AJ |
1771 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1772 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1773 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1774 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1775 | } else { | |
a7812ae4 | 1776 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1777 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1778 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1779 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1780 | } else { |
1781 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1782 | } |
d03ef511 | 1783 | tcg_temp_free(t0); |
51789c41 | 1784 | } |
51789c41 | 1785 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1786 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1787 | } |
d9bce9d9 | 1788 | /* rldicl - rldicl. */ |
636aa200 | 1789 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1790 | { |
51789c41 | 1791 | uint32_t sh, mb; |
d9bce9d9 | 1792 | |
9d53c753 JM |
1793 | sh = SH(ctx->opcode) | (shn << 5); |
1794 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1795 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1796 | } |
51789c41 | 1797 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1798 | /* rldicr - rldicr. */ |
636aa200 | 1799 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1800 | { |
51789c41 | 1801 | uint32_t sh, me; |
d9bce9d9 | 1802 | |
9d53c753 JM |
1803 | sh = SH(ctx->opcode) | (shn << 5); |
1804 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1805 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1806 | } |
51789c41 | 1807 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 1808 | /* rldic - rldic. */ |
636aa200 | 1809 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1810 | { |
51789c41 | 1811 | uint32_t sh, mb; |
d9bce9d9 | 1812 | |
9d53c753 JM |
1813 | sh = SH(ctx->opcode) | (shn << 5); |
1814 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
1815 | gen_rldinm(ctx, mb, 63 - sh, sh); |
1816 | } | |
1817 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
1818 | ||
636aa200 | 1819 | static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me) |
51789c41 | 1820 | { |
54843a58 | 1821 | TCGv t0; |
d03ef511 | 1822 | |
a7812ae4 | 1823 | t0 = tcg_temp_new(); |
d03ef511 | 1824 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 1825 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 1826 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
1827 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1828 | } else { | |
1829 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1830 | } | |
1831 | tcg_temp_free(t0); | |
51789c41 | 1832 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1833 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1834 | } |
51789c41 | 1835 | |
d9bce9d9 | 1836 | /* rldcl - rldcl. */ |
636aa200 | 1837 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 1838 | { |
51789c41 | 1839 | uint32_t mb; |
d9bce9d9 | 1840 | |
9d53c753 | 1841 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 1842 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 1843 | } |
36081602 | 1844 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 1845 | /* rldcr - rldcr. */ |
636aa200 | 1846 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 1847 | { |
51789c41 | 1848 | uint32_t me; |
d9bce9d9 | 1849 | |
9d53c753 | 1850 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 1851 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 1852 | } |
36081602 | 1853 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 1854 | /* rldimi - rldimi. */ |
636aa200 | 1855 | static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1856 | { |
271a916e | 1857 | uint32_t sh, mb, me; |
d9bce9d9 | 1858 | |
9d53c753 JM |
1859 | sh = SH(ctx->opcode) | (shn << 5); |
1860 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 1861 | me = 63 - sh; |
d03ef511 AJ |
1862 | if (unlikely(sh == 0 && mb == 0)) { |
1863 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1864 | } else { | |
1865 | TCGv t0, t1; | |
1866 | target_ulong mask; | |
1867 | ||
a7812ae4 | 1868 | t0 = tcg_temp_new(); |
54843a58 | 1869 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 1870 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1871 | mask = MASK(mb, me); |
1872 | tcg_gen_andi_tl(t0, t0, mask); | |
1873 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1874 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1875 | tcg_temp_free(t0); | |
1876 | tcg_temp_free(t1); | |
51789c41 | 1877 | } |
51789c41 | 1878 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1879 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 1880 | } |
36081602 | 1881 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
1882 | #endif |
1883 | ||
79aceca5 | 1884 | /*** Integer shift ***/ |
99e300ef | 1885 | |
54623277 | 1886 | /* slw & slw. */ |
99e300ef | 1887 | static void gen_slw(DisasContext *ctx) |
26d67362 | 1888 | { |
7fd6bf7d | 1889 | TCGv t0, t1; |
26d67362 | 1890 | |
7fd6bf7d AJ |
1891 | t0 = tcg_temp_new(); |
1892 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1893 | #if defined(TARGET_PPC64) | |
1894 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1895 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1896 | #else | |
1897 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1898 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1899 | #endif | |
1900 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1901 | t1 = tcg_temp_new(); | |
1902 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
1903 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1904 | tcg_temp_free(t1); | |
fea0c503 | 1905 | tcg_temp_free(t0); |
7fd6bf7d | 1906 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
1907 | if (unlikely(Rc(ctx->opcode) != 0)) |
1908 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1909 | } | |
99e300ef | 1910 | |
54623277 | 1911 | /* sraw & sraw. */ |
99e300ef | 1912 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 1913 | { |
d15f74fb | 1914 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1915 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1916 | if (unlikely(Rc(ctx->opcode) != 0)) |
1917 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1918 | } | |
99e300ef | 1919 | |
54623277 | 1920 | /* srawi & srawi. */ |
99e300ef | 1921 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 1922 | { |
26d67362 | 1923 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
1924 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
1925 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
1926 | if (sh == 0) { | |
1927 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 1928 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 1929 | } else { |
ba4af3e4 RH |
1930 | TCGv t0; |
1931 | tcg_gen_ext32s_tl(dst, src); | |
1932 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
1933 | t0 = tcg_temp_new(); | |
1934 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
1935 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
1936 | tcg_temp_free(t0); | |
1937 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
1938 | tcg_gen_sari_tl(dst, dst, sh); | |
1939 | } | |
1940 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1941 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 1942 | } |
79aceca5 | 1943 | } |
99e300ef | 1944 | |
54623277 | 1945 | /* srw & srw. */ |
99e300ef | 1946 | static void gen_srw(DisasContext *ctx) |
26d67362 | 1947 | { |
fea0c503 | 1948 | TCGv t0, t1; |
d9bce9d9 | 1949 | |
7fd6bf7d AJ |
1950 | t0 = tcg_temp_new(); |
1951 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
1952 | #if defined(TARGET_PPC64) | |
1953 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
1954 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1955 | #else | |
1956 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
1957 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
1958 | #endif | |
1959 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1960 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 1961 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
1962 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
1963 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 1964 | tcg_temp_free(t1); |
fea0c503 | 1965 | tcg_temp_free(t0); |
26d67362 AJ |
1966 | if (unlikely(Rc(ctx->opcode) != 0)) |
1967 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1968 | } | |
54623277 | 1969 | |
d9bce9d9 JM |
1970 | #if defined(TARGET_PPC64) |
1971 | /* sld & sld. */ | |
99e300ef | 1972 | static void gen_sld(DisasContext *ctx) |
26d67362 | 1973 | { |
7fd6bf7d | 1974 | TCGv t0, t1; |
26d67362 | 1975 | |
7fd6bf7d AJ |
1976 | t0 = tcg_temp_new(); |
1977 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
1978 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
1979 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
1980 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1981 | t1 = tcg_temp_new(); | |
1982 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
1983 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1984 | tcg_temp_free(t1); | |
fea0c503 | 1985 | tcg_temp_free(t0); |
26d67362 AJ |
1986 | if (unlikely(Rc(ctx->opcode) != 0)) |
1987 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1988 | } | |
99e300ef | 1989 | |
54623277 | 1990 | /* srad & srad. */ |
99e300ef | 1991 | static void gen_srad(DisasContext *ctx) |
26d67362 | 1992 | { |
d15f74fb | 1993 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 1994 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1995 | if (unlikely(Rc(ctx->opcode) != 0)) |
1996 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1997 | } | |
d9bce9d9 | 1998 | /* sradi & sradi. */ |
636aa200 | 1999 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2000 | { |
26d67362 | 2001 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2002 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2003 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2004 | if (sh == 0) { | |
2005 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2006 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 2007 | } else { |
ba4af3e4 RH |
2008 | TCGv t0; |
2009 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2010 | t0 = tcg_temp_new(); | |
2011 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2012 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2013 | tcg_temp_free(t0); | |
2014 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
2015 | tcg_gen_sari_tl(dst, src, sh); | |
2016 | } | |
2017 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2018 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2019 | } |
d9bce9d9 | 2020 | } |
e8eaa2c0 BS |
2021 | |
2022 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2023 | { |
2024 | gen_sradi(ctx, 0); | |
2025 | } | |
e8eaa2c0 BS |
2026 | |
2027 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2028 | { |
2029 | gen_sradi(ctx, 1); | |
2030 | } | |
99e300ef | 2031 | |
54623277 | 2032 | /* srd & srd. */ |
99e300ef | 2033 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2034 | { |
7fd6bf7d | 2035 | TCGv t0, t1; |
26d67362 | 2036 | |
7fd6bf7d AJ |
2037 | t0 = tcg_temp_new(); |
2038 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2039 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2040 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2041 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2042 | t1 = tcg_temp_new(); | |
2043 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2044 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2045 | tcg_temp_free(t1); | |
fea0c503 | 2046 | tcg_temp_free(t0); |
26d67362 AJ |
2047 | if (unlikely(Rc(ctx->opcode) != 0)) |
2048 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2049 | } | |
d9bce9d9 | 2050 | #endif |
79aceca5 FB |
2051 | |
2052 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 2053 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef | 2054 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2055 | { \ |
76a66253 | 2056 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2057 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2058 | return; \ |
2059 | } \ | |
eb44b959 AJ |
2060 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2061 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2062 | gen_reset_fpstatus(); \ |
8e703949 BS |
2063 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2064 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2065 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2066 | if (isfloat) { \ |
8e703949 BS |
2067 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2068 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2069 | } \ |
af12906f AJ |
2070 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
2071 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
2072 | } |
2073 | ||
7c58044c JM |
2074 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
2075 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
2076 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 2077 | |
7c58044c | 2078 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2079 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2080 | { \ |
76a66253 | 2081 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2082 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2083 | return; \ |
2084 | } \ | |
eb44b959 AJ |
2085 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2086 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2087 | gen_reset_fpstatus(); \ |
8e703949 BS |
2088 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2089 | cpu_fpr[rA(ctx->opcode)], \ | |
af12906f | 2090 | cpu_fpr[rB(ctx->opcode)]); \ |
4ecc3190 | 2091 | if (isfloat) { \ |
8e703949 BS |
2092 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2093 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2094 | } \ |
af12906f AJ |
2095 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2096 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2097 | } |
7c58044c JM |
2098 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2099 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2100 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2101 | |
7c58044c | 2102 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef | 2103 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2104 | { \ |
76a66253 | 2105 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2106 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2107 | return; \ |
2108 | } \ | |
eb44b959 AJ |
2109 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2110 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2111 | gen_reset_fpstatus(); \ |
8e703949 BS |
2112 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2113 | cpu_fpr[rA(ctx->opcode)], \ | |
2114 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2115 | if (isfloat) { \ |
8e703949 BS |
2116 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2117 | cpu_fpr[rD(ctx->opcode)]); \ | |
4ecc3190 | 2118 | } \ |
af12906f AJ |
2119 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2120 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2121 | } |
7c58044c JM |
2122 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2123 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2124 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2125 | |
7c58044c | 2126 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef | 2127 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2128 | { \ |
76a66253 | 2129 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2130 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2131 | return; \ |
2132 | } \ | |
eb44b959 AJ |
2133 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2134 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2135 | gen_reset_fpstatus(); \ |
8e703949 BS |
2136 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2137 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2138 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2139 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2140 | } |
2141 | ||
7c58044c | 2142 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef | 2143 | static void gen_f##name(DisasContext *ctx) \ |
9a64fbe4 | 2144 | { \ |
76a66253 | 2145 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2146 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2147 | return; \ |
2148 | } \ | |
eb44b959 AJ |
2149 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2150 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2151 | gen_reset_fpstatus(); \ |
8e703949 BS |
2152 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \ |
2153 | cpu_fpr[rB(ctx->opcode)]); \ | |
af12906f AJ |
2154 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2155 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2156 | } |
2157 | ||
9a64fbe4 | 2158 | /* fadd - fadds */ |
7c58044c | 2159 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2160 | /* fdiv - fdivs */ |
7c58044c | 2161 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2162 | /* fmul - fmuls */ |
7c58044c | 2163 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2164 | |
d7e4b87e | 2165 | /* fre */ |
7c58044c | 2166 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2167 | |
a750fc0b | 2168 | /* fres */ |
7c58044c | 2169 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2170 | |
a750fc0b | 2171 | /* frsqrte */ |
7c58044c JM |
2172 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2173 | ||
2174 | /* frsqrtes */ | |
99e300ef | 2175 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2176 | { |
af12906f | 2177 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2178 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2179 | return; |
2180 | } | |
eb44b959 AJ |
2181 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2182 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f | 2183 | gen_reset_fpstatus(); |
8e703949 BS |
2184 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2185 | cpu_fpr[rB(ctx->opcode)]); | |
2186 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2187 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2188 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
7c58044c | 2189 | } |
79aceca5 | 2190 | |
a750fc0b | 2191 | /* fsel */ |
7c58044c | 2192 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2193 | /* fsub - fsubs */ |
7c58044c | 2194 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2195 | /* Optional: */ |
99e300ef | 2196 | |
54623277 | 2197 | /* fsqrt */ |
99e300ef | 2198 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2199 | { |
76a66253 | 2200 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2201 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2202 | return; |
2203 | } | |
eb44b959 AJ |
2204 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2205 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2206 | gen_reset_fpstatus(); |
8e703949 BS |
2207 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2208 | cpu_fpr[rB(ctx->opcode)]); | |
af12906f | 2209 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
c7d344af | 2210 | } |
79aceca5 | 2211 | |
99e300ef | 2212 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2213 | { |
76a66253 | 2214 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2215 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2216 | return; |
2217 | } | |
eb44b959 AJ |
2218 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2219 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2220 | gen_reset_fpstatus(); |
8e703949 BS |
2221 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env, |
2222 | cpu_fpr[rB(ctx->opcode)]); | |
2223 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, | |
2224 | cpu_fpr[rD(ctx->opcode)]); | |
af12906f | 2225 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2226 | } |
2227 | ||
2228 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2229 | /* fmadd - fmadds */ |
7c58044c | 2230 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2231 | /* fmsub - fmsubs */ |
7c58044c | 2232 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2233 | /* fnmadd - fnmadds */ |
7c58044c | 2234 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2235 | /* fnmsub - fnmsubs */ |
7c58044c | 2236 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2237 | |
2238 | /*** Floating-Point round & convert ***/ | |
2239 | /* fctiw */ | |
7c58044c | 2240 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
fab7fe42 TM |
2241 | /* fctiwu */ |
2242 | GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206); | |
79aceca5 | 2243 | /* fctiwz */ |
7c58044c | 2244 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
fab7fe42 TM |
2245 | /* fctiwuz */ |
2246 | GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206); | |
79aceca5 | 2247 | /* frsp */ |
7c58044c | 2248 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2249 | #if defined(TARGET_PPC64) |
2250 | /* fcfid */ | |
7c58044c | 2251 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
28288b48 TM |
2252 | /* fcfids */ |
2253 | GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206); | |
2254 | /* fcfidu */ | |
2255 | GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); | |
2256 | /* fcfidus */ | |
2257 | GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206); | |
426613db | 2258 | /* fctid */ |
7c58044c | 2259 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
fab7fe42 TM |
2260 | /* fctidu */ |
2261 | GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206); | |
426613db | 2262 | /* fctidz */ |
7c58044c | 2263 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
fab7fe42 TM |
2264 | /* fctidu */ |
2265 | GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206); | |
426613db | 2266 | #endif |
79aceca5 | 2267 | |
d7e4b87e | 2268 | /* frin */ |
7c58044c | 2269 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2270 | /* friz */ |
7c58044c | 2271 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2272 | /* frip */ |
7c58044c | 2273 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2274 | /* frim */ |
7c58044c | 2275 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2276 | |
da29cb7b TM |
2277 | static void gen_ftdiv(DisasContext *ctx) |
2278 | { | |
2279 | if (unlikely(!ctx->fpu_enabled)) { | |
2280 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2281 | return; | |
2282 | } | |
2283 | gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2284 | cpu_fpr[rB(ctx->opcode)]); | |
2285 | } | |
2286 | ||
6d41d146 TM |
2287 | static void gen_ftsqrt(DisasContext *ctx) |
2288 | { | |
2289 | if (unlikely(!ctx->fpu_enabled)) { | |
2290 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2291 | return; | |
2292 | } | |
2293 | gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2294 | } | |
2295 | ||
da29cb7b TM |
2296 | |
2297 | ||
79aceca5 | 2298 | /*** Floating-Point compare ***/ |
99e300ef | 2299 | |
54623277 | 2300 | /* fcmpo */ |
99e300ef | 2301 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2302 | { |
330c483b | 2303 | TCGv_i32 crf; |
76a66253 | 2304 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2305 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2306 | return; |
2307 | } | |
eb44b959 AJ |
2308 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2309 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2310 | gen_reset_fpstatus(); |
9a819377 | 2311 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2312 | gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2313 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2314 | tcg_temp_free_i32(crf); |
8e703949 | 2315 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2316 | } |
2317 | ||
2318 | /* fcmpu */ | |
99e300ef | 2319 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2320 | { |
330c483b | 2321 | TCGv_i32 crf; |
76a66253 | 2322 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2323 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2324 | return; |
2325 | } | |
eb44b959 AJ |
2326 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2327 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2328 | gen_reset_fpstatus(); |
9a819377 | 2329 | crf = tcg_const_i32(crfD(ctx->opcode)); |
8e703949 BS |
2330 | gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)], |
2331 | cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2332 | tcg_temp_free_i32(crf); |
8e703949 | 2333 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2334 | } |
2335 | ||
9a64fbe4 FB |
2336 | /*** Floating-point move ***/ |
2337 | /* fabs */ | |
7c58044c | 2338 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2339 | static void gen_fabs(DisasContext *ctx) |
2340 | { | |
2341 | if (unlikely(!ctx->fpu_enabled)) { | |
2342 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2343 | return; | |
2344 | } | |
2345 | tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2346 | ~(1ULL << 63)); | |
2347 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2348 | } | |
9a64fbe4 FB |
2349 | |
2350 | /* fmr - fmr. */ | |
7c58044c | 2351 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2352 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2353 | { |
76a66253 | 2354 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2355 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2356 | return; |
2357 | } | |
af12906f AJ |
2358 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2359 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2360 | } |
2361 | ||
2362 | /* fnabs */ | |
7c58044c | 2363 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2364 | static void gen_fnabs(DisasContext *ctx) |
2365 | { | |
2366 | if (unlikely(!ctx->fpu_enabled)) { | |
2367 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2368 | return; | |
2369 | } | |
2370 | tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2371 | 1ULL << 63); | |
2372 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2373 | } | |
2374 | ||
9a64fbe4 | 2375 | /* fneg */ |
7c58044c | 2376 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
bf45a2e6 AJ |
2377 | static void gen_fneg(DisasContext *ctx) |
2378 | { | |
2379 | if (unlikely(!ctx->fpu_enabled)) { | |
2380 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2381 | return; | |
2382 | } | |
2383 | tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], | |
2384 | 1ULL << 63); | |
2385 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2386 | } | |
9a64fbe4 | 2387 | |
f0332888 AJ |
2388 | /* fcpsgn: PowerPC 2.05 specification */ |
2389 | /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ | |
2390 | static void gen_fcpsgn(DisasContext *ctx) | |
2391 | { | |
2392 | if (unlikely(!ctx->fpu_enabled)) { | |
2393 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2394 | return; | |
2395 | } | |
2396 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2397 | cpu_fpr[rB(ctx->opcode)], 0, 63); | |
2398 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
2399 | } | |
2400 | ||
097ec5d8 TM |
2401 | static void gen_fmrgew(DisasContext *ctx) |
2402 | { | |
2403 | TCGv_i64 b0; | |
2404 | if (unlikely(!ctx->fpu_enabled)) { | |
2405 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2406 | return; | |
2407 | } | |
2408 | b0 = tcg_temp_new_i64(); | |
2409 | tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32); | |
2410 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], | |
2411 | b0, 0, 32); | |
2412 | tcg_temp_free_i64(b0); | |
2413 | } | |
2414 | ||
2415 | static void gen_fmrgow(DisasContext *ctx) | |
2416 | { | |
2417 | if (unlikely(!ctx->fpu_enabled)) { | |
2418 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
2419 | return; | |
2420 | } | |
2421 | tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], | |
2422 | cpu_fpr[rB(ctx->opcode)], | |
2423 | cpu_fpr[rA(ctx->opcode)], | |
2424 | 32, 32); | |
2425 | } | |
2426 | ||
79aceca5 | 2427 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2428 | |
54623277 | 2429 | /* mcrfs */ |
99e300ef | 2430 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2431 | { |
30304420 | 2432 | TCGv tmp = tcg_temp_new(); |
7c58044c JM |
2433 | int bfa; |
2434 | ||
76a66253 | 2435 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2436 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2437 | return; |
2438 | } | |
7c58044c | 2439 | bfa = 4 * (7 - crfS(ctx->opcode)); |
30304420 DG |
2440 | tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); |
2441 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); | |
2442 | tcg_temp_free(tmp); | |
e1571908 | 2443 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); |
30304420 | 2444 | tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2445 | } |
2446 | ||
2447 | /* mffs */ | |
99e300ef | 2448 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2449 | { |
76a66253 | 2450 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2451 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2452 | return; |
2453 | } | |
7c58044c | 2454 | gen_reset_fpstatus(); |
30304420 | 2455 | tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
af12906f | 2456 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); |
79aceca5 FB |
2457 | } |
2458 | ||
2459 | /* mtfsb0 */ | |
99e300ef | 2460 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2461 | { |
fb0eaffc | 2462 | uint8_t crb; |
3b46e624 | 2463 | |
76a66253 | 2464 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2465 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2466 | return; |
2467 | } | |
6e35d524 | 2468 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2469 | gen_reset_fpstatus(); |
6e35d524 | 2470 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2471 | TCGv_i32 t0; |
2472 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2473 | gen_update_nip(ctx, ctx->nip - 4); | |
2474 | t0 = tcg_const_i32(crb); | |
8e703949 | 2475 | gen_helper_fpscr_clrbit(cpu_env, t0); |
6e35d524 AJ |
2476 | tcg_temp_free_i32(t0); |
2477 | } | |
7c58044c | 2478 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2479 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2480 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c | 2481 | } |
79aceca5 FB |
2482 | } |
2483 | ||
2484 | /* mtfsb1 */ | |
99e300ef | 2485 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2486 | { |
fb0eaffc | 2487 | uint8_t crb; |
3b46e624 | 2488 | |
76a66253 | 2489 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2490 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2491 | return; |
2492 | } | |
6e35d524 | 2493 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2494 | gen_reset_fpstatus(); |
2495 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2496 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2497 | TCGv_i32 t0; |
2498 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2499 | gen_update_nip(ctx, ctx->nip - 4); | |
2500 | t0 = tcg_const_i32(crb); | |
8e703949 | 2501 | gen_helper_fpscr_setbit(cpu_env, t0); |
0f2f39c2 | 2502 | tcg_temp_free_i32(t0); |
af12906f | 2503 | } |
7c58044c | 2504 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2505 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2506 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2507 | } |
2508 | /* We can raise a differed exception */ | |
8e703949 | 2509 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2510 | } |
2511 | ||
2512 | /* mtfsf */ | |
99e300ef | 2513 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2514 | { |
0f2f39c2 | 2515 | TCGv_i32 t0; |
7d08d856 | 2516 | int flm, l, w; |
af12906f | 2517 | |
76a66253 | 2518 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2519 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2520 | return; |
2521 | } | |
7d08d856 AJ |
2522 | flm = FPFLM(ctx->opcode); |
2523 | l = FPL(ctx->opcode); | |
2524 | w = FPW(ctx->opcode); | |
2525 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2526 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2527 | return; | |
2528 | } | |
eb44b959 AJ |
2529 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2530 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2531 | gen_reset_fpstatus(); |
7d08d856 AJ |
2532 | if (l) { |
2533 | t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff); | |
2534 | } else { | |
2535 | t0 = tcg_const_i32(flm << (w * 8)); | |
2536 | } | |
8e703949 | 2537 | gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2538 | tcg_temp_free_i32(t0); |
7c58044c | 2539 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2540 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2541 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2542 | } |
2543 | /* We can raise a differed exception */ | |
8e703949 | 2544 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2545 | } |
2546 | ||
2547 | /* mtfsfi */ | |
99e300ef | 2548 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2549 | { |
7d08d856 | 2550 | int bf, sh, w; |
0f2f39c2 AJ |
2551 | TCGv_i64 t0; |
2552 | TCGv_i32 t1; | |
7c58044c | 2553 | |
76a66253 | 2554 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2555 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2556 | return; |
2557 | } | |
7d08d856 AJ |
2558 | w = FPW(ctx->opcode); |
2559 | bf = FPBF(ctx->opcode); | |
2560 | if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) { | |
2561 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2562 | return; | |
2563 | } | |
2564 | sh = (8 * w) + 7 - bf; | |
eb44b959 AJ |
2565 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2566 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2567 | gen_reset_fpstatus(); |
7d08d856 | 2568 | t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); |
af12906f | 2569 | t1 = tcg_const_i32(1 << sh); |
8e703949 | 2570 | gen_helper_store_fpscr(cpu_env, t0, t1); |
0f2f39c2 AJ |
2571 | tcg_temp_free_i64(t0); |
2572 | tcg_temp_free_i32(t1); | |
7c58044c | 2573 | if (unlikely(Rc(ctx->opcode) != 0)) { |
30304420 DG |
2574 | tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); |
2575 | tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); | |
7c58044c JM |
2576 | } |
2577 | /* We can raise a differed exception */ | |
8e703949 | 2578 | gen_helper_float_check_status(cpu_env); |
79aceca5 FB |
2579 | } |
2580 | ||
76a66253 JM |
2581 | /*** Addressing modes ***/ |
2582 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2583 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2584 | target_long maskl) | |
76a66253 JM |
2585 | { |
2586 | target_long simm = SIMM(ctx->opcode); | |
2587 | ||
be147d08 | 2588 | simm &= ~maskl; |
76db3ba4 | 2589 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2590 | if (NARROW_MODE(ctx)) { |
2591 | simm = (uint32_t)simm; | |
2592 | } | |
e2be8d8d | 2593 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2594 | } else if (likely(simm != 0)) { |
e2be8d8d | 2595 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2596 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2597 | tcg_gen_ext32u_tl(EA, EA); |
2598 | } | |
76db3ba4 | 2599 | } else { |
c791fe84 | 2600 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2601 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2602 | } else { |
2603 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2604 | } | |
76db3ba4 | 2605 | } |
76a66253 JM |
2606 | } |
2607 | ||
636aa200 | 2608 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2609 | { |
76db3ba4 | 2610 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2611 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2612 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2613 | } else { |
2614 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2615 | } | |
76db3ba4 | 2616 | } else { |
e2be8d8d | 2617 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2618 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2619 | tcg_gen_ext32u_tl(EA, EA); |
2620 | } | |
76db3ba4 | 2621 | } |
76a66253 JM |
2622 | } |
2623 | ||
636aa200 | 2624 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2625 | { |
76db3ba4 | 2626 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2627 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2628 | } else if (NARROW_MODE(ctx)) { |
2629 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2630 | } else { |
c791fe84 | 2631 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2632 | } |
2633 | } | |
2634 | ||
636aa200 BS |
2635 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2636 | target_long val) | |
76db3ba4 AJ |
2637 | { |
2638 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2639 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2640 | tcg_gen_ext32u_tl(ret, ret); |
2641 | } | |
76a66253 JM |
2642 | } |
2643 | ||
636aa200 | 2644 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 AJ |
2645 | { |
2646 | int l1 = gen_new_label(); | |
2647 | TCGv t0 = tcg_temp_new(); | |
2648 | TCGv_i32 t1, t2; | |
2649 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2650 | gen_update_nip(ctx, ctx->nip - 4); | |
2651 | tcg_gen_andi_tl(t0, EA, mask); | |
2652 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2653 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2654 | t2 = tcg_const_i32(0); | |
e5f17ac6 | 2655 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2656 | tcg_temp_free_i32(t1); |
2657 | tcg_temp_free_i32(t2); | |
2658 | gen_set_label(l1); | |
2659 | tcg_temp_free(t0); | |
2660 | } | |
2661 | ||
7863667f | 2662 | /*** Integer load ***/ |
636aa200 | 2663 | static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2664 | { |
2665 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2666 | } | |
2667 | ||
636aa200 | 2668 | static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 AJ |
2669 | { |
2670 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); | |
2671 | } | |
2672 | ||
636aa200 | 2673 | static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
76db3ba4 | 2674 | { |
e22c357b DK |
2675 | TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask; |
2676 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2677 | } |
2678 | ||
636aa200 | 2679 | static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2680 | { |
e22c357b DK |
2681 | TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask; |
2682 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2683 | } |
2684 | ||
636aa200 | 2685 | static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2686 | { |
e22c357b DK |
2687 | TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask; |
2688 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2689 | } |
2690 | ||
f976b09e AG |
2691 | static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2692 | { | |
2693 | TCGv tmp = tcg_temp_new(); | |
2694 | gen_qemu_ld32u(ctx, tmp, addr); | |
2695 | tcg_gen_extu_tl_i64(val, tmp); | |
2696 | tcg_temp_free(tmp); | |
2697 | } | |
2698 | ||
636aa200 | 2699 | static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2700 | { |
e22c357b DK |
2701 | TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask; |
2702 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2703 | } |
2704 | ||
cac7f0ba TM |
2705 | static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2706 | { | |
2707 | TCGv tmp = tcg_temp_new(); | |
2708 | gen_qemu_ld32s(ctx, tmp, addr); | |
2709 | tcg_gen_ext_tl_i64(val, tmp); | |
2710 | tcg_temp_free(tmp); | |
2711 | } | |
2712 | ||
636aa200 | 2713 | static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2714 | { |
e22c357b DK |
2715 | TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask; |
2716 | tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2717 | } |
2718 | ||
636aa200 | 2719 | static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2720 | { |
76db3ba4 | 2721 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2722 | } |
2723 | ||
636aa200 | 2724 | static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2725 | { |
e22c357b DK |
2726 | TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask; |
2727 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2728 | } |
2729 | ||
636aa200 | 2730 | static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2731 | { |
e22c357b DK |
2732 | TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask; |
2733 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2734 | } |
2735 | ||
f976b09e AG |
2736 | static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) |
2737 | { | |
2738 | TCGv tmp = tcg_temp_new(); | |
2739 | tcg_gen_trunc_i64_tl(tmp, val); | |
2740 | gen_qemu_st32(ctx, tmp, addr); | |
2741 | tcg_temp_free(tmp); | |
2742 | } | |
2743 | ||
636aa200 | 2744 | static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2745 | { |
e22c357b DK |
2746 | TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask; |
2747 | tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 AJ |
2748 | } |
2749 | ||
0c8aacd4 | 2750 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2751 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2752 | { \ |
76db3ba4 AJ |
2753 | TCGv EA; \ |
2754 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2755 | EA = tcg_temp_new(); \ | |
2756 | gen_addr_imm_index(ctx, EA, 0); \ | |
2757 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2758 | tcg_temp_free(EA); \ |
79aceca5 FB |
2759 | } |
2760 | ||
0c8aacd4 | 2761 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2762 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2763 | { \ |
b61f2753 | 2764 | TCGv EA; \ |
76a66253 JM |
2765 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2766 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2767 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2768 | return; \ |
9a64fbe4 | 2769 | } \ |
76db3ba4 | 2770 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2771 | EA = tcg_temp_new(); \ |
9d53c753 | 2772 | if (type == PPC_64B) \ |
76db3ba4 | 2773 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2774 | else \ |
76db3ba4 AJ |
2775 | gen_addr_imm_index(ctx, EA, 0); \ |
2776 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2777 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2778 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2779 | } |
2780 | ||
0c8aacd4 | 2781 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2782 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2783 | { \ |
b61f2753 | 2784 | TCGv EA; \ |
76a66253 JM |
2785 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2786 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2787 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2788 | return; \ |
9a64fbe4 | 2789 | } \ |
76db3ba4 | 2790 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2791 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2792 | gen_addr_reg_index(ctx, EA); \ |
2793 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2794 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2795 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2796 | } |
2797 | ||
cd6e9320 | 2798 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
99e300ef | 2799 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2800 | { \ |
76db3ba4 AJ |
2801 | TCGv EA; \ |
2802 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2803 | EA = tcg_temp_new(); \ | |
2804 | gen_addr_reg_index(ctx, EA); \ | |
2805 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2806 | tcg_temp_free(EA); \ |
79aceca5 | 2807 | } |
cd6e9320 TH |
2808 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2809 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2810 | |
0c8aacd4 AJ |
2811 | #define GEN_LDS(name, ldop, op, type) \ |
2812 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2813 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2814 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2815 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2816 | |
2817 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2818 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2819 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2820 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2821 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2822 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2823 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2824 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2825 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2826 | /* lwaux */ |
0c8aacd4 | 2827 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2828 | /* lwax */ |
0c8aacd4 | 2829 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2830 | /* ldux */ |
0c8aacd4 | 2831 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2832 | /* ldx */ |
0c8aacd4 | 2833 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2834 | |
2835 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2836 | { |
b61f2753 | 2837 | TCGv EA; |
d9bce9d9 JM |
2838 | if (Rc(ctx->opcode)) { |
2839 | if (unlikely(rA(ctx->opcode) == 0 || | |
2840 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2841 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2842 | return; |
2843 | } | |
2844 | } | |
76db3ba4 | 2845 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2846 | EA = tcg_temp_new(); |
76db3ba4 | 2847 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2848 | if (ctx->opcode & 0x02) { |
2849 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2850 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2851 | } else { |
2852 | /* ld - ldu */ | |
76db3ba4 | 2853 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2854 | } |
d9bce9d9 | 2855 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2856 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2857 | tcg_temp_free(EA); | |
d9bce9d9 | 2858 | } |
99e300ef | 2859 | |
54623277 | 2860 | /* lq */ |
99e300ef | 2861 | static void gen_lq(DisasContext *ctx) |
be147d08 | 2862 | { |
be147d08 | 2863 | int ra, rd; |
b61f2753 | 2864 | TCGv EA; |
be147d08 | 2865 | |
e0498daa TM |
2866 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2867 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2868 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2869 | ||
2870 | if (!legal_in_user_mode && is_user_mode(ctx)) { | |
e06fcd75 | 2871 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2872 | return; |
2873 | } | |
e0498daa TM |
2874 | |
2875 | if (!le_is_supported && ctx->le_mode) { | |
2876 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); | |
2877 | return; | |
2878 | } | |
2879 | ||
be147d08 JM |
2880 | ra = rA(ctx->opcode); |
2881 | rd = rD(ctx->opcode); | |
2882 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2883 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2884 | return; |
2885 | } | |
e0498daa | 2886 | |
76db3ba4 | 2887 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2888 | EA = tcg_temp_new(); |
76db3ba4 | 2889 | gen_addr_imm_index(ctx, EA, 0x0F); |
e0498daa | 2890 | |
e22c357b DK |
2891 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary |
2892 | 64-bit byteswap already. */ | |
e0498daa TM |
2893 | if (unlikely(ctx->le_mode)) { |
2894 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
2895 | gen_addr_add(ctx, EA, EA, 8); | |
2896 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2897 | } else { | |
2898 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2899 | gen_addr_add(ctx, EA, EA, 8); | |
2900 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
2901 | } | |
b61f2753 | 2902 | tcg_temp_free(EA); |
be147d08 | 2903 | } |
d9bce9d9 | 2904 | #endif |
79aceca5 FB |
2905 | |
2906 | /*** Integer store ***/ | |
0c8aacd4 | 2907 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2908 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2909 | { \ |
76db3ba4 AJ |
2910 | TCGv EA; \ |
2911 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2912 | EA = tcg_temp_new(); \ | |
2913 | gen_addr_imm_index(ctx, EA, 0); \ | |
2914 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2915 | tcg_temp_free(EA); \ |
79aceca5 FB |
2916 | } |
2917 | ||
0c8aacd4 | 2918 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2919 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2920 | { \ |
b61f2753 | 2921 | TCGv EA; \ |
76a66253 | 2922 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2923 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2924 | return; \ |
9a64fbe4 | 2925 | } \ |
76db3ba4 | 2926 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2927 | EA = tcg_temp_new(); \ |
9d53c753 | 2928 | if (type == PPC_64B) \ |
76db3ba4 | 2929 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2930 | else \ |
76db3ba4 AJ |
2931 | gen_addr_imm_index(ctx, EA, 0); \ |
2932 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2933 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2934 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2935 | } |
2936 | ||
0c8aacd4 | 2937 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2938 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2939 | { \ |
b61f2753 | 2940 | TCGv EA; \ |
76a66253 | 2941 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2942 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2943 | return; \ |
9a64fbe4 | 2944 | } \ |
76db3ba4 | 2945 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2946 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2947 | gen_addr_reg_index(ctx, EA); \ |
2948 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2949 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2950 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2951 | } |
2952 | ||
cd6e9320 TH |
2953 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
2954 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 2955 | { \ |
76db3ba4 AJ |
2956 | TCGv EA; \ |
2957 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2958 | EA = tcg_temp_new(); \ | |
2959 | gen_addr_reg_index(ctx, EA); \ | |
2960 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2961 | tcg_temp_free(EA); \ |
79aceca5 | 2962 | } |
cd6e9320 TH |
2963 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
2964 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE) | |
79aceca5 | 2965 | |
0c8aacd4 AJ |
2966 | #define GEN_STS(name, stop, op, type) \ |
2967 | GEN_ST(name, stop, op | 0x20, type); \ | |
2968 | GEN_STU(name, stop, op | 0x21, type); \ | |
2969 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2970 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2971 | |
2972 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2973 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2974 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2975 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2976 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2977 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2978 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
2979 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
2980 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
2981 | |
2982 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2983 | { |
be147d08 | 2984 | int rs; |
b61f2753 | 2985 | TCGv EA; |
be147d08 JM |
2986 | |
2987 | rs = rS(ctx->opcode); | |
84cab1e2 TM |
2988 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
2989 | ||
2990 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2991 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2992 | ||
2993 | if (!legal_in_user_mode && is_user_mode(ctx)) { | |
e06fcd75 | 2994 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2995 | return; |
2996 | } | |
84cab1e2 TM |
2997 | |
2998 | if (!le_is_supported && ctx->le_mode) { | |
2999 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); | |
d9bce9d9 JM |
3000 | return; |
3001 | } | |
84cab1e2 TM |
3002 | |
3003 | if (unlikely(rs & 1)) { | |
3004 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
be147d08 JM |
3005 | return; |
3006 | } | |
76db3ba4 | 3007 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 3008 | EA = tcg_temp_new(); |
76db3ba4 | 3009 | gen_addr_imm_index(ctx, EA, 0x03); |
84cab1e2 | 3010 | |
e22c357b DK |
3011 | /* We only need to swap high and low halves. gen_qemu_st64 does |
3012 | necessary 64-bit byteswap already. */ | |
84cab1e2 TM |
3013 | if (unlikely(ctx->le_mode)) { |
3014 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
3015 | gen_addr_add(ctx, EA, EA, 8); | |
3016 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
3017 | } else { | |
3018 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
3019 | gen_addr_add(ctx, EA, EA, 8); | |
3020 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
3021 | } | |
b61f2753 | 3022 | tcg_temp_free(EA); |
be147d08 | 3023 | } else { |
84cab1e2 | 3024 | /* std / stdu*/ |
be147d08 JM |
3025 | if (Rc(ctx->opcode)) { |
3026 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 3027 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
3028 | return; |
3029 | } | |
3030 | } | |
76db3ba4 | 3031 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 3032 | EA = tcg_temp_new(); |
76db3ba4 AJ |
3033 | gen_addr_imm_index(ctx, EA, 0x03); |
3034 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 3035 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
3036 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
3037 | tcg_temp_free(EA); | |
d9bce9d9 | 3038 | } |
d9bce9d9 JM |
3039 | } |
3040 | #endif | |
79aceca5 | 3041 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 3042 | |
79aceca5 | 3043 | /* lhbrx */ |
86178a57 | 3044 | static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3045 | { |
e22c357b DK |
3046 | TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3047 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3048 | } |
0c8aacd4 | 3049 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 3050 | |
79aceca5 | 3051 | /* lwbrx */ |
86178a57 | 3052 | static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3053 | { |
e22c357b DK |
3054 | TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3055 | tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3056 | } |
0c8aacd4 | 3057 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 3058 | |
cd6e9320 TH |
3059 | #if defined(TARGET_PPC64) |
3060 | /* ldbrx */ | |
3061 | static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
3062 | { | |
e22c357b DK |
3063 | TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3064 | tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op); | |
cd6e9320 TH |
3065 | } |
3066 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX); | |
3067 | #endif /* TARGET_PPC64 */ | |
3068 | ||
79aceca5 | 3069 | /* sthbrx */ |
86178a57 | 3070 | static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3071 | { |
e22c357b DK |
3072 | TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3073 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3074 | } |
0c8aacd4 | 3075 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 3076 | |
79aceca5 | 3077 | /* stwbrx */ |
86178a57 | 3078 | static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3079 | { |
e22c357b DK |
3080 | TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3081 | tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op); | |
b61f2753 | 3082 | } |
0c8aacd4 | 3083 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 | 3084 | |
cd6e9320 TH |
3085 | #if defined(TARGET_PPC64) |
3086 | /* stdbrx */ | |
3087 | static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
3088 | { | |
e22c357b DK |
3089 | TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP); |
3090 | tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op); | |
cd6e9320 TH |
3091 | } |
3092 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX); | |
3093 | #endif /* TARGET_PPC64 */ | |
3094 | ||
79aceca5 | 3095 | /*** Integer load and store multiple ***/ |
99e300ef | 3096 | |
54623277 | 3097 | /* lmw */ |
99e300ef | 3098 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 3099 | { |
76db3ba4 AJ |
3100 | TCGv t0; |
3101 | TCGv_i32 t1; | |
3102 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3103 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3104 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3105 | t0 = tcg_temp_new(); |
3106 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3107 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 3108 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
3109 | tcg_temp_free(t0); |
3110 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3111 | } |
3112 | ||
3113 | /* stmw */ | |
99e300ef | 3114 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 3115 | { |
76db3ba4 AJ |
3116 | TCGv t0; |
3117 | TCGv_i32 t1; | |
3118 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3119 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3120 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3121 | t0 = tcg_temp_new(); |
3122 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
3123 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 3124 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
3125 | tcg_temp_free(t0); |
3126 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3127 | } |
3128 | ||
3129 | /*** Integer load and store strings ***/ | |
54623277 | 3130 | |
79aceca5 | 3131 | /* lswi */ |
3fc6c082 | 3132 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
3133 | * rA is in the range of registers to be loaded. |
3134 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
3135 | * For now, I'll follow the spec... | |
3136 | */ | |
99e300ef | 3137 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 3138 | { |
dfbc799d AJ |
3139 | TCGv t0; |
3140 | TCGv_i32 t1, t2; | |
79aceca5 FB |
3141 | int nb = NB(ctx->opcode); |
3142 | int start = rD(ctx->opcode); | |
9a64fbe4 | 3143 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3144 | int nr; |
3145 | ||
3146 | if (nb == 0) | |
3147 | nb = 32; | |
3148 | nr = nb / 4; | |
76a66253 JM |
3149 | if (unlikely(((start + nr) > 32 && |
3150 | start <= ra && (start + nr - 32) > ra) || | |
3151 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 3152 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3153 | return; |
297d8e62 | 3154 | } |
76db3ba4 | 3155 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 3156 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3157 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 3158 | t0 = tcg_temp_new(); |
76db3ba4 | 3159 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
3160 | t1 = tcg_const_i32(nb); |
3161 | t2 = tcg_const_i32(start); | |
2f5a189c | 3162 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3163 | tcg_temp_free(t0); |
3164 | tcg_temp_free_i32(t1); | |
3165 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3166 | } |
3167 | ||
3168 | /* lswx */ | |
99e300ef | 3169 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3170 | { |
76db3ba4 AJ |
3171 | TCGv t0; |
3172 | TCGv_i32 t1, t2, t3; | |
3173 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3174 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3175 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3176 | t0 = tcg_temp_new(); |
3177 | gen_addr_reg_index(ctx, t0); | |
3178 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3179 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3180 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 3181 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
3182 | tcg_temp_free(t0); |
3183 | tcg_temp_free_i32(t1); | |
3184 | tcg_temp_free_i32(t2); | |
3185 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3186 | } |
3187 | ||
3188 | /* stswi */ | |
99e300ef | 3189 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3190 | { |
76db3ba4 AJ |
3191 | TCGv t0; |
3192 | TCGv_i32 t1, t2; | |
4b3686fa | 3193 | int nb = NB(ctx->opcode); |
76db3ba4 | 3194 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 3195 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3196 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3197 | t0 = tcg_temp_new(); |
3198 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3199 | if (nb == 0) |
3200 | nb = 32; | |
dfbc799d | 3201 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3202 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3203 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3204 | tcg_temp_free(t0); |
3205 | tcg_temp_free_i32(t1); | |
3206 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3207 | } |
3208 | ||
3209 | /* stswx */ | |
99e300ef | 3210 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3211 | { |
76db3ba4 AJ |
3212 | TCGv t0; |
3213 | TCGv_i32 t1, t2; | |
3214 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3215 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3216 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3217 | t0 = tcg_temp_new(); |
3218 | gen_addr_reg_index(ctx, t0); | |
3219 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3220 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3221 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3222 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3223 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3224 | tcg_temp_free(t0); |
3225 | tcg_temp_free_i32(t1); | |
3226 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3227 | } |
3228 | ||
3229 | /*** Memory synchronisation ***/ | |
3230 | /* eieio */ | |
99e300ef | 3231 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3232 | { |
79aceca5 FB |
3233 | } |
3234 | ||
3235 | /* isync */ | |
99e300ef | 3236 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3237 | { |
e06fcd75 | 3238 | gen_stop_exception(ctx); |
79aceca5 FB |
3239 | } |
3240 | ||
5c77a786 TM |
3241 | #define LARX(name, len, loadop) \ |
3242 | static void gen_##name(DisasContext *ctx) \ | |
3243 | { \ | |
3244 | TCGv t0; \ | |
3245 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ | |
3246 | gen_set_access_type(ctx, ACCESS_RES); \ | |
3247 | t0 = tcg_temp_local_new(); \ | |
3248 | gen_addr_reg_index(ctx, t0); \ | |
3249 | if ((len) > 1) { \ | |
3250 | gen_check_align(ctx, t0, (len)-1); \ | |
3251 | } \ | |
3252 | gen_qemu_##loadop(ctx, gpr, t0); \ | |
3253 | tcg_gen_mov_tl(cpu_reserve, t0); \ | |
3254 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ | |
3255 | tcg_temp_free(t0); \ | |
79aceca5 FB |
3256 | } |
3257 | ||
5c77a786 TM |
3258 | /* lwarx */ |
3259 | LARX(lbarx, 1, ld8u); | |
3260 | LARX(lharx, 2, ld16u); | |
3261 | LARX(lwarx, 4, ld32u); | |
3262 | ||
3263 | ||
4425265b | 3264 | #if defined(CONFIG_USER_ONLY) |
587c51f7 TM |
3265 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
3266 | int reg, int size) | |
4425265b NF |
3267 | { |
3268 | TCGv t0 = tcg_temp_new(); | |
3269 | uint32_t save_exception = ctx->exception; | |
3270 | ||
1328c2bf | 3271 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
4425265b | 3272 | tcg_gen_movi_tl(t0, (size << 5) | reg); |
1328c2bf | 3273 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b NF |
3274 | tcg_temp_free(t0); |
3275 | gen_update_nip(ctx, ctx->nip-4); | |
3276 | ctx->exception = POWERPC_EXCP_BRANCH; | |
3277 | gen_exception(ctx, POWERPC_EXCP_STCX); | |
3278 | ctx->exception = save_exception; | |
3279 | } | |
4425265b | 3280 | #else |
587c51f7 TM |
3281 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
3282 | int reg, int size) | |
3283 | { | |
3284 | int l1; | |
4425265b | 3285 | |
587c51f7 TM |
3286 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3287 | l1 = gen_new_label(); | |
3288 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); | |
3289 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3290 | #if defined(TARGET_PPC64) | |
3291 | if (size == 8) { | |
3292 | gen_qemu_st64(ctx, cpu_gpr[reg], EA); | |
3293 | } else | |
3294 | #endif | |
3295 | if (size == 4) { | |
3296 | gen_qemu_st32(ctx, cpu_gpr[reg], EA); | |
3297 | } else if (size == 2) { | |
3298 | gen_qemu_st16(ctx, cpu_gpr[reg], EA); | |
27b95bfe TM |
3299 | #if defined(TARGET_PPC64) |
3300 | } else if (size == 16) { | |
3707cd62 | 3301 | TCGv gpr1, gpr2 , EA8; |
27b95bfe TM |
3302 | if (unlikely(ctx->le_mode)) { |
3303 | gpr1 = cpu_gpr[reg+1]; | |
3304 | gpr2 = cpu_gpr[reg]; | |
3305 | } else { | |
3306 | gpr1 = cpu_gpr[reg]; | |
3307 | gpr2 = cpu_gpr[reg+1]; | |
3308 | } | |
3309 | gen_qemu_st64(ctx, gpr1, EA); | |
3707cd62 TM |
3310 | EA8 = tcg_temp_local_new(); |
3311 | gen_addr_add(ctx, EA8, EA, 8); | |
3312 | gen_qemu_st64(ctx, gpr2, EA8); | |
3313 | tcg_temp_free(EA8); | |
27b95bfe | 3314 | #endif |
587c51f7 TM |
3315 | } else { |
3316 | gen_qemu_st8(ctx, cpu_gpr[reg], EA); | |
4425265b | 3317 | } |
587c51f7 TM |
3318 | gen_set_label(l1); |
3319 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3320 | } | |
4425265b | 3321 | #endif |
587c51f7 TM |
3322 | |
3323 | #define STCX(name, len) \ | |
3324 | static void gen_##name(DisasContext *ctx) \ | |
3325 | { \ | |
3326 | TCGv t0; \ | |
27b95bfe TM |
3327 | if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \ |
3328 | gen_inval_exception(ctx, \ | |
3329 | POWERPC_EXCP_INVAL_INVAL); \ | |
3330 | return; \ | |
3331 | } \ | |
587c51f7 TM |
3332 | gen_set_access_type(ctx, ACCESS_RES); \ |
3333 | t0 = tcg_temp_local_new(); \ | |
3334 | gen_addr_reg_index(ctx, t0); \ | |
3335 | if (len > 1) { \ | |
3336 | gen_check_align(ctx, t0, (len)-1); \ | |
3337 | } \ | |
3338 | gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \ | |
3339 | tcg_temp_free(t0); \ | |
79aceca5 FB |
3340 | } |
3341 | ||
587c51f7 TM |
3342 | STCX(stbcx_, 1); |
3343 | STCX(sthcx_, 2); | |
3344 | STCX(stwcx_, 4); | |
3345 | ||
426613db | 3346 | #if defined(TARGET_PPC64) |
426613db | 3347 | /* ldarx */ |
5c77a786 | 3348 | LARX(ldarx, 8, ld64); |
426613db | 3349 | |
9c294d5a TM |
3350 | /* lqarx */ |
3351 | static void gen_lqarx(DisasContext *ctx) | |
3352 | { | |
3353 | TCGv EA; | |
3354 | int rd = rD(ctx->opcode); | |
3355 | TCGv gpr1, gpr2; | |
3356 | ||
3357 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3358 | (rd == rB(ctx->opcode)))) { | |
3359 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3360 | return; | |
3361 | } | |
3362 | ||
3363 | gen_set_access_type(ctx, ACCESS_RES); | |
3364 | EA = tcg_temp_local_new(); | |
3365 | gen_addr_reg_index(ctx, EA); | |
3366 | gen_check_align(ctx, EA, 15); | |
3367 | if (unlikely(ctx->le_mode)) { | |
3368 | gpr1 = cpu_gpr[rd+1]; | |
3369 | gpr2 = cpu_gpr[rd]; | |
3370 | } else { | |
3371 | gpr1 = cpu_gpr[rd]; | |
3372 | gpr2 = cpu_gpr[rd+1]; | |
3373 | } | |
3374 | gen_qemu_ld64(ctx, gpr1, EA); | |
3375 | tcg_gen_mov_tl(cpu_reserve, EA); | |
3376 | ||
3377 | gen_addr_add(ctx, EA, EA, 8); | |
3378 | gen_qemu_ld64(ctx, gpr2, EA); | |
3379 | ||
3380 | tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); | |
3381 | tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
3382 | ||
3383 | tcg_temp_free(EA); | |
3384 | } | |
3385 | ||
426613db | 3386 | /* stdcx. */ |
587c51f7 | 3387 | STCX(stdcx_, 8); |
27b95bfe | 3388 | STCX(stqcx_, 16); |
426613db JM |
3389 | #endif /* defined(TARGET_PPC64) */ |
3390 | ||
79aceca5 | 3391 | /* sync */ |
99e300ef | 3392 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3393 | { |
79aceca5 FB |
3394 | } |
3395 | ||
0db1b20e | 3396 | /* wait */ |
99e300ef | 3397 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3398 | { |
931ff272 | 3399 | TCGv_i32 t0 = tcg_temp_new_i32(); |
259186a7 AF |
3400 | tcg_gen_st_i32(t0, cpu_env, |
3401 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3402 | tcg_temp_free_i32(t0); |
0db1b20e | 3403 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3404 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3405 | } |
3406 | ||
79aceca5 | 3407 | /*** Floating-point load ***/ |
a0d7d5a7 | 3408 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef | 3409 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3410 | { \ |
a0d7d5a7 | 3411 | TCGv EA; \ |
76a66253 | 3412 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3413 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3414 | return; \ |
3415 | } \ | |
76db3ba4 | 3416 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3417 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3418 | gen_addr_imm_index(ctx, EA, 0); \ |
3419 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3420 | tcg_temp_free(EA); \ |
79aceca5 FB |
3421 | } |
3422 | ||
a0d7d5a7 | 3423 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef | 3424 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3425 | { \ |
a0d7d5a7 | 3426 | TCGv EA; \ |
76a66253 | 3427 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3428 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3429 | return; \ |
3430 | } \ | |
76a66253 | 3431 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3432 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3433 | return; \ |
9a64fbe4 | 3434 | } \ |
76db3ba4 | 3435 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3436 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3437 | gen_addr_imm_index(ctx, EA, 0); \ |
3438 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3439 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3440 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3441 | } |
3442 | ||
a0d7d5a7 | 3443 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef | 3444 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3445 | { \ |
a0d7d5a7 | 3446 | TCGv EA; \ |
76a66253 | 3447 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3448 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3449 | return; \ |
3450 | } \ | |
76a66253 | 3451 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3452 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3453 | return; \ |
9a64fbe4 | 3454 | } \ |
76db3ba4 | 3455 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3456 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3457 | gen_addr_reg_index(ctx, EA); \ |
3458 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3459 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3460 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3461 | } |
3462 | ||
a0d7d5a7 | 3463 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef | 3464 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3465 | { \ |
a0d7d5a7 | 3466 | TCGv EA; \ |
76a66253 | 3467 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3468 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3469 | return; \ |
3470 | } \ | |
76db3ba4 | 3471 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3472 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3473 | gen_addr_reg_index(ctx, EA); \ |
3474 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3475 | tcg_temp_free(EA); \ |
79aceca5 FB |
3476 | } |
3477 | ||
a0d7d5a7 AJ |
3478 | #define GEN_LDFS(name, ldop, op, type) \ |
3479 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3480 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3481 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3482 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3483 | ||
636aa200 | 3484 | static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3485 | { |
3486 | TCGv t0 = tcg_temp_new(); | |
3487 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3488 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3489 | tcg_gen_trunc_tl_i32(t1, t0); |
3490 | tcg_temp_free(t0); | |
8e703949 | 3491 | gen_helper_float32_to_float64(arg1, cpu_env, t1); |
a0d7d5a7 AJ |
3492 | tcg_temp_free_i32(t1); |
3493 | } | |
79aceca5 | 3494 | |
a0d7d5a7 AJ |
3495 | /* lfd lfdu lfdux lfdx */ |
3496 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3497 | /* lfs lfsu lfsux lfsx */ | |
3498 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 | 3499 | |
05050ee8 AJ |
3500 | /* lfdp */ |
3501 | static void gen_lfdp(DisasContext *ctx) | |
3502 | { | |
3503 | TCGv EA; | |
3504 | if (unlikely(!ctx->fpu_enabled)) { | |
3505 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3506 | return; | |
3507 | } | |
3508 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3509 | EA = tcg_temp_new(); | |
e22c357b DK |
3510 | gen_addr_imm_index(ctx, EA, 0); |
3511 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary | |
3512 | 64-bit byteswap already. */ | |
05050ee8 AJ |
3513 | if (unlikely(ctx->le_mode)) { |
3514 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3515 | tcg_gen_addi_tl(EA, EA, 8); | |
3516 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3517 | } else { | |
3518 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3519 | tcg_gen_addi_tl(EA, EA, 8); | |
3520 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3521 | } | |
3522 | tcg_temp_free(EA); | |
3523 | } | |
3524 | ||
3525 | /* lfdpx */ | |
3526 | static void gen_lfdpx(DisasContext *ctx) | |
3527 | { | |
3528 | TCGv EA; | |
3529 | if (unlikely(!ctx->fpu_enabled)) { | |
3530 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3531 | return; | |
3532 | } | |
3533 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3534 | EA = tcg_temp_new(); | |
3535 | gen_addr_reg_index(ctx, EA); | |
e22c357b DK |
3536 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary |
3537 | 64-bit byteswap already. */ | |
05050ee8 AJ |
3538 | if (unlikely(ctx->le_mode)) { |
3539 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3540 | tcg_gen_addi_tl(EA, EA, 8); | |
3541 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3542 | } else { | |
3543 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3544 | tcg_gen_addi_tl(EA, EA, 8); | |
3545 | gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3546 | } | |
3547 | tcg_temp_free(EA); | |
3548 | } | |
3549 | ||
199f830d AJ |
3550 | /* lfiwax */ |
3551 | static void gen_lfiwax(DisasContext *ctx) | |
3552 | { | |
3553 | TCGv EA; | |
3554 | TCGv t0; | |
3555 | if (unlikely(!ctx->fpu_enabled)) { | |
3556 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3557 | return; | |
3558 | } | |
3559 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3560 | EA = tcg_temp_new(); | |
3561 | t0 = tcg_temp_new(); | |
3562 | gen_addr_reg_index(ctx, EA); | |
909eedb7 | 3563 | gen_qemu_ld32s(ctx, t0, EA); |
199f830d | 3564 | tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0); |
199f830d AJ |
3565 | tcg_temp_free(EA); |
3566 | tcg_temp_free(t0); | |
3567 | } | |
3568 | ||
66c3e328 TM |
3569 | /* lfiwzx */ |
3570 | static void gen_lfiwzx(DisasContext *ctx) | |
3571 | { | |
3572 | TCGv EA; | |
3573 | if (unlikely(!ctx->fpu_enabled)) { | |
3574 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3575 | return; | |
3576 | } | |
3577 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3578 | EA = tcg_temp_new(); | |
3579 | gen_addr_reg_index(ctx, EA); | |
3580 | gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3581 | tcg_temp_free(EA); | |
3582 | } | |
79aceca5 | 3583 | /*** Floating-point store ***/ |
a0d7d5a7 | 3584 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef | 3585 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3586 | { \ |
a0d7d5a7 | 3587 | TCGv EA; \ |
76a66253 | 3588 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3589 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3590 | return; \ |
3591 | } \ | |
76db3ba4 | 3592 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3593 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3594 | gen_addr_imm_index(ctx, EA, 0); \ |
3595 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3596 | tcg_temp_free(EA); \ |
79aceca5 FB |
3597 | } |
3598 | ||
a0d7d5a7 | 3599 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef | 3600 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 3601 | { \ |
a0d7d5a7 | 3602 | TCGv EA; \ |
76a66253 | 3603 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3604 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3605 | return; \ |
3606 | } \ | |
76a66253 | 3607 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3608 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3609 | return; \ |
9a64fbe4 | 3610 | } \ |
76db3ba4 | 3611 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3612 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3613 | gen_addr_imm_index(ctx, EA, 0); \ |
3614 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3615 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3616 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3617 | } |
3618 | ||
a0d7d5a7 | 3619 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef | 3620 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 3621 | { \ |
a0d7d5a7 | 3622 | TCGv EA; \ |
76a66253 | 3623 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3624 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3625 | return; \ |
3626 | } \ | |
76a66253 | 3627 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3628 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3629 | return; \ |
9a64fbe4 | 3630 | } \ |
76db3ba4 | 3631 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3632 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3633 | gen_addr_reg_index(ctx, EA); \ |
3634 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3635 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3636 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3637 | } |
3638 | ||
a0d7d5a7 | 3639 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef | 3640 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 3641 | { \ |
a0d7d5a7 | 3642 | TCGv EA; \ |
76a66253 | 3643 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3644 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3645 | return; \ |
3646 | } \ | |
76db3ba4 | 3647 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3648 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3649 | gen_addr_reg_index(ctx, EA); \ |
3650 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3651 | tcg_temp_free(EA); \ |
79aceca5 FB |
3652 | } |
3653 | ||
a0d7d5a7 AJ |
3654 | #define GEN_STFS(name, stop, op, type) \ |
3655 | GEN_STF(name, stop, op | 0x20, type); \ | |
3656 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3657 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3658 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3659 | ||
636aa200 | 3660 | static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3661 | { |
3662 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3663 | TCGv t1 = tcg_temp_new(); | |
8e703949 | 3664 | gen_helper_float64_to_float32(t0, cpu_env, arg1); |
a0d7d5a7 AJ |
3665 | tcg_gen_extu_i32_tl(t1, t0); |
3666 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3667 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3668 | tcg_temp_free(t1); |
3669 | } | |
79aceca5 FB |
3670 | |
3671 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3672 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3673 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3674 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 | 3675 | |
44bc0c4d AJ |
3676 | /* stfdp */ |
3677 | static void gen_stfdp(DisasContext *ctx) | |
3678 | { | |
3679 | TCGv EA; | |
3680 | if (unlikely(!ctx->fpu_enabled)) { | |
3681 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3682 | return; | |
3683 | } | |
3684 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3685 | EA = tcg_temp_new(); | |
e22c357b DK |
3686 | gen_addr_imm_index(ctx, EA, 0); |
3687 | /* We only need to swap high and low halves. gen_qemu_st64 does necessary | |
3688 | 64-bit byteswap already. */ | |
44bc0c4d AJ |
3689 | if (unlikely(ctx->le_mode)) { |
3690 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3691 | tcg_gen_addi_tl(EA, EA, 8); | |
3692 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3693 | } else { | |
3694 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3695 | tcg_gen_addi_tl(EA, EA, 8); | |
3696 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3697 | } | |
3698 | tcg_temp_free(EA); | |
3699 | } | |
3700 | ||
3701 | /* stfdpx */ | |
3702 | static void gen_stfdpx(DisasContext *ctx) | |
3703 | { | |
3704 | TCGv EA; | |
3705 | if (unlikely(!ctx->fpu_enabled)) { | |
3706 | gen_exception(ctx, POWERPC_EXCP_FPU); | |
3707 | return; | |
3708 | } | |
3709 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
3710 | EA = tcg_temp_new(); | |
3711 | gen_addr_reg_index(ctx, EA); | |
e22c357b DK |
3712 | /* We only need to swap high and low halves. gen_qemu_st64 does necessary |
3713 | 64-bit byteswap already. */ | |
44bc0c4d AJ |
3714 | if (unlikely(ctx->le_mode)) { |
3715 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3716 | tcg_gen_addi_tl(EA, EA, 8); | |
3717 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3718 | } else { | |
3719 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA); | |
3720 | tcg_gen_addi_tl(EA, EA, 8); | |
3721 | gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA); | |
3722 | } | |
3723 | tcg_temp_free(EA); | |
3724 | } | |
3725 | ||
79aceca5 | 3726 | /* Optional: */ |
636aa200 | 3727 | static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3728 | { |
3729 | TCGv t0 = tcg_temp_new(); | |
3730 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3731 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3732 | tcg_temp_free(t0); |
3733 | } | |
79aceca5 | 3734 | /* stfiwx */ |
a0d7d5a7 | 3735 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 | 3736 | |
697ab892 DG |
3737 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3738 | { | |
3739 | #if defined(TARGET_PPC64) | |
3740 | if (ctx->has_cfar) | |
3741 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3742 | #endif | |
3743 | } | |
3744 | ||
79aceca5 | 3745 | /*** Branch ***/ |
636aa200 | 3746 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 FB |
3747 | { |
3748 | TranslationBlock *tb; | |
3749 | tb = ctx->tb; | |
e0c8f9ce | 3750 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3751 | dest = (uint32_t) dest; |
e0c8f9ce | 3752 | } |
57fec1fe | 3753 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3754 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3755 | tcg_gen_goto_tb(n); |
a2ffb812 | 3756 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cfd0495 | 3757 | tcg_gen_exit_tb((uintptr_t)tb + n); |
c1942362 | 3758 | } else { |
a2ffb812 | 3759 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3760 | if (unlikely(ctx->singlestep_enabled)) { |
3761 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3762 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3763 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3764 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
8cbcb4fa AJ |
3765 | target_ulong tmp = ctx->nip; |
3766 | ctx->nip = dest; | |
e06fcd75 | 3767 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3768 | ctx->nip = tmp; |
3769 | } | |
3770 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3771 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3772 | } |
3773 | } | |
57fec1fe | 3774 | tcg_gen_exit_tb(0); |
c1942362 | 3775 | } |
c53be334 FB |
3776 | } |
3777 | ||
636aa200 | 3778 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3779 | { |
e0c8f9ce RH |
3780 | if (NARROW_MODE(ctx)) { |
3781 | nip = (uint32_t)nip; | |
3782 | } | |
3783 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3784 | } |
3785 | ||
79aceca5 | 3786 | /* b ba bl bla */ |
99e300ef | 3787 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3788 | { |
76a66253 | 3789 | target_ulong li, target; |
38a64f9d | 3790 | |
8cbcb4fa | 3791 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3792 | /* sign extend LI */ |
e0c8f9ce RH |
3793 | li = LI(ctx->opcode); |
3794 | li = (li ^ 0x02000000) - 0x02000000; | |
3795 | if (likely(AA(ctx->opcode) == 0)) { | |
046d6672 | 3796 | target = ctx->nip + li - 4; |
e0c8f9ce | 3797 | } else { |
9a64fbe4 | 3798 | target = li; |
e0c8f9ce RH |
3799 | } |
3800 | if (LK(ctx->opcode)) { | |
e1833e1f | 3801 | gen_setlr(ctx, ctx->nip); |
e0c8f9ce | 3802 | } |
697ab892 | 3803 | gen_update_cfar(ctx, ctx->nip); |
c1942362 | 3804 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3805 | } |
3806 | ||
e98a6e40 FB |
3807 | #define BCOND_IM 0 |
3808 | #define BCOND_LR 1 | |
3809 | #define BCOND_CTR 2 | |
52a4984d | 3810 | #define BCOND_TAR 3 |
e98a6e40 | 3811 | |
636aa200 | 3812 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3813 | { |
d9bce9d9 | 3814 | uint32_t bo = BO(ctx->opcode); |
05f92404 | 3815 | int l1; |
a2ffb812 | 3816 | TCGv target; |
e98a6e40 | 3817 | |
8cbcb4fa | 3818 | ctx->exception = POWERPC_EXCP_BRANCH; |
52a4984d | 3819 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
a7812ae4 | 3820 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3821 | if (type == BCOND_CTR) |
3822 | tcg_gen_mov_tl(target, cpu_ctr); | |
52a4984d TM |
3823 | else if (type == BCOND_TAR) |
3824 | gen_load_spr(target, SPR_TAR); | |
a2ffb812 AJ |
3825 | else |
3826 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3827 | } else { |
3828 | TCGV_UNUSED(target); | |
e98a6e40 | 3829 | } |
e1833e1f JM |
3830 | if (LK(ctx->opcode)) |
3831 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3832 | l1 = gen_new_label(); |
3833 | if ((bo & 0x4) == 0) { | |
3834 | /* Decrement and test CTR */ | |
a7812ae4 | 3835 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3836 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3837 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3838 | return; |
3839 | } | |
3840 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3841 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3842 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3843 | } else { |
a2ffb812 | 3844 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3845 | } |
a2ffb812 AJ |
3846 | if (bo & 0x2) { |
3847 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3848 | } else { | |
3849 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3850 | } |
a7812ae4 | 3851 | tcg_temp_free(temp); |
a2ffb812 AJ |
3852 | } |
3853 | if ((bo & 0x10) == 0) { | |
3854 | /* Test CR */ | |
3855 | uint32_t bi = BI(ctx->opcode); | |
3856 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3857 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3858 | |
d9bce9d9 | 3859 | if (bo & 0x8) { |
a2ffb812 AJ |
3860 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3861 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3862 | } else { |
a2ffb812 AJ |
3863 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3864 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3865 | } |
a7812ae4 | 3866 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3867 | } |
697ab892 | 3868 | gen_update_cfar(ctx, ctx->nip); |
e98a6e40 | 3869 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3870 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3871 | if (likely(AA(ctx->opcode) == 0)) { | |
3872 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3873 | } else { | |
3874 | gen_goto_tb(ctx, 0, li); | |
3875 | } | |
c53be334 | 3876 | gen_set_label(l1); |
c1942362 | 3877 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3878 | } else { |
e0c8f9ce | 3879 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3880 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3881 | } else { |
a2ffb812 | 3882 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3883 | } |
a2ffb812 AJ |
3884 | tcg_gen_exit_tb(0); |
3885 | gen_set_label(l1); | |
e0c8f9ce | 3886 | gen_update_nip(ctx, ctx->nip); |
57fec1fe | 3887 | tcg_gen_exit_tb(0); |
08e46e54 | 3888 | } |
a9e8f4e7 | 3889 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
c80d1df5 AG |
3890 | tcg_temp_free(target); |
3891 | } | |
e98a6e40 FB |
3892 | } |
3893 | ||
99e300ef | 3894 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3895 | { |
e98a6e40 FB |
3896 | gen_bcond(ctx, BCOND_IM); |
3897 | } | |
3898 | ||
99e300ef | 3899 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3900 | { |
e98a6e40 FB |
3901 | gen_bcond(ctx, BCOND_CTR); |
3902 | } | |
3903 | ||
99e300ef | 3904 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3905 | { |
e98a6e40 FB |
3906 | gen_bcond(ctx, BCOND_LR); |
3907 | } | |
79aceca5 | 3908 | |
52a4984d TM |
3909 | static void gen_bctar(DisasContext *ctx) |
3910 | { | |
3911 | gen_bcond(ctx, BCOND_TAR); | |
3912 | } | |
3913 | ||
79aceca5 | 3914 | /*** Condition register logical ***/ |
e1571908 | 3915 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3916 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3917 | { \ |
fc0d441e JM |
3918 | uint8_t bitmask; \ |
3919 | int sh; \ | |
a7812ae4 | 3920 | TCGv_i32 t0, t1; \ |
fc0d441e | 3921 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3922 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3923 | if (sh > 0) \ |
fea0c503 | 3924 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3925 | else if (sh < 0) \ |
fea0c503 | 3926 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3927 | else \ |
fea0c503 | 3928 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3929 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3930 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3931 | if (sh > 0) \ | |
fea0c503 | 3932 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3933 | else if (sh < 0) \ |
fea0c503 | 3934 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3935 | else \ |
fea0c503 AJ |
3936 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3937 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3938 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3939 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3940 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3941 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3942 | tcg_temp_free_i32(t0); \ |
3943 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3944 | } |
3945 | ||
3946 | /* crand */ | |
e1571908 | 3947 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3948 | /* crandc */ |
e1571908 | 3949 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3950 | /* creqv */ |
e1571908 | 3951 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3952 | /* crnand */ |
e1571908 | 3953 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3954 | /* crnor */ |
e1571908 | 3955 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3956 | /* cror */ |
e1571908 | 3957 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3958 | /* crorc */ |
e1571908 | 3959 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3960 | /* crxor */ |
e1571908 | 3961 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3962 | |
54623277 | 3963 | /* mcrf */ |
99e300ef | 3964 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3965 | { |
47e4661c | 3966 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3967 | } |
3968 | ||
3969 | /*** System linkage ***/ | |
99e300ef | 3970 | |
54623277 | 3971 | /* rfi (mem_idx only) */ |
99e300ef | 3972 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3973 | { |
9a64fbe4 | 3974 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3975 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3976 | #else |
3977 | /* Restore CPU state */ | |
76db3ba4 | 3978 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3979 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3980 | return; |
9a64fbe4 | 3981 | } |
697ab892 | 3982 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 3983 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3984 | gen_sync_exception(ctx); |
9a64fbe4 | 3985 | #endif |
79aceca5 FB |
3986 | } |
3987 | ||
426613db | 3988 | #if defined(TARGET_PPC64) |
99e300ef | 3989 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3990 | { |
3991 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3992 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3993 | #else |
3994 | /* Restore CPU state */ | |
76db3ba4 | 3995 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3996 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3997 | return; |
3998 | } | |
697ab892 | 3999 | gen_update_cfar(ctx, ctx->nip); |
e5f17ac6 | 4000 | gen_helper_rfid(cpu_env); |
e06fcd75 | 4001 | gen_sync_exception(ctx); |
426613db JM |
4002 | #endif |
4003 | } | |
426613db | 4004 | |
99e300ef | 4005 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
4006 | { |
4007 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4008 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
4009 | #else |
4010 | /* Restore CPU state */ | |
76db3ba4 | 4011 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 4012 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
4013 | return; |
4014 | } | |
e5f17ac6 | 4015 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 4016 | gen_sync_exception(ctx); |
be147d08 JM |
4017 | #endif |
4018 | } | |
4019 | #endif | |
4020 | ||
79aceca5 | 4021 | /* sc */ |
417bf010 JM |
4022 | #if defined(CONFIG_USER_ONLY) |
4023 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
4024 | #else | |
4025 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
4026 | #endif | |
99e300ef | 4027 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 4028 | { |
e1833e1f JM |
4029 | uint32_t lev; |
4030 | ||
4031 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 4032 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
4033 | } |
4034 | ||
4035 | /*** Trap ***/ | |
99e300ef | 4036 | |
54623277 | 4037 | /* tw */ |
99e300ef | 4038 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 4039 | { |
cab3bee2 | 4040 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
4041 | /* Update the nip since this might generate a trap exception */ |
4042 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
4043 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4044 | t0); | |
cab3bee2 | 4045 | tcg_temp_free_i32(t0); |
79aceca5 FB |
4046 | } |
4047 | ||
4048 | /* twi */ | |
99e300ef | 4049 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 4050 | { |
cab3bee2 AJ |
4051 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
4052 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
4053 | /* Update the nip since this might generate a trap exception */ |
4054 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 4055 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4056 | tcg_temp_free(t0); |
4057 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
4058 | } |
4059 | ||
d9bce9d9 JM |
4060 | #if defined(TARGET_PPC64) |
4061 | /* td */ | |
99e300ef | 4062 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 4063 | { |
cab3bee2 | 4064 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
db9a231d AJ |
4065 | /* Update the nip since this might generate a trap exception */ |
4066 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 BS |
4067 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4068 | t0); | |
cab3bee2 | 4069 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
4070 | } |
4071 | ||
4072 | /* tdi */ | |
99e300ef | 4073 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 4074 | { |
cab3bee2 AJ |
4075 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
4076 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
db9a231d AJ |
4077 | /* Update the nip since this might generate a trap exception */ |
4078 | gen_update_nip(ctx, ctx->nip); | |
e5f17ac6 | 4079 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
4080 | tcg_temp_free(t0); |
4081 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
4082 | } |
4083 | #endif | |
4084 | ||
79aceca5 | 4085 | /*** Processor control ***/ |
99e300ef | 4086 | |
da91a00f RH |
4087 | static void gen_read_xer(TCGv dst) |
4088 | { | |
4089 | TCGv t0 = tcg_temp_new(); | |
4090 | TCGv t1 = tcg_temp_new(); | |
4091 | TCGv t2 = tcg_temp_new(); | |
4092 | tcg_gen_mov_tl(dst, cpu_xer); | |
4093 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
4094 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
4095 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
4096 | tcg_gen_or_tl(t0, t0, t1); | |
4097 | tcg_gen_or_tl(dst, dst, t2); | |
4098 | tcg_gen_or_tl(dst, dst, t0); | |
4099 | tcg_temp_free(t0); | |
4100 | tcg_temp_free(t1); | |
4101 | tcg_temp_free(t2); | |
4102 | } | |
4103 | ||
4104 | static void gen_write_xer(TCGv src) | |
4105 | { | |
4106 | tcg_gen_andi_tl(cpu_xer, src, | |
4107 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
4108 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
4109 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
4110 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
4111 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
4112 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
4113 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
4114 | } | |
4115 | ||
54623277 | 4116 | /* mcrxr */ |
99e300ef | 4117 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 4118 | { |
da91a00f RH |
4119 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4120 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
4121 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
4122 | ||
4123 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
4124 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
4125 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
4126 | tcg_gen_shri_i32(t0, t0, 2); | |
4127 | tcg_gen_shri_i32(t1, t1, 1); | |
4128 | tcg_gen_or_i32(dst, dst, t0); | |
4129 | tcg_gen_or_i32(dst, dst, t1); | |
4130 | tcg_temp_free_i32(t0); | |
4131 | tcg_temp_free_i32(t1); | |
4132 | ||
4133 | tcg_gen_movi_tl(cpu_so, 0); | |
4134 | tcg_gen_movi_tl(cpu_ov, 0); | |
4135 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
4136 | } |
4137 | ||
0cfe11ea | 4138 | /* mfcr mfocrf */ |
99e300ef | 4139 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 4140 | { |
76a66253 | 4141 | uint32_t crm, crn; |
3b46e624 | 4142 | |
76a66253 JM |
4143 | if (likely(ctx->opcode & 0x00100000)) { |
4144 | crm = CRM(ctx->opcode); | |
8dd640e4 | 4145 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 4146 | crn = ctz32 (crm); |
e1571908 | 4147 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
4148 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
4149 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 4150 | } |
d9bce9d9 | 4151 | } else { |
651721b2 AJ |
4152 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4153 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
4154 | tcg_gen_shli_i32(t0, t0, 4); | |
4155 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
4156 | tcg_gen_shli_i32(t0, t0, 4); | |
4157 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
4158 | tcg_gen_shli_i32(t0, t0, 4); | |
4159 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
4160 | tcg_gen_shli_i32(t0, t0, 4); | |
4161 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
4162 | tcg_gen_shli_i32(t0, t0, 4); | |
4163 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
4164 | tcg_gen_shli_i32(t0, t0, 4); | |
4165 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
4166 | tcg_gen_shli_i32(t0, t0, 4); | |
4167 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
4168 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4169 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 4170 | } |
79aceca5 FB |
4171 | } |
4172 | ||
4173 | /* mfmsr */ | |
99e300ef | 4174 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 4175 | { |
9a64fbe4 | 4176 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4177 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4178 | #else |
76db3ba4 | 4179 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4180 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4181 | return; |
9a64fbe4 | 4182 | } |
6527f6ea | 4183 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 4184 | #endif |
79aceca5 FB |
4185 | } |
4186 | ||
7b13448f | 4187 | static void spr_noaccess(void *opaque, int gprn, int sprn) |
3fc6c082 | 4188 | { |
7b13448f | 4189 | #if 0 |
3fc6c082 FB |
4190 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
4191 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 4192 | #endif |
3fc6c082 FB |
4193 | } |
4194 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 4195 | |
79aceca5 | 4196 | /* mfspr */ |
636aa200 | 4197 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 4198 | { |
45d827d2 | 4199 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
4200 | uint32_t sprn = SPR(ctx->opcode); |
4201 | ||
3fc6c082 | 4202 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4203 | if (ctx->mem_idx == 2) |
be147d08 | 4204 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 4205 | else if (ctx->mem_idx) |
3fc6c082 FB |
4206 | read_cb = ctx->spr_cb[sprn].oea_read; |
4207 | else | |
9a64fbe4 | 4208 | #endif |
3fc6c082 | 4209 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
4210 | if (likely(read_cb != NULL)) { |
4211 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4212 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4213 | } else { |
4214 | /* Privilege exception */ | |
9fceefa7 JM |
4215 | /* This is a hack to avoid warnings when running Linux: |
4216 | * this OS breaks the PowerPC virtualisation model, | |
4217 | * allowing userland application to read the PVR | |
4218 | */ | |
4219 | if (sprn != SPR_PVR) { | |
c05541ee AB |
4220 | qemu_log("Trying to read privileged spr %d (0x%03x) at " |
4221 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4222 | printf("Trying to read privileged spr %d (0x%03x) at " | |
4223 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
f24e5695 | 4224 | } |
e06fcd75 | 4225 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4226 | } |
3fc6c082 FB |
4227 | } else { |
4228 | /* Not defined */ | |
c05541ee AB |
4229 | qemu_log("Trying to read invalid spr %d (0x%03x) at " |
4230 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4231 | printf("Trying to read invalid spr %d (0x%03x) at " | |
4232 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4233 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4234 | } |
79aceca5 FB |
4235 | } |
4236 | ||
99e300ef | 4237 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4238 | { |
3fc6c082 | 4239 | gen_op_mfspr(ctx); |
76a66253 | 4240 | } |
3fc6c082 FB |
4241 | |
4242 | /* mftb */ | |
99e300ef | 4243 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4244 | { |
4245 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4246 | } |
4247 | ||
0cfe11ea | 4248 | /* mtcrf mtocrf*/ |
99e300ef | 4249 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4250 | { |
76a66253 | 4251 | uint32_t crm, crn; |
3b46e624 | 4252 | |
76a66253 | 4253 | crm = CRM(ctx->opcode); |
8dd640e4 | 4254 | if (likely((ctx->opcode & 0x00100000))) { |
4255 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4256 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 4257 | crn = ctz32 (crm); |
8dd640e4 | 4258 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4259 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4260 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4261 | tcg_temp_free_i32(temp); |
4262 | } | |
76a66253 | 4263 | } else { |
651721b2 AJ |
4264 | TCGv_i32 temp = tcg_temp_new_i32(); |
4265 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4266 | for (crn = 0 ; crn < 8 ; crn++) { | |
4267 | if (crm & (1 << crn)) { | |
4268 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4269 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4270 | } | |
4271 | } | |
a7812ae4 | 4272 | tcg_temp_free_i32(temp); |
76a66253 | 4273 | } |
79aceca5 FB |
4274 | } |
4275 | ||
4276 | /* mtmsr */ | |
426613db | 4277 | #if defined(TARGET_PPC64) |
99e300ef | 4278 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
4279 | { |
4280 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4281 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 4282 | #else |
76db3ba4 | 4283 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4284 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
4285 | return; |
4286 | } | |
be147d08 JM |
4287 | if (ctx->opcode & 0x00010000) { |
4288 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4289 | TCGv t0 = tcg_temp_new(); |
4290 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4291 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4292 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4293 | tcg_temp_free(t0); | |
be147d08 | 4294 | } else { |
056b05f8 JM |
4295 | /* XXX: we need to update nip before the store |
4296 | * if we enter power saving mode, we will exit the loop | |
4297 | * directly from ppc_store_msr | |
4298 | */ | |
be147d08 | 4299 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 4300 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
4301 | /* Must stop the translation as machine state (may have) changed */ |
4302 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 4303 | gen_stop_exception(ctx); |
be147d08 | 4304 | } |
426613db JM |
4305 | #endif |
4306 | } | |
4307 | #endif | |
4308 | ||
99e300ef | 4309 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4310 | { |
9a64fbe4 | 4311 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4312 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4313 | #else |
76db3ba4 | 4314 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4315 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4316 | return; |
9a64fbe4 | 4317 | } |
be147d08 JM |
4318 | if (ctx->opcode & 0x00010000) { |
4319 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4320 | TCGv t0 = tcg_temp_new(); |
4321 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4322 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4323 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4324 | tcg_temp_free(t0); | |
be147d08 | 4325 | } else { |
8018dc63 AG |
4326 | TCGv msr = tcg_temp_new(); |
4327 | ||
056b05f8 JM |
4328 | /* XXX: we need to update nip before the store |
4329 | * if we enter power saving mode, we will exit the loop | |
4330 | * directly from ppc_store_msr | |
4331 | */ | |
be147d08 | 4332 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 4333 | #if defined(TARGET_PPC64) |
8018dc63 AG |
4334 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4335 | #else | |
4336 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 4337 | #endif |
e5f17ac6 | 4338 | gen_helper_store_msr(cpu_env, msr); |
c80d1df5 | 4339 | tcg_temp_free(msr); |
be147d08 | 4340 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4341 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4342 | gen_stop_exception(ctx); |
be147d08 | 4343 | } |
9a64fbe4 | 4344 | #endif |
79aceca5 FB |
4345 | } |
4346 | ||
4347 | /* mtspr */ | |
99e300ef | 4348 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4349 | { |
45d827d2 | 4350 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
4351 | uint32_t sprn = SPR(ctx->opcode); |
4352 | ||
3fc6c082 | 4353 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4354 | if (ctx->mem_idx == 2) |
be147d08 | 4355 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 4356 | else if (ctx->mem_idx) |
3fc6c082 FB |
4357 | write_cb = ctx->spr_cb[sprn].oea_write; |
4358 | else | |
9a64fbe4 | 4359 | #endif |
3fc6c082 | 4360 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
4361 | if (likely(write_cb != NULL)) { |
4362 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4363 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4364 | } else { |
4365 | /* Privilege exception */ | |
c05541ee AB |
4366 | qemu_log("Trying to write privileged spr %d (0x%03x) at " |
4367 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4368 | printf("Trying to write privileged spr %d (0x%03x) at " | |
4369 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4370 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4371 | } |
3fc6c082 FB |
4372 | } else { |
4373 | /* Not defined */ | |
c05541ee AB |
4374 | qemu_log("Trying to write invalid spr %d (0x%03x) at " |
4375 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4376 | printf("Trying to write invalid spr %d (0x%03x) at " | |
4377 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
e06fcd75 | 4378 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4379 | } |
79aceca5 FB |
4380 | } |
4381 | ||
4382 | /*** Cache management ***/ | |
99e300ef | 4383 | |
54623277 | 4384 | /* dcbf */ |
99e300ef | 4385 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4386 | { |
dac454af | 4387 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4388 | TCGv t0; |
4389 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4390 | t0 = tcg_temp_new(); | |
4391 | gen_addr_reg_index(ctx, t0); | |
4392 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4393 | tcg_temp_free(t0); |
79aceca5 FB |
4394 | } |
4395 | ||
4396 | /* dcbi (Supervisor only) */ | |
99e300ef | 4397 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4398 | { |
a541f297 | 4399 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4400 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4401 | #else |
b61f2753 | 4402 | TCGv EA, val; |
76db3ba4 | 4403 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4404 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4405 | return; |
9a64fbe4 | 4406 | } |
a7812ae4 | 4407 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4408 | gen_set_access_type(ctx, ACCESS_CACHE); |
4409 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4410 | val = tcg_temp_new(); |
76a66253 | 4411 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4412 | gen_qemu_ld8u(ctx, val, EA); |
4413 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4414 | tcg_temp_free(val); |
4415 | tcg_temp_free(EA); | |
a541f297 | 4416 | #endif |
79aceca5 FB |
4417 | } |
4418 | ||
4419 | /* dcdst */ | |
99e300ef | 4420 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4421 | { |
76a66253 | 4422 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4423 | TCGv t0; |
4424 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4425 | t0 = tcg_temp_new(); | |
4426 | gen_addr_reg_index(ctx, t0); | |
4427 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4428 | tcg_temp_free(t0); |
79aceca5 FB |
4429 | } |
4430 | ||
4431 | /* dcbt */ | |
99e300ef | 4432 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4433 | { |
0db1b20e | 4434 | /* interpreted as no-op */ |
76a66253 JM |
4435 | /* XXX: specification say this is treated as a load by the MMU |
4436 | * but does not generate any exception | |
4437 | */ | |
79aceca5 FB |
4438 | } |
4439 | ||
4440 | /* dcbtst */ | |
99e300ef | 4441 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4442 | { |
0db1b20e | 4443 | /* interpreted as no-op */ |
76a66253 JM |
4444 | /* XXX: specification say this is treated as a load by the MMU |
4445 | * but does not generate any exception | |
4446 | */ | |
79aceca5 FB |
4447 | } |
4448 | ||
4d09d529 AG |
4449 | /* dcbtls */ |
4450 | static void gen_dcbtls(DisasContext *ctx) | |
4451 | { | |
4452 | /* Always fails locking the cache */ | |
4453 | TCGv t0 = tcg_temp_new(); | |
4454 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4455 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4456 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4457 | tcg_temp_free(t0); | |
4458 | } | |
4459 | ||
79aceca5 | 4460 | /* dcbz */ |
99e300ef | 4461 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4462 | { |
8e33944f AG |
4463 | TCGv tcgv_addr; |
4464 | TCGv_i32 tcgv_is_dcbzl; | |
4465 | int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; | |
d63001d1 | 4466 | |
76db3ba4 | 4467 | gen_set_access_type(ctx, ACCESS_CACHE); |
799a8c8d AJ |
4468 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4469 | gen_update_nip(ctx, ctx->nip - 4); | |
8e33944f AG |
4470 | tcgv_addr = tcg_temp_new(); |
4471 | tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); | |
4472 | ||
4473 | gen_addr_reg_index(ctx, tcgv_addr); | |
4474 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); | |
4475 | ||
4476 | tcg_temp_free(tcgv_addr); | |
4477 | tcg_temp_free_i32(tcgv_is_dcbzl); | |
79aceca5 FB |
4478 | } |
4479 | ||
ae1c1a3d | 4480 | /* dst / dstt */ |
99e300ef | 4481 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4482 | { |
4483 | if (rA(ctx->opcode) == 0) { | |
4484 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4485 | } else { | |
4486 | /* interpreted as no-op */ | |
4487 | } | |
4488 | } | |
4489 | ||
4490 | /* dstst /dststt */ | |
99e300ef | 4491 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4492 | { |
4493 | if (rA(ctx->opcode) == 0) { | |
4494 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4495 | } else { | |
4496 | /* interpreted as no-op */ | |
4497 | } | |
4498 | ||
4499 | } | |
4500 | ||
4501 | /* dss / dssall */ | |
99e300ef | 4502 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4503 | { |
4504 | /* interpreted as no-op */ | |
4505 | } | |
4506 | ||
79aceca5 | 4507 | /* icbi */ |
99e300ef | 4508 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4509 | { |
76db3ba4 AJ |
4510 | TCGv t0; |
4511 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4512 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4513 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4514 | t0 = tcg_temp_new(); |
4515 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4516 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4517 | tcg_temp_free(t0); |
79aceca5 FB |
4518 | } |
4519 | ||
4520 | /* Optional: */ | |
4521 | /* dcba */ | |
99e300ef | 4522 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4523 | { |
0db1b20e JM |
4524 | /* interpreted as no-op */ |
4525 | /* XXX: specification say this is treated as a store by the MMU | |
4526 | * but does not generate any exception | |
4527 | */ | |
79aceca5 FB |
4528 | } |
4529 | ||
4530 | /*** Segment register manipulation ***/ | |
4531 | /* Supervisor only: */ | |
99e300ef | 4532 | |
54623277 | 4533 | /* mfsr */ |
99e300ef | 4534 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4535 | { |
9a64fbe4 | 4536 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4537 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4538 | #else |
74d37793 | 4539 | TCGv t0; |
76db3ba4 | 4540 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4541 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4542 | return; |
9a64fbe4 | 4543 | } |
74d37793 | 4544 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4545 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4546 | tcg_temp_free(t0); |
9a64fbe4 | 4547 | #endif |
79aceca5 FB |
4548 | } |
4549 | ||
4550 | /* mfsrin */ | |
99e300ef | 4551 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4552 | { |
9a64fbe4 | 4553 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4554 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4555 | #else |
74d37793 | 4556 | TCGv t0; |
76db3ba4 | 4557 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4558 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4559 | return; |
9a64fbe4 | 4560 | } |
74d37793 AJ |
4561 | t0 = tcg_temp_new(); |
4562 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4563 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4564 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4565 | tcg_temp_free(t0); |
9a64fbe4 | 4566 | #endif |
79aceca5 FB |
4567 | } |
4568 | ||
4569 | /* mtsr */ | |
99e300ef | 4570 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4571 | { |
9a64fbe4 | 4572 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4573 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4574 | #else |
74d37793 | 4575 | TCGv t0; |
76db3ba4 | 4576 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4577 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4578 | return; |
9a64fbe4 | 4579 | } |
74d37793 | 4580 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4581 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4582 | tcg_temp_free(t0); |
9a64fbe4 | 4583 | #endif |
79aceca5 FB |
4584 | } |
4585 | ||
4586 | /* mtsrin */ | |
99e300ef | 4587 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4588 | { |
9a64fbe4 | 4589 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4590 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4591 | #else |
74d37793 | 4592 | TCGv t0; |
76db3ba4 | 4593 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4594 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4595 | return; |
9a64fbe4 | 4596 | } |
74d37793 AJ |
4597 | t0 = tcg_temp_new(); |
4598 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4599 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4600 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4601 | tcg_temp_free(t0); |
9a64fbe4 | 4602 | #endif |
79aceca5 FB |
4603 | } |
4604 | ||
12de9a39 JM |
4605 | #if defined(TARGET_PPC64) |
4606 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4607 | |
54623277 | 4608 | /* mfsr */ |
e8eaa2c0 | 4609 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4610 | { |
4611 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4612 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4613 | #else |
74d37793 | 4614 | TCGv t0; |
76db3ba4 | 4615 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4616 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4617 | return; |
4618 | } | |
74d37793 | 4619 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4620 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4621 | tcg_temp_free(t0); |
12de9a39 JM |
4622 | #endif |
4623 | } | |
4624 | ||
4625 | /* mfsrin */ | |
e8eaa2c0 | 4626 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4627 | { |
4628 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4629 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4630 | #else |
74d37793 | 4631 | TCGv t0; |
76db3ba4 | 4632 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4633 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4634 | return; |
4635 | } | |
74d37793 AJ |
4636 | t0 = tcg_temp_new(); |
4637 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4638 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4639 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4640 | tcg_temp_free(t0); |
12de9a39 JM |
4641 | #endif |
4642 | } | |
4643 | ||
4644 | /* mtsr */ | |
e8eaa2c0 | 4645 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4646 | { |
4647 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4648 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4649 | #else |
74d37793 | 4650 | TCGv t0; |
76db3ba4 | 4651 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4652 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4653 | return; |
4654 | } | |
74d37793 | 4655 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4656 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4657 | tcg_temp_free(t0); |
12de9a39 JM |
4658 | #endif |
4659 | } | |
4660 | ||
4661 | /* mtsrin */ | |
e8eaa2c0 | 4662 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4663 | { |
4664 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4665 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4666 | #else |
74d37793 | 4667 | TCGv t0; |
76db3ba4 | 4668 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4669 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4670 | return; |
4671 | } | |
74d37793 AJ |
4672 | t0 = tcg_temp_new(); |
4673 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4674 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4675 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4676 | tcg_temp_free(t0); |
12de9a39 JM |
4677 | #endif |
4678 | } | |
f6b868fc BS |
4679 | |
4680 | /* slbmte */ | |
e8eaa2c0 | 4681 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4682 | { |
4683 | #if defined(CONFIG_USER_ONLY) | |
4684 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4685 | #else | |
4686 | if (unlikely(!ctx->mem_idx)) { | |
4687 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4688 | return; | |
4689 | } | |
c6c7cf05 BS |
4690 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4691 | cpu_gpr[rS(ctx->opcode)]); | |
f6b868fc BS |
4692 | #endif |
4693 | } | |
4694 | ||
efdef95f DG |
4695 | static void gen_slbmfee(DisasContext *ctx) |
4696 | { | |
4697 | #if defined(CONFIG_USER_ONLY) | |
4698 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4699 | #else | |
4700 | if (unlikely(!ctx->mem_idx)) { | |
4701 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4702 | return; | |
4703 | } | |
c6c7cf05 | 4704 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4705 | cpu_gpr[rB(ctx->opcode)]); |
4706 | #endif | |
4707 | } | |
4708 | ||
4709 | static void gen_slbmfev(DisasContext *ctx) | |
4710 | { | |
4711 | #if defined(CONFIG_USER_ONLY) | |
4712 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4713 | #else | |
4714 | if (unlikely(!ctx->mem_idx)) { | |
4715 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4716 | return; | |
4717 | } | |
c6c7cf05 | 4718 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f DG |
4719 | cpu_gpr[rB(ctx->opcode)]); |
4720 | #endif | |
4721 | } | |
12de9a39 JM |
4722 | #endif /* defined(TARGET_PPC64) */ |
4723 | ||
79aceca5 | 4724 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4725 | /* Optional & mem_idx only: */ |
99e300ef | 4726 | |
54623277 | 4727 | /* tlbia */ |
99e300ef | 4728 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4729 | { |
9a64fbe4 | 4730 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4731 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4732 | #else |
76db3ba4 | 4733 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4734 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4735 | return; |
9a64fbe4 | 4736 | } |
c6c7cf05 | 4737 | gen_helper_tlbia(cpu_env); |
9a64fbe4 | 4738 | #endif |
79aceca5 FB |
4739 | } |
4740 | ||
bf14b1ce | 4741 | /* tlbiel */ |
99e300ef | 4742 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4743 | { |
4744 | #if defined(CONFIG_USER_ONLY) | |
4745 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4746 | #else | |
4747 | if (unlikely(!ctx->mem_idx)) { | |
4748 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4749 | return; | |
4750 | } | |
c6c7cf05 | 4751 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
bf14b1ce BS |
4752 | #endif |
4753 | } | |
4754 | ||
79aceca5 | 4755 | /* tlbie */ |
99e300ef | 4756 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4757 | { |
9a64fbe4 | 4758 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4759 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4760 | #else |
76db3ba4 | 4761 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4762 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4763 | return; |
9a64fbe4 | 4764 | } |
9ca3f7f3 | 4765 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4766 | TCGv t0 = tcg_temp_new(); |
4767 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4768 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4769 | tcg_temp_free(t0); |
9ca3f7f3 | 4770 | } else { |
c6c7cf05 | 4771 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4772 | } |
9a64fbe4 | 4773 | #endif |
79aceca5 FB |
4774 | } |
4775 | ||
4776 | /* tlbsync */ | |
99e300ef | 4777 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4778 | { |
9a64fbe4 | 4779 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4780 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4781 | #else |
76db3ba4 | 4782 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4783 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4784 | return; |
9a64fbe4 FB |
4785 | } |
4786 | /* This has no effect: it should ensure that all previous | |
4787 | * tlbie have completed | |
4788 | */ | |
e06fcd75 | 4789 | gen_stop_exception(ctx); |
9a64fbe4 | 4790 | #endif |
79aceca5 FB |
4791 | } |
4792 | ||
426613db JM |
4793 | #if defined(TARGET_PPC64) |
4794 | /* slbia */ | |
99e300ef | 4795 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4796 | { |
4797 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4798 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4799 | #else |
76db3ba4 | 4800 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4801 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4802 | return; |
4803 | } | |
c6c7cf05 | 4804 | gen_helper_slbia(cpu_env); |
426613db JM |
4805 | #endif |
4806 | } | |
4807 | ||
4808 | /* slbie */ | |
99e300ef | 4809 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4810 | { |
4811 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4812 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4813 | #else |
76db3ba4 | 4814 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4815 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4816 | return; |
4817 | } | |
c6c7cf05 | 4818 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4819 | #endif |
4820 | } | |
4821 | #endif | |
4822 | ||
79aceca5 FB |
4823 | /*** External control ***/ |
4824 | /* Optional: */ | |
99e300ef | 4825 | |
54623277 | 4826 | /* eciwx */ |
99e300ef | 4827 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4828 | { |
76db3ba4 | 4829 | TCGv t0; |
fa407c03 | 4830 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4831 | gen_set_access_type(ctx, ACCESS_EXT); |
4832 | t0 = tcg_temp_new(); | |
4833 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4834 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4835 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4836 | tcg_temp_free(t0); |
76a66253 JM |
4837 | } |
4838 | ||
4839 | /* ecowx */ | |
99e300ef | 4840 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4841 | { |
76db3ba4 | 4842 | TCGv t0; |
fa407c03 | 4843 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4844 | gen_set_access_type(ctx, ACCESS_EXT); |
4845 | t0 = tcg_temp_new(); | |
4846 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4847 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4848 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4849 | tcg_temp_free(t0); |
76a66253 JM |
4850 | } |
4851 | ||
4852 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4853 | |
54623277 | 4854 | /* abs - abs. */ |
99e300ef | 4855 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4856 | { |
22e0e173 AJ |
4857 | int l1 = gen_new_label(); |
4858 | int l2 = gen_new_label(); | |
4859 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4860 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4861 | tcg_gen_br(l2); | |
4862 | gen_set_label(l1); | |
4863 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4864 | gen_set_label(l2); | |
76a66253 | 4865 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4866 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4867 | } |
4868 | ||
4869 | /* abso - abso. */ | |
99e300ef | 4870 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4871 | { |
22e0e173 AJ |
4872 | int l1 = gen_new_label(); |
4873 | int l2 = gen_new_label(); | |
4874 | int l3 = gen_new_label(); | |
4875 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4876 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4877 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4878 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4879 | tcg_gen_movi_tl(cpu_ov, 1); |
4880 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4881 | tcg_gen_br(l2); |
4882 | gen_set_label(l1); | |
4883 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4884 | tcg_gen_br(l3); | |
4885 | gen_set_label(l2); | |
4886 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4887 | gen_set_label(l3); | |
76a66253 | 4888 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4889 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4890 | } |
4891 | ||
4892 | /* clcs */ | |
99e300ef | 4893 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4894 | { |
22e0e173 | 4895 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4896 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4897 | tcg_temp_free_i32(t0); |
c7697e1f | 4898 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4899 | } |
4900 | ||
4901 | /* div - div. */ | |
99e300ef | 4902 | static void gen_div(DisasContext *ctx) |
76a66253 | 4903 | { |
d15f74fb BS |
4904 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4905 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4906 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4907 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4908 | } |
4909 | ||
4910 | /* divo - divo. */ | |
99e300ef | 4911 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4912 | { |
d15f74fb BS |
4913 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4914 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4915 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4916 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4917 | } |
4918 | ||
4919 | /* divs - divs. */ | |
99e300ef | 4920 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4921 | { |
d15f74fb BS |
4922 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4923 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4924 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4925 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4926 | } |
4927 | ||
4928 | /* divso - divso. */ | |
99e300ef | 4929 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4930 | { |
d15f74fb BS |
4931 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4932 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4933 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4934 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4935 | } |
4936 | ||
4937 | /* doz - doz. */ | |
99e300ef | 4938 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4939 | { |
22e0e173 AJ |
4940 | int l1 = gen_new_label(); |
4941 | int l2 = gen_new_label(); | |
4942 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4943 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4944 | tcg_gen_br(l2); | |
4945 | gen_set_label(l1); | |
4946 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4947 | gen_set_label(l2); | |
76a66253 | 4948 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4949 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4950 | } |
4951 | ||
4952 | /* dozo - dozo. */ | |
99e300ef | 4953 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4954 | { |
22e0e173 AJ |
4955 | int l1 = gen_new_label(); |
4956 | int l2 = gen_new_label(); | |
4957 | TCGv t0 = tcg_temp_new(); | |
4958 | TCGv t1 = tcg_temp_new(); | |
4959 | TCGv t2 = tcg_temp_new(); | |
4960 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4961 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4962 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4963 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4964 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4965 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4966 | tcg_gen_andc_tl(t1, t1, t2); | |
4967 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4968 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4969 | tcg_gen_movi_tl(cpu_ov, 1); |
4970 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4971 | tcg_gen_br(l2); |
4972 | gen_set_label(l1); | |
4973 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4974 | gen_set_label(l2); | |
4975 | tcg_temp_free(t0); | |
4976 | tcg_temp_free(t1); | |
4977 | tcg_temp_free(t2); | |
76a66253 | 4978 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4979 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4980 | } |
4981 | ||
4982 | /* dozi */ | |
99e300ef | 4983 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4984 | { |
22e0e173 AJ |
4985 | target_long simm = SIMM(ctx->opcode); |
4986 | int l1 = gen_new_label(); | |
4987 | int l2 = gen_new_label(); | |
4988 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
4989 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4990 | tcg_gen_br(l2); | |
4991 | gen_set_label(l1); | |
4992 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4993 | gen_set_label(l2); | |
4994 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4995 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4996 | } |
4997 | ||
76a66253 | 4998 | /* lscbx - lscbx. */ |
99e300ef | 4999 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 5000 | { |
bdb4b689 AJ |
5001 | TCGv t0 = tcg_temp_new(); |
5002 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
5003 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
5004 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 5005 | |
76db3ba4 | 5006 | gen_addr_reg_index(ctx, t0); |
76a66253 | 5007 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 5008 | gen_update_nip(ctx, ctx->nip - 4); |
2f5a189c | 5009 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
5010 | tcg_temp_free_i32(t1); |
5011 | tcg_temp_free_i32(t2); | |
5012 | tcg_temp_free_i32(t3); | |
3d7b417e | 5013 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 5014 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 5015 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
5016 | gen_set_Rc0(ctx, t0); |
5017 | tcg_temp_free(t0); | |
76a66253 JM |
5018 | } |
5019 | ||
5020 | /* maskg - maskg. */ | |
99e300ef | 5021 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 5022 | { |
22e0e173 AJ |
5023 | int l1 = gen_new_label(); |
5024 | TCGv t0 = tcg_temp_new(); | |
5025 | TCGv t1 = tcg_temp_new(); | |
5026 | TCGv t2 = tcg_temp_new(); | |
5027 | TCGv t3 = tcg_temp_new(); | |
5028 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
5029 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5030 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
5031 | tcg_gen_addi_tl(t2, t0, 1); | |
5032 | tcg_gen_shr_tl(t2, t3, t2); | |
5033 | tcg_gen_shr_tl(t3, t3, t1); | |
5034 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
5035 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
5036 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5037 | gen_set_label(l1); | |
5038 | tcg_temp_free(t0); | |
5039 | tcg_temp_free(t1); | |
5040 | tcg_temp_free(t2); | |
5041 | tcg_temp_free(t3); | |
76a66253 | 5042 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5043 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5044 | } |
5045 | ||
5046 | /* maskir - maskir. */ | |
99e300ef | 5047 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 5048 | { |
22e0e173 AJ |
5049 | TCGv t0 = tcg_temp_new(); |
5050 | TCGv t1 = tcg_temp_new(); | |
5051 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5052 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
5053 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5054 | tcg_temp_free(t0); | |
5055 | tcg_temp_free(t1); | |
76a66253 | 5056 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5057 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5058 | } |
5059 | ||
5060 | /* mul - mul. */ | |
99e300ef | 5061 | static void gen_mul(DisasContext *ctx) |
76a66253 | 5062 | { |
22e0e173 AJ |
5063 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5064 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5065 | TCGv t2 = tcg_temp_new(); | |
5066 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
5067 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5068 | tcg_gen_mul_i64(t0, t0, t1); | |
5069 | tcg_gen_trunc_i64_tl(t2, t0); | |
5070 | gen_store_spr(SPR_MQ, t2); | |
5071 | tcg_gen_shri_i64(t1, t0, 32); | |
5072 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5073 | tcg_temp_free_i64(t0); | |
5074 | tcg_temp_free_i64(t1); | |
5075 | tcg_temp_free(t2); | |
76a66253 | 5076 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5077 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5078 | } |
5079 | ||
5080 | /* mulo - mulo. */ | |
99e300ef | 5081 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 5082 | { |
22e0e173 AJ |
5083 | int l1 = gen_new_label(); |
5084 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
5085 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
5086 | TCGv t2 = tcg_temp_new(); | |
5087 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5088 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
5089 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
5090 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
5091 | tcg_gen_mul_i64(t0, t0, t1); | |
5092 | tcg_gen_trunc_i64_tl(t2, t0); | |
5093 | gen_store_spr(SPR_MQ, t2); | |
5094 | tcg_gen_shri_i64(t1, t0, 32); | |
5095 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
5096 | tcg_gen_ext32s_i64(t1, t0); | |
5097 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
5098 | tcg_gen_movi_tl(cpu_ov, 1); |
5099 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
5100 | gen_set_label(l1); |
5101 | tcg_temp_free_i64(t0); | |
5102 | tcg_temp_free_i64(t1); | |
5103 | tcg_temp_free(t2); | |
76a66253 | 5104 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5105 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5106 | } |
5107 | ||
5108 | /* nabs - nabs. */ | |
99e300ef | 5109 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 5110 | { |
22e0e173 AJ |
5111 | int l1 = gen_new_label(); |
5112 | int l2 = gen_new_label(); | |
5113 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
5114 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5115 | tcg_gen_br(l2); | |
5116 | gen_set_label(l1); | |
5117 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5118 | gen_set_label(l2); | |
76a66253 | 5119 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5120 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5121 | } |
5122 | ||
5123 | /* nabso - nabso. */ | |
99e300ef | 5124 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 5125 | { |
22e0e173 AJ |
5126 | int l1 = gen_new_label(); |
5127 | int l2 = gen_new_label(); | |
5128 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
5129 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5130 | tcg_gen_br(l2); | |
5131 | gen_set_label(l1); | |
5132 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
5133 | gen_set_label(l2); | |
5134 | /* nabs never overflows */ | |
da91a00f | 5135 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 5136 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 5137 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
5138 | } |
5139 | ||
5140 | /* rlmi - rlmi. */ | |
99e300ef | 5141 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 5142 | { |
7487953d AJ |
5143 | uint32_t mb = MB(ctx->opcode); |
5144 | uint32_t me = ME(ctx->opcode); | |
5145 | TCGv t0 = tcg_temp_new(); | |
5146 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5147 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5148 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
5149 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
5150 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
5151 | tcg_temp_free(t0); | |
76a66253 | 5152 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5153 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5154 | } |
5155 | ||
5156 | /* rrib - rrib. */ | |
99e300ef | 5157 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 5158 | { |
7487953d AJ |
5159 | TCGv t0 = tcg_temp_new(); |
5160 | TCGv t1 = tcg_temp_new(); | |
5161 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5162 | tcg_gen_movi_tl(t1, 0x80000000); | |
5163 | tcg_gen_shr_tl(t1, t1, t0); | |
5164 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5165 | tcg_gen_and_tl(t0, t0, t1); | |
5166 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
5167 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5168 | tcg_temp_free(t0); | |
5169 | tcg_temp_free(t1); | |
76a66253 | 5170 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5171 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5172 | } |
5173 | ||
5174 | /* sle - sle. */ | |
99e300ef | 5175 | static void gen_sle(DisasContext *ctx) |
76a66253 | 5176 | { |
7487953d AJ |
5177 | TCGv t0 = tcg_temp_new(); |
5178 | TCGv t1 = tcg_temp_new(); | |
5179 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5180 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5181 | tcg_gen_subfi_tl(t1, 32, t1); | |
5182 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5183 | tcg_gen_or_tl(t1, t0, t1); | |
5184 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5185 | gen_store_spr(SPR_MQ, t1); | |
5186 | tcg_temp_free(t0); | |
5187 | tcg_temp_free(t1); | |
76a66253 | 5188 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5189 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5190 | } |
5191 | ||
5192 | /* sleq - sleq. */ | |
99e300ef | 5193 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 5194 | { |
7487953d AJ |
5195 | TCGv t0 = tcg_temp_new(); |
5196 | TCGv t1 = tcg_temp_new(); | |
5197 | TCGv t2 = tcg_temp_new(); | |
5198 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5199 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
5200 | tcg_gen_shl_tl(t2, t2, t0); | |
5201 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5202 | gen_load_spr(t1, SPR_MQ); | |
5203 | gen_store_spr(SPR_MQ, t0); | |
5204 | tcg_gen_and_tl(t0, t0, t2); | |
5205 | tcg_gen_andc_tl(t1, t1, t2); | |
5206 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5207 | tcg_temp_free(t0); | |
5208 | tcg_temp_free(t1); | |
5209 | tcg_temp_free(t2); | |
76a66253 | 5210 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5211 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5212 | } |
5213 | ||
5214 | /* sliq - sliq. */ | |
99e300ef | 5215 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 5216 | { |
7487953d AJ |
5217 | int sh = SH(ctx->opcode); |
5218 | TCGv t0 = tcg_temp_new(); | |
5219 | TCGv t1 = tcg_temp_new(); | |
5220 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5221 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5222 | tcg_gen_or_tl(t1, t0, t1); | |
5223 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5224 | gen_store_spr(SPR_MQ, t1); | |
5225 | tcg_temp_free(t0); | |
5226 | tcg_temp_free(t1); | |
76a66253 | 5227 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5228 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5229 | } |
5230 | ||
5231 | /* slliq - slliq. */ | |
99e300ef | 5232 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5233 | { |
7487953d AJ |
5234 | int sh = SH(ctx->opcode); |
5235 | TCGv t0 = tcg_temp_new(); | |
5236 | TCGv t1 = tcg_temp_new(); | |
5237 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5238 | gen_load_spr(t1, SPR_MQ); | |
5239 | gen_store_spr(SPR_MQ, t0); | |
5240 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5241 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5242 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5243 | tcg_temp_free(t0); | |
5244 | tcg_temp_free(t1); | |
76a66253 | 5245 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5246 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5247 | } |
5248 | ||
5249 | /* sllq - sllq. */ | |
99e300ef | 5250 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5251 | { |
7487953d AJ |
5252 | int l1 = gen_new_label(); |
5253 | int l2 = gen_new_label(); | |
5254 | TCGv t0 = tcg_temp_local_new(); | |
5255 | TCGv t1 = tcg_temp_local_new(); | |
5256 | TCGv t2 = tcg_temp_local_new(); | |
5257 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5258 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5259 | tcg_gen_shl_tl(t1, t1, t2); | |
5260 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5261 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5262 | gen_load_spr(t0, SPR_MQ); | |
5263 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5264 | tcg_gen_br(l2); | |
5265 | gen_set_label(l1); | |
5266 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5267 | gen_load_spr(t2, SPR_MQ); | |
5268 | tcg_gen_andc_tl(t1, t2, t1); | |
5269 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5270 | gen_set_label(l2); | |
5271 | tcg_temp_free(t0); | |
5272 | tcg_temp_free(t1); | |
5273 | tcg_temp_free(t2); | |
76a66253 | 5274 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5275 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5276 | } |
5277 | ||
5278 | /* slq - slq. */ | |
99e300ef | 5279 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5280 | { |
7487953d AJ |
5281 | int l1 = gen_new_label(); |
5282 | TCGv t0 = tcg_temp_new(); | |
5283 | TCGv t1 = tcg_temp_new(); | |
5284 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5285 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5286 | tcg_gen_subfi_tl(t1, 32, t1); | |
5287 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5288 | tcg_gen_or_tl(t1, t0, t1); | |
5289 | gen_store_spr(SPR_MQ, t1); | |
5290 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5291 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5292 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5293 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5294 | gen_set_label(l1); | |
5295 | tcg_temp_free(t0); | |
5296 | tcg_temp_free(t1); | |
76a66253 | 5297 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5298 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5299 | } |
5300 | ||
d9bce9d9 | 5301 | /* sraiq - sraiq. */ |
99e300ef | 5302 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5303 | { |
7487953d AJ |
5304 | int sh = SH(ctx->opcode); |
5305 | int l1 = gen_new_label(); | |
5306 | TCGv t0 = tcg_temp_new(); | |
5307 | TCGv t1 = tcg_temp_new(); | |
5308 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5309 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5310 | tcg_gen_or_tl(t0, t0, t1); | |
5311 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 5312 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5313 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5314 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 5315 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5316 | gen_set_label(l1); |
5317 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5318 | tcg_temp_free(t0); | |
5319 | tcg_temp_free(t1); | |
76a66253 | 5320 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5321 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5322 | } |
5323 | ||
5324 | /* sraq - sraq. */ | |
99e300ef | 5325 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5326 | { |
7487953d AJ |
5327 | int l1 = gen_new_label(); |
5328 | int l2 = gen_new_label(); | |
5329 | TCGv t0 = tcg_temp_new(); | |
5330 | TCGv t1 = tcg_temp_local_new(); | |
5331 | TCGv t2 = tcg_temp_local_new(); | |
5332 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5333 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5334 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5335 | tcg_gen_subfi_tl(t2, 32, t2); | |
5336 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5337 | tcg_gen_or_tl(t0, t0, t2); | |
5338 | gen_store_spr(SPR_MQ, t0); | |
5339 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5340 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5341 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5342 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5343 | gen_set_label(l1); | |
5344 | tcg_temp_free(t0); | |
5345 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 5346 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
5347 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5348 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5349 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5350 | gen_set_label(l2); |
5351 | tcg_temp_free(t1); | |
5352 | tcg_temp_free(t2); | |
76a66253 | 5353 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5354 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5355 | } |
5356 | ||
5357 | /* sre - sre. */ | |
99e300ef | 5358 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5359 | { |
7487953d AJ |
5360 | TCGv t0 = tcg_temp_new(); |
5361 | TCGv t1 = tcg_temp_new(); | |
5362 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5363 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5364 | tcg_gen_subfi_tl(t1, 32, t1); | |
5365 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5366 | tcg_gen_or_tl(t1, t0, t1); | |
5367 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5368 | gen_store_spr(SPR_MQ, t1); | |
5369 | tcg_temp_free(t0); | |
5370 | tcg_temp_free(t1); | |
76a66253 | 5371 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5372 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5373 | } |
5374 | ||
5375 | /* srea - srea. */ | |
99e300ef | 5376 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5377 | { |
7487953d AJ |
5378 | TCGv t0 = tcg_temp_new(); |
5379 | TCGv t1 = tcg_temp_new(); | |
5380 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5381 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5382 | gen_store_spr(SPR_MQ, t0); | |
5383 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5384 | tcg_temp_free(t0); | |
5385 | tcg_temp_free(t1); | |
76a66253 | 5386 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5387 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5388 | } |
5389 | ||
5390 | /* sreq */ | |
99e300ef | 5391 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5392 | { |
7487953d AJ |
5393 | TCGv t0 = tcg_temp_new(); |
5394 | TCGv t1 = tcg_temp_new(); | |
5395 | TCGv t2 = tcg_temp_new(); | |
5396 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5397 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5398 | tcg_gen_shr_tl(t1, t1, t0); | |
5399 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5400 | gen_load_spr(t2, SPR_MQ); | |
5401 | gen_store_spr(SPR_MQ, t0); | |
5402 | tcg_gen_and_tl(t0, t0, t1); | |
5403 | tcg_gen_andc_tl(t2, t2, t1); | |
5404 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5405 | tcg_temp_free(t0); | |
5406 | tcg_temp_free(t1); | |
5407 | tcg_temp_free(t2); | |
76a66253 | 5408 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5409 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5410 | } |
5411 | ||
5412 | /* sriq */ | |
99e300ef | 5413 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5414 | { |
7487953d AJ |
5415 | int sh = SH(ctx->opcode); |
5416 | TCGv t0 = tcg_temp_new(); | |
5417 | TCGv t1 = tcg_temp_new(); | |
5418 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5419 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5420 | tcg_gen_or_tl(t1, t0, t1); | |
5421 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5422 | gen_store_spr(SPR_MQ, t1); | |
5423 | tcg_temp_free(t0); | |
5424 | tcg_temp_free(t1); | |
76a66253 | 5425 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5426 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5427 | } |
5428 | ||
5429 | /* srliq */ | |
99e300ef | 5430 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5431 | { |
7487953d AJ |
5432 | int sh = SH(ctx->opcode); |
5433 | TCGv t0 = tcg_temp_new(); | |
5434 | TCGv t1 = tcg_temp_new(); | |
5435 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5436 | gen_load_spr(t1, SPR_MQ); | |
5437 | gen_store_spr(SPR_MQ, t0); | |
5438 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5439 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5440 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5441 | tcg_temp_free(t0); | |
5442 | tcg_temp_free(t1); | |
76a66253 | 5443 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5444 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5445 | } |
5446 | ||
5447 | /* srlq */ | |
99e300ef | 5448 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5449 | { |
7487953d AJ |
5450 | int l1 = gen_new_label(); |
5451 | int l2 = gen_new_label(); | |
5452 | TCGv t0 = tcg_temp_local_new(); | |
5453 | TCGv t1 = tcg_temp_local_new(); | |
5454 | TCGv t2 = tcg_temp_local_new(); | |
5455 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5456 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5457 | tcg_gen_shr_tl(t2, t1, t2); | |
5458 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5459 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5460 | gen_load_spr(t0, SPR_MQ); | |
5461 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5462 | tcg_gen_br(l2); | |
5463 | gen_set_label(l1); | |
5464 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5465 | tcg_gen_and_tl(t0, t0, t2); | |
5466 | gen_load_spr(t1, SPR_MQ); | |
5467 | tcg_gen_andc_tl(t1, t1, t2); | |
5468 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5469 | gen_set_label(l2); | |
5470 | tcg_temp_free(t0); | |
5471 | tcg_temp_free(t1); | |
5472 | tcg_temp_free(t2); | |
76a66253 | 5473 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5474 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5475 | } |
5476 | ||
5477 | /* srq */ | |
99e300ef | 5478 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5479 | { |
7487953d AJ |
5480 | int l1 = gen_new_label(); |
5481 | TCGv t0 = tcg_temp_new(); | |
5482 | TCGv t1 = tcg_temp_new(); | |
5483 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5484 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5485 | tcg_gen_subfi_tl(t1, 32, t1); | |
5486 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5487 | tcg_gen_or_tl(t1, t0, t1); | |
5488 | gen_store_spr(SPR_MQ, t1); | |
5489 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5490 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5491 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5492 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5493 | gen_set_label(l1); | |
5494 | tcg_temp_free(t0); | |
5495 | tcg_temp_free(t1); | |
76a66253 | 5496 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5497 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5498 | } |
5499 | ||
5500 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5501 | |
54623277 | 5502 | /* dsa */ |
99e300ef | 5503 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5504 | { |
5505 | /* XXX: TODO */ | |
e06fcd75 | 5506 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5507 | } |
5508 | ||
5509 | /* esa */ | |
99e300ef | 5510 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5511 | { |
5512 | /* XXX: TODO */ | |
e06fcd75 | 5513 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5514 | } |
5515 | ||
5516 | /* mfrom */ | |
99e300ef | 5517 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5518 | { |
5519 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5520 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5521 | #else |
76db3ba4 | 5522 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5523 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5524 | return; |
5525 | } | |
cf02a65c | 5526 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5527 | #endif |
5528 | } | |
5529 | ||
5530 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5531 | |
54623277 | 5532 | /* tlbld */ |
e8eaa2c0 | 5533 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5534 | { |
5535 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5536 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5537 | #else |
76db3ba4 | 5538 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5539 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5540 | return; |
5541 | } | |
c6c7cf05 | 5542 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5543 | #endif |
5544 | } | |
5545 | ||
5546 | /* tlbli */ | |
e8eaa2c0 | 5547 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5548 | { |
5549 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5550 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5551 | #else |
76db3ba4 | 5552 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5553 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5554 | return; |
5555 | } | |
c6c7cf05 | 5556 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5557 | #endif |
5558 | } | |
5559 | ||
7dbe11ac | 5560 | /* 74xx TLB management */ |
e8eaa2c0 | 5561 | |
54623277 | 5562 | /* tlbld */ |
e8eaa2c0 | 5563 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5564 | { |
5565 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5566 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5567 | #else |
76db3ba4 | 5568 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5569 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5570 | return; |
5571 | } | |
c6c7cf05 | 5572 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5573 | #endif |
5574 | } | |
5575 | ||
5576 | /* tlbli */ | |
e8eaa2c0 | 5577 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5578 | { |
5579 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5580 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5581 | #else |
76db3ba4 | 5582 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5583 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5584 | return; |
5585 | } | |
c6c7cf05 | 5586 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5587 | #endif |
5588 | } | |
5589 | ||
76a66253 | 5590 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5591 | |
54623277 | 5592 | /* clf */ |
99e300ef | 5593 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5594 | { |
5595 | /* Cache line flush: implemented as no-op */ | |
5596 | } | |
5597 | ||
5598 | /* cli */ | |
99e300ef | 5599 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5600 | { |
7f75ffd3 | 5601 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5602 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5603 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5604 | #else |
76db3ba4 | 5605 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5606 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5607 | return; |
5608 | } | |
5609 | #endif | |
5610 | } | |
5611 | ||
5612 | /* dclst */ | |
99e300ef | 5613 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5614 | { |
5615 | /* Data cache line store: treated as no-op */ | |
5616 | } | |
5617 | ||
99e300ef | 5618 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5619 | { |
5620 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5621 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5622 | #else |
74d37793 AJ |
5623 | int ra = rA(ctx->opcode); |
5624 | int rd = rD(ctx->opcode); | |
5625 | TCGv t0; | |
76db3ba4 | 5626 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5627 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5628 | return; |
5629 | } | |
74d37793 | 5630 | t0 = tcg_temp_new(); |
76db3ba4 | 5631 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5632 | tcg_gen_shri_tl(t0, t0, 28); |
5633 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5634 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5635 | tcg_temp_free(t0); |
76a66253 | 5636 | if (ra != 0 && ra != rd) |
74d37793 | 5637 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5638 | #endif |
5639 | } | |
5640 | ||
99e300ef | 5641 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5642 | { |
5643 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5644 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5645 | #else |
22e0e173 | 5646 | TCGv t0; |
76db3ba4 | 5647 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5648 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5649 | return; |
5650 | } | |
22e0e173 | 5651 | t0 = tcg_temp_new(); |
76db3ba4 | 5652 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5653 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5654 | tcg_temp_free(t0); |
76a66253 JM |
5655 | #endif |
5656 | } | |
5657 | ||
99e300ef | 5658 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5659 | { |
5660 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5661 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5662 | #else |
76db3ba4 | 5663 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5664 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5665 | return; |
5666 | } | |
e5f17ac6 | 5667 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5668 | gen_sync_exception(ctx); |
76a66253 JM |
5669 | #endif |
5670 | } | |
5671 | ||
5672 | /* svc is not implemented for now */ | |
5673 | ||
5674 | /* POWER2 specific instructions */ | |
5675 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5676 | |
5677 | /* lfq */ | |
99e300ef | 5678 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5679 | { |
01a4afeb | 5680 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5681 | TCGv t0; |
5682 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5683 | t0 = tcg_temp_new(); | |
5684 | gen_addr_imm_index(ctx, t0, 0); | |
5685 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5686 | gen_addr_add(ctx, t0, t0, 8); | |
5687 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5688 | tcg_temp_free(t0); |
76a66253 JM |
5689 | } |
5690 | ||
5691 | /* lfqu */ | |
99e300ef | 5692 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5693 | { |
5694 | int ra = rA(ctx->opcode); | |
01a4afeb | 5695 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5696 | TCGv t0, t1; |
5697 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5698 | t0 = tcg_temp_new(); | |
5699 | t1 = tcg_temp_new(); | |
5700 | gen_addr_imm_index(ctx, t0, 0); | |
5701 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5702 | gen_addr_add(ctx, t1, t0, 8); | |
5703 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5704 | if (ra != 0) |
01a4afeb AJ |
5705 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5706 | tcg_temp_free(t0); | |
5707 | tcg_temp_free(t1); | |
76a66253 JM |
5708 | } |
5709 | ||
5710 | /* lfqux */ | |
99e300ef | 5711 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5712 | { |
5713 | int ra = rA(ctx->opcode); | |
01a4afeb | 5714 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5715 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5716 | TCGv t0, t1; | |
5717 | t0 = tcg_temp_new(); | |
5718 | gen_addr_reg_index(ctx, t0); | |
5719 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5720 | t1 = tcg_temp_new(); | |
5721 | gen_addr_add(ctx, t1, t0, 8); | |
5722 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5723 | tcg_temp_free(t1); | |
76a66253 | 5724 | if (ra != 0) |
01a4afeb AJ |
5725 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5726 | tcg_temp_free(t0); | |
76a66253 JM |
5727 | } |
5728 | ||
5729 | /* lfqx */ | |
99e300ef | 5730 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5731 | { |
01a4afeb | 5732 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5733 | TCGv t0; |
5734 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5735 | t0 = tcg_temp_new(); | |
5736 | gen_addr_reg_index(ctx, t0); | |
5737 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5738 | gen_addr_add(ctx, t0, t0, 8); | |
5739 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5740 | tcg_temp_free(t0); |
76a66253 JM |
5741 | } |
5742 | ||
5743 | /* stfq */ | |
99e300ef | 5744 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5745 | { |
01a4afeb | 5746 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5747 | TCGv t0; |
5748 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5749 | t0 = tcg_temp_new(); | |
5750 | gen_addr_imm_index(ctx, t0, 0); | |
5751 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5752 | gen_addr_add(ctx, t0, t0, 8); | |
5753 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5754 | tcg_temp_free(t0); |
76a66253 JM |
5755 | } |
5756 | ||
5757 | /* stfqu */ | |
99e300ef | 5758 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5759 | { |
5760 | int ra = rA(ctx->opcode); | |
01a4afeb | 5761 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5762 | TCGv t0, t1; |
5763 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5764 | t0 = tcg_temp_new(); | |
5765 | gen_addr_imm_index(ctx, t0, 0); | |
5766 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5767 | t1 = tcg_temp_new(); | |
5768 | gen_addr_add(ctx, t1, t0, 8); | |
5769 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5770 | tcg_temp_free(t1); | |
76a66253 | 5771 | if (ra != 0) |
01a4afeb AJ |
5772 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5773 | tcg_temp_free(t0); | |
76a66253 JM |
5774 | } |
5775 | ||
5776 | /* stfqux */ | |
99e300ef | 5777 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5778 | { |
5779 | int ra = rA(ctx->opcode); | |
01a4afeb | 5780 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5781 | TCGv t0, t1; |
5782 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5783 | t0 = tcg_temp_new(); | |
5784 | gen_addr_reg_index(ctx, t0); | |
5785 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5786 | t1 = tcg_temp_new(); | |
5787 | gen_addr_add(ctx, t1, t0, 8); | |
5788 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5789 | tcg_temp_free(t1); | |
76a66253 | 5790 | if (ra != 0) |
01a4afeb AJ |
5791 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5792 | tcg_temp_free(t0); | |
76a66253 JM |
5793 | } |
5794 | ||
5795 | /* stfqx */ | |
99e300ef | 5796 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5797 | { |
01a4afeb | 5798 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5799 | TCGv t0; |
5800 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5801 | t0 = tcg_temp_new(); | |
5802 | gen_addr_reg_index(ctx, t0); | |
5803 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5804 | gen_addr_add(ctx, t0, t0, 8); | |
5805 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5806 | tcg_temp_free(t0); |
76a66253 JM |
5807 | } |
5808 | ||
5809 | /* BookE specific instructions */ | |
99e300ef | 5810 | |
54623277 | 5811 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5812 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5813 | { |
5814 | /* XXX: TODO */ | |
e06fcd75 | 5815 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5816 | } |
5817 | ||
2662a059 | 5818 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5819 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5820 | { |
5821 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5822 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5823 | #else |
74d37793 | 5824 | TCGv t0; |
76db3ba4 | 5825 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5826 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5827 | return; |
5828 | } | |
ec72e276 | 5829 | t0 = tcg_temp_new(); |
76db3ba4 | 5830 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5831 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5832 | tcg_temp_free(t0); |
76a66253 JM |
5833 | #endif |
5834 | } | |
5835 | ||
5836 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5837 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5838 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5839 | { |
182608d4 AJ |
5840 | TCGv t0, t1; |
5841 | ||
a7812ae4 PB |
5842 | t0 = tcg_temp_local_new(); |
5843 | t1 = tcg_temp_local_new(); | |
182608d4 | 5844 | |
76a66253 JM |
5845 | switch (opc3 & 0x0D) { |
5846 | case 0x05: | |
5847 | /* macchw - macchw. - macchwo - macchwo. */ | |
5848 | /* macchws - macchws. - macchwso - macchwso. */ | |
5849 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5850 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5851 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5852 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5853 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5854 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5855 | break; |
5856 | case 0x04: | |
5857 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5858 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5859 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5860 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5861 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5862 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5863 | break; |
5864 | case 0x01: | |
5865 | /* machhw - machhw. - machhwo - machhwo. */ | |
5866 | /* machhws - machhws. - machhwso - machhwso. */ | |
5867 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5868 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5869 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5870 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5871 | tcg_gen_ext16s_tl(t0, t0); | |
5872 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5873 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5874 | break; |
5875 | case 0x00: | |
5876 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5877 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5878 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5879 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5880 | tcg_gen_ext16u_tl(t0, t0); | |
5881 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5882 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5883 | break; |
5884 | case 0x0D: | |
5885 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5886 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5887 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5888 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5889 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5890 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5891 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5892 | break; |
5893 | case 0x0C: | |
5894 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5895 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5896 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5897 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5898 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5899 | break; |
5900 | } | |
76a66253 | 5901 | if (opc2 & 0x04) { |
182608d4 AJ |
5902 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5903 | tcg_gen_mul_tl(t1, t0, t1); | |
5904 | if (opc2 & 0x02) { | |
5905 | /* nmultiply-and-accumulate (0x0E) */ | |
5906 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5907 | } else { | |
5908 | /* multiply-and-accumulate (0x0C) */ | |
5909 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5910 | } | |
5911 | ||
5912 | if (opc3 & 0x12) { | |
5913 | /* Check overflow and/or saturate */ | |
5914 | int l1 = gen_new_label(); | |
5915 | ||
5916 | if (opc3 & 0x10) { | |
5917 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5918 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5919 | } |
5920 | if (opc3 & 0x01) { | |
5921 | /* Signed */ | |
5922 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5923 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5924 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5925 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5926 | if (opc3 & 0x02) { |
182608d4 AJ |
5927 | /* Saturate */ |
5928 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5929 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5930 | } | |
5931 | } else { | |
5932 | /* Unsigned */ | |
5933 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5934 | if (opc3 & 0x02) { |
182608d4 AJ |
5935 | /* Saturate */ |
5936 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5937 | } | |
5938 | } | |
5939 | if (opc3 & 0x10) { | |
5940 | /* Check overflow */ | |
da91a00f RH |
5941 | tcg_gen_movi_tl(cpu_ov, 1); |
5942 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5943 | } |
5944 | gen_set_label(l1); | |
5945 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5946 | } | |
5947 | } else { | |
5948 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5949 | } |
182608d4 AJ |
5950 | tcg_temp_free(t0); |
5951 | tcg_temp_free(t1); | |
76a66253 JM |
5952 | if (unlikely(Rc) != 0) { |
5953 | /* Update Rc0 */ | |
182608d4 | 5954 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5955 | } |
5956 | } | |
5957 | ||
a750fc0b | 5958 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5959 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5960 | { \ |
5961 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5962 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5963 | } | |
5964 | ||
5965 | /* macchw - macchw. */ | |
a750fc0b | 5966 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5967 | /* macchwo - macchwo. */ |
a750fc0b | 5968 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5969 | /* macchws - macchws. */ |
a750fc0b | 5970 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5971 | /* macchwso - macchwso. */ |
a750fc0b | 5972 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5973 | /* macchwsu - macchwsu. */ |
a750fc0b | 5974 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5975 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5976 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5977 | /* macchwu - macchwu. */ |
a750fc0b | 5978 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5979 | /* macchwuo - macchwuo. */ |
a750fc0b | 5980 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5981 | /* machhw - machhw. */ |
a750fc0b | 5982 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5983 | /* machhwo - machhwo. */ |
a750fc0b | 5984 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5985 | /* machhws - machhws. */ |
a750fc0b | 5986 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5987 | /* machhwso - machhwso. */ |
a750fc0b | 5988 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5989 | /* machhwsu - machhwsu. */ |
a750fc0b | 5990 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5991 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5992 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5993 | /* machhwu - machhwu. */ |
a750fc0b | 5994 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5995 | /* machhwuo - machhwuo. */ |
a750fc0b | 5996 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5997 | /* maclhw - maclhw. */ |
a750fc0b | 5998 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5999 | /* maclhwo - maclhwo. */ |
a750fc0b | 6000 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 6001 | /* maclhws - maclhws. */ |
a750fc0b | 6002 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 6003 | /* maclhwso - maclhwso. */ |
a750fc0b | 6004 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 6005 | /* maclhwu - maclhwu. */ |
a750fc0b | 6006 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 6007 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 6008 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 6009 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 6010 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 6011 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 6012 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 6013 | /* nmacchw - nmacchw. */ |
a750fc0b | 6014 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 6015 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 6016 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 6017 | /* nmacchws - nmacchws. */ |
a750fc0b | 6018 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 6019 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 6020 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 6021 | /* nmachhw - nmachhw. */ |
a750fc0b | 6022 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 6023 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 6024 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 6025 | /* nmachhws - nmachhws. */ |
a750fc0b | 6026 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 6027 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 6028 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 6029 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 6030 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 6031 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 6032 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 6033 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 6034 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 6035 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 6036 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
6037 | |
6038 | /* mulchw - mulchw. */ | |
a750fc0b | 6039 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 6040 | /* mulchwu - mulchwu. */ |
a750fc0b | 6041 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 6042 | /* mulhhw - mulhhw. */ |
a750fc0b | 6043 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 6044 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 6045 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 6046 | /* mullhw - mullhw. */ |
a750fc0b | 6047 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 6048 | /* mullhwu - mullhwu. */ |
a750fc0b | 6049 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
6050 | |
6051 | /* mfdcr */ | |
99e300ef | 6052 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
6053 | { |
6054 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6055 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 6056 | #else |
06dca6a7 | 6057 | TCGv dcrn; |
76db3ba4 | 6058 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6059 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
6060 | return; |
6061 | } | |
06dca6a7 AJ |
6062 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6063 | gen_update_nip(ctx, ctx->nip - 4); | |
6064 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 6065 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 6066 | tcg_temp_free(dcrn); |
76a66253 JM |
6067 | #endif |
6068 | } | |
6069 | ||
6070 | /* mtdcr */ | |
99e300ef | 6071 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
6072 | { |
6073 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6074 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 6075 | #else |
06dca6a7 | 6076 | TCGv dcrn; |
76db3ba4 | 6077 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6078 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
6079 | return; |
6080 | } | |
06dca6a7 AJ |
6081 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6082 | gen_update_nip(ctx, ctx->nip - 4); | |
6083 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
d0f1562d | 6084 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 6085 | tcg_temp_free(dcrn); |
a42bd6cc JM |
6086 | #endif |
6087 | } | |
6088 | ||
6089 | /* mfdcrx */ | |
2662a059 | 6090 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6091 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
6092 | { |
6093 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6094 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 6095 | #else |
76db3ba4 | 6096 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6097 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
6098 | return; |
6099 | } | |
06dca6a7 AJ |
6100 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6101 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
6102 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6103 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 6104 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
6105 | #endif |
6106 | } | |
6107 | ||
6108 | /* mtdcrx */ | |
2662a059 | 6109 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6110 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
6111 | { |
6112 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6113 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 6114 | #else |
76db3ba4 | 6115 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6116 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
6117 | return; |
6118 | } | |
06dca6a7 AJ |
6119 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6120 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
6121 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6122 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 6123 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
6124 | #endif |
6125 | } | |
6126 | ||
a750fc0b | 6127 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 6128 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 6129 | { |
06dca6a7 AJ |
6130 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6131 | gen_update_nip(ctx, ctx->nip - 4); | |
d0f1562d BS |
6132 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6133 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
6134 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6135 | } | |
6136 | ||
6137 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 6138 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 6139 | { |
06dca6a7 AJ |
6140 | /* NIP cannot be restored if the memory exception comes from an helper */ |
6141 | gen_update_nip(ctx, ctx->nip - 4); | |
975e5463 | 6142 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 6143 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
6144 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6145 | } | |
6146 | ||
76a66253 | 6147 | /* dccci */ |
99e300ef | 6148 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
6149 | { |
6150 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6151 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6152 | #else |
76db3ba4 | 6153 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6154 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6155 | return; |
6156 | } | |
6157 | /* interpreted as no-op */ | |
6158 | #endif | |
6159 | } | |
6160 | ||
6161 | /* dcread */ | |
99e300ef | 6162 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
6163 | { |
6164 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6165 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6166 | #else |
b61f2753 | 6167 | TCGv EA, val; |
76db3ba4 | 6168 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6169 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6170 | return; |
6171 | } | |
76db3ba4 | 6172 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 6173 | EA = tcg_temp_new(); |
76db3ba4 | 6174 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 6175 | val = tcg_temp_new(); |
76db3ba4 | 6176 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
6177 | tcg_temp_free(val); |
6178 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
6179 | tcg_temp_free(EA); | |
76a66253 JM |
6180 | #endif |
6181 | } | |
6182 | ||
6183 | /* icbt */ | |
e8eaa2c0 | 6184 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
6185 | { |
6186 | /* interpreted as no-op */ | |
6187 | /* XXX: specification say this is treated as a load by the MMU | |
6188 | * but does not generate any exception | |
6189 | */ | |
6190 | } | |
6191 | ||
6192 | /* iccci */ | |
99e300ef | 6193 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
6194 | { |
6195 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6196 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6197 | #else |
76db3ba4 | 6198 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6199 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6200 | return; |
6201 | } | |
6202 | /* interpreted as no-op */ | |
6203 | #endif | |
6204 | } | |
6205 | ||
6206 | /* icread */ | |
99e300ef | 6207 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
6208 | { |
6209 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6210 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6211 | #else |
76db3ba4 | 6212 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6213 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6214 | return; |
6215 | } | |
6216 | /* interpreted as no-op */ | |
6217 | #endif | |
6218 | } | |
6219 | ||
76db3ba4 | 6220 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 6221 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
6222 | { |
6223 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6224 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6225 | #else |
76db3ba4 | 6226 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6227 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6228 | return; |
6229 | } | |
6230 | /* Restore CPU state */ | |
e5f17ac6 | 6231 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 6232 | gen_sync_exception(ctx); |
a42bd6cc JM |
6233 | #endif |
6234 | } | |
6235 | ||
99e300ef | 6236 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
6237 | { |
6238 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6239 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6240 | #else |
76db3ba4 | 6241 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6242 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6243 | return; |
6244 | } | |
6245 | /* Restore CPU state */ | |
e5f17ac6 | 6246 | gen_helper_rfci(cpu_env); |
e06fcd75 | 6247 | gen_sync_exception(ctx); |
a42bd6cc JM |
6248 | #endif |
6249 | } | |
6250 | ||
6251 | /* BookE specific */ | |
99e300ef | 6252 | |
54623277 | 6253 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6254 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
6255 | { |
6256 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6257 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6258 | #else |
76db3ba4 | 6259 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6260 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6261 | return; |
6262 | } | |
6263 | /* Restore CPU state */ | |
e5f17ac6 | 6264 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 6265 | gen_sync_exception(ctx); |
76a66253 JM |
6266 | #endif |
6267 | } | |
6268 | ||
2662a059 | 6269 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6270 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
6271 | { |
6272 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6273 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6274 | #else |
76db3ba4 | 6275 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6276 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6277 | return; |
6278 | } | |
6279 | /* Restore CPU state */ | |
e5f17ac6 | 6280 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 6281 | gen_sync_exception(ctx); |
a42bd6cc JM |
6282 | #endif |
6283 | } | |
5eb7995e | 6284 | |
d9bce9d9 | 6285 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 6286 | |
54623277 | 6287 | /* tlbre */ |
e8eaa2c0 | 6288 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
6289 | { |
6290 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6291 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6292 | #else |
76db3ba4 | 6293 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6294 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6295 | return; |
6296 | } | |
6297 | switch (rB(ctx->opcode)) { | |
6298 | case 0: | |
c6c7cf05 BS |
6299 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6300 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6301 | break; |
6302 | case 1: | |
c6c7cf05 BS |
6303 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6304 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
6305 | break; |
6306 | default: | |
e06fcd75 | 6307 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6308 | break; |
9a64fbe4 | 6309 | } |
76a66253 JM |
6310 | #endif |
6311 | } | |
6312 | ||
d9bce9d9 | 6313 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 6314 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
6315 | { |
6316 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6317 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6318 | #else |
74d37793 | 6319 | TCGv t0; |
76db3ba4 | 6320 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6321 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6322 | return; |
6323 | } | |
74d37793 | 6324 | t0 = tcg_temp_new(); |
76db3ba4 | 6325 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6326 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6327 | tcg_temp_free(t0); |
6328 | if (Rc(ctx->opcode)) { | |
6329 | int l1 = gen_new_label(); | |
da91a00f | 6330 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6331 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6332 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6333 | gen_set_label(l1); | |
6334 | } | |
76a66253 | 6335 | #endif |
79aceca5 FB |
6336 | } |
6337 | ||
76a66253 | 6338 | /* tlbwe */ |
e8eaa2c0 | 6339 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6340 | { |
76a66253 | 6341 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 6342 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6343 | #else |
76db3ba4 | 6344 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6345 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6346 | return; |
6347 | } | |
6348 | switch (rB(ctx->opcode)) { | |
6349 | case 0: | |
c6c7cf05 BS |
6350 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6351 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6352 | break; |
6353 | case 1: | |
c6c7cf05 BS |
6354 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6355 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
6356 | break; |
6357 | default: | |
e06fcd75 | 6358 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6359 | break; |
9a64fbe4 | 6360 | } |
76a66253 JM |
6361 | #endif |
6362 | } | |
6363 | ||
a4bb6c3e | 6364 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6365 | |
54623277 | 6366 | /* tlbre */ |
e8eaa2c0 | 6367 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6368 | { |
6369 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6370 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6371 | #else |
76db3ba4 | 6372 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6373 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6374 | return; |
6375 | } | |
6376 | switch (rB(ctx->opcode)) { | |
6377 | case 0: | |
5eb7995e | 6378 | case 1: |
5eb7995e | 6379 | case 2: |
74d37793 AJ |
6380 | { |
6381 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6382 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6383 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
6384 | tcg_temp_free_i32(t0); |
6385 | } | |
5eb7995e JM |
6386 | break; |
6387 | default: | |
e06fcd75 | 6388 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6389 | break; |
6390 | } | |
6391 | #endif | |
6392 | } | |
6393 | ||
6394 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6395 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6396 | { |
6397 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6398 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6399 | #else |
74d37793 | 6400 | TCGv t0; |
76db3ba4 | 6401 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6402 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6403 | return; |
6404 | } | |
74d37793 | 6405 | t0 = tcg_temp_new(); |
76db3ba4 | 6406 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 6407 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
6408 | tcg_temp_free(t0); |
6409 | if (Rc(ctx->opcode)) { | |
6410 | int l1 = gen_new_label(); | |
da91a00f | 6411 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
6412 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6413 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6414 | gen_set_label(l1); | |
6415 | } | |
5eb7995e JM |
6416 | #endif |
6417 | } | |
6418 | ||
6419 | /* tlbwe */ | |
e8eaa2c0 | 6420 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6421 | { |
6422 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6423 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6424 | #else |
76db3ba4 | 6425 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6426 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6427 | return; |
6428 | } | |
6429 | switch (rB(ctx->opcode)) { | |
6430 | case 0: | |
5eb7995e | 6431 | case 1: |
5eb7995e | 6432 | case 2: |
74d37793 AJ |
6433 | { |
6434 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
6435 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6436 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
6437 | tcg_temp_free_i32(t0); |
6438 | } | |
5eb7995e JM |
6439 | break; |
6440 | default: | |
e06fcd75 | 6441 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6442 | break; |
6443 | } | |
6444 | #endif | |
6445 | } | |
6446 | ||
01662f3e AG |
6447 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6448 | ||
6449 | /* tlbre */ | |
6450 | static void gen_tlbre_booke206(DisasContext *ctx) | |
6451 | { | |
6452 | #if defined(CONFIG_USER_ONLY) | |
6453 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6454 | #else | |
6455 | if (unlikely(!ctx->mem_idx)) { | |
6456 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6457 | return; | |
6458 | } | |
6459 | ||
c6c7cf05 | 6460 | gen_helper_booke206_tlbre(cpu_env); |
01662f3e AG |
6461 | #endif |
6462 | } | |
6463 | ||
6464 | /* tlbsx - tlbsx. */ | |
6465 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
6466 | { | |
6467 | #if defined(CONFIG_USER_ONLY) | |
6468 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6469 | #else | |
6470 | TCGv t0; | |
6471 | if (unlikely(!ctx->mem_idx)) { | |
6472 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6473 | return; | |
6474 | } | |
6475 | ||
6476 | if (rA(ctx->opcode)) { | |
6477 | t0 = tcg_temp_new(); | |
6478 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
6479 | } else { | |
6480 | t0 = tcg_const_tl(0); | |
6481 | } | |
6482 | ||
6483 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 6484 | gen_helper_booke206_tlbsx(cpu_env, t0); |
c80d1df5 | 6485 | tcg_temp_free(t0); |
01662f3e AG |
6486 | #endif |
6487 | } | |
6488 | ||
6489 | /* tlbwe */ | |
6490 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
6491 | { | |
6492 | #if defined(CONFIG_USER_ONLY) | |
6493 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6494 | #else | |
6495 | if (unlikely(!ctx->mem_idx)) { | |
6496 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6497 | return; | |
6498 | } | |
3f162d11 | 6499 | gen_update_nip(ctx, ctx->nip - 4); |
c6c7cf05 | 6500 | gen_helper_booke206_tlbwe(cpu_env); |
01662f3e AG |
6501 | #endif |
6502 | } | |
6503 | ||
6504 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
6505 | { | |
6506 | #if defined(CONFIG_USER_ONLY) | |
6507 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6508 | #else | |
6509 | TCGv t0; | |
6510 | if (unlikely(!ctx->mem_idx)) { | |
6511 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6512 | return; | |
6513 | } | |
6514 | ||
6515 | t0 = tcg_temp_new(); | |
6516 | gen_addr_reg_index(ctx, t0); | |
6517 | ||
c6c7cf05 | 6518 | gen_helper_booke206_tlbivax(cpu_env, t0); |
c80d1df5 | 6519 | tcg_temp_free(t0); |
01662f3e AG |
6520 | #endif |
6521 | } | |
6522 | ||
6d3db821 AG |
6523 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6524 | { | |
6525 | #if defined(CONFIG_USER_ONLY) | |
6526 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6527 | #else | |
6528 | TCGv t0; | |
6529 | if (unlikely(!ctx->mem_idx)) { | |
6530 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6531 | return; | |
6532 | } | |
6533 | ||
6534 | t0 = tcg_temp_new(); | |
6535 | gen_addr_reg_index(ctx, t0); | |
6536 | ||
6537 | switch((ctx->opcode >> 21) & 0x3) { | |
6538 | case 0: | |
c6c7cf05 | 6539 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
6540 | break; |
6541 | case 1: | |
c6c7cf05 | 6542 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
6543 | break; |
6544 | case 3: | |
c6c7cf05 | 6545 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
6546 | break; |
6547 | default: | |
6548 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
6549 | break; | |
6550 | } | |
6551 | ||
6552 | tcg_temp_free(t0); | |
6553 | #endif | |
6554 | } | |
6555 | ||
01662f3e | 6556 | |
76a66253 | 6557 | /* wrtee */ |
99e300ef | 6558 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6559 | { |
6560 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6561 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6562 | #else |
6527f6ea | 6563 | TCGv t0; |
76db3ba4 | 6564 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6565 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6566 | return; |
6567 | } | |
6527f6ea AJ |
6568 | t0 = tcg_temp_new(); |
6569 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6570 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6571 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6572 | tcg_temp_free(t0); | |
dee96f6c JM |
6573 | /* Stop translation to have a chance to raise an exception |
6574 | * if we just set msr_ee to 1 | |
6575 | */ | |
e06fcd75 | 6576 | gen_stop_exception(ctx); |
76a66253 JM |
6577 | #endif |
6578 | } | |
6579 | ||
6580 | /* wrteei */ | |
99e300ef | 6581 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6582 | { |
6583 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6584 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6585 | #else |
76db3ba4 | 6586 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6587 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6588 | return; |
6589 | } | |
fbe73008 | 6590 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
6591 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6592 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6593 | gen_stop_exception(ctx); |
6527f6ea | 6594 | } else { |
1b6e5f99 | 6595 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6596 | } |
76a66253 JM |
6597 | #endif |
6598 | } | |
6599 | ||
08e46e54 | 6600 | /* PowerPC 440 specific instructions */ |
99e300ef | 6601 | |
54623277 | 6602 | /* dlmzb */ |
99e300ef | 6603 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6604 | { |
ef0d51af | 6605 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6606 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6607 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6608 | tcg_temp_free_i32(t0); |
76a66253 JM |
6609 | } |
6610 | ||
6611 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6612 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6613 | { |
6614 | /* interpreted as no-op */ | |
6615 | } | |
6616 | ||
6617 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6618 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6619 | { |
6620 | /* interpreted as no-op */ | |
6621 | } | |
6622 | ||
6623 | /* icbt */ | |
e8eaa2c0 | 6624 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6625 | { |
6626 | /* interpreted as no-op */ | |
6627 | /* XXX: specification say this is treated as a load by the MMU | |
6628 | * but does not generate any exception | |
6629 | */ | |
79aceca5 FB |
6630 | } |
6631 | ||
9e0b5cb1 AG |
6632 | /* Embedded.Processor Control */ |
6633 | ||
6634 | static void gen_msgclr(DisasContext *ctx) | |
6635 | { | |
6636 | #if defined(CONFIG_USER_ONLY) | |
6637 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6638 | #else | |
6639 | if (unlikely(ctx->mem_idx == 0)) { | |
6640 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6641 | return; | |
6642 | } | |
6643 | ||
e5f17ac6 | 6644 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9e0b5cb1 AG |
6645 | #endif |
6646 | } | |
6647 | ||
d5d11a39 AG |
6648 | static void gen_msgsnd(DisasContext *ctx) |
6649 | { | |
6650 | #if defined(CONFIG_USER_ONLY) | |
6651 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6652 | #else | |
6653 | if (unlikely(ctx->mem_idx == 0)) { | |
6654 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
6655 | return; | |
6656 | } | |
6657 | ||
6658 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); | |
6659 | #endif | |
6660 | } | |
6661 | ||
a9d9eb8f JM |
6662 | /*** Altivec vector extension ***/ |
6663 | /* Altivec registers moves */ | |
a9d9eb8f | 6664 | |
636aa200 | 6665 | static inline TCGv_ptr gen_avr_ptr(int reg) |
564e571a | 6666 | { |
e4704b3b | 6667 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6668 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6669 | return r; | |
6670 | } | |
6671 | ||
a9d9eb8f | 6672 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef | 6673 | static void glue(gen_, name)(DisasContext *ctx) \ |
a9d9eb8f | 6674 | { \ |
fe1e5c53 | 6675 | TCGv EA; \ |
a9d9eb8f | 6676 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6677 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6678 | return; \ |
6679 | } \ | |
76db3ba4 | 6680 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6681 | EA = tcg_temp_new(); \ |
76db3ba4 | 6682 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6683 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
e22c357b DK |
6684 | /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \ |
6685 | 64-bit byteswap already. */ \ | |
76db3ba4 AJ |
6686 | if (ctx->le_mode) { \ |
6687 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6688 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6689 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6690 | } else { \ |
76db3ba4 | 6691 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6692 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6693 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6694 | } \ |
6695 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6696 | } |
6697 | ||
6698 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef | 6699 | static void gen_st##name(DisasContext *ctx) \ |
a9d9eb8f | 6700 | { \ |
fe1e5c53 | 6701 | TCGv EA; \ |
a9d9eb8f | 6702 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6703 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6704 | return; \ |
6705 | } \ | |
76db3ba4 | 6706 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6707 | EA = tcg_temp_new(); \ |
76db3ba4 | 6708 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6709 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
e22c357b DK |
6710 | /* We only need to swap high and low halves. gen_qemu_st64 does necessary \ |
6711 | 64-bit byteswap already. */ \ | |
76db3ba4 AJ |
6712 | if (ctx->le_mode) { \ |
6713 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6714 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6715 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6716 | } else { \ |
76db3ba4 | 6717 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6718 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6719 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6720 | } \ |
6721 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6722 | } |
6723 | ||
cbfb6ae9 | 6724 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef | 6725 | static void gen_lve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6726 | { \ |
6727 | TCGv EA; \ | |
6728 | TCGv_ptr rs; \ | |
6729 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6730 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6731 | return; \ | |
6732 | } \ | |
6733 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6734 | EA = tcg_temp_new(); \ | |
6735 | gen_addr_reg_index(ctx, EA); \ | |
6736 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6737 | gen_helper_lve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6738 | tcg_temp_free(EA); \ |
6739 | tcg_temp_free_ptr(rs); \ | |
6740 | } | |
6741 | ||
6742 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef | 6743 | static void gen_stve##name(DisasContext *ctx) \ |
cbfb6ae9 AJ |
6744 | { \ |
6745 | TCGv EA; \ | |
6746 | TCGv_ptr rs; \ | |
6747 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6748 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6749 | return; \ | |
6750 | } \ | |
6751 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6752 | EA = tcg_temp_new(); \ | |
6753 | gen_addr_reg_index(ctx, EA); \ | |
6754 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
2f5a189c | 6755 | gen_helper_stve##name(cpu_env, rs, EA); \ |
cbfb6ae9 AJ |
6756 | tcg_temp_free(EA); \ |
6757 | tcg_temp_free_ptr(rs); \ | |
6758 | } | |
6759 | ||
fe1e5c53 | 6760 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6761 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6762 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6763 | |
cbfb6ae9 AJ |
6764 | GEN_VR_LVE(bx, 0x07, 0x00); |
6765 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6766 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6767 | ||
fe1e5c53 | 6768 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6769 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6770 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6771 | |
cbfb6ae9 AJ |
6772 | GEN_VR_STVE(bx, 0x07, 0x04); |
6773 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6774 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6775 | ||
99e300ef | 6776 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6777 | { |
6778 | TCGv_ptr rd; | |
6779 | TCGv EA; | |
6780 | if (unlikely(!ctx->altivec_enabled)) { | |
6781 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6782 | return; | |
6783 | } | |
6784 | EA = tcg_temp_new(); | |
6785 | gen_addr_reg_index(ctx, EA); | |
6786 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6787 | gen_helper_lvsl(rd, EA); | |
6788 | tcg_temp_free(EA); | |
6789 | tcg_temp_free_ptr(rd); | |
6790 | } | |
6791 | ||
99e300ef | 6792 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6793 | { |
6794 | TCGv_ptr rd; | |
6795 | TCGv EA; | |
6796 | if (unlikely(!ctx->altivec_enabled)) { | |
6797 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6798 | return; | |
6799 | } | |
6800 | EA = tcg_temp_new(); | |
6801 | gen_addr_reg_index(ctx, EA); | |
6802 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6803 | gen_helper_lvsr(rd, EA); | |
6804 | tcg_temp_free(EA); | |
6805 | tcg_temp_free_ptr(rd); | |
6806 | } | |
6807 | ||
99e300ef | 6808 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6809 | { |
6810 | TCGv_i32 t; | |
6811 | if (unlikely(!ctx->altivec_enabled)) { | |
6812 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6813 | return; | |
6814 | } | |
6815 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6816 | t = tcg_temp_new_i32(); | |
1328c2bf | 6817 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr)); |
785f451b | 6818 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); |
fce5ecb7 | 6819 | tcg_temp_free_i32(t); |
785f451b AJ |
6820 | } |
6821 | ||
99e300ef | 6822 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6823 | { |
6e87b7c7 | 6824 | TCGv_ptr p; |
785f451b AJ |
6825 | if (unlikely(!ctx->altivec_enabled)) { |
6826 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6827 | return; | |
6828 | } | |
6e87b7c7 | 6829 | p = gen_avr_ptr(rD(ctx->opcode)); |
d15f74fb | 6830 | gen_helper_mtvscr(cpu_env, p); |
6e87b7c7 | 6831 | tcg_temp_free_ptr(p); |
785f451b AJ |
6832 | } |
6833 | ||
7a9b96cf AJ |
6834 | /* Logical operations */ |
6835 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef | 6836 | static void glue(gen_, name)(DisasContext *ctx) \ |
7a9b96cf AJ |
6837 | { \ |
6838 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6839 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6840 | return; \ | |
6841 | } \ | |
6842 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6843 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6844 | } | |
6845 | ||
6846 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6847 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6848 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6849 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6850 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
111c5f54 TM |
6851 | GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26); |
6852 | GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22); | |
6853 | GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21); | |
7a9b96cf | 6854 | |
8e27dd6f | 6855 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef | 6856 | static void glue(gen_, name)(DisasContext *ctx) \ |
8e27dd6f AJ |
6857 | { \ |
6858 | TCGv_ptr ra, rb, rd; \ | |
6859 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6860 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6861 | return; \ | |
6862 | } \ | |
6863 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6864 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6865 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6866 | gen_helper_##name (rd, ra, rb); \ | |
6867 | tcg_temp_free_ptr(ra); \ | |
6868 | tcg_temp_free_ptr(rb); \ | |
6869 | tcg_temp_free_ptr(rd); \ | |
6870 | } | |
6871 | ||
d15f74fb BS |
6872 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
6873 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6874 | { \ | |
6875 | TCGv_ptr ra, rb, rd; \ | |
6876 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6877 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6878 | return; \ | |
6879 | } \ | |
6880 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6881 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6882 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
54cddd21 | 6883 | gen_helper_##name(cpu_env, rd, ra, rb); \ |
d15f74fb BS |
6884 | tcg_temp_free_ptr(ra); \ |
6885 | tcg_temp_free_ptr(rb); \ | |
6886 | tcg_temp_free_ptr(rd); \ | |
9b47bb49 TM |
6887 | } |
6888 | ||
6889 | #define GEN_VXFORM3(name, opc2, opc3) \ | |
6890 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6891 | { \ | |
6892 | TCGv_ptr ra, rb, rc, rd; \ | |
6893 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6894 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6895 | return; \ | |
6896 | } \ | |
6897 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6898 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6899 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6900 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6901 | gen_helper_##name(rd, ra, rb, rc); \ | |
6902 | tcg_temp_free_ptr(ra); \ | |
6903 | tcg_temp_free_ptr(rb); \ | |
6904 | tcg_temp_free_ptr(rc); \ | |
6905 | tcg_temp_free_ptr(rd); \ | |
d15f74fb BS |
6906 | } |
6907 | ||
5dffff5a TM |
6908 | /* |
6909 | * Support for Altivec instruction pairs that use bit 31 (Rc) as | |
6910 | * an opcode bit. In general, these pairs come from different | |
6911 | * versions of the ISA, so we must also support a pair of flags for | |
6912 | * each instruction. | |
6913 | */ | |
6914 | #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
6915 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
6916 | { \ | |
6917 | if ((Rc(ctx->opcode) == 0) && \ | |
6918 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
6919 | gen_##name0(ctx); \ | |
6920 | } else if ((Rc(ctx->opcode) == 1) && \ | |
6921 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
6922 | gen_##name1(ctx); \ | |
6923 | } else { \ | |
6924 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
6925 | } \ | |
6926 | } | |
6927 | ||
7872c51c AJ |
6928 | GEN_VXFORM(vaddubm, 0, 0); |
6929 | GEN_VXFORM(vadduhm, 0, 1); | |
6930 | GEN_VXFORM(vadduwm, 0, 2); | |
56eabc75 | 6931 | GEN_VXFORM(vaddudm, 0, 3); |
7872c51c AJ |
6932 | GEN_VXFORM(vsububm, 0, 16); |
6933 | GEN_VXFORM(vsubuhm, 0, 17); | |
6934 | GEN_VXFORM(vsubuwm, 0, 18); | |
56eabc75 | 6935 | GEN_VXFORM(vsubudm, 0, 19); |
e4039339 AJ |
6936 | GEN_VXFORM(vmaxub, 1, 0); |
6937 | GEN_VXFORM(vmaxuh, 1, 1); | |
6938 | GEN_VXFORM(vmaxuw, 1, 2); | |
8203e31b | 6939 | GEN_VXFORM(vmaxud, 1, 3); |
e4039339 AJ |
6940 | GEN_VXFORM(vmaxsb, 1, 4); |
6941 | GEN_VXFORM(vmaxsh, 1, 5); | |
6942 | GEN_VXFORM(vmaxsw, 1, 6); | |
8203e31b | 6943 | GEN_VXFORM(vmaxsd, 1, 7); |
e4039339 AJ |
6944 | GEN_VXFORM(vminub, 1, 8); |
6945 | GEN_VXFORM(vminuh, 1, 9); | |
6946 | GEN_VXFORM(vminuw, 1, 10); | |
8203e31b | 6947 | GEN_VXFORM(vminud, 1, 11); |
e4039339 AJ |
6948 | GEN_VXFORM(vminsb, 1, 12); |
6949 | GEN_VXFORM(vminsh, 1, 13); | |
6950 | GEN_VXFORM(vminsw, 1, 14); | |
8203e31b | 6951 | GEN_VXFORM(vminsd, 1, 15); |
fab3cbe9 AJ |
6952 | GEN_VXFORM(vavgub, 1, 16); |
6953 | GEN_VXFORM(vavguh, 1, 17); | |
6954 | GEN_VXFORM(vavguw, 1, 18); | |
6955 | GEN_VXFORM(vavgsb, 1, 20); | |
6956 | GEN_VXFORM(vavgsh, 1, 21); | |
6957 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6958 | GEN_VXFORM(vmrghb, 6, 0); |
6959 | GEN_VXFORM(vmrghh, 6, 1); | |
6960 | GEN_VXFORM(vmrghw, 6, 2); | |
6961 | GEN_VXFORM(vmrglb, 6, 4); | |
6962 | GEN_VXFORM(vmrglh, 6, 5); | |
6963 | GEN_VXFORM(vmrglw, 6, 6); | |
e0ffe77f TM |
6964 | |
6965 | static void gen_vmrgew(DisasContext *ctx) | |
6966 | { | |
6967 | TCGv_i64 tmp; | |
6968 | int VT, VA, VB; | |
6969 | if (unlikely(!ctx->altivec_enabled)) { | |
6970 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6971 | return; | |
6972 | } | |
6973 | VT = rD(ctx->opcode); | |
6974 | VA = rA(ctx->opcode); | |
6975 | VB = rB(ctx->opcode); | |
6976 | tmp = tcg_temp_new_i64(); | |
6977 | tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32); | |
6978 | tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32); | |
6979 | tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32); | |
6980 | tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32); | |
6981 | tcg_temp_free_i64(tmp); | |
6982 | } | |
6983 | ||
6984 | static void gen_vmrgow(DisasContext *ctx) | |
6985 | { | |
6986 | int VT, VA, VB; | |
6987 | if (unlikely(!ctx->altivec_enabled)) { | |
6988 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6989 | return; | |
6990 | } | |
6991 | VT = rD(ctx->opcode); | |
6992 | VA = rA(ctx->opcode); | |
6993 | VB = rB(ctx->opcode); | |
6994 | ||
6995 | tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32); | |
6996 | tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32); | |
6997 | } | |
6998 | ||
2c277908 AJ |
6999 | GEN_VXFORM(vmuloub, 4, 0); |
7000 | GEN_VXFORM(vmulouh, 4, 1); | |
63be0936 | 7001 | GEN_VXFORM(vmulouw, 4, 2); |
953f0f58 TM |
7002 | GEN_VXFORM(vmuluwm, 4, 2); |
7003 | GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE, | |
7004 | vmuluwm, PPC_NONE, PPC2_ALTIVEC_207) | |
2c277908 AJ |
7005 | GEN_VXFORM(vmulosb, 4, 4); |
7006 | GEN_VXFORM(vmulosh, 4, 5); | |
63be0936 | 7007 | GEN_VXFORM(vmulosw, 4, 6); |
2c277908 AJ |
7008 | GEN_VXFORM(vmuleub, 4, 8); |
7009 | GEN_VXFORM(vmuleuh, 4, 9); | |
63be0936 | 7010 | GEN_VXFORM(vmuleuw, 4, 10); |
2c277908 AJ |
7011 | GEN_VXFORM(vmulesb, 4, 12); |
7012 | GEN_VXFORM(vmulesh, 4, 13); | |
63be0936 | 7013 | GEN_VXFORM(vmulesw, 4, 14); |
d79f0809 AJ |
7014 | GEN_VXFORM(vslb, 2, 4); |
7015 | GEN_VXFORM(vslh, 2, 5); | |
7016 | GEN_VXFORM(vslw, 2, 6); | |
2fdf78e6 | 7017 | GEN_VXFORM(vsld, 2, 23); |
07ef34c3 AJ |
7018 | GEN_VXFORM(vsrb, 2, 8); |
7019 | GEN_VXFORM(vsrh, 2, 9); | |
7020 | GEN_VXFORM(vsrw, 2, 10); | |
2fdf78e6 | 7021 | GEN_VXFORM(vsrd, 2, 27); |
07ef34c3 AJ |
7022 | GEN_VXFORM(vsrab, 2, 12); |
7023 | GEN_VXFORM(vsrah, 2, 13); | |
7024 | GEN_VXFORM(vsraw, 2, 14); | |
2fdf78e6 | 7025 | GEN_VXFORM(vsrad, 2, 15); |
7b239bec AJ |
7026 | GEN_VXFORM(vslo, 6, 16); |
7027 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
7028 | GEN_VXFORM(vaddcuw, 0, 6); |
7029 | GEN_VXFORM(vsubcuw, 0, 22); | |
d15f74fb BS |
7030 | GEN_VXFORM_ENV(vaddubs, 0, 8); |
7031 | GEN_VXFORM_ENV(vadduhs, 0, 9); | |
7032 | GEN_VXFORM_ENV(vadduws, 0, 10); | |
7033 | GEN_VXFORM_ENV(vaddsbs, 0, 12); | |
7034 | GEN_VXFORM_ENV(vaddshs, 0, 13); | |
7035 | GEN_VXFORM_ENV(vaddsws, 0, 14); | |
7036 | GEN_VXFORM_ENV(vsububs, 0, 24); | |
7037 | GEN_VXFORM_ENV(vsubuhs, 0, 25); | |
7038 | GEN_VXFORM_ENV(vsubuws, 0, 26); | |
7039 | GEN_VXFORM_ENV(vsubsbs, 0, 28); | |
7040 | GEN_VXFORM_ENV(vsubshs, 0, 29); | |
7041 | GEN_VXFORM_ENV(vsubsws, 0, 30); | |
b41da4eb TM |
7042 | GEN_VXFORM(vadduqm, 0, 4); |
7043 | GEN_VXFORM(vaddcuq, 0, 5); | |
7044 | GEN_VXFORM3(vaddeuqm, 30, 0); | |
7045 | GEN_VXFORM3(vaddecuq, 30, 0); | |
7046 | GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7047 | vaddecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
7048 | GEN_VXFORM(vsubuqm, 0, 20); | |
7049 | GEN_VXFORM(vsubcuq, 0, 21); | |
7050 | GEN_VXFORM3(vsubeuqm, 31, 0); | |
7051 | GEN_VXFORM3(vsubecuq, 31, 0); | |
7052 | GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7053 | vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
5e1d0985 AJ |
7054 | GEN_VXFORM(vrlb, 2, 0); |
7055 | GEN_VXFORM(vrlh, 2, 1); | |
7056 | GEN_VXFORM(vrlw, 2, 2); | |
2fdf78e6 | 7057 | GEN_VXFORM(vrld, 2, 3); |
d9430add AJ |
7058 | GEN_VXFORM(vsl, 2, 7); |
7059 | GEN_VXFORM(vsr, 2, 11); | |
d15f74fb BS |
7060 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
7061 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
024215b2 | 7062 | GEN_VXFORM_ENV(vpkudum, 7, 17); |
d15f74fb BS |
7063 | GEN_VXFORM_ENV(vpkuhus, 7, 2); |
7064 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
024215b2 | 7065 | GEN_VXFORM_ENV(vpkudus, 7, 19); |
d15f74fb BS |
7066 | GEN_VXFORM_ENV(vpkshus, 7, 4); |
7067 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
024215b2 | 7068 | GEN_VXFORM_ENV(vpksdus, 7, 21); |
d15f74fb BS |
7069 | GEN_VXFORM_ENV(vpkshss, 7, 6); |
7070 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
024215b2 | 7071 | GEN_VXFORM_ENV(vpksdss, 7, 23); |
1dd9ffb9 | 7072 | GEN_VXFORM(vpkpx, 7, 12); |
d15f74fb BS |
7073 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); |
7074 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
7075 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
7076 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
7077 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
7078 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
7079 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
7080 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
7081 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
fab3cbe9 | 7082 | |
0cbcd906 | 7083 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 | 7084 | static void glue(gen_, name)(DisasContext *ctx) \ |
0cbcd906 AJ |
7085 | { \ |
7086 | TCGv_ptr ra, rb, rd; \ | |
7087 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7088 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7089 | return; \ | |
7090 | } \ | |
7091 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7092 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7093 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
d15f74fb | 7094 | gen_helper_##opname(cpu_env, rd, ra, rb); \ |
0cbcd906 AJ |
7095 | tcg_temp_free_ptr(ra); \ |
7096 | tcg_temp_free_ptr(rb); \ | |
7097 | tcg_temp_free_ptr(rd); \ | |
7098 | } | |
7099 | ||
7100 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
7101 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
7102 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
7103 | ||
a737d3eb TM |
7104 | /* |
7105 | * Support for Altivec instructions that use bit 31 (Rc) as an opcode | |
7106 | * bit but also use bit 21 as an actual Rc bit. In general, thse pairs | |
7107 | * come from different versions of the ISA, so we must also support a | |
7108 | * pair of flags for each instruction. | |
7109 | */ | |
7110 | #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
7111 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
7112 | { \ | |
7113 | if ((Rc(ctx->opcode) == 0) && \ | |
7114 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
7115 | if (Rc21(ctx->opcode) == 0) { \ | |
7116 | gen_##name0(ctx); \ | |
7117 | } else { \ | |
7118 | gen_##name0##_(ctx); \ | |
7119 | } \ | |
7120 | } else if ((Rc(ctx->opcode) == 1) && \ | |
7121 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
7122 | if (Rc21(ctx->opcode) == 0) { \ | |
7123 | gen_##name1(ctx); \ | |
7124 | } else { \ | |
7125 | gen_##name1##_(ctx); \ | |
7126 | } \ | |
7127 | } else { \ | |
7128 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
7129 | } \ | |
7130 | } | |
7131 | ||
1add6e23 AJ |
7132 | GEN_VXRFORM(vcmpequb, 3, 0) |
7133 | GEN_VXRFORM(vcmpequh, 3, 1) | |
7134 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6f3dab41 | 7135 | GEN_VXRFORM(vcmpequd, 3, 3) |
1add6e23 AJ |
7136 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
7137 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
7138 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6f3dab41 | 7139 | GEN_VXRFORM(vcmpgtsd, 3, 15) |
1add6e23 AJ |
7140 | GEN_VXRFORM(vcmpgtub, 3, 8) |
7141 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
7142 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
6f3dab41 | 7143 | GEN_VXRFORM(vcmpgtud, 3, 11) |
819ca121 AJ |
7144 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
7145 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
7146 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
7147 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 7148 | |
6f3dab41 TM |
7149 | GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \ |
7150 | vcmpequd, PPC_NONE, PPC2_ALTIVEC_207) | |
7151 | GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \ | |
7152 | vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207) | |
7153 | GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \ | |
7154 | vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207) | |
7155 | ||
c026766b | 7156 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 7157 | static void glue(gen_, name)(DisasContext *ctx) \ |
c026766b AJ |
7158 | { \ |
7159 | TCGv_ptr rd; \ | |
7160 | TCGv_i32 simm; \ | |
7161 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7162 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7163 | return; \ | |
7164 | } \ | |
7165 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
7166 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7167 | gen_helper_##name (rd, simm); \ | |
7168 | tcg_temp_free_i32(simm); \ | |
7169 | tcg_temp_free_ptr(rd); \ | |
7170 | } | |
7171 | ||
7172 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
7173 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
7174 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
7175 | ||
de5f2484 | 7176 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef | 7177 | static void glue(gen_, name)(DisasContext *ctx) \ |
de5f2484 AJ |
7178 | { \ |
7179 | TCGv_ptr rb, rd; \ | |
7180 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7181 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7182 | return; \ | |
7183 | } \ | |
7184 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7185 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7186 | gen_helper_##name (rd, rb); \ | |
7187 | tcg_temp_free_ptr(rb); \ | |
7188 | tcg_temp_free_ptr(rd); \ | |
7189 | } | |
7190 | ||
d15f74fb BS |
7191 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ |
7192 | static void glue(gen_, name)(DisasContext *ctx) \ | |
7193 | { \ | |
7194 | TCGv_ptr rb, rd; \ | |
7195 | \ | |
7196 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7197 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7198 | return; \ | |
7199 | } \ | |
7200 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7201 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7202 | gen_helper_##name(cpu_env, rd, rb); \ | |
7203 | tcg_temp_free_ptr(rb); \ | |
7204 | tcg_temp_free_ptr(rd); \ | |
7205 | } | |
7206 | ||
6cf1c6e5 AJ |
7207 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
7208 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
4430e076 | 7209 | GEN_VXFORM_NOA(vupkhsw, 7, 25); |
6cf1c6e5 AJ |
7210 | GEN_VXFORM_NOA(vupklsb, 7, 10); |
7211 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
4430e076 | 7212 | GEN_VXFORM_NOA(vupklsw, 7, 27); |
79f85c3a AJ |
7213 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
7214 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
d15f74fb BS |
7215 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); |
7216 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
7217 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
7218 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
7219 | GEN_VXFORM_NOA_ENV(vrfim, 5, 8); | |
7220 | GEN_VXFORM_NOA_ENV(vrfin, 5, 9); | |
7221 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
7222 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 11); | |
79f85c3a | 7223 | |
21d21583 | 7224 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef | 7225 | static void glue(gen_, name)(DisasContext *ctx) \ |
21d21583 AJ |
7226 | { \ |
7227 | TCGv_ptr rd; \ | |
7228 | TCGv_i32 simm; \ | |
7229 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7230 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7231 | return; \ | |
7232 | } \ | |
7233 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
7234 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7235 | gen_helper_##name (rd, simm); \ | |
7236 | tcg_temp_free_i32(simm); \ | |
7237 | tcg_temp_free_ptr(rd); \ | |
7238 | } | |
7239 | ||
27a4edb3 | 7240 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef | 7241 | static void glue(gen_, name)(DisasContext *ctx) \ |
27a4edb3 AJ |
7242 | { \ |
7243 | TCGv_ptr rb, rd; \ | |
7244 | TCGv_i32 uimm; \ | |
7245 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7246 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7247 | return; \ | |
7248 | } \ | |
7249 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
7250 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7251 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7252 | gen_helper_##name (rd, rb, uimm); \ | |
7253 | tcg_temp_free_i32(uimm); \ | |
7254 | tcg_temp_free_ptr(rb); \ | |
7255 | tcg_temp_free_ptr(rd); \ | |
7256 | } | |
7257 | ||
d15f74fb BS |
7258 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
7259 | static void glue(gen_, name)(DisasContext *ctx) \ | |
7260 | { \ | |
7261 | TCGv_ptr rb, rd; \ | |
7262 | TCGv_i32 uimm; \ | |
7263 | \ | |
7264 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7265 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7266 | return; \ | |
7267 | } \ | |
7268 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
7269 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7270 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7271 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
7272 | tcg_temp_free_i32(uimm); \ | |
7273 | tcg_temp_free_ptr(rb); \ | |
7274 | tcg_temp_free_ptr(rd); \ | |
7275 | } | |
7276 | ||
e4e6bee7 AJ |
7277 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
7278 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
7279 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
d15f74fb BS |
7280 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
7281 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
7282 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
7283 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
e4e6bee7 | 7284 | |
99e300ef | 7285 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
7286 | { |
7287 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 7288 | TCGv_i32 sh; |
cd633b10 AJ |
7289 | if (unlikely(!ctx->altivec_enabled)) { |
7290 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7291 | return; | |
7292 | } | |
7293 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
7294 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
7295 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
7296 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
7297 | gen_helper_vsldoi (rd, ra, rb, sh); | |
7298 | tcg_temp_free_ptr(ra); | |
7299 | tcg_temp_free_ptr(rb); | |
7300 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 7301 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
7302 | } |
7303 | ||
707cec33 | 7304 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
d15f74fb | 7305 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
707cec33 AJ |
7306 | { \ |
7307 | TCGv_ptr ra, rb, rc, rd; \ | |
7308 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7309 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7310 | return; \ | |
7311 | } \ | |
7312 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7313 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7314 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
7315 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7316 | if (Rc(ctx->opcode)) { \ | |
d15f74fb | 7317 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ |
707cec33 | 7318 | } else { \ |
d15f74fb | 7319 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ |
707cec33 AJ |
7320 | } \ |
7321 | tcg_temp_free_ptr(ra); \ | |
7322 | tcg_temp_free_ptr(rb); \ | |
7323 | tcg_temp_free_ptr(rc); \ | |
7324 | tcg_temp_free_ptr(rd); \ | |
7325 | } | |
7326 | ||
b161ae27 AJ |
7327 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
7328 | ||
99e300ef | 7329 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
7330 | { |
7331 | TCGv_ptr ra, rb, rc, rd; | |
7332 | if (unlikely(!ctx->altivec_enabled)) { | |
7333 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7334 | return; | |
7335 | } | |
7336 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
7337 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
7338 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
7339 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
7340 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
7341 | tcg_temp_free_ptr(ra); | |
7342 | tcg_temp_free_ptr(rb); | |
7343 | tcg_temp_free_ptr(rc); | |
7344 | tcg_temp_free_ptr(rd); | |
7345 | } | |
7346 | ||
b04ae981 | 7347 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 7348 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 7349 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 7350 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 7351 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 7352 | |
f293f04a TM |
7353 | GEN_VXFORM_NOA(vclzb, 1, 28) |
7354 | GEN_VXFORM_NOA(vclzh, 1, 29) | |
7355 | GEN_VXFORM_NOA(vclzw, 1, 30) | |
7356 | GEN_VXFORM_NOA(vclzd, 1, 31) | |
e13500b3 TM |
7357 | GEN_VXFORM_NOA(vpopcntb, 1, 28) |
7358 | GEN_VXFORM_NOA(vpopcnth, 1, 29) | |
7359 | GEN_VXFORM_NOA(vpopcntw, 1, 30) | |
7360 | GEN_VXFORM_NOA(vpopcntd, 1, 31) | |
7361 | GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7362 | vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) | |
7363 | GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7364 | vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) | |
7365 | GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7366 | vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) | |
7367 | GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ | |
7368 | vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) | |
4d82038e | 7369 | GEN_VXFORM(vbpermq, 6, 21); |
f1064f61 | 7370 | GEN_VXFORM_NOA(vgbbd, 6, 20); |
b8476fc7 TM |
7371 | GEN_VXFORM(vpmsumb, 4, 16) |
7372 | GEN_VXFORM(vpmsumh, 4, 17) | |
7373 | GEN_VXFORM(vpmsumw, 4, 18) | |
7374 | GEN_VXFORM(vpmsumd, 4, 19) | |
e13500b3 | 7375 | |
e8f7b27b TM |
7376 | #define GEN_BCD(op) \ |
7377 | static void gen_##op(DisasContext *ctx) \ | |
7378 | { \ | |
7379 | TCGv_ptr ra, rb, rd; \ | |
7380 | TCGv_i32 ps; \ | |
7381 | \ | |
7382 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7383 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7384 | return; \ | |
7385 | } \ | |
7386 | \ | |
7387 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7388 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
7389 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7390 | \ | |
7391 | ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ | |
7392 | \ | |
7393 | gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ | |
7394 | \ | |
7395 | tcg_temp_free_ptr(ra); \ | |
7396 | tcg_temp_free_ptr(rb); \ | |
7397 | tcg_temp_free_ptr(rd); \ | |
7398 | tcg_temp_free_i32(ps); \ | |
7399 | } | |
7400 | ||
7401 | GEN_BCD(bcdadd) | |
7402 | GEN_BCD(bcdsub) | |
7403 | ||
7404 | GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ | |
7405 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
7406 | GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \ | |
7407 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
7408 | GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ | |
7409 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
7410 | GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \ | |
7411 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
7412 | ||
557d52fa TM |
7413 | static void gen_vsbox(DisasContext *ctx) |
7414 | { | |
7415 | TCGv_ptr ra, rd; | |
7416 | if (unlikely(!ctx->altivec_enabled)) { | |
7417 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
7418 | return; | |
7419 | } | |
7420 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
7421 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
7422 | gen_helper_vsbox(rd, ra); | |
7423 | tcg_temp_free_ptr(ra); | |
7424 | tcg_temp_free_ptr(rd); | |
7425 | } | |
7426 | ||
7427 | GEN_VXFORM(vcipher, 4, 20) | |
7428 | GEN_VXFORM(vcipherlast, 4, 20) | |
7429 | GEN_VXFORM(vncipher, 4, 21) | |
7430 | GEN_VXFORM(vncipherlast, 4, 21) | |
7431 | ||
7432 | GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207, | |
7433 | vcipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
7434 | GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207, | |
7435 | vncipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
7436 | ||
57354f8f TM |
7437 | #define VSHASIGMA(op) \ |
7438 | static void gen_##op(DisasContext *ctx) \ | |
7439 | { \ | |
7440 | TCGv_ptr ra, rd; \ | |
7441 | TCGv_i32 st_six; \ | |
7442 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7443 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7444 | return; \ | |
7445 | } \ | |
7446 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
7447 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
7448 | st_six = tcg_const_i32(rB(ctx->opcode)); \ | |
7449 | gen_helper_##op(rd, ra, st_six); \ | |
7450 | tcg_temp_free_ptr(ra); \ | |
7451 | tcg_temp_free_ptr(rd); \ | |
7452 | tcg_temp_free_i32(st_six); \ | |
7453 | } | |
7454 | ||
7455 | VSHASIGMA(vshasigmaw) | |
7456 | VSHASIGMA(vshasigmad) | |
7457 | ||
ac174549 TM |
7458 | GEN_VXFORM3(vpermxor, 22, 0xFF) |
7459 | GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, | |
7460 | vpermxor, PPC_NONE, PPC2_ALTIVEC_207) | |
7461 | ||
472b24ce TM |
7462 | /*** VSX extension ***/ |
7463 | ||
7464 | static inline TCGv_i64 cpu_vsrh(int n) | |
7465 | { | |
7466 | if (n < 32) { | |
7467 | return cpu_fpr[n]; | |
7468 | } else { | |
7469 | return cpu_avrh[n-32]; | |
7470 | } | |
7471 | } | |
7472 | ||
7473 | static inline TCGv_i64 cpu_vsrl(int n) | |
7474 | { | |
7475 | if (n < 32) { | |
7476 | return cpu_vsr[n]; | |
7477 | } else { | |
7478 | return cpu_avrl[n-32]; | |
7479 | } | |
7480 | } | |
7481 | ||
e072fe79 TM |
7482 | #define VSX_LOAD_SCALAR(name, operation) \ |
7483 | static void gen_##name(DisasContext *ctx) \ | |
7484 | { \ | |
7485 | TCGv EA; \ | |
7486 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7487 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7488 | return; \ | |
7489 | } \ | |
7490 | gen_set_access_type(ctx, ACCESS_INT); \ | |
7491 | EA = tcg_temp_new(); \ | |
7492 | gen_addr_reg_index(ctx, EA); \ | |
7493 | gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \ | |
7494 | /* NOTE: cpu_vsrl is undefined */ \ | |
7495 | tcg_temp_free(EA); \ | |
7496 | } | |
7497 | ||
7498 | VSX_LOAD_SCALAR(lxsdx, ld64) | |
cac7f0ba TM |
7499 | VSX_LOAD_SCALAR(lxsiwax, ld32s_i64) |
7500 | VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64) | |
7501 | VSX_LOAD_SCALAR(lxsspx, ld32fs) | |
fa1832d7 | 7502 | |
304af367 TM |
7503 | static void gen_lxvd2x(DisasContext *ctx) |
7504 | { | |
7505 | TCGv EA; | |
7506 | if (unlikely(!ctx->vsx_enabled)) { | |
7507 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7508 | return; | |
7509 | } | |
7510 | gen_set_access_type(ctx, ACCESS_INT); | |
7511 | EA = tcg_temp_new(); | |
7512 | gen_addr_reg_index(ctx, EA); | |
7513 | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); | |
7514 | tcg_gen_addi_tl(EA, EA, 8); | |
7515 | gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA); | |
7516 | tcg_temp_free(EA); | |
7517 | } | |
7518 | ||
ca03b467 TM |
7519 | static void gen_lxvdsx(DisasContext *ctx) |
7520 | { | |
7521 | TCGv EA; | |
7522 | if (unlikely(!ctx->vsx_enabled)) { | |
7523 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7524 | return; | |
7525 | } | |
7526 | gen_set_access_type(ctx, ACCESS_INT); | |
7527 | EA = tcg_temp_new(); | |
7528 | gen_addr_reg_index(ctx, EA); | |
7529 | gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA); | |
f976b09e | 7530 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); |
ca03b467 TM |
7531 | tcg_temp_free(EA); |
7532 | } | |
7533 | ||
897e61d1 TM |
7534 | static void gen_lxvw4x(DisasContext *ctx) |
7535 | { | |
f976b09e AG |
7536 | TCGv EA; |
7537 | TCGv_i64 tmp; | |
897e61d1 TM |
7538 | TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode)); |
7539 | TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode)); | |
7540 | if (unlikely(!ctx->vsx_enabled)) { | |
7541 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7542 | return; | |
7543 | } | |
7544 | gen_set_access_type(ctx, ACCESS_INT); | |
7545 | EA = tcg_temp_new(); | |
f976b09e AG |
7546 | tmp = tcg_temp_new_i64(); |
7547 | ||
897e61d1 | 7548 | gen_addr_reg_index(ctx, EA); |
f976b09e | 7549 | gen_qemu_ld32u_i64(ctx, tmp, EA); |
897e61d1 | 7550 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7551 | gen_qemu_ld32u_i64(ctx, xth, EA); |
897e61d1 TM |
7552 | tcg_gen_deposit_i64(xth, xth, tmp, 32, 32); |
7553 | ||
7554 | tcg_gen_addi_tl(EA, EA, 4); | |
f976b09e | 7555 | gen_qemu_ld32u_i64(ctx, tmp, EA); |
897e61d1 | 7556 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7557 | gen_qemu_ld32u_i64(ctx, xtl, EA); |
897e61d1 TM |
7558 | tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32); |
7559 | ||
7560 | tcg_temp_free(EA); | |
f976b09e | 7561 | tcg_temp_free_i64(tmp); |
897e61d1 TM |
7562 | } |
7563 | ||
f026da78 TM |
7564 | #define VSX_STORE_SCALAR(name, operation) \ |
7565 | static void gen_##name(DisasContext *ctx) \ | |
7566 | { \ | |
7567 | TCGv EA; \ | |
7568 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7569 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7570 | return; \ | |
7571 | } \ | |
7572 | gen_set_access_type(ctx, ACCESS_INT); \ | |
7573 | EA = tcg_temp_new(); \ | |
7574 | gen_addr_reg_index(ctx, EA); \ | |
7575 | gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \ | |
7576 | tcg_temp_free(EA); \ | |
9231ba9e TM |
7577 | } |
7578 | ||
f026da78 | 7579 | VSX_STORE_SCALAR(stxsdx, st64) |
e16a626b TM |
7580 | VSX_STORE_SCALAR(stxsiwx, st32_i64) |
7581 | VSX_STORE_SCALAR(stxsspx, st32fs) | |
f026da78 | 7582 | |
fbed2478 TM |
7583 | static void gen_stxvd2x(DisasContext *ctx) |
7584 | { | |
7585 | TCGv EA; | |
7586 | if (unlikely(!ctx->vsx_enabled)) { | |
7587 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7588 | return; | |
7589 | } | |
7590 | gen_set_access_type(ctx, ACCESS_INT); | |
7591 | EA = tcg_temp_new(); | |
7592 | gen_addr_reg_index(ctx, EA); | |
7593 | gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); | |
7594 | tcg_gen_addi_tl(EA, EA, 8); | |
7595 | gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); | |
7596 | tcg_temp_free(EA); | |
7597 | } | |
7598 | ||
86e61ce3 TM |
7599 | static void gen_stxvw4x(DisasContext *ctx) |
7600 | { | |
f976b09e AG |
7601 | TCGv_i64 tmp; |
7602 | TCGv EA; | |
86e61ce3 TM |
7603 | if (unlikely(!ctx->vsx_enabled)) { |
7604 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7605 | return; | |
7606 | } | |
7607 | gen_set_access_type(ctx, ACCESS_INT); | |
7608 | EA = tcg_temp_new(); | |
7609 | gen_addr_reg_index(ctx, EA); | |
f976b09e | 7610 | tmp = tcg_temp_new_i64(); |
86e61ce3 TM |
7611 | |
7612 | tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32); | |
f976b09e | 7613 | gen_qemu_st32_i64(ctx, tmp, EA); |
86e61ce3 | 7614 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7615 | gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA); |
86e61ce3 TM |
7616 | |
7617 | tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32); | |
7618 | tcg_gen_addi_tl(EA, EA, 4); | |
f976b09e | 7619 | gen_qemu_st32_i64(ctx, tmp, EA); |
86e61ce3 | 7620 | tcg_gen_addi_tl(EA, EA, 4); |
f976b09e | 7621 | gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA); |
86e61ce3 TM |
7622 | |
7623 | tcg_temp_free(EA); | |
f976b09e | 7624 | tcg_temp_free_i64(tmp); |
86e61ce3 TM |
7625 | } |
7626 | ||
f5c0f7f9 TM |
7627 | #define MV_VSRW(name, tcgop1, tcgop2, target, source) \ |
7628 | static void gen_##name(DisasContext *ctx) \ | |
7629 | { \ | |
7630 | if (xS(ctx->opcode) < 32) { \ | |
7631 | if (unlikely(!ctx->fpu_enabled)) { \ | |
7632 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
7633 | return; \ | |
7634 | } \ | |
7635 | } else { \ | |
7636 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7637 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7638 | return; \ | |
7639 | } \ | |
7640 | } \ | |
7641 | TCGv_i64 tmp = tcg_temp_new_i64(); \ | |
7642 | tcg_gen_##tcgop1(tmp, source); \ | |
7643 | tcg_gen_##tcgop2(target, tmp); \ | |
7644 | tcg_temp_free_i64(tmp); \ | |
7645 | } | |
7646 | ||
7647 | ||
7648 | MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \ | |
7649 | cpu_vsrh(xS(ctx->opcode))) | |
7650 | MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \ | |
7651 | cpu_gpr[rA(ctx->opcode)]) | |
7652 | MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \ | |
7653 | cpu_gpr[rA(ctx->opcode)]) | |
7654 | ||
7655 | #if defined(TARGET_PPC64) | |
7656 | #define MV_VSRD(name, target, source) \ | |
7657 | static void gen_##name(DisasContext *ctx) \ | |
7658 | { \ | |
7659 | if (xS(ctx->opcode) < 32) { \ | |
7660 | if (unlikely(!ctx->fpu_enabled)) { \ | |
7661 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
7662 | return; \ | |
7663 | } \ | |
7664 | } else { \ | |
7665 | if (unlikely(!ctx->altivec_enabled)) { \ | |
7666 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
7667 | return; \ | |
7668 | } \ | |
7669 | } \ | |
7670 | tcg_gen_mov_i64(target, source); \ | |
7671 | } | |
7672 | ||
7673 | MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode))) | |
7674 | MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]) | |
7675 | ||
7676 | #endif | |
7677 | ||
cd73f2c9 TM |
7678 | static void gen_xxpermdi(DisasContext *ctx) |
7679 | { | |
7680 | if (unlikely(!ctx->vsx_enabled)) { | |
7681 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
7682 | return; | |
7683 | } | |
7684 | ||
f5bc1bfa TM |
7685 | if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) || |
7686 | (xT(ctx->opcode) == xB(ctx->opcode)))) { | |
7687 | TCGv_i64 xh, xl; | |
7688 | ||
7689 | xh = tcg_temp_new_i64(); | |
7690 | xl = tcg_temp_new_i64(); | |
7691 | ||
7692 | if ((DM(ctx->opcode) & 2) == 0) { | |
7693 | tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode))); | |
7694 | } else { | |
7695 | tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode))); | |
7696 | } | |
7697 | if ((DM(ctx->opcode) & 1) == 0) { | |
7698 | tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode))); | |
7699 | } else { | |
7700 | tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode))); | |
7701 | } | |
7702 | ||
7703 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh); | |
7704 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl); | |
7705 | ||
7706 | tcg_temp_free_i64(xh); | |
7707 | tcg_temp_free_i64(xl); | |
cd73f2c9 | 7708 | } else { |
f5bc1bfa TM |
7709 | if ((DM(ctx->opcode) & 2) == 0) { |
7710 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode))); | |
7711 | } else { | |
7712 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode))); | |
7713 | } | |
7714 | if ((DM(ctx->opcode) & 1) == 0) { | |
7715 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode))); | |
7716 | } else { | |
7717 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode))); | |
7718 | } | |
cd73f2c9 TM |
7719 | } |
7720 | } | |
7721 | ||
df020ce0 TM |
7722 | #define OP_ABS 1 |
7723 | #define OP_NABS 2 | |
7724 | #define OP_NEG 3 | |
7725 | #define OP_CPSGN 4 | |
e5d7d2b0 PM |
7726 | #define SGN_MASK_DP 0x8000000000000000ull |
7727 | #define SGN_MASK_SP 0x8000000080000000ull | |
df020ce0 TM |
7728 | |
7729 | #define VSX_SCALAR_MOVE(name, op, sgn_mask) \ | |
7730 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7731 | { \ | |
7732 | TCGv_i64 xb, sgm; \ | |
7733 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7734 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7735 | return; \ | |
7736 | } \ | |
f976b09e AG |
7737 | xb = tcg_temp_new_i64(); \ |
7738 | sgm = tcg_temp_new_i64(); \ | |
df020ce0 TM |
7739 | tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \ |
7740 | tcg_gen_movi_i64(sgm, sgn_mask); \ | |
7741 | switch (op) { \ | |
7742 | case OP_ABS: { \ | |
7743 | tcg_gen_andc_i64(xb, xb, sgm); \ | |
7744 | break; \ | |
7745 | } \ | |
7746 | case OP_NABS: { \ | |
7747 | tcg_gen_or_i64(xb, xb, sgm); \ | |
7748 | break; \ | |
7749 | } \ | |
7750 | case OP_NEG: { \ | |
7751 | tcg_gen_xor_i64(xb, xb, sgm); \ | |
7752 | break; \ | |
7753 | } \ | |
7754 | case OP_CPSGN: { \ | |
f976b09e | 7755 | TCGv_i64 xa = tcg_temp_new_i64(); \ |
df020ce0 TM |
7756 | tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \ |
7757 | tcg_gen_and_i64(xa, xa, sgm); \ | |
7758 | tcg_gen_andc_i64(xb, xb, sgm); \ | |
7759 | tcg_gen_or_i64(xb, xb, xa); \ | |
f976b09e | 7760 | tcg_temp_free_i64(xa); \ |
df020ce0 TM |
7761 | break; \ |
7762 | } \ | |
7763 | } \ | |
7764 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \ | |
f976b09e AG |
7765 | tcg_temp_free_i64(xb); \ |
7766 | tcg_temp_free_i64(sgm); \ | |
df020ce0 TM |
7767 | } |
7768 | ||
7769 | VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP) | |
7770 | VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP) | |
7771 | VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP) | |
7772 | VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP) | |
7773 | ||
be574920 TM |
7774 | #define VSX_VECTOR_MOVE(name, op, sgn_mask) \ |
7775 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7776 | { \ | |
7777 | TCGv_i64 xbh, xbl, sgm; \ | |
7778 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7779 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7780 | return; \ | |
7781 | } \ | |
f976b09e AG |
7782 | xbh = tcg_temp_new_i64(); \ |
7783 | xbl = tcg_temp_new_i64(); \ | |
7784 | sgm = tcg_temp_new_i64(); \ | |
be574920 TM |
7785 | tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \ |
7786 | tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \ | |
7787 | tcg_gen_movi_i64(sgm, sgn_mask); \ | |
7788 | switch (op) { \ | |
7789 | case OP_ABS: { \ | |
7790 | tcg_gen_andc_i64(xbh, xbh, sgm); \ | |
7791 | tcg_gen_andc_i64(xbl, xbl, sgm); \ | |
7792 | break; \ | |
7793 | } \ | |
7794 | case OP_NABS: { \ | |
7795 | tcg_gen_or_i64(xbh, xbh, sgm); \ | |
7796 | tcg_gen_or_i64(xbl, xbl, sgm); \ | |
7797 | break; \ | |
7798 | } \ | |
7799 | case OP_NEG: { \ | |
7800 | tcg_gen_xor_i64(xbh, xbh, sgm); \ | |
7801 | tcg_gen_xor_i64(xbl, xbl, sgm); \ | |
7802 | break; \ | |
7803 | } \ | |
7804 | case OP_CPSGN: { \ | |
f976b09e AG |
7805 | TCGv_i64 xah = tcg_temp_new_i64(); \ |
7806 | TCGv_i64 xal = tcg_temp_new_i64(); \ | |
be574920 TM |
7807 | tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \ |
7808 | tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \ | |
7809 | tcg_gen_and_i64(xah, xah, sgm); \ | |
7810 | tcg_gen_and_i64(xal, xal, sgm); \ | |
7811 | tcg_gen_andc_i64(xbh, xbh, sgm); \ | |
7812 | tcg_gen_andc_i64(xbl, xbl, sgm); \ | |
7813 | tcg_gen_or_i64(xbh, xbh, xah); \ | |
7814 | tcg_gen_or_i64(xbl, xbl, xal); \ | |
f976b09e AG |
7815 | tcg_temp_free_i64(xah); \ |
7816 | tcg_temp_free_i64(xal); \ | |
be574920 TM |
7817 | break; \ |
7818 | } \ | |
7819 | } \ | |
7820 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \ | |
7821 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \ | |
f976b09e AG |
7822 | tcg_temp_free_i64(xbh); \ |
7823 | tcg_temp_free_i64(xbl); \ | |
7824 | tcg_temp_free_i64(sgm); \ | |
be574920 TM |
7825 | } |
7826 | ||
7827 | VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP) | |
7828 | VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP) | |
7829 | VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP) | |
7830 | VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP) | |
7831 | VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP) | |
7832 | VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP) | |
7833 | VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP) | |
7834 | VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP) | |
7835 | ||
3c3cbbdc TM |
7836 | #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \ |
7837 | static void gen_##name(DisasContext * ctx) \ | |
7838 | { \ | |
7839 | TCGv_i32 opc; \ | |
7840 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7841 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7842 | return; \ | |
7843 | } \ | |
7844 | /* NIP cannot be restored if the memory exception comes from an helper */ \ | |
7845 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7846 | opc = tcg_const_i32(ctx->opcode); \ | |
7847 | gen_helper_##name(cpu_env, opc); \ | |
7848 | tcg_temp_free_i32(opc); \ | |
7849 | } | |
be574920 | 7850 | |
3d1140bf TM |
7851 | #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ |
7852 | static void gen_##name(DisasContext * ctx) \ | |
7853 | { \ | |
7854 | if (unlikely(!ctx->vsx_enabled)) { \ | |
7855 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
7856 | return; \ | |
7857 | } \ | |
7858 | /* NIP cannot be restored if the exception comes */ \ | |
7859 | /* from a helper. */ \ | |
7860 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7861 | \ | |
7862 | gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \ | |
7863 | cpu_vsrh(xB(ctx->opcode))); \ | |
7864 | } | |
7865 | ||
ee6e02c0 TM |
7866 | GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX) |
7867 | GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX) | |
5e591d88 | 7868 | GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX) |
4b98eeef | 7869 | GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) |
2009227f | 7870 | GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX) |
d32404fe | 7871 | GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) |
d3f9df8f | 7872 | GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) |
bc80838f | 7873 | GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) |
5cb151ac | 7874 | GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX) |
595c6eef TM |
7875 | GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX) |
7876 | GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX) | |
7877 | GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX) | |
7878 | GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX) | |
7879 | GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX) | |
7880 | GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX) | |
7881 | GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX) | |
7882 | GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX) | |
4f17e9c7 TM |
7883 | GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX) |
7884 | GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX) | |
959e9c9d TM |
7885 | GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX) |
7886 | GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX) | |
ed8ac568 | 7887 | GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX) |
7ee19fb9 | 7888 | GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207) |
ed8ac568 | 7889 | GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX) |
7ee19fb9 | 7890 | GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207) |
5177d2ca TM |
7891 | GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX) |
7892 | GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX) | |
7893 | GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX) | |
7894 | GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX) | |
7895 | GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX) | |
7896 | GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX) | |
88e33d08 TM |
7897 | GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX) |
7898 | GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX) | |
7899 | GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) | |
7900 | GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) | |
7901 | GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) | |
3d1140bf | 7902 | GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207) |
ee6e02c0 | 7903 | |
3fd0aadf TM |
7904 | GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) |
7905 | GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) | |
ab9408a2 | 7906 | GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207) |
b24d0b47 | 7907 | GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207) |
2c0c52ae | 7908 | GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207) |
cea4e574 | 7909 | GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207) |
968e76bc | 7910 | GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207) |
f53f81e0 TM |
7911 | GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207) |
7912 | GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207) | |
7913 | GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207) | |
7914 | GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207) | |
7915 | GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207) | |
7916 | GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207) | |
7917 | GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207) | |
7918 | GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207) | |
74698350 TM |
7919 | GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207) |
7920 | GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207) | |
3fd0aadf | 7921 | |
ee6e02c0 TM |
7922 | GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) |
7923 | GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) | |
5e591d88 | 7924 | GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) |
4b98eeef | 7925 | GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) |
2009227f | 7926 | GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) |
d32404fe | 7927 | GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) |
d3f9df8f | 7928 | GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) |
bc80838f | 7929 | GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) |
5cb151ac | 7930 | GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX) |
595c6eef TM |
7931 | GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX) |
7932 | GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX) | |
7933 | GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX) | |
7934 | GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX) | |
7935 | GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX) | |
7936 | GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX) | |
7937 | GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX) | |
7938 | GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX) | |
959e9c9d TM |
7939 | GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX) |
7940 | GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX) | |
354a6dec TM |
7941 | GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX) |
7942 | GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX) | |
7943 | GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX) | |
ed8ac568 | 7944 | GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX) |
5177d2ca TM |
7945 | GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX) |
7946 | GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX) | |
7947 | GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX) | |
7948 | GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX) | |
7949 | GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX) | |
7950 | GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX) | |
7951 | GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX) | |
7952 | GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX) | |
88e33d08 TM |
7953 | GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX) |
7954 | GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX) | |
7955 | GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX) | |
7956 | GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX) | |
7957 | GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX) | |
ee6e02c0 TM |
7958 | |
7959 | GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) | |
7960 | GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) | |
5e591d88 | 7961 | GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX) |
4b98eeef | 7962 | GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) |
2009227f | 7963 | GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX) |
d32404fe | 7964 | GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) |
d3f9df8f | 7965 | GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) |
bc80838f | 7966 | GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) |
5cb151ac | 7967 | GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX) |
595c6eef TM |
7968 | GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX) |
7969 | GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX) | |
7970 | GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX) | |
7971 | GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX) | |
7972 | GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX) | |
7973 | GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX) | |
7974 | GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX) | |
7975 | GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX) | |
959e9c9d TM |
7976 | GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX) |
7977 | GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX) | |
354a6dec TM |
7978 | GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX) |
7979 | GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX) | |
7980 | GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX) | |
ed8ac568 | 7981 | GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX) |
5177d2ca TM |
7982 | GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX) |
7983 | GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX) | |
7984 | GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX) | |
7985 | GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX) | |
7986 | GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX) | |
7987 | GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX) | |
7988 | GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX) | |
7989 | GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX) | |
88e33d08 TM |
7990 | GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX) |
7991 | GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX) | |
7992 | GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX) | |
7993 | GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX) | |
7994 | GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX) | |
ee6e02c0 | 7995 | |
79ca8a6a TM |
7996 | #define VSX_LOGICAL(name, tcg_op) \ |
7997 | static void glue(gen_, name)(DisasContext * ctx) \ | |
7998 | { \ | |
7999 | if (unlikely(!ctx->vsx_enabled)) { \ | |
8000 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
8001 | return; \ | |
8002 | } \ | |
8003 | tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \ | |
8004 | cpu_vsrh(xB(ctx->opcode))); \ | |
8005 | tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \ | |
8006 | cpu_vsrl(xB(ctx->opcode))); \ | |
8007 | } | |
8008 | ||
f976b09e AG |
8009 | VSX_LOGICAL(xxland, tcg_gen_and_i64) |
8010 | VSX_LOGICAL(xxlandc, tcg_gen_andc_i64) | |
8011 | VSX_LOGICAL(xxlor, tcg_gen_or_i64) | |
8012 | VSX_LOGICAL(xxlxor, tcg_gen_xor_i64) | |
8013 | VSX_LOGICAL(xxlnor, tcg_gen_nor_i64) | |
67a33f37 TM |
8014 | VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64) |
8015 | VSX_LOGICAL(xxlnand, tcg_gen_nand_i64) | |
8016 | VSX_LOGICAL(xxlorc, tcg_gen_orc_i64) | |
df020ce0 | 8017 | |
ce577d2e TM |
8018 | #define VSX_XXMRG(name, high) \ |
8019 | static void glue(gen_, name)(DisasContext * ctx) \ | |
8020 | { \ | |
8021 | TCGv_i64 a0, a1, b0, b1; \ | |
8022 | if (unlikely(!ctx->vsx_enabled)) { \ | |
8023 | gen_exception(ctx, POWERPC_EXCP_VSXU); \ | |
8024 | return; \ | |
8025 | } \ | |
f976b09e AG |
8026 | a0 = tcg_temp_new_i64(); \ |
8027 | a1 = tcg_temp_new_i64(); \ | |
8028 | b0 = tcg_temp_new_i64(); \ | |
8029 | b1 = tcg_temp_new_i64(); \ | |
ce577d2e TM |
8030 | if (high) { \ |
8031 | tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \ | |
8032 | tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \ | |
8033 | tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \ | |
8034 | tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \ | |
8035 | } else { \ | |
8036 | tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \ | |
8037 | tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \ | |
8038 | tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \ | |
8039 | tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \ | |
8040 | } \ | |
8041 | tcg_gen_shri_i64(a0, a0, 32); \ | |
8042 | tcg_gen_shri_i64(b0, b0, 32); \ | |
8043 | tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \ | |
8044 | b0, a0, 32, 32); \ | |
8045 | tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \ | |
8046 | b1, a1, 32, 32); \ | |
f976b09e AG |
8047 | tcg_temp_free_i64(a0); \ |
8048 | tcg_temp_free_i64(a1); \ | |
8049 | tcg_temp_free_i64(b0); \ | |
8050 | tcg_temp_free_i64(b1); \ | |
ce577d2e TM |
8051 | } |
8052 | ||
8053 | VSX_XXMRG(xxmrghw, 1) | |
8054 | VSX_XXMRG(xxmrglw, 0) | |
8055 | ||
551e3ef7 TM |
8056 | static void gen_xxsel(DisasContext * ctx) |
8057 | { | |
8058 | TCGv_i64 a, b, c; | |
8059 | if (unlikely(!ctx->vsx_enabled)) { | |
8060 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
8061 | return; | |
8062 | } | |
f976b09e AG |
8063 | a = tcg_temp_new_i64(); |
8064 | b = tcg_temp_new_i64(); | |
8065 | c = tcg_temp_new_i64(); | |
551e3ef7 TM |
8066 | |
8067 | tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode))); | |
8068 | tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode))); | |
8069 | tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode))); | |
8070 | ||
8071 | tcg_gen_and_i64(b, b, c); | |
8072 | tcg_gen_andc_i64(a, a, c); | |
8073 | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b); | |
8074 | ||
8075 | tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode))); | |
8076 | tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode))); | |
8077 | tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode))); | |
8078 | ||
8079 | tcg_gen_and_i64(b, b, c); | |
8080 | tcg_gen_andc_i64(a, a, c); | |
8081 | tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b); | |
8082 | ||
f976b09e AG |
8083 | tcg_temp_free_i64(a); |
8084 | tcg_temp_free_i64(b); | |
8085 | tcg_temp_free_i64(c); | |
551e3ef7 TM |
8086 | } |
8087 | ||
76c15fe0 TM |
8088 | static void gen_xxspltw(DisasContext *ctx) |
8089 | { | |
8090 | TCGv_i64 b, b2; | |
8091 | TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ? | |
8092 | cpu_vsrl(xB(ctx->opcode)) : | |
8093 | cpu_vsrh(xB(ctx->opcode)); | |
8094 | ||
8095 | if (unlikely(!ctx->vsx_enabled)) { | |
8096 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
8097 | return; | |
8098 | } | |
8099 | ||
f976b09e AG |
8100 | b = tcg_temp_new_i64(); |
8101 | b2 = tcg_temp_new_i64(); | |
76c15fe0 TM |
8102 | |
8103 | if (UIM(ctx->opcode) & 1) { | |
8104 | tcg_gen_ext32u_i64(b, vsr); | |
8105 | } else { | |
8106 | tcg_gen_shri_i64(b, vsr, 32); | |
8107 | } | |
8108 | ||
8109 | tcg_gen_shli_i64(b2, b, 32); | |
8110 | tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2); | |
8111 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode))); | |
8112 | ||
f976b09e AG |
8113 | tcg_temp_free_i64(b); |
8114 | tcg_temp_free_i64(b2); | |
76c15fe0 TM |
8115 | } |
8116 | ||
acc42968 TM |
8117 | static void gen_xxsldwi(DisasContext *ctx) |
8118 | { | |
8119 | TCGv_i64 xth, xtl; | |
8120 | if (unlikely(!ctx->vsx_enabled)) { | |
8121 | gen_exception(ctx, POWERPC_EXCP_VSXU); | |
8122 | return; | |
8123 | } | |
f976b09e AG |
8124 | xth = tcg_temp_new_i64(); |
8125 | xtl = tcg_temp_new_i64(); | |
acc42968 TM |
8126 | |
8127 | switch (SHW(ctx->opcode)) { | |
8128 | case 0: { | |
8129 | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); | |
8130 | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); | |
8131 | break; | |
8132 | } | |
8133 | case 1: { | |
f976b09e | 8134 | TCGv_i64 t0 = tcg_temp_new_i64(); |
acc42968 TM |
8135 | tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode))); |
8136 | tcg_gen_shli_i64(xth, xth, 32); | |
8137 | tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode))); | |
8138 | tcg_gen_shri_i64(t0, t0, 32); | |
8139 | tcg_gen_or_i64(xth, xth, t0); | |
8140 | tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode))); | |
8141 | tcg_gen_shli_i64(xtl, xtl, 32); | |
8142 | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); | |
8143 | tcg_gen_shri_i64(t0, t0, 32); | |
8144 | tcg_gen_or_i64(xtl, xtl, t0); | |
f976b09e | 8145 | tcg_temp_free_i64(t0); |
acc42968 TM |
8146 | break; |
8147 | } | |
8148 | case 2: { | |
8149 | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); | |
8150 | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); | |
8151 | break; | |
8152 | } | |
8153 | case 3: { | |
f976b09e | 8154 | TCGv_i64 t0 = tcg_temp_new_i64(); |
acc42968 TM |
8155 | tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode))); |
8156 | tcg_gen_shli_i64(xth, xth, 32); | |
8157 | tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode))); | |
8158 | tcg_gen_shri_i64(t0, t0, 32); | |
8159 | tcg_gen_or_i64(xth, xth, t0); | |
8160 | tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode))); | |
8161 | tcg_gen_shli_i64(xtl, xtl, 32); | |
8162 | tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode))); | |
8163 | tcg_gen_shri_i64(t0, t0, 32); | |
8164 | tcg_gen_or_i64(xtl, xtl, t0); | |
f976b09e | 8165 | tcg_temp_free_i64(t0); |
acc42968 TM |
8166 | break; |
8167 | } | |
8168 | } | |
8169 | ||
8170 | tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth); | |
8171 | tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl); | |
8172 | ||
f976b09e AG |
8173 | tcg_temp_free_i64(xth); |
8174 | tcg_temp_free_i64(xtl); | |
acc42968 TM |
8175 | } |
8176 | ||
f0b01f02 TM |
8177 | /*** Decimal Floating Point ***/ |
8178 | ||
8179 | static inline TCGv_ptr gen_fprp_ptr(int reg) | |
8180 | { | |
8181 | TCGv_ptr r = tcg_temp_new_ptr(); | |
8182 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg])); | |
8183 | return r; | |
8184 | } | |
8185 | ||
8186 | #if defined(TARGET_PPC64) | |
f0b01f02 TM |
8187 | static void gen_set_cr6_from_fpscr(DisasContext *ctx) |
8188 | { | |
8189 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
8190 | tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); | |
8191 | tcg_gen_shri_i32(cpu_crf[1], tmp, 28); | |
8192 | tcg_temp_free_i32(tmp); | |
8193 | } | |
8194 | #else | |
f0b01f02 TM |
8195 | static void gen_set_cr6_from_fpscr(DisasContext *ctx) |
8196 | { | |
8197 | tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); | |
8198 | } | |
8199 | #endif | |
8200 | ||
8201 | #define GEN_DFP_T_A_B_Rc(name) \ | |
8202 | static void gen_##name(DisasContext *ctx) \ | |
8203 | { \ | |
8204 | TCGv_ptr rd, ra, rb; \ | |
8205 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8206 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8207 | return; \ | |
8208 | } \ | |
8209 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8210 | rd = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8211 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8212 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8213 | gen_helper_##name(cpu_env, rd, ra, rb); \ | |
8214 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8215 | gen_set_cr6_from_fpscr(ctx); \ | |
8216 | } \ | |
8217 | tcg_temp_free_ptr(rd); \ | |
8218 | tcg_temp_free_ptr(ra); \ | |
8219 | tcg_temp_free_ptr(rb); \ | |
8220 | } | |
8221 | ||
8222 | #define GEN_DFP_BF_A_B(name) \ | |
8223 | static void gen_##name(DisasContext *ctx) \ | |
8224 | { \ | |
8225 | TCGv_ptr ra, rb; \ | |
8226 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8227 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8228 | return; \ | |
8229 | } \ | |
8230 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8231 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8232 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8233 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
8234 | cpu_env, ra, rb); \ | |
8235 | tcg_temp_free_ptr(ra); \ | |
8236 | tcg_temp_free_ptr(rb); \ | |
8237 | } | |
8238 | ||
8239 | #define GEN_DFP_BF_A_DCM(name) \ | |
8240 | static void gen_##name(DisasContext *ctx) \ | |
8241 | { \ | |
8242 | TCGv_ptr ra; \ | |
8243 | TCGv_i32 dcm; \ | |
8244 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8245 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8246 | return; \ | |
8247 | } \ | |
8248 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8249 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8250 | dcm = tcg_const_i32(DCM(ctx->opcode)); \ | |
8251 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
8252 | cpu_env, ra, dcm); \ | |
8253 | tcg_temp_free_ptr(ra); \ | |
8254 | tcg_temp_free_i32(dcm); \ | |
8255 | } | |
8256 | ||
8257 | #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \ | |
8258 | static void gen_##name(DisasContext *ctx) \ | |
8259 | { \ | |
8260 | TCGv_ptr rt, rb; \ | |
8261 | TCGv_i32 u32_1, u32_2; \ | |
8262 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8263 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8264 | return; \ | |
8265 | } \ | |
8266 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8267 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8268 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8269 | u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \ | |
8270 | u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \ | |
8271 | gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \ | |
8272 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8273 | gen_set_cr6_from_fpscr(ctx); \ | |
8274 | } \ | |
8275 | tcg_temp_free_ptr(rt); \ | |
8276 | tcg_temp_free_ptr(rb); \ | |
8277 | tcg_temp_free_i32(u32_1); \ | |
8278 | tcg_temp_free_i32(u32_2); \ | |
8279 | } | |
8280 | ||
8281 | #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \ | |
8282 | static void gen_##name(DisasContext *ctx) \ | |
8283 | { \ | |
8284 | TCGv_ptr rt, ra, rb; \ | |
8285 | TCGv_i32 i32; \ | |
8286 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8287 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8288 | return; \ | |
8289 | } \ | |
8290 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8291 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8292 | ra = gen_fprp_ptr(rA(ctx->opcode)); \ | |
8293 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8294 | i32 = tcg_const_i32(i32fld(ctx->opcode)); \ | |
8295 | gen_helper_##name(cpu_env, rt, ra, rb, i32); \ | |
8296 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8297 | gen_set_cr6_from_fpscr(ctx); \ | |
8298 | } \ | |
8299 | tcg_temp_free_ptr(rt); \ | |
8300 | tcg_temp_free_ptr(rb); \ | |
8301 | tcg_temp_free_ptr(ra); \ | |
8302 | tcg_temp_free_i32(i32); \ | |
8303 | } | |
8304 | ||
8305 | #define GEN_DFP_T_B_Rc(name) \ | |
8306 | static void gen_##name(DisasContext *ctx) \ | |
8307 | { \ | |
8308 | TCGv_ptr rt, rb; \ | |
8309 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8310 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8311 | return; \ | |
8312 | } \ | |
8313 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8314 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8315 | rb = gen_fprp_ptr(rB(ctx->opcode)); \ | |
8316 | gen_helper_##name(cpu_env, rt, rb); \ | |
8317 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8318 | gen_set_cr6_from_fpscr(ctx); \ | |
8319 | } \ | |
8320 | tcg_temp_free_ptr(rt); \ | |
8321 | tcg_temp_free_ptr(rb); \ | |
8322 | } | |
8323 | ||
8324 | #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \ | |
8325 | static void gen_##name(DisasContext *ctx) \ | |
8326 | { \ | |
8327 | TCGv_ptr rt, rs; \ | |
8328 | TCGv_i32 i32; \ | |
8329 | if (unlikely(!ctx->fpu_enabled)) { \ | |
8330 | gen_exception(ctx, POWERPC_EXCP_FPU); \ | |
8331 | return; \ | |
8332 | } \ | |
8333 | gen_update_nip(ctx, ctx->nip - 4); \ | |
8334 | rt = gen_fprp_ptr(rD(ctx->opcode)); \ | |
8335 | rs = gen_fprp_ptr(fprfld(ctx->opcode)); \ | |
8336 | i32 = tcg_const_i32(i32fld(ctx->opcode)); \ | |
8337 | gen_helper_##name(cpu_env, rt, rs, i32); \ | |
8338 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
8339 | gen_set_cr6_from_fpscr(ctx); \ | |
8340 | } \ | |
8341 | tcg_temp_free_ptr(rt); \ | |
8342 | tcg_temp_free_ptr(rs); \ | |
8343 | tcg_temp_free_i32(i32); \ | |
8344 | } | |
ce577d2e | 8345 | |
a9d7ba03 TM |
8346 | GEN_DFP_T_A_B_Rc(dadd) |
8347 | GEN_DFP_T_A_B_Rc(daddq) | |
2128f8a5 TM |
8348 | GEN_DFP_T_A_B_Rc(dsub) |
8349 | GEN_DFP_T_A_B_Rc(dsubq) | |
8de6a1cc TM |
8350 | GEN_DFP_T_A_B_Rc(dmul) |
8351 | GEN_DFP_T_A_B_Rc(dmulq) | |
9024ff40 TM |
8352 | GEN_DFP_T_A_B_Rc(ddiv) |
8353 | GEN_DFP_T_A_B_Rc(ddivq) | |
5833505b TM |
8354 | GEN_DFP_BF_A_B(dcmpu) |
8355 | GEN_DFP_BF_A_B(dcmpuq) | |
8356 | GEN_DFP_BF_A_B(dcmpo) | |
8357 | GEN_DFP_BF_A_B(dcmpoq) | |
e601c1ee TM |
8358 | GEN_DFP_BF_A_DCM(dtstdc) |
8359 | GEN_DFP_BF_A_DCM(dtstdcq) | |
1bf9c0e1 TM |
8360 | GEN_DFP_BF_A_DCM(dtstdg) |
8361 | GEN_DFP_BF_A_DCM(dtstdgq) | |
f3d2b0bc TM |
8362 | GEN_DFP_BF_A_B(dtstex) |
8363 | GEN_DFP_BF_A_B(dtstexq) | |
f6022a76 TM |
8364 | GEN_DFP_BF_A_B(dtstsf) |
8365 | GEN_DFP_BF_A_B(dtstsfq) | |
5826ebe2 TM |
8366 | GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC) |
8367 | GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC) | |
8368 | GEN_DFP_T_A_B_I32_Rc(dqua, RMC) | |
8369 | GEN_DFP_T_A_B_I32_Rc(dquaq, RMC) | |
512918aa TM |
8370 | GEN_DFP_T_A_B_I32_Rc(drrnd, RMC) |
8371 | GEN_DFP_T_A_B_I32_Rc(drrndq, RMC) | |
97c0d930 TM |
8372 | GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC) |
8373 | GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC) | |
8374 | GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC) | |
8375 | GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC) | |
290d9ee5 TM |
8376 | GEN_DFP_T_B_Rc(dctdp) |
8377 | GEN_DFP_T_B_Rc(dctqpq) | |
ca603eb4 TM |
8378 | GEN_DFP_T_B_Rc(drsp) |
8379 | GEN_DFP_T_B_Rc(drdpq) | |
f1214193 TM |
8380 | GEN_DFP_T_B_Rc(dcffix) |
8381 | GEN_DFP_T_B_Rc(dcffixq) | |
bea0dd79 TM |
8382 | GEN_DFP_T_B_Rc(dctfix) |
8383 | GEN_DFP_T_B_Rc(dctfixq) | |
7796676f TM |
8384 | GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP) |
8385 | GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP) | |
013c3ac0 TM |
8386 | GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP) |
8387 | GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP) | |
e8a48460 TM |
8388 | GEN_DFP_T_B_Rc(dxex) |
8389 | GEN_DFP_T_B_Rc(dxexq) | |
297666eb TM |
8390 | GEN_DFP_T_A_B_Rc(diex) |
8391 | GEN_DFP_T_A_B_Rc(diexq) | |
804e654a TM |
8392 | GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM) |
8393 | GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM) | |
8394 | GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM) | |
8395 | GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM) | |
8396 | ||
0487d6a8 | 8397 | /*** SPE extension ***/ |
0487d6a8 | 8398 | /* Register moves */ |
3cd7d1dd | 8399 | |
a0e13900 FC |
8400 | static inline void gen_evmra(DisasContext *ctx) |
8401 | { | |
8402 | ||
8403 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8404 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8405 | return; |
8406 | } | |
8407 | ||
a0e13900 FC |
8408 | TCGv_i64 tmp = tcg_temp_new_i64(); |
8409 | ||
8410 | /* tmp := rA_lo + rA_hi << 32 */ | |
13b6a455 | 8411 | tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
a0e13900 FC |
8412 | |
8413 | /* spe_acc := tmp */ | |
1328c2bf | 8414 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8415 | tcg_temp_free_i64(tmp); |
8416 | ||
8417 | /* rD := rA */ | |
13b6a455 AG |
8418 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8419 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
a0e13900 FC |
8420 | } |
8421 | ||
636aa200 BS |
8422 | static inline void gen_load_gpr64(TCGv_i64 t, int reg) |
8423 | { | |
13b6a455 | 8424 | tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
f78fb44e | 8425 | } |
3cd7d1dd | 8426 | |
636aa200 BS |
8427 | static inline void gen_store_gpr64(int reg, TCGv_i64 t) |
8428 | { | |
13b6a455 | 8429 | tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t); |
f78fb44e | 8430 | } |
3cd7d1dd | 8431 | |
70560da7 | 8432 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
99e300ef | 8433 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ |
0487d6a8 JM |
8434 | { \ |
8435 | if (Rc(ctx->opcode)) \ | |
8436 | gen_##name1(ctx); \ | |
8437 | else \ | |
8438 | gen_##name0(ctx); \ | |
8439 | } | |
8440 | ||
8441 | /* Handler for undefined SPE opcodes */ | |
636aa200 | 8442 | static inline void gen_speundef(DisasContext *ctx) |
0487d6a8 | 8443 | { |
e06fcd75 | 8444 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
8445 | } |
8446 | ||
57951c27 | 8447 | /* SPE logic */ |
57951c27 | 8448 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ |
636aa200 | 8449 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8450 | { \ |
8451 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8452 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8453 | return; \ |
8454 | } \ | |
8455 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
8456 | cpu_gpr[rB(ctx->opcode)]); \ | |
8457 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
8458 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 8459 | } |
57951c27 AJ |
8460 | |
8461 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
8462 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
8463 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
8464 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
8465 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
8466 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
8467 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
8468 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 8469 | |
57951c27 | 8470 | /* SPE logic immediate */ |
57951c27 | 8471 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ |
636aa200 | 8472 | static inline void gen_##name(DisasContext *ctx) \ |
3d3a6a0a | 8473 | { \ |
13b6a455 | 8474 | TCGv_i32 t0; \ |
3d3a6a0a | 8475 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8476 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
3d3a6a0a AJ |
8477 | return; \ |
8478 | } \ | |
13b6a455 AG |
8479 | t0 = tcg_temp_new_i32(); \ |
8480 | \ | |
8481 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8482 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
8483 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
8484 | \ | |
8485 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ | |
57951c27 | 8486 | tcg_opi(t0, t0, rB(ctx->opcode)); \ |
13b6a455 AG |
8487 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ |
8488 | \ | |
a7812ae4 | 8489 | tcg_temp_free_i32(t0); \ |
3d3a6a0a | 8490 | } |
57951c27 AJ |
8491 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); |
8492 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
8493 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
8494 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 8495 | |
57951c27 | 8496 | /* SPE arithmetic */ |
57951c27 | 8497 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
636aa200 | 8498 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8499 | { \ |
13b6a455 | 8500 | TCGv_i32 t0; \ |
0487d6a8 | 8501 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8502 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
8503 | return; \ |
8504 | } \ | |
13b6a455 AG |
8505 | t0 = tcg_temp_new_i32(); \ |
8506 | \ | |
8507 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
57951c27 | 8508 | tcg_op(t0, t0); \ |
13b6a455 AG |
8509 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ |
8510 | \ | |
8511 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ | |
8512 | tcg_op(t0, t0); \ | |
8513 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ | |
8514 | \ | |
a7812ae4 | 8515 | tcg_temp_free_i32(t0); \ |
57951c27 | 8516 | } |
0487d6a8 | 8517 | |
636aa200 | 8518 | static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
8519 | { |
8520 | int l1 = gen_new_label(); | |
8521 | int l2 = gen_new_label(); | |
0487d6a8 | 8522 | |
57951c27 AJ |
8523 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
8524 | tcg_gen_neg_i32(ret, arg1); | |
8525 | tcg_gen_br(l2); | |
8526 | gen_set_label(l1); | |
a7812ae4 | 8527 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
8528 | gen_set_label(l2); |
8529 | } | |
8530 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
8531 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
8532 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
8533 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
636aa200 | 8534 | static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 8535 | { |
57951c27 AJ |
8536 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
8537 | tcg_gen_ext16u_i32(ret, ret); | |
8538 | } | |
8539 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
8540 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
8541 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 8542 | |
57951c27 | 8543 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ |
636aa200 | 8544 | static inline void gen_##name(DisasContext *ctx) \ |
0487d6a8 | 8545 | { \ |
13b6a455 | 8546 | TCGv_i32 t0, t1; \ |
0487d6a8 | 8547 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8548 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
0487d6a8 JM |
8549 | return; \ |
8550 | } \ | |
13b6a455 AG |
8551 | t0 = tcg_temp_new_i32(); \ |
8552 | t1 = tcg_temp_new_i32(); \ | |
8553 | \ | |
8554 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
8555 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
8556 | tcg_op(t0, t0, t1); \ | |
8557 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
8558 | \ | |
8559 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \ | |
8560 | tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \ | |
8561 | tcg_op(t0, t0, t1); \ | |
8562 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ | |
8563 | \ | |
a7812ae4 PB |
8564 | tcg_temp_free_i32(t0); \ |
8565 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 8566 | } |
0487d6a8 | 8567 | |
636aa200 | 8568 | static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8569 | { |
a7812ae4 | 8570 | TCGv_i32 t0; |
57951c27 | 8571 | int l1, l2; |
0487d6a8 | 8572 | |
57951c27 AJ |
8573 | l1 = gen_new_label(); |
8574 | l2 = gen_new_label(); | |
a7812ae4 | 8575 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
8576 | /* No error here: 6 bits are used */ |
8577 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
8578 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
8579 | tcg_gen_shr_i32(ret, arg1, t0); | |
8580 | tcg_gen_br(l2); | |
8581 | gen_set_label(l1); | |
8582 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 8583 | gen_set_label(l2); |
a7812ae4 | 8584 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8585 | } |
8586 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
636aa200 | 8587 | static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8588 | { |
a7812ae4 | 8589 | TCGv_i32 t0; |
57951c27 AJ |
8590 | int l1, l2; |
8591 | ||
8592 | l1 = gen_new_label(); | |
8593 | l2 = gen_new_label(); | |
a7812ae4 | 8594 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
8595 | /* No error here: 6 bits are used */ |
8596 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
8597 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
8598 | tcg_gen_sar_i32(ret, arg1, t0); | |
8599 | tcg_gen_br(l2); | |
8600 | gen_set_label(l1); | |
8601 | tcg_gen_movi_i32(ret, 0); | |
0aef4261 | 8602 | gen_set_label(l2); |
a7812ae4 | 8603 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8604 | } |
8605 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
636aa200 | 8606 | static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8607 | { |
a7812ae4 | 8608 | TCGv_i32 t0; |
57951c27 AJ |
8609 | int l1, l2; |
8610 | ||
8611 | l1 = gen_new_label(); | |
8612 | l2 = gen_new_label(); | |
a7812ae4 | 8613 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
8614 | /* No error here: 6 bits are used */ |
8615 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
8616 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
8617 | tcg_gen_shl_i32(ret, arg1, t0); | |
8618 | tcg_gen_br(l2); | |
8619 | gen_set_label(l1); | |
8620 | tcg_gen_movi_i32(ret, 0); | |
e29ef9fa | 8621 | gen_set_label(l2); |
a7812ae4 | 8622 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8623 | } |
8624 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
636aa200 | 8625 | static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 8626 | { |
a7812ae4 | 8627 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
8628 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
8629 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 8630 | tcg_temp_free_i32(t0); |
57951c27 AJ |
8631 | } |
8632 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
636aa200 | 8633 | static inline void gen_evmergehi(DisasContext *ctx) |
57951c27 AJ |
8634 | { |
8635 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8636 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8637 | return; |
8638 | } | |
13b6a455 AG |
8639 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8640 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
57951c27 AJ |
8641 | } |
8642 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
636aa200 | 8643 | static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 8644 | { |
57951c27 AJ |
8645 | tcg_gen_sub_i32(ret, arg2, arg1); |
8646 | } | |
8647 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 8648 | |
57951c27 | 8649 | /* SPE arithmetic immediate */ |
57951c27 | 8650 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ |
636aa200 | 8651 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 | 8652 | { \ |
13b6a455 | 8653 | TCGv_i32 t0; \ |
57951c27 | 8654 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 8655 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8656 | return; \ |
8657 | } \ | |
13b6a455 AG |
8658 | t0 = tcg_temp_new_i32(); \ |
8659 | \ | |
8660 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 8661 | tcg_op(t0, t0, rA(ctx->opcode)); \ |
13b6a455 AG |
8662 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ |
8663 | \ | |
8664 | tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \ | |
8665 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
8666 | tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ | |
8667 | \ | |
a7812ae4 | 8668 | tcg_temp_free_i32(t0); \ |
57951c27 | 8669 | } |
57951c27 AJ |
8670 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); |
8671 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
8672 | ||
8673 | /* SPE comparison */ | |
57951c27 | 8674 | #define GEN_SPEOP_COMP(name, tcg_cond) \ |
636aa200 | 8675 | static inline void gen_##name(DisasContext *ctx) \ |
57951c27 AJ |
8676 | { \ |
8677 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 8678 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
57951c27 AJ |
8679 | return; \ |
8680 | } \ | |
8681 | int l1 = gen_new_label(); \ | |
8682 | int l2 = gen_new_label(); \ | |
8683 | int l3 = gen_new_label(); \ | |
8684 | int l4 = gen_new_label(); \ | |
8685 | \ | |
13b6a455 AG |
8686 | tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ |
8687 | tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
8688 | tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
8689 | tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \ | |
8690 | \ | |
8691 | tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
57951c27 | 8692 | cpu_gpr[rB(ctx->opcode)], l1); \ |
13b6a455 | 8693 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
8694 | tcg_gen_br(l2); \ |
8695 | gen_set_label(l1); \ | |
8696 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
8697 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
8698 | gen_set_label(l2); \ | |
13b6a455 | 8699 | tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ |
57951c27 AJ |
8700 | cpu_gprh[rB(ctx->opcode)], l3); \ |
8701 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
8702 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
8703 | tcg_gen_br(l4); \ | |
8704 | gen_set_label(l3); \ | |
8705 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
8706 | CRF_CH | CRF_CH_OR_CL); \ | |
8707 | gen_set_label(l4); \ | |
8708 | } | |
57951c27 AJ |
8709 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); |
8710 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
8711 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
8712 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
8713 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
8714 | ||
8715 | /* SPE misc */ | |
636aa200 | 8716 | static inline void gen_brinc(DisasContext *ctx) |
57951c27 AJ |
8717 | { |
8718 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
8719 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
8720 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 8721 | } |
636aa200 | 8722 | static inline void gen_evmergelo(DisasContext *ctx) |
57951c27 AJ |
8723 | { |
8724 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8725 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8726 | return; |
8727 | } | |
13b6a455 AG |
8728 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
8729 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
57951c27 | 8730 | } |
636aa200 | 8731 | static inline void gen_evmergehilo(DisasContext *ctx) |
57951c27 AJ |
8732 | { |
8733 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8734 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8735 | return; |
8736 | } | |
13b6a455 AG |
8737 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
8738 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
57951c27 | 8739 | } |
636aa200 | 8740 | static inline void gen_evmergelohi(DisasContext *ctx) |
57951c27 AJ |
8741 | { |
8742 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8743 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
57951c27 AJ |
8744 | return; |
8745 | } | |
33890b3e | 8746 | if (rD(ctx->opcode) == rA(ctx->opcode)) { |
13b6a455 AG |
8747 | TCGv tmp = tcg_temp_new(); |
8748 | tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]); | |
8749 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
8750 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp); | |
8751 | tcg_temp_free(tmp); | |
33890b3e | 8752 | } else { |
13b6a455 AG |
8753 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
8754 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
33890b3e | 8755 | } |
57951c27 | 8756 | } |
636aa200 | 8757 | static inline void gen_evsplati(DisasContext *ctx) |
57951c27 | 8758 | { |
ae01847f | 8759 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27; |
0487d6a8 | 8760 | |
13b6a455 AG |
8761 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); |
8762 | tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); | |
57951c27 | 8763 | } |
636aa200 | 8764 | static inline void gen_evsplatfi(DisasContext *ctx) |
0487d6a8 | 8765 | { |
ae01847f | 8766 | uint64_t imm = rA(ctx->opcode) << 27; |
0487d6a8 | 8767 | |
13b6a455 AG |
8768 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm); |
8769 | tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm); | |
0487d6a8 JM |
8770 | } |
8771 | ||
636aa200 | 8772 | static inline void gen_evsel(DisasContext *ctx) |
57951c27 AJ |
8773 | { |
8774 | int l1 = gen_new_label(); | |
8775 | int l2 = gen_new_label(); | |
8776 | int l3 = gen_new_label(); | |
8777 | int l4 = gen_new_label(); | |
a7812ae4 | 8778 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
8779 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); |
8780 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
57951c27 | 8781 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); |
57951c27 AJ |
8782 | tcg_gen_br(l2); |
8783 | gen_set_label(l1); | |
57951c27 | 8784 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); |
57951c27 AJ |
8785 | gen_set_label(l2); |
8786 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
8787 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
57951c27 | 8788 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
57951c27 AJ |
8789 | tcg_gen_br(l4); |
8790 | gen_set_label(l3); | |
57951c27 | 8791 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
57951c27 | 8792 | gen_set_label(l4); |
a7812ae4 | 8793 | tcg_temp_free_i32(t0); |
57951c27 | 8794 | } |
e8eaa2c0 BS |
8795 | |
8796 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
8797 | { |
8798 | gen_evsel(ctx); | |
8799 | } | |
e8eaa2c0 BS |
8800 | |
8801 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
8802 | { |
8803 | gen_evsel(ctx); | |
8804 | } | |
e8eaa2c0 BS |
8805 | |
8806 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
8807 | { |
8808 | gen_evsel(ctx); | |
8809 | } | |
e8eaa2c0 BS |
8810 | |
8811 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
8812 | { |
8813 | gen_evsel(ctx); | |
8814 | } | |
0487d6a8 | 8815 | |
a0e13900 FC |
8816 | /* Multiply */ |
8817 | ||
8818 | static inline void gen_evmwumi(DisasContext *ctx) | |
8819 | { | |
8820 | TCGv_i64 t0, t1; | |
8821 | ||
8822 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8823 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8824 | return; |
8825 | } | |
8826 | ||
8827 | t0 = tcg_temp_new_i64(); | |
8828 | t1 = tcg_temp_new_i64(); | |
8829 | ||
8830 | /* t0 := rA; t1 := rB */ | |
a0e13900 | 8831 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
13b6a455 | 8832 | tcg_gen_ext32u_i64(t0, t0); |
a0e13900 | 8833 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
13b6a455 | 8834 | tcg_gen_ext32u_i64(t1, t1); |
a0e13900 FC |
8835 | |
8836 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
8837 | ||
8838 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
8839 | ||
8840 | tcg_temp_free_i64(t0); | |
8841 | tcg_temp_free_i64(t1); | |
8842 | } | |
8843 | ||
8844 | static inline void gen_evmwumia(DisasContext *ctx) | |
8845 | { | |
8846 | TCGv_i64 tmp; | |
8847 | ||
8848 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8849 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8850 | return; |
8851 | } | |
8852 | ||
8853 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
8854 | ||
8855 | tmp = tcg_temp_new_i64(); | |
8856 | ||
8857 | /* acc := rD */ | |
8858 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 8859 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8860 | tcg_temp_free_i64(tmp); |
8861 | } | |
8862 | ||
8863 | static inline void gen_evmwumiaa(DisasContext *ctx) | |
8864 | { | |
8865 | TCGv_i64 acc; | |
8866 | TCGv_i64 tmp; | |
8867 | ||
8868 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8869 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8870 | return; |
8871 | } | |
8872 | ||
8873 | gen_evmwumi(ctx); /* rD := rA * rB */ | |
8874 | ||
8875 | acc = tcg_temp_new_i64(); | |
8876 | tmp = tcg_temp_new_i64(); | |
8877 | ||
8878 | /* tmp := rD */ | |
8879 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
8880 | ||
8881 | /* Load acc */ | |
1328c2bf | 8882 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8883 | |
8884 | /* acc := tmp + acc */ | |
8885 | tcg_gen_add_i64(acc, acc, tmp); | |
8886 | ||
8887 | /* Store acc */ | |
1328c2bf | 8888 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8889 | |
8890 | /* rD := acc */ | |
8891 | gen_store_gpr64(rD(ctx->opcode), acc); | |
8892 | ||
8893 | tcg_temp_free_i64(acc); | |
8894 | tcg_temp_free_i64(tmp); | |
8895 | } | |
8896 | ||
8897 | static inline void gen_evmwsmi(DisasContext *ctx) | |
8898 | { | |
8899 | TCGv_i64 t0, t1; | |
8900 | ||
8901 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 8902 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
a0e13900 FC |
8903 | return; |
8904 | } | |
8905 | ||
8906 | t0 = tcg_temp_new_i64(); | |
8907 | t1 = tcg_temp_new_i64(); | |
8908 | ||
8909 | /* t0 := rA; t1 := rB */ | |
13b6a455 AG |
8910 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
8911 | tcg_gen_ext32s_i64(t0, t0); | |
8912 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
8913 | tcg_gen_ext32s_i64(t1, t1); | |
a0e13900 FC |
8914 | |
8915 | tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */ | |
8916 | ||
8917 | gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */ | |
8918 | ||
8919 | tcg_temp_free_i64(t0); | |
8920 | tcg_temp_free_i64(t1); | |
8921 | } | |
8922 | ||
8923 | static inline void gen_evmwsmia(DisasContext *ctx) | |
8924 | { | |
8925 | TCGv_i64 tmp; | |
8926 | ||
8927 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
8928 | ||
8929 | tmp = tcg_temp_new_i64(); | |
8930 | ||
8931 | /* acc := rD */ | |
8932 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
1328c2bf | 8933 | tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8934 | |
8935 | tcg_temp_free_i64(tmp); | |
8936 | } | |
8937 | ||
8938 | static inline void gen_evmwsmiaa(DisasContext *ctx) | |
8939 | { | |
8940 | TCGv_i64 acc = tcg_temp_new_i64(); | |
8941 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
8942 | ||
8943 | gen_evmwsmi(ctx); /* rD := rA * rB */ | |
8944 | ||
8945 | acc = tcg_temp_new_i64(); | |
8946 | tmp = tcg_temp_new_i64(); | |
8947 | ||
8948 | /* tmp := rD */ | |
8949 | gen_load_gpr64(tmp, rD(ctx->opcode)); | |
8950 | ||
8951 | /* Load acc */ | |
1328c2bf | 8952 | tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8953 | |
8954 | /* acc := tmp + acc */ | |
8955 | tcg_gen_add_i64(acc, acc, tmp); | |
8956 | ||
8957 | /* Store acc */ | |
1328c2bf | 8958 | tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); |
a0e13900 FC |
8959 | |
8960 | /* rD := acc */ | |
8961 | gen_store_gpr64(rD(ctx->opcode), acc); | |
8962 | ||
8963 | tcg_temp_free_i64(acc); | |
8964 | tcg_temp_free_i64(tmp); | |
8965 | } | |
8966 | ||
70560da7 FC |
8967 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// |
8968 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8969 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8970 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8971 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
8972 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
8973 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); //// | |
8974 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); // | |
8975 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE); | |
8976 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
8977 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8978 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8979 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8980 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8981 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
8982 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
8983 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); //// | |
8984 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8985 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8986 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE); | |
8987 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); //// | |
8988 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
8989 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); // | |
8990 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE); | |
8991 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8992 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); //// | |
8993 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
8994 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); //// | |
8995 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); //// | |
0487d6a8 | 8996 | |
6a6ae23f | 8997 | /* SPE load and stores */ |
636aa200 | 8998 | static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
8999 | { |
9000 | target_ulong uimm = rB(ctx->opcode); | |
9001 | ||
76db3ba4 | 9002 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 9003 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 9004 | } else { |
6a6ae23f | 9005 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
c791fe84 | 9006 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
9007 | tcg_gen_ext32u_tl(EA, EA); |
9008 | } | |
76db3ba4 | 9009 | } |
0487d6a8 | 9010 | } |
6a6ae23f | 9011 | |
636aa200 | 9012 | static inline void gen_op_evldd(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9013 | { |
6a6ae23f | 9014 | TCGv_i64 t0 = tcg_temp_new_i64(); |
76db3ba4 | 9015 | gen_qemu_ld64(ctx, t0, addr); |
13b6a455 | 9016 | gen_store_gpr64(rD(ctx->opcode), t0); |
6a6ae23f | 9017 | tcg_temp_free_i64(t0); |
0487d6a8 | 9018 | } |
6a6ae23f | 9019 | |
636aa200 | 9020 | static inline void gen_op_evldw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9021 | { |
76db3ba4 AJ |
9022 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
9023 | gen_addr_add(ctx, addr, addr, 4); | |
9024 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
0487d6a8 | 9025 | } |
6a6ae23f | 9026 | |
636aa200 | 9027 | static inline void gen_op_evldh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9028 | { |
9029 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9030 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 9031 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
9032 | gen_addr_add(ctx, addr, addr, 2); |
9033 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9034 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
9035 | gen_addr_add(ctx, addr, addr, 2); |
9036 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9037 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
9038 | gen_addr_add(ctx, addr, addr, 2); |
9039 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9040 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
6a6ae23f | 9041 | tcg_temp_free(t0); |
0487d6a8 JM |
9042 | } |
9043 | ||
636aa200 | 9044 | static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9045 | { |
9046 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9047 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
9048 | tcg_gen_shli_tl(t0, t0, 16); |
9049 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
9050 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f | 9051 | tcg_temp_free(t0); |
0487d6a8 JM |
9052 | } |
9053 | ||
636aa200 | 9054 | static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9055 | { |
9056 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9057 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
9058 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
9059 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f | 9060 | tcg_temp_free(t0); |
0487d6a8 JM |
9061 | } |
9062 | ||
636aa200 | 9063 | static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9064 | { |
9065 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9066 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
9067 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
9068 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f AJ |
9069 | tcg_temp_free(t0); |
9070 | } | |
9071 | ||
636aa200 | 9072 | static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9073 | { |
9074 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9075 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 9076 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
9077 | gen_addr_add(ctx, addr, addr, 2); |
9078 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 9079 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
6a6ae23f AJ |
9080 | tcg_temp_free(t0); |
9081 | } | |
9082 | ||
636aa200 | 9083 | static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9084 | { |
76db3ba4 AJ |
9085 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
9086 | gen_addr_add(ctx, addr, addr, 2); | |
9087 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
9088 | } |
9089 | ||
636aa200 | 9090 | static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9091 | { |
76db3ba4 AJ |
9092 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
9093 | gen_addr_add(ctx, addr, addr, 2); | |
9094 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
9095 | } |
9096 | ||
636aa200 | 9097 | static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9098 | { |
9099 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9100 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f AJ |
9101 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); |
9102 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
6a6ae23f AJ |
9103 | tcg_temp_free(t0); |
9104 | } | |
9105 | ||
636aa200 | 9106 | static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9107 | { |
9108 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 9109 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
9110 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
9111 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
9112 | gen_addr_add(ctx, addr, addr, 2); |
9113 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
9114 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
9115 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
6a6ae23f AJ |
9116 | tcg_temp_free(t0); |
9117 | } | |
9118 | ||
636aa200 | 9119 | static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9120 | { |
6a6ae23f | 9121 | TCGv_i64 t0 = tcg_temp_new_i64(); |
13b6a455 | 9122 | gen_load_gpr64(t0, rS(ctx->opcode)); |
76db3ba4 | 9123 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f | 9124 | tcg_temp_free_i64(t0); |
6a6ae23f AJ |
9125 | } |
9126 | ||
636aa200 | 9127 | static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9128 | { |
76db3ba4 | 9129 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
76db3ba4 AJ |
9130 | gen_addr_add(ctx, addr, addr, 4); |
9131 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
9132 | } |
9133 | ||
636aa200 | 9134 | static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9135 | { |
9136 | TCGv t0 = tcg_temp_new(); | |
6a6ae23f | 9137 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); |
76db3ba4 AJ |
9138 | gen_qemu_st16(ctx, t0, addr); |
9139 | gen_addr_add(ctx, addr, addr, 2); | |
76db3ba4 | 9140 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
76db3ba4 | 9141 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 9142 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 9143 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 9144 | tcg_temp_free(t0); |
76db3ba4 AJ |
9145 | gen_addr_add(ctx, addr, addr, 2); |
9146 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
9147 | } |
9148 | ||
636aa200 | 9149 | static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) |
6a6ae23f AJ |
9150 | { |
9151 | TCGv t0 = tcg_temp_new(); | |
6a6ae23f | 9152 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); |
76db3ba4 AJ |
9153 | gen_qemu_st16(ctx, t0, addr); |
9154 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 9155 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 9156 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
9157 | tcg_temp_free(t0); |
9158 | } | |
9159 | ||
636aa200 | 9160 | static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9161 | { |
76db3ba4 | 9162 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
76db3ba4 AJ |
9163 | gen_addr_add(ctx, addr, addr, 2); |
9164 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
9165 | } |
9166 | ||
636aa200 | 9167 | static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9168 | { |
76db3ba4 | 9169 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
9170 | } |
9171 | ||
636aa200 | 9172 | static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) |
6a6ae23f | 9173 | { |
76db3ba4 | 9174 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
9175 | } |
9176 | ||
9177 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef | 9178 | static void glue(gen_, name)(DisasContext *ctx) \ |
6a6ae23f AJ |
9179 | { \ |
9180 | TCGv t0; \ | |
9181 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 9182 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
6a6ae23f AJ |
9183 | return; \ |
9184 | } \ | |
76db3ba4 | 9185 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
9186 | t0 = tcg_temp_new(); \ |
9187 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 9188 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 9189 | } else { \ |
76db3ba4 | 9190 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
9191 | } \ |
9192 | gen_op_##name(ctx, t0); \ | |
9193 | tcg_temp_free(t0); \ | |
9194 | } | |
9195 | ||
9196 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
9197 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
9198 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
9199 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
9200 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
9201 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
9202 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
9203 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
9204 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
9205 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
9206 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
9207 | ||
9208 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
9209 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
9210 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
9211 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
9212 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
9213 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
9214 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
9215 | |
9216 | /* Multiply and add - TODO */ | |
9217 | #if 0 | |
70560da7 FC |
9218 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);// |
9219 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9220 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9221 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9222 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9223 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9224 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9225 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9226 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9227 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9228 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE); | |
9229 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9230 | ||
9231 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9232 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9233 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
9234 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9235 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9236 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9237 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9238 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE); | |
9239 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE); | |
9240 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9241 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9242 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9243 | ||
9244 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9245 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9246 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9247 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE); | |
9248 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE); | |
9249 | ||
9250 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9251 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9252 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9253 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9254 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9255 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9256 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9257 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9258 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9259 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9260 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE); | |
9261 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9262 | ||
9263 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
9264 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE); | |
9265 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9266 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9267 | ||
9268 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9269 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9270 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9271 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9272 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9273 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9274 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9275 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9276 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9277 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9278 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE); | |
9279 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9280 | ||
9281 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
9282 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
9283 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
9284 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE); | |
9285 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE); | |
0487d6a8 JM |
9286 | #endif |
9287 | ||
9288 | /*** SPE floating-point extension ***/ | |
1c97856d | 9289 | #define GEN_SPEFPUOP_CONV_32_32(name) \ |
636aa200 | 9290 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9291 | { \ |
9292 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
9293 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
13b6a455 AG |
9294 | gen_helper_##name(t0, cpu_env, t0); \ |
9295 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
1c97856d | 9296 | tcg_temp_free_i32(t0); \ |
57951c27 | 9297 | } |
1c97856d | 9298 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
636aa200 | 9299 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9300 | { \ |
9301 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
13b6a455 | 9302 | TCGv_i32 t1 = tcg_temp_new_i32(); \ |
1c97856d | 9303 | gen_load_gpr64(t0, rB(ctx->opcode)); \ |
13b6a455 AG |
9304 | gen_helper_##name(t1, cpu_env, t0); \ |
9305 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \ | |
1c97856d | 9306 | tcg_temp_free_i64(t0); \ |
13b6a455 | 9307 | tcg_temp_free_i32(t1); \ |
1c97856d AJ |
9308 | } |
9309 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
636aa200 | 9310 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9311 | { \ |
9312 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
13b6a455 AG |
9313 | TCGv_i32 t1 = tcg_temp_new_i32(); \ |
9314 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
9315 | gen_helper_##name(t0, cpu_env, t1); \ | |
1c97856d AJ |
9316 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9317 | tcg_temp_free_i64(t0); \ | |
13b6a455 | 9318 | tcg_temp_free_i32(t1); \ |
1c97856d AJ |
9319 | } |
9320 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
636aa200 | 9321 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9322 | { \ |
9323 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
9324 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8e703949 | 9325 | gen_helper_##name(t0, cpu_env, t0); \ |
1c97856d AJ |
9326 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9327 | tcg_temp_free_i64(t0); \ | |
9328 | } | |
9329 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
636aa200 | 9330 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 9331 | { \ |
13b6a455 | 9332 | TCGv_i32 t0, t1; \ |
1c97856d | 9333 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 9334 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9335 | return; \ |
9336 | } \ | |
13b6a455 AG |
9337 | t0 = tcg_temp_new_i32(); \ |
9338 | t1 = tcg_temp_new_i32(); \ | |
9339 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
9340 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
9341 | gen_helper_##name(t0, cpu_env, t0, t1); \ | |
9342 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ | |
9343 | \ | |
9344 | tcg_temp_free_i32(t0); \ | |
9345 | tcg_temp_free_i32(t1); \ | |
1c97856d AJ |
9346 | } |
9347 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
636aa200 | 9348 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9349 | { \ |
9350 | TCGv_i64 t0, t1; \ | |
9351 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 9352 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9353 | return; \ |
9354 | } \ | |
9355 | t0 = tcg_temp_new_i64(); \ | |
9356 | t1 = tcg_temp_new_i64(); \ | |
9357 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
9358 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 9359 | gen_helper_##name(t0, cpu_env, t0, t1); \ |
1c97856d AJ |
9360 | gen_store_gpr64(rD(ctx->opcode), t0); \ |
9361 | tcg_temp_free_i64(t0); \ | |
9362 | tcg_temp_free_i64(t1); \ | |
9363 | } | |
9364 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
636aa200 | 9365 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d | 9366 | { \ |
13b6a455 | 9367 | TCGv_i32 t0, t1; \ |
1c97856d | 9368 | if (unlikely(!ctx->spe_enabled)) { \ |
27a69bb0 | 9369 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9370 | return; \ |
9371 | } \ | |
13b6a455 AG |
9372 | t0 = tcg_temp_new_i32(); \ |
9373 | t1 = tcg_temp_new_i32(); \ | |
9374 | \ | |
9375 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
9376 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
9377 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ | |
9378 | \ | |
9379 | tcg_temp_free_i32(t0); \ | |
9380 | tcg_temp_free_i32(t1); \ | |
1c97856d AJ |
9381 | } |
9382 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
636aa200 | 9383 | static inline void gen_##name(DisasContext *ctx) \ |
1c97856d AJ |
9384 | { \ |
9385 | TCGv_i64 t0, t1; \ | |
9386 | if (unlikely(!ctx->spe_enabled)) { \ | |
27a69bb0 | 9387 | gen_exception(ctx, POWERPC_EXCP_SPEU); \ |
1c97856d AJ |
9388 | return; \ |
9389 | } \ | |
9390 | t0 = tcg_temp_new_i64(); \ | |
9391 | t1 = tcg_temp_new_i64(); \ | |
9392 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
9393 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8e703949 | 9394 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \ |
1c97856d AJ |
9395 | tcg_temp_free_i64(t0); \ |
9396 | tcg_temp_free_i64(t1); \ | |
9397 | } | |
57951c27 | 9398 | |
0487d6a8 JM |
9399 | /* Single precision floating-point vectors operations */ |
9400 | /* Arithmetic */ | |
1c97856d AJ |
9401 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
9402 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
9403 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
9404 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
636aa200 | 9405 | static inline void gen_evfsabs(DisasContext *ctx) |
1c97856d AJ |
9406 | { |
9407 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9408 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9409 | return; |
9410 | } | |
13b6a455 AG |
9411 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
9412 | ~0x80000000); | |
9413 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], | |
9414 | ~0x80000000); | |
1c97856d | 9415 | } |
636aa200 | 9416 | static inline void gen_evfsnabs(DisasContext *ctx) |
1c97856d AJ |
9417 | { |
9418 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9419 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9420 | return; |
9421 | } | |
13b6a455 AG |
9422 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
9423 | 0x80000000); | |
9424 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], | |
9425 | 0x80000000); | |
1c97856d | 9426 | } |
636aa200 | 9427 | static inline void gen_evfsneg(DisasContext *ctx) |
1c97856d AJ |
9428 | { |
9429 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9430 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9431 | return; |
9432 | } | |
13b6a455 AG |
9433 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
9434 | 0x80000000); | |
9435 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], | |
9436 | 0x80000000); | |
1c97856d AJ |
9437 | } |
9438 | ||
0487d6a8 | 9439 | /* Conversion */ |
1c97856d AJ |
9440 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
9441 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
9442 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
9443 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
9444 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
9445 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
9446 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
9447 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
9448 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
9449 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
9450 | ||
0487d6a8 | 9451 | /* Comparison */ |
1c97856d AJ |
9452 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
9453 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
9454 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
9455 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
9456 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
9457 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
9458 | |
9459 | /* Opcodes definitions */ | |
70560da7 FC |
9460 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9461 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
9462 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9463 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
9464 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9465 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9466 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9467 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9468 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9469 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9470 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9471 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9472 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9473 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
9474 | |
9475 | /* Single precision floating-point operations */ | |
9476 | /* Arithmetic */ | |
1c97856d AJ |
9477 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
9478 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
9479 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
9480 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
636aa200 | 9481 | static inline void gen_efsabs(DisasContext *ctx) |
1c97856d AJ |
9482 | { |
9483 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9484 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9485 | return; |
9486 | } | |
6d5c34fa | 9487 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); |
1c97856d | 9488 | } |
636aa200 | 9489 | static inline void gen_efsnabs(DisasContext *ctx) |
1c97856d AJ |
9490 | { |
9491 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9492 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9493 | return; |
9494 | } | |
6d5c34fa | 9495 | tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d | 9496 | } |
636aa200 | 9497 | static inline void gen_efsneg(DisasContext *ctx) |
1c97856d AJ |
9498 | { |
9499 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9500 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9501 | return; |
9502 | } | |
6d5c34fa | 9503 | tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); |
1c97856d AJ |
9504 | } |
9505 | ||
0487d6a8 | 9506 | /* Conversion */ |
1c97856d AJ |
9507 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
9508 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
9509 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
9510 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
9511 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
9512 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
9513 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
9514 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
9515 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
9516 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
9517 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
9518 | ||
0487d6a8 | 9519 | /* Comparison */ |
1c97856d AJ |
9520 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
9521 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
9522 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
9523 | GEN_SPEFPUOP_COMP_32(efststgt); | |
9524 | GEN_SPEFPUOP_COMP_32(efststlt); | |
9525 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
9526 | |
9527 | /* Opcodes definitions */ | |
70560da7 FC |
9528 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // |
9529 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); // | |
9530 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9531 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); // | |
9532 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9533 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); // | |
9534 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9535 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9536 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9537 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); // | |
9538 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9539 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
9540 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); // | |
9541 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
9542 | |
9543 | /* Double precision floating-point operations */ | |
9544 | /* Arithmetic */ | |
1c97856d AJ |
9545 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
9546 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
9547 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
9548 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
636aa200 | 9549 | static inline void gen_efdabs(DisasContext *ctx) |
1c97856d AJ |
9550 | { |
9551 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9552 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9553 | return; |
9554 | } | |
6d5c34fa | 9555 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
13b6a455 AG |
9556 | tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], |
9557 | ~0x80000000); | |
1c97856d | 9558 | } |
636aa200 | 9559 | static inline void gen_efdnabs(DisasContext *ctx) |
1c97856d AJ |
9560 | { |
9561 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9562 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9563 | return; |
9564 | } | |
6d5c34fa | 9565 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
13b6a455 AG |
9566 | tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], |
9567 | 0x80000000); | |
1c97856d | 9568 | } |
636aa200 | 9569 | static inline void gen_efdneg(DisasContext *ctx) |
1c97856d AJ |
9570 | { |
9571 | if (unlikely(!ctx->spe_enabled)) { | |
27a69bb0 | 9572 | gen_exception(ctx, POWERPC_EXCP_SPEU); |
1c97856d AJ |
9573 | return; |
9574 | } | |
6d5c34fa | 9575 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
13b6a455 AG |
9576 | tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], |
9577 | 0x80000000); | |
1c97856d AJ |
9578 | } |
9579 | ||
0487d6a8 | 9580 | /* Conversion */ |
1c97856d AJ |
9581 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
9582 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
9583 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
9584 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
9585 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
9586 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
9587 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
9588 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
9589 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
9590 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
9591 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
9592 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
9593 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
9594 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
9595 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 9596 | |
0487d6a8 | 9597 | /* Comparison */ |
1c97856d AJ |
9598 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
9599 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
9600 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
9601 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
9602 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
9603 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
9604 | |
9605 | /* Opcodes definitions */ | |
70560da7 FC |
9606 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // |
9607 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9608 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); // | |
9609 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9610 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); // | |
9611 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9612 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
9613 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); // | |
9614 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9615 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9616 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9617 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); // | |
9618 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9619 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
9620 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); // | |
9621 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); // | |
0487d6a8 | 9622 | |
c227f099 | 9623 | static opcode_t opcodes[] = { |
5c55ff99 BS |
9624 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
9625 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
9626 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
9627 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
9628 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
fcfda20f | 9629 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
5c55ff99 BS |
9630 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
9631 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9632 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9633 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9634 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9635 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), | |
9636 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
9637 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
9638 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
9639 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9640 | #if defined(TARGET_PPC64) | |
9641 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
9642 | #endif | |
9643 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
9644 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
9645 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9646 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9647 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9648 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
9649 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), | |
9650 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
9651 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9652 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9653 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9654 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 9655 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 9656 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 9657 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 9658 | #if defined(TARGET_PPC64) |
eaabeef2 | 9659 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 9660 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
725bcec2 | 9661 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 9662 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
9663 | #endif |
9664 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9665 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9666 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9667 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
9668 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
9669 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
9670 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
9671 | #if defined(TARGET_PPC64) | |
9672 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
9673 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
9674 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
9675 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
9676 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
9677 | #endif | |
9678 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES), | |
9679 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
9680 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT), | |
9681 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT), | |
9682 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT), | |
bf45a2e6 | 9683 | GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), |
5c55ff99 | 9684 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), |
bf45a2e6 AJ |
9685 | GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), |
9686 | GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), | |
f0332888 | 9687 | GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), |
097ec5d8 TM |
9688 | GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207), |
9689 | GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207), | |
5c55ff99 BS |
9690 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), |
9691 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), | |
9692 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT), | |
9693 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT), | |
7d08d856 AJ |
9694 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT), |
9695 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT), | |
5c55ff99 BS |
9696 | #if defined(TARGET_PPC64) |
9697 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9698 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
9699 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9700 | #endif | |
9701 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9702 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
9703 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
9704 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
9705 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
9706 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
9707 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
9708 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
5c77a786 TM |
9709 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9710 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 9711 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
587c51f7 TM |
9712 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
9713 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
9714 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
9715 | #if defined(TARGET_PPC64) | |
f844c817 | 9716 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 9717 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 9718 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 9719 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
9720 | #endif |
9721 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
9722 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
9723 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9724 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9725 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
9726 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
52a4984d | 9727 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
9728 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
9729 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
9730 | #if defined(TARGET_PPC64) | |
9731 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
9732 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), | |
9733 | #endif | |
9734 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
9735 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
9736 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
9737 | #if defined(TARGET_PPC64) | |
9738 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
9739 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
9740 | #endif | |
9741 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
9742 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
9743 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
9744 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
9745 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
9746 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
9747 | #if defined(TARGET_PPC64) | |
9748 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
9749 | #endif | |
9750 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC), | |
9751 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC), | |
9752 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), | |
9753 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
9754 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
3f34cf91 CLG |
9755 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
9756 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), | |
4d09d529 | 9757 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 9758 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
9759 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
9760 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
9761 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
9762 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
9763 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
9764 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
9765 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
9766 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
9767 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
9768 | #if defined(TARGET_PPC64) | |
9769 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
9770 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
9771 | PPC_SEGMENT_64B), | |
9772 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
9773 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
9774 | PPC_SEGMENT_64B), | |
efdef95f DG |
9775 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
9776 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
9777 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
5c55ff99 BS |
9778 | #endif |
9779 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
9780 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE), | |
9781 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE), | |
9782 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), | |
9783 | #if defined(TARGET_PPC64) | |
9784 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI), | |
9785 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), | |
9786 | #endif | |
9787 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
9788 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
9789 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
9790 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
9791 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
9792 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
9793 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
9794 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
9795 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
9796 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
9797 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
9798 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
9799 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
9800 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
9801 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
9802 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
9803 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
9804 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
9805 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
9806 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
9807 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
9808 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
9809 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
9810 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
9811 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
9812 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
9813 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
9814 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
9815 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
9816 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
9817 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
9818 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
9819 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
9820 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
9821 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
9822 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
9823 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
9824 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
9825 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
9826 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
9827 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
9828 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
9829 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
9830 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
9831 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
9832 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
9833 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
9834 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
9835 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
9836 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9837 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9838 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
9839 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
9840 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9841 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
9842 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
9843 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
9844 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
9845 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
9846 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
9847 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
9848 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
9849 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
9850 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
9851 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
9852 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
9853 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
9854 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
9855 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
9856 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
9857 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 9858 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
9859 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
9860 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
9861 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
9862 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
9863 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
9864 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
9865 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
9866 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
9867 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
9868 | PPC_NONE, PPC2_BOOKE206), | |
9869 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
9870 | PPC_NONE, PPC2_BOOKE206), | |
9871 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
9872 | PPC_NONE, PPC2_BOOKE206), | |
9873 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
9874 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
9875 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
9876 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
9877 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
9878 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
9879 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
9880 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 9881 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 9882 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 9883 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
9884 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
9885 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 9886 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
9887 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
9888 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
9889 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
9890 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
9891 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
9892 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
5c55ff99 BS |
9893 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
9894 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE), | |
9895 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE), | |
9896 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE), | |
9897 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE), | |
9898 | ||
9899 | #undef GEN_INT_ARITH_ADD | |
9900 | #undef GEN_INT_ARITH_ADD_CONST | |
9901 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
9902 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
9903 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
9904 | add_ca, compute_ca, compute_ov) \ | |
9905 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
9906 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
9907 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
9908 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
9909 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
9910 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
9911 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
9912 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
9913 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
9914 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
9915 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
9916 | ||
9917 | #undef GEN_INT_ARITH_DIVW | |
9918 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
9919 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
9920 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
9921 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
9922 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
9923 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
9924 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9925 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
9926 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9927 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
5c55ff99 BS |
9928 | |
9929 | #if defined(TARGET_PPC64) | |
9930 | #undef GEN_INT_ARITH_DIVD | |
9931 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
9932 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
9933 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
9934 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
9935 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
9936 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
9937 | ||
98d1eb27 TM |
9938 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9939 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
9940 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
9941 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
98d1eb27 | 9942 | |
5c55ff99 BS |
9943 | #undef GEN_INT_ARITH_MUL_HELPER |
9944 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
9945 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
9946 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
9947 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
9948 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
9949 | #endif | |
9950 | ||
9951 | #undef GEN_INT_ARITH_SUBF | |
9952 | #undef GEN_INT_ARITH_SUBF_CONST | |
9953 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
9954 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
9955 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
9956 | add_ca, compute_ca, compute_ov) \ | |
9957 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
9958 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
9959 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
9960 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
9961 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
9962 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
9963 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
9964 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
9965 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
9966 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
9967 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
9968 | ||
9969 | #undef GEN_LOGICAL1 | |
9970 | #undef GEN_LOGICAL2 | |
9971 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
9972 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
9973 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
9974 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
9975 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
9976 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
9977 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
9978 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
9979 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
9980 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
9981 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
9982 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
9983 | #if defined(TARGET_PPC64) | |
9984 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
9985 | #endif | |
9986 | ||
9987 | #if defined(TARGET_PPC64) | |
9988 | #undef GEN_PPC64_R2 | |
9989 | #undef GEN_PPC64_R4 | |
9990 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
9991 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
9992 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
9993 | PPC_64B) | |
9994 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
9995 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
9996 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
9997 | PPC_64B), \ | |
9998 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
9999 | PPC_64B), \ | |
10000 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
10001 | PPC_64B) | |
10002 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
10003 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
10004 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
10005 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
10006 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
10007 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
10008 | #endif | |
10009 | ||
10010 | #undef _GEN_FLOAT_ACB | |
10011 | #undef GEN_FLOAT_ACB | |
10012 | #undef _GEN_FLOAT_AB | |
10013 | #undef GEN_FLOAT_AB | |
10014 | #undef _GEN_FLOAT_AC | |
10015 | #undef GEN_FLOAT_AC | |
10016 | #undef GEN_FLOAT_B | |
10017 | #undef GEN_FLOAT_BS | |
10018 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ | |
10019 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) | |
10020 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ | |
10021 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \ | |
10022 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type) | |
10023 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
10024 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
10025 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ | |
10026 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
10027 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
10028 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ | |
10029 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) | |
10030 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ | |
10031 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \ | |
10032 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type) | |
10033 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ | |
10034 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) | |
10035 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ | |
10036 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) | |
10037 | ||
10038 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT), | |
10039 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT), | |
10040 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT), | |
10041 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT), | |
10042 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES), | |
10043 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE), | |
10044 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL), | |
10045 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT), | |
10046 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT), | |
10047 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT), | |
10048 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT), | |
10049 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT), | |
da29cb7b | 10050 | GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206), |
6d41d146 | 10051 | GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206), |
5c55ff99 | 10052 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT), |
fab7fe42 | 10053 | GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 | 10054 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT), |
fab7fe42 | 10055 | GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 BS |
10056 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT), |
10057 | #if defined(TARGET_PPC64) | |
10058 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B), | |
28288b48 TM |
10059 | GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
10060 | GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), | |
10061 | GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206), | |
5c55ff99 | 10062 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B), |
fab7fe42 | 10063 | GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 | 10064 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B), |
fab7fe42 | 10065 | GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206), |
5c55ff99 BS |
10066 | #endif |
10067 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT), | |
10068 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT), | |
10069 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT), | |
10070 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), | |
5c55ff99 BS |
10071 | |
10072 | #undef GEN_LD | |
10073 | #undef GEN_LDU | |
10074 | #undef GEN_LDUX | |
cd6e9320 | 10075 | #undef GEN_LDX_E |
5c55ff99 BS |
10076 | #undef GEN_LDS |
10077 | #define GEN_LD(name, ldop, opc, type) \ | |
10078 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10079 | #define GEN_LDU(name, ldop, opc, type) \ | |
10080 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10081 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
10082 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
10083 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \ |
10084 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
10085 | #define GEN_LDS(name, ldop, op, type) \ |
10086 | GEN_LD(name, ldop, op | 0x20, type) \ | |
10087 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
10088 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
10089 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
10090 | ||
10091 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
10092 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
10093 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
10094 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
10095 | #if defined(TARGET_PPC64) | |
10096 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
10097 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
10098 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B) | |
10099 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B) | |
cd6e9320 | 10100 | GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
10101 | #endif |
10102 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
10103 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
10104 | ||
10105 | #undef GEN_ST | |
10106 | #undef GEN_STU | |
10107 | #undef GEN_STUX | |
cd6e9320 | 10108 | #undef GEN_STX_E |
5c55ff99 BS |
10109 | #undef GEN_STS |
10110 | #define GEN_ST(name, stop, opc, type) \ | |
10111 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10112 | #define GEN_STU(name, stop, opc, type) \ | |
10113 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10114 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
10115 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
cd6e9320 TH |
10116 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \ |
10117 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), | |
5c55ff99 BS |
10118 | #define GEN_STS(name, stop, op, type) \ |
10119 | GEN_ST(name, stop, op | 0x20, type) \ | |
10120 | GEN_STU(name, stop, op | 0x21, type) \ | |
10121 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
10122 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
10123 | ||
10124 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
10125 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
10126 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
10127 | #if defined(TARGET_PPC64) | |
10128 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B) | |
10129 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B) | |
cd6e9320 | 10130 | GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX) |
5c55ff99 BS |
10131 | #endif |
10132 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
10133 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
10134 | ||
10135 | #undef GEN_LDF | |
10136 | #undef GEN_LDUF | |
10137 | #undef GEN_LDUXF | |
10138 | #undef GEN_LDXF | |
10139 | #undef GEN_LDFS | |
10140 | #define GEN_LDF(name, ldop, opc, type) \ | |
10141 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10142 | #define GEN_LDUF(name, ldop, opc, type) \ | |
10143 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10144 | #define GEN_LDUXF(name, ldop, opc, type) \ | |
10145 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
10146 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ | |
10147 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
10148 | #define GEN_LDFS(name, ldop, op, type) \ | |
10149 | GEN_LDF(name, ldop, op | 0x20, type) \ | |
10150 | GEN_LDUF(name, ldop, op | 0x21, type) \ | |
10151 | GEN_LDUXF(name, ldop, op | 0x01, type) \ | |
10152 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
10153 | ||
10154 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) | |
10155 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) | |
199f830d | 10156 | GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), |
66c3e328 | 10157 | GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206), |
05050ee8 AJ |
10158 | GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
10159 | GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
10160 | |
10161 | #undef GEN_STF | |
10162 | #undef GEN_STUF | |
10163 | #undef GEN_STUXF | |
10164 | #undef GEN_STXF | |
10165 | #undef GEN_STFS | |
10166 | #define GEN_STF(name, stop, opc, type) \ | |
10167 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
10168 | #define GEN_STUF(name, stop, opc, type) \ | |
10169 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
10170 | #define GEN_STUXF(name, stop, opc, type) \ | |
10171 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), | |
10172 | #define GEN_STXF(name, stop, opc2, opc3, type) \ | |
10173 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), | |
10174 | #define GEN_STFS(name, stop, op, type) \ | |
10175 | GEN_STF(name, stop, op | 0x20, type) \ | |
10176 | GEN_STUF(name, stop, op | 0x21, type) \ | |
10177 | GEN_STUXF(name, stop, op | 0x01, type) \ | |
10178 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
10179 | ||
10180 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT) | |
10181 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT) | |
10182 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX) | |
44bc0c4d AJ |
10183 | GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205), |
10184 | GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205), | |
5c55ff99 BS |
10185 | |
10186 | #undef GEN_CRLOGIC | |
10187 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
10188 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
10189 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
10190 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
10191 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
10192 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
10193 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
10194 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
10195 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
10196 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
10197 | ||
10198 | #undef GEN_MAC_HANDLER | |
10199 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
10200 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
10201 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
10202 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
10203 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
10204 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
10205 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
10206 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
10207 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
10208 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
10209 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
10210 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
10211 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
10212 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
10213 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
10214 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
10215 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
10216 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
10217 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
10218 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
10219 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
10220 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
10221 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
10222 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
10223 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
10224 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
10225 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
10226 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
10227 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
10228 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
10229 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
10230 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
10231 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
10232 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
10233 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
10234 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
10235 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
10236 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
10237 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
10238 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
10239 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
10240 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
10241 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
10242 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
10243 | ||
10244 | #undef GEN_VR_LDX | |
10245 | #undef GEN_VR_STX | |
10246 | #undef GEN_VR_LVE | |
10247 | #undef GEN_VR_STVE | |
10248 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
10249 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10250 | #define GEN_VR_STX(name, opc2, opc3) \ | |
10251 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10252 | #define GEN_VR_LVE(name, opc2, opc3) \ | |
10253 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10254 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
10255 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) | |
10256 | GEN_VR_LDX(lvx, 0x07, 0x03), | |
10257 | GEN_VR_LDX(lvxl, 0x07, 0x0B), | |
10258 | GEN_VR_LVE(bx, 0x07, 0x00), | |
10259 | GEN_VR_LVE(hx, 0x07, 0x01), | |
10260 | GEN_VR_LVE(wx, 0x07, 0x02), | |
10261 | GEN_VR_STX(svx, 0x07, 0x07), | |
10262 | GEN_VR_STX(svxl, 0x07, 0x0F), | |
10263 | GEN_VR_STVE(bx, 0x07, 0x04), | |
10264 | GEN_VR_STVE(hx, 0x07, 0x05), | |
10265 | GEN_VR_STVE(wx, 0x07, 0x06), | |
10266 | ||
10267 | #undef GEN_VX_LOGICAL | |
10268 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
10269 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
111c5f54 TM |
10270 | |
10271 | #undef GEN_VX_LOGICAL_207 | |
10272 | #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \ | |
10273 | GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) | |
10274 | ||
5c55ff99 BS |
10275 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16), |
10276 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17), | |
10277 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18), | |
10278 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19), | |
10279 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20), | |
111c5f54 TM |
10280 | GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26), |
10281 | GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22), | |
10282 | GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21), | |
5c55ff99 BS |
10283 | |
10284 | #undef GEN_VXFORM | |
10285 | #define GEN_VXFORM(name, opc2, opc3) \ | |
10286 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
50f5fc0c TM |
10287 | |
10288 | #undef GEN_VXFORM_207 | |
10289 | #define GEN_VXFORM_207(name, opc2, opc3) \ | |
10290 | GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207) | |
10291 | ||
5dffff5a TM |
10292 | #undef GEN_VXFORM_DUAL |
10293 | #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ | |
10294 | GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) | |
10295 | ||
a737d3eb TM |
10296 | #undef GEN_VXRFORM_DUAL |
10297 | #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \ | |
10298 | GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \ | |
10299 | GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1), | |
10300 | ||
5c55ff99 BS |
10301 | GEN_VXFORM(vaddubm, 0, 0), |
10302 | GEN_VXFORM(vadduhm, 0, 1), | |
10303 | GEN_VXFORM(vadduwm, 0, 2), | |
56eabc75 | 10304 | GEN_VXFORM_207(vaddudm, 0, 3), |
e8f7b27b TM |
10305 | GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE), |
10306 | GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE), | |
5c55ff99 | 10307 | GEN_VXFORM(vsubuwm, 0, 18), |
56eabc75 | 10308 | GEN_VXFORM_207(vsubudm, 0, 19), |
5c55ff99 BS |
10309 | GEN_VXFORM(vmaxub, 1, 0), |
10310 | GEN_VXFORM(vmaxuh, 1, 1), | |
10311 | GEN_VXFORM(vmaxuw, 1, 2), | |
8203e31b | 10312 | GEN_VXFORM_207(vmaxud, 1, 3), |
5c55ff99 BS |
10313 | GEN_VXFORM(vmaxsb, 1, 4), |
10314 | GEN_VXFORM(vmaxsh, 1, 5), | |
10315 | GEN_VXFORM(vmaxsw, 1, 6), | |
8203e31b | 10316 | GEN_VXFORM_207(vmaxsd, 1, 7), |
5c55ff99 BS |
10317 | GEN_VXFORM(vminub, 1, 8), |
10318 | GEN_VXFORM(vminuh, 1, 9), | |
10319 | GEN_VXFORM(vminuw, 1, 10), | |
8203e31b | 10320 | GEN_VXFORM_207(vminud, 1, 11), |
5c55ff99 BS |
10321 | GEN_VXFORM(vminsb, 1, 12), |
10322 | GEN_VXFORM(vminsh, 1, 13), | |
10323 | GEN_VXFORM(vminsw, 1, 14), | |
8203e31b | 10324 | GEN_VXFORM_207(vminsd, 1, 15), |
5c55ff99 BS |
10325 | GEN_VXFORM(vavgub, 1, 16), |
10326 | GEN_VXFORM(vavguh, 1, 17), | |
10327 | GEN_VXFORM(vavguw, 1, 18), | |
10328 | GEN_VXFORM(vavgsb, 1, 20), | |
10329 | GEN_VXFORM(vavgsh, 1, 21), | |
10330 | GEN_VXFORM(vavgsw, 1, 22), | |
10331 | GEN_VXFORM(vmrghb, 6, 0), | |
10332 | GEN_VXFORM(vmrghh, 6, 1), | |
10333 | GEN_VXFORM(vmrghw, 6, 2), | |
10334 | GEN_VXFORM(vmrglb, 6, 4), | |
10335 | GEN_VXFORM(vmrglh, 6, 5), | |
10336 | GEN_VXFORM(vmrglw, 6, 6), | |
e0ffe77f TM |
10337 | GEN_VXFORM_207(vmrgew, 6, 30), |
10338 | GEN_VXFORM_207(vmrgow, 6, 26), | |
5c55ff99 BS |
10339 | GEN_VXFORM(vmuloub, 4, 0), |
10340 | GEN_VXFORM(vmulouh, 4, 1), | |
953f0f58 | 10341 | GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE), |
5c55ff99 BS |
10342 | GEN_VXFORM(vmulosb, 4, 4), |
10343 | GEN_VXFORM(vmulosh, 4, 5), | |
63be0936 | 10344 | GEN_VXFORM_207(vmulosw, 4, 6), |
5c55ff99 BS |
10345 | GEN_VXFORM(vmuleub, 4, 8), |
10346 | GEN_VXFORM(vmuleuh, 4, 9), | |
63be0936 | 10347 | GEN_VXFORM_207(vmuleuw, 4, 10), |
5c55ff99 BS |
10348 | GEN_VXFORM(vmulesb, 4, 12), |
10349 | GEN_VXFORM(vmulesh, 4, 13), | |
63be0936 | 10350 | GEN_VXFORM_207(vmulesw, 4, 14), |
5c55ff99 BS |
10351 | GEN_VXFORM(vslb, 2, 4), |
10352 | GEN_VXFORM(vslh, 2, 5), | |
10353 | GEN_VXFORM(vslw, 2, 6), | |
2fdf78e6 | 10354 | GEN_VXFORM_207(vsld, 2, 23), |
5c55ff99 BS |
10355 | GEN_VXFORM(vsrb, 2, 8), |
10356 | GEN_VXFORM(vsrh, 2, 9), | |
10357 | GEN_VXFORM(vsrw, 2, 10), | |
2fdf78e6 | 10358 | GEN_VXFORM_207(vsrd, 2, 27), |
5c55ff99 BS |
10359 | GEN_VXFORM(vsrab, 2, 12), |
10360 | GEN_VXFORM(vsrah, 2, 13), | |
10361 | GEN_VXFORM(vsraw, 2, 14), | |
2fdf78e6 | 10362 | GEN_VXFORM_207(vsrad, 2, 15), |
5c55ff99 BS |
10363 | GEN_VXFORM(vslo, 6, 16), |
10364 | GEN_VXFORM(vsro, 6, 17), | |
10365 | GEN_VXFORM(vaddcuw, 0, 6), | |
10366 | GEN_VXFORM(vsubcuw, 0, 22), | |
10367 | GEN_VXFORM(vaddubs, 0, 8), | |
10368 | GEN_VXFORM(vadduhs, 0, 9), | |
10369 | GEN_VXFORM(vadduws, 0, 10), | |
10370 | GEN_VXFORM(vaddsbs, 0, 12), | |
10371 | GEN_VXFORM(vaddshs, 0, 13), | |
10372 | GEN_VXFORM(vaddsws, 0, 14), | |
e8f7b27b TM |
10373 | GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE), |
10374 | GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE), | |
5c55ff99 BS |
10375 | GEN_VXFORM(vsubuws, 0, 26), |
10376 | GEN_VXFORM(vsubsbs, 0, 28), | |
10377 | GEN_VXFORM(vsubshs, 0, 29), | |
10378 | GEN_VXFORM(vsubsws, 0, 30), | |
b41da4eb TM |
10379 | GEN_VXFORM_207(vadduqm, 0, 4), |
10380 | GEN_VXFORM_207(vaddcuq, 0, 5), | |
10381 | GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), | |
10382 | GEN_VXFORM_207(vsubuqm, 0, 20), | |
10383 | GEN_VXFORM_207(vsubcuq, 0, 21), | |
10384 | GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), | |
5c55ff99 BS |
10385 | GEN_VXFORM(vrlb, 2, 0), |
10386 | GEN_VXFORM(vrlh, 2, 1), | |
10387 | GEN_VXFORM(vrlw, 2, 2), | |
2fdf78e6 | 10388 | GEN_VXFORM_207(vrld, 2, 3), |
5c55ff99 BS |
10389 | GEN_VXFORM(vsl, 2, 7), |
10390 | GEN_VXFORM(vsr, 2, 11), | |
10391 | GEN_VXFORM(vpkuhum, 7, 0), | |
10392 | GEN_VXFORM(vpkuwum, 7, 1), | |
024215b2 | 10393 | GEN_VXFORM_207(vpkudum, 7, 17), |
5c55ff99 BS |
10394 | GEN_VXFORM(vpkuhus, 7, 2), |
10395 | GEN_VXFORM(vpkuwus, 7, 3), | |
024215b2 | 10396 | GEN_VXFORM_207(vpkudus, 7, 19), |
5c55ff99 BS |
10397 | GEN_VXFORM(vpkshus, 7, 4), |
10398 | GEN_VXFORM(vpkswus, 7, 5), | |
024215b2 | 10399 | GEN_VXFORM_207(vpksdus, 7, 21), |
5c55ff99 BS |
10400 | GEN_VXFORM(vpkshss, 7, 6), |
10401 | GEN_VXFORM(vpkswss, 7, 7), | |
024215b2 | 10402 | GEN_VXFORM_207(vpksdss, 7, 23), |
5c55ff99 BS |
10403 | GEN_VXFORM(vpkpx, 7, 12), |
10404 | GEN_VXFORM(vsum4ubs, 4, 24), | |
10405 | GEN_VXFORM(vsum4sbs, 4, 28), | |
10406 | GEN_VXFORM(vsum4shs, 4, 25), | |
10407 | GEN_VXFORM(vsum2sws, 4, 26), | |
10408 | GEN_VXFORM(vsumsws, 4, 30), | |
10409 | GEN_VXFORM(vaddfp, 5, 0), | |
10410 | GEN_VXFORM(vsubfp, 5, 1), | |
10411 | GEN_VXFORM(vmaxfp, 5, 16), | |
10412 | GEN_VXFORM(vminfp, 5, 17), | |
10413 | ||
10414 | #undef GEN_VXRFORM1 | |
10415 | #undef GEN_VXRFORM | |
10416 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
10417 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC), | |
10418 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
10419 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
10420 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
10421 | GEN_VXRFORM(vcmpequb, 3, 0) | |
10422 | GEN_VXRFORM(vcmpequh, 3, 1) | |
10423 | GEN_VXRFORM(vcmpequw, 3, 2) | |
10424 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
10425 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
10426 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
10427 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
10428 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
10429 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
6f3dab41 | 10430 | GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE) |
5c55ff99 | 10431 | GEN_VXRFORM(vcmpgefp, 3, 7) |
6f3dab41 TM |
10432 | GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE) |
10433 | GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE) | |
5c55ff99 BS |
10434 | |
10435 | #undef GEN_VXFORM_SIMM | |
10436 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ | |
10437 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
10438 | GEN_VXFORM_SIMM(vspltisb, 6, 12), | |
10439 | GEN_VXFORM_SIMM(vspltish, 6, 13), | |
10440 | GEN_VXFORM_SIMM(vspltisw, 6, 14), | |
10441 | ||
10442 | #undef GEN_VXFORM_NOA | |
10443 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
10444 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) | |
10445 | GEN_VXFORM_NOA(vupkhsb, 7, 8), | |
10446 | GEN_VXFORM_NOA(vupkhsh, 7, 9), | |
4430e076 | 10447 | GEN_VXFORM_207(vupkhsw, 7, 25), |
5c55ff99 BS |
10448 | GEN_VXFORM_NOA(vupklsb, 7, 10), |
10449 | GEN_VXFORM_NOA(vupklsh, 7, 11), | |
4430e076 | 10450 | GEN_VXFORM_207(vupklsw, 7, 27), |
5c55ff99 BS |
10451 | GEN_VXFORM_NOA(vupkhpx, 7, 13), |
10452 | GEN_VXFORM_NOA(vupklpx, 7, 15), | |
10453 | GEN_VXFORM_NOA(vrefp, 5, 4), | |
10454 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5), | |
0bffbc6c | 10455 | GEN_VXFORM_NOA(vexptefp, 5, 6), |
5c55ff99 BS |
10456 | GEN_VXFORM_NOA(vlogefp, 5, 7), |
10457 | GEN_VXFORM_NOA(vrfim, 5, 8), | |
10458 | GEN_VXFORM_NOA(vrfin, 5, 9), | |
10459 | GEN_VXFORM_NOA(vrfip, 5, 10), | |
10460 | GEN_VXFORM_NOA(vrfiz, 5, 11), | |
10461 | ||
10462 | #undef GEN_VXFORM_UIMM | |
10463 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ | |
10464 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) | |
10465 | GEN_VXFORM_UIMM(vspltb, 6, 8), | |
10466 | GEN_VXFORM_UIMM(vsplth, 6, 9), | |
10467 | GEN_VXFORM_UIMM(vspltw, 6, 10), | |
10468 | GEN_VXFORM_UIMM(vcfux, 5, 12), | |
10469 | GEN_VXFORM_UIMM(vcfsx, 5, 13), | |
10470 | GEN_VXFORM_UIMM(vctuxs, 5, 14), | |
10471 | GEN_VXFORM_UIMM(vctsxs, 5, 15), | |
10472 | ||
10473 | #undef GEN_VAFORM_PAIRED | |
10474 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
10475 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) | |
10476 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16), | |
10477 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18), | |
10478 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), | |
10479 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), | |
10480 | GEN_VAFORM_PAIRED(vsel, vperm, 21), | |
10481 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), | |
10482 | ||
e13500b3 TM |
10483 | GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), |
10484 | GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207), | |
10485 | GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207), | |
10486 | GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207), | |
10487 | ||
4d82038e | 10488 | GEN_VXFORM_207(vbpermq, 6, 21), |
f1064f61 | 10489 | GEN_VXFORM_207(vgbbd, 6, 20), |
b8476fc7 TM |
10490 | GEN_VXFORM_207(vpmsumb, 4, 16), |
10491 | GEN_VXFORM_207(vpmsumh, 4, 17), | |
10492 | GEN_VXFORM_207(vpmsumw, 4, 18), | |
10493 | GEN_VXFORM_207(vpmsumd, 4, 19), | |
f293f04a | 10494 | |
557d52fa TM |
10495 | GEN_VXFORM_207(vsbox, 4, 23), |
10496 | ||
10497 | GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207), | |
10498 | GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207), | |
10499 | ||
57354f8f TM |
10500 | GEN_VXFORM_207(vshasigmaw, 1, 26), |
10501 | GEN_VXFORM_207(vshasigmad, 1, 27), | |
10502 | ||
ac174549 TM |
10503 | GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE), |
10504 | ||
fa1832d7 | 10505 | GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), |
cac7f0ba TM |
10506 | GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207), |
10507 | GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207), | |
10508 | GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207), | |
304af367 | 10509 | GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), |
ca03b467 | 10510 | GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX), |
897e61d1 | 10511 | GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX), |
304af367 | 10512 | |
9231ba9e | 10513 | GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX), |
e16a626b TM |
10514 | GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207), |
10515 | GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207), | |
fbed2478 | 10516 | GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), |
86e61ce3 | 10517 | GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), |
fbed2478 | 10518 | |
f5c0f7f9 TM |
10519 | GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207), |
10520 | GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10521 | GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10522 | #if defined(TARGET_PPC64) | |
10523 | GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10524 | GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207), | |
10525 | #endif | |
10526 | ||
df020ce0 TM |
10527 | #undef GEN_XX2FORM |
10528 | #define GEN_XX2FORM(name, opc2, opc3, fl2) \ | |
10529 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ | |
10530 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2) | |
10531 | ||
10532 | #undef GEN_XX3FORM | |
10533 | #define GEN_XX3FORM(name, opc2, opc3, fl2) \ | |
10534 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \ | |
10535 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \ | |
10536 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \ | |
10537 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2) | |
10538 | ||
354a6dec TM |
10539 | #undef GEN_XX3_RC_FORM |
10540 | #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \ | |
10541 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10542 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10543 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10544 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \ | |
10545 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \ | |
10546 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \ | |
10547 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \ | |
10548 | GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2) | |
10549 | ||
cd73f2c9 TM |
10550 | #undef GEN_XX3FORM_DM |
10551 | #define GEN_XX3FORM_DM(name, opc2, opc3) \ | |
10552 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10553 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10554 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10555 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\ | |
10556 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10557 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10558 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10559 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\ | |
10560 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10561 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10562 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10563 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\ | |
10564 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
10565 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
10566 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\ | |
10567 | GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX) | |
10568 | ||
df020ce0 TM |
10569 | GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX), |
10570 | GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX), | |
10571 | GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX), | |
10572 | GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX), | |
10573 | ||
be574920 TM |
10574 | GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), |
10575 | GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), | |
10576 | GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX), | |
10577 | GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX), | |
10578 | GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX), | |
10579 | GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX), | |
10580 | GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX), | |
10581 | GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX), | |
79ca8a6a | 10582 | |
ee6e02c0 TM |
10583 | GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX), |
10584 | GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX), | |
5e591d88 | 10585 | GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX), |
4b98eeef | 10586 | GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX), |
2009227f | 10587 | GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX), |
d32404fe | 10588 | GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX), |
d3f9df8f | 10589 | GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX), |
bc80838f | 10590 | GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX), |
5cb151ac | 10591 | GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX), |
595c6eef TM |
10592 | GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX), |
10593 | GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX), | |
10594 | GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX), | |
10595 | GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX), | |
10596 | GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX), | |
10597 | GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX), | |
10598 | GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX), | |
10599 | GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX), | |
4f17e9c7 TM |
10600 | GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX), |
10601 | GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX), | |
959e9c9d TM |
10602 | GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX), |
10603 | GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX), | |
ed8ac568 | 10604 | GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX), |
7ee19fb9 | 10605 | GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207), |
ed8ac568 | 10606 | GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX), |
7ee19fb9 | 10607 | GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207), |
5177d2ca TM |
10608 | GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX), |
10609 | GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX), | |
10610 | GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX), | |
10611 | GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX), | |
10612 | GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX), | |
10613 | GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX), | |
88e33d08 TM |
10614 | GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX), |
10615 | GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX), | |
10616 | GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX), | |
10617 | GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), | |
10618 | GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), | |
ee6e02c0 | 10619 | |
3fd0aadf TM |
10620 | GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), |
10621 | GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), | |
ab9408a2 | 10622 | GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207), |
b24d0b47 | 10623 | GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207), |
2c0c52ae | 10624 | GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207), |
3d1140bf | 10625 | GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207), |
cea4e574 | 10626 | GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207), |
968e76bc | 10627 | GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207), |
f53f81e0 TM |
10628 | GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207), |
10629 | GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207), | |
10630 | GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207), | |
10631 | GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207), | |
10632 | GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207), | |
10633 | GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207), | |
10634 | GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207), | |
10635 | GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207), | |
74698350 TM |
10636 | GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207), |
10637 | GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207), | |
3fd0aadf | 10638 | |
ee6e02c0 TM |
10639 | GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), |
10640 | GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), | |
5e591d88 | 10641 | GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX), |
4b98eeef | 10642 | GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX), |
2009227f | 10643 | GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX), |
d32404fe | 10644 | GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), |
d3f9df8f | 10645 | GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX), |
bc80838f | 10646 | GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX), |
5cb151ac | 10647 | GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX), |
595c6eef TM |
10648 | GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX), |
10649 | GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX), | |
10650 | GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX), | |
10651 | GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX), | |
10652 | GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX), | |
10653 | GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX), | |
10654 | GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX), | |
10655 | GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX), | |
959e9c9d TM |
10656 | GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX), |
10657 | GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX), | |
354a6dec TM |
10658 | GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX), |
10659 | GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX), | |
10660 | GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX), | |
ed8ac568 | 10661 | GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX), |
5177d2ca TM |
10662 | GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX), |
10663 | GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX), | |
10664 | GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX), | |
10665 | GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX), | |
10666 | GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX), | |
10667 | GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX), | |
10668 | GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX), | |
10669 | GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX), | |
88e33d08 TM |
10670 | GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX), |
10671 | GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX), | |
10672 | GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX), | |
10673 | GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX), | |
10674 | GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX), | |
ee6e02c0 TM |
10675 | |
10676 | GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX), | |
10677 | GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX), | |
5e591d88 | 10678 | GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX), |
4b98eeef | 10679 | GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX), |
2009227f | 10680 | GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX), |
d32404fe | 10681 | GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX), |
d3f9df8f | 10682 | GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX), |
bc80838f | 10683 | GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX), |
5cb151ac | 10684 | GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX), |
595c6eef TM |
10685 | GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX), |
10686 | GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX), | |
10687 | GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX), | |
10688 | GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX), | |
10689 | GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX), | |
10690 | GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX), | |
10691 | GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX), | |
10692 | GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX), | |
959e9c9d TM |
10693 | GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX), |
10694 | GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX), | |
354a6dec TM |
10695 | GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX), |
10696 | GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX), | |
10697 | GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX), | |
ed8ac568 | 10698 | GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX), |
5177d2ca TM |
10699 | GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX), |
10700 | GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX), | |
10701 | GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX), | |
10702 | GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX), | |
10703 | GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX), | |
10704 | GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX), | |
10705 | GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX), | |
10706 | GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX), | |
88e33d08 TM |
10707 | GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX), |
10708 | GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX), | |
10709 | GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX), | |
10710 | GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX), | |
10711 | GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX), | |
ee6e02c0 | 10712 | |
79ca8a6a TM |
10713 | #undef VSX_LOGICAL |
10714 | #define VSX_LOGICAL(name, opc2, opc3, fl2) \ | |
10715 | GEN_XX3FORM(name, opc2, opc3, fl2) | |
10716 | ||
10717 | VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX), | |
10718 | VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX), | |
10719 | VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX), | |
10720 | VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX), | |
10721 | VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX), | |
67a33f37 TM |
10722 | VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207), |
10723 | VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207), | |
10724 | VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207), | |
ce577d2e TM |
10725 | GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), |
10726 | GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), | |
76c15fe0 | 10727 | GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX), |
acc42968 | 10728 | GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), |
79ca8a6a | 10729 | |
551e3ef7 TM |
10730 | #define GEN_XXSEL_ROW(opc3) \ |
10731 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10732 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10733 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10734 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10735 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10736 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10737 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10738 | GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \ | |
10739 | ||
10740 | GEN_XXSEL_ROW(0x00) | |
10741 | GEN_XXSEL_ROW(0x01) | |
10742 | GEN_XXSEL_ROW(0x02) | |
10743 | GEN_XXSEL_ROW(0x03) | |
10744 | GEN_XXSEL_ROW(0x04) | |
10745 | GEN_XXSEL_ROW(0x05) | |
10746 | GEN_XXSEL_ROW(0x06) | |
10747 | GEN_XXSEL_ROW(0x07) | |
10748 | GEN_XXSEL_ROW(0x08) | |
10749 | GEN_XXSEL_ROW(0x09) | |
10750 | GEN_XXSEL_ROW(0x0A) | |
10751 | GEN_XXSEL_ROW(0x0B) | |
10752 | GEN_XXSEL_ROW(0x0C) | |
10753 | GEN_XXSEL_ROW(0x0D) | |
10754 | GEN_XXSEL_ROW(0x0E) | |
10755 | GEN_XXSEL_ROW(0x0F) | |
10756 | GEN_XXSEL_ROW(0x10) | |
10757 | GEN_XXSEL_ROW(0x11) | |
10758 | GEN_XXSEL_ROW(0x12) | |
10759 | GEN_XXSEL_ROW(0x13) | |
10760 | GEN_XXSEL_ROW(0x14) | |
10761 | GEN_XXSEL_ROW(0x15) | |
10762 | GEN_XXSEL_ROW(0x16) | |
10763 | GEN_XXSEL_ROW(0x17) | |
10764 | GEN_XXSEL_ROW(0x18) | |
10765 | GEN_XXSEL_ROW(0x19) | |
10766 | GEN_XXSEL_ROW(0x1A) | |
10767 | GEN_XXSEL_ROW(0x1B) | |
10768 | GEN_XXSEL_ROW(0x1C) | |
10769 | GEN_XXSEL_ROW(0x1D) | |
10770 | GEN_XXSEL_ROW(0x1E) | |
10771 | GEN_XXSEL_ROW(0x1F) | |
10772 | ||
cd73f2c9 TM |
10773 | GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01), |
10774 | ||
275e35c6 TM |
10775 | #undef GEN_DFP_T_A_B_Rc |
10776 | #undef GEN_DFP_BF_A_B | |
10777 | #undef GEN_DFP_BF_A_DCM | |
10778 | #undef GEN_DFP_T_B_U32_U32_Rc | |
10779 | #undef GEN_DFP_T_A_B_I32_Rc | |
10780 | #undef GEN_DFP_T_B_Rc | |
10781 | #undef GEN_DFP_T_FPR_I32_Rc | |
10782 | ||
10783 | #define _GEN_DFP_LONG(name, op1, op2, mask) \ | |
10784 | GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP) | |
10785 | ||
10786 | #define _GEN_DFP_LONGx2(name, op1, op2, mask) \ | |
10787 | GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10788 | GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) | |
10789 | ||
10790 | #define _GEN_DFP_LONGx4(name, op1, op2, mask) \ | |
10791 | GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10792 | GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10793 | GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10794 | GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) | |
10795 | ||
10796 | #define _GEN_DFP_QUAD(name, op1, op2, mask) \ | |
10797 | GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP) | |
10798 | ||
10799 | #define _GEN_DFP_QUADx2(name, op1, op2, mask) \ | |
10800 | GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10801 | GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP) | |
10802 | ||
10803 | #define _GEN_DFP_QUADx4(name, op1, op2, mask) \ | |
10804 | GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10805 | GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10806 | GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \ | |
10807 | GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP) | |
10808 | ||
10809 | #define GEN_DFP_T_A_B_Rc(name, op1, op2) \ | |
10810 | _GEN_DFP_LONG(name, op1, op2, 0x00000000) | |
10811 | ||
10812 | #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \ | |
10813 | _GEN_DFP_QUAD(name, op1, op2, 0x00210800) | |
10814 | ||
10815 | #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \ | |
10816 | _GEN_DFP_QUAD(name, op1, op2, 0x00200800) | |
10817 | ||
10818 | #define GEN_DFP_T_B_Rc(name, op1, op2) \ | |
10819 | _GEN_DFP_LONG(name, op1, op2, 0x001F0000) | |
10820 | ||
10821 | #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \ | |
10822 | _GEN_DFP_QUAD(name, op1, op2, 0x003F0800) | |
10823 | ||
10824 | #define GEN_DFP_Tp_B_Rc(name, op1, op2) \ | |
10825 | _GEN_DFP_QUAD(name, op1, op2, 0x003F0000) | |
10826 | ||
10827 | #define GEN_DFP_T_Bp_Rc(name, op1, op2) \ | |
10828 | _GEN_DFP_QUAD(name, op1, op2, 0x001F0800) | |
10829 | ||
10830 | #define GEN_DFP_BF_A_B(name, op1, op2) \ | |
10831 | _GEN_DFP_LONG(name, op1, op2, 0x00000001) | |
10832 | ||
10833 | #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \ | |
10834 | _GEN_DFP_QUAD(name, op1, op2, 0x00610801) | |
10835 | ||
10836 | #define GEN_DFP_BF_A_Bp(name, op1, op2) \ | |
10837 | _GEN_DFP_QUAD(name, op1, op2, 0x00600801) | |
10838 | ||
10839 | #define GEN_DFP_BF_A_DCM(name, op1, op2) \ | |
10840 | _GEN_DFP_LONGx2(name, op1, op2, 0x00600001) | |
10841 | ||
10842 | #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \ | |
10843 | _GEN_DFP_QUADx2(name, op1, op2, 0x00610001) | |
10844 | ||
10845 | #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \ | |
10846 | _GEN_DFP_LONGx4(name, op1, op2, 0x00000000) | |
10847 | ||
10848 | #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \ | |
10849 | _GEN_DFP_QUADx4(name, op1, op2, 0x02010800) | |
10850 | ||
10851 | #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \ | |
10852 | _GEN_DFP_QUADx4(name, op1, op2, 0x02000800) | |
10853 | ||
10854 | #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \ | |
10855 | _GEN_DFP_LONGx4(name, op1, op2, 0x00000000) | |
10856 | ||
10857 | #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \ | |
10858 | _GEN_DFP_QUADx4(name, op1, op2, 0x00200800) | |
10859 | ||
10860 | #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \ | |
10861 | _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000) | |
10862 | ||
10863 | #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \ | |
10864 | _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800) | |
10865 | ||
10866 | #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \ | |
10867 | _GEN_DFP_LONG(name, op1, op2, 0x00070000) | |
10868 | ||
10869 | #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \ | |
10870 | _GEN_DFP_QUAD(name, op1, op2, 0x00270800) | |
10871 | ||
10872 | #define GEN_DFP_S_T_B_Rc(name, op1, op2) \ | |
10873 | _GEN_DFP_LONG(name, op1, op2, 0x000F0000) | |
10874 | ||
10875 | #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \ | |
10876 | _GEN_DFP_QUAD(name, op1, op2, 0x002F0800) | |
10877 | ||
10878 | #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \ | |
10879 | _GEN_DFP_LONGx2(name, op1, op2, 0x00000000) | |
10880 | ||
10881 | #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \ | |
10882 | _GEN_DFP_QUADx2(name, op1, op2, 0x00210000) | |
10883 | ||
a9d7ba03 TM |
10884 | GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00), |
10885 | GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00), | |
2128f8a5 TM |
10886 | GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10), |
10887 | GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10), | |
8de6a1cc TM |
10888 | GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01), |
10889 | GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01), | |
9024ff40 TM |
10890 | GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11), |
10891 | GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11), | |
5833505b TM |
10892 | GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14), |
10893 | GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14), | |
10894 | GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04), | |
10895 | GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04), | |
e601c1ee TM |
10896 | GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06), |
10897 | GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06), | |
1bf9c0e1 TM |
10898 | GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07), |
10899 | GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07), | |
f3d2b0bc TM |
10900 | GEN_DFP_BF_A_B(dtstex, 0x02, 0x05), |
10901 | GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05), | |
f6022a76 TM |
10902 | GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15), |
10903 | GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15), | |
5826ebe2 TM |
10904 | GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02), |
10905 | GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02), | |
10906 | GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00), | |
10907 | GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00), | |
512918aa TM |
10908 | GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01), |
10909 | GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01), | |
97c0d930 TM |
10910 | GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03), |
10911 | GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03), | |
10912 | GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07), | |
10913 | GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07), | |
290d9ee5 TM |
10914 | GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08), |
10915 | GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08), | |
ca603eb4 TM |
10916 | GEN_DFP_T_B_Rc(drsp, 0x02, 0x18), |
10917 | GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18), | |
f1214193 TM |
10918 | GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19), |
10919 | GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19), | |
bea0dd79 TM |
10920 | GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09), |
10921 | GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09), | |
7796676f TM |
10922 | GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a), |
10923 | GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a), | |
013c3ac0 TM |
10924 | GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a), |
10925 | GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a), | |
e8a48460 TM |
10926 | GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b), |
10927 | GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b), | |
297666eb TM |
10928 | GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b), |
10929 | GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b), | |
804e654a TM |
10930 | GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02), |
10931 | GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02), | |
10932 | GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03), | |
10933 | GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03), | |
10934 | ||
5c55ff99 | 10935 | #undef GEN_SPE |
70560da7 FC |
10936 | #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \ |
10937 | GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE) | |
10938 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10939 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10940 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10941 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10942 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
10943 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
10944 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE), | |
10945 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE), | |
10946 | GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE), | |
10947 | GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
10948 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10949 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10950 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10951 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
10952 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE), | |
10953 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE), | |
10954 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE), | |
10955 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10956 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10957 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10958 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10959 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE), | |
10960 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
10961 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE), | |
10962 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10963 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE), | |
10964 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
10965 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE), | |
10966 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE), | |
10967 | ||
10968 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10969 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
10970 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10971 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10972 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10973 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10974 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10975 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10976 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10977 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10978 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10979 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10980 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10981 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10982 | ||
10983 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10984 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE), | |
10985 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10986 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE), | |
10987 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10988 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE), | |
10989 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10990 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10991 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10992 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE), | |
10993 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10994 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10995 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE), | |
10996 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE), | |
10997 | ||
10998 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
10999 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11000 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE), | |
11001 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
11002 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE), | |
11003 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11004 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
11005 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), | |
11006 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11007 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11008 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11009 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE), | |
11010 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
11011 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
11012 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE), | |
11013 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE), | |
5c55ff99 BS |
11014 | |
11015 | #undef GEN_SPEOP_LDST | |
11016 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
11017 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) | |
11018 | GEN_SPEOP_LDST(evldd, 0x00, 3), | |
11019 | GEN_SPEOP_LDST(evldw, 0x01, 3), | |
11020 | GEN_SPEOP_LDST(evldh, 0x02, 3), | |
11021 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1), | |
11022 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1), | |
11023 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1), | |
11024 | GEN_SPEOP_LDST(evlwhe, 0x08, 2), | |
11025 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2), | |
11026 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2), | |
11027 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2), | |
11028 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2), | |
11029 | ||
11030 | GEN_SPEOP_LDST(evstdd, 0x10, 3), | |
11031 | GEN_SPEOP_LDST(evstdw, 0x11, 3), | |
11032 | GEN_SPEOP_LDST(evstdh, 0x12, 3), | |
11033 | GEN_SPEOP_LDST(evstwhe, 0x18, 2), | |
11034 | GEN_SPEOP_LDST(evstwho, 0x1A, 2), | |
11035 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2), | |
11036 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2), | |
11037 | }; | |
11038 | ||
0411a972 | 11039 | #include "helper_regs.h" |
a1389542 | 11040 | #include "translate_init.c" |
79aceca5 | 11041 | |
9a64fbe4 | 11042 | /*****************************************************************************/ |
3fc6c082 | 11043 | /* Misc PowerPC helpers */ |
878096ee AF |
11044 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
11045 | int flags) | |
79aceca5 | 11046 | { |
3fc6c082 FB |
11047 | #define RGPL 4 |
11048 | #define RFPL 4 | |
3fc6c082 | 11049 | |
878096ee AF |
11050 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
11051 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
11052 | int i; |
11053 | ||
90e189ec | 11054 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
9a78eead | 11055 | TARGET_FMT_lx " XER " TARGET_FMT_lx "\n", |
da91a00f | 11056 | env->nip, env->lr, env->ctr, cpu_read_xer(env)); |
90e189ec BS |
11057 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
11058 | TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0], | |
11059 | env->hflags, env->mmu_idx); | |
d9bce9d9 | 11060 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 11061 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 11062 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 11063 | " DECR %08" PRIu32 |
76a66253 JM |
11064 | #endif |
11065 | "\n", | |
077fc206 | 11066 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
11067 | #if !defined(CONFIG_USER_ONLY) |
11068 | , cpu_ppc_load_decr(env) | |
11069 | #endif | |
11070 | ); | |
077fc206 | 11071 | #endif |
76a66253 | 11072 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
11073 | if ((i & (RGPL - 1)) == 0) |
11074 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 11075 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 11076 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 11077 | cpu_fprintf(f, "\n"); |
76a66253 | 11078 | } |
3fc6c082 | 11079 | cpu_fprintf(f, "CR "); |
76a66253 | 11080 | for (i = 0; i < 8; i++) |
7fe48483 FB |
11081 | cpu_fprintf(f, "%01x", env->crf[i]); |
11082 | cpu_fprintf(f, " ["); | |
76a66253 JM |
11083 | for (i = 0; i < 8; i++) { |
11084 | char a = '-'; | |
11085 | if (env->crf[i] & 0x08) | |
11086 | a = 'L'; | |
11087 | else if (env->crf[i] & 0x04) | |
11088 | a = 'G'; | |
11089 | else if (env->crf[i] & 0x02) | |
11090 | a = 'E'; | |
7fe48483 | 11091 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 11092 | } |
90e189ec BS |
11093 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
11094 | env->reserve_addr); | |
3fc6c082 FB |
11095 | for (i = 0; i < 32; i++) { |
11096 | if ((i & (RFPL - 1)) == 0) | |
11097 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 11098 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 11099 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 11100 | cpu_fprintf(f, "\n"); |
79aceca5 | 11101 | } |
30304420 | 11102 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 11103 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
11104 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
11105 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
11106 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
11107 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
11108 | ||
11109 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
11110 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
11111 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
11112 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
11113 | ||
11114 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
11115 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
11116 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
11117 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
11118 | ||
11119 | if (env->excp_model == POWERPC_EXCP_BOOKE) { | |
11120 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
11121 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
11122 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
11123 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
11124 | ||
11125 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
11126 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
11127 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
11128 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
11129 | ||
11130 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
11131 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
11132 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
11133 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
11134 | ||
11135 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
11136 | " EPR " TARGET_FMT_lx "\n", | |
11137 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
11138 | env->spr[SPR_BOOKE_EPR]); | |
11139 | ||
11140 | /* FSL-specific */ | |
11141 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
11142 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
11143 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
11144 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
11145 | ||
11146 | /* | |
11147 | * IVORs are left out as they are large and do not change often -- | |
11148 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
11149 | */ | |
11150 | } | |
11151 | ||
697ab892 DG |
11152 | #if defined(TARGET_PPC64) |
11153 | if (env->flags & POWERPC_FLAG_CFAR) { | |
11154 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
11155 | } | |
11156 | #endif | |
11157 | ||
90dc8812 SW |
11158 | switch (env->mmu_model) { |
11159 | case POWERPC_MMU_32B: | |
11160 | case POWERPC_MMU_601: | |
11161 | case POWERPC_MMU_SOFT_6xx: | |
11162 | case POWERPC_MMU_SOFT_74xx: | |
11163 | #if defined(TARGET_PPC64) | |
90dc8812 | 11164 | case POWERPC_MMU_64B: |
ca480de6 AB |
11165 | case POWERPC_MMU_2_06: |
11166 | case POWERPC_MMU_2_06a: | |
11167 | case POWERPC_MMU_2_06d: | |
90dc8812 | 11168 | #endif |
ca480de6 AB |
11169 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx |
11170 | " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], | |
11171 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); | |
90dc8812 | 11172 | break; |
01662f3e | 11173 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
11174 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
11175 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
11176 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
11177 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
11178 | ||
11179 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
11180 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
11181 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
11182 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
11183 | ||
11184 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
11185 | " TLB1CFG " TARGET_FMT_lx "\n", | |
11186 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
11187 | env->spr[SPR_BOOKE_TLB1CFG]); | |
11188 | break; | |
11189 | default: | |
11190 | break; | |
11191 | } | |
f2e63a42 | 11192 | #endif |
79aceca5 | 11193 | |
3fc6c082 FB |
11194 | #undef RGPL |
11195 | #undef RFPL | |
79aceca5 FB |
11196 | } |
11197 | ||
878096ee AF |
11198 | void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, |
11199 | fprintf_function cpu_fprintf, int flags) | |
76a66253 JM |
11200 | { |
11201 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 11202 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 11203 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
11204 | int op1, op2, op3; |
11205 | ||
878096ee | 11206 | t1 = cpu->env.opcodes; |
76a66253 JM |
11207 | for (op1 = 0; op1 < 64; op1++) { |
11208 | handler = t1[op1]; | |
11209 | if (is_indirect_opcode(handler)) { | |
11210 | t2 = ind_table(handler); | |
11211 | for (op2 = 0; op2 < 32; op2++) { | |
11212 | handler = t2[op2]; | |
11213 | if (is_indirect_opcode(handler)) { | |
11214 | t3 = ind_table(handler); | |
11215 | for (op3 = 0; op3 < 32; op3++) { | |
11216 | handler = t3[op3]; | |
11217 | if (handler->count == 0) | |
11218 | continue; | |
11219 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 11220 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
11221 | op1, op2, op3, op1, (op3 << 5) | op2, |
11222 | handler->oname, | |
11223 | handler->count, handler->count); | |
11224 | } | |
11225 | } else { | |
11226 | if (handler->count == 0) | |
11227 | continue; | |
11228 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 11229 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
11230 | op1, op2, op1, op2, handler->oname, |
11231 | handler->count, handler->count); | |
11232 | } | |
11233 | } | |
11234 | } else { | |
11235 | if (handler->count == 0) | |
11236 | continue; | |
0bfcd599 BS |
11237 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
11238 | " %" PRId64 "\n", | |
76a66253 JM |
11239 | op1, op1, handler->oname, |
11240 | handler->count, handler->count); | |
11241 | } | |
11242 | } | |
11243 | #endif | |
11244 | } | |
11245 | ||
9a64fbe4 | 11246 | /*****************************************************************************/ |
213fe1f5 | 11247 | static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, |
636aa200 | 11248 | TranslationBlock *tb, |
213fe1f5 | 11249 | bool search_pc) |
79aceca5 | 11250 | { |
ed2803da | 11251 | CPUState *cs = CPU(cpu); |
213fe1f5 | 11252 | CPUPPCState *env = &cpu->env; |
9fddaa0c | 11253 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 11254 | opc_handler_t **table, *handler; |
0fa85d43 | 11255 | target_ulong pc_start; |
79aceca5 | 11256 | uint16_t *gen_opc_end; |
a1d1bb31 | 11257 | CPUBreakpoint *bp; |
79aceca5 | 11258 | int j, lj = -1; |
2e70f6ef PB |
11259 | int num_insns; |
11260 | int max_insns; | |
79aceca5 FB |
11261 | |
11262 | pc_start = tb->pc; | |
92414b31 | 11263 | gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 11264 | ctx.nip = pc_start; |
79aceca5 | 11265 | ctx.tb = tb; |
e1833e1f | 11266 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 11267 | ctx.spr_cb = env->spr_cb; |
76db3ba4 | 11268 | ctx.mem_idx = env->mmu_idx; |
7d08d856 AJ |
11269 | ctx.insns_flags = env->insns_flags; |
11270 | ctx.insns_flags2 = env->insns_flags2; | |
76db3ba4 AJ |
11271 | ctx.access_type = -1; |
11272 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
e22c357b | 11273 | ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; |
d9bce9d9 | 11274 | #if defined(TARGET_PPC64) |
e42a61f1 | 11275 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 11276 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 11277 | #endif |
3cc62370 | 11278 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 11279 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
11280 | ctx.spe_enabled = msr_spe; |
11281 | else | |
11282 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
11283 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
11284 | ctx.altivec_enabled = msr_vr; | |
11285 | else | |
11286 | ctx.altivec_enabled = 0; | |
1f29871c TM |
11287 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
11288 | ctx.vsx_enabled = msr_vsx; | |
11289 | } else { | |
11290 | ctx.vsx_enabled = 0; | |
11291 | } | |
d26bfc9a | 11292 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 11293 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 11294 | else |
8cbcb4fa | 11295 | ctx.singlestep_enabled = 0; |
d26bfc9a | 11296 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa | 11297 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
ed2803da | 11298 | if (unlikely(cs->singlestep_enabled)) { |
8cbcb4fa | 11299 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
ed2803da | 11300 | } |
3fc6c082 | 11301 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
11302 | /* Single step trace mode */ |
11303 | msr_se = 1; | |
11304 | #endif | |
2e70f6ef PB |
11305 | num_insns = 0; |
11306 | max_insns = tb->cflags & CF_COUNT_MASK; | |
11307 | if (max_insns == 0) | |
11308 | max_insns = CF_COUNT_MASK; | |
11309 | ||
806f352d | 11310 | gen_tb_start(); |
3de31797 | 11311 | tcg_clear_temp_count(); |
9a64fbe4 | 11312 | /* Set env in case of segfault during code fetch */ |
efd7f486 EV |
11313 | while (ctx.exception == POWERPC_EXCP_NONE |
11314 | && tcg_ctx.gen_opc_ptr < gen_opc_end) { | |
f0c3c505 AF |
11315 | if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { |
11316 | QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { | |
a1d1bb31 | 11317 | if (bp->pc == ctx.nip) { |
e06fcd75 | 11318 | gen_debug_exception(ctxp); |
ea4e754f FB |
11319 | break; |
11320 | } | |
11321 | } | |
11322 | } | |
76a66253 | 11323 | if (unlikely(search_pc)) { |
92414b31 | 11324 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
79aceca5 FB |
11325 | if (lj < j) { |
11326 | lj++; | |
11327 | while (lj < j) | |
ab1103de | 11328 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
79aceca5 | 11329 | } |
25983cad | 11330 | tcg_ctx.gen_opc_pc[lj] = ctx.nip; |
ab1103de | 11331 | tcg_ctx.gen_opc_instr_start[lj] = 1; |
c9c99c22 | 11332 | tcg_ctx.gen_opc_icount[lj] = num_insns; |
79aceca5 | 11333 | } |
d12d51d5 | 11334 | LOG_DISAS("----------------\n"); |
90e189ec | 11335 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 11336 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
2e70f6ef PB |
11337 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
11338 | gen_io_start(); | |
e22c357b | 11339 | if (unlikely(need_byteswap(&ctx))) { |
2f5a189c | 11340 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 11341 | } else { |
2f5a189c | 11342 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 11343 | } |
d12d51d5 | 11344 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 11345 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
476b6d16 | 11346 | opc3(ctx.opcode), ctx.le_mode ? "little" : "big"); |
fdefe51c | 11347 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { |
731c54f8 | 11348 | tcg_gen_debug_insn_start(ctx.nip); |
fdefe51c | 11349 | } |
046d6672 | 11350 | ctx.nip += 4; |
3fc6c082 | 11351 | table = env->opcodes; |
2e70f6ef | 11352 | num_insns++; |
79aceca5 FB |
11353 | handler = table[opc1(ctx.opcode)]; |
11354 | if (is_indirect_opcode(handler)) { | |
11355 | table = ind_table(handler); | |
11356 | handler = table[opc2(ctx.opcode)]; | |
11357 | if (is_indirect_opcode(handler)) { | |
11358 | table = ind_table(handler); | |
11359 | handler = table[opc3(ctx.opcode)]; | |
11360 | } | |
11361 | } | |
11362 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 11363 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
11364 | if (qemu_log_enabled()) { |
11365 | qemu_log("invalid/unsupported opcode: " | |
90e189ec BS |
11366 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n", |
11367 | opc1(ctx.opcode), opc2(ctx.opcode), | |
11368 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa | 11369 | } |
76a66253 | 11370 | } else { |
70560da7 FC |
11371 | uint32_t inval; |
11372 | ||
11373 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
11374 | inval = handler->inval2; | |
11375 | } else { | |
11376 | inval = handler->inval1; | |
11377 | } | |
11378 | ||
11379 | if (unlikely((ctx.opcode & inval) != 0)) { | |
93fcfe39 AL |
11380 | if (qemu_log_enabled()) { |
11381 | qemu_log("invalid bits: %08x for opcode: " | |
90e189ec | 11382 | "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n", |
70560da7 | 11383 | ctx.opcode & inval, opc1(ctx.opcode), |
90e189ec BS |
11384 | opc2(ctx.opcode), opc3(ctx.opcode), |
11385 | ctx.opcode, ctx.nip - 4); | |
76a66253 | 11386 | } |
e06fcd75 | 11387 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 11388 | break; |
79aceca5 | 11389 | } |
79aceca5 | 11390 | } |
4b3686fa | 11391 | (*(handler->handler))(&ctx); |
76a66253 JM |
11392 | #if defined(DO_PPC_STATISTICS) |
11393 | handler->count++; | |
11394 | #endif | |
9a64fbe4 | 11395 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
11396 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
11397 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
11398 | ctx.exception != POWERPC_SYSCALL && | |
11399 | ctx.exception != POWERPC_EXCP_TRAP && | |
11400 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 11401 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 11402 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
ed2803da | 11403 | (cs->singlestep_enabled) || |
1b530a6d | 11404 | singlestep || |
2e70f6ef | 11405 | num_insns >= max_insns)) { |
d26bfc9a JM |
11406 | /* if we reach a page boundary or are single stepping, stop |
11407 | * generation | |
11408 | */ | |
8dd4983c | 11409 | break; |
76a66253 | 11410 | } |
3de31797 AG |
11411 | if (tcg_check_temp_count()) { |
11412 | fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n", | |
11413 | opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), | |
11414 | ctx.opcode); | |
11415 | exit(1); | |
11416 | } | |
3fc6c082 | 11417 | } |
2e70f6ef PB |
11418 | if (tb->cflags & CF_LAST_IO) |
11419 | gen_io_end(); | |
e1833e1f | 11420 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 11421 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 11422 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
ed2803da | 11423 | if (unlikely(cs->singlestep_enabled)) { |
e06fcd75 | 11424 | gen_debug_exception(ctxp); |
8cbcb4fa | 11425 | } |
76a66253 | 11426 | /* Generate the return instruction */ |
57fec1fe | 11427 | tcg_gen_exit_tb(0); |
9a64fbe4 | 11428 | } |
806f352d | 11429 | gen_tb_end(tb, num_insns); |
efd7f486 | 11430 | *tcg_ctx.gen_opc_ptr = INDEX_op_end; |
76a66253 | 11431 | if (unlikely(search_pc)) { |
92414b31 | 11432 | j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; |
9a64fbe4 FB |
11433 | lj++; |
11434 | while (lj <= j) | |
ab1103de | 11435 | tcg_ctx.gen_opc_instr_start[lj++] = 0; |
9a64fbe4 | 11436 | } else { |
046d6672 | 11437 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 11438 | tb->icount = num_insns; |
9a64fbe4 | 11439 | } |
d9bce9d9 | 11440 | #if defined(DEBUG_DISAS) |
8fec2b8c | 11441 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 11442 | int flags; |
237c0af0 | 11443 | flags = env->bfd_mach; |
76db3ba4 | 11444 | flags |= ctx.le_mode << 16; |
93fcfe39 | 11445 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
f4359b9f | 11446 | log_target_disas(env, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 11447 | qemu_log("\n"); |
9fddaa0c | 11448 | } |
79aceca5 | 11449 | #endif |
79aceca5 FB |
11450 | } |
11451 | ||
1328c2bf | 11452 | void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 11453 | { |
213fe1f5 | 11454 | gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false); |
79aceca5 FB |
11455 | } |
11456 | ||
1328c2bf | 11457 | void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 11458 | { |
213fe1f5 | 11459 | gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true); |
79aceca5 | 11460 | } |
d2856f1a | 11461 | |
1328c2bf | 11462 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) |
d2856f1a | 11463 | { |
25983cad | 11464 | env->nip = tcg_ctx.gen_opc_pc[pc_pos]; |
d2856f1a | 11465 | } |