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update nip when processing exceptions (Jocelyn Mayer)
[mirror_qemu.git] / target-ppc / translate.c
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79aceca5
FB		 1/*
2 * PPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include "dyngen-exec.h"
21#include "cpu.h"
22#include "exec.h"
23#include "disas.h"
24
25//#define DO_SINGLE_STEP
26//#define DO_STEP_FLUSH
9a64fbe4 27//#define DEBUG_DISAS
79aceca5
FB		 28
29enum {
30#define DEF(s, n, copy_size) INDEX_op_ ## s,
31#include "opc.h"
32#undef DEF
33 NB_OPS,
34};
35
36static uint16_t *gen_opc_ptr;
37static uint32_t *gen_opparam_ptr;
38
39#include "gen-op.h"
28b6751f 40
28b6751f 41#define GEN8(func, NAME) \
9a64fbe4
FB		 42static GenOpFunc *NAME ## _table [8] = { \
43NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
44NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
45}; \
46static inline void func(int n) \
47{ \
48 NAME ## _table[n](); \
49}
50
51#define GEN16(func, NAME) \
52static GenOpFunc *NAME ## _table [16] = { \
53NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
54NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
55NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
56NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
57}; \
58static inline void func(int n) \
59{ \
60 NAME ## _table[n](); \
28b6751f
FB		 61}
62
63#define GEN32(func, NAME) \
9a64fbe4
FB		 64static GenOpFunc *NAME ## _table [32] = { \
65NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
66NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
67NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
68NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
69NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
70NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
71NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
72NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
73}; \
74static inline void func(int n) \
75{ \
76 NAME ## _table[n](); \
77}
78
79/* Condition register moves */
80GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
81GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
82GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
83GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
28b6751f 84
fb0eaffc
FB		 85/* Floating point condition and status register moves */
86GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
87GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
88GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
89static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
90 &gen_op_store_T0_fpscri_fpscr0,
91 &gen_op_store_T0_fpscri_fpscr1,
92 &gen_op_store_T0_fpscri_fpscr2,
93 &gen_op_store_T0_fpscri_fpscr3,
94 &gen_op_store_T0_fpscri_fpscr4,
95 &gen_op_store_T0_fpscri_fpscr5,
96 &gen_op_store_T0_fpscri_fpscr6,
97 &gen_op_store_T0_fpscri_fpscr7,
98};
99static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
100{
101 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
102}
103
9a64fbe4
FB		 104/* Segment register moves */
105GEN16(gen_op_load_sr, gen_op_load_sr);
106GEN16(gen_op_store_sr, gen_op_store_sr);
28b6751f 107
9a64fbe4
FB		 108/* General purpose registers moves */
109GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
110GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
111GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
112
113GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
114GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
115GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
28b6751f 116
fb0eaffc
FB		 117/* floating point registers moves */
118GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
119GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
120GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
121GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
122GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
123GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
79aceca5
FB		 124
125static uint8_t spr_access[1024 / 2];
126
127/* internal defines */
128typedef struct DisasContext {
129 struct TranslationBlock *tb;
130 uint32_t *nip;
131 uint32_t opcode;
9a64fbe4
FB		 132 uint32_t exception;
133 /* Time base offset */
79aceca5 134 uint32_t tb_offset;
9a64fbe4
FB		 135 /* Decrementer offset */
136 uint32_t decr_offset;
137 /* Execution mode */
138#if !defined(CONFIG_USER_ONLY)
79aceca5 139 int supervisor;
9a64fbe4
FB		 140#endif
141 /* Routine used to access memory */
142 int mem_idx;
79aceca5
FB		 143} DisasContext;
144
145typedef struct opc_handler_t {
146 /* invalid bits */
147 uint32_t inval;
9a64fbe4
FB		 148 /* instruction type */
149 uint32_t type;
79aceca5
FB		 150 /* handler */
151 void (*handler)(DisasContext *ctx);
152} opc_handler_t;
153
9a64fbe4 154#define RET_EXCP(excp, error) \
79aceca5 155do { \
9a64fbe4
FB		 156 gen_op_queue_exception_err(excp, error); \
157 ctx->exception = excp; \
79aceca5
FB		 158 return; \
159} while (0)
160
9a64fbe4
FB		 161#define RET_INVAL() \
162RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
163
164#define RET_PRIVOPC() \
165RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
166
167#define RET_PRIVREG() \
168RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
79aceca5
FB		 169
170#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
171static void gen_##name (DisasContext *ctx); \
172GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
173static void gen_##name (DisasContext *ctx)
174
79aceca5
FB		 175typedef struct opcode_t {
176 unsigned char opc1, opc2, opc3;
79aceca5
FB		 177 opc_handler_t handler;
178} opcode_t;
179
180/* XXX: move that elsewhere */
181extern FILE *logfile;
182extern int loglevel;
183
79aceca5
FB		 184/*** Instruction decoding ***/
185#define EXTRACT_HELPER(name, shift, nb) \
186static inline uint32_t name (uint32_t opcode) \
187{ \
188 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
189}
190
191#define EXTRACT_SHELPER(name, shift, nb) \
192static inline int32_t name (uint32_t opcode) \
193{ \
194 return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \
195}
196
197/* Opcode part 1 */
198EXTRACT_HELPER(opc1, 26, 6);
199/* Opcode part 2 */
200EXTRACT_HELPER(opc2, 1, 5);
201/* Opcode part 3 */
202EXTRACT_HELPER(opc3, 6, 5);
203/* Update Cr0 flags */
204EXTRACT_HELPER(Rc, 0, 1);
205/* Destination */
206EXTRACT_HELPER(rD, 21, 5);
207/* Source */
208EXTRACT_HELPER(rS, 21, 5);
209/* First operand */
210EXTRACT_HELPER(rA, 16, 5);
211/* Second operand */
212EXTRACT_HELPER(rB, 11, 5);
213/* Third operand */
214EXTRACT_HELPER(rC, 6, 5);
215/*** Get CRn ***/
216EXTRACT_HELPER(crfD, 23, 3);
217EXTRACT_HELPER(crfS, 18, 3);
218EXTRACT_HELPER(crbD, 21, 5);
219EXTRACT_HELPER(crbA, 16, 5);
220EXTRACT_HELPER(crbB, 11, 5);
221/* SPR / TBL */
222EXTRACT_HELPER(SPR, 11, 10);
223/*** Get constants ***/
224EXTRACT_HELPER(IMM, 12, 8);
225/* 16 bits signed immediate value */
226EXTRACT_SHELPER(SIMM, 0, 16);
227/* 16 bits unsigned immediate value */
228EXTRACT_HELPER(UIMM, 0, 16);
229/* Bit count */
230EXTRACT_HELPER(NB, 11, 5);
231/* Shift count */
232EXTRACT_HELPER(SH, 11, 5);
233/* Mask start */
234EXTRACT_HELPER(MB, 6, 5);
235/* Mask end */
236EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 237/* Trap operand */
238EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 239
240EXTRACT_HELPER(CRM, 12, 8);
241EXTRACT_HELPER(FM, 17, 8);
242EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 243EXTRACT_HELPER(FPIMM, 20, 4);
244
79aceca5
FB		 245/*** Jump target decoding ***/
246/* Displacement */
247EXTRACT_SHELPER(d, 0, 16);
248/* Immediate address */
249static inline uint32_t LI (uint32_t opcode)
250{
251 return (opcode >> 0) & 0x03FFFFFC;
252}
253
254static inline uint32_t BD (uint32_t opcode)
255{
256 return (opcode >> 0) & 0xFFFC;
257}
258
259EXTRACT_HELPER(BO, 21, 5);
260EXTRACT_HELPER(BI, 16, 5);
261/* Absolute/relative address */
262EXTRACT_HELPER(AA, 1, 1);
263/* Link */
264EXTRACT_HELPER(LK, 0, 1);
265
266/* Create a mask between <start> and <end> bits */
267static inline uint32_t MASK (uint32_t start, uint32_t end)
268{
269 uint32_t ret;
270
271 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
272 if (start > end)
273 return ~ret;
274
275 return ret;
276}
277
278#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
279__attribute__ ((section(".opcodes"), unused)) \
280static opcode_t opc_##name = { \
281 .opc1 = op1, \
282 .opc2 = op2, \
283 .opc3 = op3, \
79aceca5
FB		 284 .handler = { \
285 .inval = invl, \
9a64fbe4 286 .type = _typ, \
79aceca5
FB		 287 .handler = &gen_##name, \
288 }, \
289}
290
291#define GEN_OPCODE_MARK(name) \
292__attribute__ ((section(".opcodes"), unused)) \
293static opcode_t opc_##name = { \
294 .opc1 = 0xFF, \
295 .opc2 = 0xFF, \
296 .opc3 = 0xFF, \
79aceca5
FB		 297 .handler = { \
298 .inval = 0x00000000, \
9a64fbe4 299 .type = 0x00, \
79aceca5
FB		 300 .handler = NULL, \
301 }, \
302}
303
304/* Start opcode list */
305GEN_OPCODE_MARK(start);
306
307/* Invalid instruction */
9a64fbe4
FB		 308GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
309{
310 RET_INVAL();
311}
312
313/* Special opcode to stop emulation */
314GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
79aceca5 315{
9a64fbe4
FB		 316 gen_op_queue_exception(EXCP_HLT);
317 ctx->exception = EXCP_HLT;
318}
319
320/* Special opcode to call open-firmware */
321GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
322{
323 gen_op_queue_exception(EXCP_OFCALL);
324 ctx->exception = EXCP_OFCALL;
325}
326
327/* Special opcode to call RTAS */
328GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
329{
330 printf("RTAS entry point !\n");
331 gen_op_queue_exception(EXCP_RTASCALL);
332 ctx->exception = EXCP_RTASCALL;
79aceca5
FB		 333}
334
335static opc_handler_t invalid_handler = {
336 .inval = 0xFFFFFFFF,
9a64fbe4 337 .type = PPC_NONE,
79aceca5
FB		 338 .handler = gen_invalid,
339};
340
341/*** Integer arithmetic ***/
342#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
343GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
344{ \
345 gen_op_load_gpr_T0(rA(ctx->opcode)); \
346 gen_op_load_gpr_T1(rB(ctx->opcode)); \
347 gen_op_##name(); \
348 if (Rc(ctx->opcode) != 0) \
349 gen_op_set_Rc0(); \
350 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 351}
352
353#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
354GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
355{ \
356 gen_op_load_gpr_T0(rA(ctx->opcode)); \
357 gen_op_load_gpr_T1(rB(ctx->opcode)); \
358 gen_op_##name(); \
359 if (Rc(ctx->opcode) != 0) \
360 gen_op_set_Rc0_ov(); \
361 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 362}
363
364#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
365GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
366{ \
367 gen_op_load_gpr_T0(rA(ctx->opcode)); \
368 gen_op_##name(); \
369 if (Rc(ctx->opcode) != 0) \
370 gen_op_set_Rc0(); \
371 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 372}
373#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
374GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
375{ \
376 gen_op_load_gpr_T0(rA(ctx->opcode)); \
377 gen_op_##name(); \
378 if (Rc(ctx->opcode) != 0) \
379 gen_op_set_Rc0_ov(); \
380 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 381}
382
383/* Two operands arithmetic functions */
384#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
385__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
386__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
387
388/* Two operands arithmetic functions with no overflow allowed */
389#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
390__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
391
392/* One operand arithmetic functions */
393#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
394__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
395__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
396
397/* add add. addo addo. */
398GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
399/* addc addc. addco addco. */
400GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
401/* adde adde. addeo addeo. */
402GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
403/* addme addme. addmeo addmeo. */
404GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
405/* addze addze. addzeo addzeo. */
406GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
407/* divw divw. divwo divwo. */
408GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
409/* divwu divwu. divwuo divwuo. */
410GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
411/* mulhw mulhw. */
412GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
413/* mulhwu mulhwu. */
414GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
415/* mullw mullw. mullwo mullwo. */
416GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
417/* neg neg. nego nego. */
418GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
419/* subf subf. subfo subfo. */
420GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
421/* subfc subfc. subfco subfco. */
422GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
423/* subfe subfe. subfeo subfeo. */
424GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
425/* subfme subfme. subfmeo subfmeo. */
426GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
427/* subfze subfze. subfzeo subfzeo. */
428GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
429/* addi */
430GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
431{
432 int32_t simm = SIMM(ctx->opcode);
433
434 if (rA(ctx->opcode) == 0) {
435 gen_op_set_T0(simm);
436 } else {
437 gen_op_load_gpr_T0(rA(ctx->opcode));
438 gen_op_addi(simm);
439 }
440 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 441}
442/* addic */
443GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
444{
445 gen_op_load_gpr_T0(rA(ctx->opcode));
446 gen_op_addic(SIMM(ctx->opcode));
447 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 448}
449/* addic. */
450GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
451{
452 gen_op_load_gpr_T0(rA(ctx->opcode));
453 gen_op_addic(SIMM(ctx->opcode));
454 gen_op_set_Rc0();
455 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 456}
457/* addis */
458GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
459{
460 int32_t simm = SIMM(ctx->opcode);
461
462 if (rA(ctx->opcode) == 0) {
463 gen_op_set_T0(simm << 16);
464 } else {
465 gen_op_load_gpr_T0(rA(ctx->opcode));
466 gen_op_addi(simm << 16);
467 }
468 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 469}
470/* mulli */
471GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
472{
473 gen_op_load_gpr_T0(rA(ctx->opcode));
474 gen_op_mulli(SIMM(ctx->opcode));
475 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 476}
477/* subfic */
478GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
479{
480 gen_op_load_gpr_T0(rA(ctx->opcode));
481 gen_op_subfic(SIMM(ctx->opcode));
482 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 483}
484
485/*** Integer comparison ***/
486#define GEN_CMP(name, opc) \
487GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
488{ \
489 gen_op_load_gpr_T0(rA(ctx->opcode)); \
490 gen_op_load_gpr_T1(rB(ctx->opcode)); \
491 gen_op_##name(); \
492 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5
FB		 493}
494
495/* cmp */
496GEN_CMP(cmp, 0x00);
497/* cmpi */
498GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
499{
500 gen_op_load_gpr_T0(rA(ctx->opcode));
501 gen_op_cmpi(SIMM(ctx->opcode));
502 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 503}
504/* cmpl */
505GEN_CMP(cmpl, 0x01);
506/* cmpli */
507GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
508{
509 gen_op_load_gpr_T0(rA(ctx->opcode));
510 gen_op_cmpli(UIMM(ctx->opcode));
511 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 512}
513
514/*** Integer logical ***/
515#define __GEN_LOGICAL2(name, opc2, opc3) \
516GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
517{ \
518 gen_op_load_gpr_T0(rS(ctx->opcode)); \
519 gen_op_load_gpr_T1(rB(ctx->opcode)); \
520 gen_op_##name(); \
521 if (Rc(ctx->opcode) != 0) \
522 gen_op_set_Rc0(); \
523 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 524}
525#define GEN_LOGICAL2(name, opc) \
526__GEN_LOGICAL2(name, 0x1C, opc)
527
528#define GEN_LOGICAL1(name, opc) \
529GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
530{ \
531 gen_op_load_gpr_T0(rS(ctx->opcode)); \
532 gen_op_##name(); \
533 if (Rc(ctx->opcode) != 0) \
534 gen_op_set_Rc0(); \
535 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 536}
537
538/* and & and. */
539GEN_LOGICAL2(and, 0x00);
540/* andc & andc. */
541GEN_LOGICAL2(andc, 0x01);
542/* andi. */
543GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
544{
545 gen_op_load_gpr_T0(rS(ctx->opcode));
546 gen_op_andi_(UIMM(ctx->opcode));
547 gen_op_set_Rc0();
548 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 549}
550/* andis. */
551GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
552{
553 gen_op_load_gpr_T0(rS(ctx->opcode));
554 gen_op_andi_(UIMM(ctx->opcode) << 16);
555 gen_op_set_Rc0();
556 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 557}
558
559/* cntlzw */
560GEN_LOGICAL1(cntlzw, 0x00);
561/* eqv & eqv. */
562GEN_LOGICAL2(eqv, 0x08);
563/* extsb & extsb. */
564GEN_LOGICAL1(extsb, 0x1D);
565/* extsh & extsh. */
566GEN_LOGICAL1(extsh, 0x1C);
567/* nand & nand. */
568GEN_LOGICAL2(nand, 0x0E);
569/* nor & nor. */
570GEN_LOGICAL2(nor, 0x03);
9a64fbe4 571
79aceca5 572/* or & or. */
9a64fbe4
FB		 573GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
574{
575 gen_op_load_gpr_T0(rS(ctx->opcode));
576 /* Optimisation for mr case */
577 if (rS(ctx->opcode) != rB(ctx->opcode)) {
578 gen_op_load_gpr_T1(rB(ctx->opcode));
579 gen_op_or();
580 }
581 if (Rc(ctx->opcode) != 0)
582 gen_op_set_Rc0();
583 gen_op_store_T0_gpr(rA(ctx->opcode));
584}
585
79aceca5
FB		 586/* orc & orc. */
587GEN_LOGICAL2(orc, 0x0C);
588/* xor & xor. */
9a64fbe4
FB		 589GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
590{
591 gen_op_load_gpr_T0(rS(ctx->opcode));
592 /* Optimisation for "set to zero" case */
593 if (rS(ctx->opcode) != rB(ctx->opcode)) {
594 gen_op_load_gpr_T1(rB(ctx->opcode));
595 gen_op_xor();
596 } else {
597 gen_op_set_T0(0);
598 }
599 if (Rc(ctx->opcode) != 0)
600 gen_op_set_Rc0();
601 gen_op_store_T0_gpr(rA(ctx->opcode));
602}
79aceca5
FB		 603/* ori */
604GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
605{
606 uint32_t uimm = UIMM(ctx->opcode);
607
9a64fbe4
FB		 608 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
609 /* NOP */
610 return;
79aceca5 611 }
79aceca5 612 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 613 if (uimm != 0)
79aceca5
FB		 614 gen_op_ori(uimm);
615 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 616}
617/* oris */
618GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
619{
620 uint32_t uimm = UIMM(ctx->opcode);
621
9a64fbe4
FB		 622 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
623 /* NOP */
624 return;
79aceca5 625 }
79aceca5 626 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 627 if (uimm != 0)
79aceca5
FB		 628 gen_op_ori(uimm << 16);
629 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 630}
631/* xori */
632GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
633{
9a64fbe4
FB		 634 uint32_t uimm = UIMM(ctx->opcode);
635
636 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
637 /* NOP */
638 return;
639 }
79aceca5 640 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 641 if (uimm != 0)
79aceca5
FB		 642 gen_op_xori(UIMM(ctx->opcode));
643 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 644}
645
646/* xoris */
647GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
648{
9a64fbe4
FB		 649 uint32_t uimm = UIMM(ctx->opcode);
650
651 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
652 /* NOP */
653 return;
654 }
79aceca5 655 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 656 if (uimm != 0)
79aceca5
FB		 657 gen_op_xori(UIMM(ctx->opcode) << 16);
658 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 659}
660
661/*** Integer rotate ***/
662/* rlwimi & rlwimi. */
663GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
664{
665 uint32_t mb, me;
666
667 mb = MB(ctx->opcode);
668 me = ME(ctx->opcode);
669 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 670 gen_op_load_gpr_T1(rA(ctx->opcode));
79aceca5
FB		 671 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
672 if (Rc(ctx->opcode) != 0)
673 gen_op_set_Rc0();
674 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 675}
676/* rlwinm & rlwinm. */
677GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
678{
679 uint32_t mb, me, sh;
680
681 sh = SH(ctx->opcode);
682 mb = MB(ctx->opcode);
683 me = ME(ctx->opcode);
684 gen_op_load_gpr_T0(rS(ctx->opcode));
79aceca5
FB		 685 if (mb == 0) {
686 if (me == 31) {
687 gen_op_rotlwi(sh);
688 goto store;
689 } else if (me == (31 - sh)) {
690 gen_op_slwi(sh);
691 goto store;
692 } else if (sh == 0) {
693 gen_op_andi_(MASK(0, me));
694 goto store;
695 }
696 } else if (me == 31) {
697 if (sh == (32 - mb)) {
698 gen_op_srwi(mb);
699 goto store;
700 } else if (sh == 0) {
701 gen_op_andi_(MASK(mb, 31));
702 goto store;
703 }
704 }
705 gen_op_rlwinm(sh, MASK(mb, me));
706store:
707 if (Rc(ctx->opcode) != 0)
708 gen_op_set_Rc0();
709 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 710}
711/* rlwnm & rlwnm. */
712GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
713{
714 uint32_t mb, me;
715
716 mb = MB(ctx->opcode);
717 me = ME(ctx->opcode);
718 gen_op_load_gpr_T0(rS(ctx->opcode));
719 gen_op_load_gpr_T1(rB(ctx->opcode));
720 if (mb == 0 && me == 31) {
721 gen_op_rotl();
722 } else
723 {
724 gen_op_rlwnm(MASK(mb, me));
725 }
726 if (Rc(ctx->opcode) != 0)
727 gen_op_set_Rc0();
728 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 729}
730
731/*** Integer shift ***/
732/* slw & slw. */
733__GEN_LOGICAL2(slw, 0x18, 0x00);
734/* sraw & sraw. */
735__GEN_LOGICAL2(sraw, 0x18, 0x18);
736/* srawi & srawi. */
737GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
738{
739 gen_op_load_gpr_T0(rS(ctx->opcode));
740 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
741 if (Rc(ctx->opcode) != 0)
742 gen_op_set_Rc0();
743 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 744}
745/* srw & srw. */
746__GEN_LOGICAL2(srw, 0x18, 0x10);
747
748/*** Floating-Point arithmetic ***/
9a64fbe4
FB		 749#define _GEN_FLOAT_ACB(name, op1, op2) \
750GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
751{ \
752 gen_op_reset_scrfx(); \
753 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
754 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
755 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
756 gen_op_f##name(); \
757 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
758 if (Rc(ctx->opcode)) \
759 gen_op_set_Rc1(); \
760}
761
762#define GEN_FLOAT_ACB(name, op2) \
763_GEN_FLOAT_ACB(name, 0x3F, op2); \
764_GEN_FLOAT_ACB(name##s, 0x3B, op2);
765
766#define _GEN_FLOAT_AB(name, op1, op2, inval) \
767GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
768{ \
769 gen_op_reset_scrfx(); \
770 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
771 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
772 gen_op_f##name(); \
773 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
774 if (Rc(ctx->opcode)) \
775 gen_op_set_Rc1(); \
776}
777#define GEN_FLOAT_AB(name, op2, inval) \
778_GEN_FLOAT_AB(name, 0x3F, op2, inval); \
779_GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
780
781#define _GEN_FLOAT_AC(name, op1, op2, inval) \
782GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
783{ \
784 gen_op_reset_scrfx(); \
785 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
786 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
787 gen_op_f##name(); \
788 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
789 if (Rc(ctx->opcode)) \
790 gen_op_set_Rc1(); \
791}
792#define GEN_FLOAT_AC(name, op2, inval) \
793_GEN_FLOAT_AC(name, 0x3F, op2, inval); \
794_GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
795
796#define GEN_FLOAT_B(name, op2, op3) \
797GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
798{ \
799 gen_op_reset_scrfx(); \
800 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
801 gen_op_f##name(); \
802 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
803 if (Rc(ctx->opcode)) \
804 gen_op_set_Rc1(); \
79aceca5
FB		 805}
806
9a64fbe4
FB		 807#define GEN_FLOAT_BS(name, op2) \
808GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
809{ \
810 gen_op_reset_scrfx(); \
811 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
812 gen_op_f##name(); \
813 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
814 if (Rc(ctx->opcode)) \
815 gen_op_set_Rc1(); \
79aceca5
FB		 816}
817
9a64fbe4
FB		 818/* fadd - fadds */
819GEN_FLOAT_AB(add, 0x15, 0x000007C0);
79aceca5 820/* fdiv */
9a64fbe4 821GEN_FLOAT_AB(div, 0x12, 0x000007C0);
79aceca5 822/* fmul */
9a64fbe4 823GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
79aceca5
FB		 824
825/* fres */
9a64fbe4 826GEN_FLOAT_BS(res, 0x18);
79aceca5
FB		 827
828/* frsqrte */
9a64fbe4 829GEN_FLOAT_BS(rsqrte, 0x1A);
79aceca5
FB		 830
831/* fsel */
9a64fbe4 832_GEN_FLOAT_ACB(sel, 0x3F, 0x17);
79aceca5 833/* fsub */
9a64fbe4 834GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
79aceca5
FB		 835/* Optional: */
836/* fsqrt */
9a64fbe4 837GEN_FLOAT_BS(sqrt, 0x16);
79aceca5 838
9a64fbe4 839GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
79aceca5 840{
9a64fbe4
FB		 841 gen_op_reset_scrfx();
842 gen_op_load_fpr_FT0(rB(ctx->opcode));
843 gen_op_fsqrts();
844 gen_op_store_FT0_fpr(rD(ctx->opcode));
845 if (Rc(ctx->opcode))
846 gen_op_set_Rc1();
79aceca5
FB		 847}
848
849/*** Floating-Point multiply-and-add ***/
850/* fmadd */
9a64fbe4 851GEN_FLOAT_ACB(madd, 0x1D);
79aceca5 852/* fmsub */
9a64fbe4 853GEN_FLOAT_ACB(msub, 0x1C);
79aceca5 854/* fnmadd */
9a64fbe4 855GEN_FLOAT_ACB(nmadd, 0x1F);
79aceca5 856/* fnmsub */
9a64fbe4 857GEN_FLOAT_ACB(nmsub, 0x1E);
79aceca5
FB		 858
859/*** Floating-Point round & convert ***/
860/* fctiw */
9a64fbe4 861GEN_FLOAT_B(ctiw, 0x0E, 0x00);
79aceca5 862/* fctiwz */
9a64fbe4 863GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
79aceca5 864/* frsp */
9a64fbe4 865GEN_FLOAT_B(rsp, 0x0C, 0x00);
79aceca5
FB		 866
867/*** Floating-Point compare ***/
868/* fcmpo */
869GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
870{
9a64fbe4
FB		 871 gen_op_reset_scrfx();
872 gen_op_load_fpr_FT0(rA(ctx->opcode));
873 gen_op_load_fpr_FT1(rB(ctx->opcode));
874 gen_op_fcmpo();
875 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 876}
877
878/* fcmpu */
879GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
880{
9a64fbe4
FB		 881 gen_op_reset_scrfx();
882 gen_op_load_fpr_FT0(rA(ctx->opcode));
883 gen_op_load_fpr_FT1(rB(ctx->opcode));
884 gen_op_fcmpu();
885 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 886}
887
9a64fbe4
FB		 888/*** Floating-point move ***/
889/* fabs */
890GEN_FLOAT_B(abs, 0x08, 0x08);
891
892/* fmr - fmr. */
893GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
894{
895 gen_op_reset_scrfx();
896 gen_op_load_fpr_FT0(rB(ctx->opcode));
897 gen_op_store_FT0_fpr(rD(ctx->opcode));
898 if (Rc(ctx->opcode))
899 gen_op_set_Rc1();
900}
901
902/* fnabs */
903GEN_FLOAT_B(nabs, 0x08, 0x04);
904/* fneg */
905GEN_FLOAT_B(neg, 0x08, 0x01);
906
79aceca5
FB		 907/*** Floating-Point status & ctrl register ***/
908/* mcrfs */
909GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
910{
fb0eaffc
FB		 911 gen_op_load_fpscr_T0(crfS(ctx->opcode));
912 gen_op_store_T0_crf(crfD(ctx->opcode));
913 gen_op_clear_fpscr(crfS(ctx->opcode));
79aceca5
FB		 914}
915
916/* mffs */
917GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
918{
28b6751f 919 gen_op_load_fpscr();
fb0eaffc
FB		 920 gen_op_store_FT0_fpr(rD(ctx->opcode));
921 if (Rc(ctx->opcode))
922 gen_op_set_Rc1();
79aceca5
FB		 923}
924
925/* mtfsb0 */
926GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
927{
fb0eaffc
FB		 928 uint8_t crb;
929
930 crb = crbD(ctx->opcode) >> 2;
931 gen_op_load_fpscr_T0(crb);
932 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
933 gen_op_store_T0_fpscr(crb);
934 if (Rc(ctx->opcode))
935 gen_op_set_Rc1();
79aceca5
FB		 936}
937
938/* mtfsb1 */
939GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
940{
fb0eaffc
FB		 941 uint8_t crb;
942
943 crb = crbD(ctx->opcode) >> 2;
944 gen_op_load_fpscr_T0(crb);
945 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
946 gen_op_store_T0_fpscr(crb);
947 if (Rc(ctx->opcode))
948 gen_op_set_Rc1();
79aceca5
FB		 949}
950
951/* mtfsf */
952GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
953{
fb0eaffc 954 gen_op_load_fpr_FT0(rB(ctx->opcode));
28b6751f 955 gen_op_store_fpscr(FM(ctx->opcode));
fb0eaffc
FB		 956 if (Rc(ctx->opcode))
957 gen_op_set_Rc1();
79aceca5
FB		 958}
959
960/* mtfsfi */
961GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
962{
fb0eaffc
FB		 963 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
964 if (Rc(ctx->opcode))
965 gen_op_set_Rc1();
79aceca5
FB		 966}
967
968/*** Integer load ***/
9a64fbe4
FB		 969#if defined(CONFIG_USER_ONLY)
970#define op_ldst(name) gen_op_##name##_raw()
971#define OP_LD_TABLE(width)
972#define OP_ST_TABLE(width)
973#else
974#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
975#define OP_LD_TABLE(width) \
976static GenOpFunc *gen_op_l##width[] = { \
977 &gen_op_l##width##_user, \
978 &gen_op_l##width##_kernel, \
979}
980#define OP_ST_TABLE(width) \
981static GenOpFunc *gen_op_st##width[] = { \
982 &gen_op_st##width##_user, \
983 &gen_op_st##width##_kernel, \
984}
985#endif
986
987#define GEN_LD(width, opc) \
79aceca5
FB		 988GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
989{ \
990 uint32_t simm = SIMM(ctx->opcode); \
991 if (rA(ctx->opcode) == 0) { \
9a64fbe4 992 gen_op_set_T0(simm); \
79aceca5
FB		 993 } else { \
994 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 995 if (simm != 0) \
996 gen_op_addi(simm); \
79aceca5 997 } \
9a64fbe4 998 op_ldst(l##width); \
79aceca5 999 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1000}
1001
9a64fbe4 1002#define GEN_LDU(width, opc) \
79aceca5
FB		 1003GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1004{ \
9a64fbe4 1005 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1006 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1007 rA(ctx->opcode) == rD(ctx->opcode)) { \
1008 RET_INVAL(); \
1009 } \
79aceca5 1010 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1011 if (simm != 0) \
1012 gen_op_addi(simm); \
1013 op_ldst(l##width); \
79aceca5
FB		 1014 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1015 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1016}
1017
9a64fbe4 1018#define GEN_LDUX(width, opc) \
79aceca5
FB		 1019GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1020{ \
1021 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1022 rA(ctx->opcode) == rD(ctx->opcode)) { \
1023 RET_INVAL(); \
1024 } \
79aceca5
FB		 1025 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1026 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1027 gen_op_add(); \
1028 op_ldst(l##width); \
79aceca5
FB		 1029 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1030 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1031}
1032
9a64fbe4 1033#define GEN_LDX(width, opc2, opc3) \
79aceca5
FB		 1034GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1035{ \
1036 if (rA(ctx->opcode) == 0) { \
1037 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1038 } else { \
1039 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1040 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1041 gen_op_add(); \
79aceca5 1042 } \
9a64fbe4 1043 op_ldst(l##width); \
79aceca5 1044 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1045}
1046
9a64fbe4
FB		 1047#define GEN_LDS(width, op) \
1048OP_LD_TABLE(width); \
1049GEN_LD(width, op | 0x20); \
1050GEN_LDU(width, op | 0x21); \
1051GEN_LDUX(width, op | 0x01); \
1052GEN_LDX(width, 0x17, op | 0x00)
79aceca5
FB		 1053
1054/* lbz lbzu lbzux lbzx */
9a64fbe4 1055GEN_LDS(bz, 0x02);
79aceca5 1056/* lha lhau lhaux lhax */
9a64fbe4 1057GEN_LDS(ha, 0x0A);
79aceca5 1058/* lhz lhzu lhzux lhzx */
9a64fbe4 1059GEN_LDS(hz, 0x08);
79aceca5 1060/* lwz lwzu lwzux lwzx */
9a64fbe4 1061GEN_LDS(wz, 0x00);
79aceca5
FB		 1062
1063/*** Integer store ***/
9a64fbe4 1064#define GEN_ST(width, opc) \
79aceca5
FB		 1065GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1066{ \
1067 uint32_t simm = SIMM(ctx->opcode); \
1068 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1069 gen_op_set_T0(simm); \
79aceca5
FB		 1070 } else { \
1071 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1072 if (simm != 0) \
1073 gen_op_addi(simm); \
79aceca5 1074 } \
9a64fbe4
FB		 1075 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1076 op_ldst(st##width); \
79aceca5
FB		 1077}
1078
9a64fbe4 1079#define GEN_STU(width, opc) \
79aceca5
FB		 1080GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1081{ \
9a64fbe4
FB		 1082 uint32_t simm = SIMM(ctx->opcode); \
1083 if (rA(ctx->opcode) == 0) { \
1084 RET_INVAL(); \
1085 } \
79aceca5 1086 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1087 if (simm != 0) \
1088 gen_op_addi(simm); \
79aceca5 1089 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 1090 op_ldst(st##width); \
79aceca5 1091 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1092}
1093
9a64fbe4 1094#define GEN_STUX(width, opc) \
79aceca5
FB		 1095GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1096{ \
9a64fbe4
FB		 1097 if (rA(ctx->opcode) == 0) { \
1098 RET_INVAL(); \
1099 } \
79aceca5
FB		 1100 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1101 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1102 gen_op_add(); \
1103 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1104 op_ldst(st##width); \
79aceca5 1105 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1106}
1107
9a64fbe4 1108#define GEN_STX(width, opc2, opc3) \
79aceca5
FB		 1109GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1110{ \
1111 if (rA(ctx->opcode) == 0) { \
1112 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1113 } else { \
1114 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1115 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1116 gen_op_add(); \
79aceca5 1117 } \
9a64fbe4
FB		 1118 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1119 op_ldst(st##width); \
79aceca5
FB		 1120}
1121
9a64fbe4
FB		 1122#define GEN_STS(width, op) \
1123OP_ST_TABLE(width); \
1124GEN_ST(width, op | 0x20); \
1125GEN_STU(width, op | 0x21); \
1126GEN_STUX(width, op | 0x01); \
1127GEN_STX(width, 0x17, op | 0x00)
79aceca5
FB		 1128
1129/* stb stbu stbux stbx */
9a64fbe4 1130GEN_STS(b, 0x06);
79aceca5 1131/* sth sthu sthux sthx */
9a64fbe4 1132GEN_STS(h, 0x0C);
79aceca5 1133/* stw stwu stwux stwx */
9a64fbe4 1134GEN_STS(w, 0x04);
79aceca5
FB		 1135
1136/*** Integer load and store with byte reverse ***/
1137/* lhbrx */
9a64fbe4
FB		 1138OP_LD_TABLE(hbr);
1139GEN_LDX(hbr, 0x16, 0x18);
79aceca5 1140/* lwbrx */
9a64fbe4
FB		 1141OP_LD_TABLE(wbr);
1142GEN_LDX(wbr, 0x16, 0x10);
79aceca5 1143/* sthbrx */
9a64fbe4
FB		 1144OP_ST_TABLE(hbr);
1145GEN_STX(hbr, 0x16, 0x1C);
79aceca5 1146/* stwbrx */
9a64fbe4
FB		 1147OP_ST_TABLE(wbr);
1148GEN_STX(wbr, 0x16, 0x14);
79aceca5
FB		 1149
1150/*** Integer load and store multiple ***/
9a64fbe4
FB		 1151#if defined(CONFIG_USER_ONLY)
1152#define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1153#else
1154#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1155static GenOpFunc1 *gen_op_lmw[] = {
1156 &gen_op_lmw_user,
1157 &gen_op_lmw_kernel,
1158};
1159static GenOpFunc1 *gen_op_stmw[] = {
1160 &gen_op_stmw_user,
1161 &gen_op_stmw_kernel,
1162};
1163#endif
1164
79aceca5
FB		 1165/* lmw */
1166GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1167{
9a64fbe4
FB		 1168 int simm = SIMM(ctx->opcode);
1169
79aceca5 1170 if (rA(ctx->opcode) == 0) {
9a64fbe4 1171 gen_op_set_T0(simm);
79aceca5
FB		 1172 } else {
1173 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1174 if (simm != 0)
1175 gen_op_addi(simm);
79aceca5 1176 }
9a64fbe4 1177 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 1178}
1179
1180/* stmw */
1181GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1182{
9a64fbe4
FB		 1183 int simm = SIMM(ctx->opcode);
1184
79aceca5 1185 if (rA(ctx->opcode) == 0) {
9a64fbe4 1186 gen_op_set_T0(simm);
79aceca5
FB		 1187 } else {
1188 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1189 if (simm != 0)
1190 gen_op_addi(simm);
79aceca5 1191 }
9a64fbe4 1192 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 1193}
1194
1195/*** Integer load and store strings ***/
9a64fbe4
FB		 1196#if defined(CONFIG_USER_ONLY)
1197#define op_ldsts(name, start) gen_op_##name##_raw(start)
1198#define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1199#else
1200#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1201#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1202static GenOpFunc1 *gen_op_lswi[] = {
1203 &gen_op_lswi_user,
1204 &gen_op_lswi_kernel,
1205};
1206static GenOpFunc3 *gen_op_lswx[] = {
1207 &gen_op_lswx_user,
1208 &gen_op_lswx_kernel,
1209};
1210static GenOpFunc1 *gen_op_stsw[] = {
1211 &gen_op_stsw_user,
1212 &gen_op_stsw_kernel,
1213};
1214#endif
1215
79aceca5 1216/* lswi */
9a64fbe4
FB		 1217/* PPC32 specification says we must generate an exception if
1218 * rA is in the range of registers to be loaded.
1219 * In an other hand, IBM says this is valid, but rA won't be loaded.
1220 * For now, I'll follow the spec...
1221 */
79aceca5
FB		 1222GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1223{
1224 int nb = NB(ctx->opcode);
1225 int start = rD(ctx->opcode);
9a64fbe4 1226 int ra = rA(ctx->opcode);
79aceca5
FB		 1227 int nr;
1228
1229 if (nb == 0)
1230 nb = 32;
1231 nr = nb / 4;
9a64fbe4
FB		 1232 if (((start + nr) > 32 && start <= ra && (start + nr - 32) >= ra) ||
1233 ((start + nr) <= 32 && start <= ra && (start + nr) >= ra)) {
1234 RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
79aceca5 1235 }
9a64fbe4 1236 if (ra == 0) {
79aceca5
FB		 1237 gen_op_set_T0(0);
1238 } else {
9a64fbe4 1239 gen_op_load_gpr_T0(ra);
79aceca5 1240 }
9a64fbe4
FB		 1241 gen_op_set_T1(nb);
1242 op_ldsts(lswi, start);
79aceca5
FB		 1243}
1244
1245/* lswx */
1246GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1247{
9a64fbe4
FB		 1248 int ra = rA(ctx->opcode);
1249 int rb = rB(ctx->opcode);
1250
1251 if (ra == 0) {
1252 gen_op_load_gpr_T0(rb);
1253 ra = rb;
79aceca5 1254 } else {
9a64fbe4
FB		 1255 gen_op_load_gpr_T0(ra);
1256 gen_op_load_gpr_T1(rb);
1257 gen_op_add();
79aceca5 1258 }
9a64fbe4
FB		 1259 gen_op_load_xer_bc();
1260 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 1261}
1262
1263/* stswi */
1264GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1265{
79aceca5
FB		 1266 if (rA(ctx->opcode) == 0) {
1267 gen_op_set_T0(0);
1268 } else {
1269 gen_op_load_gpr_T0(rA(ctx->opcode));
1270 }
9a64fbe4
FB		 1271 gen_op_set_T1(NB(ctx->opcode));
1272 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1273}
1274
1275/* stswx */
1276GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1277{
9a64fbe4
FB		 1278 int ra = rA(ctx->opcode);
1279
1280 if (ra == 0) {
1281 gen_op_load_gpr_T0(rB(ctx->opcode));
1282 ra = rB(ctx->opcode);
79aceca5 1283 } else {
9a64fbe4
FB		 1284 gen_op_load_gpr_T0(ra);
1285 gen_op_load_gpr_T1(rB(ctx->opcode));
1286 gen_op_add();
79aceca5 1287 }
9a64fbe4
FB		 1288 gen_op_load_xer_bc();
1289 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1290}
1291
1292/*** Memory synchronisation ***/
1293/* eieio */
1294GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1295{
79aceca5
FB		 1296}
1297
1298/* isync */
1299GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1300{
79aceca5
FB		 1301}
1302
1303/* lwarx */
9a64fbe4 1304#if defined(CONFIG_USER_ONLY)
985a19d6 1305#define op_lwarx() gen_op_lwarx_raw()
9a64fbe4
FB		 1306#define op_stwcx() gen_op_stwcx_raw()
1307#else
985a19d6
FB		 1308#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1309static GenOpFunc *gen_op_lwarx[] = {
1310 &gen_op_lwarx_user,
1311 &gen_op_lwarx_kernel,
1312};
9a64fbe4
FB		 1313#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1314static GenOpFunc *gen_op_stwcx[] = {
1315 &gen_op_stwcx_user,
1316 &gen_op_stwcx_kernel,
1317};
1318#endif
1319
1320GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
79aceca5 1321{
79aceca5
FB		 1322 if (rA(ctx->opcode) == 0) {
1323 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1324 } else {
1325 gen_op_load_gpr_T0(rA(ctx->opcode));
1326 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1327 gen_op_add();
79aceca5 1328 }
985a19d6 1329 op_lwarx();
79aceca5 1330 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 1331}
1332
1333/* stwcx. */
9a64fbe4 1334GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 1335{
79aceca5
FB		 1336 if (rA(ctx->opcode) == 0) {
1337 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1338 } else {
1339 gen_op_load_gpr_T0(rA(ctx->opcode));
1340 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1341 gen_op_add();
79aceca5 1342 }
9a64fbe4
FB		 1343 gen_op_load_gpr_T1(rS(ctx->opcode));
1344 op_stwcx();
79aceca5
FB		 1345}
1346
1347/* sync */
1348GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1349{
79aceca5
FB		 1350}
1351
1352/*** Floating-point load ***/
9a64fbe4
FB		 1353#define GEN_LDF(width, opc) \
1354GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1355{ \
1356 uint32_t simm = SIMM(ctx->opcode); \
1357 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1358 gen_op_set_T0(simm); \
79aceca5
FB		 1359 } else { \
1360 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1361 if (simm != 0) \
1362 gen_op_addi(simm); \
79aceca5 1363 } \
9a64fbe4
FB		 1364 op_ldst(l##width); \
1365 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1366}
1367
9a64fbe4
FB		 1368#define GEN_LDUF(width, opc) \
1369GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1370{ \
9a64fbe4 1371 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1372 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1373 rA(ctx->opcode) == rD(ctx->opcode)) { \
1374 RET_INVAL(); \
1375 } \
79aceca5 1376 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1377 if (simm != 0) \
1378 gen_op_addi(simm); \
1379 op_ldst(l##width); \
1380 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1381 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1382}
1383
9a64fbe4
FB		 1384#define GEN_LDUXF(width, opc) \
1385GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1386{ \
1387 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1388 rA(ctx->opcode) == rD(ctx->opcode)) { \
1389 RET_INVAL(); \
1390 } \
79aceca5
FB		 1391 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1392 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1393 gen_op_add(); \
1394 op_ldst(l##width); \
1395 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1396 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1397}
1398
9a64fbe4
FB		 1399#define GEN_LDXF(width, opc2, opc3) \
1400GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1401{ \
1402 if (rA(ctx->opcode) == 0) { \
1403 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1404 } else { \
1405 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1406 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1407 gen_op_add(); \
79aceca5 1408 } \
9a64fbe4
FB		 1409 op_ldst(l##width); \
1410 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1411}
1412
9a64fbe4
FB		 1413#define GEN_LDFS(width, op) \
1414OP_LD_TABLE(width); \
1415GEN_LDF(width, op | 0x20); \
1416GEN_LDUF(width, op | 0x21); \
1417GEN_LDUXF(width, op | 0x01); \
1418GEN_LDXF(width, 0x17, op | 0x00)
79aceca5
FB		 1419
1420/* lfd lfdu lfdux lfdx */
9a64fbe4 1421GEN_LDFS(fd, 0x12);
79aceca5 1422/* lfs lfsu lfsux lfsx */
9a64fbe4 1423GEN_LDFS(fs, 0x10);
79aceca5
FB		 1424
1425/*** Floating-point store ***/
1426#define GEN_STF(width, opc) \
9a64fbe4 1427GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1428{ \
1429 uint32_t simm = SIMM(ctx->opcode); \
1430 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1431 gen_op_set_T0(simm); \
79aceca5
FB		 1432 } else { \
1433 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1434 if (simm != 0) \
1435 gen_op_addi(simm); \
79aceca5 1436 } \
9a64fbe4
FB		 1437 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1438 op_ldst(st##width); \
79aceca5
FB		 1439}
1440
9a64fbe4
FB		 1441#define GEN_STUF(width, opc) \
1442GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1443{ \
9a64fbe4
FB		 1444 uint32_t simm = SIMM(ctx->opcode); \
1445 if (rA(ctx->opcode) == 0) { \
1446 RET_INVAL(); \
1447 } \
79aceca5 1448 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1449 if (simm != 0) \
1450 gen_op_addi(simm); \
1451 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1452 op_ldst(st##width); \
79aceca5 1453 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1454}
1455
9a64fbe4
FB		 1456#define GEN_STUXF(width, opc) \
1457GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5 1458{ \
9a64fbe4
FB		 1459 if (rA(ctx->opcode) == 0) { \
1460 RET_INVAL(); \
1461 } \
79aceca5
FB		 1462 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1463 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1464 gen_op_add(); \
1465 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1466 op_ldst(st##width); \
79aceca5 1467 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1468}
1469
9a64fbe4
FB		 1470#define GEN_STXF(width, opc2, opc3) \
1471GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1472{ \
1473 if (rA(ctx->opcode) == 0) { \
1474 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1475 } else { \
1476 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1477 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1478 gen_op_add(); \
79aceca5 1479 } \
9a64fbe4
FB		 1480 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1481 op_ldst(st##width); \
79aceca5
FB		 1482}
1483
9a64fbe4
FB		 1484#define GEN_STFS(width, op) \
1485OP_ST_TABLE(width); \
1486GEN_STF(width, op | 0x20); \
1487GEN_STUF(width, op | 0x21); \
1488GEN_STUXF(width, op | 0x01); \
1489GEN_STXF(width, 0x17, op | 0x00)
79aceca5
FB		 1490
1491/* stfd stfdu stfdux stfdx */
9a64fbe4 1492GEN_STFS(fd, 0x16);
79aceca5 1493/* stfs stfsu stfsux stfsx */
9a64fbe4 1494GEN_STFS(fs, 0x14);
79aceca5
FB		 1495
1496/* Optional: */
1497/* stfiwx */
1498GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1499{
9a64fbe4 1500 RET_INVAL();
79aceca5
FB		 1501}
1502
1503/*** Branch ***/
1504#define GEN_BCOND(name, opc1, opc2, opc3, prologue, \
9a64fbe4 1505 bl_ctr, b_ctr, bl_ctrz, b_ctrz, b, bl, \
79aceca5
FB		 1506 bl_ctr_true, b_ctr_true, bl_ctrz_true, b_ctrz_true, bl_true, b_true, \
1507 bl_ctr_false, b_ctr_false, bl_ctrz_false, b_ctrz_false, bl_false, b_false) \
1508GEN_HANDLER(name, opc1, opc2, opc3, 0x00000000, PPC_FLOW) \
1509{ \
1510 __attribute__ ((unused)) uint32_t target; \
1511 uint32_t bo = BO(ctx->opcode); \
1512 uint32_t bi = BI(ctx->opcode); \
1513 uint32_t mask; \
9a64fbe4
FB		 1514 gen_op_update_tb(ctx->tb_offset); \
1515 gen_op_update_decr(ctx->decr_offset); \
1516 gen_op_process_exceptions((uint32_t)ctx->nip - 4); \
79aceca5 1517 prologue; \
9a64fbe4 1518/* gen_op_set_T1((uint32_t)ctx->tb);*/ \
79aceca5
FB		 1519 if ((bo & 0x4) == 0) \
1520 gen_op_dec_ctr(); \
1521 if (bo & 0x10) { \
1522 /* No CR condition */ \
1523 switch (bo & 0x6) { \
1524 case 0: \
1525 if (LK(ctx->opcode)) { \
1526 bl_ctr; \
1527 } else { \
1528 b_ctr; \
1529 } \
1530 break; \
1531 case 2: \
1532 if (LK(ctx->opcode)) { \
1533 bl_ctrz; \
1534 } else { \
1535 b_ctrz; \
1536 } \
1537 break; \
1538 case 4: \
1539 case 6: \
9a64fbe4
FB		 1540 if (LK(ctx->opcode)) { \
1541 bl; \
1542 } else { \
79aceca5 1543 b; \
9a64fbe4 1544 } \
79aceca5
FB		 1545 break; \
1546 default: \
1547 printf("ERROR: %s: unhandled ba case (%d)\n", __func__, bo); \
9a64fbe4 1548 RET_INVAL(); \
79aceca5
FB		 1549 break; \
1550 } \
1551 } else { \
1552 mask = 1 << (3 - (bi & 0x03)); \
1553 gen_op_load_crf_T0(bi >> 2); \
1554 if (bo & 0x8) { \
1555 switch (bo & 0x6) { \
1556 case 0: \
1557 if (LK(ctx->opcode)) { \
1558 bl_ctr_true; \
1559 } else { \
1560 b_ctr_true; \
1561 } \
1562 break; \
1563 case 2: \
1564 if (LK(ctx->opcode)) { \
1565 bl_ctrz_true; \
1566 } else { \
1567 b_ctrz_true; \
1568 } \
1569 break; \
1570 case 4: \
1571 case 6: \
1572 if (LK(ctx->opcode)) { \
1573 bl_true; \
1574 } else { \
1575 b_true; \
1576 } \
1577 break; \
1578 default: \
1579 printf("ERROR: %s: unhandled b case (%d)\n", __func__, bo); \
9a64fbe4 1580 RET_INVAL(); \
79aceca5
FB		 1581 break; \
1582 } \
1583 } else { \
1584 switch (bo & 0x6) { \
1585 case 0: \
1586 if (LK(ctx->opcode)) { \
1587 bl_ctr_false; \
1588 } else { \
1589 b_ctr_false; \
1590 } \
1591 break; \
1592 case 2: \
1593 if (LK(ctx->opcode)) { \
1594 bl_ctrz_false; \
1595 } else { \
1596 b_ctrz_false; \
1597 } \
1598 break; \
1599 case 4: \
1600 case 6: \
1601 if (LK(ctx->opcode)) { \
1602 bl_false; \
1603 } else { \
1604 b_false; \
1605 } \
1606 break; \
1607 default: \
1608 printf("ERROR: %s: unhandled bn case (%d)\n", __func__, bo); \
9a64fbe4 1609 RET_INVAL(); \
79aceca5
FB		 1610 break; \
1611 } \
1612 } \
1613 } \
9a64fbe4 1614 ctx->exception = EXCP_BRANCH; \
79aceca5
FB		 1615}
1616
1617/* b ba bl bla */
1618GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1619{
1620 uint32_t li = s_ext24(LI(ctx->opcode)), target;
1621
9a64fbe4
FB		 1622 gen_op_update_tb(ctx->tb_offset);
1623 gen_op_update_decr(ctx->decr_offset);
1624 gen_op_process_exceptions((uint32_t)ctx->nip - 4);
79aceca5
FB		 1625 if (AA(ctx->opcode) == 0)
1626 target = (uint32_t)ctx->nip + li - 4;
1627 else
9a64fbe4
FB		 1628 target = li;
1629// gen_op_set_T1((uint32_t)ctx->tb);
1630 if (LK(ctx->opcode)) {
1631 gen_op_bl(target, (uint32_t)ctx->nip);
1632 } else {
79aceca5 1633 gen_op_b(target);
9a64fbe4
FB		 1634 }
1635 ctx->exception = EXCP_BRANCH;
79aceca5
FB		 1636}
1637
1638/* bc bca bcl bcla */
1639GEN_BCOND(bc, 0x10, 0xFF, 0xFF,
1640 do {
1641 uint32_t li = s_ext16(BD(ctx->opcode));
1642 if (AA(ctx->opcode) == 0) {
1643 target = (uint32_t)ctx->nip + li - 4;
1644 } else {
1645 target = li;
1646 }
1647 } while (0),
1648 gen_op_bl_ctr((uint32_t)ctx->nip, target),
1649 gen_op_b_ctr((uint32_t)ctx->nip, target),
1650 gen_op_bl_ctrz((uint32_t)ctx->nip, target),
1651 gen_op_b_ctrz((uint32_t)ctx->nip, target),
1652 gen_op_b(target),
9a64fbe4 1653 gen_op_bl(target, (uint32_t)ctx->nip),
79aceca5
FB		 1654 gen_op_bl_ctr_true((uint32_t)ctx->nip, target, mask),
1655 gen_op_b_ctr_true((uint32_t)ctx->nip, target, mask),
1656 gen_op_bl_ctrz_true((uint32_t)ctx->nip, target, mask),
1657 gen_op_b_ctrz_true((uint32_t)ctx->nip, target, mask),
1658 gen_op_bl_true((uint32_t)ctx->nip, target, mask),
1659 gen_op_b_true((uint32_t)ctx->nip, target, mask),
1660 gen_op_bl_ctr_false((uint32_t)ctx->nip, target, mask),
1661 gen_op_b_ctr_false((uint32_t)ctx->nip, target, mask),
1662 gen_op_bl_ctrz_false((uint32_t)ctx->nip, target, mask),
1663 gen_op_b_ctrz_false((uint32_t)ctx->nip, target, mask),
1664 gen_op_bl_false((uint32_t)ctx->nip, target, mask),
1665 gen_op_b_false((uint32_t)ctx->nip, target, mask));
1666
1667/* bcctr bcctrl */
1668GEN_BCOND(bcctr, 0x13, 0x10, 0x10, do { } while (0),
1669 gen_op_bctrl_ctr((uint32_t)ctx->nip),
1670 gen_op_bctr_ctr((uint32_t)ctx->nip),
1671 gen_op_bctrl_ctrz((uint32_t)ctx->nip),
1672 gen_op_bctr_ctrz((uint32_t)ctx->nip),
1673 gen_op_bctr(),
9a64fbe4 1674 gen_op_bctrl((uint32_t)ctx->nip),
79aceca5
FB		 1675 gen_op_bctrl_ctr_true((uint32_t)ctx->nip, mask),
1676 gen_op_bctr_ctr_true((uint32_t)ctx->nip, mask),
1677 gen_op_bctrl_ctrz_true((uint32_t)ctx->nip, mask),
1678 gen_op_bctr_ctrz_true((uint32_t)ctx->nip, mask),
1679 gen_op_bctrl_true((uint32_t)ctx->nip, mask),
1680 gen_op_bctr_true((uint32_t)ctx->nip, mask),
1681 gen_op_bctrl_ctr_false((uint32_t)ctx->nip, mask),
1682 gen_op_bctr_ctr_false((uint32_t)ctx->nip, mask),
1683 gen_op_bctrl_ctrz_false((uint32_t)ctx->nip, mask),
1684 gen_op_bctr_ctrz_false((uint32_t)ctx->nip, mask),
1685 gen_op_bctrl_false((uint32_t)ctx->nip, mask),
1686 gen_op_bctr_false((uint32_t)ctx->nip, mask))
1687
1688/* bclr bclrl */
1689GEN_BCOND(bclr, 0x13, 0x10, 0x00, do { } while (0),
1690 gen_op_blrl_ctr((uint32_t)ctx->nip),
1691 gen_op_blr_ctr((uint32_t)ctx->nip),
1692 gen_op_blrl_ctrz((uint32_t)ctx->nip),
1693 gen_op_blr_ctrz((uint32_t)ctx->nip),
1694 gen_op_blr(),
9a64fbe4 1695 gen_op_blrl((uint32_t)ctx->nip),
79aceca5
FB		 1696 gen_op_blrl_ctr_true((uint32_t)ctx->nip, mask),
1697 gen_op_blr_ctr_true((uint32_t)ctx->nip, mask),
1698 gen_op_blrl_ctrz_true((uint32_t)ctx->nip, mask),
1699 gen_op_blr_ctrz_true((uint32_t)ctx->nip, mask),
1700 gen_op_blrl_true((uint32_t)ctx->nip, mask),
1701 gen_op_blr_true((uint32_t)ctx->nip, mask),
1702 gen_op_blrl_ctr_false((uint32_t)ctx->nip, mask),
1703 gen_op_blr_ctr_false((uint32_t)ctx->nip, mask),
1704 gen_op_blrl_ctrz_false((uint32_t)ctx->nip, mask),
1705 gen_op_blr_ctrz_false((uint32_t)ctx->nip, mask),
1706 gen_op_blrl_false((uint32_t)ctx->nip, mask),
1707 gen_op_blr_false((uint32_t)ctx->nip, mask))
1708
1709/*** Condition register logical ***/
1710#define GEN_CRLOGIC(op, opc) \
1711GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1712{ \
1713 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1714 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1715 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1716 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1717 gen_op_##op(); \
1718 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1719 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1720 3 - (crbD(ctx->opcode) & 0x03)); \
1721 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 1722}
1723
1724/* crand */
1725GEN_CRLOGIC(and, 0x08)
1726/* crandc */
1727GEN_CRLOGIC(andc, 0x04)
1728/* creqv */
1729GEN_CRLOGIC(eqv, 0x09)
1730/* crnand */
1731GEN_CRLOGIC(nand, 0x07)
1732/* crnor */
1733GEN_CRLOGIC(nor, 0x01)
1734/* cror */
1735GEN_CRLOGIC(or, 0x0E)
1736/* crorc */
1737GEN_CRLOGIC(orc, 0x0D)
1738/* crxor */
1739GEN_CRLOGIC(xor, 0x06)
1740/* mcrf */
1741GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1742{
1743 gen_op_load_crf_T0(crfS(ctx->opcode));
1744 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1745}
1746
1747/*** System linkage ***/
1748/* rfi (supervisor only) */
1749GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1750{
9a64fbe4
FB		 1751#if defined(CONFIG_USER_ONLY)
1752 RET_PRIVOPC();
1753#else
1754 /* Restore CPU state */
1755 if (!ctx->supervisor) {
1756 RET_PRIVOPC();
1757 }
1758 gen_op_rfi();
1759 ctx->exception = EXCP_RFI;
1760#endif
79aceca5
FB		 1761}
1762
1763/* sc */
1764GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1765{
9a64fbe4
FB		 1766#if defined(CONFIG_USER_ONLY)
1767 gen_op_queue_exception(EXCP_SYSCALL_USER);
1768#else
1769 gen_op_queue_exception(EXCP_SYSCALL);
1770#endif
1771 ctx->exception = EXCP_SYSCALL;
79aceca5
FB		 1772}
1773
1774/*** Trap ***/
1775/* tw */
1776GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1777{
9a64fbe4
FB		 1778 gen_op_load_gpr_T0(rA(ctx->opcode));
1779 gen_op_load_gpr_T1(rB(ctx->opcode));
1780 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 1781}
1782
1783/* twi */
1784GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1785{
9a64fbe4
FB		 1786 gen_op_load_gpr_T0(rA(ctx->opcode));
1787#if 0
1788 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1789 SIMM(ctx->opcode), TO(ctx->opcode));
1790#endif
1791 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
79aceca5
FB		 1792}
1793
1794/*** Processor control ***/
1795static inline int check_spr_access (int spr, int rw, int supervisor)
1796{
1797 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1798
9a64fbe4
FB		 1799#if 0
1800 if (spr != LR && spr != CTR) {
1801 if (loglevel > 0) {
1802 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1803 SPR_ENCODE(spr), supervisor, rw, rights,
1804 (rights >> ((2 * supervisor) + rw)) & 1);
1805 } else {
1806 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1807 SPR_ENCODE(spr), supervisor, rw, rights,
1808 (rights >> ((2 * supervisor) + rw)) & 1);
1809 }
1810 }
1811#endif
1812 if (rights == 0)
1813 return -1;
79aceca5
FB		 1814 rights = rights >> (2 * supervisor);
1815 rights = rights >> rw;
1816
1817 return rights & 1;
1818}
1819
1820/* mcrxr */
1821GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1822{
1823 gen_op_load_xer_cr();
1824 gen_op_store_T0_crf(crfD(ctx->opcode));
1825 gen_op_clear_xer_cr();
79aceca5
FB		 1826}
1827
1828/* mfcr */
1829GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1830{
1831 gen_op_load_cr();
1832 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1833}
1834
1835/* mfmsr */
1836GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1837{
9a64fbe4
FB		 1838#if defined(CONFIG_USER_ONLY)
1839 RET_PRIVREG();
1840#else
1841 if (!ctx->supervisor) {
1842 RET_PRIVREG();
1843 }
79aceca5
FB		 1844 gen_op_load_msr();
1845 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 1846#endif
79aceca5
FB		 1847}
1848
1849/* mfspr */
1850GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1851{
1852 uint32_t sprn = SPR(ctx->opcode);
1853
9a64fbe4
FB		 1854#if defined(CONFIG_USER_ONLY)
1855 switch (check_spr_access(sprn, 0, 0))
1856#else
1857 switch (check_spr_access(sprn, 0, ctx->supervisor))
1858#endif
1859 {
1860 case -1:
1861 RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1862 break;
1863 case 0:
1864 RET_PRIVREG();
1865 break;
1866 default:
1867 break;
79aceca5 1868 }
9a64fbe4
FB		 1869 switch (sprn) {
1870 case XER:
79aceca5
FB		 1871 gen_op_load_xer();
1872 break;
9a64fbe4
FB		 1873 case LR:
1874 gen_op_load_lr();
1875 break;
1876 case CTR:
1877 gen_op_load_ctr();
1878 break;
1879 case IBAT0U:
1880 gen_op_load_ibat(0, 0);
1881 break;
1882 case IBAT1U:
1883 gen_op_load_ibat(0, 1);
1884 break;
1885 case IBAT2U:
1886 gen_op_load_ibat(0, 2);
1887 break;
1888 case IBAT3U:
1889 gen_op_load_ibat(0, 3);
1890 break;
1891 case IBAT4U:
1892 gen_op_load_ibat(0, 4);
1893 break;
1894 case IBAT5U:
1895 gen_op_load_ibat(0, 5);
1896 break;
1897 case IBAT6U:
1898 gen_op_load_ibat(0, 6);
1899 break;
1900 case IBAT7U:
1901 gen_op_load_ibat(0, 7);
1902 break;
1903 case IBAT0L:
1904 gen_op_load_ibat(1, 0);
1905 break;
1906 case IBAT1L:
1907 gen_op_load_ibat(1, 1);
1908 break;
1909 case IBAT2L:
1910 gen_op_load_ibat(1, 2);
1911 break;
1912 case IBAT3L:
1913 gen_op_load_ibat(1, 3);
1914 break;
1915 case IBAT4L:
1916 gen_op_load_ibat(1, 4);
1917 break;
1918 case IBAT5L:
1919 gen_op_load_ibat(1, 5);
1920 break;
1921 case IBAT6L:
1922 gen_op_load_ibat(1, 6);
1923 break;
1924 case IBAT7L:
1925 gen_op_load_ibat(1, 7);
1926 break;
1927 case DBAT0U:
1928 gen_op_load_dbat(0, 0);
1929 break;
1930 case DBAT1U:
1931 gen_op_load_dbat(0, 1);
1932 break;
1933 case DBAT2U:
1934 gen_op_load_dbat(0, 2);
1935 break;
1936 case DBAT3U:
1937 gen_op_load_dbat(0, 3);
1938 break;
1939 case DBAT4U:
1940 gen_op_load_dbat(0, 4);
1941 break;
1942 case DBAT5U:
1943 gen_op_load_dbat(0, 5);
1944 break;
1945 case DBAT6U:
1946 gen_op_load_dbat(0, 6);
1947 break;
1948 case DBAT7U:
1949 gen_op_load_dbat(0, 7);
1950 break;
1951 case DBAT0L:
1952 gen_op_load_dbat(1, 0);
1953 break;
1954 case DBAT1L:
1955 gen_op_load_dbat(1, 1);
1956 break;
1957 case DBAT2L:
1958 gen_op_load_dbat(1, 2);
1959 break;
1960 case DBAT3L:
1961 gen_op_load_dbat(1, 3);
1962 break;
1963 case DBAT4L:
1964 gen_op_load_dbat(1, 4);
1965 break;
1966 case DBAT5L:
1967 gen_op_load_dbat(1, 5);
1968 break;
1969 case DBAT6L:
1970 gen_op_load_dbat(1, 6);
1971 break;
1972 case DBAT7L:
1973 gen_op_load_dbat(1, 7);
1974 break;
1975 case SDR1:
1976 gen_op_load_sdr1();
1977 break;
1978 case V_TBL:
79aceca5
FB		 1979 gen_op_update_tb(ctx->tb_offset);
1980 ctx->tb_offset = 0;
9a64fbe4 1981 /* TBL is still in T0 */
79aceca5 1982 break;
9a64fbe4 1983 case V_TBU:
79aceca5
FB		 1984 gen_op_update_tb(ctx->tb_offset);
1985 ctx->tb_offset = 0;
9a64fbe4
FB		 1986 gen_op_load_tb(1);
1987 break;
1988 case DECR:
1989 gen_op_update_decr(ctx->decr_offset);
1990 ctx->decr_offset = 0;
1991 /* decr is still in T0 */
79aceca5
FB		 1992 break;
1993 default:
1994 gen_op_load_spr(sprn);
1995 break;
1996 }
9a64fbe4 1997 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1998}
1999
2000/* mftb */
2001GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
2002{
2003 uint32_t sprn = SPR(ctx->opcode);
2004
79aceca5 2005 /* We need to update the time base before reading it */
9a64fbe4
FB		 2006 switch (sprn) {
2007 case V_TBL:
79aceca5 2008 gen_op_update_tb(ctx->tb_offset);
9a64fbe4 2009 /* TBL is still in T0 */
79aceca5 2010 break;
9a64fbe4 2011 case V_TBU:
79aceca5 2012 gen_op_update_tb(ctx->tb_offset);
9a64fbe4 2013 gen_op_load_tb(1);
79aceca5
FB		 2014 break;
2015 default:
9a64fbe4 2016 RET_INVAL();
79aceca5
FB		 2017 break;
2018 }
9a64fbe4
FB		 2019 ctx->tb_offset = 0;
2020 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2021}
2022
2023/* mtcrf */
2024GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
2025{
2026 gen_op_load_gpr_T0(rS(ctx->opcode));
2027 gen_op_store_cr(CRM(ctx->opcode));
79aceca5
FB		 2028}
2029
2030/* mtmsr */
2031GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
2032{
9a64fbe4
FB		 2033#if defined(CONFIG_USER_ONLY)
2034 RET_PRIVREG();
2035#else
2036 if (!ctx->supervisor) {
2037 RET_PRIVREG();
2038 }
79aceca5
FB		 2039 gen_op_load_gpr_T0(rS(ctx->opcode));
2040 gen_op_store_msr();
2041 /* Must stop the translation as machine state (may have) changed */
9a64fbe4
FB		 2042 ctx->exception = EXCP_MTMSR;
2043#endif
79aceca5
FB		 2044}
2045
2046/* mtspr */
2047GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
2048{
2049 uint32_t sprn = SPR(ctx->opcode);
2050
9a64fbe4
FB		 2051#if 0
2052 if (loglevel > 0) {
2053 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
2054 rS(ctx->opcode), sprn);
2055 }
2056#endif
2057#if defined(CONFIG_USER_ONLY)
2058 switch (check_spr_access(sprn, 1, 0))
2059#else
2060 switch (check_spr_access(sprn, 1, ctx->supervisor))
2061#endif
2062 {
2063 case -1:
2064 RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
2065 break;
2066 case 0:
2067 RET_PRIVREG();
2068 break;
2069 default:
2070 break;
2071 }
79aceca5 2072 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4
FB		 2073 switch (sprn) {
2074 case XER:
79aceca5 2075 gen_op_store_xer();
9a64fbe4
FB		 2076 break;
2077 case LR:
2078 gen_op_andi_(~0x03);
2079 gen_op_store_lr();
2080 break;
2081 case CTR:
2082 gen_op_store_ctr();
2083 break;
2084 case IBAT0U:
2085 gen_op_store_ibat(0, 0);
2086 gen_op_tlbia();
2087 break;
2088 case IBAT1U:
2089 gen_op_store_ibat(0, 1);
2090 gen_op_tlbia();
2091 break;
2092 case IBAT2U:
2093 gen_op_store_ibat(0, 2);
2094 gen_op_tlbia();
2095 break;
2096 case IBAT3U:
2097 gen_op_store_ibat(0, 3);
2098 gen_op_tlbia();
2099 break;
2100 case IBAT4U:
2101 gen_op_store_ibat(0, 4);
2102 gen_op_tlbia();
2103 break;
2104 case IBAT5U:
2105 gen_op_store_ibat(0, 5);
2106 gen_op_tlbia();
2107 break;
2108 case IBAT6U:
2109 gen_op_store_ibat(0, 6);
2110 gen_op_tlbia();
2111 break;
2112 case IBAT7U:
2113 gen_op_store_ibat(0, 7);
2114 gen_op_tlbia();
2115 break;
2116 case IBAT0L:
2117 gen_op_store_ibat(1, 0);
2118 gen_op_tlbia();
2119 break;
2120 case IBAT1L:
2121 gen_op_store_ibat(1, 1);
2122 gen_op_tlbia();
2123 break;
2124 case IBAT2L:
2125 gen_op_store_ibat(1, 2);
2126 gen_op_tlbia();
2127 break;
2128 case IBAT3L:
2129 gen_op_store_ibat(1, 3);
2130 gen_op_tlbia();
2131 break;
2132 case IBAT4L:
2133 gen_op_store_ibat(1, 4);
2134 gen_op_tlbia();
2135 break;
2136 case IBAT5L:
2137 gen_op_store_ibat(1, 5);
2138 gen_op_tlbia();
2139 break;
2140 case IBAT6L:
2141 gen_op_store_ibat(1, 6);
2142 gen_op_tlbia();
2143 break;
2144 case IBAT7L:
2145 gen_op_store_ibat(1, 7);
2146 gen_op_tlbia();
2147 break;
2148 case DBAT0U:
2149 gen_op_store_dbat(0, 0);
2150 gen_op_tlbia();
2151 break;
2152 case DBAT1U:
2153 gen_op_store_dbat(0, 1);
2154 gen_op_tlbia();
2155 break;
2156 case DBAT2U:
2157 gen_op_store_dbat(0, 2);
2158 gen_op_tlbia();
2159 break;
2160 case DBAT3U:
2161 gen_op_store_dbat(0, 3);
2162 gen_op_tlbia();
2163 break;
2164 case DBAT4U:
2165 gen_op_store_dbat(0, 4);
2166 gen_op_tlbia();
2167 break;
2168 case DBAT5U:
2169 gen_op_store_dbat(0, 5);
2170 gen_op_tlbia();
2171 break;
2172 case DBAT6U:
2173 gen_op_store_dbat(0, 6);
2174 gen_op_tlbia();
2175 break;
2176 case DBAT7U:
2177 gen_op_store_dbat(0, 7);
2178 gen_op_tlbia();
2179 break;
2180 case DBAT0L:
2181 gen_op_store_dbat(1, 0);
2182 gen_op_tlbia();
2183 break;
2184 case DBAT1L:
2185 gen_op_store_dbat(1, 1);
2186 gen_op_tlbia();
2187 break;
2188 case DBAT2L:
2189 gen_op_store_dbat(1, 2);
2190 gen_op_tlbia();
2191 break;
2192 case DBAT3L:
2193 gen_op_store_dbat(1, 3);
2194 gen_op_tlbia();
2195 break;
2196 case DBAT4L:
2197 gen_op_store_dbat(1, 4);
2198 gen_op_tlbia();
2199 break;
2200 case DBAT5L:
2201 gen_op_store_dbat(1, 5);
2202 gen_op_tlbia();
2203 break;
2204 case DBAT6L:
2205 gen_op_store_dbat(1, 6);
2206 gen_op_tlbia();
2207 break;
2208 case DBAT7L:
2209 gen_op_store_dbat(1, 7);
2210 gen_op_tlbia();
2211 break;
2212 case SDR1:
2213 gen_op_store_sdr1();
2214 gen_op_tlbia();
2215 break;
2216 case O_TBL:
2217 gen_op_store_tb(0);
2218 ctx->tb_offset = 0;
2219 break;
2220 case O_TBU:
2221 gen_op_store_tb(1);
2222 ctx->tb_offset = 0;
2223 break;
2224 case DECR:
2225 gen_op_store_decr();
2226 ctx->decr_offset = 0;
2227 break;
2228 default:
79aceca5 2229 gen_op_store_spr(sprn);
9a64fbe4 2230 break;
79aceca5 2231 }
79aceca5
FB		 2232}
2233
2234/*** Cache management ***/
2235/* For now, all those will be implemented as nop:
2236 * this is valid, regarding the PowerPC specs...
9a64fbe4 2237 * We just have to flush tb while invalidating instruction cache lines...
79aceca5
FB		 2238 */
2239/* dcbf */
9a64fbe4 2240GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
79aceca5 2241{
79aceca5
FB		 2242}
2243
2244/* dcbi (Supervisor only) */
9a64fbe4 2245GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 2246{
9a64fbe4
FB		 2247#if !defined(CONFIG_USER_ONLY)
2248 if (!ctx->supervisor)
2249#endif
2250 {
2251 RET_PRIVOPC();
2252 }
79aceca5
FB		 2253}
2254
2255/* dcdst */
9a64fbe4 2256GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 2257{
79aceca5
FB		 2258}
2259
2260/* dcbt */
9a64fbe4 2261GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
79aceca5 2262{
79aceca5
FB		 2263}
2264
2265/* dcbtst */
9a64fbe4 2266GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
79aceca5 2267{
79aceca5
FB		 2268}
2269
2270/* dcbz */
9a64fbe4
FB		 2271#if defined(CONFIG_USER_ONLY)
2272#define op_dcbz() gen_op_dcbz_raw()
2273#else
2274#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2275static GenOpFunc *gen_op_dcbz[] = {
2276 &gen_op_dcbz_user,
2277 &gen_op_dcbz_kernel,
2278};
2279#endif
2280
2281GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
79aceca5 2282{
fb0eaffc
FB		 2283 if (rA(ctx->opcode) == 0) {
2284 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2285 } else {
2286 gen_op_load_gpr_T0(rA(ctx->opcode));
2287 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2288 gen_op_add();
fb0eaffc 2289 }
9a64fbe4 2290 op_dcbz();
79aceca5
FB		 2291}
2292
2293/* icbi */
9a64fbe4 2294GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
79aceca5 2295{
fb0eaffc
FB		 2296 if (rA(ctx->opcode) == 0) {
2297 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2298 } else {
2299 gen_op_load_gpr_T0(rA(ctx->opcode));
2300 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2301 gen_op_add();
fb0eaffc 2302 }
9a64fbe4 2303 gen_op_icbi();
79aceca5
FB		 2304}
2305
2306/* Optional: */
2307/* dcba */
9a64fbe4 2308GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
79aceca5 2309{
79aceca5
FB		 2310}
2311
2312/*** Segment register manipulation ***/
2313/* Supervisor only: */
2314/* mfsr */
2315GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2316{
9a64fbe4
FB		 2317#if defined(CONFIG_USER_ONLY)
2318 RET_PRIVREG();
2319#else
2320 if (!ctx->supervisor) {
2321 RET_PRIVREG();
2322 }
2323 gen_op_load_sr(SR(ctx->opcode));
2324 gen_op_store_T0_gpr(rD(ctx->opcode));
2325#endif
79aceca5
FB		 2326}
2327
2328/* mfsrin */
9a64fbe4 2329GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 2330{
9a64fbe4
FB		 2331#if defined(CONFIG_USER_ONLY)
2332 RET_PRIVREG();
2333#else
2334 if (!ctx->supervisor) {
2335 RET_PRIVREG();
2336 }
2337 gen_op_load_gpr_T1(rB(ctx->opcode));
2338 gen_op_load_srin();
2339 gen_op_store_T0_gpr(rD(ctx->opcode));
2340#endif
79aceca5
FB		 2341}
2342
2343/* mtsr */
2344GEN_HANDLER(mtsr, 0x1F, 0x12, 0x02, 0x0010F801, PPC_SEGMENT)
2345{
9a64fbe4
FB		 2346#if defined(CONFIG_USER_ONLY)
2347 RET_PRIVREG();
2348#else
2349 if (!ctx->supervisor) {
2350 RET_PRIVREG();
2351 }
2352 gen_op_load_gpr_T0(rS(ctx->opcode));
2353 gen_op_store_sr(SR(ctx->opcode));
2354 gen_op_tlbia();
2355#endif
79aceca5
FB		 2356}
2357
2358/* mtsrin */
9a64fbe4 2359GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 2360{
9a64fbe4
FB		 2361#if defined(CONFIG_USER_ONLY)
2362 RET_PRIVREG();
2363#else
2364 if (!ctx->supervisor) {
2365 RET_PRIVREG();
2366 }
2367 gen_op_load_gpr_T0(rS(ctx->opcode));
2368 gen_op_load_gpr_T1(rB(ctx->opcode));
2369 gen_op_store_srin();
2370 gen_op_tlbia();
2371#endif
79aceca5
FB		 2372}
2373
2374/*** Lookaside buffer management ***/
2375/* Optional & supervisor only: */
2376/* tlbia */
9a64fbe4 2377GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
79aceca5 2378{
9a64fbe4
FB		 2379#if defined(CONFIG_USER_ONLY)
2380 RET_PRIVOPC();
2381#else
2382 if (!ctx->supervisor) {
2383 RET_PRIVOPC();
2384 }
2385 gen_op_tlbia();
2386#endif
79aceca5
FB		 2387}
2388
2389/* tlbie */
9a64fbe4 2390GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
79aceca5 2391{
9a64fbe4
FB		 2392#if defined(CONFIG_USER_ONLY)
2393 RET_PRIVOPC();
2394#else
2395 if (!ctx->supervisor) {
2396 RET_PRIVOPC();
2397 }
2398 gen_op_load_gpr_T0(rB(ctx->opcode));
2399 gen_op_tlbie();
2400#endif
79aceca5
FB		 2401}
2402
2403/* tlbsync */
2404GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFFC01, PPC_MEM)
2405{
9a64fbe4
FB		 2406#if defined(CONFIG_USER_ONLY)
2407 RET_PRIVOPC();
2408#else
2409 if (!ctx->supervisor) {
2410 RET_PRIVOPC();
2411 }
2412 /* This has no effect: it should ensure that all previous
2413 * tlbie have completed
2414 */
2415#endif
79aceca5
FB		 2416}
2417
2418/*** External control ***/
2419/* Optional: */
2420/* eciwx */
9a64fbe4
FB		 2421#if defined(CONFIG_USER_ONLY)
2422#define op_eciwx() gen_op_eciwx_raw()
2423#define op_ecowx() gen_op_ecowx_raw()
2424#else
2425#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2426#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2427static GenOpFunc *gen_op_eciwx[] = {
2428 &gen_op_eciwx_user,
2429 &gen_op_eciwx_kernel,
2430};
2431static GenOpFunc *gen_op_ecowx[] = {
2432 &gen_op_ecowx_user,
2433 &gen_op_ecowx_kernel,
2434};
2435#endif
2436
79aceca5
FB		 2437GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2438{
9a64fbe4
FB		 2439 /* Should check EAR[E] & alignment ! */
2440 if (rA(ctx->opcode) == 0) {
2441 gen_op_load_gpr_T0(rB(ctx->opcode));
2442 } else {
2443 gen_op_load_gpr_T0(rA(ctx->opcode));
2444 gen_op_load_gpr_T1(rB(ctx->opcode));
2445 gen_op_add();
2446 }
2447 op_eciwx();
2448 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2449}
2450
2451/* ecowx */
2452GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2453{
9a64fbe4
FB		 2454 /* Should check EAR[E] & alignment ! */
2455 if (rA(ctx->opcode) == 0) {
2456 gen_op_load_gpr_T0(rB(ctx->opcode));
2457 } else {
2458 gen_op_load_gpr_T0(rA(ctx->opcode));
2459 gen_op_load_gpr_T1(rB(ctx->opcode));
2460 gen_op_add();
2461 }
2462 gen_op_load_gpr_T2(rS(ctx->opcode));
2463 op_ecowx();
79aceca5
FB		 2464}
2465
2466/* End opcode list */
2467GEN_OPCODE_MARK(end);
2468
2469/*****************************************************************************/
9a64fbe4 2470#include <stdlib.h>
79aceca5 2471#include <string.h>
9a64fbe4
FB		 2472
2473int fflush (FILE *stream);
79aceca5
FB		 2474
2475/* Main ppc opcodes table:
2476 * at init, all opcodes are invalids
2477 */
2478static opc_handler_t *ppc_opcodes[0x40];
2479
2480/* Opcode types */
2481enum {
2482 PPC_DIRECT = 0, /* Opcode routine */
2483 PPC_INDIRECT = 1, /* Indirect opcode table */
2484};
2485
2486static inline int is_indirect_opcode (void *handler)
2487{
2488 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2489}
2490
2491static inline opc_handler_t **ind_table(void *handler)
2492{
2493 return (opc_handler_t **)((unsigned long)handler & ~3);
2494}
2495
9a64fbe4 2496/* Instruction table creation */
79aceca5
FB		 2497/* Opcodes tables creation */
2498static void fill_new_table (opc_handler_t **table, int len)
2499{
2500 int i;
2501
2502 for (i = 0; i < len; i++)
2503 table[i] = &invalid_handler;
2504}
2505
2506static int create_new_table (opc_handler_t **table, unsigned char idx)
2507{
2508 opc_handler_t **tmp;
2509
2510 tmp = malloc(0x20 * sizeof(opc_handler_t));
2511 if (tmp == NULL)
2512 return -1;
2513 fill_new_table(tmp, 0x20);
2514 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2515
2516 return 0;
2517}
2518
2519static int insert_in_table (opc_handler_t **table, unsigned char idx,
2520 opc_handler_t *handler)
2521{
2522 if (table[idx] != &invalid_handler)
2523 return -1;
2524 table[idx] = handler;
2525
2526 return 0;
2527}
2528
9a64fbe4
FB		 2529static int register_direct_insn (opc_handler_t **ppc_opcodes,
2530 unsigned char idx, opc_handler_t *handler)
79aceca5
FB		 2531{
2532 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9a64fbe4 2533 printf("*** ERROR: opcode %02x already assigned in main "
79aceca5
FB		 2534 "opcode table\n", idx);
2535 return -1;
2536 }
2537
2538 return 0;
2539}
2540
2541static int register_ind_in_table (opc_handler_t **table,
2542 unsigned char idx1, unsigned char idx2,
2543 opc_handler_t *handler)
2544{
2545 if (table[idx1] == &invalid_handler) {
2546 if (create_new_table(table, idx1) < 0) {
9a64fbe4 2547 printf("*** ERROR: unable to create indirect table "
79aceca5
FB		 2548 "idx=%02x\n", idx1);
2549 return -1;
2550 }
2551 } else {
2552 if (!is_indirect_opcode(table[idx1])) {
9a64fbe4 2553 printf("*** ERROR: idx %02x already assigned to a direct "
79aceca5
FB		 2554 "opcode\n", idx1);
2555 return -1;
2556 }
2557 }
2558 if (handler != NULL &&
2559 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9a64fbe4 2560 printf("*** ERROR: opcode %02x already assigned in "
79aceca5
FB		 2561 "opcode table %02x\n", idx2, idx1);
2562 return -1;
2563 }
2564
2565 return 0;
2566}
2567
9a64fbe4
FB		 2568static int register_ind_insn (opc_handler_t **ppc_opcodes,
2569 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2570 opc_handler_t *handler)
2571{
2572 int ret;
2573
2574 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2575
2576 return ret;
2577}
2578
9a64fbe4
FB		 2579static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2580 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2581 unsigned char idx3, opc_handler_t *handler)
2582{
2583 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9a64fbe4 2584 printf("*** ERROR: unable to join indirect table idx "
79aceca5
FB		 2585 "[%02x-%02x]\n", idx1, idx2);
2586 return -1;
2587 }
2588 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2589 handler) < 0) {
9a64fbe4 2590 printf("*** ERROR: unable to insert opcode "
79aceca5
FB		 2591 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2592 return -1;
2593 }
2594
2595 return 0;
2596}
2597
9a64fbe4 2598static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
79aceca5
FB		 2599{
2600 if (insn->opc2 != 0xFF) {
2601 if (insn->opc3 != 0xFF) {
9a64fbe4
FB		 2602 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2603 insn->opc3, &insn->handler) < 0)
79aceca5
FB		 2604 return -1;
2605 } else {
9a64fbe4
FB		 2606 if (register_ind_insn(ppc_opcodes, insn->opc1,
2607 insn->opc2, &insn->handler) < 0)
79aceca5
FB		 2608 return -1;
2609 }
2610 } else {
9a64fbe4 2611 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
79aceca5
FB		 2612 return -1;
2613 }
2614
2615 return 0;
2616}
2617
2618static int test_opcode_table (opc_handler_t **table, int len)
2619{
2620 int i, count, tmp;
2621
2622 for (i = 0, count = 0; i < len; i++) {
2623 /* Consistency fixup */
2624 if (table[i] == NULL)
2625 table[i] = &invalid_handler;
2626 if (table[i] != &invalid_handler) {
2627 if (is_indirect_opcode(table[i])) {
2628 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2629 if (tmp == 0) {
2630 free(table[i]);
2631 table[i] = &invalid_handler;
2632 } else {
2633 count++;
2634 }
2635 } else {
2636 count++;
2637 }
2638 }
2639 }
2640
2641 return count;
2642}
2643
9a64fbe4 2644static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
79aceca5
FB		 2645{
2646 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9a64fbe4 2647 printf("*** WARNING: no opcode defined !\n");
79aceca5
FB		 2648}
2649
9a64fbe4 2650#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
79aceca5
FB		 2651#define SPR_UR SPR_RIGHTS(0, 0)
2652#define SPR_UW SPR_RIGHTS(1, 0)
2653#define SPR_SR SPR_RIGHTS(0, 1)
2654#define SPR_SW SPR_RIGHTS(1, 1)
2655
2656#define spr_set_rights(spr, rights) \
2657do { \
2658 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2659} while (0)
2660
9a64fbe4 2661static void init_spr_rights (uint32_t pvr)
79aceca5
FB		 2662{
2663 /* XER (SPR 1) */
9a64fbe4 2664 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2665 /* LR (SPR 8) */
9a64fbe4 2666 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2667 /* CTR (SPR 9) */
9a64fbe4 2668 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2669 /* TBL (SPR 268) */
9a64fbe4 2670 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
79aceca5 2671 /* TBU (SPR 269) */
9a64fbe4 2672 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
79aceca5 2673 /* DSISR (SPR 18) */
9a64fbe4 2674 spr_set_rights(DSISR, SPR_SR | SPR_SW);
79aceca5 2675 /* DAR (SPR 19) */
9a64fbe4 2676 spr_set_rights(DAR, SPR_SR | SPR_SW);
79aceca5 2677 /* DEC (SPR 22) */
9a64fbe4 2678 spr_set_rights(DECR, SPR_SR | SPR_SW);
79aceca5 2679 /* SDR1 (SPR 25) */
9a64fbe4
FB		 2680 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2681 /* SRR0 (SPR 26) */
2682 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2683 /* SRR1 (SPR 27) */
2684 spr_set_rights(SRR1, SPR_SR | SPR_SW);
79aceca5 2685 /* SPRG0 (SPR 272) */
9a64fbe4 2686 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
79aceca5 2687 /* SPRG1 (SPR 273) */
9a64fbe4 2688 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
79aceca5 2689 /* SPRG2 (SPR 274) */
9a64fbe4 2690 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
79aceca5 2691 /* SPRG3 (SPR 275) */
9a64fbe4 2692 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
79aceca5 2693 /* ASR (SPR 280) */
9a64fbe4 2694 spr_set_rights(ASR, SPR_SR | SPR_SW);
79aceca5 2695 /* EAR (SPR 282) */
9a64fbe4
FB		 2696 spr_set_rights(EAR, SPR_SR | SPR_SW);
2697 /* TBL (SPR 284) */
2698 spr_set_rights(O_TBL, SPR_SW);
2699 /* TBU (SPR 285) */
2700 spr_set_rights(O_TBU, SPR_SW);
2701 /* PVR (SPR 287) */
2702 spr_set_rights(PVR, SPR_SR);
79aceca5 2703 /* IBAT0U (SPR 528) */
9a64fbe4 2704 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
79aceca5 2705 /* IBAT0L (SPR 529) */
9a64fbe4 2706 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
79aceca5 2707 /* IBAT1U (SPR 530) */
9a64fbe4 2708 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
79aceca5 2709 /* IBAT1L (SPR 531) */
9a64fbe4 2710 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
79aceca5 2711 /* IBAT2U (SPR 532) */
9a64fbe4 2712 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
79aceca5 2713 /* IBAT2L (SPR 533) */
9a64fbe4 2714 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
79aceca5 2715 /* IBAT3U (SPR 534) */
9a64fbe4 2716 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
79aceca5 2717 /* IBAT3L (SPR 535) */
9a64fbe4 2718 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
79aceca5 2719 /* DBAT0U (SPR 536) */
9a64fbe4 2720 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
79aceca5 2721 /* DBAT0L (SPR 537) */
9a64fbe4 2722 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
79aceca5 2723 /* DBAT1U (SPR 538) */
9a64fbe4 2724 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
79aceca5 2725 /* DBAT1L (SPR 539) */
9a64fbe4 2726 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
79aceca5 2727 /* DBAT2U (SPR 540) */
9a64fbe4 2728 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
79aceca5 2729 /* DBAT2L (SPR 541) */
9a64fbe4 2730 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
79aceca5 2731 /* DBAT3U (SPR 542) */
9a64fbe4 2732 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
79aceca5 2733 /* DBAT3L (SPR 543) */
9a64fbe4 2734 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
79aceca5 2735 /* DABR (SPR 1013) */
9a64fbe4 2736 spr_set_rights(DABR, SPR_SR | SPR_SW);
79aceca5 2737 /* FPECR (SPR 1022) */
9a64fbe4 2738 spr_set_rights(FPECR, SPR_SR | SPR_SW);
79aceca5 2739 /* PIR (SPR 1023) */
9a64fbe4
FB		 2740 spr_set_rights(PIR, SPR_SR | SPR_SW);
2741 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2742 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2743 (pvr & 0xFFFF0000) == 0x70000000) {
2744 /* HID0 */
2745 spr_set_rights(SPR_ENCODE(1008), SPR_SR | SPR_SW);
2746 /* HID1 */
2747 spr_set_rights(SPR_ENCODE(1009), SPR_SR | SPR_SW);
2748 /* IABR */
2749 spr_set_rights(SPR_ENCODE(1010), SPR_SR | SPR_SW);
2750 /* ICTC */
2751 spr_set_rights(SPR_ENCODE(1019), SPR_SR | SPR_SW);
2752 /* L2CR */
2753 spr_set_rights(SPR_ENCODE(1017), SPR_SR | SPR_SW);
2754 /* MMCR0 */
2755 spr_set_rights(SPR_ENCODE(952), SPR_SR | SPR_SW);
2756 /* MMCR1 */
2757 spr_set_rights(SPR_ENCODE(956), SPR_SR | SPR_SW);
2758 /* PMC1 */
2759 spr_set_rights(SPR_ENCODE(953), SPR_SR | SPR_SW);
2760 /* PMC2 */
2761 spr_set_rights(SPR_ENCODE(954), SPR_SR | SPR_SW);
2762 /* PMC3 */
2763 spr_set_rights(SPR_ENCODE(957), SPR_SR | SPR_SW);
2764 /* PMC4 */
2765 spr_set_rights(SPR_ENCODE(958), SPR_SR | SPR_SW);
2766 /* SIA */
2767 spr_set_rights(SPR_ENCODE(955), SPR_SR | SPR_SW);
2768 /* THRM1 */
2769 spr_set_rights(SPR_ENCODE(1020), SPR_SR | SPR_SW);
2770 /* THRM2 */
2771 spr_set_rights(SPR_ENCODE(1021), SPR_SR | SPR_SW);
2772 /* THRM3 */
2773 spr_set_rights(SPR_ENCODE(1022), SPR_SR | SPR_SW);
2774 /* UMMCR0 */
2775 spr_set_rights(SPR_ENCODE(936), SPR_UR | SPR_UW);
2776 /* UMMCR1 */
2777 spr_set_rights(SPR_ENCODE(940), SPR_UR | SPR_UW);
2778 /* UPMC1 */
2779 spr_set_rights(SPR_ENCODE(937), SPR_UR | SPR_UW);
2780 /* UPMC2 */
2781 spr_set_rights(SPR_ENCODE(938), SPR_UR | SPR_UW);
2782 /* UPMC3 */
2783 spr_set_rights(SPR_ENCODE(941), SPR_UR | SPR_UW);
2784 /* UPMC4 */
2785 spr_set_rights(SPR_ENCODE(942), SPR_UR | SPR_UW);
2786 /* USIA */
2787 spr_set_rights(SPR_ENCODE(939), SPR_UR | SPR_UW);
2788 }
2789 /* MPC755 has special registers */
2790 if (pvr == 0x00083100) {
2791 /* SPRG4 */
2792 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2793 /* SPRG5 */
2794 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2795 /* SPRG6 */
2796 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2797 /* SPRG7 */
2798 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2799 /* IBAT4U */
2800 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2801 /* IBAT4L */
2802 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2803 /* IBAT5U */
2804 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2805 /* IBAT5L */
2806 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2807 /* IBAT6U */
2808 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2809 /* IBAT6L */
2810 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2811 /* IBAT7U */
2812 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2813 /* IBAT7L */
2814 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2815 /* DBAT4U */
2816 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2817 /* DBAT4L */
2818 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2819 /* DBAT5U */
2820 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2821 /* DBAT5L */
2822 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2823 /* DBAT6U */
2824 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2825 /* DBAT6L */
2826 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2827 /* DBAT7U */
2828 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2829 /* DBAT7L */
2830 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2831 /* DMISS */
2832 spr_set_rights(SPR_ENCODE(976), SPR_SR | SPR_SW);
2833 /* DCMP */
2834 spr_set_rights(SPR_ENCODE(977), SPR_SR | SPR_SW);
2835 /* DHASH1 */
2836 spr_set_rights(SPR_ENCODE(978), SPR_SR | SPR_SW);
2837 /* DHASH2 */
2838 spr_set_rights(SPR_ENCODE(979), SPR_SR | SPR_SW);
2839 /* IMISS */
2840 spr_set_rights(SPR_ENCODE(980), SPR_SR | SPR_SW);
2841 /* ICMP */
2842 spr_set_rights(SPR_ENCODE(981), SPR_SR | SPR_SW);
2843 /* RPA */
2844 spr_set_rights(SPR_ENCODE(982), SPR_SR | SPR_SW);
2845 /* HID2 */
2846 spr_set_rights(SPR_ENCODE(1011), SPR_SR | SPR_SW);
2847 /* L2PM */
2848 spr_set_rights(SPR_ENCODE(1016), SPR_SR | SPR_SW);
2849 }
79aceca5
FB		 2850}
2851
9a64fbe4
FB		 2852/*****************************************************************************/
2853/* PPC "main stream" common instructions (no optional ones) */
79aceca5
FB		 2854
2855typedef struct ppc_proc_t {
2856 int flags;
2857 void *specific;
2858} ppc_proc_t;
2859
2860typedef struct ppc_def_t {
2861 unsigned long pvr;
2862 unsigned long pvr_mask;
2863 ppc_proc_t *proc;
2864} ppc_def_t;
2865
2866static ppc_proc_t ppc_proc_common = {
2867 .flags = PPC_COMMON,
2868 .specific = NULL,
2869};
2870
9a64fbe4
FB		 2871static ppc_proc_t ppc_proc_G3 = {
2872 .flags = PPC_750,
2873 .specific = NULL,
2874};
2875
79aceca5
FB		 2876static ppc_def_t ppc_defs[] =
2877{
9a64fbe4
FB		 2878 /* MPC740/745/750/755 (G3) */
2879 {
2880 .pvr = 0x00080000,
2881 .pvr_mask = 0xFFFF0000,
2882 .proc = &ppc_proc_G3,
2883 },
2884 /* IBM 750FX (G3 embedded) */
2885 {
2886 .pvr = 0x70000000,
2887 .pvr_mask = 0xFFFF0000,
2888 .proc = &ppc_proc_G3,
2889 },
2890 /* Fallback (generic PPC) */
79aceca5
FB		 2891 {
2892 .pvr = 0x00000000,
2893 .pvr_mask = 0x00000000,
2894 .proc = &ppc_proc_common,
2895 },
2896};
2897
9a64fbe4 2898static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
79aceca5
FB		 2899{
2900 opcode_t *opc;
2901 int i, flags;
2902
2903 fill_new_table(ppc_opcodes, 0x40);
2904 for (i = 0; ; i++) {
2905 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2906 (pvr & ppc_defs[i].pvr_mask)) {
2907 flags = ppc_defs[i].proc->flags;
2908 break;
2909 }
2910 }
2911
2912 for (opc = &opc_start + 1; opc != &opc_end; opc++) {
9a64fbe4
FB		 2913 if ((opc->handler.type & flags) != 0)
2914 if (register_insn(ppc_opcodes, opc) < 0) {
2915 printf("*** ERROR initializing PPC instruction "
79aceca5
FB		 2916 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2917 opc->opc3);
2918 return -1;
2919 }
2920 }
9a64fbe4 2921 fix_opcode_tables(ppc_opcodes);
79aceca5
FB		 2922
2923 return 0;
2924}
2925
9a64fbe4 2926
79aceca5 2927/*****************************************************************************/
9a64fbe4
FB		 2928/* Misc PPC helpers */
2929FILE *stdout;
79aceca5
FB		 2930
2931void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags)
2932{
2933 int i;
2934
9a64fbe4
FB		 2935 fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
2936 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
2937 _load_xer(), _load_msr());
79aceca5
FB		 2938 for (i = 0; i < 32; i++) {
2939 if ((i & 7) == 0)
9a64fbe4
FB		 2940 fprintf(f, "GPR%02d:", i);
2941 fprintf(f, " %08x", env->gpr[i]);
79aceca5 2942 if ((i & 7) == 7)
9a64fbe4 2943 fprintf(f, "\n");
79aceca5 2944 }
9a64fbe4 2945 fprintf(f, "CR: 0x");
79aceca5 2946 for (i = 0; i < 8; i++)
9a64fbe4
FB		 2947 fprintf(f, "%01x", env->crf[i]);
2948 fprintf(f, " [");
79aceca5
FB		 2949 for (i = 0; i < 8; i++) {
2950 char a = '-';
79aceca5
FB		 2951 if (env->crf[i] & 0x08)
2952 a = 'L';
2953 else if (env->crf[i] & 0x04)
2954 a = 'G';
2955 else if (env->crf[i] & 0x02)
2956 a = 'E';
9a64fbe4 2957 fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
79aceca5 2958 }
9a64fbe4
FB		 2959 fprintf(f, " ] ");
2960 fprintf(f, "TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
79aceca5
FB		 2961 for (i = 0; i < 16; i++) {
2962 if ((i & 3) == 0)
9a64fbe4
FB		 2963 fprintf(f, "FPR%02d:", i);
2964 fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
79aceca5 2965 if ((i & 3) == 3)
9a64fbe4 2966 fprintf(f, "\n");
79aceca5 2967 }
9a64fbe4
FB		 2968 fprintf(f, "SRR0 0x%08x SRR1 0x%08x\n",
2969 env->spr[SRR0], env->spr[SRR1]);
2970 fprintf(f, "reservation 0x%08x\n", env->reserve);
2971 fflush(f);
79aceca5
FB		 2972}
2973
9a64fbe4
FB		 2974#if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
2975int setup_machine (CPUPPCState *env, uint32_t mid);
2976#endif
2977
79aceca5
FB		 2978CPUPPCState *cpu_ppc_init(void)
2979{
2980 CPUPPCState *env;
2981
2982 cpu_exec_init();
2983
2984 env = malloc(sizeof(CPUPPCState));
2985 if (!env)
2986 return NULL;
2987 memset(env, 0, sizeof(CPUPPCState));
9a64fbe4
FB		 2988#if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
2989 setup_machine(env, 0);
2990#else
2991// env->spr[PVR] = 0; /* Basic PPC */
2992 env->spr[PVR] = 0x00080100; /* G3 CPU */
2993// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
2994// env->spr[PVR] = 0x00070100; /* IBM 750FX */
2995#endif
2996 env->decr = 0xFFFFFFFF;
2997 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
79aceca5 2998 return NULL;
9a64fbe4 2999 init_spr_rights(env->spr[PVR]);
ad081323 3000 tlb_flush(env, 1);
9a64fbe4
FB		 3001#if defined (DO_SINGLE_STEP)
3002 /* Single step trace mode */
3003 msr_se = 1;
3004#endif
3005#if defined(CONFIG_USER_ONLY)
3006 msr_pr = 1;
3007#endif
79aceca5
FB		 3008
3009 return env;
3010}
3011
3012void cpu_ppc_close(CPUPPCState *env)
3013{
3014 /* Should also remove all opcode tables... */
3015 free(env);
3016}
3017
9a64fbe4
FB		 3018/*****************************************************************************/
3019void raise_exception_err (int exception_index, int error_code);
3020int print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr,
3021 int dialect);
3022
79aceca5
FB		 3023int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3024 int search_pc)
3025{
3026 DisasContext ctx;
3027 opc_handler_t **table, *handler;
3028 uint32_t pc_start;
3029 uint16_t *gen_opc_end;
3030 int j, lj = -1;
79aceca5
FB		 3031
3032 pc_start = tb->pc;
3033 gen_opc_ptr = gen_opc_buf;
3034 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3035 gen_opparam_ptr = gen_opparam_buf;
3036 ctx.nip = (uint32_t *)pc_start;
3037 ctx.tb_offset = 0;
9a64fbe4 3038 ctx.decr_offset = 0;
79aceca5 3039 ctx.tb = tb;
9a64fbe4
FB		 3040 ctx.exception = EXCP_NONE;
3041#if defined(CONFIG_USER_ONLY)
3042 ctx.mem_idx = 0;
3043#else
3044 ctx.supervisor = 1 - msr_pr;
3045 ctx.mem_idx = (1 - msr_pr);
3046#endif
3047#if defined (DO_SINGLE_STEP)
3048 /* Single step trace mode */
3049 msr_se = 1;
3050#endif
3051 /* Set env in case of segfault during code fetch */
3052 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
79aceca5
FB		 3053 if (search_pc) {
3054 if (loglevel > 0)
3055 fprintf(logfile, "Search PC...\n");
3056 j = gen_opc_ptr - gen_opc_buf;
3057 if (lj < j) {
3058 lj++;
3059 while (lj < j)
3060 gen_opc_instr_start[lj++] = 0;
3061 gen_opc_pc[lj] = (uint32_t)ctx.nip;
3062 gen_opc_instr_start[lj] = 1;
3063 }
3064 }
9a64fbe4 3065#if defined DEBUG_DISAS
79aceca5
FB		 3066 if (loglevel > 0) {
3067 fprintf(logfile, "----------------\n");
9a64fbe4
FB		 3068 fprintf(logfile, "nip=%p super=%d ir=%d\n",
3069 ctx.nip, 1 - msr_pr, msr_ir);
3070 }
3071#endif
3072 ctx.opcode = ldl_code(ctx.nip);
3073#if defined DEBUG_DISAS
3074 if (loglevel > 0) {
3075 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3076 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3077 opc3(ctx.opcode));
79aceca5
FB		 3078 }
3079#endif
3080 ctx.nip++;
9a64fbe4
FB		 3081 ctx.tb_offset++;
3082 /* Check decrementer exception */
3083 if (++ctx.decr_offset == env->decr + 1)
3084 ctx.exception = EXCP_DECR;
79aceca5
FB		 3085 table = ppc_opcodes;
3086 handler = table[opc1(ctx.opcode)];
3087 if (is_indirect_opcode(handler)) {
3088 table = ind_table(handler);
3089 handler = table[opc2(ctx.opcode)];
3090 if (is_indirect_opcode(handler)) {
3091 table = ind_table(handler);
3092 handler = table[opc3(ctx.opcode)];
3093 }
3094 }
3095 /* Is opcode *REALLY* valid ? */
3096 if ((ctx.opcode & handler->inval) != 0) {
3097 if (loglevel > 0) {
3098 if (handler->handler == &gen_invalid) {
3099 fprintf(logfile, "invalid/unsupported opcode: "
9a64fbe4
FB		 3100 "%02x -%02x - %02x (%08x) %p\n",
3101 opc1(ctx.opcode), opc2(ctx.opcode),
3102 opc3(ctx.opcode), ctx.opcode, ctx.nip - 1);
79aceca5
FB		 3103 } else {
3104 fprintf(logfile, "invalid bits: %08x for opcode: "
9a64fbe4 3105 "%02x -%02x - %02x (0x%08x) (%p)\n",
79aceca5
FB		 3106 ctx.opcode & handler->inval, opc1(ctx.opcode),
3107 opc2(ctx.opcode), opc3(ctx.opcode),
9a64fbe4 3108 ctx.opcode, ctx.nip - 1);
79aceca5 3109 }
9a64fbe4
FB		 3110 } else {
3111 if (handler->handler == &gen_invalid) {
3112 printf("invalid/unsupported opcode: "
3113 "%02x -%02x - %02x (%08x) %p\n",
3114 opc1(ctx.opcode), opc2(ctx.opcode),
3115 opc3(ctx.opcode), ctx.opcode, ctx.nip - 1);
3116 } else {
3117 printf("invalid bits: %08x for opcode: "
3118 "%02x -%02x - %02x (0x%08x) (%p)\n",
3119 ctx.opcode & handler->inval, opc1(ctx.opcode),
3120 opc2(ctx.opcode), opc3(ctx.opcode),
3121 ctx.opcode, ctx.nip - 1);
3122 }
79aceca5 3123 }
9a64fbe4 3124 (*gen_invalid)(&ctx);
79aceca5 3125 } else {
9a64fbe4 3126 (*(handler->handler))(&ctx);
79aceca5 3127 }
9a64fbe4
FB		 3128 /* Check trace mode exceptions */
3129 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3130 /* Check in single step trace mode
3131 * we need to stop except if:
3132 * - rfi, trap or syscall
3133 * - first instruction of an exception handler
3134 */
3135 (msr_se && ((uint32_t)ctx.nip < 0x100 ||
3136 (uint32_t)ctx.nip > 0xF00 ||
3137 ((uint32_t)ctx.nip & 0xFC) != 0x04) &&
3138 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3139 ctx.exception != EXCP_TRAP)) {
3140#if !defined(CONFIG_USER_ONLY)
3141 gen_op_queue_exception(EXCP_TRACE);
79aceca5 3142#endif
9a64fbe4
FB		 3143 if (ctx.exception == EXCP_NONE) {
3144 ctx.exception = EXCP_TRACE;
79aceca5 3145 }
9a64fbe4
FB		 3146 }
3147 /* if too long translation, stop generation too */
3148 if (gen_opc_ptr >= gen_opc_end ||
3149 ((uint32_t)ctx.nip - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
3150 if (ctx.exception == EXCP_NONE) {
79aceca5 3151 gen_op_b((uint32_t)ctx.nip);
9a64fbe4 3152 ctx.exception = EXCP_BRANCH;
79aceca5 3153 }
79aceca5 3154 }
9a64fbe4
FB		 3155 }
3156 /* In case of branch, this has already been done *BEFORE* the branch */
3157 if (ctx.exception != EXCP_BRANCH && ctx.exception != EXCP_RFI) {
3158 gen_op_update_tb(ctx.tb_offset);
3159 gen_op_update_decr(ctx.decr_offset);
3160 gen_op_process_exceptions((uint32_t)ctx.nip);
3161 }
3162#if 1
79aceca5
FB		 3163 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3164 * do bad business and then qemu crashes !
3165 */
3166 gen_op_set_T0(0);
9a64fbe4 3167#endif
79aceca5
FB		 3168 /* Generate the return instruction */
3169 gen_op_exit_tb();
3170 *gen_opc_ptr = INDEX_op_end;
9a64fbe4
FB		 3171 if (search_pc) {
3172 j = gen_opc_ptr - gen_opc_buf;
3173 lj++;
3174 while (lj <= j)
3175 gen_opc_instr_start[lj++] = 0;
79aceca5 3176 tb->size = 0;
985a19d6 3177#if 0
9a64fbe4
FB		 3178 if (loglevel > 0) {
3179 page_dump(logfile);
3180 }
985a19d6 3181#endif
9a64fbe4
FB		 3182 } else {
3183 tb->size = (uint32_t)ctx.nip - pc_start;
3184 }
79aceca5
FB		 3185#ifdef DEBUG_DISAS
3186 if (loglevel > 0) {
9a64fbe4
FB		 3187 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
3188 cpu_ppc_dump_state(env, logfile, 0);
79aceca5
FB		 3189 fprintf(logfile, "IN: %s\n", lookup_symbol((void *)pc_start));
3190 disas(logfile, (void *)pc_start, (uint32_t)ctx.nip - pc_start, 0, 0);
3191 fprintf(logfile, "\n");
3192
3193 fprintf(logfile, "OP:\n");
3194 dump_ops(gen_opc_buf, gen_opparam_buf);
3195 fprintf(logfile, "\n");
3196 }
3197#endif
3198
3199 return 0;
3200}
3201
9a64fbe4 3202int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3203{
3204 return gen_intermediate_code_internal(env, tb, 0);
3205}
3206
9a64fbe4 3207int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3208{
3209 return gen_intermediate_code_internal(env, tb, 1);
3210}
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