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suppressed tgetx and tputx (initial patch by Thayne Harbaugh)
[mirror_qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5
FB		 28#include "disas.h"
29
a750fc0b 30/* Include definitions for instructions classes and implementations flags */
79aceca5 31//#define DO_SINGLE_STEP
9fddaa0c 32//#define PPC_DEBUG_DISAS
a496775f 33//#define DEBUG_MEMORY_ACCESSES
76a66253 34//#define DO_PPC_STATISTICS
7c58044c 35//#define OPTIMIZE_FPRF_UPDATE
79aceca5 36
a750fc0b
JM		 37/*****************************************************************************/
38/* Code translation helpers */
d9bce9d9 39#if defined(USE_DIRECT_JUMP)
c53be334
FB		 40#define TBPARAM(x)
41#else
42#define TBPARAM(x) (long)(x)
43#endif
44
79aceca5
FB		 45enum {
46#define DEF(s, n, copy_size) INDEX_op_ ## s,
47#include "opc.h"
48#undef DEF
49 NB_OPS,
50};
51
52static uint16_t *gen_opc_ptr;
53static uint32_t *gen_opparam_ptr;
7c58044c
JM		 54#if defined(OPTIMIZE_FPRF_UPDATE)
55static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
56static uint16_t **gen_fprf_ptr;
57#endif
79aceca5
FB		 58
59#include "gen-op.h"
28b6751f 60
b068d6a7 61static always_inline void gen_set_T0 (target_ulong val)
d9bce9d9
JM		 62{
63#if defined(TARGET_PPC64)
64 if (val >> 32)
65 gen_op_set_T0_64(val >> 32, val);
66 else
67#endif
68 gen_op_set_T0(val);
69}
70
b068d6a7 71static always_inline void gen_set_T1 (target_ulong val)
d9bce9d9
JM		 72{
73#if defined(TARGET_PPC64)
74 if (val >> 32)
75 gen_op_set_T1_64(val >> 32, val);
76 else
77#endif
78 gen_op_set_T1(val);
79}
80
81#define GEN8(func, NAME) \
9a64fbe4
FB		 82static GenOpFunc *NAME ## _table [8] = { \
83NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
84NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
85}; \
b068d6a7 86static always_inline void func (int n) \
9a64fbe4
FB		 87{ \
88 NAME ## _table[n](); \
89}
90
91#define GEN16(func, NAME) \
92static GenOpFunc *NAME ## _table [16] = { \
93NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
94NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
95NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
96NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
97}; \
b068d6a7 98static always_inline void func (int n) \
9a64fbe4
FB		 99{ \
100 NAME ## _table[n](); \
28b6751f
FB		 101}
102
d9bce9d9 103#define GEN32(func, NAME) \
9a64fbe4
FB		 104static GenOpFunc *NAME ## _table [32] = { \
105NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
106NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
107NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
108NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
109NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
110NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
111NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
112NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
113}; \
b068d6a7 114static always_inline void func (int n) \
9a64fbe4
FB		 115{ \
116 NAME ## _table[n](); \
117}
118
119/* Condition register moves */
120GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
121GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
122GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
fc0d441e 123#if 0 // Unused
9a64fbe4 124GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
fc0d441e 125#endif
28b6751f 126
9a64fbe4
FB		 127/* General purpose registers moves */
128GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
129GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
130GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
131
132GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
133GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
76a66253 134#if 0 // unused
9a64fbe4 135GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
76a66253 136#endif
28b6751f 137
fb0eaffc
FB		 138/* floating point registers moves */
139GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
140GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
141GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
142GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
143GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
76a66253 144#if 0 // unused
fb0eaffc 145GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
76a66253 146#endif
79aceca5
FB		 147
148/* internal defines */
149typedef struct DisasContext {
150 struct TranslationBlock *tb;
0fa85d43 151 target_ulong nip;
79aceca5 152 uint32_t opcode;
9a64fbe4 153 uint32_t exception;
3cc62370
FB		 154 /* Routine used to access memory */
155 int mem_idx;
156 /* Translation flags */
9a64fbe4 157#if !defined(CONFIG_USER_ONLY)
79aceca5 158 int supervisor;
d9bce9d9
JM		 159#endif
160#if defined(TARGET_PPC64)
161 int sf_mode;
9a64fbe4 162#endif
3cc62370 163 int fpu_enabled;
a9d9eb8f 164 int altivec_enabled;
0487d6a8 165 int spe_enabled;
3fc6c082 166 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 167 int singlestep_enabled;
d63001d1 168 int dcache_line_size;
79aceca5
FB		 169} DisasContext;
170
3fc6c082 171struct opc_handler_t {
79aceca5
FB		 172 /* invalid bits */
173 uint32_t inval;
9a64fbe4 174 /* instruction type */
0487d6a8 175 uint64_t type;
79aceca5
FB		 176 /* handler */
177 void (*handler)(DisasContext *ctx);
a750fc0b 178#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
76a66253 179 const unsigned char *oname;
a750fc0b
JM		 180#endif
181#if defined(DO_PPC_STATISTICS)
76a66253
JM		 182 uint64_t count;
183#endif
3fc6c082 184};
79aceca5 185
b068d6a7 186static always_inline void gen_set_Rc0 (DisasContext *ctx)
76a66253 187{
d9bce9d9
JM		 188#if defined(TARGET_PPC64)
189 if (ctx->sf_mode)
190 gen_op_cmpi_64(0);
191 else
192#endif
193 gen_op_cmpi(0);
76a66253
JM		 194 gen_op_set_Rc0();
195}
196
7c58044c
JM		 197static always_inline void gen_reset_fpstatus (void)
198{
199#ifdef CONFIG_SOFTFLOAT
200 gen_op_reset_fpstatus();
201#endif
202}
203
204static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
205{
206 if (set_fprf != 0) {
207 /* This case might be optimized later */
208#if defined(OPTIMIZE_FPRF_UPDATE)
209 *gen_fprf_ptr++ = gen_opc_ptr;
210#endif
211 gen_op_compute_fprf(1);
212 if (unlikely(set_rc))
213 gen_op_store_T0_crf(1);
214 gen_op_float_check_status();
215 } else if (unlikely(set_rc)) {
216 /* We always need to compute fpcc */
217 gen_op_compute_fprf(0);
218 gen_op_store_T0_crf(1);
219 if (set_fprf)
220 gen_op_float_check_status();
221 }
222}
223
224static always_inline void gen_optimize_fprf (void)
225{
226#if defined(OPTIMIZE_FPRF_UPDATE)
227 uint16_t **ptr;
228
229 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
230 *ptr = INDEX_op_nop1;
231 gen_fprf_ptr = gen_fprf_buf;
232#endif
233}
234
b068d6a7 235static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 236{
237#if defined(TARGET_PPC64)
238 if (ctx->sf_mode)
239 gen_op_update_nip_64(nip >> 32, nip);
240 else
241#endif
242 gen_op_update_nip(nip);
243}
244
e1833e1f 245#define GEN_EXCP(ctx, excp, error) \
79aceca5 246do { \
e1833e1f 247 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 248 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 249 } \
250 gen_op_raise_exception_err((excp), (error)); \
251 ctx->exception = (excp); \
79aceca5
FB		 252} while (0)
253
e1833e1f
JM		 254#define GEN_EXCP_INVAL(ctx) \
255GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
256 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 257
e1833e1f
JM		 258#define GEN_EXCP_PRIVOPC(ctx) \
259GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
260 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 261
e1833e1f
JM		 262#define GEN_EXCP_PRIVREG(ctx) \
263GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
264 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
265
266#define GEN_EXCP_NO_FP(ctx) \
267GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
268
269#define GEN_EXCP_NO_AP(ctx) \
270GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 271
a9d9eb8f
JM		 272#define GEN_EXCP_NO_VR(ctx) \
273GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
274
f24e5695 275/* Stop translation */
b068d6a7 276static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 277{
d9bce9d9 278 gen_update_nip(ctx, ctx->nip);
e1833e1f 279 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 280}
281
f24e5695 282/* No need to update nip here, as execution flow will change */
b068d6a7 283static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 284{
e1833e1f 285 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 286}
287
79aceca5
FB		 288#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
289static void gen_##name (DisasContext *ctx); \
290GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
291static void gen_##name (DisasContext *ctx)
292
c7697e1f
JM		 293#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
294static void gen_##name (DisasContext *ctx); \
295GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
296static void gen_##name (DisasContext *ctx)
297
79aceca5
FB		 298typedef struct opcode_t {
299 unsigned char opc1, opc2, opc3;
18fba28c
FB		 300#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
301 unsigned char pad[5];
302#else
303 unsigned char pad[1];
304#endif
79aceca5 305 opc_handler_t handler;
3fc6c082 306 const unsigned char *oname;
79aceca5
FB		 307} opcode_t;
308
a750fc0b 309/*****************************************************************************/
79aceca5
FB		 310/*** Instruction decoding ***/
311#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 312static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 313{ \
314 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
315}
316
317#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 318static always_inline int32_t name (uint32_t opcode) \
79aceca5 319{ \
18fba28c 320 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 321}
322
323/* Opcode part 1 */
324EXTRACT_HELPER(opc1, 26, 6);
325/* Opcode part 2 */
326EXTRACT_HELPER(opc2, 1, 5);
327/* Opcode part 3 */
328EXTRACT_HELPER(opc3, 6, 5);
329/* Update Cr0 flags */
330EXTRACT_HELPER(Rc, 0, 1);
331/* Destination */
332EXTRACT_HELPER(rD, 21, 5);
333/* Source */
334EXTRACT_HELPER(rS, 21, 5);
335/* First operand */
336EXTRACT_HELPER(rA, 16, 5);
337/* Second operand */
338EXTRACT_HELPER(rB, 11, 5);
339/* Third operand */
340EXTRACT_HELPER(rC, 6, 5);
341/*** Get CRn ***/
342EXTRACT_HELPER(crfD, 23, 3);
343EXTRACT_HELPER(crfS, 18, 3);
344EXTRACT_HELPER(crbD, 21, 5);
345EXTRACT_HELPER(crbA, 16, 5);
346EXTRACT_HELPER(crbB, 11, 5);
347/* SPR / TBL */
3fc6c082 348EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 349static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 350{
351 uint32_t sprn = _SPR(opcode);
352
353 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
354}
79aceca5
FB		 355/*** Get constants ***/
356EXTRACT_HELPER(IMM, 12, 8);
357/* 16 bits signed immediate value */
358EXTRACT_SHELPER(SIMM, 0, 16);
359/* 16 bits unsigned immediate value */
360EXTRACT_HELPER(UIMM, 0, 16);
361/* Bit count */
362EXTRACT_HELPER(NB, 11, 5);
363/* Shift count */
364EXTRACT_HELPER(SH, 11, 5);
365/* Mask start */
366EXTRACT_HELPER(MB, 6, 5);
367/* Mask end */
368EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 369/* Trap operand */
370EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 371
372EXTRACT_HELPER(CRM, 12, 8);
373EXTRACT_HELPER(FM, 17, 8);
374EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 375EXTRACT_HELPER(FPIMM, 20, 4);
376
79aceca5
FB		 377/*** Jump target decoding ***/
378/* Displacement */
379EXTRACT_SHELPER(d, 0, 16);
380/* Immediate address */
b068d6a7 381static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 382{
383 return (opcode >> 0) & 0x03FFFFFC;
384}
385
b068d6a7 386static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 387{
388 return (opcode >> 0) & 0xFFFC;
389}
390
391EXTRACT_HELPER(BO, 21, 5);
392EXTRACT_HELPER(BI, 16, 5);
393/* Absolute/relative address */
394EXTRACT_HELPER(AA, 1, 1);
395/* Link */
396EXTRACT_HELPER(LK, 0, 1);
397
398/* Create a mask between <start> and <end> bits */
b068d6a7 399static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 400{
76a66253 401 target_ulong ret;
79aceca5 402
76a66253
JM		 403#if defined(TARGET_PPC64)
404 if (likely(start == 0)) {
6f2d8978 405 ret = UINT64_MAX << (63 - end);
76a66253 406 } else if (likely(end == 63)) {
6f2d8978 407 ret = UINT64_MAX >> start;
76a66253
JM		 408 }
409#else
410 if (likely(start == 0)) {
6f2d8978 411 ret = UINT32_MAX << (31 - end);
76a66253 412 } else if (likely(end == 31)) {
6f2d8978 413 ret = UINT32_MAX >> start;
76a66253
JM		 414 }
415#endif
416 else {
417 ret = (((target_ulong)(-1ULL)) >> (start)) ^
418 (((target_ulong)(-1ULL) >> (end)) >> 1);
419 if (unlikely(start > end))
420 return ~ret;
421 }
79aceca5
FB		 422
423 return ret;
424}
425
a750fc0b
JM		 426/*****************************************************************************/
427/* PowerPC Instructions types definitions */
428enum {
1b413d55 429 PPC_NONE = 0x0000000000000000ULL,
12de9a39 430 /* PowerPC base instructions set */
1b413d55
JM		 431 PPC_INSNS_BASE = 0x0000000000000001ULL,
432 /* integer operations instructions */
a750fc0b 433#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 434 /* flow control instructions */
a750fc0b 435#define PPC_FLOW PPC_INSNS_BASE
1b413d55 436 /* virtual memory instructions */
a750fc0b 437#define PPC_MEM PPC_INSNS_BASE
1b413d55 438 /* ld/st with reservation instructions */
a750fc0b 439#define PPC_RES PPC_INSNS_BASE
1b413d55 440 /* spr/msr access instructions */
a750fc0b 441#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 442 /* Deprecated instruction sets */
443 /* Original POWER instruction set */
444 PPC_POWER = 0x0000000000000001ULL,
445 /* POWER2 instruction set extension */
446 PPC_POWER2 = 0x0000000000000002ULL,
447 /* Power RTC support */
448 PPC_POWER_RTC = 0x0000000000000004ULL,
449 /* Power-to-PowerPC bridge (601) */
450 PPC_POWER_BR = 0x0000000000000008ULL,
451 /* 64 bits PowerPC instruction set */
452 PPC_64B = 0x0000000000000010ULL,
453 /* New 64 bits extensions (PowerPC 2.0x) */
454 PPC_64BX = 0x0000000000000020ULL,
455 /* 64 bits hypervisor extensions */
456 PPC_64H = 0x0000000000000040ULL,
457 /* New wait instruction (PowerPC 2.0x) */
458 PPC_WAIT = 0x0000000000000080ULL,
459 /* Time base mftb instruction */
460 PPC_MFTB = 0x0000000000000100ULL,
461
462 /* Fixed-point unit extensions */
463 /* PowerPC 602 specific */
464 PPC_602_SPEC = 0x0000000000000200ULL,
465 /* PowerPC 2.03 specification extensions */
466 PPC_203 = 0x0000000000000400ULL,
467
468 /* Floating-point unit extensions */
469 /* Optional floating point instructions */
470 PPC_FLOAT = 0x0000000000010000ULL,
471 /* New floating-point extensions (PowerPC 2.0x) */
472 PPC_FLOAT_EXT = 0x0000000000020000ULL,
473 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
474 PPC_FLOAT_FRES = 0x0000000000080000ULL,
475 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
476 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
477 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
478 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
479
480 /* Vector/SIMD extensions */
481 /* Altivec support */
482 PPC_ALTIVEC = 0x0000000001000000ULL,
483 /* e500 vector instructions */
484 PPC_E500_VECTOR = 0x0000000002000000ULL,
485 /* PowerPC 2.03 SPE extension */
486 PPC_SPE = 0x0000000004000000ULL,
487 /* PowerPC 2.03 SPE floating-point extension */
488 PPC_SPEFPU = 0x0000000008000000ULL,
489
12de9a39 490 /* Optional memory control instructions */
1b413d55
JM		 491 PPC_MEM_TLBIA = 0x0000000010000000ULL,
492 PPC_MEM_TLBIE = 0x0000000020000000ULL,
493 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
494 /* sync instruction */
495 PPC_MEM_SYNC = 0x0000000080000000ULL,
496 /* eieio instruction */
497 PPC_MEM_EIEIO = 0x0000000100000000ULL,
498
499 /* Cache control instructions */
500 PPC_CACHE = 0x0000001000000000ULL,
501 /* icbi instruction */
502 PPC_CACHE_ICBI = 0x0000002000000000ULL,
503 /* dcbz instruction with fixed cache line size */
504 PPC_CACHE_DCBZ = 0x0000004000000000ULL,
505 /* dcbz instruction with tunable cache line size */
506 PPC_CACHE_DCBZT = 0x0000008000000000ULL,
507 /* dcba instruction */
508 PPC_CACHE_DCBA = 0x0000010000000000ULL,
509
510 /* MMU related extensions */
511 /* external control instructions */
512 PPC_EXTERN = 0x0000100000000000ULL,
513 /* segment register access instructions */
514 PPC_SEGMENT = 0x0000200000000000ULL,
515 /* PowerPC 6xx TLB management instructions */
516 PPC_6xx_TLB = 0x0000400000000000ULL,
517 /* PowerPC 74xx TLB management instructions */
518 PPC_74xx_TLB = 0x0000800000000000ULL,
519 /* PowerPC 40x TLB management instructions */
520 PPC_40x_TLB = 0x0001000000000000ULL,
521 /* segment register access instructions for PowerPC 64 "bridge" */
522 PPC_SEGMENT_64B = 0x0002000000000000ULL,
523 /* SLB management */
524 PPC_SLBI = 0x0004000000000000ULL,
525
12de9a39 526 /* Embedded PowerPC dedicated instructions */
1b413d55 527 PPC_EMB_COMMON = 0x0010000000000000ULL,
12de9a39 528 /* PowerPC 40x exception model */
1b413d55 529 PPC_40x_EXCP = 0x0020000000000000ULL,
12de9a39 530 /* PowerPC 405 Mac instructions */
1b413d55 531 PPC_405_MAC = 0x0040000000000000ULL,
12de9a39 532 /* PowerPC 440 specific instructions */
1b413d55 533 PPC_440_SPEC = 0x0080000000000000ULL,
12de9a39 534 /* BookE (embedded) PowerPC specification */
1b413d55
JM		 535 PPC_BOOKE = 0x0100000000000000ULL,
536 /* More BookE (embedded) instructions... */
537 PPC_BOOKE_EXT = 0x0200000000000000ULL,
12de9a39 538 /* PowerPC 4xx dedicated instructions */
1b413d55 539 PPC_4xx_COMMON = 0x0400000000000000ULL,
12de9a39 540 /* PowerPC 40x ibct instructions */
1b413d55 541 PPC_40x_ICBT = 0x0800000000000000ULL,
12de9a39 542 /* rfmci is not implemented in all BookE PowerPC */
1b413d55 543 PPC_RFMCI = 0x1000000000000000ULL,
12de9a39 544 /* user-mode DCR access, implemented in PowerPC 460 */
1b413d55 545 PPC_DCRUX = 0x2000000000000000ULL,
a750fc0b
JM		 546};
547
548/*****************************************************************************/
549/* PowerPC instructions table */
3fc6c082
FB		 550#if HOST_LONG_BITS == 64
551#define OPC_ALIGN 8
552#else
553#define OPC_ALIGN 4
554#endif
1b039c09 555#if defined(__APPLE__)
d9bce9d9 556#define OPCODES_SECTION \
3fc6c082 557 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 558#else
d9bce9d9 559#define OPCODES_SECTION \
3fc6c082 560 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 561#endif
562
76a66253 563#if defined(DO_PPC_STATISTICS)
79aceca5 564#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 565OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 566 .opc1 = op1, \
567 .opc2 = op2, \
568 .opc3 = op3, \
18fba28c 569 .pad = { 0, }, \
79aceca5
FB		 570 .handler = { \
571 .inval = invl, \
9a64fbe4 572 .type = _typ, \
79aceca5 573 .handler = &gen_##name, \
76a66253 574 .oname = stringify(name), \
79aceca5 575 }, \
3fc6c082 576 .oname = stringify(name), \
79aceca5 577}
c7697e1f
JM		 578#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
579OPCODES_SECTION opcode_t opc_##name = { \
580 .opc1 = op1, \
581 .opc2 = op2, \
582 .opc3 = op3, \
583 .pad = { 0, }, \
584 .handler = { \
585 .inval = invl, \
586 .type = _typ, \
587 .handler = &gen_##name, \
588 .oname = onam, \
589 }, \
590 .oname = onam, \
591}
76a66253
JM		 592#else
593#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
594OPCODES_SECTION opcode_t opc_##name = { \
595 .opc1 = op1, \
596 .opc2 = op2, \
597 .opc3 = op3, \
598 .pad = { 0, }, \
599 .handler = { \
600 .inval = invl, \
601 .type = _typ, \
602 .handler = &gen_##name, \
603 }, \
604 .oname = stringify(name), \
605}
c7697e1f
JM		 606#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
607OPCODES_SECTION opcode_t opc_##name = { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .pad = { 0, }, \
612 .handler = { \
613 .inval = invl, \
614 .type = _typ, \
615 .handler = &gen_##name, \
616 }, \
617 .oname = onam, \
618}
76a66253 619#endif
79aceca5
FB		 620
621#define GEN_OPCODE_MARK(name) \
18fba28c 622OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 623 .opc1 = 0xFF, \
624 .opc2 = 0xFF, \
625 .opc3 = 0xFF, \
18fba28c 626 .pad = { 0, }, \
79aceca5
FB		 627 .handler = { \
628 .inval = 0x00000000, \
9a64fbe4 629 .type = 0x00, \
79aceca5
FB		 630 .handler = NULL, \
631 }, \
3fc6c082 632 .oname = stringify(name), \
79aceca5
FB		 633}
634
635/* Start opcode list */
636GEN_OPCODE_MARK(start);
637
638/* Invalid instruction */
9a64fbe4
FB		 639GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
640{
e1833e1f 641 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 642}
643
79aceca5
FB		 644static opc_handler_t invalid_handler = {
645 .inval = 0xFFFFFFFF,
9a64fbe4 646 .type = PPC_NONE,
79aceca5
FB		 647 .handler = gen_invalid,
648};
649
650/*** Integer arithmetic ***/
d9bce9d9
JM		 651#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
652GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5
FB		 653{ \
654 gen_op_load_gpr_T0(rA(ctx->opcode)); \
655 gen_op_load_gpr_T1(rB(ctx->opcode)); \
656 gen_op_##name(); \
79aceca5 657 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 658 if (unlikely(Rc(ctx->opcode) != 0)) \
659 gen_set_Rc0(ctx); \
79aceca5
FB		 660}
661
d9bce9d9
JM		 662#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
663GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5
FB		 664{ \
665 gen_op_load_gpr_T0(rA(ctx->opcode)); \
666 gen_op_load_gpr_T1(rB(ctx->opcode)); \
667 gen_op_##name(); \
79aceca5 668 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 669 if (unlikely(Rc(ctx->opcode) != 0)) \
670 gen_set_Rc0(ctx); \
79aceca5
FB		 671}
672
d9bce9d9
JM		 673#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
674GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5
FB		 675{ \
676 gen_op_load_gpr_T0(rA(ctx->opcode)); \
677 gen_op_##name(); \
79aceca5 678 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 679 if (unlikely(Rc(ctx->opcode) != 0)) \
680 gen_set_Rc0(ctx); \
79aceca5 681}
d9bce9d9
JM		 682#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
683GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5
FB		 684{ \
685 gen_op_load_gpr_T0(rA(ctx->opcode)); \
686 gen_op_##name(); \
79aceca5 687 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 688 if (unlikely(Rc(ctx->opcode) != 0)) \
689 gen_set_Rc0(ctx); \
79aceca5
FB		 690}
691
692/* Two operands arithmetic functions */
d9bce9d9
JM		 693#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
694__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
695__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
696
697/* Two operands arithmetic functions with no overflow allowed */
698#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
699__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
700
701/* One operand arithmetic functions */
702#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
703__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
704__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
705
706#if defined(TARGET_PPC64)
707#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
708GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
709{ \
710 gen_op_load_gpr_T0(rA(ctx->opcode)); \
711 gen_op_load_gpr_T1(rB(ctx->opcode)); \
712 if (ctx->sf_mode) \
713 gen_op_##name##_64(); \
714 else \
715 gen_op_##name(); \
716 gen_op_store_T0_gpr(rD(ctx->opcode)); \
717 if (unlikely(Rc(ctx->opcode) != 0)) \
718 gen_set_Rc0(ctx); \
719}
720
721#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
722GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
723{ \
724 gen_op_load_gpr_T0(rA(ctx->opcode)); \
725 gen_op_load_gpr_T1(rB(ctx->opcode)); \
726 if (ctx->sf_mode) \
727 gen_op_##name##_64(); \
728 else \
729 gen_op_##name(); \
730 gen_op_store_T0_gpr(rD(ctx->opcode)); \
731 if (unlikely(Rc(ctx->opcode) != 0)) \
732 gen_set_Rc0(ctx); \
733}
734
735#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
736GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
737{ \
738 gen_op_load_gpr_T0(rA(ctx->opcode)); \
739 if (ctx->sf_mode) \
740 gen_op_##name##_64(); \
741 else \
742 gen_op_##name(); \
743 gen_op_store_T0_gpr(rD(ctx->opcode)); \
744 if (unlikely(Rc(ctx->opcode) != 0)) \
745 gen_set_Rc0(ctx); \
746}
747#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
748GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
749{ \
750 gen_op_load_gpr_T0(rA(ctx->opcode)); \
751 if (ctx->sf_mode) \
752 gen_op_##name##_64(); \
753 else \
754 gen_op_##name(); \
755 gen_op_store_T0_gpr(rD(ctx->opcode)); \
756 if (unlikely(Rc(ctx->opcode) != 0)) \
757 gen_set_Rc0(ctx); \
758}
759
760/* Two operands arithmetic functions */
761#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
762__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
763__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 764
765/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 766#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
767__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 768
769/* One operand arithmetic functions */
d9bce9d9
JM		 770#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
771__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
772__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
773#else
774#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
775#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
776#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
777#endif
79aceca5
FB		 778
779/* add add. addo addo. */
b068d6a7 780static always_inline void gen_op_addo (void)
d9bce9d9
JM		 781{
782 gen_op_move_T2_T0();
783 gen_op_add();
784 gen_op_check_addo();
785}
786#if defined(TARGET_PPC64)
787#define gen_op_add_64 gen_op_add
b068d6a7 788static always_inline void gen_op_addo_64 (void)
d9bce9d9
JM		 789{
790 gen_op_move_T2_T0();
791 gen_op_add();
792 gen_op_check_addo_64();
793}
794#endif
795GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 796/* addc addc. addco addco. */
b068d6a7 797static always_inline void gen_op_addc (void)
d9bce9d9
JM		 798{
799 gen_op_move_T2_T0();
800 gen_op_add();
801 gen_op_check_addc();
802}
b068d6a7 803static always_inline void gen_op_addco (void)
d9bce9d9
JM		 804{
805 gen_op_move_T2_T0();
806 gen_op_add();
807 gen_op_check_addc();
808 gen_op_check_addo();
809}
810#if defined(TARGET_PPC64)
b068d6a7 811static always_inline void gen_op_addc_64 (void)
d9bce9d9
JM		 812{
813 gen_op_move_T2_T0();
814 gen_op_add();
815 gen_op_check_addc_64();
816}
b068d6a7 817static always_inline void gen_op_addco_64 (void)
d9bce9d9
JM		 818{
819 gen_op_move_T2_T0();
820 gen_op_add();
821 gen_op_check_addc_64();
822 gen_op_check_addo_64();
823}
824#endif
825GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 826/* adde adde. addeo addeo. */
b068d6a7 827static always_inline void gen_op_addeo (void)
d9bce9d9
JM		 828{
829 gen_op_move_T2_T0();
830 gen_op_adde();
831 gen_op_check_addo();
832}
833#if defined(TARGET_PPC64)
b068d6a7 834static always_inline void gen_op_addeo_64 (void)
d9bce9d9
JM		 835{
836 gen_op_move_T2_T0();
837 gen_op_adde_64();
838 gen_op_check_addo_64();
839}
840#endif
841GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 842/* addme addme. addmeo addmeo. */
b068d6a7 843static always_inline void gen_op_addme (void)
d9bce9d9
JM		 844{
845 gen_op_move_T1_T0();
846 gen_op_add_me();
847}
848#if defined(TARGET_PPC64)
b068d6a7 849static always_inline void gen_op_addme_64 (void)
d9bce9d9
JM		 850{
851 gen_op_move_T1_T0();
852 gen_op_add_me_64();
853}
854#endif
855GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 856/* addze addze. addzeo addzeo. */
b068d6a7 857static always_inline void gen_op_addze (void)
d9bce9d9
JM		 858{
859 gen_op_move_T2_T0();
860 gen_op_add_ze();
861 gen_op_check_addc();
862}
b068d6a7 863static always_inline void gen_op_addzeo (void)
d9bce9d9
JM		 864{
865 gen_op_move_T2_T0();
866 gen_op_add_ze();
867 gen_op_check_addc();
868 gen_op_check_addo();
869}
870#if defined(TARGET_PPC64)
b068d6a7 871static always_inline void gen_op_addze_64 (void)
d9bce9d9
JM		 872{
873 gen_op_move_T2_T0();
874 gen_op_add_ze();
875 gen_op_check_addc_64();
876}
b068d6a7 877static always_inline void gen_op_addzeo_64 (void)
d9bce9d9
JM		 878{
879 gen_op_move_T2_T0();
880 gen_op_add_ze();
881 gen_op_check_addc_64();
882 gen_op_check_addo_64();
883}
884#endif
885GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 886/* divw divw. divwo divwo. */
d9bce9d9 887GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 888/* divwu divwu. divwuo divwuo. */
d9bce9d9 889GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 890/* mulhw mulhw. */
d9bce9d9 891GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 892/* mulhwu mulhwu. */
d9bce9d9 893GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 894/* mullw mullw. mullwo mullwo. */
d9bce9d9 895GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 896/* neg neg. nego nego. */
d9bce9d9 897GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 898/* subf subf. subfo subfo. */
b068d6a7 899static always_inline void gen_op_subfo (void)
d9bce9d9 900{
c3e10c7b 901 gen_op_moven_T2_T0();
d9bce9d9 902 gen_op_subf();
c3e10c7b 903 gen_op_check_addo();
d9bce9d9
JM		 904}
905#if defined(TARGET_PPC64)
906#define gen_op_subf_64 gen_op_subf
b068d6a7 907static always_inline void gen_op_subfo_64 (void)
d9bce9d9 908{
c3e10c7b 909 gen_op_moven_T2_T0();
d9bce9d9 910 gen_op_subf();
c3e10c7b 911 gen_op_check_addo_64();
d9bce9d9
JM		 912}
913#endif
914GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 915/* subfc subfc. subfco subfco. */
b068d6a7 916static always_inline void gen_op_subfc (void)
d9bce9d9
JM		 917{
918 gen_op_subf();
919 gen_op_check_subfc();
920}
b068d6a7 921static always_inline void gen_op_subfco (void)
d9bce9d9 922{
c3e10c7b 923 gen_op_moven_T2_T0();
d9bce9d9
JM		 924 gen_op_subf();
925 gen_op_check_subfc();
c3e10c7b 926 gen_op_check_addo();
d9bce9d9
JM		 927}
928#if defined(TARGET_PPC64)
b068d6a7 929static always_inline void gen_op_subfc_64 (void)
d9bce9d9
JM		 930{
931 gen_op_subf();
932 gen_op_check_subfc_64();
933}
b068d6a7 934static always_inline void gen_op_subfco_64 (void)
d9bce9d9 935{
c3e10c7b 936 gen_op_moven_T2_T0();
d9bce9d9
JM		 937 gen_op_subf();
938 gen_op_check_subfc_64();
c3e10c7b 939 gen_op_check_addo_64();
d9bce9d9
JM		 940}
941#endif
942GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 943/* subfe subfe. subfeo subfeo. */
b068d6a7 944static always_inline void gen_op_subfeo (void)
d9bce9d9 945{
c3e10c7b 946 gen_op_moven_T2_T0();
d9bce9d9 947 gen_op_subfe();
c3e10c7b 948 gen_op_check_addo();
d9bce9d9
JM		 949}
950#if defined(TARGET_PPC64)
951#define gen_op_subfe_64 gen_op_subfe
b068d6a7 952static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 953{
c3e10c7b 954 gen_op_moven_T2_T0();
d9bce9d9 955 gen_op_subfe_64();
c3e10c7b 956 gen_op_check_addo_64();
d9bce9d9
JM		 957}
958#endif
959GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 960/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 961GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 962/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 963GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 964/* addi */
965GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
966{
76a66253 967 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 968
969 if (rA(ctx->opcode) == 0) {
76a66253 970 /* li case */
d9bce9d9 971 gen_set_T0(simm);
79aceca5
FB		 972 } else {
973 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 974 if (likely(simm != 0))
975 gen_op_addi(simm);
79aceca5
FB		 976 }
977 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 978}
979/* addic */
980GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
981{
76a66253
JM		 982 target_long simm = SIMM(ctx->opcode);
983
79aceca5 984 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 985 if (likely(simm != 0)) {
986 gen_op_move_T2_T0();
987 gen_op_addi(simm);
988#if defined(TARGET_PPC64)
989 if (ctx->sf_mode)
990 gen_op_check_addc_64();
991 else
992#endif
993 gen_op_check_addc();
e864cabd
JM		 994 } else {
995 gen_op_clear_xer_ca();
d9bce9d9 996 }
79aceca5 997 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 998}
999/* addic. */
c7697e1f 1000GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1001{
76a66253
JM		 1002 target_long simm = SIMM(ctx->opcode);
1003
79aceca5 1004 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 1005 if (likely(simm != 0)) {
1006 gen_op_move_T2_T0();
1007 gen_op_addi(simm);
1008#if defined(TARGET_PPC64)
1009 if (ctx->sf_mode)
1010 gen_op_check_addc_64();
1011 else
1012#endif
1013 gen_op_check_addc();
966439a6
JM		 1014 } else {
1015 gen_op_clear_xer_ca();
d9bce9d9 1016 }
79aceca5 1017 gen_op_store_T0_gpr(rD(ctx->opcode));
76a66253 1018 gen_set_Rc0(ctx);
79aceca5
FB		 1019}
1020/* addis */
1021GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1022{
76a66253 1023 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1024
1025 if (rA(ctx->opcode) == 0) {
76a66253 1026 /* lis case */
d9bce9d9 1027 gen_set_T0(simm << 16);
79aceca5
FB		 1028 } else {
1029 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 1030 if (likely(simm != 0))
1031 gen_op_addi(simm << 16);
79aceca5
FB		 1032 }
1033 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1034}
1035/* mulli */
1036GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1037{
1038 gen_op_load_gpr_T0(rA(ctx->opcode));
1039 gen_op_mulli(SIMM(ctx->opcode));
1040 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1041}
1042/* subfic */
1043GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1044{
1045 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 1046#if defined(TARGET_PPC64)
1047 if (ctx->sf_mode)
1048 gen_op_subfic_64(SIMM(ctx->opcode));
1049 else
1050#endif
1051 gen_op_subfic(SIMM(ctx->opcode));
79aceca5 1052 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1053}
1054
d9bce9d9
JM		 1055#if defined(TARGET_PPC64)
1056/* mulhd mulhd. */
a750fc0b 1057GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1058/* mulhdu mulhdu. */
a750fc0b 1059GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1060/* mulld mulld. mulldo mulldo. */
a750fc0b 1061GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1062/* divd divd. divdo divdo. */
a750fc0b 1063GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1064/* divdu divdu. divduo divduo. */
a750fc0b 1065GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1066#endif
1067
79aceca5 1068/*** Integer comparison ***/
d9bce9d9
JM		 1069#if defined(TARGET_PPC64)
1070#define GEN_CMP(name, opc, type) \
1071GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1072{ \
1073 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1074 gen_op_load_gpr_T1(rB(ctx->opcode)); \
e3878283 1075 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
d9bce9d9
JM		 1076 gen_op_##name##_64(); \
1077 else \
1078 gen_op_##name(); \
1079 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1080}
1081#else
1082#define GEN_CMP(name, opc, type) \
1083GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
79aceca5
FB		 1084{ \
1085 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1086 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1087 gen_op_##name(); \
1088 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5 1089}
d9bce9d9 1090#endif
79aceca5
FB		 1091
1092/* cmp */
d9bce9d9 1093GEN_CMP(cmp, 0x00, PPC_INTEGER);
79aceca5
FB		 1094/* cmpi */
1095GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1096{
1097 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9 1098#if defined(TARGET_PPC64)
e3878283 1099 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1100 gen_op_cmpi_64(SIMM(ctx->opcode));
1101 else
1102#endif
1103 gen_op_cmpi(SIMM(ctx->opcode));
79aceca5 1104 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1105}
1106/* cmpl */
d9bce9d9 1107GEN_CMP(cmpl, 0x01, PPC_INTEGER);
79aceca5
FB		 1108/* cmpli */
1109GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1110{
1111 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9 1112#if defined(TARGET_PPC64)
e3878283 1113 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1114 gen_op_cmpli_64(UIMM(ctx->opcode));
1115 else
1116#endif
1117 gen_op_cmpli(UIMM(ctx->opcode));
79aceca5 1118 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1119}
1120
d9bce9d9
JM		 1121/* isel (PowerPC 2.03 specification) */
1122GEN_HANDLER(isel, 0x1F, 0x0F, 0x00, 0x00000001, PPC_203)
1123{
1124 uint32_t bi = rC(ctx->opcode);
1125 uint32_t mask;
1126
1127 if (rA(ctx->opcode) == 0) {
1128 gen_set_T0(0);
1129 } else {
1130 gen_op_load_gpr_T1(rA(ctx->opcode));
1131 }
1132 gen_op_load_gpr_T2(rB(ctx->opcode));
1133 mask = 1 << (3 - (bi & 0x03));
1134 gen_op_load_crf_T0(bi >> 2);
1135 gen_op_test_true(mask);
1136 gen_op_isel();
1137 gen_op_store_T0_gpr(rD(ctx->opcode));
1138}
1139
79aceca5 1140/*** Integer logical ***/
d9bce9d9
JM		 1141#define __GEN_LOGICAL2(name, opc2, opc3, type) \
1142GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
79aceca5
FB		 1143{ \
1144 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1145 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1146 gen_op_##name(); \
79aceca5 1147 gen_op_store_T0_gpr(rA(ctx->opcode)); \
76a66253
JM		 1148 if (unlikely(Rc(ctx->opcode) != 0)) \
1149 gen_set_Rc0(ctx); \
79aceca5 1150}
d9bce9d9
JM		 1151#define GEN_LOGICAL2(name, opc, type) \
1152__GEN_LOGICAL2(name, 0x1C, opc, type)
79aceca5 1153
d9bce9d9
JM		 1154#define GEN_LOGICAL1(name, opc, type) \
1155GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5
FB		 1156{ \
1157 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1158 gen_op_##name(); \
79aceca5 1159 gen_op_store_T0_gpr(rA(ctx->opcode)); \
76a66253
JM		 1160 if (unlikely(Rc(ctx->opcode) != 0)) \
1161 gen_set_Rc0(ctx); \
79aceca5
FB		 1162}
1163
1164/* and & and. */
d9bce9d9 1165GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
79aceca5 1166/* andc & andc. */
d9bce9d9 1167GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
79aceca5 1168/* andi. */
c7697e1f 1169GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5
FB		 1170{
1171 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253 1172 gen_op_andi_T0(UIMM(ctx->opcode));
79aceca5 1173 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253 1174 gen_set_Rc0(ctx);
79aceca5
FB		 1175}
1176/* andis. */
c7697e1f 1177GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5
FB		 1178{
1179 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253 1180 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
79aceca5 1181 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253 1182 gen_set_Rc0(ctx);
79aceca5
FB		 1183}
1184
1185/* cntlzw */
d9bce9d9 1186GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
79aceca5 1187/* eqv & eqv. */
d9bce9d9 1188GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
79aceca5 1189/* extsb & extsb. */
d9bce9d9 1190GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
79aceca5 1191/* extsh & extsh. */
d9bce9d9 1192GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
79aceca5 1193/* nand & nand. */
d9bce9d9 1194GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
79aceca5 1195/* nor & nor. */
d9bce9d9 1196GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
9a64fbe4 1197
79aceca5 1198/* or & or. */
9a64fbe4
FB		 1199GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1200{
76a66253
JM		 1201 int rs, ra, rb;
1202
1203 rs = rS(ctx->opcode);
1204 ra = rA(ctx->opcode);
1205 rb = rB(ctx->opcode);
1206 /* Optimisation for mr. ri case */
1207 if (rs != ra || rs != rb) {
1208 gen_op_load_gpr_T0(rs);
1209 if (rs != rb) {
1210 gen_op_load_gpr_T1(rb);
1211 gen_op_or();
1212 }
1213 gen_op_store_T0_gpr(ra);
1214 if (unlikely(Rc(ctx->opcode) != 0))
1215 gen_set_Rc0(ctx);
1216 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1217 gen_op_load_gpr_T0(rs);
1218 gen_set_Rc0(ctx);
c80f84e3
JM		 1219#if defined(TARGET_PPC64)
1220 } else {
1221 switch (rs) {
1222 case 1:
1223 /* Set process priority to low */
1224 gen_op_store_pri(2);
1225 break;
1226 case 6:
1227 /* Set process priority to medium-low */
1228 gen_op_store_pri(3);
1229 break;
1230 case 2:
1231 /* Set process priority to normal */
1232 gen_op_store_pri(4);
1233 break;
be147d08
JM		 1234#if !defined(CONFIG_USER_ONLY)
1235 case 31:
1236 if (ctx->supervisor > 0) {
1237 /* Set process priority to very low */
1238 gen_op_store_pri(1);
1239 }
1240 break;
1241 case 5:
1242 if (ctx->supervisor > 0) {
1243 /* Set process priority to medium-hight */
1244 gen_op_store_pri(5);
1245 }
1246 break;
1247 case 3:
1248 if (ctx->supervisor > 0) {
1249 /* Set process priority to high */
1250 gen_op_store_pri(6);
1251 }
1252 break;
1253#if defined(TARGET_PPC64H)
1254 case 7:
1255 if (ctx->supervisor > 1) {
1256 /* Set process priority to very high */
1257 gen_op_store_pri(7);
1258 }
1259 break;
1260#endif
1261#endif
c80f84e3
JM		 1262 default:
1263 /* nop */
1264 break;
1265 }
1266#endif
9a64fbe4 1267 }
9a64fbe4
FB		 1268}
1269
79aceca5 1270/* orc & orc. */
d9bce9d9 1271GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
79aceca5 1272/* xor & xor. */
9a64fbe4
FB		 1273GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1274{
1275 gen_op_load_gpr_T0(rS(ctx->opcode));
1276 /* Optimisation for "set to zero" case */
1277 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1278 gen_op_load_gpr_T1(rB(ctx->opcode));
1279 gen_op_xor();
1280 } else {
76a66253 1281 gen_op_reset_T0();
9a64fbe4 1282 }
9a64fbe4 1283 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1284 if (unlikely(Rc(ctx->opcode) != 0))
1285 gen_set_Rc0(ctx);
9a64fbe4 1286}
79aceca5
FB		 1287/* ori */
1288GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1289{
76a66253 1290 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1291
9a64fbe4
FB		 1292 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1293 /* NOP */
76a66253 1294 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1295 return;
76a66253
JM		 1296 }
1297 gen_op_load_gpr_T0(rS(ctx->opcode));
1298 if (likely(uimm != 0))
79aceca5 1299 gen_op_ori(uimm);
76a66253 1300 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1301}
1302/* oris */
1303GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1304{
76a66253 1305 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1306
9a64fbe4
FB		 1307 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1308 /* NOP */
1309 return;
76a66253
JM		 1310 }
1311 gen_op_load_gpr_T0(rS(ctx->opcode));
1312 if (likely(uimm != 0))
79aceca5 1313 gen_op_ori(uimm << 16);
76a66253 1314 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1315}
1316/* xori */
1317GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1318{
76a66253 1319 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1320
1321 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1322 /* NOP */
1323 return;
1324 }
79aceca5 1325 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1326 if (likely(uimm != 0))
1327 gen_op_xori(uimm);
79aceca5 1328 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1329}
1330
1331/* xoris */
1332GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1333{
76a66253 1334 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1335
1336 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1337 /* NOP */
1338 return;
1339 }
79aceca5 1340 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1341 if (likely(uimm != 0))
1342 gen_op_xori(uimm << 16);
79aceca5 1343 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1344}
1345
d9bce9d9
JM		 1346/* popcntb : PowerPC 2.03 specification */
1347GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_203)
1348{
1349 gen_op_load_gpr_T0(rS(ctx->opcode));
1350#if defined(TARGET_PPC64)
1351 if (ctx->sf_mode)
1352 gen_op_popcntb_64();
1353 else
1354#endif
1355 gen_op_popcntb();
1356 gen_op_store_T0_gpr(rA(ctx->opcode));
1357}
1358
1359#if defined(TARGET_PPC64)
1360/* extsw & extsw. */
1361GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1362/* cntlzd */
1363GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1364#endif
1365
79aceca5
FB		 1366/*** Integer rotate ***/
1367/* rlwimi & rlwimi. */
1368GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1369{
76a66253
JM		 1370 target_ulong mask;
1371 uint32_t mb, me, sh;
79aceca5
FB		 1372
1373 mb = MB(ctx->opcode);
1374 me = ME(ctx->opcode);
76a66253 1375 sh = SH(ctx->opcode);
76a66253
JM		 1376 if (likely(sh == 0)) {
1377 if (likely(mb == 0 && me == 31)) {
1378 gen_op_load_gpr_T0(rS(ctx->opcode));
1379 goto do_store;
1380 } else if (likely(mb == 31 && me == 0)) {
1381 gen_op_load_gpr_T0(rA(ctx->opcode));
1382 goto do_store;
1383 }
1384 gen_op_load_gpr_T0(rS(ctx->opcode));
1385 gen_op_load_gpr_T1(rA(ctx->opcode));
1386 goto do_mask;
1387 }
79aceca5 1388 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 1389 gen_op_load_gpr_T1(rA(ctx->opcode));
76a66253
JM		 1390 gen_op_rotli32_T0(SH(ctx->opcode));
1391 do_mask:
1392#if defined(TARGET_PPC64)
1393 mb += 32;
1394 me += 32;
1395#endif
1396 mask = MASK(mb, me);
1397 gen_op_andi_T0(mask);
1398 gen_op_andi_T1(~mask);
1399 gen_op_or();
1400 do_store:
79aceca5 1401 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1402 if (unlikely(Rc(ctx->opcode) != 0))
1403 gen_set_Rc0(ctx);
79aceca5
FB		 1404}
1405/* rlwinm & rlwinm. */
1406GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1407{
1408 uint32_t mb, me, sh;
3b46e624 1409
79aceca5
FB		 1410 sh = SH(ctx->opcode);
1411 mb = MB(ctx->opcode);
1412 me = ME(ctx->opcode);
1413 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1414 if (likely(sh == 0)) {
1415 goto do_mask;
1416 }
1417 if (likely(mb == 0)) {
1418 if (likely(me == 31)) {
1419 gen_op_rotli32_T0(sh);
1420 goto do_store;
1421 } else if (likely(me == (31 - sh))) {
1422 gen_op_sli_T0(sh);
1423 goto do_store;
79aceca5 1424 }
76a66253
JM		 1425 } else if (likely(me == 31)) {
1426 if (likely(sh == (32 - mb))) {
1427 gen_op_srli_T0(mb);
1428 goto do_store;
79aceca5
FB		 1429 }
1430 }
76a66253
JM		 1431 gen_op_rotli32_T0(sh);
1432 do_mask:
1433#if defined(TARGET_PPC64)
1434 mb += 32;
1435 me += 32;
1436#endif
1437 gen_op_andi_T0(MASK(mb, me));
1438 do_store:
79aceca5 1439 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1440 if (unlikely(Rc(ctx->opcode) != 0))
1441 gen_set_Rc0(ctx);
79aceca5
FB		 1442}
1443/* rlwnm & rlwnm. */
1444GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1445{
1446 uint32_t mb, me;
1447
1448 mb = MB(ctx->opcode);
1449 me = ME(ctx->opcode);
1450 gen_op_load_gpr_T0(rS(ctx->opcode));
1451 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 1452 gen_op_rotl32_T0_T1();
1453 if (unlikely(mb != 0 || me != 31)) {
1454#if defined(TARGET_PPC64)
1455 mb += 32;
1456 me += 32;
1457#endif
1458 gen_op_andi_T0(MASK(mb, me));
79aceca5 1459 }
79aceca5 1460 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1461 if (unlikely(Rc(ctx->opcode) != 0))
1462 gen_set_Rc0(ctx);
79aceca5
FB		 1463}
1464
d9bce9d9
JM		 1465#if defined(TARGET_PPC64)
1466#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1467GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1468{ \
1469 gen_##name(ctx, 0); \
1470} \
c7697e1f
JM		 1471GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1472 PPC_64B) \
d9bce9d9
JM		 1473{ \
1474 gen_##name(ctx, 1); \
1475}
1476#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1477GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1478{ \
1479 gen_##name(ctx, 0, 0); \
1480} \
c7697e1f
JM		 1481GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1482 PPC_64B) \
d9bce9d9
JM		 1483{ \
1484 gen_##name(ctx, 0, 1); \
1485} \
c7697e1f
JM		 1486GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1487 PPC_64B) \
d9bce9d9
JM		 1488{ \
1489 gen_##name(ctx, 1, 0); \
1490} \
c7697e1f
JM		 1491GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1492 PPC_64B) \
d9bce9d9
JM		 1493{ \
1494 gen_##name(ctx, 1, 1); \
1495}
51789c41 1496
b068d6a7 1497static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
40d0591e
JM		 1498{
1499 if (mask >> 32)
1500 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1501 else
1502 gen_op_andi_T0(mask);
1503}
1504
b068d6a7 1505static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
40d0591e
JM		 1506{
1507 if (mask >> 32)
1508 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1509 else
1510 gen_op_andi_T1(mask);
1511}
1512
b068d6a7
JM		 1513static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1514 uint32_t me, uint32_t sh)
51789c41
JM		 1515{
1516 gen_op_load_gpr_T0(rS(ctx->opcode));
1517 if (likely(sh == 0)) {
1518 goto do_mask;
1519 }
1520 if (likely(mb == 0)) {
1521 if (likely(me == 63)) {
40d0591e 1522 gen_op_rotli64_T0(sh);
51789c41
JM		 1523 goto do_store;
1524 } else if (likely(me == (63 - sh))) {
1525 gen_op_sli_T0(sh);
1526 goto do_store;
1527 }
1528 } else if (likely(me == 63)) {
1529 if (likely(sh == (64 - mb))) {
40d0591e 1530 gen_op_srli_T0_64(mb);
51789c41
JM		 1531 goto do_store;
1532 }
1533 }
1534 gen_op_rotli64_T0(sh);
1535 do_mask:
40d0591e 1536 gen_andi_T0_64(ctx, MASK(mb, me));
51789c41
JM		 1537 do_store:
1538 gen_op_store_T0_gpr(rA(ctx->opcode));
1539 if (unlikely(Rc(ctx->opcode) != 0))
1540 gen_set_Rc0(ctx);
1541}
d9bce9d9 1542/* rldicl - rldicl. */
b068d6a7 1543static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1544{
51789c41 1545 uint32_t sh, mb;
d9bce9d9 1546
9d53c753
JM		 1547 sh = SH(ctx->opcode) | (shn << 5);
1548 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1549 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1550}
51789c41 1551GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1552/* rldicr - rldicr. */
b068d6a7 1553static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1554{
51789c41 1555 uint32_t sh, me;
d9bce9d9 1556
9d53c753
JM		 1557 sh = SH(ctx->opcode) | (shn << 5);
1558 me = MB(ctx->opcode) | (men << 5);
51789c41 1559 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1560}
51789c41 1561GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1562/* rldic - rldic. */
b068d6a7 1563static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1564{
51789c41 1565 uint32_t sh, mb;
d9bce9d9 1566
9d53c753
JM		 1567 sh = SH(ctx->opcode) | (shn << 5);
1568 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1569 gen_rldinm(ctx, mb, 63 - sh, sh);
1570}
1571GEN_PPC64_R4(rldic, 0x1E, 0x04);
1572
b068d6a7
JM		 1573static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1574 uint32_t me)
51789c41
JM		 1575{
1576 gen_op_load_gpr_T0(rS(ctx->opcode));
1577 gen_op_load_gpr_T1(rB(ctx->opcode));
1578 gen_op_rotl64_T0_T1();
1579 if (unlikely(mb != 0 || me != 63)) {
40d0591e 1580 gen_andi_T0_64(ctx, MASK(mb, me));
51789c41
JM		 1581 }
1582 gen_op_store_T0_gpr(rA(ctx->opcode));
1583 if (unlikely(Rc(ctx->opcode) != 0))
1584 gen_set_Rc0(ctx);
d9bce9d9 1585}
51789c41 1586
d9bce9d9 1587/* rldcl - rldcl. */
b068d6a7 1588static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1589{
51789c41 1590 uint32_t mb;
d9bce9d9 1591
9d53c753 1592 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1593 gen_rldnm(ctx, mb, 63);
d9bce9d9 1594}
36081602 1595GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1596/* rldcr - rldcr. */
b068d6a7 1597static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1598{
51789c41 1599 uint32_t me;
d9bce9d9 1600
9d53c753 1601 me = MB(ctx->opcode) | (men << 5);
51789c41 1602 gen_rldnm(ctx, 0, me);
d9bce9d9 1603}
36081602 1604GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1605/* rldimi - rldimi. */
b068d6a7 1606static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1607{
51789c41 1608 uint64_t mask;
271a916e 1609 uint32_t sh, mb, me;
d9bce9d9 1610
9d53c753
JM		 1611 sh = SH(ctx->opcode) | (shn << 5);
1612 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1613 me = 63 - sh;
51789c41
JM		 1614 if (likely(sh == 0)) {
1615 if (likely(mb == 0)) {
1616 gen_op_load_gpr_T0(rS(ctx->opcode));
1617 goto do_store;
51789c41
JM		 1618 }
1619 gen_op_load_gpr_T0(rS(ctx->opcode));
1620 gen_op_load_gpr_T1(rA(ctx->opcode));
1621 goto do_mask;
1622 }
1623 gen_op_load_gpr_T0(rS(ctx->opcode));
1624 gen_op_load_gpr_T1(rA(ctx->opcode));
40d0591e 1625 gen_op_rotli64_T0(sh);
51789c41 1626 do_mask:
271a916e 1627 mask = MASK(mb, me);
40d0591e
JM		 1628 gen_andi_T0_64(ctx, mask);
1629 gen_andi_T1_64(ctx, ~mask);
51789c41
JM		 1630 gen_op_or();
1631 do_store:
1632 gen_op_store_T0_gpr(rA(ctx->opcode));
1633 if (unlikely(Rc(ctx->opcode) != 0))
1634 gen_set_Rc0(ctx);
d9bce9d9 1635}
36081602 1636GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1637#endif
1638
79aceca5
FB		 1639/*** Integer shift ***/
1640/* slw & slw. */
d9bce9d9 1641__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
79aceca5 1642/* sraw & sraw. */
d9bce9d9 1643__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
79aceca5
FB		 1644/* srawi & srawi. */
1645GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1646{
d9bce9d9 1647 int mb, me;
79aceca5 1648 gen_op_load_gpr_T0(rS(ctx->opcode));
d9bce9d9
JM		 1649 if (SH(ctx->opcode) != 0) {
1650 gen_op_move_T1_T0();
1651 mb = 32 - SH(ctx->opcode);
1652 me = 31;
1653#if defined(TARGET_PPC64)
1654 mb += 32;
1655 me += 32;
1656#endif
1657 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1658 }
79aceca5 1659 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1660 if (unlikely(Rc(ctx->opcode) != 0))
1661 gen_set_Rc0(ctx);
79aceca5
FB		 1662}
1663/* srw & srw. */
d9bce9d9
JM		 1664__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1665
1666#if defined(TARGET_PPC64)
1667/* sld & sld. */
1668__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1669/* srad & srad. */
1670__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1671/* sradi & sradi. */
b068d6a7 1672static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9
JM		 1673{
1674 uint64_t mask;
1675 int sh, mb, me;
1676
1677 gen_op_load_gpr_T0(rS(ctx->opcode));
1678 sh = SH(ctx->opcode) + (n << 5);
1679 if (sh != 0) {
1680 gen_op_move_T1_T0();
1681 mb = 64 - SH(ctx->opcode);
1682 me = 63;
1683 mask = MASK(mb, me);
1684 gen_op_sradi(sh, mask >> 32, mask);
1685 }
1686 gen_op_store_T0_gpr(rA(ctx->opcode));
1687 if (unlikely(Rc(ctx->opcode) != 0))
1688 gen_set_Rc0(ctx);
1689}
c7697e1f 1690GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1691{
1692 gen_sradi(ctx, 0);
1693}
c7697e1f 1694GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1695{
1696 gen_sradi(ctx, 1);
1697}
1698/* srd & srd. */
1699__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1700#endif
79aceca5
FB		 1701
1702/*** Floating-Point arithmetic ***/
7c58044c 1703#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1704GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1705{ \
76a66253 1706 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1707 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1708 return; \
1709 } \
9a64fbe4
FB		 1710 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1711 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1712 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
7c58044c 1713 gen_reset_fpstatus(); \
4ecc3190
FB		 1714 gen_op_f##op(); \
1715 if (isfloat) { \
1716 gen_op_frsp(); \
1717 } \
9a64fbe4 1718 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1719 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1720}
1721
7c58044c
JM		 1722#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1723_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1724_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1725
7c58044c
JM		 1726#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1727GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1728{ \
76a66253 1729 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1730 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1731 return; \
1732 } \
9a64fbe4
FB		 1733 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1734 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
7c58044c 1735 gen_reset_fpstatus(); \
4ecc3190
FB		 1736 gen_op_f##op(); \
1737 if (isfloat) { \
1738 gen_op_frsp(); \
1739 } \
9a64fbe4 1740 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1741 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1742}
7c58044c
JM		 1743#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1744_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1745_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1746
7c58044c
JM		 1747#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1748GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1749{ \
76a66253 1750 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1751 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1752 return; \
1753 } \
9a64fbe4
FB		 1754 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1755 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
7c58044c 1756 gen_reset_fpstatus(); \
4ecc3190
FB		 1757 gen_op_f##op(); \
1758 if (isfloat) { \
1759 gen_op_frsp(); \
1760 } \
9a64fbe4 1761 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1762 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1763}
7c58044c
JM		 1764#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1765_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1766_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1767
7c58044c 1768#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 1769GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 1770{ \
76a66253 1771 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1772 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1773 return; \
1774 } \
9a64fbe4 1775 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
7c58044c 1776 gen_reset_fpstatus(); \
9a64fbe4
FB		 1777 gen_op_f##name(); \
1778 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1779 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1780}
1781
7c58044c 1782#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 1783GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 1784{ \
76a66253 1785 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1786 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1787 return; \
1788 } \
9a64fbe4 1789 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
7c58044c 1790 gen_reset_fpstatus(); \
9a64fbe4
FB		 1791 gen_op_f##name(); \
1792 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1793 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1794}
1795
9a64fbe4 1796/* fadd - fadds */
7c58044c 1797GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1798/* fdiv - fdivs */
7c58044c 1799GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1800/* fmul - fmuls */
7c58044c 1801GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 1802
d7e4b87e 1803/* fre */
7c58044c 1804GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 1805
a750fc0b 1806/* fres */
7c58044c 1807GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 1808
a750fc0b 1809/* frsqrte */
7c58044c
JM		 1810GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1811
1812/* frsqrtes */
1813static always_inline void gen_op_frsqrtes (void)
1814{
1815 gen_op_frsqrte();
1816 gen_op_frsp();
1817}
1b413d55 1818GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 1819
a750fc0b 1820/* fsel */
7c58044c 1821_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 1822/* fsub - fsubs */
7c58044c 1823GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 1824/* Optional: */
1825/* fsqrt */
a750fc0b 1826GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 1827{
76a66253 1828 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1829 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 1830 return;
1831 }
c7d344af 1832 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 1833 gen_reset_fpstatus();
c7d344af
FB		 1834 gen_op_fsqrt();
1835 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1836 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 1837}
79aceca5 1838
a750fc0b 1839GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 1840{
76a66253 1841 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1842 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1843 return;
1844 }
9a64fbe4 1845 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 1846 gen_reset_fpstatus();
4ecc3190
FB		 1847 gen_op_fsqrt();
1848 gen_op_frsp();
9a64fbe4 1849 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1850 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 1851}
1852
1853/*** Floating-Point multiply-and-add ***/
4ecc3190 1854/* fmadd - fmadds */
7c58044c 1855GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 1856/* fmsub - fmsubs */
7c58044c 1857GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 1858/* fnmadd - fnmadds */
7c58044c 1859GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 1860/* fnmsub - fnmsubs */
7c58044c 1861GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 1862
1863/*** Floating-Point round & convert ***/
1864/* fctiw */
7c58044c 1865GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 1866/* fctiwz */
7c58044c 1867GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 1868/* frsp */
7c58044c 1869GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 1870#if defined(TARGET_PPC64)
1871/* fcfid */
7c58044c 1872GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 1873/* fctid */
7c58044c 1874GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 1875/* fctidz */
7c58044c 1876GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 1877#endif
79aceca5 1878
d7e4b87e 1879/* frin */
7c58044c 1880GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 1881/* friz */
7c58044c 1882GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 1883/* frip */
7c58044c 1884GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 1885/* frim */
7c58044c 1886GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 1887
79aceca5
FB		 1888/*** Floating-Point compare ***/
1889/* fcmpo */
76a66253 1890GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 1891{
76a66253 1892 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1893 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1894 return;
1895 }
9a64fbe4
FB		 1896 gen_op_load_fpr_FT0(rA(ctx->opcode));
1897 gen_op_load_fpr_FT1(rB(ctx->opcode));
7c58044c 1898 gen_reset_fpstatus();
9a64fbe4
FB		 1899 gen_op_fcmpo();
1900 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1901 gen_op_float_check_status();
79aceca5
FB		 1902}
1903
1904/* fcmpu */
76a66253 1905GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 1906{
76a66253 1907 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1908 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1909 return;
1910 }
9a64fbe4
FB		 1911 gen_op_load_fpr_FT0(rA(ctx->opcode));
1912 gen_op_load_fpr_FT1(rB(ctx->opcode));
7c58044c 1913 gen_reset_fpstatus();
9a64fbe4
FB		 1914 gen_op_fcmpu();
1915 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1916 gen_op_float_check_status();
79aceca5
FB		 1917}
1918
9a64fbe4
FB		 1919/*** Floating-point move ***/
1920/* fabs */
7c58044c
JM		 1921/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1922GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 1923
1924/* fmr - fmr. */
7c58044c 1925/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 1926GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1927{
76a66253 1928 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1929 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1930 return;
1931 }
9a64fbe4
FB		 1932 gen_op_load_fpr_FT0(rB(ctx->opcode));
1933 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1934 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 1935}
1936
1937/* fnabs */
7c58044c
JM		 1938/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1939GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 1940/* fneg */
7c58044c
JM		 1941/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1942GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 1943
79aceca5
FB		 1944/*** Floating-Point status & ctrl register ***/
1945/* mcrfs */
1946GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1947{
7c58044c
JM		 1948 int bfa;
1949
76a66253 1950 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1951 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1952 return;
1953 }
7c58044c
JM		 1954 gen_optimize_fprf();
1955 bfa = 4 * (7 - crfS(ctx->opcode));
1956 gen_op_load_fpscr_T0(bfa);
fb0eaffc 1957 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1958 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 1959}
1960
1961/* mffs */
1962GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1963{
76a66253 1964 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1965 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1966 return;
1967 }
7c58044c
JM		 1968 gen_optimize_fprf();
1969 gen_reset_fpstatus();
1970 gen_op_load_fpscr_FT0();
fb0eaffc 1971 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1972 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 1973}
1974
1975/* mtfsb0 */
1976GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1977{
fb0eaffc 1978 uint8_t crb;
3b46e624 1979
76a66253 1980 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1981 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1982 return;
1983 }
7c58044c
JM		 1984 crb = 32 - (crbD(ctx->opcode) >> 2);
1985 gen_optimize_fprf();
1986 gen_reset_fpstatus();
1987 if (likely(crb != 30 && crb != 29))
1988 gen_op_fpscr_resetbit(~(1 << crb));
1989 if (unlikely(Rc(ctx->opcode) != 0)) {
1990 gen_op_load_fpcc();
1991 gen_op_set_Rc0();
1992 }
79aceca5
FB		 1993}
1994
1995/* mtfsb1 */
1996GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1997{
fb0eaffc 1998 uint8_t crb;
3b46e624 1999
76a66253 2000 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2001 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2002 return;
2003 }
7c58044c
JM		 2004 crb = 32 - (crbD(ctx->opcode) >> 2);
2005 gen_optimize_fprf();
2006 gen_reset_fpstatus();
2007 /* XXX: we pretend we can only do IEEE floating-point computations */
2008 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2009 gen_op_fpscr_setbit(crb);
2010 if (unlikely(Rc(ctx->opcode) != 0)) {
2011 gen_op_load_fpcc();
2012 gen_op_set_Rc0();
2013 }
2014 /* We can raise a differed exception */
2015 gen_op_float_check_status();
79aceca5
FB		 2016}
2017
2018/* mtfsf */
2019GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2020{
76a66253 2021 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2022 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2023 return;
2024 }
7c58044c 2025 gen_optimize_fprf();
fb0eaffc 2026 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 2027 gen_reset_fpstatus();
28b6751f 2028 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c
JM		 2029 if (unlikely(Rc(ctx->opcode) != 0)) {
2030 gen_op_load_fpcc();
2031 gen_op_set_Rc0();
2032 }
2033 /* We can raise a differed exception */
2034 gen_op_float_check_status();
79aceca5
FB		 2035}
2036
2037/* mtfsfi */
2038GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2039{
7c58044c
JM		 2040 int bf, sh;
2041
76a66253 2042 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2043 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2044 return;
2045 }
7c58044c
JM		 2046 bf = crbD(ctx->opcode) >> 2;
2047 sh = 7 - bf;
2048 gen_optimize_fprf();
2049 gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2050 gen_reset_fpstatus();
2051 gen_op_store_fpscr(1 << sh);
2052 if (unlikely(Rc(ctx->opcode) != 0)) {
2053 gen_op_load_fpcc();
2054 gen_op_set_Rc0();
2055 }
2056 /* We can raise a differed exception */
2057 gen_op_float_check_status();
79aceca5
FB		 2058}
2059
76a66253
JM		 2060/*** Addressing modes ***/
2061/* Register indirect with immediate index : EA = (rA|0) + SIMM */
b068d6a7
JM		 2062static always_inline void gen_addr_imm_index (DisasContext *ctx,
2063 target_long maskl)
76a66253
JM		 2064{
2065 target_long simm = SIMM(ctx->opcode);
2066
be147d08 2067 simm &= ~maskl;
76a66253 2068 if (rA(ctx->opcode) == 0) {
d9bce9d9 2069 gen_set_T0(simm);
76a66253
JM		 2070 } else {
2071 gen_op_load_gpr_T0(rA(ctx->opcode));
2072 if (likely(simm != 0))
2073 gen_op_addi(simm);
2074 }
a496775f
JM		 2075#ifdef DEBUG_MEMORY_ACCESSES
2076 gen_op_print_mem_EA();
2077#endif
76a66253
JM		 2078}
2079
b068d6a7 2080static always_inline void gen_addr_reg_index (DisasContext *ctx)
76a66253
JM		 2081{
2082 if (rA(ctx->opcode) == 0) {
2083 gen_op_load_gpr_T0(rB(ctx->opcode));
2084 } else {
2085 gen_op_load_gpr_T0(rA(ctx->opcode));
2086 gen_op_load_gpr_T1(rB(ctx->opcode));
2087 gen_op_add();
2088 }
a496775f
JM		 2089#ifdef DEBUG_MEMORY_ACCESSES
2090 gen_op_print_mem_EA();
2091#endif
76a66253
JM		 2092}
2093
b068d6a7 2094static always_inline void gen_addr_register (DisasContext *ctx)
76a66253
JM		 2095{
2096 if (rA(ctx->opcode) == 0) {
2097 gen_op_reset_T0();
2098 } else {
2099 gen_op_load_gpr_T0(rA(ctx->opcode));
2100 }
a496775f
JM		 2101#ifdef DEBUG_MEMORY_ACCESSES
2102 gen_op_print_mem_EA();
2103#endif
76a66253
JM		 2104}
2105
79aceca5 2106/*** Integer load ***/
111bfab3 2107#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
9a64fbe4 2108#if defined(CONFIG_USER_ONLY)
d9bce9d9 2109#if defined(TARGET_PPC64)
2857068e 2110/* User mode only - 64 bits */
111bfab3
FB		 2111#define OP_LD_TABLE(width) \
2112static GenOpFunc *gen_op_l##width[] = { \
2113 &gen_op_l##width##_raw, \
2114 &gen_op_l##width##_le_raw, \
d9bce9d9
JM		 2115 &gen_op_l##width##_64_raw, \
2116 &gen_op_l##width##_le_64_raw, \
111bfab3
FB		 2117};
2118#define OP_ST_TABLE(width) \
2119static GenOpFunc *gen_op_st##width[] = { \
2120 &gen_op_st##width##_raw, \
2121 &gen_op_st##width##_le_raw, \
d9bce9d9
JM		 2122 &gen_op_st##width##_64_raw, \
2123 &gen_op_st##width##_le_64_raw, \
111bfab3
FB		 2124};
2125/* Byte access routine are endian safe */
d9bce9d9
JM		 2126#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2127#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2128#else
2857068e 2129/* User mode only - 32 bits */
d9bce9d9
JM		 2130#define OP_LD_TABLE(width) \
2131static GenOpFunc *gen_op_l##width[] = { \
2132 &gen_op_l##width##_raw, \
2133 &gen_op_l##width##_le_raw, \
2134};
2135#define OP_ST_TABLE(width) \
2136static GenOpFunc *gen_op_st##width[] = { \
2137 &gen_op_st##width##_raw, \
2138 &gen_op_st##width##_le_raw, \
2139};
2140#endif
2141/* Byte access routine are endian safe */
111bfab3
FB		 2142#define gen_op_stb_le_raw gen_op_stb_raw
2143#define gen_op_lbz_le_raw gen_op_lbz_raw
9a64fbe4 2144#else
d9bce9d9 2145#if defined(TARGET_PPC64)
2857068e
JM		 2146#if defined(TARGET_PPC64H)
2147/* Full system - 64 bits with hypervisor mode */
9a64fbe4
FB		 2148#define OP_LD_TABLE(width) \
2149static GenOpFunc *gen_op_l##width[] = { \
2150 &gen_op_l##width##_user, \
111bfab3 2151 &gen_op_l##width##_le_user, \
d9bce9d9
JM		 2152 &gen_op_l##width##_64_user, \
2153 &gen_op_l##width##_le_64_user, \
2857068e
JM		 2154 &gen_op_l##width##_kernel, \
2155 &gen_op_l##width##_le_kernel, \
d9bce9d9
JM		 2156 &gen_op_l##width##_64_kernel, \
2157 &gen_op_l##width##_le_64_kernel, \
2857068e
JM		 2158 &gen_op_l##width##_hypv, \
2159 &gen_op_l##width##_le_hypv, \
2160 &gen_op_l##width##_64_hypv, \
2161 &gen_op_l##width##_le_64_hypv, \
111bfab3 2162};
9a64fbe4
FB		 2163#define OP_ST_TABLE(width) \
2164static GenOpFunc *gen_op_st##width[] = { \
2165 &gen_op_st##width##_user, \
111bfab3 2166 &gen_op_st##width##_le_user, \
2857068e
JM		 2167 &gen_op_st##width##_64_user, \
2168 &gen_op_st##width##_le_64_user, \
9a64fbe4 2169 &gen_op_st##width##_kernel, \
111bfab3 2170 &gen_op_st##width##_le_kernel, \
2857068e
JM		 2171 &gen_op_st##width##_64_kernel, \
2172 &gen_op_st##width##_le_64_kernel, \
2173 &gen_op_st##width##_hypv, \
2174 &gen_op_st##width##_le_hypv, \
2175 &gen_op_st##width##_64_hypv, \
2176 &gen_op_st##width##_le_64_hypv, \
2177};
2178/* Byte access routine are endian safe */
2179#define gen_op_stb_le_hypv gen_op_stb_64_hypv
2180#define gen_op_lbz_le_hypv gen_op_lbz_64_hypv
2181#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
2182#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2183#else
2184/* Full system - 64 bits */
2185#define OP_LD_TABLE(width) \
2186static GenOpFunc *gen_op_l##width[] = { \
2187 &gen_op_l##width##_user, \
2188 &gen_op_l##width##_le_user, \
2189 &gen_op_l##width##_64_user, \
2190 &gen_op_l##width##_le_64_user, \
2191 &gen_op_l##width##_kernel, \
2192 &gen_op_l##width##_le_kernel, \
2193 &gen_op_l##width##_64_kernel, \
2194 &gen_op_l##width##_le_64_kernel, \
2195};
2196#define OP_ST_TABLE(width) \
2197static GenOpFunc *gen_op_st##width[] = { \
2198 &gen_op_st##width##_user, \
2199 &gen_op_st##width##_le_user, \
d9bce9d9
JM		 2200 &gen_op_st##width##_64_user, \
2201 &gen_op_st##width##_le_64_user, \
2857068e
JM		 2202 &gen_op_st##width##_kernel, \
2203 &gen_op_st##width##_le_kernel, \
d9bce9d9
JM		 2204 &gen_op_st##width##_64_kernel, \
2205 &gen_op_st##width##_le_64_kernel, \
111bfab3 2206};
2857068e 2207#endif
111bfab3 2208/* Byte access routine are endian safe */
2857068e
JM		 2209#define gen_op_stb_le_64_user gen_op_stb_64_user
2210#define gen_op_lbz_le_64_user gen_op_lbz_64_user
d9bce9d9
JM		 2211#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2212#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
2213#else
2857068e 2214/* Full system - 32 bits */
d9bce9d9
JM		 2215#define OP_LD_TABLE(width) \
2216static GenOpFunc *gen_op_l##width[] = { \
2217 &gen_op_l##width##_user, \
2218 &gen_op_l##width##_le_user, \
2219 &gen_op_l##width##_kernel, \
2220 &gen_op_l##width##_le_kernel, \
2221};
2222#define OP_ST_TABLE(width) \
2223static GenOpFunc *gen_op_st##width[] = { \
2224 &gen_op_st##width##_user, \
2225 &gen_op_st##width##_le_user, \
2226 &gen_op_st##width##_kernel, \
2227 &gen_op_st##width##_le_kernel, \
2228};
2229#endif
2230/* Byte access routine are endian safe */
2857068e
JM		 2231#define gen_op_stb_le_user gen_op_stb_user
2232#define gen_op_lbz_le_user gen_op_lbz_user
111bfab3
FB		 2233#define gen_op_stb_le_kernel gen_op_stb_kernel
2234#define gen_op_lbz_le_kernel gen_op_lbz_kernel
9a64fbe4
FB		 2235#endif
2236
d9bce9d9
JM		 2237#define GEN_LD(width, opc, type) \
2238GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2239{ \
9d53c753 2240 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2241 op_ldst(l##width); \
79aceca5 2242 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 2243}
2244
d9bce9d9
JM		 2245#define GEN_LDU(width, opc, type) \
2246GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2247{ \
76a66253
JM		 2248 if (unlikely(rA(ctx->opcode) == 0 || \
2249 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2250 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2251 return; \
9a64fbe4 2252 } \
9d53c753 2253 if (type == PPC_64B) \
be147d08 2254 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2255 else \
2256 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2257 op_ldst(l##width); \
79aceca5
FB		 2258 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2259 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2260}
2261
d9bce9d9
JM		 2262#define GEN_LDUX(width, opc2, opc3, type) \
2263GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2264{ \
76a66253
JM		 2265 if (unlikely(rA(ctx->opcode) == 0 || \
2266 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2267 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2268 return; \
9a64fbe4 2269 } \
76a66253 2270 gen_addr_reg_index(ctx); \
9a64fbe4 2271 op_ldst(l##width); \
79aceca5
FB		 2272 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2273 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2274}
2275
d9bce9d9
JM		 2276#define GEN_LDX(width, opc2, opc3, type) \
2277GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2278{ \
76a66253 2279 gen_addr_reg_index(ctx); \
9a64fbe4 2280 op_ldst(l##width); \
79aceca5 2281 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 2282}
2283
d9bce9d9 2284#define GEN_LDS(width, op, type) \
9a64fbe4 2285OP_LD_TABLE(width); \
d9bce9d9
JM		 2286GEN_LD(width, op | 0x20, type); \
2287GEN_LDU(width, op | 0x21, type); \
2288GEN_LDUX(width, 0x17, op | 0x01, type); \
2289GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2290
2291/* lbz lbzu lbzux lbzx */
d9bce9d9 2292GEN_LDS(bz, 0x02, PPC_INTEGER);
79aceca5 2293/* lha lhau lhaux lhax */
d9bce9d9 2294GEN_LDS(ha, 0x0A, PPC_INTEGER);
79aceca5 2295/* lhz lhzu lhzux lhzx */
d9bce9d9 2296GEN_LDS(hz, 0x08, PPC_INTEGER);
79aceca5 2297/* lwz lwzu lwzux lwzx */
d9bce9d9
JM		 2298GEN_LDS(wz, 0x00, PPC_INTEGER);
2299#if defined(TARGET_PPC64)
2300OP_LD_TABLE(wa);
2301OP_LD_TABLE(d);
2302/* lwaux */
2303GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2304/* lwax */
2305GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2306/* ldux */
2307GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2308/* ldx */
2309GEN_LDX(d, 0x15, 0x00, PPC_64B);
2310GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2311{
2312 if (Rc(ctx->opcode)) {
2313 if (unlikely(rA(ctx->opcode) == 0 ||
2314 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2315 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2316 return;
2317 }
2318 }
be147d08 2319 gen_addr_imm_index(ctx, 0x03);
d9bce9d9
JM		 2320 if (ctx->opcode & 0x02) {
2321 /* lwa (lwau is undefined) */
2322 op_ldst(lwa);
2323 } else {
2324 /* ld - ldu */
2325 op_ldst(ld);
2326 }
2327 gen_op_store_T1_gpr(rD(ctx->opcode));
2328 if (Rc(ctx->opcode))
2329 gen_op_store_T0_gpr(rA(ctx->opcode));
2330}
be147d08
JM		 2331/* lq */
2332GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2333{
2334#if defined(CONFIG_USER_ONLY)
2335 GEN_EXCP_PRIVOPC(ctx);
2336#else
2337 int ra, rd;
2338
2339 /* Restore CPU state */
2340 if (unlikely(ctx->supervisor == 0)) {
2341 GEN_EXCP_PRIVOPC(ctx);
2342 return;
2343 }
2344 ra = rA(ctx->opcode);
2345 rd = rD(ctx->opcode);
2346 if (unlikely((rd & 1) || rd == ra)) {
2347 GEN_EXCP_INVAL(ctx);
2348 return;
2349 }
2350 if (unlikely(ctx->mem_idx & 1)) {
2351 /* Little-endian mode is not handled */
2352 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2353 return;
2354 }
2355 gen_addr_imm_index(ctx, 0x0F);
2356 op_ldst(ld);
2357 gen_op_store_T1_gpr(rd);
2358 gen_op_addi(8);
2359 op_ldst(ld);
2360 gen_op_store_T1_gpr(rd + 1);
2361#endif
2362}
d9bce9d9 2363#endif
79aceca5
FB		 2364
2365/*** Integer store ***/
d9bce9d9
JM		 2366#define GEN_ST(width, opc, type) \
2367GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2368{ \
9d53c753 2369 gen_addr_imm_index(ctx, 0); \
9a64fbe4
FB		 2370 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2371 op_ldst(st##width); \
79aceca5
FB		 2372}
2373
d9bce9d9
JM		 2374#define GEN_STU(width, opc, type) \
2375GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2376{ \
76a66253 2377 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2378 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2379 return; \
9a64fbe4 2380 } \
9d53c753 2381 if (type == PPC_64B) \
be147d08 2382 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2383 else \
2384 gen_addr_imm_index(ctx, 0); \
79aceca5 2385 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 2386 op_ldst(st##width); \
79aceca5 2387 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2388}
2389
d9bce9d9
JM		 2390#define GEN_STUX(width, opc2, opc3, type) \
2391GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2392{ \
76a66253 2393 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2394 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2395 return; \
9a64fbe4 2396 } \
76a66253 2397 gen_addr_reg_index(ctx); \
9a64fbe4
FB		 2398 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2399 op_ldst(st##width); \
79aceca5 2400 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2401}
2402
d9bce9d9
JM		 2403#define GEN_STX(width, opc2, opc3, type) \
2404GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2405{ \
76a66253 2406 gen_addr_reg_index(ctx); \
9a64fbe4
FB		 2407 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2408 op_ldst(st##width); \
79aceca5
FB		 2409}
2410
d9bce9d9 2411#define GEN_STS(width, op, type) \
9a64fbe4 2412OP_ST_TABLE(width); \
d9bce9d9
JM		 2413GEN_ST(width, op | 0x20, type); \
2414GEN_STU(width, op | 0x21, type); \
2415GEN_STUX(width, 0x17, op | 0x01, type); \
2416GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2417
2418/* stb stbu stbux stbx */
d9bce9d9 2419GEN_STS(b, 0x06, PPC_INTEGER);
79aceca5 2420/* sth sthu sthux sthx */
d9bce9d9 2421GEN_STS(h, 0x0C, PPC_INTEGER);
79aceca5 2422/* stw stwu stwux stwx */
d9bce9d9
JM		 2423GEN_STS(w, 0x04, PPC_INTEGER);
2424#if defined(TARGET_PPC64)
2425OP_ST_TABLE(d);
426613db
JM		 2426GEN_STUX(d, 0x15, 0x05, PPC_64B);
2427GEN_STX(d, 0x15, 0x04, PPC_64B);
be147d08 2428GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2429{
be147d08
JM		 2430 int rs;
2431
2432 rs = rS(ctx->opcode);
2433 if ((ctx->opcode & 0x3) == 0x2) {
2434#if defined(CONFIG_USER_ONLY)
2435 GEN_EXCP_PRIVOPC(ctx);
2436#else
2437 /* stq */
2438 if (unlikely(ctx->supervisor == 0)) {
2439 GEN_EXCP_PRIVOPC(ctx);
2440 return;
2441 }
2442 if (unlikely(rs & 1)) {
e1833e1f 2443 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2444 return;
2445 }
be147d08
JM		 2446 if (unlikely(ctx->mem_idx & 1)) {
2447 /* Little-endian mode is not handled */
2448 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2449 return;
2450 }
2451 gen_addr_imm_index(ctx, 0x03);
2452 gen_op_load_gpr_T1(rs);
2453 op_ldst(std);
2454 gen_op_addi(8);
2455 gen_op_load_gpr_T1(rs + 1);
2456 op_ldst(std);
2457#endif
2458 } else {
2459 /* std / stdu */
2460 if (Rc(ctx->opcode)) {
2461 if (unlikely(rA(ctx->opcode) == 0)) {
2462 GEN_EXCP_INVAL(ctx);
2463 return;
2464 }
2465 }
2466 gen_addr_imm_index(ctx, 0x03);
2467 gen_op_load_gpr_T1(rs);
2468 op_ldst(std);
2469 if (Rc(ctx->opcode))
2470 gen_op_store_T0_gpr(rA(ctx->opcode));
d9bce9d9 2471 }
d9bce9d9
JM		 2472}
2473#endif
79aceca5
FB		 2474/*** Integer load and store with byte reverse ***/
2475/* lhbrx */
9a64fbe4 2476OP_LD_TABLE(hbr);
d9bce9d9 2477GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
79aceca5 2478/* lwbrx */
9a64fbe4 2479OP_LD_TABLE(wbr);
d9bce9d9 2480GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
79aceca5 2481/* sthbrx */
9a64fbe4 2482OP_ST_TABLE(hbr);
d9bce9d9 2483GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
79aceca5 2484/* stwbrx */
9a64fbe4 2485OP_ST_TABLE(wbr);
d9bce9d9 2486GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2487
2488/*** Integer load and store multiple ***/
111bfab3 2489#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
d9bce9d9 2490#if defined(CONFIG_USER_ONLY)
2857068e 2491/* User-mode only */
d9bce9d9
JM		 2492static GenOpFunc1 *gen_op_lmw[] = {
2493 &gen_op_lmw_raw,
2494 &gen_op_lmw_le_raw,
2857068e 2495#if defined(TARGET_PPC64)
d9bce9d9
JM		 2496 &gen_op_lmw_64_raw,
2497 &gen_op_lmw_le_64_raw,
2857068e 2498#endif
d9bce9d9
JM		 2499};
2500static GenOpFunc1 *gen_op_stmw[] = {
2857068e
JM		 2501 &gen_op_stmw_raw,
2502 &gen_op_stmw_le_raw,
2503#if defined(TARGET_PPC64)
d9bce9d9
JM		 2504 &gen_op_stmw_64_raw,
2505 &gen_op_stmw_le_64_raw,
2857068e 2506#endif
d9bce9d9
JM		 2507};
2508#else
2857068e
JM		 2509#if defined(TARGET_PPC64)
2510/* Full system - 64 bits mode */
d9bce9d9
JM		 2511static GenOpFunc1 *gen_op_lmw[] = {
2512 &gen_op_lmw_user,
2513 &gen_op_lmw_le_user,
d9bce9d9
JM		 2514 &gen_op_lmw_64_user,
2515 &gen_op_lmw_le_64_user,
2857068e
JM		 2516 &gen_op_lmw_kernel,
2517 &gen_op_lmw_le_kernel,
d9bce9d9
JM		 2518 &gen_op_lmw_64_kernel,
2519 &gen_op_lmw_le_64_kernel,
2857068e
JM		 2520#if defined(TARGET_PPC64H)
2521 &gen_op_lmw_hypv,
2522 &gen_op_lmw_le_hypv,
2523 &gen_op_lmw_64_hypv,
2524 &gen_op_lmw_le_64_hypv,
2525#endif
d9bce9d9
JM		 2526};
2527static GenOpFunc1 *gen_op_stmw[] = {
2528 &gen_op_stmw_user,
2529 &gen_op_stmw_le_user,
d9bce9d9
JM		 2530 &gen_op_stmw_64_user,
2531 &gen_op_stmw_le_64_user,
2857068e
JM		 2532 &gen_op_stmw_kernel,
2533 &gen_op_stmw_le_kernel,
d9bce9d9
JM		 2534 &gen_op_stmw_64_kernel,
2535 &gen_op_stmw_le_64_kernel,
2857068e
JM		 2536#if defined(TARGET_PPC64H)
2537 &gen_op_stmw_hypv,
2538 &gen_op_stmw_le_hypv,
2539 &gen_op_stmw_64_hypv,
2540 &gen_op_stmw_le_64_hypv,
d9bce9d9 2541#endif
111bfab3 2542};
9a64fbe4 2543#else
2857068e 2544/* Full system - 32 bits mode */
9a64fbe4
FB		 2545static GenOpFunc1 *gen_op_lmw[] = {
2546 &gen_op_lmw_user,
111bfab3 2547 &gen_op_lmw_le_user,
9a64fbe4 2548 &gen_op_lmw_kernel,
111bfab3 2549 &gen_op_lmw_le_kernel,
9a64fbe4
FB		 2550};
2551static GenOpFunc1 *gen_op_stmw[] = {
2552 &gen_op_stmw_user,
111bfab3 2553 &gen_op_stmw_le_user,
9a64fbe4 2554 &gen_op_stmw_kernel,
111bfab3 2555 &gen_op_stmw_le_kernel,
9a64fbe4
FB		 2556};
2557#endif
d9bce9d9 2558#endif
9a64fbe4 2559
79aceca5
FB		 2560/* lmw */
2561GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2562{
76a66253 2563 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2564 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2565 gen_addr_imm_index(ctx, 0);
9a64fbe4 2566 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2567}
2568
2569/* stmw */
2570GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2571{
76a66253 2572 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2573 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2574 gen_addr_imm_index(ctx, 0);
9a64fbe4 2575 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2576}
2577
2578/*** Integer load and store strings ***/
9a64fbe4
FB		 2579#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2580#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
d9bce9d9 2581#if defined(CONFIG_USER_ONLY)
2857068e 2582/* User-mode only */
d9bce9d9
JM		 2583static GenOpFunc1 *gen_op_lswi[] = {
2584 &gen_op_lswi_raw,
2585 &gen_op_lswi_le_raw,
2857068e 2586#if defined(TARGET_PPC64)
d9bce9d9
JM		 2587 &gen_op_lswi_64_raw,
2588 &gen_op_lswi_le_64_raw,
2857068e 2589#endif
d9bce9d9
JM		 2590};
2591static GenOpFunc3 *gen_op_lswx[] = {
2592 &gen_op_lswx_raw,
2593 &gen_op_lswx_le_raw,
2857068e 2594#if defined(TARGET_PPC64)
d9bce9d9
JM		 2595 &gen_op_lswx_64_raw,
2596 &gen_op_lswx_le_64_raw,
2857068e 2597#endif
d9bce9d9
JM		 2598};
2599static GenOpFunc1 *gen_op_stsw[] = {
2600 &gen_op_stsw_raw,
2601 &gen_op_stsw_le_raw,
2857068e 2602#if defined(TARGET_PPC64)
d9bce9d9
JM		 2603 &gen_op_stsw_64_raw,
2604 &gen_op_stsw_le_64_raw,
2857068e 2605#endif
d9bce9d9
JM		 2606};
2607#else
2857068e
JM		 2608#if defined(TARGET_PPC64)
2609/* Full system - 64 bits mode */
d9bce9d9
JM		 2610static GenOpFunc1 *gen_op_lswi[] = {
2611 &gen_op_lswi_user,
2612 &gen_op_lswi_le_user,
d9bce9d9
JM		 2613 &gen_op_lswi_64_user,
2614 &gen_op_lswi_le_64_user,
2857068e
JM		 2615 &gen_op_lswi_kernel,
2616 &gen_op_lswi_le_kernel,
d9bce9d9
JM		 2617 &gen_op_lswi_64_kernel,
2618 &gen_op_lswi_le_64_kernel,
2857068e
JM		 2619#if defined(TARGET_PPC64H)
2620 &gen_op_lswi_hypv,
2621 &gen_op_lswi_le_hypv,
2622 &gen_op_lswi_64_hypv,
2623 &gen_op_lswi_le_64_hypv,
2624#endif
d9bce9d9
JM		 2625};
2626static GenOpFunc3 *gen_op_lswx[] = {
2627 &gen_op_lswx_user,
2628 &gen_op_lswx_le_user,
d9bce9d9
JM		 2629 &gen_op_lswx_64_user,
2630 &gen_op_lswx_le_64_user,
2857068e
JM		 2631 &gen_op_lswx_kernel,
2632 &gen_op_lswx_le_kernel,
d9bce9d9
JM		 2633 &gen_op_lswx_64_kernel,
2634 &gen_op_lswx_le_64_kernel,
2857068e
JM		 2635#if defined(TARGET_PPC64H)
2636 &gen_op_lswx_hypv,
2637 &gen_op_lswx_le_hypv,
2638 &gen_op_lswx_64_hypv,
2639 &gen_op_lswx_le_64_hypv,
2640#endif
d9bce9d9
JM		 2641};
2642static GenOpFunc1 *gen_op_stsw[] = {
2643 &gen_op_stsw_user,
2644 &gen_op_stsw_le_user,
d9bce9d9
JM		 2645 &gen_op_stsw_64_user,
2646 &gen_op_stsw_le_64_user,
2857068e
JM		 2647 &gen_op_stsw_kernel,
2648 &gen_op_stsw_le_kernel,
d9bce9d9
JM		 2649 &gen_op_stsw_64_kernel,
2650 &gen_op_stsw_le_64_kernel,
2857068e
JM		 2651#if defined(TARGET_PPC64H)
2652 &gen_op_stsw_hypv,
2653 &gen_op_stsw_le_hypv,
2654 &gen_op_stsw_64_hypv,
2655 &gen_op_stsw_le_64_hypv,
d9bce9d9 2656#endif
111bfab3
FB		 2657};
2658#else
2857068e 2659/* Full system - 32 bits mode */
9a64fbe4
FB		 2660static GenOpFunc1 *gen_op_lswi[] = {
2661 &gen_op_lswi_user,
111bfab3 2662 &gen_op_lswi_le_user,
9a64fbe4 2663 &gen_op_lswi_kernel,
111bfab3 2664 &gen_op_lswi_le_kernel,
9a64fbe4
FB		 2665};
2666static GenOpFunc3 *gen_op_lswx[] = {
2667 &gen_op_lswx_user,
111bfab3 2668 &gen_op_lswx_le_user,
9a64fbe4 2669 &gen_op_lswx_kernel,
111bfab3 2670 &gen_op_lswx_le_kernel,
9a64fbe4
FB		 2671};
2672static GenOpFunc1 *gen_op_stsw[] = {
2673 &gen_op_stsw_user,
111bfab3 2674 &gen_op_stsw_le_user,
9a64fbe4 2675 &gen_op_stsw_kernel,
111bfab3 2676 &gen_op_stsw_le_kernel,
9a64fbe4
FB		 2677};
2678#endif
d9bce9d9 2679#endif
9a64fbe4 2680
79aceca5 2681/* lswi */
3fc6c082 2682/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2683 * rA is in the range of registers to be loaded.
2684 * In an other hand, IBM says this is valid, but rA won't be loaded.
2685 * For now, I'll follow the spec...
2686 */
79aceca5
FB		 2687GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
2688{
2689 int nb = NB(ctx->opcode);
2690 int start = rD(ctx->opcode);
9a64fbe4 2691 int ra = rA(ctx->opcode);
79aceca5
FB		 2692 int nr;
2693
2694 if (nb == 0)
2695 nb = 32;
2696 nr = nb / 4;
76a66253
JM		 2697 if (unlikely(((start + nr) > 32 &&
2698 start <= ra && (start + nr - 32) > ra) ||
2699 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 2700 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2701 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2702 return;
297d8e62 2703 }
8dd4983c 2704 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2705 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 2706 gen_addr_register(ctx);
2707 gen_op_set_T1(nb);
9a64fbe4 2708 op_ldsts(lswi, start);
79aceca5
FB		 2709}
2710
2711/* lswx */
2712GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
2713{
9a64fbe4
FB		 2714 int ra = rA(ctx->opcode);
2715 int rb = rB(ctx->opcode);
2716
76a66253 2717 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2718 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2719 gen_addr_reg_index(ctx);
9a64fbe4 2720 if (ra == 0) {
9a64fbe4 2721 ra = rb;
79aceca5 2722 }
9a64fbe4
FB		 2723 gen_op_load_xer_bc();
2724 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 2725}
2726
2727/* stswi */
2728GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
2729{
4b3686fa
FB		 2730 int nb = NB(ctx->opcode);
2731
76a66253 2732 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2733 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2734 gen_addr_register(ctx);
4b3686fa
FB		 2735 if (nb == 0)
2736 nb = 32;
2737 gen_op_set_T1(nb);
9a64fbe4 2738 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2739}
2740
2741/* stswx */
2742GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
2743{
8dd4983c 2744 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 2745 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 2746 gen_addr_reg_index(ctx);
2747 gen_op_load_xer_bc();
9a64fbe4 2748 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2749}
2750
2751/*** Memory synchronisation ***/
2752/* eieio */
0db1b20e 2753GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 2754{
79aceca5
FB		 2755}
2756
2757/* isync */
0db1b20e 2758GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 2759{
e1833e1f 2760 GEN_STOP(ctx);
79aceca5
FB		 2761}
2762
111bfab3
FB		 2763#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2764#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
9a64fbe4 2765#if defined(CONFIG_USER_ONLY)
2857068e 2766/* User-mode only */
111bfab3
FB		 2767static GenOpFunc *gen_op_lwarx[] = {
2768 &gen_op_lwarx_raw,
2769 &gen_op_lwarx_le_raw,
2857068e 2770#if defined(TARGET_PPC64)
d9bce9d9
JM		 2771 &gen_op_lwarx_64_raw,
2772 &gen_op_lwarx_le_64_raw,
2857068e 2773#endif
111bfab3
FB		 2774};
2775static GenOpFunc *gen_op_stwcx[] = {
2776 &gen_op_stwcx_raw,
2777 &gen_op_stwcx_le_raw,
2857068e 2778#if defined(TARGET_PPC64)
d9bce9d9
JM		 2779 &gen_op_stwcx_64_raw,
2780 &gen_op_stwcx_le_64_raw,
2857068e 2781#endif
111bfab3 2782};
9a64fbe4 2783#else
2857068e
JM		 2784#if defined(TARGET_PPC64)
2785/* Full system - 64 bits mode */
985a19d6
FB		 2786static GenOpFunc *gen_op_lwarx[] = {
2787 &gen_op_lwarx_user,
111bfab3 2788 &gen_op_lwarx_le_user,
d9bce9d9
JM		 2789 &gen_op_lwarx_64_user,
2790 &gen_op_lwarx_le_64_user,
2857068e
JM		 2791 &gen_op_lwarx_kernel,
2792 &gen_op_lwarx_le_kernel,
d9bce9d9
JM		 2793 &gen_op_lwarx_64_kernel,
2794 &gen_op_lwarx_le_64_kernel,
2857068e
JM		 2795#if defined(TARGET_PPC64H)
2796 &gen_op_lwarx_hypv,
2797 &gen_op_lwarx_le_hypv,
2798 &gen_op_lwarx_64_hypv,
2799 &gen_op_lwarx_le_64_hypv,
2800#endif
985a19d6 2801};
9a64fbe4
FB		 2802static GenOpFunc *gen_op_stwcx[] = {
2803 &gen_op_stwcx_user,
111bfab3 2804 &gen_op_stwcx_le_user,
d9bce9d9
JM		 2805 &gen_op_stwcx_64_user,
2806 &gen_op_stwcx_le_64_user,
2857068e
JM		 2807 &gen_op_stwcx_kernel,
2808 &gen_op_stwcx_le_kernel,
d9bce9d9
JM		 2809 &gen_op_stwcx_64_kernel,
2810 &gen_op_stwcx_le_64_kernel,
2857068e
JM		 2811#if defined(TARGET_PPC64H)
2812 &gen_op_stwcx_hypv,
2813 &gen_op_stwcx_le_hypv,
2814 &gen_op_stwcx_64_hypv,
2815 &gen_op_stwcx_le_64_hypv,
9a64fbe4 2816#endif
d9bce9d9
JM		 2817};
2818#else
2857068e 2819/* Full system - 32 bits mode */
d9bce9d9
JM		 2820static GenOpFunc *gen_op_lwarx[] = {
2821 &gen_op_lwarx_user,
2822 &gen_op_lwarx_le_user,
2823 &gen_op_lwarx_kernel,
2824 &gen_op_lwarx_le_kernel,
2825};
2826static GenOpFunc *gen_op_stwcx[] = {
2827 &gen_op_stwcx_user,
2828 &gen_op_stwcx_le_user,
2829 &gen_op_stwcx_kernel,
2830 &gen_op_stwcx_le_kernel,
2831};
2832#endif
2833#endif
9a64fbe4 2834
111bfab3 2835/* lwarx */
76a66253 2836GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 2837{
30032c94
JM		 2838 /* NIP cannot be restored if the memory exception comes from an helper */
2839 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2840 gen_addr_reg_index(ctx);
985a19d6 2841 op_lwarx();
79aceca5 2842 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 2843}
2844
2845/* stwcx. */
c7697e1f 2846GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 2847{
30032c94
JM		 2848 /* NIP cannot be restored if the memory exception comes from an helper */
2849 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2850 gen_addr_reg_index(ctx);
9a64fbe4
FB		 2851 gen_op_load_gpr_T1(rS(ctx->opcode));
2852 op_stwcx();
79aceca5
FB		 2853}
2854
426613db
JM		 2855#if defined(TARGET_PPC64)
2856#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2857#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
2858#if defined(CONFIG_USER_ONLY)
2857068e 2859/* User-mode only */
426613db
JM		 2860static GenOpFunc *gen_op_ldarx[] = {
2861 &gen_op_ldarx_raw,
2862 &gen_op_ldarx_le_raw,
2863 &gen_op_ldarx_64_raw,
2864 &gen_op_ldarx_le_64_raw,
2865};
2866static GenOpFunc *gen_op_stdcx[] = {
2867 &gen_op_stdcx_raw,
2868 &gen_op_stdcx_le_raw,
2869 &gen_op_stdcx_64_raw,
2870 &gen_op_stdcx_le_64_raw,
2871};
2872#else
2857068e 2873/* Full system */
426613db
JM		 2874static GenOpFunc *gen_op_ldarx[] = {
2875 &gen_op_ldarx_user,
2876 &gen_op_ldarx_le_user,
426613db
JM		 2877 &gen_op_ldarx_64_user,
2878 &gen_op_ldarx_le_64_user,
2857068e
JM		 2879 &gen_op_ldarx_kernel,
2880 &gen_op_ldarx_le_kernel,
426613db
JM		 2881 &gen_op_ldarx_64_kernel,
2882 &gen_op_ldarx_le_64_kernel,
2857068e
JM		 2883#if defined(TARGET_PPC64H)
2884 &gen_op_ldarx_hypv,
2885 &gen_op_ldarx_le_hypv,
2886 &gen_op_ldarx_64_hypv,
2887 &gen_op_ldarx_le_64_hypv,
2888#endif
426613db
JM		 2889};
2890static GenOpFunc *gen_op_stdcx[] = {
2891 &gen_op_stdcx_user,
2892 &gen_op_stdcx_le_user,
426613db
JM		 2893 &gen_op_stdcx_64_user,
2894 &gen_op_stdcx_le_64_user,
2857068e
JM		 2895 &gen_op_stdcx_kernel,
2896 &gen_op_stdcx_le_kernel,
426613db
JM		 2897 &gen_op_stdcx_64_kernel,
2898 &gen_op_stdcx_le_64_kernel,
2857068e
JM		 2899#if defined(TARGET_PPC64H)
2900 &gen_op_stdcx_hypv,
2901 &gen_op_stdcx_le_hypv,
2902 &gen_op_stdcx_64_hypv,
2903 &gen_op_stdcx_le_64_hypv,
2904#endif
426613db
JM		 2905};
2906#endif
2907
2908/* ldarx */
a750fc0b 2909GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 2910{
30032c94
JM		 2911 /* NIP cannot be restored if the memory exception comes from an helper */
2912 gen_update_nip(ctx, ctx->nip - 4);
426613db
JM		 2913 gen_addr_reg_index(ctx);
2914 op_ldarx();
2915 gen_op_store_T1_gpr(rD(ctx->opcode));
2916}
2917
2918/* stdcx. */
c7697e1f 2919GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 2920{
30032c94
JM		 2921 /* NIP cannot be restored if the memory exception comes from an helper */
2922 gen_update_nip(ctx, ctx->nip - 4);
426613db
JM		 2923 gen_addr_reg_index(ctx);
2924 gen_op_load_gpr_T1(rS(ctx->opcode));
2925 op_stdcx();
2926}
2927#endif /* defined(TARGET_PPC64) */
2928
79aceca5 2929/* sync */
a902d886 2930GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 2931{
79aceca5
FB		 2932}
2933
0db1b20e
JM		 2934/* wait */
2935GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2936{
2937 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 2938 gen_op_wait();
2939 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 2940}
2941
79aceca5 2942/*** Floating-point load ***/
477023a6
JM		 2943#define GEN_LDF(width, opc, type) \
2944GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2945{ \
76a66253 2946 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2947 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2948 return; \
2949 } \
9d53c753 2950 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2951 op_ldst(l##width); \
76a66253 2952 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5
FB		 2953}
2954
477023a6
JM		 2955#define GEN_LDUF(width, opc, type) \
2956GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2957{ \
76a66253 2958 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2959 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2960 return; \
2961 } \
76a66253 2962 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2963 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2964 return; \
9a64fbe4 2965 } \
9d53c753 2966 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2967 op_ldst(l##width); \
76a66253 2968 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5 2969 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2970}
2971
477023a6
JM		 2972#define GEN_LDUXF(width, opc, type) \
2973GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2974{ \
76a66253 2975 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2976 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2977 return; \
2978 } \
76a66253 2979 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2980 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2981 return; \
9a64fbe4 2982 } \
76a66253 2983 gen_addr_reg_index(ctx); \
9a64fbe4 2984 op_ldst(l##width); \
76a66253 2985 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5 2986 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2987}
2988
477023a6
JM		 2989#define GEN_LDXF(width, opc2, opc3, type) \
2990GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2991{ \
76a66253 2992 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2993 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2994 return; \
2995 } \
76a66253 2996 gen_addr_reg_index(ctx); \
9a64fbe4 2997 op_ldst(l##width); \
76a66253 2998 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5
FB		 2999}
3000
477023a6 3001#define GEN_LDFS(width, op, type) \
9a64fbe4 3002OP_LD_TABLE(width); \
477023a6
JM		 3003GEN_LDF(width, op | 0x20, type); \
3004GEN_LDUF(width, op | 0x21, type); \
3005GEN_LDUXF(width, op | 0x01, type); \
3006GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3007
3008/* lfd lfdu lfdux lfdx */
477023a6 3009GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 3010/* lfs lfsu lfsux lfsx */
477023a6 3011GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3012
3013/*** Floating-point store ***/
477023a6
JM		 3014#define GEN_STF(width, opc, type) \
3015GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3016{ \
76a66253 3017 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3018 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3019 return; \
3020 } \
9d53c753 3021 gen_addr_imm_index(ctx, 0); \
76a66253 3022 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 3023 op_ldst(st##width); \
79aceca5
FB		 3024}
3025
477023a6
JM		 3026#define GEN_STUF(width, opc, type) \
3027GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3028{ \
76a66253 3029 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3030 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3031 return; \
3032 } \
76a66253 3033 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3034 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3035 return; \
9a64fbe4 3036 } \
9d53c753 3037 gen_addr_imm_index(ctx, 0); \
76a66253 3038 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 3039 op_ldst(st##width); \
79aceca5 3040 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 3041}
3042
477023a6
JM		 3043#define GEN_STUXF(width, opc, type) \
3044GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3045{ \
76a66253 3046 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3047 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3048 return; \
3049 } \
76a66253 3050 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3051 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3052 return; \
9a64fbe4 3053 } \
76a66253
JM		 3054 gen_addr_reg_index(ctx); \
3055 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 3056 op_ldst(st##width); \
79aceca5 3057 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 3058}
3059
477023a6
JM		 3060#define GEN_STXF(width, opc2, opc3, type) \
3061GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3062{ \
76a66253 3063 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3064 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3065 return; \
3066 } \
76a66253
JM		 3067 gen_addr_reg_index(ctx); \
3068 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 3069 op_ldst(st##width); \
79aceca5
FB		 3070}
3071
477023a6 3072#define GEN_STFS(width, op, type) \
9a64fbe4 3073OP_ST_TABLE(width); \
477023a6
JM		 3074GEN_STF(width, op | 0x20, type); \
3075GEN_STUF(width, op | 0x21, type); \
3076GEN_STUXF(width, op | 0x01, type); \
3077GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3078
3079/* stfd stfdu stfdux stfdx */
477023a6 3080GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 3081/* stfs stfsu stfsux stfsx */
477023a6 3082GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3083
3084/* Optional: */
3085/* stfiwx */
477023a6
JM		 3086OP_ST_TABLE(fiwx);
3087GEN_STXF(fiwx, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3088
3089/*** Branch ***/
b068d6a7
JM		 3090static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3091 target_ulong dest)
c1942362
FB		 3092{
3093 TranslationBlock *tb;
3094 tb = ctx->tb;
3095 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
3096 if (n == 0)
3097 gen_op_goto_tb0(TBPARAM(tb));
3098 else
3099 gen_op_goto_tb1(TBPARAM(tb));
d9bce9d9
JM		 3100 gen_set_T1(dest);
3101#if defined(TARGET_PPC64)
3102 if (ctx->sf_mode)
3103 gen_op_b_T1_64();
3104 else
3105#endif
3106 gen_op_b_T1();
c1942362 3107 gen_op_set_T0((long)tb + n);
ea4e754f
FB		 3108 if (ctx->singlestep_enabled)
3109 gen_op_debug();
c1942362
FB		 3110 gen_op_exit_tb();
3111 } else {
d9bce9d9
JM		 3112 gen_set_T1(dest);
3113#if defined(TARGET_PPC64)
3114 if (ctx->sf_mode)
3115 gen_op_b_T1_64();
3116 else
3117#endif
3118 gen_op_b_T1();
76a66253 3119 gen_op_reset_T0();
ea4e754f
FB		 3120 if (ctx->singlestep_enabled)
3121 gen_op_debug();
c1942362
FB		 3122 gen_op_exit_tb();
3123 }
c53be334
FB		 3124}
3125
b068d6a7 3126static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3127{
3128#if defined(TARGET_PPC64)
3129 if (ctx->sf_mode != 0 && (nip >> 32))
3130 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3131 else
3132#endif
3133 gen_op_setlr(ctx->nip);
3134}
3135
79aceca5
FB		 3136/* b ba bl bla */
3137GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3138{
76a66253 3139 target_ulong li, target;
38a64f9d
FB		 3140
3141 /* sign extend LI */
76a66253 3142#if defined(TARGET_PPC64)
d9bce9d9
JM		 3143 if (ctx->sf_mode)
3144 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3145 else
76a66253 3146#endif
d9bce9d9 3147 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3148 if (likely(AA(ctx->opcode) == 0))
046d6672 3149 target = ctx->nip + li - 4;
79aceca5 3150 else
9a64fbe4 3151 target = li;
d9bce9d9 3152#if defined(TARGET_PPC64)
e1833e1f
JM		 3153 if (!ctx->sf_mode)
3154 target = (uint32_t)target;
d9bce9d9 3155#endif
e1833e1f
JM		 3156 if (LK(ctx->opcode))
3157 gen_setlr(ctx, ctx->nip);
c1942362 3158 gen_goto_tb(ctx, 0, target);
e1833e1f 3159 ctx->exception = POWERPC_EXCP_BRANCH;
79aceca5
FB		 3160}
3161
e98a6e40
FB		 3162#define BCOND_IM 0
3163#define BCOND_LR 1
3164#define BCOND_CTR 2
3165
b068d6a7 3166static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3167{
76a66253
JM		 3168 target_ulong target = 0;
3169 target_ulong li;
d9bce9d9
JM		 3170 uint32_t bo = BO(ctx->opcode);
3171 uint32_t bi = BI(ctx->opcode);
3172 uint32_t mask;
e98a6e40 3173
e98a6e40 3174 if ((bo & 0x4) == 0)
d9bce9d9 3175 gen_op_dec_ctr();
e98a6e40
FB		 3176 switch(type) {
3177 case BCOND_IM:
76a66253
JM		 3178 li = (target_long)((int16_t)(BD(ctx->opcode)));
3179 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3180 target = ctx->nip + li - 4;
e98a6e40
FB		 3181 } else {
3182 target = li;
3183 }
e1833e1f
JM		 3184#if defined(TARGET_PPC64)
3185 if (!ctx->sf_mode)
3186 target = (uint32_t)target;
3187#endif
e98a6e40
FB		 3188 break;
3189 case BCOND_CTR:
3190 gen_op_movl_T1_ctr();
3191 break;
3192 default:
3193 case BCOND_LR:
3194 gen_op_movl_T1_lr();
3195 break;
3196 }
e1833e1f
JM		 3197 if (LK(ctx->opcode))
3198 gen_setlr(ctx, ctx->nip);
e98a6e40 3199 if (bo & 0x10) {
d9bce9d9
JM		 3200 /* No CR condition */
3201 switch (bo & 0x6) {
3202 case 0:
3203#if defined(TARGET_PPC64)
3204 if (ctx->sf_mode)
3205 gen_op_test_ctr_64();
3206 else
3207#endif
3208 gen_op_test_ctr();
3209 break;
3210 case 2:
3211#if defined(TARGET_PPC64)
3212 if (ctx->sf_mode)
3213 gen_op_test_ctrz_64();
3214 else
3215#endif
3216 gen_op_test_ctrz();
e98a6e40 3217 break;
e98a6e40 3218 default:
d9bce9d9
JM		 3219 case 4:
3220 case 6:
e98a6e40 3221 if (type == BCOND_IM) {
c1942362 3222 gen_goto_tb(ctx, 0, target);
056b05f8 3223 goto out;
e98a6e40 3224 } else {
d9bce9d9
JM		 3225#if defined(TARGET_PPC64)
3226 if (ctx->sf_mode)
3227 gen_op_b_T1_64();
3228 else
3229#endif
3230 gen_op_b_T1();
76a66253 3231 gen_op_reset_T0();
056b05f8 3232 goto no_test;
e98a6e40 3233 }
056b05f8 3234 break;
e98a6e40 3235 }
d9bce9d9
JM		 3236 } else {
3237 mask = 1 << (3 - (bi & 0x03));
3238 gen_op_load_crf_T0(bi >> 2);
3239 if (bo & 0x8) {
3240 switch (bo & 0x6) {
3241 case 0:
3242#if defined(TARGET_PPC64)
3243 if (ctx->sf_mode)
3244 gen_op_test_ctr_true_64(mask);
3245 else
3246#endif
3247 gen_op_test_ctr_true(mask);
3248 break;
3249 case 2:
3250#if defined(TARGET_PPC64)
3251 if (ctx->sf_mode)
3252 gen_op_test_ctrz_true_64(mask);
3253 else
3254#endif
3255 gen_op_test_ctrz_true(mask);
3256 break;
3257 default:
3258 case 4:
3259 case 6:
e98a6e40 3260 gen_op_test_true(mask);
d9bce9d9
JM		 3261 break;
3262 }
3263 } else {
3264 switch (bo & 0x6) {
3265 case 0:
3266#if defined(TARGET_PPC64)
3267 if (ctx->sf_mode)
3268 gen_op_test_ctr_false_64(mask);
3269 else
3270#endif
3271 gen_op_test_ctr_false(mask);
3b46e624 3272 break;
d9bce9d9
JM		 3273 case 2:
3274#if defined(TARGET_PPC64)
3275 if (ctx->sf_mode)
3276 gen_op_test_ctrz_false_64(mask);
3277 else
3278#endif
3279 gen_op_test_ctrz_false(mask);
3280 break;
e98a6e40 3281 default:
d9bce9d9
JM		 3282 case 4:
3283 case 6:
e98a6e40 3284 gen_op_test_false(mask);
d9bce9d9
JM		 3285 break;
3286 }
3287 }
3288 }
e98a6e40 3289 if (type == BCOND_IM) {
c53be334
FB		 3290 int l1 = gen_new_label();
3291 gen_op_jz_T0(l1);
c1942362 3292 gen_goto_tb(ctx, 0, target);
c53be334 3293 gen_set_label(l1);
c1942362 3294 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3295 } else {
d9bce9d9
JM		 3296#if defined(TARGET_PPC64)
3297 if (ctx->sf_mode)
3298 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3299 else
3300#endif
3301 gen_op_btest_T1(ctx->nip);
76a66253 3302 gen_op_reset_T0();
36081602 3303 no_test:
08e46e54
JM		 3304 if (ctx->singlestep_enabled)
3305 gen_op_debug();
3306 gen_op_exit_tb();
3307 }
056b05f8 3308 out:
e1833e1f 3309 ctx->exception = POWERPC_EXCP_BRANCH;
e98a6e40
FB		 3310}
3311
3312GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3313{
e98a6e40
FB		 3314 gen_bcond(ctx, BCOND_IM);
3315}
3316
3317GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3318{
e98a6e40
FB		 3319 gen_bcond(ctx, BCOND_CTR);
3320}
3321
3322GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3323{
e98a6e40
FB		 3324 gen_bcond(ctx, BCOND_LR);
3325}
79aceca5
FB		 3326
3327/*** Condition register logical ***/
3328#define GEN_CRLOGIC(op, opc) \
3329GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3330{ \
fc0d441e
JM		 3331 uint8_t bitmask; \
3332 int sh; \
79aceca5 3333 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
fc0d441e
JM		 3334 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3335 if (sh > 0) \
3336 gen_op_srli_T0(sh); \
3337 else if (sh < 0) \
3338 gen_op_sli_T0(-sh); \
79aceca5 3339 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
fc0d441e
JM		 3340 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3341 if (sh > 0) \
3342 gen_op_srli_T1(sh); \
3343 else if (sh < 0) \
3344 gen_op_sli_T1(-sh); \
79aceca5 3345 gen_op_##op(); \
fc0d441e
JM		 3346 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3347 gen_op_andi_T0(bitmask); \
79aceca5 3348 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
fc0d441e
JM		 3349 gen_op_andi_T1(~bitmask); \
3350 gen_op_or(); \
3351 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 3352}
3353
3354/* crand */
76a66253 3355GEN_CRLOGIC(and, 0x08);
79aceca5 3356/* crandc */
76a66253 3357GEN_CRLOGIC(andc, 0x04);
79aceca5 3358/* creqv */
76a66253 3359GEN_CRLOGIC(eqv, 0x09);
79aceca5 3360/* crnand */
76a66253 3361GEN_CRLOGIC(nand, 0x07);
79aceca5 3362/* crnor */
76a66253 3363GEN_CRLOGIC(nor, 0x01);
79aceca5 3364/* cror */
76a66253 3365GEN_CRLOGIC(or, 0x0E);
79aceca5 3366/* crorc */
76a66253 3367GEN_CRLOGIC(orc, 0x0D);
79aceca5 3368/* crxor */
76a66253 3369GEN_CRLOGIC(xor, 0x06);
79aceca5
FB		 3370/* mcrf */
3371GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3372{
3373 gen_op_load_crf_T0(crfS(ctx->opcode));
3374 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 3375}
3376
3377/*** System linkage ***/
3378/* rfi (supervisor only) */
76a66253 3379GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3380{
9a64fbe4 3381#if defined(CONFIG_USER_ONLY)
e1833e1f 3382 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3383#else
3384 /* Restore CPU state */
76a66253 3385 if (unlikely(!ctx->supervisor)) {
e1833e1f 3386 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3387 return;
9a64fbe4 3388 }
a42bd6cc 3389 gen_op_rfi();
e1833e1f 3390 GEN_SYNC(ctx);
9a64fbe4 3391#endif
79aceca5
FB		 3392}
3393
426613db 3394#if defined(TARGET_PPC64)
a750fc0b 3395GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3396{
3397#if defined(CONFIG_USER_ONLY)
e1833e1f 3398 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3399#else
3400 /* Restore CPU state */
3401 if (unlikely(!ctx->supervisor)) {
e1833e1f 3402 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3403 return;
3404 }
a42bd6cc 3405 gen_op_rfid();
e1833e1f 3406 GEN_SYNC(ctx);
426613db
JM		 3407#endif
3408}
3409#endif
3410
be147d08
JM		 3411#if defined(TARGET_PPC64H)
3412GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64B)
3413{
3414#if defined(CONFIG_USER_ONLY)
3415 GEN_EXCP_PRIVOPC(ctx);
3416#else
3417 /* Restore CPU state */
3418 if (unlikely(ctx->supervisor <= 1)) {
3419 GEN_EXCP_PRIVOPC(ctx);
3420 return;
3421 }
3422 gen_op_hrfid();
3423 GEN_SYNC(ctx);
3424#endif
3425}
3426#endif
3427
79aceca5 3428/* sc */
417bf010
JM		 3429#if defined(CONFIG_USER_ONLY)
3430#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3431#else
3432#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3433#endif
e1833e1f 3434GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3435{
e1833e1f
JM		 3436 uint32_t lev;
3437
3438 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3439 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3440}
3441
3442/*** Trap ***/
3443/* tw */
76a66253 3444GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3445{
9a64fbe4
FB		 3446 gen_op_load_gpr_T0(rA(ctx->opcode));
3447 gen_op_load_gpr_T1(rB(ctx->opcode));
a0ae05aa 3448 /* Update the nip since this might generate a trap exception */
d9bce9d9 3449 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3450 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3451}
3452
3453/* twi */
3454GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3455{
9a64fbe4 3456 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 3457 gen_set_T1(SIMM(ctx->opcode));
3458 /* Update the nip since this might generate a trap exception */
3459 gen_update_nip(ctx, ctx->nip);
76a66253 3460 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3461}
3462
d9bce9d9
JM		 3463#if defined(TARGET_PPC64)
3464/* td */
3465GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3466{
3467 gen_op_load_gpr_T0(rA(ctx->opcode));
3468 gen_op_load_gpr_T1(rB(ctx->opcode));
3469 /* Update the nip since this might generate a trap exception */
3470 gen_update_nip(ctx, ctx->nip);
3471 gen_op_td(TO(ctx->opcode));
3472}
3473
3474/* tdi */
3475GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3476{
3477 gen_op_load_gpr_T0(rA(ctx->opcode));
3478 gen_set_T1(SIMM(ctx->opcode));
3479 /* Update the nip since this might generate a trap exception */
3480 gen_update_nip(ctx, ctx->nip);
3481 gen_op_td(TO(ctx->opcode));
3482}
3483#endif
3484
79aceca5 3485/*** Processor control ***/
79aceca5
FB		 3486/* mcrxr */
3487GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3488{
3489 gen_op_load_xer_cr();
3490 gen_op_store_T0_crf(crfD(ctx->opcode));
e864cabd
JM		 3491 gen_op_clear_xer_ov();
3492 gen_op_clear_xer_ca();
79aceca5
FB		 3493}
3494
3495/* mfcr */
76a66253 3496GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3497{
76a66253 3498 uint32_t crm, crn;
3b46e624 3499
76a66253
JM		 3500 if (likely(ctx->opcode & 0x00100000)) {
3501 crm = CRM(ctx->opcode);
3502 if (likely((crm ^ (crm - 1)) == 0)) {
3503 crn = ffs(crm);
3504 gen_op_load_cro(7 - crn);
3505 }
d9bce9d9
JM		 3506 } else {
3507 gen_op_load_cr();
3508 }
79aceca5 3509 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 3510}
3511
3512/* mfmsr */
3513GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3514{
9a64fbe4 3515#if defined(CONFIG_USER_ONLY)
e1833e1f 3516 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3517#else
76a66253 3518 if (unlikely(!ctx->supervisor)) {
e1833e1f 3519 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3520 return;
9a64fbe4 3521 }
79aceca5
FB		 3522 gen_op_load_msr();
3523 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 3524#endif
79aceca5
FB		 3525}
3526
a11b8151 3527#if 1
6f2d8978 3528#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3529#else
3530static void spr_noaccess (void *opaque, int sprn)
3531{
3532 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3533 printf("ERROR: try to access SPR %d !\n", sprn);
3534}
3535#define SPR_NOACCESS (&spr_noaccess)
3536#endif
3537
79aceca5 3538/* mfspr */
b068d6a7 3539static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3540{
3fc6c082 3541 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3542 uint32_t sprn = SPR(ctx->opcode);
3543
3fc6c082 3544#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3545#if defined(TARGET_PPC64H)
3546 if (ctx->supervisor == 2)
3547 read_cb = ctx->spr_cb[sprn].hea_read;
3548 else
3549#endif
3fc6c082
FB		 3550 if (ctx->supervisor)
3551 read_cb = ctx->spr_cb[sprn].oea_read;
3552 else
9a64fbe4 3553#endif
3fc6c082 3554 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3555 if (likely(read_cb != NULL)) {
3556 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082
FB		 3557 (*read_cb)(ctx, sprn);
3558 gen_op_store_T0_gpr(rD(ctx->opcode));
3559 } else {
3560 /* Privilege exception */
9fceefa7
JM		 3561 /* This is a hack to avoid warnings when running Linux:
3562 * this OS breaks the PowerPC virtualisation model,
3563 * allowing userland application to read the PVR
3564 */
3565 if (sprn != SPR_PVR) {
3566 if (loglevel != 0) {
077fc206
JM		 3567 fprintf(logfile, "Trying to read privileged spr %d %03x at"
3568 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3569 }
077fc206
JM		 3570 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3571 sprn, sprn, ctx->nip);
f24e5695 3572 }
e1833e1f 3573 GEN_EXCP_PRIVREG(ctx);
79aceca5 3574 }
3fc6c082
FB		 3575 } else {
3576 /* Not defined */
4a057712 3577 if (loglevel != 0) {
077fc206
JM		 3578 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3579 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3580 }
077fc206
JM		 3581 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3582 sprn, sprn, ctx->nip);
e1833e1f
JM		 3583 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3584 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3585 }
79aceca5
FB		 3586}
3587
3fc6c082 3588GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3589{
3fc6c082 3590 gen_op_mfspr(ctx);
76a66253 3591}
3fc6c082
FB		 3592
3593/* mftb */
a750fc0b 3594GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3595{
3596 gen_op_mfspr(ctx);
79aceca5
FB		 3597}
3598
3599/* mtcrf */
8dd4983c 3600GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3601{
76a66253 3602 uint32_t crm, crn;
3b46e624 3603
79aceca5 3604 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 3605 crm = CRM(ctx->opcode);
3606 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3607 crn = ffs(crm);
3608 gen_op_srli_T0(crn * 4);
3609 gen_op_andi_T0(0xF);
3610 gen_op_store_cro(7 - crn);
3611 } else {
3612 gen_op_store_cr(crm);
3613 }
79aceca5
FB		 3614}
3615
3616/* mtmsr */
426613db 3617#if defined(TARGET_PPC64)
be147d08 3618GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3619{
3620#if defined(CONFIG_USER_ONLY)
e1833e1f 3621 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3622#else
3623 if (unlikely(!ctx->supervisor)) {
e1833e1f 3624 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3625 return;
3626 }
426613db 3627 gen_op_load_gpr_T0(rS(ctx->opcode));
be147d08
JM		 3628 if (ctx->opcode & 0x00010000) {
3629 /* Special form that does not need any synchronisation */
3630 gen_op_update_riee();
3631 } else {
056b05f8
JM		 3632 /* XXX: we need to update nip before the store
3633 * if we enter power saving mode, we will exit the loop
3634 * directly from ppc_store_msr
3635 */
be147d08
JM		 3636 gen_update_nip(ctx, ctx->nip);
3637 gen_op_store_msr();
3638 /* Must stop the translation as machine state (may have) changed */
3639 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3640 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3641 }
426613db
JM		 3642#endif
3643}
3644#endif
3645
79aceca5
FB		 3646GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3647{
9a64fbe4 3648#if defined(CONFIG_USER_ONLY)
e1833e1f 3649 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3650#else
76a66253 3651 if (unlikely(!ctx->supervisor)) {
e1833e1f 3652 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3653 return;
9a64fbe4 3654 }
79aceca5 3655 gen_op_load_gpr_T0(rS(ctx->opcode));
be147d08
JM		 3656 if (ctx->opcode & 0x00010000) {
3657 /* Special form that does not need any synchronisation */
3658 gen_op_update_riee();
3659 } else {
056b05f8
JM		 3660 /* XXX: we need to update nip before the store
3661 * if we enter power saving mode, we will exit the loop
3662 * directly from ppc_store_msr
3663 */
be147d08 3664 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3665#if defined(TARGET_PPC64)
be147d08
JM		 3666 if (!ctx->sf_mode)
3667 gen_op_store_msr_32();
3668 else
d9bce9d9 3669#endif
be147d08
JM		 3670 gen_op_store_msr();
3671 /* Must stop the translation as machine state (may have) changed */
3672 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3673 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3674 }
9a64fbe4 3675#endif
79aceca5
FB		 3676}
3677
3678/* mtspr */
3679GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3680{
3fc6c082 3681 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3682 uint32_t sprn = SPR(ctx->opcode);
3683
3fc6c082 3684#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3685#if defined(TARGET_PPC64H)
3686 if (ctx->supervisor == 2)
3687 write_cb = ctx->spr_cb[sprn].hea_write;
3688 else
3689#endif
3fc6c082
FB		 3690 if (ctx->supervisor)
3691 write_cb = ctx->spr_cb[sprn].oea_write;
3692 else
9a64fbe4 3693#endif
3fc6c082 3694 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3695 if (likely(write_cb != NULL)) {
3696 if (likely(write_cb != SPR_NOACCESS)) {
3fc6c082
FB		 3697 gen_op_load_gpr_T0(rS(ctx->opcode));
3698 (*write_cb)(ctx, sprn);
3699 } else {
3700 /* Privilege exception */
4a057712 3701 if (loglevel != 0) {
077fc206
JM		 3702 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3703 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3704 }
077fc206
JM		 3705 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3706 sprn, sprn, ctx->nip);
e1833e1f 3707 GEN_EXCP_PRIVREG(ctx);
76a66253 3708 }
3fc6c082
FB		 3709 } else {
3710 /* Not defined */
4a057712 3711 if (loglevel != 0) {
077fc206
JM		 3712 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3713 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3714 }
077fc206
JM		 3715 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3716 sprn, sprn, ctx->nip);
e1833e1f
JM		 3717 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3718 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3719 }
79aceca5
FB		 3720}
3721
3722/*** Cache management ***/
79aceca5 3723/* dcbf */
0db1b20e 3724GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3725{
dac454af 3726 /* XXX: specification says this is treated as a load by the MMU */
76a66253 3727 gen_addr_reg_index(ctx);
a541f297 3728 op_ldst(lbz);
79aceca5
FB		 3729}
3730
3731/* dcbi (Supervisor only) */
9a64fbe4 3732GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3733{
a541f297 3734#if defined(CONFIG_USER_ONLY)
e1833e1f 3735 GEN_EXCP_PRIVOPC(ctx);
a541f297 3736#else
76a66253 3737 if (unlikely(!ctx->supervisor)) {
e1833e1f 3738 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3739 return;
9a64fbe4 3740 }
76a66253
JM		 3741 gen_addr_reg_index(ctx);
3742 /* XXX: specification says this should be treated as a store by the MMU */
dac454af 3743 op_ldst(lbz);
a541f297
FB		 3744 op_ldst(stb);
3745#endif
79aceca5
FB		 3746}
3747
3748/* dcdst */
9a64fbe4 3749GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3750{
76a66253
JM		 3751 /* XXX: specification say this is treated as a load by the MMU */
3752 gen_addr_reg_index(ctx);
a541f297 3753 op_ldst(lbz);
79aceca5
FB		 3754}
3755
3756/* dcbt */
0db1b20e 3757GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3758{
0db1b20e 3759 /* interpreted as no-op */
76a66253
JM		 3760 /* XXX: specification say this is treated as a load by the MMU
3761 * but does not generate any exception
3762 */
79aceca5
FB		 3763}
3764
3765/* dcbtst */
0db1b20e 3766GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3767{
0db1b20e 3768 /* interpreted as no-op */
76a66253
JM		 3769 /* XXX: specification say this is treated as a load by the MMU
3770 * but does not generate any exception
3771 */
79aceca5
FB		 3772}
3773
3774/* dcbz */
d63001d1 3775#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
d9bce9d9 3776#if defined(CONFIG_USER_ONLY)
2857068e 3777/* User-mode only */
d63001d1
JM		 3778static GenOpFunc *gen_op_dcbz[4][4] = {
3779 {
3780 &gen_op_dcbz_l32_raw,
3781 &gen_op_dcbz_l32_raw,
2857068e 3782#if defined(TARGET_PPC64)
d63001d1
JM		 3783 &gen_op_dcbz_l32_64_raw,
3784 &gen_op_dcbz_l32_64_raw,
2857068e 3785#endif
d63001d1
JM		 3786 },
3787 {
3788 &gen_op_dcbz_l64_raw,
3789 &gen_op_dcbz_l64_raw,
3790#if defined(TARGET_PPC64)
3791 &gen_op_dcbz_l64_64_raw,
3792 &gen_op_dcbz_l64_64_raw,
3793#endif
3794 },
3795 {
3796 &gen_op_dcbz_l128_raw,
3797 &gen_op_dcbz_l128_raw,
3798#if defined(TARGET_PPC64)
3799 &gen_op_dcbz_l128_64_raw,
3800 &gen_op_dcbz_l128_64_raw,
3801#endif
3802 },
3803 {
3804 &gen_op_dcbz_raw,
3805 &gen_op_dcbz_raw,
3806#if defined(TARGET_PPC64)
3807 &gen_op_dcbz_64_raw,
3808 &gen_op_dcbz_64_raw,
3809#endif
3810 },
d9bce9d9
JM		 3811};
3812#else
2857068e
JM		 3813#if defined(TARGET_PPC64)
3814/* Full system - 64 bits mode */
d63001d1
JM		 3815static GenOpFunc *gen_op_dcbz[4][12] = {
3816 {
3817 &gen_op_dcbz_l32_user,
3818 &gen_op_dcbz_l32_user,
3819 &gen_op_dcbz_l32_64_user,
3820 &gen_op_dcbz_l32_64_user,
3821 &gen_op_dcbz_l32_kernel,
3822 &gen_op_dcbz_l32_kernel,
3823 &gen_op_dcbz_l32_64_kernel,
3824 &gen_op_dcbz_l32_64_kernel,
3825#if defined(TARGET_PPC64H)
3826 &gen_op_dcbz_l32_hypv,
3827 &gen_op_dcbz_l32_hypv,
3828 &gen_op_dcbz_l32_64_hypv,
3829 &gen_op_dcbz_l32_64_hypv,
3830#endif
3831 },
3832 {
3833 &gen_op_dcbz_l64_user,
3834 &gen_op_dcbz_l64_user,
3835 &gen_op_dcbz_l64_64_user,
3836 &gen_op_dcbz_l64_64_user,
3837 &gen_op_dcbz_l64_kernel,
3838 &gen_op_dcbz_l64_kernel,
3839 &gen_op_dcbz_l64_64_kernel,
3840 &gen_op_dcbz_l64_64_kernel,
2857068e 3841#if defined(TARGET_PPC64H)
d63001d1
JM		 3842 &gen_op_dcbz_l64_hypv,
3843 &gen_op_dcbz_l64_hypv,
3844 &gen_op_dcbz_l64_64_hypv,
3845 &gen_op_dcbz_l64_64_hypv,
3846#endif
3847 },
3848 {
3849 &gen_op_dcbz_l128_user,
3850 &gen_op_dcbz_l128_user,
3851 &gen_op_dcbz_l128_64_user,
3852 &gen_op_dcbz_l128_64_user,
3853 &gen_op_dcbz_l128_kernel,
3854 &gen_op_dcbz_l128_kernel,
3855 &gen_op_dcbz_l128_64_kernel,
3856 &gen_op_dcbz_l128_64_kernel,
3857#if defined(TARGET_PPC64H)
3858 &gen_op_dcbz_l128_hypv,
3859 &gen_op_dcbz_l128_hypv,
3860 &gen_op_dcbz_l128_64_hypv,
3861 &gen_op_dcbz_l128_64_hypv,
3862#endif
3863 },
3864 {
3865 &gen_op_dcbz_user,
3866 &gen_op_dcbz_user,
3867 &gen_op_dcbz_64_user,
3868 &gen_op_dcbz_64_user,
3869 &gen_op_dcbz_kernel,
3870 &gen_op_dcbz_kernel,
3871 &gen_op_dcbz_64_kernel,
3872 &gen_op_dcbz_64_kernel,
3873#if defined(TARGET_PPC64H)
3874 &gen_op_dcbz_hypv,
3875 &gen_op_dcbz_hypv,
3876 &gen_op_dcbz_64_hypv,
3877 &gen_op_dcbz_64_hypv,
d9bce9d9 3878#endif
d63001d1 3879 },
76a66253 3880};
9a64fbe4 3881#else
2857068e 3882/* Full system - 32 bits mode */
d63001d1
JM		 3883static GenOpFunc *gen_op_dcbz[4][4] = {
3884 {
3885 &gen_op_dcbz_l32_user,
3886 &gen_op_dcbz_l32_user,
3887 &gen_op_dcbz_l32_kernel,
3888 &gen_op_dcbz_l32_kernel,
3889 },
3890 {
3891 &gen_op_dcbz_l64_user,
3892 &gen_op_dcbz_l64_user,
3893 &gen_op_dcbz_l64_kernel,
3894 &gen_op_dcbz_l64_kernel,
3895 },
3896 {
3897 &gen_op_dcbz_l128_user,
3898 &gen_op_dcbz_l128_user,
3899 &gen_op_dcbz_l128_kernel,
3900 &gen_op_dcbz_l128_kernel,
3901 },
3902 {
3903 &gen_op_dcbz_user,
3904 &gen_op_dcbz_user,
3905 &gen_op_dcbz_kernel,
3906 &gen_op_dcbz_kernel,
3907 },
9a64fbe4
FB		 3908};
3909#endif
d9bce9d9 3910#endif
9a64fbe4 3911
b068d6a7
JM		 3912static always_inline void handler_dcbz (DisasContext *ctx,
3913 int dcache_line_size)
d63001d1
JM		 3914{
3915 int n;
3916
3917 switch (dcache_line_size) {
3918 case 32:
3919 n = 0;
3920 break;
3921 case 64:
3922 n = 1;
3923 break;
3924 case 128:
3925 n = 2;
3926 break;
3927 default:
3928 n = 3;
3929 break;
3930 }
3931 op_dcbz(n);
3932}
3933
3934GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 3935{
76a66253 3936 gen_addr_reg_index(ctx);
d63001d1
JM		 3937 handler_dcbz(ctx, ctx->dcache_line_size);
3938 gen_op_check_reservation();
3939}
3940
c7697e1f 3941GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1
JM		 3942{
3943 gen_addr_reg_index(ctx);
3944 if (ctx->opcode & 0x00200000)
3945 handler_dcbz(ctx, ctx->dcache_line_size);
3946 else
3947 handler_dcbz(ctx, -1);
4b3686fa 3948 gen_op_check_reservation();
79aceca5
FB		 3949}
3950
3951/* icbi */
36f69651 3952#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
36f69651 3953#if defined(CONFIG_USER_ONLY)
2857068e 3954/* User-mode only */
36f69651
JM		 3955static GenOpFunc *gen_op_icbi[] = {
3956 &gen_op_icbi_raw,
3957 &gen_op_icbi_raw,
2857068e 3958#if defined(TARGET_PPC64)
36f69651
JM		 3959 &gen_op_icbi_64_raw,
3960 &gen_op_icbi_64_raw,
2857068e 3961#endif
36f69651
JM		 3962};
3963#else
2857068e
JM		 3964/* Full system - 64 bits mode */
3965#if defined(TARGET_PPC64)
36f69651
JM		 3966static GenOpFunc *gen_op_icbi[] = {
3967 &gen_op_icbi_user,
3968 &gen_op_icbi_user,
36f69651
JM		 3969 &gen_op_icbi_64_user,
3970 &gen_op_icbi_64_user,
2857068e
JM		 3971 &gen_op_icbi_kernel,
3972 &gen_op_icbi_kernel,
36f69651
JM		 3973 &gen_op_icbi_64_kernel,
3974 &gen_op_icbi_64_kernel,
2857068e
JM		 3975#if defined(TARGET_PPC64H)
3976 &gen_op_icbi_hypv,
3977 &gen_op_icbi_hypv,
3978 &gen_op_icbi_64_hypv,
3979 &gen_op_icbi_64_hypv,
36f69651 3980#endif
36f69651
JM		 3981};
3982#else
2857068e 3983/* Full system - 32 bits mode */
36f69651
JM		 3984static GenOpFunc *gen_op_icbi[] = {
3985 &gen_op_icbi_user,
3986 &gen_op_icbi_user,
3987 &gen_op_icbi_kernel,
3988 &gen_op_icbi_kernel,
3989};
3990#endif
3991#endif
e1833e1f 3992
1b413d55 3993GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 3994{
30032c94
JM		 3995 /* NIP cannot be restored if the memory exception comes from an helper */
3996 gen_update_nip(ctx, ctx->nip - 4);
76a66253 3997 gen_addr_reg_index(ctx);
36f69651 3998 op_icbi();
79aceca5
FB		 3999}
4000
4001/* Optional: */
4002/* dcba */
a750fc0b 4003GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4004{
0db1b20e
JM		 4005 /* interpreted as no-op */
4006 /* XXX: specification say this is treated as a store by the MMU
4007 * but does not generate any exception
4008 */
79aceca5
FB		 4009}
4010
4011/*** Segment register manipulation ***/
4012/* Supervisor only: */
4013/* mfsr */
4014GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4015{
9a64fbe4 4016#if defined(CONFIG_USER_ONLY)
e1833e1f 4017 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4018#else
76a66253 4019 if (unlikely(!ctx->supervisor)) {
e1833e1f 4020 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4021 return;
9a64fbe4 4022 }
76a66253
JM		 4023 gen_op_set_T1(SR(ctx->opcode));
4024 gen_op_load_sr();
9a64fbe4
FB		 4025 gen_op_store_T0_gpr(rD(ctx->opcode));
4026#endif
79aceca5
FB		 4027}
4028
4029/* mfsrin */
9a64fbe4 4030GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4031{
9a64fbe4 4032#if defined(CONFIG_USER_ONLY)
e1833e1f 4033 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4034#else
76a66253 4035 if (unlikely(!ctx->supervisor)) {
e1833e1f 4036 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4037 return;
9a64fbe4
FB		 4038 }
4039 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 4040 gen_op_srli_T1(28);
4041 gen_op_load_sr();
9a64fbe4
FB		 4042 gen_op_store_T0_gpr(rD(ctx->opcode));
4043#endif
79aceca5
FB		 4044}
4045
4046/* mtsr */
e63c59cb 4047GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4048{
9a64fbe4 4049#if defined(CONFIG_USER_ONLY)
e1833e1f 4050 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4051#else
76a66253 4052 if (unlikely(!ctx->supervisor)) {
e1833e1f 4053 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4054 return;
9a64fbe4
FB		 4055 }
4056 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 4057 gen_op_set_T1(SR(ctx->opcode));
4058 gen_op_store_sr();
9a64fbe4 4059#endif
79aceca5
FB		 4060}
4061
4062/* mtsrin */
9a64fbe4 4063GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4064{
9a64fbe4 4065#if defined(CONFIG_USER_ONLY)
e1833e1f 4066 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4067#else
76a66253 4068 if (unlikely(!ctx->supervisor)) {
e1833e1f 4069 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4070 return;
9a64fbe4
FB		 4071 }
4072 gen_op_load_gpr_T0(rS(ctx->opcode));
4073 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 4074 gen_op_srli_T1(28);
4075 gen_op_store_sr();
9a64fbe4 4076#endif
79aceca5
FB		 4077}
4078
12de9a39
JM		 4079#if defined(TARGET_PPC64)
4080/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4081/* mfsr */
c7697e1f 4082GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4083{
4084#if defined(CONFIG_USER_ONLY)
4085 GEN_EXCP_PRIVREG(ctx);
4086#else
4087 if (unlikely(!ctx->supervisor)) {
4088 GEN_EXCP_PRIVREG(ctx);
4089 return;
4090 }
4091 gen_op_set_T1(SR(ctx->opcode));
4092 gen_op_load_slb();
4093 gen_op_store_T0_gpr(rD(ctx->opcode));
4094#endif
4095}
4096
4097/* mfsrin */
c7697e1f
JM		 4098GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4099 PPC_SEGMENT_64B)
12de9a39
JM		 4100{
4101#if defined(CONFIG_USER_ONLY)
4102 GEN_EXCP_PRIVREG(ctx);
4103#else
4104 if (unlikely(!ctx->supervisor)) {
4105 GEN_EXCP_PRIVREG(ctx);
4106 return;
4107 }
4108 gen_op_load_gpr_T1(rB(ctx->opcode));
4109 gen_op_srli_T1(28);
4110 gen_op_load_slb();
4111 gen_op_store_T0_gpr(rD(ctx->opcode));
4112#endif
4113}
4114
4115/* mtsr */
c7697e1f 4116GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4117{
4118#if defined(CONFIG_USER_ONLY)
4119 GEN_EXCP_PRIVREG(ctx);
4120#else
4121 if (unlikely(!ctx->supervisor)) {
4122 GEN_EXCP_PRIVREG(ctx);
4123 return;
4124 }
4125 gen_op_load_gpr_T0(rS(ctx->opcode));
4126 gen_op_set_T1(SR(ctx->opcode));
4127 gen_op_store_slb();
4128#endif
4129}
4130
4131/* mtsrin */
c7697e1f
JM		 4132GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4133 PPC_SEGMENT_64B)
12de9a39
JM		 4134{
4135#if defined(CONFIG_USER_ONLY)
4136 GEN_EXCP_PRIVREG(ctx);
4137#else
4138 if (unlikely(!ctx->supervisor)) {
4139 GEN_EXCP_PRIVREG(ctx);
4140 return;
4141 }
4142 gen_op_load_gpr_T0(rS(ctx->opcode));
4143 gen_op_load_gpr_T1(rB(ctx->opcode));
4144 gen_op_srli_T1(28);
4145 gen_op_store_slb();
4146#endif
4147}
4148#endif /* defined(TARGET_PPC64) */
4149
79aceca5
FB		 4150/*** Lookaside buffer management ***/
4151/* Optional & supervisor only: */
4152/* tlbia */
3fc6c082 4153GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4154{
9a64fbe4 4155#if defined(CONFIG_USER_ONLY)
e1833e1f 4156 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4157#else
76a66253 4158 if (unlikely(!ctx->supervisor)) {
4a057712 4159 if (loglevel != 0)
9fddaa0c 4160 fprintf(logfile, "%s: ! supervisor\n", __func__);
e1833e1f 4161 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4162 return;
9a64fbe4
FB		 4163 }
4164 gen_op_tlbia();
4165#endif
79aceca5
FB		 4166}
4167
4168/* tlbie */
76a66253 4169GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4170{
9a64fbe4 4171#if defined(CONFIG_USER_ONLY)
e1833e1f 4172 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4173#else
76a66253 4174 if (unlikely(!ctx->supervisor)) {
e1833e1f 4175 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4176 return;
9a64fbe4
FB		 4177 }
4178 gen_op_load_gpr_T0(rB(ctx->opcode));
d9bce9d9
JM		 4179#if defined(TARGET_PPC64)
4180 if (ctx->sf_mode)
4181 gen_op_tlbie_64();
4182 else
4183#endif
4184 gen_op_tlbie();
9a64fbe4 4185#endif
79aceca5
FB		 4186}
4187
4188/* tlbsync */
76a66253 4189GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4190{
9a64fbe4 4191#if defined(CONFIG_USER_ONLY)
e1833e1f 4192 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4193#else
76a66253 4194 if (unlikely(!ctx->supervisor)) {
e1833e1f 4195 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4196 return;
9a64fbe4
FB		 4197 }
4198 /* This has no effect: it should ensure that all previous
4199 * tlbie have completed
4200 */
e1833e1f 4201 GEN_STOP(ctx);
9a64fbe4 4202#endif
79aceca5
FB		 4203}
4204
426613db
JM		 4205#if defined(TARGET_PPC64)
4206/* slbia */
4207GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4208{
4209#if defined(CONFIG_USER_ONLY)
e1833e1f 4210 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4211#else
4212 if (unlikely(!ctx->supervisor)) {
4a057712 4213 if (loglevel != 0)
426613db 4214 fprintf(logfile, "%s: ! supervisor\n", __func__);
e1833e1f 4215 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4216 return;
4217 }
4218 gen_op_slbia();
426613db
JM		 4219#endif
4220}
4221
4222/* slbie */
4223GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4224{
4225#if defined(CONFIG_USER_ONLY)
e1833e1f 4226 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4227#else
4228 if (unlikely(!ctx->supervisor)) {
e1833e1f 4229 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4230 return;
4231 }
4232 gen_op_load_gpr_T0(rB(ctx->opcode));
4233 gen_op_slbie();
426613db
JM		 4234#endif
4235}
4236#endif
4237
79aceca5
FB		 4238/*** External control ***/
4239/* Optional: */
9a64fbe4
FB		 4240#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4241#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
111bfab3 4242#if defined(CONFIG_USER_ONLY)
2857068e 4243/* User-mode only */
111bfab3
FB		 4244static GenOpFunc *gen_op_eciwx[] = {
4245 &gen_op_eciwx_raw,
4246 &gen_op_eciwx_le_raw,
2857068e 4247#if defined(TARGET_PPC64)
d9bce9d9
JM		 4248 &gen_op_eciwx_64_raw,
4249 &gen_op_eciwx_le_64_raw,
2857068e 4250#endif
111bfab3
FB		 4251};
4252static GenOpFunc *gen_op_ecowx[] = {
4253 &gen_op_ecowx_raw,
4254 &gen_op_ecowx_le_raw,
2857068e 4255#if defined(TARGET_PPC64)
d9bce9d9
JM		 4256 &gen_op_ecowx_64_raw,
4257 &gen_op_ecowx_le_64_raw,
2857068e 4258#endif
111bfab3
FB		 4259};
4260#else
2857068e
JM		 4261#if defined(TARGET_PPC64)
4262/* Full system - 64 bits mode */
9a64fbe4
FB		 4263static GenOpFunc *gen_op_eciwx[] = {
4264 &gen_op_eciwx_user,
111bfab3 4265 &gen_op_eciwx_le_user,
d9bce9d9
JM		 4266 &gen_op_eciwx_64_user,
4267 &gen_op_eciwx_le_64_user,
2857068e
JM		 4268 &gen_op_eciwx_kernel,
4269 &gen_op_eciwx_le_kernel,
d9bce9d9
JM		 4270 &gen_op_eciwx_64_kernel,
4271 &gen_op_eciwx_le_64_kernel,
2857068e
JM		 4272#if defined(TARGET_PPC64H)
4273 &gen_op_eciwx_hypv,
4274 &gen_op_eciwx_le_hypv,
4275 &gen_op_eciwx_64_hypv,
4276 &gen_op_eciwx_le_64_hypv,
4277#endif
9a64fbe4
FB		 4278};
4279static GenOpFunc *gen_op_ecowx[] = {
4280 &gen_op_ecowx_user,
111bfab3 4281 &gen_op_ecowx_le_user,
d9bce9d9
JM		 4282 &gen_op_ecowx_64_user,
4283 &gen_op_ecowx_le_64_user,
2857068e
JM		 4284 &gen_op_ecowx_kernel,
4285 &gen_op_ecowx_le_kernel,
d9bce9d9
JM		 4286 &gen_op_ecowx_64_kernel,
4287 &gen_op_ecowx_le_64_kernel,
2857068e
JM		 4288#if defined(TARGET_PPC64H)
4289 &gen_op_ecowx_hypv,
4290 &gen_op_ecowx_le_hypv,
4291 &gen_op_ecowx_64_hypv,
4292 &gen_op_ecowx_le_64_hypv,
9a64fbe4 4293#endif
d9bce9d9
JM		 4294};
4295#else
2857068e 4296/* Full system - 32 bits mode */
d9bce9d9
JM		 4297static GenOpFunc *gen_op_eciwx[] = {
4298 &gen_op_eciwx_user,
4299 &gen_op_eciwx_le_user,
4300 &gen_op_eciwx_kernel,
4301 &gen_op_eciwx_le_kernel,
4302};
4303static GenOpFunc *gen_op_ecowx[] = {
4304 &gen_op_ecowx_user,
4305 &gen_op_ecowx_le_user,
4306 &gen_op_ecowx_kernel,
4307 &gen_op_ecowx_le_kernel,
4308};
4309#endif
4310#endif
9a64fbe4 4311
111bfab3 4312/* eciwx */
79aceca5
FB		 4313GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4314{
9a64fbe4 4315 /* Should check EAR[E] & alignment ! */
76a66253
JM		 4316 gen_addr_reg_index(ctx);
4317 op_eciwx();
4318 gen_op_store_T0_gpr(rD(ctx->opcode));
4319}
4320
4321/* ecowx */
4322GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4323{
4324 /* Should check EAR[E] & alignment ! */
4325 gen_addr_reg_index(ctx);
4326 gen_op_load_gpr_T1(rS(ctx->opcode));
4327 op_ecowx();
4328}
4329
4330/* PowerPC 601 specific instructions */
4331/* abs - abs. */
4332GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4333{
4334 gen_op_load_gpr_T0(rA(ctx->opcode));
4335 gen_op_POWER_abs();
4336 gen_op_store_T0_gpr(rD(ctx->opcode));
4337 if (unlikely(Rc(ctx->opcode) != 0))
4338 gen_set_Rc0(ctx);
4339}
4340
4341/* abso - abso. */
4342GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4343{
4344 gen_op_load_gpr_T0(rA(ctx->opcode));
4345 gen_op_POWER_abso();
4346 gen_op_store_T0_gpr(rD(ctx->opcode));
4347 if (unlikely(Rc(ctx->opcode) != 0))
4348 gen_set_Rc0(ctx);
4349}
4350
4351/* clcs */
a750fc0b 4352GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253
JM		 4353{
4354 gen_op_load_gpr_T0(rA(ctx->opcode));
4355 gen_op_POWER_clcs();
c7697e1f 4356 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4357 gen_op_store_T0_gpr(rD(ctx->opcode));
4358}
4359
4360/* div - div. */
4361GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4362{
4363 gen_op_load_gpr_T0(rA(ctx->opcode));
4364 gen_op_load_gpr_T1(rB(ctx->opcode));
4365 gen_op_POWER_div();
4366 gen_op_store_T0_gpr(rD(ctx->opcode));
4367 if (unlikely(Rc(ctx->opcode) != 0))
4368 gen_set_Rc0(ctx);
4369}
4370
4371/* divo - divo. */
4372GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4373{
4374 gen_op_load_gpr_T0(rA(ctx->opcode));
4375 gen_op_load_gpr_T1(rB(ctx->opcode));
4376 gen_op_POWER_divo();
4377 gen_op_store_T0_gpr(rD(ctx->opcode));
4378 if (unlikely(Rc(ctx->opcode) != 0))
4379 gen_set_Rc0(ctx);
4380}
4381
4382/* divs - divs. */
4383GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4384{
4385 gen_op_load_gpr_T0(rA(ctx->opcode));
4386 gen_op_load_gpr_T1(rB(ctx->opcode));
4387 gen_op_POWER_divs();
4388 gen_op_store_T0_gpr(rD(ctx->opcode));
4389 if (unlikely(Rc(ctx->opcode) != 0))
4390 gen_set_Rc0(ctx);
4391}
4392
4393/* divso - divso. */
4394GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4395{
4396 gen_op_load_gpr_T0(rA(ctx->opcode));
4397 gen_op_load_gpr_T1(rB(ctx->opcode));
4398 gen_op_POWER_divso();
4399 gen_op_store_T0_gpr(rD(ctx->opcode));
4400 if (unlikely(Rc(ctx->opcode) != 0))
4401 gen_set_Rc0(ctx);
4402}
4403
4404/* doz - doz. */
4405GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4406{
4407 gen_op_load_gpr_T0(rA(ctx->opcode));
4408 gen_op_load_gpr_T1(rB(ctx->opcode));
4409 gen_op_POWER_doz();
4410 gen_op_store_T0_gpr(rD(ctx->opcode));
4411 if (unlikely(Rc(ctx->opcode) != 0))
4412 gen_set_Rc0(ctx);
4413}
4414
4415/* dozo - dozo. */
4416GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4417{
4418 gen_op_load_gpr_T0(rA(ctx->opcode));
4419 gen_op_load_gpr_T1(rB(ctx->opcode));
4420 gen_op_POWER_dozo();
4421 gen_op_store_T0_gpr(rD(ctx->opcode));
4422 if (unlikely(Rc(ctx->opcode) != 0))
4423 gen_set_Rc0(ctx);
4424}
4425
4426/* dozi */
4427GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4428{
4429 gen_op_load_gpr_T0(rA(ctx->opcode));
4430 gen_op_set_T1(SIMM(ctx->opcode));
4431 gen_op_POWER_doz();
4432 gen_op_store_T0_gpr(rD(ctx->opcode));
4433}
4434
4435/* As lscbx load from memory byte after byte, it's always endian safe */
2857068e 4436#define op_POWER_lscbx(start, ra, rb) \
76a66253
JM		 4437(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
4438#if defined(CONFIG_USER_ONLY)
4439static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4440 &gen_op_POWER_lscbx_raw,
4441 &gen_op_POWER_lscbx_raw,
4442};
4443#else
4444static GenOpFunc3 *gen_op_POWER_lscbx[] = {
4445 &gen_op_POWER_lscbx_user,
4446 &gen_op_POWER_lscbx_user,
4447 &gen_op_POWER_lscbx_kernel,
4448 &gen_op_POWER_lscbx_kernel,
4449};
4450#endif
4451
4452/* lscbx - lscbx. */
4453GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4454{
4455 int ra = rA(ctx->opcode);
4456 int rb = rB(ctx->opcode);
4457
4458 gen_addr_reg_index(ctx);
4459 if (ra == 0) {
4460 ra = rb;
4461 }
4462 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4463 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4464 gen_op_load_xer_bc();
4465 gen_op_load_xer_cmp();
4466 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
4467 gen_op_store_xer_bc();
4468 if (unlikely(Rc(ctx->opcode) != 0))
4469 gen_set_Rc0(ctx);
4470}
4471
4472/* maskg - maskg. */
4473GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4474{
4475 gen_op_load_gpr_T0(rS(ctx->opcode));
4476 gen_op_load_gpr_T1(rB(ctx->opcode));
4477 gen_op_POWER_maskg();
4478 gen_op_store_T0_gpr(rA(ctx->opcode));
4479 if (unlikely(Rc(ctx->opcode) != 0))
4480 gen_set_Rc0(ctx);
4481}
4482
4483/* maskir - maskir. */
4484GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4485{
4486 gen_op_load_gpr_T0(rA(ctx->opcode));
4487 gen_op_load_gpr_T1(rS(ctx->opcode));
4488 gen_op_load_gpr_T2(rB(ctx->opcode));
4489 gen_op_POWER_maskir();
4490 gen_op_store_T0_gpr(rA(ctx->opcode));
4491 if (unlikely(Rc(ctx->opcode) != 0))
4492 gen_set_Rc0(ctx);
4493}
4494
4495/* mul - mul. */
4496GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4497{
4498 gen_op_load_gpr_T0(rA(ctx->opcode));
4499 gen_op_load_gpr_T1(rB(ctx->opcode));
4500 gen_op_POWER_mul();
4501 gen_op_store_T0_gpr(rD(ctx->opcode));
4502 if (unlikely(Rc(ctx->opcode) != 0))
4503 gen_set_Rc0(ctx);
4504}
4505
4506/* mulo - mulo. */
4507GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4508{
4509 gen_op_load_gpr_T0(rA(ctx->opcode));
4510 gen_op_load_gpr_T1(rB(ctx->opcode));
4511 gen_op_POWER_mulo();
4512 gen_op_store_T0_gpr(rD(ctx->opcode));
4513 if (unlikely(Rc(ctx->opcode) != 0))
4514 gen_set_Rc0(ctx);
4515}
4516
4517/* nabs - nabs. */
4518GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4519{
4520 gen_op_load_gpr_T0(rA(ctx->opcode));
4521 gen_op_POWER_nabs();
4522 gen_op_store_T0_gpr(rD(ctx->opcode));
4523 if (unlikely(Rc(ctx->opcode) != 0))
4524 gen_set_Rc0(ctx);
4525}
4526
4527/* nabso - nabso. */
4528GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4529{
4530 gen_op_load_gpr_T0(rA(ctx->opcode));
4531 gen_op_POWER_nabso();
4532 gen_op_store_T0_gpr(rD(ctx->opcode));
4533 if (unlikely(Rc(ctx->opcode) != 0))
4534 gen_set_Rc0(ctx);
4535}
4536
4537/* rlmi - rlmi. */
4538GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4539{
4540 uint32_t mb, me;
4541
4542 mb = MB(ctx->opcode);
4543 me = ME(ctx->opcode);
4544 gen_op_load_gpr_T0(rS(ctx->opcode));
4545 gen_op_load_gpr_T1(rA(ctx->opcode));
4546 gen_op_load_gpr_T2(rB(ctx->opcode));
4547 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4548 gen_op_store_T0_gpr(rA(ctx->opcode));
4549 if (unlikely(Rc(ctx->opcode) != 0))
4550 gen_set_Rc0(ctx);
4551}
4552
4553/* rrib - rrib. */
4554GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4555{
4556 gen_op_load_gpr_T0(rS(ctx->opcode));
4557 gen_op_load_gpr_T1(rA(ctx->opcode));
4558 gen_op_load_gpr_T2(rB(ctx->opcode));
4559 gen_op_POWER_rrib();
4560 gen_op_store_T0_gpr(rA(ctx->opcode));
4561 if (unlikely(Rc(ctx->opcode) != 0))
4562 gen_set_Rc0(ctx);
4563}
4564
4565/* sle - sle. */
4566GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4567{
4568 gen_op_load_gpr_T0(rS(ctx->opcode));
4569 gen_op_load_gpr_T1(rB(ctx->opcode));
4570 gen_op_POWER_sle();
4571 gen_op_store_T0_gpr(rA(ctx->opcode));
4572 if (unlikely(Rc(ctx->opcode) != 0))
4573 gen_set_Rc0(ctx);
4574}
4575
4576/* sleq - sleq. */
4577GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4578{
4579 gen_op_load_gpr_T0(rS(ctx->opcode));
4580 gen_op_load_gpr_T1(rB(ctx->opcode));
4581 gen_op_POWER_sleq();
4582 gen_op_store_T0_gpr(rA(ctx->opcode));
4583 if (unlikely(Rc(ctx->opcode) != 0))
4584 gen_set_Rc0(ctx);
4585}
4586
4587/* sliq - sliq. */
4588GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4589{
4590 gen_op_load_gpr_T0(rS(ctx->opcode));
4591 gen_op_set_T1(SH(ctx->opcode));
4592 gen_op_POWER_sle();
4593 gen_op_store_T0_gpr(rA(ctx->opcode));
4594 if (unlikely(Rc(ctx->opcode) != 0))
4595 gen_set_Rc0(ctx);
4596}
4597
4598/* slliq - slliq. */
4599GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4600{
4601 gen_op_load_gpr_T0(rS(ctx->opcode));
4602 gen_op_set_T1(SH(ctx->opcode));
4603 gen_op_POWER_sleq();
4604 gen_op_store_T0_gpr(rA(ctx->opcode));
4605 if (unlikely(Rc(ctx->opcode) != 0))
4606 gen_set_Rc0(ctx);
4607}
4608
4609/* sllq - sllq. */
4610GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4611{
4612 gen_op_load_gpr_T0(rS(ctx->opcode));
4613 gen_op_load_gpr_T1(rB(ctx->opcode));
4614 gen_op_POWER_sllq();
4615 gen_op_store_T0_gpr(rA(ctx->opcode));
4616 if (unlikely(Rc(ctx->opcode) != 0))
4617 gen_set_Rc0(ctx);
4618}
4619
4620/* slq - slq. */
4621GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4622{
4623 gen_op_load_gpr_T0(rS(ctx->opcode));
4624 gen_op_load_gpr_T1(rB(ctx->opcode));
4625 gen_op_POWER_slq();
4626 gen_op_store_T0_gpr(rA(ctx->opcode));
4627 if (unlikely(Rc(ctx->opcode) != 0))
4628 gen_set_Rc0(ctx);
4629}
4630
d9bce9d9 4631/* sraiq - sraiq. */
76a66253
JM		 4632GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4633{
4634 gen_op_load_gpr_T0(rS(ctx->opcode));
4635 gen_op_set_T1(SH(ctx->opcode));
4636 gen_op_POWER_sraq();
4637 gen_op_store_T0_gpr(rA(ctx->opcode));
4638 if (unlikely(Rc(ctx->opcode) != 0))
4639 gen_set_Rc0(ctx);
4640}
4641
4642/* sraq - sraq. */
4643GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4644{
4645 gen_op_load_gpr_T0(rS(ctx->opcode));
4646 gen_op_load_gpr_T1(rB(ctx->opcode));
4647 gen_op_POWER_sraq();
4648 gen_op_store_T0_gpr(rA(ctx->opcode));
4649 if (unlikely(Rc(ctx->opcode) != 0))
4650 gen_set_Rc0(ctx);
4651}
4652
4653/* sre - sre. */
4654GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4655{
4656 gen_op_load_gpr_T0(rS(ctx->opcode));
4657 gen_op_load_gpr_T1(rB(ctx->opcode));
4658 gen_op_POWER_sre();
4659 gen_op_store_T0_gpr(rA(ctx->opcode));
4660 if (unlikely(Rc(ctx->opcode) != 0))
4661 gen_set_Rc0(ctx);
4662}
4663
4664/* srea - srea. */
4665GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4666{
4667 gen_op_load_gpr_T0(rS(ctx->opcode));
4668 gen_op_load_gpr_T1(rB(ctx->opcode));
4669 gen_op_POWER_srea();
4670 gen_op_store_T0_gpr(rA(ctx->opcode));
4671 if (unlikely(Rc(ctx->opcode) != 0))
4672 gen_set_Rc0(ctx);
4673}
4674
4675/* sreq */
4676GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4677{
4678 gen_op_load_gpr_T0(rS(ctx->opcode));
4679 gen_op_load_gpr_T1(rB(ctx->opcode));
4680 gen_op_POWER_sreq();
4681 gen_op_store_T0_gpr(rA(ctx->opcode));
4682 if (unlikely(Rc(ctx->opcode) != 0))
4683 gen_set_Rc0(ctx);
4684}
4685
4686/* sriq */
4687GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4688{
4689 gen_op_load_gpr_T0(rS(ctx->opcode));
4690 gen_op_set_T1(SH(ctx->opcode));
4691 gen_op_POWER_srq();
4692 gen_op_store_T0_gpr(rA(ctx->opcode));
4693 if (unlikely(Rc(ctx->opcode) != 0))
4694 gen_set_Rc0(ctx);
4695}
4696
4697/* srliq */
4698GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4699{
4700 gen_op_load_gpr_T0(rS(ctx->opcode));
4701 gen_op_load_gpr_T1(rB(ctx->opcode));
4702 gen_op_set_T1(SH(ctx->opcode));
4703 gen_op_POWER_srlq();
4704 gen_op_store_T0_gpr(rA(ctx->opcode));
4705 if (unlikely(Rc(ctx->opcode) != 0))
4706 gen_set_Rc0(ctx);
4707}
4708
4709/* srlq */
4710GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4711{
4712 gen_op_load_gpr_T0(rS(ctx->opcode));
4713 gen_op_load_gpr_T1(rB(ctx->opcode));
4714 gen_op_POWER_srlq();
4715 gen_op_store_T0_gpr(rA(ctx->opcode));
4716 if (unlikely(Rc(ctx->opcode) != 0))
4717 gen_set_Rc0(ctx);
4718}
4719
4720/* srq */
4721GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4722{
4723 gen_op_load_gpr_T0(rS(ctx->opcode));
4724 gen_op_load_gpr_T1(rB(ctx->opcode));
4725 gen_op_POWER_srq();
4726 gen_op_store_T0_gpr(rA(ctx->opcode));
4727 if (unlikely(Rc(ctx->opcode) != 0))
4728 gen_set_Rc0(ctx);
4729}
4730
4731/* PowerPC 602 specific instructions */
4732/* dsa */
4733GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4734{
4735 /* XXX: TODO */
e1833e1f 4736 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4737}
4738
4739/* esa */
4740GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4741{
4742 /* XXX: TODO */
e1833e1f 4743 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4744}
4745
4746/* mfrom */
4747GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4748{
4749#if defined(CONFIG_USER_ONLY)
e1833e1f 4750 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4751#else
4752 if (unlikely(!ctx->supervisor)) {
e1833e1f 4753 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4754 return;
4755 }
4756 gen_op_load_gpr_T0(rA(ctx->opcode));
4757 gen_op_602_mfrom();
4758 gen_op_store_T0_gpr(rD(ctx->opcode));
4759#endif
4760}
4761
4762/* 602 - 603 - G2 TLB management */
4763/* tlbld */
c7697e1f 4764GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4765{
4766#if defined(CONFIG_USER_ONLY)
e1833e1f 4767 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4768#else
4769 if (unlikely(!ctx->supervisor)) {
e1833e1f 4770 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4771 return;
4772 }
4773 gen_op_load_gpr_T0(rB(ctx->opcode));
4774 gen_op_6xx_tlbld();
76a66253
JM		 4775#endif
4776}
4777
4778/* tlbli */
c7697e1f 4779GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4780{
4781#if defined(CONFIG_USER_ONLY)
e1833e1f 4782 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4783#else
4784 if (unlikely(!ctx->supervisor)) {
e1833e1f 4785 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4786 return;
4787 }
4788 gen_op_load_gpr_T0(rB(ctx->opcode));
4789 gen_op_6xx_tlbli();
76a66253
JM		 4790#endif
4791}
4792
7dbe11ac
JM		 4793/* 74xx TLB management */
4794/* tlbld */
c7697e1f 4795GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4796{
4797#if defined(CONFIG_USER_ONLY)
4798 GEN_EXCP_PRIVOPC(ctx);
4799#else
4800 if (unlikely(!ctx->supervisor)) {
4801 GEN_EXCP_PRIVOPC(ctx);
4802 return;
4803 }
4804 gen_op_load_gpr_T0(rB(ctx->opcode));
4805 gen_op_74xx_tlbld();
4806#endif
4807}
4808
4809/* tlbli */
c7697e1f 4810GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4811{
4812#if defined(CONFIG_USER_ONLY)
4813 GEN_EXCP_PRIVOPC(ctx);
4814#else
4815 if (unlikely(!ctx->supervisor)) {
4816 GEN_EXCP_PRIVOPC(ctx);
4817 return;
4818 }
4819 gen_op_load_gpr_T0(rB(ctx->opcode));
4820 gen_op_74xx_tlbli();
4821#endif
4822}
4823
76a66253
JM		 4824/* POWER instructions not in PowerPC 601 */
4825/* clf */
4826GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4827{
4828 /* Cache line flush: implemented as no-op */
4829}
4830
4831/* cli */
4832GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4833{
7f75ffd3 4834 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4835#if defined(CONFIG_USER_ONLY)
e1833e1f 4836 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4837#else
4838 if (unlikely(!ctx->supervisor)) {
e1833e1f 4839 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4840 return;
4841 }
4842#endif
4843}
4844
4845/* dclst */
4846GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4847{
4848 /* Data cache line store: treated as no-op */
4849}
4850
4851GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4852{
4853#if defined(CONFIG_USER_ONLY)
e1833e1f 4854 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4855#else
4856 if (unlikely(!ctx->supervisor)) {
e1833e1f 4857 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4858 return;
4859 }
4860 int ra = rA(ctx->opcode);
4861 int rd = rD(ctx->opcode);
4862
4863 gen_addr_reg_index(ctx);
4864 gen_op_POWER_mfsri();
4865 gen_op_store_T0_gpr(rd);
4866 if (ra != 0 && ra != rd)
4867 gen_op_store_T1_gpr(ra);
4868#endif
4869}
4870
4871GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4872{
4873#if defined(CONFIG_USER_ONLY)
e1833e1f 4874 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4875#else
4876 if (unlikely(!ctx->supervisor)) {
e1833e1f 4877 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4878 return;
4879 }
4880 gen_addr_reg_index(ctx);
4881 gen_op_POWER_rac();
4882 gen_op_store_T0_gpr(rD(ctx->opcode));
4883#endif
4884}
4885
4886GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4887{
4888#if defined(CONFIG_USER_ONLY)
e1833e1f 4889 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4890#else
4891 if (unlikely(!ctx->supervisor)) {
e1833e1f 4892 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4893 return;
4894 }
4895 gen_op_POWER_rfsvc();
e1833e1f 4896 GEN_SYNC(ctx);
76a66253
JM		 4897#endif
4898}
4899
4900/* svc is not implemented for now */
4901
4902/* POWER2 specific instructions */
4903/* Quad manipulation (load/store two floats at a time) */
4904#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4905#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
4906#if defined(CONFIG_USER_ONLY)
4907static GenOpFunc *gen_op_POWER2_lfq[] = {
4908 &gen_op_POWER2_lfq_le_raw,
4909 &gen_op_POWER2_lfq_raw,
4910};
4911static GenOpFunc *gen_op_POWER2_stfq[] = {
4912 &gen_op_POWER2_stfq_le_raw,
4913 &gen_op_POWER2_stfq_raw,
4914};
4915#else
4916static GenOpFunc *gen_op_POWER2_lfq[] = {
4917 &gen_op_POWER2_lfq_le_user,
4918 &gen_op_POWER2_lfq_user,
4919 &gen_op_POWER2_lfq_le_kernel,
4920 &gen_op_POWER2_lfq_kernel,
4921};
4922static GenOpFunc *gen_op_POWER2_stfq[] = {
4923 &gen_op_POWER2_stfq_le_user,
4924 &gen_op_POWER2_stfq_user,
4925 &gen_op_POWER2_stfq_le_kernel,
4926 &gen_op_POWER2_stfq_kernel,
4927};
4928#endif
4929
4930/* lfq */
4931GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4932{
4933 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4934 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4935 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4936 op_POWER2_lfq();
4937 gen_op_store_FT0_fpr(rD(ctx->opcode));
4938 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4939}
4940
4941/* lfqu */
4942GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4943{
4944 int ra = rA(ctx->opcode);
4945
4946 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4947 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4948 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4949 op_POWER2_lfq();
4950 gen_op_store_FT0_fpr(rD(ctx->opcode));
4951 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4952 if (ra != 0)
4953 gen_op_store_T0_gpr(ra);
4954}
4955
4956/* lfqux */
4957GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4958{
4959 int ra = rA(ctx->opcode);
4960
4961 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4962 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4963 gen_addr_reg_index(ctx);
4964 op_POWER2_lfq();
4965 gen_op_store_FT0_fpr(rD(ctx->opcode));
4966 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4967 if (ra != 0)
4968 gen_op_store_T0_gpr(ra);
4969}
4970
4971/* lfqx */
4972GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4973{
4974 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4975 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4976 gen_addr_reg_index(ctx);
4977 op_POWER2_lfq();
4978 gen_op_store_FT0_fpr(rD(ctx->opcode));
4979 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4980}
4981
4982/* stfq */
4983GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4984{
4985 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4986 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4987 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4988 gen_op_load_fpr_FT0(rS(ctx->opcode));
4989 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4990 op_POWER2_stfq();
4991}
4992
4993/* stfqu */
4994GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4995{
4996 int ra = rA(ctx->opcode);
4997
4998 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4999 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 5000 gen_addr_imm_index(ctx, 0);
76a66253
JM		 5001 gen_op_load_fpr_FT0(rS(ctx->opcode));
5002 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5003 op_POWER2_stfq();
5004 if (ra != 0)
5005 gen_op_store_T0_gpr(ra);
5006}
5007
5008/* stfqux */
5009GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5010{
5011 int ra = rA(ctx->opcode);
5012
5013 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5014 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 5015 gen_addr_reg_index(ctx);
5016 gen_op_load_fpr_FT0(rS(ctx->opcode));
5017 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5018 op_POWER2_stfq();
5019 if (ra != 0)
5020 gen_op_store_T0_gpr(ra);
5021}
5022
5023/* stfqx */
5024GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5025{
5026 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5027 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 5028 gen_addr_reg_index(ctx);
5029 gen_op_load_fpr_FT0(rS(ctx->opcode));
5030 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
5031 op_POWER2_stfq();
5032}
5033
5034/* BookE specific instructions */
2662a059 5035/* XXX: not implemented on 440 ? */
a750fc0b 5036GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_BOOKE_EXT)
76a66253
JM		 5037{
5038 /* XXX: TODO */
e1833e1f 5039 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5040}
5041
2662a059 5042/* XXX: not implemented on 440 ? */
a750fc0b 5043GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_BOOKE_EXT)
76a66253
JM		 5044{
5045#if defined(CONFIG_USER_ONLY)
e1833e1f 5046 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5047#else
5048 if (unlikely(!ctx->supervisor)) {
e1833e1f 5049 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5050 return;
5051 }
5052 gen_addr_reg_index(ctx);
5053 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5054#if defined(TARGET_PPC64)
5055 if (ctx->sf_mode)
5056 gen_op_tlbie_64();
5057 else
5058#endif
5059 gen_op_tlbie();
76a66253
JM		 5060#endif
5061}
5062
5063/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5064static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5065 int opc2, int opc3,
5066 int ra, int rb, int rt, int Rc)
76a66253
JM		 5067{
5068 gen_op_load_gpr_T0(ra);
5069 gen_op_load_gpr_T1(rb);
5070 switch (opc3 & 0x0D) {
5071 case 0x05:
5072 /* macchw - macchw. - macchwo - macchwo. */
5073 /* macchws - macchws. - macchwso - macchwso. */
5074 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5075 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5076 /* mulchw - mulchw. */
5077 gen_op_405_mulchw();
5078 break;
5079 case 0x04:
5080 /* macchwu - macchwu. - macchwuo - macchwuo. */
5081 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5082 /* mulchwu - mulchwu. */
5083 gen_op_405_mulchwu();
5084 break;
5085 case 0x01:
5086 /* machhw - machhw. - machhwo - machhwo. */
5087 /* machhws - machhws. - machhwso - machhwso. */
5088 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5089 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5090 /* mulhhw - mulhhw. */
5091 gen_op_405_mulhhw();
5092 break;
5093 case 0x00:
5094 /* machhwu - machhwu. - machhwuo - machhwuo. */
5095 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5096 /* mulhhwu - mulhhwu. */
5097 gen_op_405_mulhhwu();
5098 break;
5099 case 0x0D:
5100 /* maclhw - maclhw. - maclhwo - maclhwo. */
5101 /* maclhws - maclhws. - maclhwso - maclhwso. */
5102 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5103 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5104 /* mullhw - mullhw. */
5105 gen_op_405_mullhw();
5106 break;
5107 case 0x0C:
5108 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5109 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5110 /* mullhwu - mullhwu. */
5111 gen_op_405_mullhwu();
5112 break;
5113 }
5114 if (opc2 & 0x02) {
5115 /* nmultiply-and-accumulate (0x0E) */
5116 gen_op_neg();
5117 }
5118 if (opc2 & 0x04) {
5119 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
5120 gen_op_load_gpr_T2(rt);
5121 gen_op_move_T1_T0();
5122 gen_op_405_add_T0_T2();
5123 }
5124 if (opc3 & 0x10) {
5125 /* Check overflow */
5126 if (opc3 & 0x01)
c3e10c7b 5127 gen_op_check_addo();
76a66253
JM		 5128 else
5129 gen_op_405_check_ovu();
5130 }
5131 if (opc3 & 0x02) {
5132 /* Saturate */
5133 if (opc3 & 0x01)
5134 gen_op_405_check_sat();
5135 else
5136 gen_op_405_check_satu();
5137 }
5138 gen_op_store_T0_gpr(rt);
5139 if (unlikely(Rc) != 0) {
5140 /* Update Rc0 */
5141 gen_set_Rc0(ctx);
5142 }
5143}
5144
a750fc0b
JM		 5145#define GEN_MAC_HANDLER(name, opc2, opc3) \
5146GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5147{ \
5148 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5149 rD(ctx->opcode), Rc(ctx->opcode)); \
5150}
5151
5152/* macchw - macchw. */
a750fc0b 5153GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5154/* macchwo - macchwo. */
a750fc0b 5155GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5156/* macchws - macchws. */
a750fc0b 5157GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5158/* macchwso - macchwso. */
a750fc0b 5159GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5160/* macchwsu - macchwsu. */
a750fc0b 5161GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5162/* macchwsuo - macchwsuo. */
a750fc0b 5163GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5164/* macchwu - macchwu. */
a750fc0b 5165GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5166/* macchwuo - macchwuo. */
a750fc0b 5167GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5168/* machhw - machhw. */
a750fc0b 5169GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5170/* machhwo - machhwo. */
a750fc0b 5171GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5172/* machhws - machhws. */
a750fc0b 5173GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5174/* machhwso - machhwso. */
a750fc0b 5175GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5176/* machhwsu - machhwsu. */
a750fc0b 5177GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5178/* machhwsuo - machhwsuo. */
a750fc0b 5179GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5180/* machhwu - machhwu. */
a750fc0b 5181GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5182/* machhwuo - machhwuo. */
a750fc0b 5183GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5184/* maclhw - maclhw. */
a750fc0b 5185GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5186/* maclhwo - maclhwo. */
a750fc0b 5187GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5188/* maclhws - maclhws. */
a750fc0b 5189GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5190/* maclhwso - maclhwso. */
a750fc0b 5191GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5192/* maclhwu - maclhwu. */
a750fc0b 5193GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5194/* maclhwuo - maclhwuo. */
a750fc0b 5195GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5196/* maclhwsu - maclhwsu. */
a750fc0b 5197GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5198/* maclhwsuo - maclhwsuo. */
a750fc0b 5199GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5200/* nmacchw - nmacchw. */
a750fc0b 5201GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5202/* nmacchwo - nmacchwo. */
a750fc0b 5203GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5204/* nmacchws - nmacchws. */
a750fc0b 5205GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5206/* nmacchwso - nmacchwso. */
a750fc0b 5207GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5208/* nmachhw - nmachhw. */
a750fc0b 5209GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5210/* nmachhwo - nmachhwo. */
a750fc0b 5211GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5212/* nmachhws - nmachhws. */
a750fc0b 5213GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5214/* nmachhwso - nmachhwso. */
a750fc0b 5215GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5216/* nmaclhw - nmaclhw. */
a750fc0b 5217GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5218/* nmaclhwo - nmaclhwo. */
a750fc0b 5219GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5220/* nmaclhws - nmaclhws. */
a750fc0b 5221GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5222/* nmaclhwso - nmaclhwso. */
a750fc0b 5223GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5224
5225/* mulchw - mulchw. */
a750fc0b 5226GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5227/* mulchwu - mulchwu. */
a750fc0b 5228GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5229/* mulhhw - mulhhw. */
a750fc0b 5230GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5231/* mulhhwu - mulhhwu. */
a750fc0b 5232GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5233/* mullhw - mullhw. */
a750fc0b 5234GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5235/* mullhwu - mullhwu. */
a750fc0b 5236GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5237
5238/* mfdcr */
5239GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_EMB_COMMON)
5240{
5241#if defined(CONFIG_USER_ONLY)
e1833e1f 5242 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5243#else
5244 uint32_t dcrn = SPR(ctx->opcode);
5245
5246 if (unlikely(!ctx->supervisor)) {
e1833e1f 5247 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5248 return;
5249 }
a42bd6cc
JM		 5250 gen_op_set_T0(dcrn);
5251 gen_op_load_dcr();
76a66253
JM		 5252 gen_op_store_T0_gpr(rD(ctx->opcode));
5253#endif
5254}
5255
5256/* mtdcr */
5257GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_EMB_COMMON)
5258{
5259#if defined(CONFIG_USER_ONLY)
e1833e1f 5260 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5261#else
5262 uint32_t dcrn = SPR(ctx->opcode);
5263
5264 if (unlikely(!ctx->supervisor)) {
e1833e1f 5265 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5266 return;
5267 }
a42bd6cc
JM		 5268 gen_op_set_T0(dcrn);
5269 gen_op_load_gpr_T1(rS(ctx->opcode));
5270 gen_op_store_dcr();
5271#endif
5272}
5273
5274/* mfdcrx */
2662a059 5275/* XXX: not implemented on 440 ? */
a750fc0b 5276GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_BOOKE_EXT)
a42bd6cc
JM		 5277{
5278#if defined(CONFIG_USER_ONLY)
e1833e1f 5279 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5280#else
5281 if (unlikely(!ctx->supervisor)) {
e1833e1f 5282 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5283 return;
5284 }
5285 gen_op_load_gpr_T0(rA(ctx->opcode));
5286 gen_op_load_dcr();
5287 gen_op_store_T0_gpr(rD(ctx->opcode));
a750fc0b 5288 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5289#endif
5290}
5291
5292/* mtdcrx */
2662a059 5293/* XXX: not implemented on 440 ? */
a750fc0b 5294GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_BOOKE_EXT)
a42bd6cc
JM		 5295{
5296#if defined(CONFIG_USER_ONLY)
e1833e1f 5297 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5298#else
5299 if (unlikely(!ctx->supervisor)) {
e1833e1f 5300 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5301 return;
5302 }
5303 gen_op_load_gpr_T0(rA(ctx->opcode));
5304 gen_op_load_gpr_T1(rS(ctx->opcode));
5305 gen_op_store_dcr();
a750fc0b 5306 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5307#endif
5308}
5309
a750fc0b
JM		 5310/* mfdcrux (PPC 460) : user-mode access to DCR */
5311GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5312{
5313 gen_op_load_gpr_T0(rA(ctx->opcode));
5314 gen_op_load_dcr();
5315 gen_op_store_T0_gpr(rD(ctx->opcode));
5316 /* Note: Rc update flag set leads to undefined state of Rc0 */
5317}
5318
5319/* mtdcrux (PPC 460) : user-mode access to DCR */
5320GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5321{
5322 gen_op_load_gpr_T0(rA(ctx->opcode));
5323 gen_op_load_gpr_T1(rS(ctx->opcode));
5324 gen_op_store_dcr();
5325 /* Note: Rc update flag set leads to undefined state of Rc0 */
5326}
5327
76a66253
JM		 5328/* dccci */
5329GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5330{
5331#if defined(CONFIG_USER_ONLY)
e1833e1f 5332 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5333#else
5334 if (unlikely(!ctx->supervisor)) {
e1833e1f 5335 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5336 return;
5337 }
5338 /* interpreted as no-op */
5339#endif
5340}
5341
5342/* dcread */
5343GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5344{
5345#if defined(CONFIG_USER_ONLY)
e1833e1f 5346 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5347#else
5348 if (unlikely(!ctx->supervisor)) {
e1833e1f 5349 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5350 return;
5351 }
5352 gen_addr_reg_index(ctx);
5353 op_ldst(lwz);
5354 gen_op_store_T0_gpr(rD(ctx->opcode));
5355#endif
5356}
5357
5358/* icbt */
c7697e1f 5359GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5360{
5361 /* interpreted as no-op */
5362 /* XXX: specification say this is treated as a load by the MMU
5363 * but does not generate any exception
5364 */
5365}
5366
5367/* iccci */
5368GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5369{
5370#if defined(CONFIG_USER_ONLY)
e1833e1f 5371 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5372#else
5373 if (unlikely(!ctx->supervisor)) {
e1833e1f 5374 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5375 return;
5376 }
5377 /* interpreted as no-op */
5378#endif
5379}
5380
5381/* icread */
5382GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5383{
5384#if defined(CONFIG_USER_ONLY)
e1833e1f 5385 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5386#else
5387 if (unlikely(!ctx->supervisor)) {
e1833e1f 5388 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5389 return;
5390 }
5391 /* interpreted as no-op */
5392#endif
5393}
5394
5395/* rfci (supervisor only) */
c7697e1f 5396GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5397{
5398#if defined(CONFIG_USER_ONLY)
e1833e1f 5399 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5400#else
5401 if (unlikely(!ctx->supervisor)) {
e1833e1f 5402 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5403 return;
5404 }
5405 /* Restore CPU state */
5406 gen_op_40x_rfci();
e1833e1f 5407 GEN_SYNC(ctx);
a42bd6cc
JM		 5408#endif
5409}
5410
5411GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5412{
5413#if defined(CONFIG_USER_ONLY)
e1833e1f 5414 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5415#else
5416 if (unlikely(!ctx->supervisor)) {
e1833e1f 5417 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5418 return;
5419 }
5420 /* Restore CPU state */
5421 gen_op_rfci();
e1833e1f 5422 GEN_SYNC(ctx);
a42bd6cc
JM		 5423#endif
5424}
5425
5426/* BookE specific */
2662a059 5427/* XXX: not implemented on 440 ? */
a750fc0b 5428GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_BOOKE_EXT)
76a66253
JM		 5429{
5430#if defined(CONFIG_USER_ONLY)
e1833e1f 5431 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5432#else
5433 if (unlikely(!ctx->supervisor)) {
e1833e1f 5434 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5435 return;
5436 }
5437 /* Restore CPU state */
a42bd6cc 5438 gen_op_rfdi();
e1833e1f 5439 GEN_SYNC(ctx);
76a66253
JM		 5440#endif
5441}
5442
2662a059 5443/* XXX: not implemented on 440 ? */
a750fc0b 5444GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5445{
5446#if defined(CONFIG_USER_ONLY)
e1833e1f 5447 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5448#else
5449 if (unlikely(!ctx->supervisor)) {
e1833e1f 5450 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5451 return;
5452 }
5453 /* Restore CPU state */
5454 gen_op_rfmci();
e1833e1f 5455 GEN_SYNC(ctx);
a42bd6cc
JM		 5456#endif
5457}
5eb7995e 5458
d9bce9d9 5459/* TLB management - PowerPC 405 implementation */
76a66253 5460/* tlbre */
c7697e1f 5461GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5462{
5463#if defined(CONFIG_USER_ONLY)
e1833e1f 5464 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5465#else
5466 if (unlikely(!ctx->supervisor)) {
e1833e1f 5467 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5468 return;
5469 }
5470 switch (rB(ctx->opcode)) {
5471 case 0:
9a64fbe4 5472 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 5473 gen_op_4xx_tlbre_hi();
5474 gen_op_store_T0_gpr(rD(ctx->opcode));
5475 break;
5476 case 1:
5477 gen_op_load_gpr_T0(rA(ctx->opcode));
5478 gen_op_4xx_tlbre_lo();
5479 gen_op_store_T0_gpr(rD(ctx->opcode));
5480 break;
5481 default:
e1833e1f 5482 GEN_EXCP_INVAL(ctx);
76a66253 5483 break;
9a64fbe4 5484 }
76a66253
JM		 5485#endif
5486}
5487
d9bce9d9 5488/* tlbsx - tlbsx. */
c7697e1f 5489GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5490{
5491#if defined(CONFIG_USER_ONLY)
e1833e1f 5492 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5493#else
5494 if (unlikely(!ctx->supervisor)) {
e1833e1f 5495 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5496 return;
5497 }
5498 gen_addr_reg_index(ctx);
daf4f96e 5499 gen_op_4xx_tlbsx();
76a66253 5500 if (Rc(ctx->opcode))
daf4f96e 5501 gen_op_4xx_tlbsx_check();
9a64fbe4 5502 gen_op_store_T0_gpr(rD(ctx->opcode));
76a66253 5503#endif
79aceca5
FB		 5504}
5505
76a66253 5506/* tlbwe */
c7697e1f 5507GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5508{
76a66253 5509#if defined(CONFIG_USER_ONLY)
e1833e1f 5510 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5511#else
5512 if (unlikely(!ctx->supervisor)) {
e1833e1f 5513 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5514 return;
5515 }
5516 switch (rB(ctx->opcode)) {
5517 case 0:
9a64fbe4 5518 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 5519 gen_op_load_gpr_T1(rS(ctx->opcode));
5520 gen_op_4xx_tlbwe_hi();
5521 break;
5522 case 1:
5523 gen_op_load_gpr_T0(rA(ctx->opcode));
5524 gen_op_load_gpr_T1(rS(ctx->opcode));
5525 gen_op_4xx_tlbwe_lo();
5526 break;
5527 default:
e1833e1f 5528 GEN_EXCP_INVAL(ctx);
76a66253 5529 break;
9a64fbe4 5530 }
76a66253
JM		 5531#endif
5532}
5533
a4bb6c3e 5534/* TLB management - PowerPC 440 implementation */
5eb7995e 5535/* tlbre */
c7697e1f 5536GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5537{
5538#if defined(CONFIG_USER_ONLY)
e1833e1f 5539 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5540#else
5541 if (unlikely(!ctx->supervisor)) {
e1833e1f 5542 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5543 return;
5544 }
5545 switch (rB(ctx->opcode)) {
5546 case 0:
5eb7995e 5547 case 1:
5eb7995e
JM		 5548 case 2:
5549 gen_op_load_gpr_T0(rA(ctx->opcode));
a4bb6c3e 5550 gen_op_440_tlbre(rB(ctx->opcode));
5eb7995e
JM		 5551 gen_op_store_T0_gpr(rD(ctx->opcode));
5552 break;
5553 default:
e1833e1f 5554 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5555 break;
5556 }
5557#endif
5558}
5559
5560/* tlbsx - tlbsx. */
c7697e1f 5561GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5562{
5563#if defined(CONFIG_USER_ONLY)
e1833e1f 5564 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5565#else
5566 if (unlikely(!ctx->supervisor)) {
e1833e1f 5567 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5568 return;
5569 }
5570 gen_addr_reg_index(ctx);
daf4f96e 5571 gen_op_440_tlbsx();
5eb7995e 5572 if (Rc(ctx->opcode))
daf4f96e 5573 gen_op_4xx_tlbsx_check();
5eb7995e
JM		 5574 gen_op_store_T0_gpr(rD(ctx->opcode));
5575#endif
5576}
5577
5578/* tlbwe */
c7697e1f 5579GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5580{
5581#if defined(CONFIG_USER_ONLY)
e1833e1f 5582 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5583#else
5584 if (unlikely(!ctx->supervisor)) {
e1833e1f 5585 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5586 return;
5587 }
5588 switch (rB(ctx->opcode)) {
5589 case 0:
5eb7995e 5590 case 1:
5eb7995e
JM		 5591 case 2:
5592 gen_op_load_gpr_T0(rA(ctx->opcode));
5593 gen_op_load_gpr_T1(rS(ctx->opcode));
a4bb6c3e 5594 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5595 break;
5596 default:
e1833e1f 5597 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5598 break;
5599 }
5600#endif
5601}
5602
76a66253
JM		 5603/* wrtee */
5604GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_EMB_COMMON)
5605{
5606#if defined(CONFIG_USER_ONLY)
e1833e1f 5607 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5608#else
5609 if (unlikely(!ctx->supervisor)) {
e1833e1f 5610 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5611 return;
5612 }
5613 gen_op_load_gpr_T0(rD(ctx->opcode));
a42bd6cc 5614 gen_op_wrte();
dee96f6c
JM		 5615 /* Stop translation to have a chance to raise an exception
5616 * if we just set msr_ee to 1
5617 */
e1833e1f 5618 GEN_STOP(ctx);
76a66253
JM		 5619#endif
5620}
5621
5622/* wrteei */
5623GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_EMB_COMMON)
5624{
5625#if defined(CONFIG_USER_ONLY)
e1833e1f 5626 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5627#else
5628 if (unlikely(!ctx->supervisor)) {
e1833e1f 5629 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5630 return;
5631 }
5632 gen_op_set_T0(ctx->opcode & 0x00010000);
a42bd6cc 5633 gen_op_wrte();
dee96f6c
JM		 5634 /* Stop translation to have a chance to raise an exception
5635 * if we just set msr_ee to 1
5636 */
e1833e1f 5637 GEN_STOP(ctx);
76a66253
JM		 5638#endif
5639}
5640
08e46e54 5641/* PowerPC 440 specific instructions */
76a66253
JM		 5642/* dlmzb */
5643GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5644{
5645 gen_op_load_gpr_T0(rS(ctx->opcode));
5646 gen_op_load_gpr_T1(rB(ctx->opcode));
5647 gen_op_440_dlmzb();
5648 gen_op_store_T0_gpr(rA(ctx->opcode));
5649 gen_op_store_xer_bc();
5650 if (Rc(ctx->opcode)) {
5651 gen_op_440_dlmzb_update_Rc();
5652 gen_op_store_T0_crf(0);
5653 }
5654}
5655
5656/* mbar replaces eieio on 440 */
5657GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5658{
5659 /* interpreted as no-op */
5660}
5661
5662/* msync replaces sync on 440 */
0db1b20e 5663GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5664{
5665 /* interpreted as no-op */
5666}
5667
5668/* icbt */
c7697e1f 5669GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5670{
5671 /* interpreted as no-op */
5672 /* XXX: specification say this is treated as a load by the MMU
5673 * but does not generate any exception
5674 */
79aceca5
FB		 5675}
5676
a9d9eb8f
JM		 5677/*** Altivec vector extension ***/
5678/* Altivec registers moves */
5679GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5680GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5681GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5682
5683GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5684GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5685#if 0 // unused
5686GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5687#endif
5688
5689#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5690#if defined(CONFIG_USER_ONLY)
5691#if defined(TARGET_PPC64)
5692/* User-mode only - 64 bits mode */
5693#define OP_VR_LD_TABLE(name) \
5694static GenOpFunc *gen_op_vr_l##name[] = { \
5695 &gen_op_vr_l##name##_raw, \
5696 &gen_op_vr_l##name##_le_raw, \
5697 &gen_op_vr_l##name##_64_raw, \
5698 &gen_op_vr_l##name##_le_64_raw, \
5699};
5700#define OP_VR_ST_TABLE(name) \
5701static GenOpFunc *gen_op_vr_st##name[] = { \
5702 &gen_op_vr_st##name##_raw, \
5703 &gen_op_vr_st##name##_le_raw, \
5704 &gen_op_vr_st##name##_64_raw, \
5705 &gen_op_vr_st##name##_le_64_raw, \
5706};
5707#else /* defined(TARGET_PPC64) */
5708/* User-mode only - 32 bits mode */
5709#define OP_VR_LD_TABLE(name) \
5710static GenOpFunc *gen_op_vr_l##name[] = { \
5711 &gen_op_vr_l##name##_raw, \
5712 &gen_op_vr_l##name##_le_raw, \
5713};
5714#define OP_VR_ST_TABLE(name) \
5715static GenOpFunc *gen_op_vr_st##name[] = { \
5716 &gen_op_vr_st##name##_raw, \
5717 &gen_op_vr_st##name##_le_raw, \
5718};
5719#endif /* defined(TARGET_PPC64) */
5720#else /* defined(CONFIG_USER_ONLY) */
5721#if defined(TARGET_PPC64H)
5722/* Full system with hypervisor mode */
5723#define OP_VR_LD_TABLE(name) \
5724static GenOpFunc *gen_op_vr_l##name[] = { \
5725 &gen_op_vr_l##name##_user, \
5726 &gen_op_vr_l##name##_le_user, \
5727 &gen_op_vr_l##name##_64_user, \
5728 &gen_op_vr_l##name##_le_64_user, \
5729 &gen_op_vr_l##name##_kernel, \
5730 &gen_op_vr_l##name##_le_kernel, \
5731 &gen_op_vr_l##name##_64_kernel, \
5732 &gen_op_vr_l##name##_le_64_kernel, \
5733 &gen_op_vr_l##name##_hypv, \
5734 &gen_op_vr_l##name##_le_hypv, \
5735 &gen_op_vr_l##name##_64_hypv, \
5736 &gen_op_vr_l##name##_le_64_hypv, \
5737};
5738#define OP_VR_ST_TABLE(name) \
5739static GenOpFunc *gen_op_vr_st##name[] = { \
5740 &gen_op_vr_st##name##_user, \
5741 &gen_op_vr_st##name##_le_user, \
5742 &gen_op_vr_st##name##_64_user, \
5743 &gen_op_vr_st##name##_le_64_user, \
5744 &gen_op_vr_st##name##_kernel, \
5745 &gen_op_vr_st##name##_le_kernel, \
5746 &gen_op_vr_st##name##_64_kernel, \
5747 &gen_op_vr_st##name##_le_64_kernel, \
5748 &gen_op_vr_st##name##_hypv, \
5749 &gen_op_vr_st##name##_le_hypv, \
5750 &gen_op_vr_st##name##_64_hypv, \
5751 &gen_op_vr_st##name##_le_64_hypv, \
5752};
5753#elif defined(TARGET_PPC64)
5754/* Full system - 64 bits mode */
5755#define OP_VR_LD_TABLE(name) \
5756static GenOpFunc *gen_op_vr_l##name[] = { \
5757 &gen_op_vr_l##name##_user, \
5758 &gen_op_vr_l##name##_le_user, \
5759 &gen_op_vr_l##name##_64_user, \
5760 &gen_op_vr_l##name##_le_64_user, \
5761 &gen_op_vr_l##name##_kernel, \
5762 &gen_op_vr_l##name##_le_kernel, \
5763 &gen_op_vr_l##name##_64_kernel, \
5764 &gen_op_vr_l##name##_le_64_kernel, \
5765};
5766#define OP_VR_ST_TABLE(name) \
5767static GenOpFunc *gen_op_vr_st##name[] = { \
5768 &gen_op_vr_st##name##_user, \
5769 &gen_op_vr_st##name##_le_user, \
5770 &gen_op_vr_st##name##_64_user, \
5771 &gen_op_vr_st##name##_le_64_user, \
5772 &gen_op_vr_st##name##_kernel, \
5773 &gen_op_vr_st##name##_le_kernel, \
5774 &gen_op_vr_st##name##_64_kernel, \
5775 &gen_op_vr_st##name##_le_64_kernel, \
5776};
5777#else /* defined(TARGET_PPC64) */
5778/* Full system - 32 bits mode */
5779#define OP_VR_LD_TABLE(name) \
5780static GenOpFunc *gen_op_vr_l##name[] = { \
5781 &gen_op_vr_l##name##_user, \
5782 &gen_op_vr_l##name##_le_user, \
5783 &gen_op_vr_l##name##_kernel, \
5784 &gen_op_vr_l##name##_le_kernel, \
5785};
5786#define OP_VR_ST_TABLE(name) \
5787static GenOpFunc *gen_op_vr_st##name[] = { \
5788 &gen_op_vr_st##name##_user, \
5789 &gen_op_vr_st##name##_le_user, \
5790 &gen_op_vr_st##name##_kernel, \
5791 &gen_op_vr_st##name##_le_kernel, \
5792};
5793#endif /* defined(TARGET_PPC64) */
5794#endif /* defined(CONFIG_USER_ONLY) */
5795
5796#define GEN_VR_LDX(name, opc2, opc3) \
5797GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5798{ \
5799 if (unlikely(!ctx->altivec_enabled)) { \
5800 GEN_EXCP_NO_VR(ctx); \
5801 return; \
5802 } \
5803 gen_addr_reg_index(ctx); \
5804 op_vr_ldst(vr_l##name); \
5805 gen_op_store_A0_avr(rD(ctx->opcode)); \
5806}
5807
5808#define GEN_VR_STX(name, opc2, opc3) \
5809GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5810{ \
5811 if (unlikely(!ctx->altivec_enabled)) { \
5812 GEN_EXCP_NO_VR(ctx); \
5813 return; \
5814 } \
5815 gen_addr_reg_index(ctx); \
5816 gen_op_load_avr_A0(rS(ctx->opcode)); \
5817 op_vr_ldst(vr_st##name); \
5818}
5819
5820OP_VR_LD_TABLE(vx);
5821GEN_VR_LDX(vx, 0x07, 0x03);
5822/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5823#define gen_op_vr_lvxl gen_op_vr_lvx
5824GEN_VR_LDX(vxl, 0x07, 0x0B);
5825
5826OP_VR_ST_TABLE(vx);
5827GEN_VR_STX(vx, 0x07, 0x07);
5828/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5829#define gen_op_vr_stvxl gen_op_vr_stvx
5830GEN_VR_STX(vxl, 0x07, 0x0F);
5831
0487d6a8
JM		 5832/*** SPE extension ***/
5833
5834/* Register moves */
65d6c0f3 5835#if !defined(TARGET_PPC64)
3cd7d1dd 5836
0487d6a8
JM		 5837GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5838GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5839#if 0 // unused
5840GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5841#endif
5842
5843GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5844GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5845#if 0 // unused
5846GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5847#endif
5848
65d6c0f3 5849#else /* !defined(TARGET_PPC64) */
3cd7d1dd
JM		 5850
5851/* No specific load/store functions: GPRs are already 64 bits */
5852#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
5853#define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
5854#if 0 // unused
5855#define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
5856#endif
5857
5858#define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
5859#define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
5860#if 0 // unused
5861#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
5862#endif
5863
65d6c0f3 5864#endif /* !defined(TARGET_PPC64) */
3cd7d1dd 5865
0487d6a8
JM		 5866#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5867GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5868{ \
5869 if (Rc(ctx->opcode)) \
5870 gen_##name1(ctx); \
5871 else \
5872 gen_##name0(ctx); \
5873}
5874
5875/* Handler for undefined SPE opcodes */
b068d6a7 5876static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5877{
e1833e1f 5878 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5879}
5880
5881/* SPE load and stores */
b068d6a7 5882static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
0487d6a8
JM		 5883{
5884 target_long simm = rB(ctx->opcode);
5885
5886 if (rA(ctx->opcode) == 0) {
5887 gen_set_T0(simm << sh);
5888 } else {
5889 gen_op_load_gpr_T0(rA(ctx->opcode));
5890 if (likely(simm != 0))
5891 gen_op_addi(simm << sh);
5892 }
5893}
5894
5895#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
5896#if defined(CONFIG_USER_ONLY)
5897#if defined(TARGET_PPC64)
2857068e 5898/* User-mode only - 64 bits mode */
0487d6a8
JM		 5899#define OP_SPE_LD_TABLE(name) \
5900static GenOpFunc *gen_op_spe_l##name[] = { \
5901 &gen_op_spe_l##name##_raw, \
5902 &gen_op_spe_l##name##_le_raw, \
5903 &gen_op_spe_l##name##_64_raw, \
5904 &gen_op_spe_l##name##_le_64_raw, \
5905};
5906#define OP_SPE_ST_TABLE(name) \
5907static GenOpFunc *gen_op_spe_st##name[] = { \
5908 &gen_op_spe_st##name##_raw, \
5909 &gen_op_spe_st##name##_le_raw, \
5910 &gen_op_spe_st##name##_64_raw, \
5911 &gen_op_spe_st##name##_le_64_raw, \
5912};
5913#else /* defined(TARGET_PPC64) */
2857068e 5914/* User-mode only - 32 bits mode */
0487d6a8
JM		 5915#define OP_SPE_LD_TABLE(name) \
5916static GenOpFunc *gen_op_spe_l##name[] = { \
5917 &gen_op_spe_l##name##_raw, \
5918 &gen_op_spe_l##name##_le_raw, \
5919};
5920#define OP_SPE_ST_TABLE(name) \
5921static GenOpFunc *gen_op_spe_st##name[] = { \
5922 &gen_op_spe_st##name##_raw, \
5923 &gen_op_spe_st##name##_le_raw, \
5924};
5925#endif /* defined(TARGET_PPC64) */
5926#else /* defined(CONFIG_USER_ONLY) */
2857068e
JM		 5927#if defined(TARGET_PPC64H)
5928/* Full system with hypervisor mode */
0487d6a8
JM		 5929#define OP_SPE_LD_TABLE(name) \
5930static GenOpFunc *gen_op_spe_l##name[] = { \
5931 &gen_op_spe_l##name##_user, \
5932 &gen_op_spe_l##name##_le_user, \
0487d6a8
JM		 5933 &gen_op_spe_l##name##_64_user, \
5934 &gen_op_spe_l##name##_le_64_user, \
2857068e
JM		 5935 &gen_op_spe_l##name##_kernel, \
5936 &gen_op_spe_l##name##_le_kernel, \
0487d6a8
JM		 5937 &gen_op_spe_l##name##_64_kernel, \
5938 &gen_op_spe_l##name##_le_64_kernel, \
2857068e
JM		 5939 &gen_op_spe_l##name##_hypv, \
5940 &gen_op_spe_l##name##_le_hypv, \
5941 &gen_op_spe_l##name##_64_hypv, \
5942 &gen_op_spe_l##name##_le_64_hypv, \
0487d6a8
JM		 5943};
5944#define OP_SPE_ST_TABLE(name) \
5945static GenOpFunc *gen_op_spe_st##name[] = { \
5946 &gen_op_spe_st##name##_user, \
5947 &gen_op_spe_st##name##_le_user, \
2857068e
JM		 5948 &gen_op_spe_st##name##_64_user, \
5949 &gen_op_spe_st##name##_le_64_user, \
0487d6a8
JM		 5950 &gen_op_spe_st##name##_kernel, \
5951 &gen_op_spe_st##name##_le_kernel, \
2857068e
JM		 5952 &gen_op_spe_st##name##_64_kernel, \
5953 &gen_op_spe_st##name##_le_64_kernel, \
5954 &gen_op_spe_st##name##_hypv, \
5955 &gen_op_spe_st##name##_le_hypv, \
5956 &gen_op_spe_st##name##_64_hypv, \
5957 &gen_op_spe_st##name##_le_64_hypv, \
5958};
5959#elif defined(TARGET_PPC64)
5960/* Full system - 64 bits mode */
5961#define OP_SPE_LD_TABLE(name) \
5962static GenOpFunc *gen_op_spe_l##name[] = { \
5963 &gen_op_spe_l##name##_user, \
5964 &gen_op_spe_l##name##_le_user, \
5965 &gen_op_spe_l##name##_64_user, \
5966 &gen_op_spe_l##name##_le_64_user, \
5967 &gen_op_spe_l##name##_kernel, \
5968 &gen_op_spe_l##name##_le_kernel, \
5969 &gen_op_spe_l##name##_64_kernel, \
5970 &gen_op_spe_l##name##_le_64_kernel, \
5971};
5972#define OP_SPE_ST_TABLE(name) \
5973static GenOpFunc *gen_op_spe_st##name[] = { \
5974 &gen_op_spe_st##name##_user, \
5975 &gen_op_spe_st##name##_le_user, \
0487d6a8
JM		 5976 &gen_op_spe_st##name##_64_user, \
5977 &gen_op_spe_st##name##_le_64_user, \
2857068e
JM		 5978 &gen_op_spe_st##name##_kernel, \
5979 &gen_op_spe_st##name##_le_kernel, \
0487d6a8
JM		 5980 &gen_op_spe_st##name##_64_kernel, \
5981 &gen_op_spe_st##name##_le_64_kernel, \
5982};
5983#else /* defined(TARGET_PPC64) */
2857068e 5984/* Full system - 32 bits mode */
0487d6a8
JM		 5985#define OP_SPE_LD_TABLE(name) \
5986static GenOpFunc *gen_op_spe_l##name[] = { \
5987 &gen_op_spe_l##name##_user, \
5988 &gen_op_spe_l##name##_le_user, \
5989 &gen_op_spe_l##name##_kernel, \
5990 &gen_op_spe_l##name##_le_kernel, \
5991};
5992#define OP_SPE_ST_TABLE(name) \
5993static GenOpFunc *gen_op_spe_st##name[] = { \
5994 &gen_op_spe_st##name##_user, \
5995 &gen_op_spe_st##name##_le_user, \
5996 &gen_op_spe_st##name##_kernel, \
5997 &gen_op_spe_st##name##_le_kernel, \
5998};
5999#endif /* defined(TARGET_PPC64) */
6000#endif /* defined(CONFIG_USER_ONLY) */
6001
6002#define GEN_SPE_LD(name, sh) \
b068d6a7 6003static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 6004{ \
6005 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6006 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6007 return; \
6008 } \
6009 gen_addr_spe_imm_index(ctx, sh); \
6010 op_spe_ldst(spe_l##name); \
6011 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
6012}
6013
6014#define GEN_SPE_LDX(name) \
b068d6a7 6015static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 6016{ \
6017 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6018 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6019 return; \
6020 } \
6021 gen_addr_reg_index(ctx); \
6022 op_spe_ldst(spe_l##name); \
6023 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
6024}
6025
6026#define GEN_SPEOP_LD(name, sh) \
6027OP_SPE_LD_TABLE(name); \
6028GEN_SPE_LD(name, sh); \
6029GEN_SPE_LDX(name)
6030
6031#define GEN_SPE_ST(name, sh) \
b068d6a7 6032static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 6033{ \
6034 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6035 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6036 return; \
6037 } \
6038 gen_addr_spe_imm_index(ctx, sh); \
6039 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6040 op_spe_ldst(spe_st##name); \
6041}
6042
6043#define GEN_SPE_STX(name) \
b068d6a7 6044static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 6045{ \
6046 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6047 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6048 return; \
6049 } \
6050 gen_addr_reg_index(ctx); \
6051 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
6052 op_spe_ldst(spe_st##name); \
6053}
6054
6055#define GEN_SPEOP_ST(name, sh) \
6056OP_SPE_ST_TABLE(name); \
6057GEN_SPE_ST(name, sh); \
6058GEN_SPE_STX(name)
6059
6060#define GEN_SPEOP_LDST(name, sh) \
6061GEN_SPEOP_LD(name, sh); \
6062GEN_SPEOP_ST(name, sh)
6063
6064/* SPE arithmetic and logic */
6065#define GEN_SPEOP_ARITH2(name) \
b068d6a7 6066static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6067{ \
6068 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6069 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6070 return; \
6071 } \
6072 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6073 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6074 gen_op_##name(); \
6075 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6076}
6077
6078#define GEN_SPEOP_ARITH1(name) \
b068d6a7 6079static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6080{ \
6081 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6082 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6083 return; \
6084 } \
6085 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6086 gen_op_##name(); \
6087 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6088}
6089
6090#define GEN_SPEOP_COMP(name) \
b068d6a7 6091static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6092{ \
6093 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6094 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6095 return; \
6096 } \
6097 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6098 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
6099 gen_op_##name(); \
6100 gen_op_store_T0_crf(crfD(ctx->opcode)); \
6101}
6102
6103/* Logical */
6104GEN_SPEOP_ARITH2(evand);
6105GEN_SPEOP_ARITH2(evandc);
6106GEN_SPEOP_ARITH2(evxor);
6107GEN_SPEOP_ARITH2(evor);
6108GEN_SPEOP_ARITH2(evnor);
6109GEN_SPEOP_ARITH2(eveqv);
6110GEN_SPEOP_ARITH2(evorc);
6111GEN_SPEOP_ARITH2(evnand);
6112GEN_SPEOP_ARITH2(evsrwu);
6113GEN_SPEOP_ARITH2(evsrws);
6114GEN_SPEOP_ARITH2(evslw);
6115GEN_SPEOP_ARITH2(evrlw);
6116GEN_SPEOP_ARITH2(evmergehi);
6117GEN_SPEOP_ARITH2(evmergelo);
6118GEN_SPEOP_ARITH2(evmergehilo);
6119GEN_SPEOP_ARITH2(evmergelohi);
6120
6121/* Arithmetic */
6122GEN_SPEOP_ARITH2(evaddw);
6123GEN_SPEOP_ARITH2(evsubfw);
6124GEN_SPEOP_ARITH1(evabs);
6125GEN_SPEOP_ARITH1(evneg);
6126GEN_SPEOP_ARITH1(evextsb);
6127GEN_SPEOP_ARITH1(evextsh);
6128GEN_SPEOP_ARITH1(evrndw);
6129GEN_SPEOP_ARITH1(evcntlzw);
6130GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 6131static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 6132{
6133 /* Note: brinc is usable even if SPE is disabled */
3cd7d1dd
JM		 6134 gen_op_load_gpr_T0(rA(ctx->opcode));
6135 gen_op_load_gpr_T1(rB(ctx->opcode));
0487d6a8 6136 gen_op_brinc();
3cd7d1dd 6137 gen_op_store_T0_gpr(rD(ctx->opcode));
0487d6a8
JM		 6138}
6139
6140#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 6141static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 6142{ \
6143 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6144 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6145 return; \
6146 } \
6147 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6148 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
6149 gen_op_##name(); \
6150 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6151}
6152
6153#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 6154static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 6155{ \
6156 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6157 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6158 return; \
6159 } \
6160 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
6161 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6162 gen_op_##name(); \
6163 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6164}
6165
6166GEN_SPEOP_ARITH_IMM2(evaddw);
6167#define gen_evaddiw gen_evaddwi
6168GEN_SPEOP_ARITH_IMM2(evsubfw);
6169#define gen_evsubifw gen_evsubfwi
6170GEN_SPEOP_LOGIC_IMM2(evslw);
6171GEN_SPEOP_LOGIC_IMM2(evsrwu);
6172#define gen_evsrwis gen_evsrwsi
6173GEN_SPEOP_LOGIC_IMM2(evsrws);
6174#define gen_evsrwiu gen_evsrwui
6175GEN_SPEOP_LOGIC_IMM2(evrlw);
6176
b068d6a7 6177static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 6178{
6179 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
6180
6181 gen_op_splatwi_T0_64(imm);
6182 gen_op_store_T0_gpr64(rD(ctx->opcode));
6183}
6184
b068d6a7 6185static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 6186{
6187 uint32_t imm = rA(ctx->opcode) << 27;
6188
6189 gen_op_splatwi_T0_64(imm);
6190 gen_op_store_T0_gpr64(rD(ctx->opcode));
6191}
6192
6193/* Comparison */
6194GEN_SPEOP_COMP(evcmpgtu);
6195GEN_SPEOP_COMP(evcmpgts);
6196GEN_SPEOP_COMP(evcmpltu);
6197GEN_SPEOP_COMP(evcmplts);
6198GEN_SPEOP_COMP(evcmpeq);
6199
6200GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6201GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6202GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6203GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6204GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6205GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6206GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6207GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6208GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6209GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6210GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6211GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6212GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6213GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6214GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6215GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6216GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6217GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6218GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6219GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6220GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6221GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6222GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6223GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6224GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6225
b068d6a7 6226static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 6227{
6228 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 6229 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 6230 return;
6231 }
6232 gen_op_load_crf_T0(ctx->opcode & 0x7);
6233 gen_op_load_gpr64_T0(rA(ctx->opcode));
6234 gen_op_load_gpr64_T1(rB(ctx->opcode));
6235 gen_op_evsel();
6236 gen_op_store_T0_gpr64(rD(ctx->opcode));
6237}
6238
c7697e1f 6239GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6240{
6241 gen_evsel(ctx);
6242}
c7697e1f 6243GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6244{
6245 gen_evsel(ctx);
6246}
c7697e1f 6247GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6248{
6249 gen_evsel(ctx);
6250}
c7697e1f 6251GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6252{
6253 gen_evsel(ctx);
6254}
6255
6256/* Load and stores */
6257#if defined(TARGET_PPC64)
6258/* In that case, we already have 64 bits load & stores
6259 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
6260 */
6261#if defined(CONFIG_USER_ONLY)
6262#define gen_op_spe_ldd_raw gen_op_ld_raw
6263#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
6264#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
6265#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
6266#define gen_op_spe_stdd_raw gen_op_ld_raw
6267#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
6268#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
6269#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
6270#else /* defined(CONFIG_USER_ONLY) */
3cd7d1dd
JM		 6271#if defined(TARGET_PPC64H)
6272#define gen_op_spe_ldd_hypv gen_op_ld_hypv
6273#define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
6274#define gen_op_spe_ldd_le_hypv gen_op_ld_hypv
6275#define gen_op_spe_ldd_le_64_hypv gen_op_ld_64_hypv
6276#endif
0487d6a8
JM		 6277#define gen_op_spe_ldd_kernel gen_op_ld_kernel
6278#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
6279#define gen_op_spe_ldd_le_kernel gen_op_ld_kernel
6280#define gen_op_spe_ldd_le_64_kernel gen_op_ld_64_kernel
6281#define gen_op_spe_ldd_user gen_op_ld_user
6282#define gen_op_spe_ldd_64_user gen_op_ld_64_user
6283#define gen_op_spe_ldd_le_user gen_op_ld_le_user
6284#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
3cd7d1dd
JM		 6285#if defined(TARGET_PPC64H)
6286#define gen_op_spe_stdd_hypv gen_op_std_hypv
6287#define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
6288#define gen_op_spe_stdd_le_hypv gen_op_std_hypv
6289#define gen_op_spe_stdd_le_64_hypv gen_op_std_64_hypv
6290#endif
0487d6a8
JM		 6291#define gen_op_spe_stdd_kernel gen_op_std_kernel
6292#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
6293#define gen_op_spe_stdd_le_kernel gen_op_std_kernel
6294#define gen_op_spe_stdd_le_64_kernel gen_op_std_64_kernel
6295#define gen_op_spe_stdd_user gen_op_std_user
6296#define gen_op_spe_stdd_64_user gen_op_std_64_user
6297#define gen_op_spe_stdd_le_user gen_op_std_le_user
6298#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
6299#endif /* defined(CONFIG_USER_ONLY) */
6300#endif /* defined(TARGET_PPC64) */
6301GEN_SPEOP_LDST(dd, 3);
6302GEN_SPEOP_LDST(dw, 3);
6303GEN_SPEOP_LDST(dh, 3);
6304GEN_SPEOP_LDST(whe, 2);
6305GEN_SPEOP_LD(whou, 2);
6306GEN_SPEOP_LD(whos, 2);
6307GEN_SPEOP_ST(who, 2);
6308
6309#if defined(TARGET_PPC64)
6310/* In that case, spe_stwwo is equivalent to stw */
6311#if defined(CONFIG_USER_ONLY)
6312#define gen_op_spe_stwwo_raw gen_op_stw_raw
6313#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
6314#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
6315#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
6316#else
6317#define gen_op_spe_stwwo_user gen_op_stw_user
6318#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
6319#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
6320#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
6321#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
6322#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
6323#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
6324#define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
3cd7d1dd
JM		 6325#if defined(TARGET_PPC64H)
6326#define gen_op_spe_stwwo_hypv gen_op_stw_hypv
6327#define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
6328#define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
6329#define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
6330#endif
0487d6a8
JM		 6331#endif
6332#endif
6333#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 6334static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 6335{ \
6336 gen_op_srli32_T1_64(); \
6337 gen_op_spe_stwwo_##suffix(); \
6338}
6339#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 6340static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 6341{ \
6342 gen_op_srli32_T1_64(); \
6343 gen_op_spe_stwwo_le_##suffix(); \
6344}
6345#if defined(TARGET_PPC64)
6346#define GEN_OP_SPE_STWWE(suffix) \
6347_GEN_OP_SPE_STWWE(suffix); \
6348_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 6349static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 6350{ \
6351 gen_op_srli32_T1_64(); \
6352 gen_op_spe_stwwo_64_##suffix(); \
6353} \
b068d6a7 6354static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 6355{ \
6356 gen_op_srli32_T1_64(); \
6357 gen_op_spe_stwwo_le_64_##suffix(); \
6358}
6359#else
6360#define GEN_OP_SPE_STWWE(suffix) \
6361_GEN_OP_SPE_STWWE(suffix); \
6362_GEN_OP_SPE_STWWE_LE(suffix)
6363#endif
6364#if defined(CONFIG_USER_ONLY)
6365GEN_OP_SPE_STWWE(raw);
6366#else /* defined(CONFIG_USER_ONLY) */
3cd7d1dd
JM		 6367#if defined(TARGET_PPC64H)
6368GEN_OP_SPE_STWWE(hypv);
6369#endif
0487d6a8
JM		 6370GEN_OP_SPE_STWWE(kernel);
6371GEN_OP_SPE_STWWE(user);
6372#endif /* defined(CONFIG_USER_ONLY) */
6373GEN_SPEOP_ST(wwe, 2);
6374GEN_SPEOP_ST(wwo, 2);
6375
6376#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 6377static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 6378{ \
6379 gen_op_##op##_##suffix(); \
6380 gen_op_splatw_T1_64(); \
6381}
6382
6383#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 6384static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 6385{ \
6386 gen_op_spe_lh_##suffix(); \
6387 gen_op_sli16_T1_64(); \
6388}
6389
6390#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 6391static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 6392{ \
6393 gen_op_spe_lh_##suffix(); \
6394 gen_op_extsh_T1_64(); \
6395}
6396
6397#if defined(CONFIG_USER_ONLY)
6398GEN_OP_SPE_LHE(raw);
6399GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6400GEN_OP_SPE_LHE(le_raw);
6401GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6402GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6403GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6404GEN_OP_SPE_LHX(raw);
6405GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6406GEN_OP_SPE_LHX(le_raw);
6407GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6408#if defined(TARGET_PPC64)
6409GEN_OP_SPE_LHE(64_raw);
6410GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6411GEN_OP_SPE_LHE(le_64_raw);
6412GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6413GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6414GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6415GEN_OP_SPE_LHX(64_raw);
6416GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6417GEN_OP_SPE_LHX(le_64_raw);
6418GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6419#endif
6420#else
3cd7d1dd
JM		 6421#if defined(TARGET_PPC64H)
6422GEN_OP_SPE_LHE(hypv);
6423#endif
0487d6a8
JM		 6424GEN_OP_SPE_LHE(kernel);
6425GEN_OP_SPE_LHE(user);
3cd7d1dd
JM		 6426#if defined(TARGET_PPC64H)
6427GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
6428#endif
0487d6a8
JM		 6429GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6430GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
3cd7d1dd
JM		 6431#if defined(TARGET_PPC64H)
6432GEN_OP_SPE_LHE(le_hypv);
6433#endif
0487d6a8
JM		 6434GEN_OP_SPE_LHE(le_kernel);
6435GEN_OP_SPE_LHE(le_user);
3cd7d1dd
JM		 6436#if defined(TARGET_PPC64H)
6437GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
6438#endif
0487d6a8
JM		 6439GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6440GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
3cd7d1dd
JM		 6441#if defined(TARGET_PPC64H)
6442GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
6443#endif
0487d6a8
JM		 6444GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6445GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
3cd7d1dd
JM		 6446#if defined(TARGET_PPC64H)
6447GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
6448#endif
0487d6a8
JM		 6449GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6450GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
3cd7d1dd
JM		 6451#if defined(TARGET_PPC64H)
6452GEN_OP_SPE_LHX(hypv);
6453#endif
0487d6a8
JM		 6454GEN_OP_SPE_LHX(kernel);
6455GEN_OP_SPE_LHX(user);
3cd7d1dd
JM		 6456#if defined(TARGET_PPC64H)
6457GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
6458#endif
0487d6a8
JM		 6459GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6460GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
3cd7d1dd
JM		 6461#if defined(TARGET_PPC64H)
6462GEN_OP_SPE_LHX(le_hypv);
6463#endif
0487d6a8
JM		 6464GEN_OP_SPE_LHX(le_kernel);
6465GEN_OP_SPE_LHX(le_user);
3cd7d1dd
JM		 6466#if defined(TARGET_PPC64H)
6467GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
6468#endif
0487d6a8
JM		 6469GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6470GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
6471#if defined(TARGET_PPC64)
3cd7d1dd
JM		 6472#if defined(TARGET_PPC64H)
6473GEN_OP_SPE_LHE(64_hypv);
6474#endif
0487d6a8
JM		 6475GEN_OP_SPE_LHE(64_kernel);
6476GEN_OP_SPE_LHE(64_user);
3cd7d1dd
JM		 6477#if defined(TARGET_PPC64H)
6478GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
6479#endif
0487d6a8
JM		 6480GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6481GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
3cd7d1dd
JM		 6482#if defined(TARGET_PPC64H)
6483GEN_OP_SPE_LHE(le_64_hypv);
6484#endif
0487d6a8
JM		 6485GEN_OP_SPE_LHE(le_64_kernel);
6486GEN_OP_SPE_LHE(le_64_user);
3cd7d1dd
JM		 6487#if defined(TARGET_PPC64H)
6488GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
6489#endif
0487d6a8
JM		 6490GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6491GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
3cd7d1dd
JM		 6492#if defined(TARGET_PPC64H)
6493GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
6494#endif
0487d6a8
JM		 6495GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6496GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
3cd7d1dd
JM		 6497#if defined(TARGET_PPC64H)
6498GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
6499#endif
0487d6a8
JM		 6500GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6501GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
3cd7d1dd
JM		 6502#if defined(TARGET_PPC64H)
6503GEN_OP_SPE_LHX(64_hypv);
6504#endif
0487d6a8
JM		 6505GEN_OP_SPE_LHX(64_kernel);
6506GEN_OP_SPE_LHX(64_user);
3cd7d1dd
JM		 6507#if defined(TARGET_PPC64H)
6508GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
6509#endif
0487d6a8
JM		 6510GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6511GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
3cd7d1dd
JM		 6512#if defined(TARGET_PPC64H)
6513GEN_OP_SPE_LHX(le_64_hypv);
6514#endif
0487d6a8
JM		 6515GEN_OP_SPE_LHX(le_64_kernel);
6516GEN_OP_SPE_LHX(le_64_user);
3cd7d1dd
JM		 6517#if defined(TARGET_PPC64H)
6518GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
6519#endif
0487d6a8
JM		 6520GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6521GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
6522#endif
6523#endif
6524GEN_SPEOP_LD(hhesplat, 1);
6525GEN_SPEOP_LD(hhousplat, 1);
6526GEN_SPEOP_LD(hhossplat, 1);
6527GEN_SPEOP_LD(wwsplat, 2);
6528GEN_SPEOP_LD(whsplat, 2);
6529
6530GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6531GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6532GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6533GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6534GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6535GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6536GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6537GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6538GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6539GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6540GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6541GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6542GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6543GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6544GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6545GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6546GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6547GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6548
6549/* Multiply and add - TODO */
6550#if 0
6551GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6552GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6553GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6554GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6555GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6556GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6557GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6558GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6559GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6560GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6561GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6562GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6563
6564GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6565GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6566GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6567GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6568GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6569GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6570GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6571GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6572GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6573GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6574GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6575GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6576GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6577GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6578
6579GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6580GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6581GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6582GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6583GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6584GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6585
6586GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6587GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6588GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6589GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6590GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6591GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6592GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6593GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6594GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6595GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6596GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6597GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6598
6599GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6600GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6601GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6602GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6603GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6604
6605GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6606GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6607GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6608GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6609GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6610GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6611GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6612GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6613GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6614GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6615GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6616GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6617
6618GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6619GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6620GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6621GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6622GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6623#endif
6624
6625/*** SPE floating-point extension ***/
6626#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 6627static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6628{ \
6629 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
6630 gen_op_##name(); \
6631 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
6632}
6633
6634/* Single precision floating-point vectors operations */
6635/* Arithmetic */
6636GEN_SPEOP_ARITH2(evfsadd);
6637GEN_SPEOP_ARITH2(evfssub);
6638GEN_SPEOP_ARITH2(evfsmul);
6639GEN_SPEOP_ARITH2(evfsdiv);
6640GEN_SPEOP_ARITH1(evfsabs);
6641GEN_SPEOP_ARITH1(evfsnabs);
6642GEN_SPEOP_ARITH1(evfsneg);
6643/* Conversion */
6644GEN_SPEFPUOP_CONV(evfscfui);
6645GEN_SPEFPUOP_CONV(evfscfsi);
6646GEN_SPEFPUOP_CONV(evfscfuf);
6647GEN_SPEFPUOP_CONV(evfscfsf);
6648GEN_SPEFPUOP_CONV(evfsctui);
6649GEN_SPEFPUOP_CONV(evfsctsi);
6650GEN_SPEFPUOP_CONV(evfsctuf);
6651GEN_SPEFPUOP_CONV(evfsctsf);
6652GEN_SPEFPUOP_CONV(evfsctuiz);
6653GEN_SPEFPUOP_CONV(evfsctsiz);
6654/* Comparison */
6655GEN_SPEOP_COMP(evfscmpgt);
6656GEN_SPEOP_COMP(evfscmplt);
6657GEN_SPEOP_COMP(evfscmpeq);
6658GEN_SPEOP_COMP(evfststgt);
6659GEN_SPEOP_COMP(evfststlt);
6660GEN_SPEOP_COMP(evfststeq);
6661
6662/* Opcodes definitions */
6663GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6664GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6665GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6666GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6667GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6668GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6669GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6670GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6671GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6672GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6673GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6674GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6675GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6676GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6677
6678/* Single precision floating-point operations */
6679/* Arithmetic */
6680GEN_SPEOP_ARITH2(efsadd);
6681GEN_SPEOP_ARITH2(efssub);
6682GEN_SPEOP_ARITH2(efsmul);
6683GEN_SPEOP_ARITH2(efsdiv);
6684GEN_SPEOP_ARITH1(efsabs);
6685GEN_SPEOP_ARITH1(efsnabs);
6686GEN_SPEOP_ARITH1(efsneg);
6687/* Conversion */
6688GEN_SPEFPUOP_CONV(efscfui);
6689GEN_SPEFPUOP_CONV(efscfsi);
6690GEN_SPEFPUOP_CONV(efscfuf);
6691GEN_SPEFPUOP_CONV(efscfsf);
6692GEN_SPEFPUOP_CONV(efsctui);
6693GEN_SPEFPUOP_CONV(efsctsi);
6694GEN_SPEFPUOP_CONV(efsctuf);
6695GEN_SPEFPUOP_CONV(efsctsf);
6696GEN_SPEFPUOP_CONV(efsctuiz);
6697GEN_SPEFPUOP_CONV(efsctsiz);
6698GEN_SPEFPUOP_CONV(efscfd);
6699/* Comparison */
6700GEN_SPEOP_COMP(efscmpgt);
6701GEN_SPEOP_COMP(efscmplt);
6702GEN_SPEOP_COMP(efscmpeq);
6703GEN_SPEOP_COMP(efststgt);
6704GEN_SPEOP_COMP(efststlt);
6705GEN_SPEOP_COMP(efststeq);
6706
6707/* Opcodes definitions */
6708GEN_SPE(efsadd, efssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6709GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6710GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6711GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6712GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6713GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6714GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6715GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6716GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6717GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
6718GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6719GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6720GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6721
6722/* Double precision floating-point operations */
6723/* Arithmetic */
6724GEN_SPEOP_ARITH2(efdadd);
6725GEN_SPEOP_ARITH2(efdsub);
6726GEN_SPEOP_ARITH2(efdmul);
6727GEN_SPEOP_ARITH2(efddiv);
6728GEN_SPEOP_ARITH1(efdabs);
6729GEN_SPEOP_ARITH1(efdnabs);
6730GEN_SPEOP_ARITH1(efdneg);
6731/* Conversion */
6732
6733GEN_SPEFPUOP_CONV(efdcfui);
6734GEN_SPEFPUOP_CONV(efdcfsi);
6735GEN_SPEFPUOP_CONV(efdcfuf);
6736GEN_SPEFPUOP_CONV(efdcfsf);
6737GEN_SPEFPUOP_CONV(efdctui);
6738GEN_SPEFPUOP_CONV(efdctsi);
6739GEN_SPEFPUOP_CONV(efdctuf);
6740GEN_SPEFPUOP_CONV(efdctsf);
6741GEN_SPEFPUOP_CONV(efdctuiz);
6742GEN_SPEFPUOP_CONV(efdctsiz);
6743GEN_SPEFPUOP_CONV(efdcfs);
6744GEN_SPEFPUOP_CONV(efdcfuid);
6745GEN_SPEFPUOP_CONV(efdcfsid);
6746GEN_SPEFPUOP_CONV(efdctuidz);
6747GEN_SPEFPUOP_CONV(efdctsidz);
6748/* Comparison */
6749GEN_SPEOP_COMP(efdcmpgt);
6750GEN_SPEOP_COMP(efdcmplt);
6751GEN_SPEOP_COMP(efdcmpeq);
6752GEN_SPEOP_COMP(efdtstgt);
6753GEN_SPEOP_COMP(efdtstlt);
6754GEN_SPEOP_COMP(efdtsteq);
6755
6756/* Opcodes definitions */
6757GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6758GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6759GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6760GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6761GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6762GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6763GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6764GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6765GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6766GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6767GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6768GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6769GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6770GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6771GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6772GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6773
79aceca5
FB		 6774/* End opcode list */
6775GEN_OPCODE_MARK(end);
6776
3fc6c082 6777#include "translate_init.c"
0411a972 6778#include "helper_regs.h"
79aceca5 6779
9a64fbe4 6780/*****************************************************************************/
3fc6c082 6781/* Misc PowerPC helpers */
36081602
JM		 6782void cpu_dump_state (CPUState *env, FILE *f,
6783 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6784 int flags)
79aceca5 6785{
3fc6c082
FB		 6786#if defined(TARGET_PPC64) || 1
6787#define FILL ""
3fc6c082
FB		 6788#define RGPL 4
6789#define RFPL 4
6790#else
6791#define FILL " "
3fc6c082
FB		 6792#define RGPL 8
6793#define RFPL 4
6794#endif
6795
79aceca5
FB		 6796 int i;
6797
077fc206
JM		 6798 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6799 env->nip, env->lr, env->ctr, hreg_load_xer(env));
6800 cpu_fprintf(f, "MSR " REGX FILL " HID0 " REGX FILL " HF " REGX FILL
6801 " idx %d\n",
6802 env->msr, env->hflags, env->spr[SPR_HID0], env->mmu_idx);
d9bce9d9 6803#if !defined(NO_TIMER_DUMP)
077fc206 6804 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6805#if !defined(CONFIG_USER_ONLY)
6806 "DECR %08x"
6807#endif
6808 "\n",
077fc206 6809 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6810#if !defined(CONFIG_USER_ONLY)
6811 , cpu_ppc_load_decr(env)
6812#endif
6813 );
077fc206 6814#endif
76a66253 6815 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6816 if ((i & (RGPL - 1)) == 0)
6817 cpu_fprintf(f, "GPR%02d", i);
a750fc0b 6818 cpu_fprintf(f, " " REGX, (target_ulong)env->gpr[i]);
3fc6c082 6819 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6820 cpu_fprintf(f, "\n");
76a66253 6821 }
3fc6c082 6822 cpu_fprintf(f, "CR ");
76a66253 6823 for (i = 0; i < 8; i++)
7fe48483
FB		 6824 cpu_fprintf(f, "%01x", env->crf[i]);
6825 cpu_fprintf(f, " [");
76a66253
JM		 6826 for (i = 0; i < 8; i++) {
6827 char a = '-';
6828 if (env->crf[i] & 0x08)
6829 a = 'L';
6830 else if (env->crf[i] & 0x04)
6831 a = 'G';
6832 else if (env->crf[i] & 0x02)
6833 a = 'E';
7fe48483 6834 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6835 }
3fc6c082
FB		 6836 cpu_fprintf(f, " ] " FILL "RES " REGX "\n", env->reserve);
6837 for (i = 0; i < 32; i++) {
6838 if ((i & (RFPL - 1)) == 0)
6839 cpu_fprintf(f, "FPR%02d", i);
26a76461 6840 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6841 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6842 cpu_fprintf(f, "\n");
79aceca5 6843 }
f2e63a42 6844#if !defined(CONFIG_USER_ONLY)
077fc206 6845 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " SDR1 " REGX "\n",
3fc6c082 6846 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6847#endif
79aceca5 6848
3fc6c082
FB		 6849#undef RGPL
6850#undef RFPL
6851#undef FILL
79aceca5
FB		 6852}
6853
76a66253
JM		 6854void cpu_dump_statistics (CPUState *env, FILE*f,
6855 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6856 int flags)
6857{
6858#if defined(DO_PPC_STATISTICS)
6859 opc_handler_t **t1, **t2, **t3, *handler;
6860 int op1, op2, op3;
6861
6862 t1 = env->opcodes;
6863 for (op1 = 0; op1 < 64; op1++) {
6864 handler = t1[op1];
6865 if (is_indirect_opcode(handler)) {
6866 t2 = ind_table(handler);
6867 for (op2 = 0; op2 < 32; op2++) {
6868 handler = t2[op2];
6869 if (is_indirect_opcode(handler)) {
6870 t3 = ind_table(handler);
6871 for (op3 = 0; op3 < 32; op3++) {
6872 handler = t3[op3];
6873 if (handler->count == 0)
6874 continue;
6875 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6876 "%016llx %lld\n",
6877 op1, op2, op3, op1, (op3 << 5) | op2,
6878 handler->oname,
6879 handler->count, handler->count);
6880 }
6881 } else {
6882 if (handler->count == 0)
6883 continue;
6884 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6885 "%016llx %lld\n",
6886 op1, op2, op1, op2, handler->oname,
6887 handler->count, handler->count);
6888 }
6889 }
6890 } else {
6891 if (handler->count == 0)
6892 continue;
6893 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6894 op1, op1, handler->oname,
6895 handler->count, handler->count);
6896 }
6897 }
6898#endif
6899}
6900
9a64fbe4 6901/*****************************************************************************/
b068d6a7
JM		 6902static always_inline int gen_intermediate_code_internal (CPUState *env,
6903 TranslationBlock *tb,
6904 int search_pc)
79aceca5 6905{
9fddaa0c 6906 DisasContext ctx, *ctxp = &ctx;
79aceca5 6907 opc_handler_t **table, *handler;
0fa85d43 6908 target_ulong pc_start;
79aceca5 6909 uint16_t *gen_opc_end;
056401ea 6910 int supervisor, little_endian;
d26bfc9a 6911 int single_step, branch_step;
79aceca5 6912 int j, lj = -1;
79aceca5
FB		 6913
6914 pc_start = tb->pc;
6915 gen_opc_ptr = gen_opc_buf;
6916 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
6917 gen_opparam_ptr = gen_opparam_buf;
7c58044c
JM		 6918#if defined(OPTIMIZE_FPRF_UPDATE)
6919 gen_fprf_ptr = gen_fprf_buf;
6920#endif
c53be334 6921 nb_gen_labels = 0;
046d6672 6922 ctx.nip = pc_start;
79aceca5 6923 ctx.tb = tb;
e1833e1f 6924 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6925 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6926 supervisor = env->mmu_idx;
6927#if !defined(CONFIG_USER_ONLY)
2857068e 6928 ctx.supervisor = supervisor;
d9bce9d9 6929#endif
056401ea 6930 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6931#if defined(TARGET_PPC64)
6932 ctx.sf_mode = msr_sf;
056401ea 6933 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6934#else
056401ea 6935 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6936#endif
d63001d1 6937 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6938 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6939 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6940 ctx.spe_enabled = msr_spe;
6941 else
6942 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6943 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6944 ctx.altivec_enabled = msr_vr;
6945 else
6946 ctx.altivec_enabled = 0;
d26bfc9a
JM		 6947 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6948 single_step = 1;
6949 else
6950 single_step = 0;
6951 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6952 branch_step = 1;
6953 else
6954 branch_step = 0;
b33c17e1 6955 ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;
3fc6c082 6956#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6957 /* Single step trace mode */
6958 msr_se = 1;
6959#endif
6960 /* Set env in case of segfault during code fetch */
e1833e1f 6961 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6962 if (unlikely(env->nb_breakpoints > 0)) {
6963 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6964 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6965 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6966 gen_op_debug();
6967 break;
6968 }
6969 }
6970 }
76a66253 6971 if (unlikely(search_pc)) {
79aceca5
FB		 6972 j = gen_opc_ptr - gen_opc_buf;
6973 if (lj < j) {
6974 lj++;
6975 while (lj < j)
6976 gen_opc_instr_start[lj++] = 0;
046d6672 6977 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 6978 gen_opc_instr_start[lj] = 1;
6979 }
6980 }
9fddaa0c
FB		 6981#if defined PPC_DEBUG_DISAS
6982 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6983 fprintf(logfile, "----------------\n");
1b9eb036 6984 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6985 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6986 }
6987#endif
056401ea
JM		 6988 if (unlikely(little_endian)) {
6989 ctx.opcode = bswap32(ldl_code(ctx.nip));
6990 } else {
6991 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6992 }
9fddaa0c
FB		 6993#if defined PPC_DEBUG_DISAS
6994 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6995 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6996 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6997 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6998 }
6999#endif
046d6672 7000 ctx.nip += 4;
3fc6c082 7001 table = env->opcodes;
79aceca5
FB		 7002 handler = table[opc1(ctx.opcode)];
7003 if (is_indirect_opcode(handler)) {
7004 table = ind_table(handler);
7005 handler = table[opc2(ctx.opcode)];
7006 if (is_indirect_opcode(handler)) {
7007 table = ind_table(handler);
7008 handler = table[opc3(ctx.opcode)];
7009 }
7010 }
7011 /* Is opcode *REALLY* valid ? */
76a66253 7012 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 7013 if (loglevel != 0) {
76a66253 7014 fprintf(logfile, "invalid/unsupported opcode: "
1b9eb036 7015 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
76a66253 7016 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7017 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 7018 } else {
7019 printf("invalid/unsupported opcode: "
1b9eb036 7020 "%02x - %02x - %02x (%08x) 0x" ADDRX " %d\n",
4b3686fa 7021 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 7022 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 7023 }
76a66253
JM		 7024 } else {
7025 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 7026 if (loglevel != 0) {
79aceca5 7027 fprintf(logfile, "invalid bits: %08x for opcode: "
e1833e1f 7028 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
79aceca5
FB		 7029 ctx.opcode & handler->inval, opc1(ctx.opcode),
7030 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7031 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 7032 } else {
7033 printf("invalid bits: %08x for opcode: "
e1833e1f 7034 "%02x - %02x - %02x (%08x) 0x" ADDRX "\n",
76a66253
JM		 7035 ctx.opcode & handler->inval, opc1(ctx.opcode),
7036 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 7037 ctx.opcode, ctx.nip - 4);
76a66253 7038 }
e1833e1f 7039 GEN_EXCP_INVAL(ctxp);
4b3686fa 7040 break;
79aceca5 7041 }
79aceca5 7042 }
4b3686fa 7043 (*(handler->handler))(&ctx);
76a66253
JM		 7044#if defined(DO_PPC_STATISTICS)
7045 handler->count++;
7046#endif
9a64fbe4 7047 /* Check trace mode exceptions */
d26bfc9a
JM		 7048 if (unlikely(branch_step != 0 &&
7049 ctx.exception == POWERPC_EXCP_BRANCH)) {
7050 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
7051 } else if (unlikely(single_step != 0 &&
7052 (ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
7053 (ctx.nip & 0xFC) != 0x04) &&
417bf010 7054 ctx.exception != POWERPC_SYSCALL &&
d26bfc9a 7055 ctx.exception != POWERPC_EXCP_TRAP)) {
e1833e1f 7056 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a
JM		 7057 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
7058 (env->singlestep_enabled))) {
7059 /* if we reach a page boundary or are single stepping, stop
7060 * generation
7061 */
8dd4983c 7062 break;
76a66253 7063 }
3fc6c082
FB		 7064#if defined (DO_SINGLE_STEP)
7065 break;
7066#endif
7067 }
e1833e1f 7068 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 7069 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 7070 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
76a66253
JM		 7071 gen_op_reset_T0();
7072 /* Generate the return instruction */
7073 gen_op_exit_tb();
9a64fbe4 7074 }
79aceca5 7075 *gen_opc_ptr = INDEX_op_end;
76a66253 7076 if (unlikely(search_pc)) {
9a64fbe4
FB		 7077 j = gen_opc_ptr - gen_opc_buf;
7078 lj++;
7079 while (lj <= j)
7080 gen_opc_instr_start[lj++] = 0;
9a64fbe4 7081 } else {
046d6672 7082 tb->size = ctx.nip - pc_start;
9a64fbe4 7083 }
d9bce9d9 7084#if defined(DEBUG_DISAS)
9fddaa0c 7085 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 7086 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 7087 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 7088 }
7089 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 7090 int flags;
237c0af0 7091 flags = env->bfd_mach;
056401ea 7092 flags |= little_endian << 16;
0fa85d43 7093 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 7094 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 7095 fprintf(logfile, "\n");
9fddaa0c
FB		 7096 }
7097 if (loglevel & CPU_LOG_TB_OP) {
79aceca5
FB		 7098 fprintf(logfile, "OP:\n");
7099 dump_ops(gen_opc_buf, gen_opparam_buf);
7100 fprintf(logfile, "\n");
7101 }
7102#endif
79aceca5
FB		 7103 return 0;
7104}
7105
9a64fbe4 7106int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 7107{
7108 return gen_intermediate_code_internal(env, tb, 0);
7109}
7110
9a64fbe4 7111int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 7112{
7113 return gen_intermediate_code_internal(env, tb, 1);
7114}
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