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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
79aceca5 31
a750fc0b 32/* Include definitions for instructions classes and implementations flags */
79aceca5 33//#define DO_SINGLE_STEP
9fddaa0c 34//#define PPC_DEBUG_DISAS
a496775f 35//#define DEBUG_MEMORY_ACCESSES
76a66253 36//#define DO_PPC_STATISTICS
7c58044c 37//#define OPTIMIZE_FPRF_UPDATE
79aceca5 38
a750fc0b
JM		 39/*****************************************************************************/
40/* Code translation helpers */
c53be334 41
7c58044c
JM		 42#if defined(OPTIMIZE_FPRF_UPDATE)
43static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
44static uint16_t **gen_fprf_ptr;
45#endif
79aceca5 46
b068d6a7 47static always_inline void gen_set_T0 (target_ulong val)
d9bce9d9
JM		 48{
49#if defined(TARGET_PPC64)
50 if (val >> 32)
51 gen_op_set_T0_64(val >> 32, val);
52 else
53#endif
54 gen_op_set_T0(val);
55}
56
b068d6a7 57static always_inline void gen_set_T1 (target_ulong val)
d9bce9d9
JM		 58{
59#if defined(TARGET_PPC64)
60 if (val >> 32)
61 gen_op_set_T1_64(val >> 32, val);
62 else
63#endif
64 gen_op_set_T1(val);
65}
66
67#define GEN8(func, NAME) \
9a64fbe4
FB		 68static GenOpFunc *NAME ## _table [8] = { \
69NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71}; \
b068d6a7 72static always_inline void func (int n) \
9a64fbe4
FB		 73{ \
74 NAME ## _table[n](); \
75}
76
77#define GEN16(func, NAME) \
78static GenOpFunc *NAME ## _table [16] = { \
79NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
80NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
81NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
82NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
83}; \
b068d6a7 84static always_inline void func (int n) \
9a64fbe4
FB		 85{ \
86 NAME ## _table[n](); \
28b6751f
FB		 87}
88
d9bce9d9 89#define GEN32(func, NAME) \
9a64fbe4
FB		 90static GenOpFunc *NAME ## _table [32] = { \
91NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
92NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
93NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
94NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
95NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
96NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
97NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
98NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
99}; \
b068d6a7 100static always_inline void func (int n) \
9a64fbe4
FB		 101{ \
102 NAME ## _table[n](); \
103}
104
105/* Condition register moves */
106GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
107GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
108GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
fc0d441e 109#if 0 // Unused
9a64fbe4 110GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
fc0d441e 111#endif
28b6751f 112
9a64fbe4
FB		 113/* General purpose registers moves */
114GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
115GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
116GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
117
118GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
119GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
76a66253 120#if 0 // unused
9a64fbe4 121GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
76a66253 122#endif
28b6751f 123
fb0eaffc
FB		 124/* floating point registers moves */
125GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
126GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
127GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
128GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
129GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
76a66253 130#if 0 // unused
fb0eaffc 131GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
76a66253 132#endif
79aceca5
FB		 133
134/* internal defines */
135typedef struct DisasContext {
136 struct TranslationBlock *tb;
0fa85d43 137 target_ulong nip;
79aceca5 138 uint32_t opcode;
9a64fbe4 139 uint32_t exception;
3cc62370
FB		 140 /* Routine used to access memory */
141 int mem_idx;
142 /* Translation flags */
9a64fbe4 143#if !defined(CONFIG_USER_ONLY)
79aceca5 144 int supervisor;
d9bce9d9
JM		 145#endif
146#if defined(TARGET_PPC64)
147 int sf_mode;
9a64fbe4 148#endif
3cc62370 149 int fpu_enabled;
a9d9eb8f 150 int altivec_enabled;
0487d6a8 151 int spe_enabled;
3fc6c082 152 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 153 int singlestep_enabled;
d63001d1 154 int dcache_line_size;
79aceca5
FB		 155} DisasContext;
156
3fc6c082 157struct opc_handler_t {
79aceca5
FB		 158 /* invalid bits */
159 uint32_t inval;
9a64fbe4 160 /* instruction type */
0487d6a8 161 uint64_t type;
79aceca5
FB		 162 /* handler */
163 void (*handler)(DisasContext *ctx);
a750fc0b 164#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
76a66253 165 const unsigned char *oname;
a750fc0b
JM		 166#endif
167#if defined(DO_PPC_STATISTICS)
76a66253
JM		 168 uint64_t count;
169#endif
3fc6c082 170};
79aceca5 171
b068d6a7 172static always_inline void gen_set_Rc0 (DisasContext *ctx)
76a66253 173{
d9bce9d9
JM		 174#if defined(TARGET_PPC64)
175 if (ctx->sf_mode)
176 gen_op_cmpi_64(0);
177 else
178#endif
179 gen_op_cmpi(0);
76a66253
JM		 180 gen_op_set_Rc0();
181}
182
7c58044c
JM		 183static always_inline void gen_reset_fpstatus (void)
184{
185#ifdef CONFIG_SOFTFLOAT
186 gen_op_reset_fpstatus();
187#endif
188}
189
190static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
191{
192 if (set_fprf != 0) {
193 /* This case might be optimized later */
194#if defined(OPTIMIZE_FPRF_UPDATE)
195 *gen_fprf_ptr++ = gen_opc_ptr;
196#endif
197 gen_op_compute_fprf(1);
198 if (unlikely(set_rc))
199 gen_op_store_T0_crf(1);
200 gen_op_float_check_status();
201 } else if (unlikely(set_rc)) {
202 /* We always need to compute fpcc */
203 gen_op_compute_fprf(0);
204 gen_op_store_T0_crf(1);
205 if (set_fprf)
206 gen_op_float_check_status();
207 }
208}
209
210static always_inline void gen_optimize_fprf (void)
211{
212#if defined(OPTIMIZE_FPRF_UPDATE)
213 uint16_t **ptr;
214
215 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
216 *ptr = INDEX_op_nop1;
217 gen_fprf_ptr = gen_fprf_buf;
218#endif
219}
220
b068d6a7 221static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 222{
223#if defined(TARGET_PPC64)
224 if (ctx->sf_mode)
225 gen_op_update_nip_64(nip >> 32, nip);
226 else
227#endif
228 gen_op_update_nip(nip);
229}
230
e1833e1f 231#define GEN_EXCP(ctx, excp, error) \
79aceca5 232do { \
e1833e1f 233 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 234 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 235 } \
236 gen_op_raise_exception_err((excp), (error)); \
237 ctx->exception = (excp); \
79aceca5
FB		 238} while (0)
239
e1833e1f
JM		 240#define GEN_EXCP_INVAL(ctx) \
241GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
242 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 243
e1833e1f
JM		 244#define GEN_EXCP_PRIVOPC(ctx) \
245GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
246 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 247
e1833e1f
JM		 248#define GEN_EXCP_PRIVREG(ctx) \
249GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
250 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
251
252#define GEN_EXCP_NO_FP(ctx) \
253GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
254
255#define GEN_EXCP_NO_AP(ctx) \
256GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 257
a9d9eb8f
JM		 258#define GEN_EXCP_NO_VR(ctx) \
259GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
260
f24e5695 261/* Stop translation */
b068d6a7 262static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 263{
d9bce9d9 264 gen_update_nip(ctx, ctx->nip);
e1833e1f 265 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 266}
267
f24e5695 268/* No need to update nip here, as execution flow will change */
b068d6a7 269static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 270{
e1833e1f 271 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 272}
273
79aceca5
FB		 274#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
275static void gen_##name (DisasContext *ctx); \
276GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
277static void gen_##name (DisasContext *ctx)
278
c7697e1f
JM		 279#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
280static void gen_##name (DisasContext *ctx); \
281GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
282static void gen_##name (DisasContext *ctx)
283
79aceca5
FB		 284typedef struct opcode_t {
285 unsigned char opc1, opc2, opc3;
18fba28c
FB		 286#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */
287 unsigned char pad[5];
288#else
289 unsigned char pad[1];
290#endif
79aceca5 291 opc_handler_t handler;
3fc6c082 292 const unsigned char *oname;
79aceca5
FB		 293} opcode_t;
294
a750fc0b 295/*****************************************************************************/
79aceca5
FB		 296/*** Instruction decoding ***/
297#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 298static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 299{ \
300 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
301}
302
303#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 304static always_inline int32_t name (uint32_t opcode) \
79aceca5 305{ \
18fba28c 306 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 307}
308
309/* Opcode part 1 */
310EXTRACT_HELPER(opc1, 26, 6);
311/* Opcode part 2 */
312EXTRACT_HELPER(opc2, 1, 5);
313/* Opcode part 3 */
314EXTRACT_HELPER(opc3, 6, 5);
315/* Update Cr0 flags */
316EXTRACT_HELPER(Rc, 0, 1);
317/* Destination */
318EXTRACT_HELPER(rD, 21, 5);
319/* Source */
320EXTRACT_HELPER(rS, 21, 5);
321/* First operand */
322EXTRACT_HELPER(rA, 16, 5);
323/* Second operand */
324EXTRACT_HELPER(rB, 11, 5);
325/* Third operand */
326EXTRACT_HELPER(rC, 6, 5);
327/*** Get CRn ***/
328EXTRACT_HELPER(crfD, 23, 3);
329EXTRACT_HELPER(crfS, 18, 3);
330EXTRACT_HELPER(crbD, 21, 5);
331EXTRACT_HELPER(crbA, 16, 5);
332EXTRACT_HELPER(crbB, 11, 5);
333/* SPR / TBL */
3fc6c082 334EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 335static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 336{
337 uint32_t sprn = _SPR(opcode);
338
339 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
340}
79aceca5
FB		 341/*** Get constants ***/
342EXTRACT_HELPER(IMM, 12, 8);
343/* 16 bits signed immediate value */
344EXTRACT_SHELPER(SIMM, 0, 16);
345/* 16 bits unsigned immediate value */
346EXTRACT_HELPER(UIMM, 0, 16);
347/* Bit count */
348EXTRACT_HELPER(NB, 11, 5);
349/* Shift count */
350EXTRACT_HELPER(SH, 11, 5);
351/* Mask start */
352EXTRACT_HELPER(MB, 6, 5);
353/* Mask end */
354EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 355/* Trap operand */
356EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 357
358EXTRACT_HELPER(CRM, 12, 8);
359EXTRACT_HELPER(FM, 17, 8);
360EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 361EXTRACT_HELPER(FPIMM, 20, 4);
362
79aceca5
FB		 363/*** Jump target decoding ***/
364/* Displacement */
365EXTRACT_SHELPER(d, 0, 16);
366/* Immediate address */
b068d6a7 367static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 368{
369 return (opcode >> 0) & 0x03FFFFFC;
370}
371
b068d6a7 372static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 373{
374 return (opcode >> 0) & 0xFFFC;
375}
376
377EXTRACT_HELPER(BO, 21, 5);
378EXTRACT_HELPER(BI, 16, 5);
379/* Absolute/relative address */
380EXTRACT_HELPER(AA, 1, 1);
381/* Link */
382EXTRACT_HELPER(LK, 0, 1);
383
384/* Create a mask between <start> and <end> bits */
b068d6a7 385static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 386{
76a66253 387 target_ulong ret;
79aceca5 388
76a66253
JM		 389#if defined(TARGET_PPC64)
390 if (likely(start == 0)) {
6f2d8978 391 ret = UINT64_MAX << (63 - end);
76a66253 392 } else if (likely(end == 63)) {
6f2d8978 393 ret = UINT64_MAX >> start;
76a66253
JM		 394 }
395#else
396 if (likely(start == 0)) {
6f2d8978 397 ret = UINT32_MAX << (31 - end);
76a66253 398 } else if (likely(end == 31)) {
6f2d8978 399 ret = UINT32_MAX >> start;
76a66253
JM		 400 }
401#endif
402 else {
403 ret = (((target_ulong)(-1ULL)) >> (start)) ^
404 (((target_ulong)(-1ULL) >> (end)) >> 1);
405 if (unlikely(start > end))
406 return ~ret;
407 }
79aceca5
FB		 408
409 return ret;
410}
411
a750fc0b
JM		 412/*****************************************************************************/
413/* PowerPC Instructions types definitions */
414enum {
1b413d55 415 PPC_NONE = 0x0000000000000000ULL,
12de9a39 416 /* PowerPC base instructions set */
1b413d55
JM		 417 PPC_INSNS_BASE = 0x0000000000000001ULL,
418 /* integer operations instructions */
a750fc0b 419#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 420 /* flow control instructions */
a750fc0b 421#define PPC_FLOW PPC_INSNS_BASE
1b413d55 422 /* virtual memory instructions */
a750fc0b 423#define PPC_MEM PPC_INSNS_BASE
1b413d55 424 /* ld/st with reservation instructions */
a750fc0b 425#define PPC_RES PPC_INSNS_BASE
1b413d55 426 /* spr/msr access instructions */
a750fc0b 427#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 428 /* Deprecated instruction sets */
429 /* Original POWER instruction set */
f610349f 430 PPC_POWER = 0x0000000000000002ULL,
1b413d55 431 /* POWER2 instruction set extension */
f610349f 432 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 433 /* Power RTC support */
f610349f 434 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 435 /* Power-to-PowerPC bridge (601) */
f610349f 436 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 437 /* 64 bits PowerPC instruction set */
f610349f 438 PPC_64B = 0x0000000000000020ULL,
1b413d55 439 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 440 PPC_64BX = 0x0000000000000040ULL,
1b413d55 441 /* 64 bits hypervisor extensions */
f610349f 442 PPC_64H = 0x0000000000000080ULL,
1b413d55 443 /* New wait instruction (PowerPC 2.0x) */
f610349f 444 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 445 /* Time base mftb instruction */
f610349f 446 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 447
448 /* Fixed-point unit extensions */
449 /* PowerPC 602 specific */
f610349f 450 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 451 /* isel instruction */
452 PPC_ISEL = 0x0000000000000800ULL,
453 /* popcntb instruction */
454 PPC_POPCNTB = 0x0000000000001000ULL,
455 /* string load / store */
456 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 457
458 /* Floating-point unit extensions */
459 /* Optional floating point instructions */
460 PPC_FLOAT = 0x0000000000010000ULL,
461 /* New floating-point extensions (PowerPC 2.0x) */
462 PPC_FLOAT_EXT = 0x0000000000020000ULL,
463 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
464 PPC_FLOAT_FRES = 0x0000000000080000ULL,
465 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
466 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
467 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
468 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
469
470 /* Vector/SIMD extensions */
471 /* Altivec support */
472 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 473 /* PowerPC 2.03 SPE extension */
05332d70 474 PPC_SPE = 0x0000000002000000ULL,
1b413d55 475 /* PowerPC 2.03 SPE floating-point extension */
05332d70 476 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 477
12de9a39 478 /* Optional memory control instructions */
1b413d55
JM		 479 PPC_MEM_TLBIA = 0x0000000010000000ULL,
480 PPC_MEM_TLBIE = 0x0000000020000000ULL,
481 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
482 /* sync instruction */
483 PPC_MEM_SYNC = 0x0000000080000000ULL,
484 /* eieio instruction */
485 PPC_MEM_EIEIO = 0x0000000100000000ULL,
486
487 /* Cache control instructions */
c8623f2e 488 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 489 /* icbi instruction */
05332d70 490 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 491 /* dcbz instruction with fixed cache line size */
05332d70 492 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 493 /* dcbz instruction with tunable cache line size */
05332d70 494 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 495 /* dcba instruction */
05332d70
JM		 496 PPC_CACHE_DCBA = 0x0000002000000000ULL,
497 /* Freescale cache locking instructions */
498 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 499
500 /* MMU related extensions */
501 /* external control instructions */
05332d70 502 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 503 /* segment register access instructions */
05332d70 504 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 505 /* PowerPC 6xx TLB management instructions */
05332d70 506 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 507 /* PowerPC 74xx TLB management instructions */
05332d70 508 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 509 /* PowerPC 40x TLB management instructions */
05332d70 510 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 511 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 512 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 513 /* SLB management */
05332d70 514 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 515
12de9a39 516 /* Embedded PowerPC dedicated instructions */
05332d70 517 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 518 /* PowerPC 40x exception model */
05332d70 519 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 520 /* PowerPC 405 Mac instructions */
05332d70 521 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 522 /* PowerPC 440 specific instructions */
05332d70 523 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 524 /* BookE (embedded) PowerPC specification */
05332d70
JM		 525 PPC_BOOKE = 0x0010000000000000ULL,
526 /* mfapidi instruction */
527 PPC_MFAPIDI = 0x0020000000000000ULL,
528 /* tlbiva instruction */
529 PPC_TLBIVA = 0x0040000000000000ULL,
530 /* tlbivax instruction */
531 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 532 /* PowerPC 4xx dedicated instructions */
05332d70 533 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 534 /* PowerPC 40x ibct instructions */
05332d70 535 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 536 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 537 PPC_RFMCI = 0x0400000000000000ULL,
538 /* rfdi instruction */
539 PPC_RFDI = 0x0800000000000000ULL,
540 /* DCR accesses */
541 PPC_DCR = 0x1000000000000000ULL,
542 /* DCR extended accesse */
543 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 544 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 545 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 546};
547
548/*****************************************************************************/
549/* PowerPC instructions table */
3fc6c082
FB		 550#if HOST_LONG_BITS == 64
551#define OPC_ALIGN 8
552#else
553#define OPC_ALIGN 4
554#endif
1b039c09 555#if defined(__APPLE__)
d9bce9d9 556#define OPCODES_SECTION \
3fc6c082 557 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 558#else
d9bce9d9 559#define OPCODES_SECTION \
3fc6c082 560 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 561#endif
562
76a66253 563#if defined(DO_PPC_STATISTICS)
79aceca5 564#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 565OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 566 .opc1 = op1, \
567 .opc2 = op2, \
568 .opc3 = op3, \
18fba28c 569 .pad = { 0, }, \
79aceca5
FB		 570 .handler = { \
571 .inval = invl, \
9a64fbe4 572 .type = _typ, \
79aceca5 573 .handler = &gen_##name, \
76a66253 574 .oname = stringify(name), \
79aceca5 575 }, \
3fc6c082 576 .oname = stringify(name), \
79aceca5 577}
c7697e1f
JM		 578#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
579OPCODES_SECTION opcode_t opc_##name = { \
580 .opc1 = op1, \
581 .opc2 = op2, \
582 .opc3 = op3, \
583 .pad = { 0, }, \
584 .handler = { \
585 .inval = invl, \
586 .type = _typ, \
587 .handler = &gen_##name, \
588 .oname = onam, \
589 }, \
590 .oname = onam, \
591}
76a66253
JM		 592#else
593#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
594OPCODES_SECTION opcode_t opc_##name = { \
595 .opc1 = op1, \
596 .opc2 = op2, \
597 .opc3 = op3, \
598 .pad = { 0, }, \
599 .handler = { \
600 .inval = invl, \
601 .type = _typ, \
602 .handler = &gen_##name, \
603 }, \
604 .oname = stringify(name), \
605}
c7697e1f
JM		 606#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
607OPCODES_SECTION opcode_t opc_##name = { \
608 .opc1 = op1, \
609 .opc2 = op2, \
610 .opc3 = op3, \
611 .pad = { 0, }, \
612 .handler = { \
613 .inval = invl, \
614 .type = _typ, \
615 .handler = &gen_##name, \
616 }, \
617 .oname = onam, \
618}
76a66253 619#endif
79aceca5
FB		 620
621#define GEN_OPCODE_MARK(name) \
18fba28c 622OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 623 .opc1 = 0xFF, \
624 .opc2 = 0xFF, \
625 .opc3 = 0xFF, \
18fba28c 626 .pad = { 0, }, \
79aceca5
FB		 627 .handler = { \
628 .inval = 0x00000000, \
9a64fbe4 629 .type = 0x00, \
79aceca5
FB		 630 .handler = NULL, \
631 }, \
3fc6c082 632 .oname = stringify(name), \
79aceca5
FB		 633}
634
635/* Start opcode list */
636GEN_OPCODE_MARK(start);
637
638/* Invalid instruction */
9a64fbe4
FB		 639GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
640{
e1833e1f 641 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 642}
643
79aceca5
FB		 644static opc_handler_t invalid_handler = {
645 .inval = 0xFFFFFFFF,
9a64fbe4 646 .type = PPC_NONE,
79aceca5
FB		 647 .handler = gen_invalid,
648};
649
650/*** Integer arithmetic ***/
d9bce9d9
JM		 651#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
652GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5
FB		 653{ \
654 gen_op_load_gpr_T0(rA(ctx->opcode)); \
655 gen_op_load_gpr_T1(rB(ctx->opcode)); \
656 gen_op_##name(); \
79aceca5 657 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 658 if (unlikely(Rc(ctx->opcode) != 0)) \
659 gen_set_Rc0(ctx); \
79aceca5
FB		 660}
661
d9bce9d9
JM		 662#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
663GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5
FB		 664{ \
665 gen_op_load_gpr_T0(rA(ctx->opcode)); \
666 gen_op_load_gpr_T1(rB(ctx->opcode)); \
667 gen_op_##name(); \
79aceca5 668 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 669 if (unlikely(Rc(ctx->opcode) != 0)) \
670 gen_set_Rc0(ctx); \
79aceca5
FB		 671}
672
d9bce9d9
JM		 673#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
674GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5
FB		 675{ \
676 gen_op_load_gpr_T0(rA(ctx->opcode)); \
677 gen_op_##name(); \
79aceca5 678 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 679 if (unlikely(Rc(ctx->opcode) != 0)) \
680 gen_set_Rc0(ctx); \
79aceca5 681}
d9bce9d9
JM		 682#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
683GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5
FB		 684{ \
685 gen_op_load_gpr_T0(rA(ctx->opcode)); \
686 gen_op_##name(); \
79aceca5 687 gen_op_store_T0_gpr(rD(ctx->opcode)); \
76a66253
JM		 688 if (unlikely(Rc(ctx->opcode) != 0)) \
689 gen_set_Rc0(ctx); \
79aceca5
FB		 690}
691
692/* Two operands arithmetic functions */
d9bce9d9
JM		 693#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
694__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
695__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
696
697/* Two operands arithmetic functions with no overflow allowed */
698#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
699__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
700
701/* One operand arithmetic functions */
702#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
703__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
704__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
705
706#if defined(TARGET_PPC64)
707#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
708GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
709{ \
710 gen_op_load_gpr_T0(rA(ctx->opcode)); \
711 gen_op_load_gpr_T1(rB(ctx->opcode)); \
712 if (ctx->sf_mode) \
713 gen_op_##name##_64(); \
714 else \
715 gen_op_##name(); \
716 gen_op_store_T0_gpr(rD(ctx->opcode)); \
717 if (unlikely(Rc(ctx->opcode) != 0)) \
718 gen_set_Rc0(ctx); \
719}
720
721#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
722GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
723{ \
724 gen_op_load_gpr_T0(rA(ctx->opcode)); \
725 gen_op_load_gpr_T1(rB(ctx->opcode)); \
726 if (ctx->sf_mode) \
727 gen_op_##name##_64(); \
728 else \
729 gen_op_##name(); \
730 gen_op_store_T0_gpr(rD(ctx->opcode)); \
731 if (unlikely(Rc(ctx->opcode) != 0)) \
732 gen_set_Rc0(ctx); \
733}
734
735#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
736GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
737{ \
738 gen_op_load_gpr_T0(rA(ctx->opcode)); \
739 if (ctx->sf_mode) \
740 gen_op_##name##_64(); \
741 else \
742 gen_op_##name(); \
743 gen_op_store_T0_gpr(rD(ctx->opcode)); \
744 if (unlikely(Rc(ctx->opcode) != 0)) \
745 gen_set_Rc0(ctx); \
746}
747#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
748GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
749{ \
750 gen_op_load_gpr_T0(rA(ctx->opcode)); \
751 if (ctx->sf_mode) \
752 gen_op_##name##_64(); \
753 else \
754 gen_op_##name(); \
755 gen_op_store_T0_gpr(rD(ctx->opcode)); \
756 if (unlikely(Rc(ctx->opcode) != 0)) \
757 gen_set_Rc0(ctx); \
758}
759
760/* Two operands arithmetic functions */
761#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
762__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
763__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 764
765/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 766#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
767__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 768
769/* One operand arithmetic functions */
d9bce9d9
JM		 770#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
771__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
772__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
773#else
774#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
775#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
776#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
777#endif
79aceca5
FB		 778
779/* add add. addo addo. */
b068d6a7 780static always_inline void gen_op_addo (void)
d9bce9d9
JM		 781{
782 gen_op_move_T2_T0();
783 gen_op_add();
784 gen_op_check_addo();
785}
786#if defined(TARGET_PPC64)
787#define gen_op_add_64 gen_op_add
b068d6a7 788static always_inline void gen_op_addo_64 (void)
d9bce9d9
JM		 789{
790 gen_op_move_T2_T0();
791 gen_op_add();
792 gen_op_check_addo_64();
793}
794#endif
795GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 796/* addc addc. addco addco. */
b068d6a7 797static always_inline void gen_op_addc (void)
d9bce9d9
JM		 798{
799 gen_op_move_T2_T0();
800 gen_op_add();
801 gen_op_check_addc();
802}
b068d6a7 803static always_inline void gen_op_addco (void)
d9bce9d9
JM		 804{
805 gen_op_move_T2_T0();
806 gen_op_add();
807 gen_op_check_addc();
808 gen_op_check_addo();
809}
810#if defined(TARGET_PPC64)
b068d6a7 811static always_inline void gen_op_addc_64 (void)
d9bce9d9
JM		 812{
813 gen_op_move_T2_T0();
814 gen_op_add();
815 gen_op_check_addc_64();
816}
b068d6a7 817static always_inline void gen_op_addco_64 (void)
d9bce9d9
JM		 818{
819 gen_op_move_T2_T0();
820 gen_op_add();
821 gen_op_check_addc_64();
822 gen_op_check_addo_64();
823}
824#endif
825GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 826/* adde adde. addeo addeo. */
b068d6a7 827static always_inline void gen_op_addeo (void)
d9bce9d9
JM		 828{
829 gen_op_move_T2_T0();
830 gen_op_adde();
831 gen_op_check_addo();
832}
833#if defined(TARGET_PPC64)
b068d6a7 834static always_inline void gen_op_addeo_64 (void)
d9bce9d9
JM		 835{
836 gen_op_move_T2_T0();
837 gen_op_adde_64();
838 gen_op_check_addo_64();
839}
840#endif
841GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 842/* addme addme. addmeo addmeo. */
b068d6a7 843static always_inline void gen_op_addme (void)
d9bce9d9
JM		 844{
845 gen_op_move_T1_T0();
846 gen_op_add_me();
847}
848#if defined(TARGET_PPC64)
b068d6a7 849static always_inline void gen_op_addme_64 (void)
d9bce9d9
JM		 850{
851 gen_op_move_T1_T0();
852 gen_op_add_me_64();
853}
854#endif
855GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 856/* addze addze. addzeo addzeo. */
b068d6a7 857static always_inline void gen_op_addze (void)
d9bce9d9
JM		 858{
859 gen_op_move_T2_T0();
860 gen_op_add_ze();
861 gen_op_check_addc();
862}
b068d6a7 863static always_inline void gen_op_addzeo (void)
d9bce9d9
JM		 864{
865 gen_op_move_T2_T0();
866 gen_op_add_ze();
867 gen_op_check_addc();
868 gen_op_check_addo();
869}
870#if defined(TARGET_PPC64)
b068d6a7 871static always_inline void gen_op_addze_64 (void)
d9bce9d9
JM		 872{
873 gen_op_move_T2_T0();
874 gen_op_add_ze();
875 gen_op_check_addc_64();
876}
b068d6a7 877static always_inline void gen_op_addzeo_64 (void)
d9bce9d9
JM		 878{
879 gen_op_move_T2_T0();
880 gen_op_add_ze();
881 gen_op_check_addc_64();
882 gen_op_check_addo_64();
883}
884#endif
885GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 886/* divw divw. divwo divwo. */
d9bce9d9 887GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 888/* divwu divwu. divwuo divwuo. */
d9bce9d9 889GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 890/* mulhw mulhw. */
d9bce9d9 891GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 892/* mulhwu mulhwu. */
d9bce9d9 893GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 894/* mullw mullw. mullwo mullwo. */
d9bce9d9 895GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 896/* neg neg. nego nego. */
d9bce9d9 897GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 898/* subf subf. subfo subfo. */
b068d6a7 899static always_inline void gen_op_subfo (void)
d9bce9d9 900{
c3e10c7b 901 gen_op_moven_T2_T0();
d9bce9d9 902 gen_op_subf();
c3e10c7b 903 gen_op_check_addo();
d9bce9d9
JM		 904}
905#if defined(TARGET_PPC64)
906#define gen_op_subf_64 gen_op_subf
b068d6a7 907static always_inline void gen_op_subfo_64 (void)
d9bce9d9 908{
c3e10c7b 909 gen_op_moven_T2_T0();
d9bce9d9 910 gen_op_subf();
c3e10c7b 911 gen_op_check_addo_64();
d9bce9d9
JM		 912}
913#endif
914GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 915/* subfc subfc. subfco subfco. */
b068d6a7 916static always_inline void gen_op_subfc (void)
d9bce9d9
JM		 917{
918 gen_op_subf();
919 gen_op_check_subfc();
920}
b068d6a7 921static always_inline void gen_op_subfco (void)
d9bce9d9 922{
c3e10c7b 923 gen_op_moven_T2_T0();
d9bce9d9
JM		 924 gen_op_subf();
925 gen_op_check_subfc();
c3e10c7b 926 gen_op_check_addo();
d9bce9d9
JM		 927}
928#if defined(TARGET_PPC64)
b068d6a7 929static always_inline void gen_op_subfc_64 (void)
d9bce9d9
JM		 930{
931 gen_op_subf();
932 gen_op_check_subfc_64();
933}
b068d6a7 934static always_inline void gen_op_subfco_64 (void)
d9bce9d9 935{
c3e10c7b 936 gen_op_moven_T2_T0();
d9bce9d9
JM		 937 gen_op_subf();
938 gen_op_check_subfc_64();
c3e10c7b 939 gen_op_check_addo_64();
d9bce9d9
JM		 940}
941#endif
942GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 943/* subfe subfe. subfeo subfeo. */
b068d6a7 944static always_inline void gen_op_subfeo (void)
d9bce9d9 945{
c3e10c7b 946 gen_op_moven_T2_T0();
d9bce9d9 947 gen_op_subfe();
c3e10c7b 948 gen_op_check_addo();
d9bce9d9
JM		 949}
950#if defined(TARGET_PPC64)
951#define gen_op_subfe_64 gen_op_subfe
b068d6a7 952static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 953{
c3e10c7b 954 gen_op_moven_T2_T0();
d9bce9d9 955 gen_op_subfe_64();
c3e10c7b 956 gen_op_check_addo_64();
d9bce9d9
JM		 957}
958#endif
959GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 960/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 961GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 962/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 963GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 964/* addi */
965GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
966{
76a66253 967 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 968
969 if (rA(ctx->opcode) == 0) {
76a66253 970 /* li case */
d9bce9d9 971 gen_set_T0(simm);
79aceca5
FB		 972 } else {
973 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 974 if (likely(simm != 0))
975 gen_op_addi(simm);
79aceca5
FB		 976 }
977 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 978}
979/* addic */
980GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
981{
76a66253
JM		 982 target_long simm = SIMM(ctx->opcode);
983
79aceca5 984 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 985 if (likely(simm != 0)) {
986 gen_op_move_T2_T0();
987 gen_op_addi(simm);
988#if defined(TARGET_PPC64)
989 if (ctx->sf_mode)
990 gen_op_check_addc_64();
991 else
992#endif
993 gen_op_check_addc();
e864cabd
JM		 994 } else {
995 gen_op_clear_xer_ca();
d9bce9d9 996 }
79aceca5 997 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 998}
999/* addic. */
c7697e1f 1000GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1001{
76a66253
JM		 1002 target_long simm = SIMM(ctx->opcode);
1003
79aceca5 1004 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 1005 if (likely(simm != 0)) {
1006 gen_op_move_T2_T0();
1007 gen_op_addi(simm);
1008#if defined(TARGET_PPC64)
1009 if (ctx->sf_mode)
1010 gen_op_check_addc_64();
1011 else
1012#endif
1013 gen_op_check_addc();
966439a6
JM		 1014 } else {
1015 gen_op_clear_xer_ca();
d9bce9d9 1016 }
79aceca5 1017 gen_op_store_T0_gpr(rD(ctx->opcode));
76a66253 1018 gen_set_Rc0(ctx);
79aceca5
FB		 1019}
1020/* addis */
1021GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1022{
76a66253 1023 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1024
1025 if (rA(ctx->opcode) == 0) {
76a66253 1026 /* lis case */
d9bce9d9 1027 gen_set_T0(simm << 16);
79aceca5
FB		 1028 } else {
1029 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 1030 if (likely(simm != 0))
1031 gen_op_addi(simm << 16);
79aceca5
FB		 1032 }
1033 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1034}
1035/* mulli */
1036GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1037{
1038 gen_op_load_gpr_T0(rA(ctx->opcode));
1039 gen_op_mulli(SIMM(ctx->opcode));
1040 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1041}
1042/* subfic */
1043GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1044{
1045 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 1046#if defined(TARGET_PPC64)
1047 if (ctx->sf_mode)
1048 gen_op_subfic_64(SIMM(ctx->opcode));
1049 else
1050#endif
1051 gen_op_subfic(SIMM(ctx->opcode));
79aceca5 1052 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1053}
1054
d9bce9d9
JM		 1055#if defined(TARGET_PPC64)
1056/* mulhd mulhd. */
a750fc0b 1057GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1058/* mulhdu mulhdu. */
a750fc0b 1059GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1060/* mulld mulld. mulldo mulldo. */
a750fc0b 1061GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1062/* divd divd. divdo divdo. */
a750fc0b 1063GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1064/* divdu divdu. divduo divduo. */
a750fc0b 1065GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1066#endif
1067
79aceca5 1068/*** Integer comparison ***/
d9bce9d9
JM		 1069#if defined(TARGET_PPC64)
1070#define GEN_CMP(name, opc, type) \
1071GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
1072{ \
1073 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1074 gen_op_load_gpr_T1(rB(ctx->opcode)); \
e3878283 1075 if (ctx->sf_mode && (ctx->opcode & 0x00200000)) \
d9bce9d9
JM		 1076 gen_op_##name##_64(); \
1077 else \
1078 gen_op_##name(); \
1079 gen_op_store_T0_crf(crfD(ctx->opcode)); \
1080}
1081#else
1082#define GEN_CMP(name, opc, type) \
1083GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type) \
79aceca5
FB		 1084{ \
1085 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1086 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1087 gen_op_##name(); \
1088 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5 1089}
d9bce9d9 1090#endif
79aceca5
FB		 1091
1092/* cmp */
d9bce9d9 1093GEN_CMP(cmp, 0x00, PPC_INTEGER);
79aceca5
FB		 1094/* cmpi */
1095GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1096{
1097 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9 1098#if defined(TARGET_PPC64)
e3878283 1099 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1100 gen_op_cmpi_64(SIMM(ctx->opcode));
1101 else
1102#endif
1103 gen_op_cmpi(SIMM(ctx->opcode));
79aceca5 1104 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1105}
1106/* cmpl */
d9bce9d9 1107GEN_CMP(cmpl, 0x01, PPC_INTEGER);
79aceca5
FB		 1108/* cmpli */
1109GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
1110{
1111 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9 1112#if defined(TARGET_PPC64)
e3878283 1113 if (ctx->sf_mode && (ctx->opcode & 0x00200000))
d9bce9d9
JM		 1114 gen_op_cmpli_64(UIMM(ctx->opcode));
1115 else
1116#endif
1117 gen_op_cmpli(UIMM(ctx->opcode));
79aceca5 1118 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1119}
1120
d9bce9d9 1121/* isel (PowerPC 2.03 specification) */
fd501a05 1122GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
d9bce9d9
JM		 1123{
1124 uint32_t bi = rC(ctx->opcode);
1125 uint32_t mask;
1126
1127 if (rA(ctx->opcode) == 0) {
1128 gen_set_T0(0);
1129 } else {
1130 gen_op_load_gpr_T1(rA(ctx->opcode));
1131 }
1132 gen_op_load_gpr_T2(rB(ctx->opcode));
1133 mask = 1 << (3 - (bi & 0x03));
1134 gen_op_load_crf_T0(bi >> 2);
1135 gen_op_test_true(mask);
1136 gen_op_isel();
1137 gen_op_store_T0_gpr(rD(ctx->opcode));
1138}
1139
79aceca5 1140/*** Integer logical ***/
d9bce9d9
JM		 1141#define __GEN_LOGICAL2(name, opc2, opc3, type) \
1142GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
79aceca5
FB		 1143{ \
1144 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1145 gen_op_load_gpr_T1(rB(ctx->opcode)); \
1146 gen_op_##name(); \
79aceca5 1147 gen_op_store_T0_gpr(rA(ctx->opcode)); \
76a66253
JM		 1148 if (unlikely(Rc(ctx->opcode) != 0)) \
1149 gen_set_Rc0(ctx); \
79aceca5 1150}
d9bce9d9
JM		 1151#define GEN_LOGICAL2(name, opc, type) \
1152__GEN_LOGICAL2(name, 0x1C, opc, type)
79aceca5 1153
d9bce9d9
JM		 1154#define GEN_LOGICAL1(name, opc, type) \
1155GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5
FB		 1156{ \
1157 gen_op_load_gpr_T0(rS(ctx->opcode)); \
1158 gen_op_##name(); \
79aceca5 1159 gen_op_store_T0_gpr(rA(ctx->opcode)); \
76a66253
JM		 1160 if (unlikely(Rc(ctx->opcode) != 0)) \
1161 gen_set_Rc0(ctx); \
79aceca5
FB		 1162}
1163
1164/* and & and. */
d9bce9d9 1165GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
79aceca5 1166/* andc & andc. */
d9bce9d9 1167GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
79aceca5 1168/* andi. */
c7697e1f 1169GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5
FB		 1170{
1171 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253 1172 gen_op_andi_T0(UIMM(ctx->opcode));
79aceca5 1173 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253 1174 gen_set_Rc0(ctx);
79aceca5
FB		 1175}
1176/* andis. */
c7697e1f 1177GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5
FB		 1178{
1179 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253 1180 gen_op_andi_T0(UIMM(ctx->opcode) << 16);
79aceca5 1181 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253 1182 gen_set_Rc0(ctx);
79aceca5
FB		 1183}
1184
1185/* cntlzw */
d9bce9d9 1186GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
79aceca5 1187/* eqv & eqv. */
d9bce9d9 1188GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
79aceca5 1189/* extsb & extsb. */
d9bce9d9 1190GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
79aceca5 1191/* extsh & extsh. */
d9bce9d9 1192GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
79aceca5 1193/* nand & nand. */
d9bce9d9 1194GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
79aceca5 1195/* nor & nor. */
d9bce9d9 1196GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
9a64fbe4 1197
79aceca5 1198/* or & or. */
9a64fbe4
FB		 1199GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1200{
76a66253
JM		 1201 int rs, ra, rb;
1202
1203 rs = rS(ctx->opcode);
1204 ra = rA(ctx->opcode);
1205 rb = rB(ctx->opcode);
1206 /* Optimisation for mr. ri case */
1207 if (rs != ra || rs != rb) {
1208 gen_op_load_gpr_T0(rs);
1209 if (rs != rb) {
1210 gen_op_load_gpr_T1(rb);
1211 gen_op_or();
1212 }
1213 gen_op_store_T0_gpr(ra);
1214 if (unlikely(Rc(ctx->opcode) != 0))
1215 gen_set_Rc0(ctx);
1216 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1217 gen_op_load_gpr_T0(rs);
1218 gen_set_Rc0(ctx);
c80f84e3
JM		 1219#if defined(TARGET_PPC64)
1220 } else {
1221 switch (rs) {
1222 case 1:
1223 /* Set process priority to low */
1224 gen_op_store_pri(2);
1225 break;
1226 case 6:
1227 /* Set process priority to medium-low */
1228 gen_op_store_pri(3);
1229 break;
1230 case 2:
1231 /* Set process priority to normal */
1232 gen_op_store_pri(4);
1233 break;
be147d08
JM		 1234#if !defined(CONFIG_USER_ONLY)
1235 case 31:
1236 if (ctx->supervisor > 0) {
1237 /* Set process priority to very low */
1238 gen_op_store_pri(1);
1239 }
1240 break;
1241 case 5:
1242 if (ctx->supervisor > 0) {
1243 /* Set process priority to medium-hight */
1244 gen_op_store_pri(5);
1245 }
1246 break;
1247 case 3:
1248 if (ctx->supervisor > 0) {
1249 /* Set process priority to high */
1250 gen_op_store_pri(6);
1251 }
1252 break;
be147d08
JM		 1253 case 7:
1254 if (ctx->supervisor > 1) {
1255 /* Set process priority to very high */
1256 gen_op_store_pri(7);
1257 }
1258 break;
be147d08 1259#endif
c80f84e3
JM		 1260 default:
1261 /* nop */
1262 break;
1263 }
1264#endif
9a64fbe4 1265 }
9a64fbe4
FB		 1266}
1267
79aceca5 1268/* orc & orc. */
d9bce9d9 1269GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
79aceca5 1270/* xor & xor. */
9a64fbe4
FB		 1271GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1272{
1273 gen_op_load_gpr_T0(rS(ctx->opcode));
1274 /* Optimisation for "set to zero" case */
1275 if (rS(ctx->opcode) != rB(ctx->opcode)) {
1276 gen_op_load_gpr_T1(rB(ctx->opcode));
1277 gen_op_xor();
1278 } else {
76a66253 1279 gen_op_reset_T0();
9a64fbe4 1280 }
9a64fbe4 1281 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1282 if (unlikely(Rc(ctx->opcode) != 0))
1283 gen_set_Rc0(ctx);
9a64fbe4 1284}
79aceca5
FB		 1285/* ori */
1286GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1287{
76a66253 1288 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1289
9a64fbe4
FB		 1290 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1291 /* NOP */
76a66253 1292 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1293 return;
76a66253
JM		 1294 }
1295 gen_op_load_gpr_T0(rS(ctx->opcode));
1296 if (likely(uimm != 0))
79aceca5 1297 gen_op_ori(uimm);
76a66253 1298 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1299}
1300/* oris */
1301GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1302{
76a66253 1303 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1304
9a64fbe4
FB		 1305 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1306 /* NOP */
1307 return;
76a66253
JM		 1308 }
1309 gen_op_load_gpr_T0(rS(ctx->opcode));
1310 if (likely(uimm != 0))
79aceca5 1311 gen_op_ori(uimm << 16);
76a66253 1312 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1313}
1314/* xori */
1315GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1316{
76a66253 1317 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1318
1319 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1320 /* NOP */
1321 return;
1322 }
79aceca5 1323 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1324 if (likely(uimm != 0))
1325 gen_op_xori(uimm);
79aceca5 1326 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1327}
1328
1329/* xoris */
1330GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1331{
76a66253 1332 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1333
1334 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1335 /* NOP */
1336 return;
1337 }
79aceca5 1338 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1339 if (likely(uimm != 0))
1340 gen_op_xori(uimm << 16);
79aceca5 1341 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 1342}
1343
d9bce9d9 1344/* popcntb : PowerPC 2.03 specification */
05332d70 1345GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9
JM		 1346{
1347 gen_op_load_gpr_T0(rS(ctx->opcode));
1348#if defined(TARGET_PPC64)
1349 if (ctx->sf_mode)
1350 gen_op_popcntb_64();
1351 else
1352#endif
1353 gen_op_popcntb();
1354 gen_op_store_T0_gpr(rA(ctx->opcode));
1355}
1356
1357#if defined(TARGET_PPC64)
1358/* extsw & extsw. */
1359GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1360/* cntlzd */
1361GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1362#endif
1363
79aceca5
FB		 1364/*** Integer rotate ***/
1365/* rlwimi & rlwimi. */
1366GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1367{
76a66253
JM		 1368 target_ulong mask;
1369 uint32_t mb, me, sh;
79aceca5
FB		 1370
1371 mb = MB(ctx->opcode);
1372 me = ME(ctx->opcode);
76a66253 1373 sh = SH(ctx->opcode);
76a66253
JM		 1374 if (likely(sh == 0)) {
1375 if (likely(mb == 0 && me == 31)) {
1376 gen_op_load_gpr_T0(rS(ctx->opcode));
1377 goto do_store;
1378 } else if (likely(mb == 31 && me == 0)) {
1379 gen_op_load_gpr_T0(rA(ctx->opcode));
1380 goto do_store;
1381 }
1382 gen_op_load_gpr_T0(rS(ctx->opcode));
1383 gen_op_load_gpr_T1(rA(ctx->opcode));
1384 goto do_mask;
1385 }
79aceca5 1386 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 1387 gen_op_load_gpr_T1(rA(ctx->opcode));
76a66253
JM		 1388 gen_op_rotli32_T0(SH(ctx->opcode));
1389 do_mask:
1390#if defined(TARGET_PPC64)
1391 mb += 32;
1392 me += 32;
1393#endif
1394 mask = MASK(mb, me);
1395 gen_op_andi_T0(mask);
1396 gen_op_andi_T1(~mask);
1397 gen_op_or();
1398 do_store:
79aceca5 1399 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1400 if (unlikely(Rc(ctx->opcode) != 0))
1401 gen_set_Rc0(ctx);
79aceca5
FB		 1402}
1403/* rlwinm & rlwinm. */
1404GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1405{
1406 uint32_t mb, me, sh;
3b46e624 1407
79aceca5
FB		 1408 sh = SH(ctx->opcode);
1409 mb = MB(ctx->opcode);
1410 me = ME(ctx->opcode);
1411 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 1412 if (likely(sh == 0)) {
1413 goto do_mask;
1414 }
1415 if (likely(mb == 0)) {
1416 if (likely(me == 31)) {
1417 gen_op_rotli32_T0(sh);
1418 goto do_store;
1419 } else if (likely(me == (31 - sh))) {
1420 gen_op_sli_T0(sh);
1421 goto do_store;
79aceca5 1422 }
76a66253
JM		 1423 } else if (likely(me == 31)) {
1424 if (likely(sh == (32 - mb))) {
1425 gen_op_srli_T0(mb);
1426 goto do_store;
79aceca5
FB		 1427 }
1428 }
76a66253
JM		 1429 gen_op_rotli32_T0(sh);
1430 do_mask:
1431#if defined(TARGET_PPC64)
1432 mb += 32;
1433 me += 32;
1434#endif
1435 gen_op_andi_T0(MASK(mb, me));
1436 do_store:
79aceca5 1437 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1438 if (unlikely(Rc(ctx->opcode) != 0))
1439 gen_set_Rc0(ctx);
79aceca5
FB		 1440}
1441/* rlwnm & rlwnm. */
1442GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1443{
1444 uint32_t mb, me;
1445
1446 mb = MB(ctx->opcode);
1447 me = ME(ctx->opcode);
1448 gen_op_load_gpr_T0(rS(ctx->opcode));
1449 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 1450 gen_op_rotl32_T0_T1();
1451 if (unlikely(mb != 0 || me != 31)) {
1452#if defined(TARGET_PPC64)
1453 mb += 32;
1454 me += 32;
1455#endif
1456 gen_op_andi_T0(MASK(mb, me));
79aceca5 1457 }
79aceca5 1458 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1459 if (unlikely(Rc(ctx->opcode) != 0))
1460 gen_set_Rc0(ctx);
79aceca5
FB		 1461}
1462
d9bce9d9
JM		 1463#if defined(TARGET_PPC64)
1464#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1465GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1466{ \
1467 gen_##name(ctx, 0); \
1468} \
c7697e1f
JM		 1469GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1470 PPC_64B) \
d9bce9d9
JM		 1471{ \
1472 gen_##name(ctx, 1); \
1473}
1474#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1475GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1476{ \
1477 gen_##name(ctx, 0, 0); \
1478} \
c7697e1f
JM		 1479GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1480 PPC_64B) \
d9bce9d9
JM		 1481{ \
1482 gen_##name(ctx, 0, 1); \
1483} \
c7697e1f
JM		 1484GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1485 PPC_64B) \
d9bce9d9
JM		 1486{ \
1487 gen_##name(ctx, 1, 0); \
1488} \
c7697e1f
JM		 1489GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1490 PPC_64B) \
d9bce9d9
JM		 1491{ \
1492 gen_##name(ctx, 1, 1); \
1493}
51789c41 1494
b068d6a7 1495static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
40d0591e
JM		 1496{
1497 if (mask >> 32)
1498 gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
1499 else
1500 gen_op_andi_T0(mask);
1501}
1502
b068d6a7 1503static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
40d0591e
JM		 1504{
1505 if (mask >> 32)
1506 gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
1507 else
1508 gen_op_andi_T1(mask);
1509}
1510
b068d6a7
JM		 1511static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1512 uint32_t me, uint32_t sh)
51789c41
JM		 1513{
1514 gen_op_load_gpr_T0(rS(ctx->opcode));
1515 if (likely(sh == 0)) {
1516 goto do_mask;
1517 }
1518 if (likely(mb == 0)) {
1519 if (likely(me == 63)) {
40d0591e 1520 gen_op_rotli64_T0(sh);
51789c41
JM		 1521 goto do_store;
1522 } else if (likely(me == (63 - sh))) {
1523 gen_op_sli_T0(sh);
1524 goto do_store;
1525 }
1526 } else if (likely(me == 63)) {
1527 if (likely(sh == (64 - mb))) {
40d0591e 1528 gen_op_srli_T0_64(mb);
51789c41
JM		 1529 goto do_store;
1530 }
1531 }
1532 gen_op_rotli64_T0(sh);
1533 do_mask:
40d0591e 1534 gen_andi_T0_64(ctx, MASK(mb, me));
51789c41
JM		 1535 do_store:
1536 gen_op_store_T0_gpr(rA(ctx->opcode));
1537 if (unlikely(Rc(ctx->opcode) != 0))
1538 gen_set_Rc0(ctx);
1539}
d9bce9d9 1540/* rldicl - rldicl. */
b068d6a7 1541static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1542{
51789c41 1543 uint32_t sh, mb;
d9bce9d9 1544
9d53c753
JM		 1545 sh = SH(ctx->opcode) | (shn << 5);
1546 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1547 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1548}
51789c41 1549GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1550/* rldicr - rldicr. */
b068d6a7 1551static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1552{
51789c41 1553 uint32_t sh, me;
d9bce9d9 1554
9d53c753
JM		 1555 sh = SH(ctx->opcode) | (shn << 5);
1556 me = MB(ctx->opcode) | (men << 5);
51789c41 1557 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1558}
51789c41 1559GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1560/* rldic - rldic. */
b068d6a7 1561static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1562{
51789c41 1563 uint32_t sh, mb;
d9bce9d9 1564
9d53c753
JM		 1565 sh = SH(ctx->opcode) | (shn << 5);
1566 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1567 gen_rldinm(ctx, mb, 63 - sh, sh);
1568}
1569GEN_PPC64_R4(rldic, 0x1E, 0x04);
1570
b068d6a7
JM		 1571static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1572 uint32_t me)
51789c41
JM		 1573{
1574 gen_op_load_gpr_T0(rS(ctx->opcode));
1575 gen_op_load_gpr_T1(rB(ctx->opcode));
1576 gen_op_rotl64_T0_T1();
1577 if (unlikely(mb != 0 || me != 63)) {
40d0591e 1578 gen_andi_T0_64(ctx, MASK(mb, me));
51789c41
JM		 1579 }
1580 gen_op_store_T0_gpr(rA(ctx->opcode));
1581 if (unlikely(Rc(ctx->opcode) != 0))
1582 gen_set_Rc0(ctx);
d9bce9d9 1583}
51789c41 1584
d9bce9d9 1585/* rldcl - rldcl. */
b068d6a7 1586static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1587{
51789c41 1588 uint32_t mb;
d9bce9d9 1589
9d53c753 1590 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1591 gen_rldnm(ctx, mb, 63);
d9bce9d9 1592}
36081602 1593GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1594/* rldcr - rldcr. */
b068d6a7 1595static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1596{
51789c41 1597 uint32_t me;
d9bce9d9 1598
9d53c753 1599 me = MB(ctx->opcode) | (men << 5);
51789c41 1600 gen_rldnm(ctx, 0, me);
d9bce9d9 1601}
36081602 1602GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1603/* rldimi - rldimi. */
b068d6a7 1604static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1605{
51789c41 1606 uint64_t mask;
271a916e 1607 uint32_t sh, mb, me;
d9bce9d9 1608
9d53c753
JM		 1609 sh = SH(ctx->opcode) | (shn << 5);
1610 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1611 me = 63 - sh;
51789c41
JM		 1612 if (likely(sh == 0)) {
1613 if (likely(mb == 0)) {
1614 gen_op_load_gpr_T0(rS(ctx->opcode));
1615 goto do_store;
51789c41
JM		 1616 }
1617 gen_op_load_gpr_T0(rS(ctx->opcode));
1618 gen_op_load_gpr_T1(rA(ctx->opcode));
1619 goto do_mask;
1620 }
1621 gen_op_load_gpr_T0(rS(ctx->opcode));
1622 gen_op_load_gpr_T1(rA(ctx->opcode));
40d0591e 1623 gen_op_rotli64_T0(sh);
51789c41 1624 do_mask:
271a916e 1625 mask = MASK(mb, me);
40d0591e
JM		 1626 gen_andi_T0_64(ctx, mask);
1627 gen_andi_T1_64(ctx, ~mask);
51789c41
JM		 1628 gen_op_or();
1629 do_store:
1630 gen_op_store_T0_gpr(rA(ctx->opcode));
1631 if (unlikely(Rc(ctx->opcode) != 0))
1632 gen_set_Rc0(ctx);
d9bce9d9 1633}
36081602 1634GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1635#endif
1636
79aceca5
FB		 1637/*** Integer shift ***/
1638/* slw & slw. */
d9bce9d9 1639__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
79aceca5 1640/* sraw & sraw. */
d9bce9d9 1641__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
79aceca5
FB		 1642/* srawi & srawi. */
1643GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1644{
d9bce9d9 1645 int mb, me;
79aceca5 1646 gen_op_load_gpr_T0(rS(ctx->opcode));
d9bce9d9
JM		 1647 if (SH(ctx->opcode) != 0) {
1648 gen_op_move_T1_T0();
1649 mb = 32 - SH(ctx->opcode);
1650 me = 31;
1651#if defined(TARGET_PPC64)
1652 mb += 32;
1653 me += 32;
1654#endif
1655 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1656 }
79aceca5 1657 gen_op_store_T0_gpr(rA(ctx->opcode));
76a66253
JM		 1658 if (unlikely(Rc(ctx->opcode) != 0))
1659 gen_set_Rc0(ctx);
79aceca5
FB		 1660}
1661/* srw & srw. */
d9bce9d9
JM		 1662__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1663
1664#if defined(TARGET_PPC64)
1665/* sld & sld. */
1666__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1667/* srad & srad. */
1668__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1669/* sradi & sradi. */
b068d6a7 1670static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9
JM		 1671{
1672 uint64_t mask;
1673 int sh, mb, me;
1674
1675 gen_op_load_gpr_T0(rS(ctx->opcode));
1676 sh = SH(ctx->opcode) + (n << 5);
1677 if (sh != 0) {
1678 gen_op_move_T1_T0();
1679 mb = 64 - SH(ctx->opcode);
1680 me = 63;
1681 mask = MASK(mb, me);
1682 gen_op_sradi(sh, mask >> 32, mask);
1683 }
1684 gen_op_store_T0_gpr(rA(ctx->opcode));
1685 if (unlikely(Rc(ctx->opcode) != 0))
1686 gen_set_Rc0(ctx);
1687}
c7697e1f 1688GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1689{
1690 gen_sradi(ctx, 0);
1691}
c7697e1f 1692GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1693{
1694 gen_sradi(ctx, 1);
1695}
1696/* srd & srd. */
1697__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1698#endif
79aceca5
FB		 1699
1700/*** Floating-Point arithmetic ***/
7c58044c 1701#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1702GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1703{ \
76a66253 1704 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1705 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1706 return; \
1707 } \
9a64fbe4
FB		 1708 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1709 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
1710 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
7c58044c 1711 gen_reset_fpstatus(); \
4ecc3190
FB		 1712 gen_op_f##op(); \
1713 if (isfloat) { \
1714 gen_op_frsp(); \
1715 } \
9a64fbe4 1716 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1717 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1718}
1719
7c58044c
JM		 1720#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1721_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1722_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1723
7c58044c
JM		 1724#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1725GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1726{ \
76a66253 1727 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1728 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1729 return; \
1730 } \
9a64fbe4
FB		 1731 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1732 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
7c58044c 1733 gen_reset_fpstatus(); \
4ecc3190
FB		 1734 gen_op_f##op(); \
1735 if (isfloat) { \
1736 gen_op_frsp(); \
1737 } \
9a64fbe4 1738 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1739 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1740}
7c58044c
JM		 1741#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1742_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1743_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1744
7c58044c
JM		 1745#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1746GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1747{ \
76a66253 1748 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1749 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1750 return; \
1751 } \
9a64fbe4
FB		 1752 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
1753 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
7c58044c 1754 gen_reset_fpstatus(); \
4ecc3190
FB		 1755 gen_op_f##op(); \
1756 if (isfloat) { \
1757 gen_op_frsp(); \
1758 } \
9a64fbe4 1759 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1760 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1761}
7c58044c
JM		 1762#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1763_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1764_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1765
7c58044c 1766#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 1767GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 1768{ \
76a66253 1769 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1770 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1771 return; \
1772 } \
9a64fbe4 1773 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
7c58044c 1774 gen_reset_fpstatus(); \
9a64fbe4
FB		 1775 gen_op_f##name(); \
1776 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1777 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1778}
1779
7c58044c 1780#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 1781GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 1782{ \
76a66253 1783 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1784 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1785 return; \
1786 } \
9a64fbe4 1787 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
7c58044c 1788 gen_reset_fpstatus(); \
9a64fbe4
FB		 1789 gen_op_f##name(); \
1790 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
7c58044c 1791 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1792}
1793
9a64fbe4 1794/* fadd - fadds */
7c58044c 1795GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1796/* fdiv - fdivs */
7c58044c 1797GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1798/* fmul - fmuls */
7c58044c 1799GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 1800
d7e4b87e 1801/* fre */
7c58044c 1802GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 1803
a750fc0b 1804/* fres */
7c58044c 1805GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 1806
a750fc0b 1807/* frsqrte */
7c58044c
JM		 1808GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1809
1810/* frsqrtes */
1811static always_inline void gen_op_frsqrtes (void)
1812{
1813 gen_op_frsqrte();
1814 gen_op_frsp();
1815}
1b413d55 1816GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 1817
a750fc0b 1818/* fsel */
7c58044c 1819_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 1820/* fsub - fsubs */
7c58044c 1821GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 1822/* Optional: */
1823/* fsqrt */
a750fc0b 1824GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 1825{
76a66253 1826 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1827 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 1828 return;
1829 }
c7d344af 1830 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 1831 gen_reset_fpstatus();
c7d344af
FB		 1832 gen_op_fsqrt();
1833 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1834 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 1835}
79aceca5 1836
a750fc0b 1837GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 1838{
76a66253 1839 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1840 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1841 return;
1842 }
9a64fbe4 1843 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 1844 gen_reset_fpstatus();
4ecc3190
FB		 1845 gen_op_fsqrt();
1846 gen_op_frsp();
9a64fbe4 1847 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1848 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 1849}
1850
1851/*** Floating-Point multiply-and-add ***/
4ecc3190 1852/* fmadd - fmadds */
7c58044c 1853GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 1854/* fmsub - fmsubs */
7c58044c 1855GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 1856/* fnmadd - fnmadds */
7c58044c 1857GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 1858/* fnmsub - fnmsubs */
7c58044c 1859GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 1860
1861/*** Floating-Point round & convert ***/
1862/* fctiw */
7c58044c 1863GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 1864/* fctiwz */
7c58044c 1865GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 1866/* frsp */
7c58044c 1867GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 1868#if defined(TARGET_PPC64)
1869/* fcfid */
7c58044c 1870GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 1871/* fctid */
7c58044c 1872GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 1873/* fctidz */
7c58044c 1874GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 1875#endif
79aceca5 1876
d7e4b87e 1877/* frin */
7c58044c 1878GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 1879/* friz */
7c58044c 1880GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 1881/* frip */
7c58044c 1882GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 1883/* frim */
7c58044c 1884GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 1885
79aceca5
FB		 1886/*** Floating-Point compare ***/
1887/* fcmpo */
76a66253 1888GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 1889{
76a66253 1890 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1891 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1892 return;
1893 }
9a64fbe4
FB		 1894 gen_op_load_fpr_FT0(rA(ctx->opcode));
1895 gen_op_load_fpr_FT1(rB(ctx->opcode));
7c58044c 1896 gen_reset_fpstatus();
9a64fbe4
FB		 1897 gen_op_fcmpo();
1898 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1899 gen_op_float_check_status();
79aceca5
FB		 1900}
1901
1902/* fcmpu */
76a66253 1903GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 1904{
76a66253 1905 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1906 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1907 return;
1908 }
9a64fbe4
FB		 1909 gen_op_load_fpr_FT0(rA(ctx->opcode));
1910 gen_op_load_fpr_FT1(rB(ctx->opcode));
7c58044c 1911 gen_reset_fpstatus();
9a64fbe4
FB		 1912 gen_op_fcmpu();
1913 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1914 gen_op_float_check_status();
79aceca5
FB		 1915}
1916
9a64fbe4
FB		 1917/*** Floating-point move ***/
1918/* fabs */
7c58044c
JM		 1919/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
1920GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 1921
1922/* fmr - fmr. */
7c58044c 1923/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 1924GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
1925{
76a66253 1926 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1927 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1928 return;
1929 }
9a64fbe4
FB		 1930 gen_op_load_fpr_FT0(rB(ctx->opcode));
1931 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1932 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 1933}
1934
1935/* fnabs */
7c58044c
JM		 1936/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
1937GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 1938/* fneg */
7c58044c
JM		 1939/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
1940GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 1941
79aceca5
FB		 1942/*** Floating-Point status & ctrl register ***/
1943/* mcrfs */
1944GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
1945{
7c58044c
JM		 1946 int bfa;
1947
76a66253 1948 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1949 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1950 return;
1951 }
7c58044c
JM		 1952 gen_optimize_fprf();
1953 bfa = 4 * (7 - crfS(ctx->opcode));
1954 gen_op_load_fpscr_T0(bfa);
fb0eaffc 1955 gen_op_store_T0_crf(crfD(ctx->opcode));
7c58044c 1956 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 1957}
1958
1959/* mffs */
1960GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
1961{
76a66253 1962 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1963 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1964 return;
1965 }
7c58044c
JM		 1966 gen_optimize_fprf();
1967 gen_reset_fpstatus();
1968 gen_op_load_fpscr_FT0();
fb0eaffc 1969 gen_op_store_FT0_fpr(rD(ctx->opcode));
7c58044c 1970 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 1971}
1972
1973/* mtfsb0 */
1974GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
1975{
fb0eaffc 1976 uint8_t crb;
3b46e624 1977
76a66253 1978 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1979 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1980 return;
1981 }
7c58044c
JM		 1982 crb = 32 - (crbD(ctx->opcode) >> 2);
1983 gen_optimize_fprf();
1984 gen_reset_fpstatus();
1985 if (likely(crb != 30 && crb != 29))
1986 gen_op_fpscr_resetbit(~(1 << crb));
1987 if (unlikely(Rc(ctx->opcode) != 0)) {
1988 gen_op_load_fpcc();
1989 gen_op_set_Rc0();
1990 }
79aceca5
FB		 1991}
1992
1993/* mtfsb1 */
1994GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
1995{
fb0eaffc 1996 uint8_t crb;
3b46e624 1997
76a66253 1998 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1999 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2000 return;
2001 }
7c58044c
JM		 2002 crb = 32 - (crbD(ctx->opcode) >> 2);
2003 gen_optimize_fprf();
2004 gen_reset_fpstatus();
2005 /* XXX: we pretend we can only do IEEE floating-point computations */
2006 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2007 gen_op_fpscr_setbit(crb);
2008 if (unlikely(Rc(ctx->opcode) != 0)) {
2009 gen_op_load_fpcc();
2010 gen_op_set_Rc0();
2011 }
2012 /* We can raise a differed exception */
2013 gen_op_float_check_status();
79aceca5
FB		 2014}
2015
2016/* mtfsf */
2017GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2018{
76a66253 2019 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2020 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2021 return;
2022 }
7c58044c 2023 gen_optimize_fprf();
fb0eaffc 2024 gen_op_load_fpr_FT0(rB(ctx->opcode));
7c58044c 2025 gen_reset_fpstatus();
28b6751f 2026 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c
JM		 2027 if (unlikely(Rc(ctx->opcode) != 0)) {
2028 gen_op_load_fpcc();
2029 gen_op_set_Rc0();
2030 }
2031 /* We can raise a differed exception */
2032 gen_op_float_check_status();
79aceca5
FB		 2033}
2034
2035/* mtfsfi */
2036GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2037{
7c58044c
JM		 2038 int bf, sh;
2039
76a66253 2040 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2041 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2042 return;
2043 }
7c58044c
JM		 2044 bf = crbD(ctx->opcode) >> 2;
2045 sh = 7 - bf;
2046 gen_optimize_fprf();
2047 gen_op_set_FT0(FPIMM(ctx->opcode) << (4 * sh));
2048 gen_reset_fpstatus();
2049 gen_op_store_fpscr(1 << sh);
2050 if (unlikely(Rc(ctx->opcode) != 0)) {
2051 gen_op_load_fpcc();
2052 gen_op_set_Rc0();
2053 }
2054 /* We can raise a differed exception */
2055 gen_op_float_check_status();
79aceca5
FB		 2056}
2057
76a66253
JM		 2058/*** Addressing modes ***/
2059/* Register indirect with immediate index : EA = (rA|0) + SIMM */
b068d6a7
JM		 2060static always_inline void gen_addr_imm_index (DisasContext *ctx,
2061 target_long maskl)
76a66253
JM		 2062{
2063 target_long simm = SIMM(ctx->opcode);
2064
be147d08 2065 simm &= ~maskl;
76a66253 2066 if (rA(ctx->opcode) == 0) {
d9bce9d9 2067 gen_set_T0(simm);
76a66253
JM		 2068 } else {
2069 gen_op_load_gpr_T0(rA(ctx->opcode));
2070 if (likely(simm != 0))
2071 gen_op_addi(simm);
2072 }
a496775f
JM		 2073#ifdef DEBUG_MEMORY_ACCESSES
2074 gen_op_print_mem_EA();
2075#endif
76a66253
JM		 2076}
2077
b068d6a7 2078static always_inline void gen_addr_reg_index (DisasContext *ctx)
76a66253
JM		 2079{
2080 if (rA(ctx->opcode) == 0) {
2081 gen_op_load_gpr_T0(rB(ctx->opcode));
2082 } else {
2083 gen_op_load_gpr_T0(rA(ctx->opcode));
2084 gen_op_load_gpr_T1(rB(ctx->opcode));
2085 gen_op_add();
2086 }
a496775f
JM		 2087#ifdef DEBUG_MEMORY_ACCESSES
2088 gen_op_print_mem_EA();
2089#endif
76a66253
JM		 2090}
2091
b068d6a7 2092static always_inline void gen_addr_register (DisasContext *ctx)
76a66253
JM		 2093{
2094 if (rA(ctx->opcode) == 0) {
2095 gen_op_reset_T0();
2096 } else {
2097 gen_op_load_gpr_T0(rA(ctx->opcode));
2098 }
a496775f
JM		 2099#ifdef DEBUG_MEMORY_ACCESSES
2100 gen_op_print_mem_EA();
2101#endif
76a66253
JM		 2102}
2103
7863667f
JM		 2104#if defined(TARGET_PPC64)
2105#define _GEN_MEM_FUNCS(name, mode) \
2106 &gen_op_##name##_##mode, \
2107 &gen_op_##name##_le_##mode, \
2108 &gen_op_##name##_64_##mode, \
2109 &gen_op_##name##_le_64_##mode
2110#else
2111#define _GEN_MEM_FUNCS(name, mode) \
2112 &gen_op_##name##_##mode, \
2113 &gen_op_##name##_le_##mode
2114#endif
9a64fbe4 2115#if defined(CONFIG_USER_ONLY)
d9bce9d9 2116#if defined(TARGET_PPC64)
7863667f 2117#define NB_MEM_FUNCS 4
d9bce9d9 2118#else
7863667f 2119#define NB_MEM_FUNCS 2
d9bce9d9 2120#endif
7863667f
JM		 2121#define GEN_MEM_FUNCS(name) \
2122 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2123#else
d9bce9d9 2124#if defined(TARGET_PPC64)
7863667f 2125#define NB_MEM_FUNCS 12
2857068e 2126#else
7863667f 2127#define NB_MEM_FUNCS 6
2857068e 2128#endif
7863667f
JM		 2129#define GEN_MEM_FUNCS(name) \
2130 _GEN_MEM_FUNCS(name, user), \
2131 _GEN_MEM_FUNCS(name, kernel), \
2132 _GEN_MEM_FUNCS(name, hypv)
2133#endif
2134
2135/*** Integer load ***/
2136#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
111bfab3 2137/* Byte access routine are endian safe */
7863667f
JM		 2138#define gen_op_lbz_le_raw gen_op_lbz_raw
2139#define gen_op_lbz_le_user gen_op_lbz_user
2140#define gen_op_lbz_le_kernel gen_op_lbz_kernel
2141#define gen_op_lbz_le_hypv gen_op_lbz_hypv
2142#define gen_op_lbz_le_64_raw gen_op_lbz_64_raw
2857068e 2143#define gen_op_lbz_le_64_user gen_op_lbz_64_user
d9bce9d9 2144#define gen_op_lbz_le_64_kernel gen_op_lbz_64_kernel
7863667f
JM		 2145#define gen_op_lbz_le_64_hypv gen_op_lbz_64_hypv
2146#define gen_op_stb_le_raw gen_op_stb_raw
2147#define gen_op_stb_le_user gen_op_stb_user
2148#define gen_op_stb_le_kernel gen_op_stb_kernel
2149#define gen_op_stb_le_hypv gen_op_stb_hypv
2150#define gen_op_stb_le_64_raw gen_op_stb_64_raw
2151#define gen_op_stb_le_64_user gen_op_stb_64_user
2152#define gen_op_stb_le_64_kernel gen_op_stb_64_kernel
2153#define gen_op_stb_le_64_hypv gen_op_stb_64_hypv
d9bce9d9 2154#define OP_LD_TABLE(width) \
7863667f
JM		 2155static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2156 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2157};
2158#define OP_ST_TABLE(width) \
7863667f
JM		 2159static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2160 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2161};
9a64fbe4 2162
d9bce9d9
JM		 2163#define GEN_LD(width, opc, type) \
2164GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2165{ \
9d53c753 2166 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2167 op_ldst(l##width); \
79aceca5 2168 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 2169}
2170
d9bce9d9
JM		 2171#define GEN_LDU(width, opc, type) \
2172GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2173{ \
76a66253
JM		 2174 if (unlikely(rA(ctx->opcode) == 0 || \
2175 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2176 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2177 return; \
9a64fbe4 2178 } \
9d53c753 2179 if (type == PPC_64B) \
be147d08 2180 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2181 else \
2182 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2183 op_ldst(l##width); \
79aceca5
FB		 2184 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2185 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2186}
2187
d9bce9d9
JM		 2188#define GEN_LDUX(width, opc2, opc3, type) \
2189GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2190{ \
76a66253
JM		 2191 if (unlikely(rA(ctx->opcode) == 0 || \
2192 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2193 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2194 return; \
9a64fbe4 2195 } \
76a66253 2196 gen_addr_reg_index(ctx); \
9a64fbe4 2197 op_ldst(l##width); \
79aceca5
FB		 2198 gen_op_store_T1_gpr(rD(ctx->opcode)); \
2199 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2200}
2201
d9bce9d9
JM		 2202#define GEN_LDX(width, opc2, opc3, type) \
2203GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2204{ \
76a66253 2205 gen_addr_reg_index(ctx); \
9a64fbe4 2206 op_ldst(l##width); \
79aceca5 2207 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 2208}
2209
d9bce9d9 2210#define GEN_LDS(width, op, type) \
9a64fbe4 2211OP_LD_TABLE(width); \
d9bce9d9
JM		 2212GEN_LD(width, op | 0x20, type); \
2213GEN_LDU(width, op | 0x21, type); \
2214GEN_LDUX(width, 0x17, op | 0x01, type); \
2215GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2216
2217/* lbz lbzu lbzux lbzx */
d9bce9d9 2218GEN_LDS(bz, 0x02, PPC_INTEGER);
79aceca5 2219/* lha lhau lhaux lhax */
d9bce9d9 2220GEN_LDS(ha, 0x0A, PPC_INTEGER);
79aceca5 2221/* lhz lhzu lhzux lhzx */
d9bce9d9 2222GEN_LDS(hz, 0x08, PPC_INTEGER);
79aceca5 2223/* lwz lwzu lwzux lwzx */
d9bce9d9
JM		 2224GEN_LDS(wz, 0x00, PPC_INTEGER);
2225#if defined(TARGET_PPC64)
2226OP_LD_TABLE(wa);
2227OP_LD_TABLE(d);
2228/* lwaux */
2229GEN_LDUX(wa, 0x15, 0x0B, PPC_64B);
2230/* lwax */
2231GEN_LDX(wa, 0x15, 0x0A, PPC_64B);
2232/* ldux */
2233GEN_LDUX(d, 0x15, 0x01, PPC_64B);
2234/* ldx */
2235GEN_LDX(d, 0x15, 0x00, PPC_64B);
2236GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2237{
2238 if (Rc(ctx->opcode)) {
2239 if (unlikely(rA(ctx->opcode) == 0 ||
2240 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2241 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2242 return;
2243 }
2244 }
be147d08 2245 gen_addr_imm_index(ctx, 0x03);
d9bce9d9
JM		 2246 if (ctx->opcode & 0x02) {
2247 /* lwa (lwau is undefined) */
2248 op_ldst(lwa);
2249 } else {
2250 /* ld - ldu */
2251 op_ldst(ld);
2252 }
2253 gen_op_store_T1_gpr(rD(ctx->opcode));
2254 if (Rc(ctx->opcode))
2255 gen_op_store_T0_gpr(rA(ctx->opcode));
2256}
be147d08
JM		 2257/* lq */
2258GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2259{
2260#if defined(CONFIG_USER_ONLY)
2261 GEN_EXCP_PRIVOPC(ctx);
2262#else
2263 int ra, rd;
2264
2265 /* Restore CPU state */
2266 if (unlikely(ctx->supervisor == 0)) {
2267 GEN_EXCP_PRIVOPC(ctx);
2268 return;
2269 }
2270 ra = rA(ctx->opcode);
2271 rd = rD(ctx->opcode);
2272 if (unlikely((rd & 1) || rd == ra)) {
2273 GEN_EXCP_INVAL(ctx);
2274 return;
2275 }
2276 if (unlikely(ctx->mem_idx & 1)) {
2277 /* Little-endian mode is not handled */
2278 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2279 return;
2280 }
2281 gen_addr_imm_index(ctx, 0x0F);
2282 op_ldst(ld);
2283 gen_op_store_T1_gpr(rd);
2284 gen_op_addi(8);
2285 op_ldst(ld);
2286 gen_op_store_T1_gpr(rd + 1);
2287#endif
2288}
d9bce9d9 2289#endif
79aceca5
FB		 2290
2291/*** Integer store ***/
d9bce9d9
JM		 2292#define GEN_ST(width, opc, type) \
2293GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2294{ \
9d53c753 2295 gen_addr_imm_index(ctx, 0); \
9a64fbe4
FB		 2296 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2297 op_ldst(st##width); \
79aceca5
FB		 2298}
2299
d9bce9d9
JM		 2300#define GEN_STU(width, opc, type) \
2301GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2302{ \
76a66253 2303 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2304 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2305 return; \
9a64fbe4 2306 } \
9d53c753 2307 if (type == PPC_64B) \
be147d08 2308 gen_addr_imm_index(ctx, 0x03); \
9d53c753
JM		 2309 else \
2310 gen_addr_imm_index(ctx, 0); \
79aceca5 2311 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 2312 op_ldst(st##width); \
79aceca5 2313 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2314}
2315
d9bce9d9
JM		 2316#define GEN_STUX(width, opc2, opc3, type) \
2317GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2318{ \
76a66253 2319 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2320 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2321 return; \
9a64fbe4 2322 } \
76a66253 2323 gen_addr_reg_index(ctx); \
9a64fbe4
FB		 2324 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2325 op_ldst(st##width); \
79aceca5 2326 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2327}
2328
d9bce9d9
JM		 2329#define GEN_STX(width, opc2, opc3, type) \
2330GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2331{ \
76a66253 2332 gen_addr_reg_index(ctx); \
9a64fbe4
FB		 2333 gen_op_load_gpr_T1(rS(ctx->opcode)); \
2334 op_ldst(st##width); \
79aceca5
FB		 2335}
2336
d9bce9d9 2337#define GEN_STS(width, op, type) \
9a64fbe4 2338OP_ST_TABLE(width); \
d9bce9d9
JM		 2339GEN_ST(width, op | 0x20, type); \
2340GEN_STU(width, op | 0x21, type); \
2341GEN_STUX(width, 0x17, op | 0x01, type); \
2342GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2343
2344/* stb stbu stbux stbx */
d9bce9d9 2345GEN_STS(b, 0x06, PPC_INTEGER);
79aceca5 2346/* sth sthu sthux sthx */
d9bce9d9 2347GEN_STS(h, 0x0C, PPC_INTEGER);
79aceca5 2348/* stw stwu stwux stwx */
d9bce9d9
JM		 2349GEN_STS(w, 0x04, PPC_INTEGER);
2350#if defined(TARGET_PPC64)
2351OP_ST_TABLE(d);
426613db
JM		 2352GEN_STUX(d, 0x15, 0x05, PPC_64B);
2353GEN_STX(d, 0x15, 0x04, PPC_64B);
be147d08 2354GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2355{
be147d08
JM		 2356 int rs;
2357
2358 rs = rS(ctx->opcode);
2359 if ((ctx->opcode & 0x3) == 0x2) {
2360#if defined(CONFIG_USER_ONLY)
2361 GEN_EXCP_PRIVOPC(ctx);
2362#else
2363 /* stq */
2364 if (unlikely(ctx->supervisor == 0)) {
2365 GEN_EXCP_PRIVOPC(ctx);
2366 return;
2367 }
2368 if (unlikely(rs & 1)) {
e1833e1f 2369 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2370 return;
2371 }
be147d08
JM		 2372 if (unlikely(ctx->mem_idx & 1)) {
2373 /* Little-endian mode is not handled */
2374 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2375 return;
2376 }
2377 gen_addr_imm_index(ctx, 0x03);
2378 gen_op_load_gpr_T1(rs);
2379 op_ldst(std);
2380 gen_op_addi(8);
2381 gen_op_load_gpr_T1(rs + 1);
2382 op_ldst(std);
2383#endif
2384 } else {
2385 /* std / stdu */
2386 if (Rc(ctx->opcode)) {
2387 if (unlikely(rA(ctx->opcode) == 0)) {
2388 GEN_EXCP_INVAL(ctx);
2389 return;
2390 }
2391 }
2392 gen_addr_imm_index(ctx, 0x03);
2393 gen_op_load_gpr_T1(rs);
2394 op_ldst(std);
2395 if (Rc(ctx->opcode))
2396 gen_op_store_T0_gpr(rA(ctx->opcode));
d9bce9d9 2397 }
d9bce9d9
JM		 2398}
2399#endif
79aceca5
FB		 2400/*** Integer load and store with byte reverse ***/
2401/* lhbrx */
9a64fbe4 2402OP_LD_TABLE(hbr);
d9bce9d9 2403GEN_LDX(hbr, 0x16, 0x18, PPC_INTEGER);
79aceca5 2404/* lwbrx */
9a64fbe4 2405OP_LD_TABLE(wbr);
d9bce9d9 2406GEN_LDX(wbr, 0x16, 0x10, PPC_INTEGER);
79aceca5 2407/* sthbrx */
9a64fbe4 2408OP_ST_TABLE(hbr);
d9bce9d9 2409GEN_STX(hbr, 0x16, 0x1C, PPC_INTEGER);
79aceca5 2410/* stwbrx */
9a64fbe4 2411OP_ST_TABLE(wbr);
d9bce9d9 2412GEN_STX(wbr, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2413
2414/*** Integer load and store multiple ***/
111bfab3 2415#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 2416static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2417 GEN_MEM_FUNCS(lmw),
d9bce9d9 2418};
7863667f
JM		 2419static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2420 GEN_MEM_FUNCS(stmw),
d9bce9d9 2421};
9a64fbe4 2422
79aceca5
FB		 2423/* lmw */
2424GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2425{
76a66253 2426 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2427 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2428 gen_addr_imm_index(ctx, 0);
9a64fbe4 2429 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2430}
2431
2432/* stmw */
2433GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2434{
76a66253 2435 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2436 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 2437 gen_addr_imm_index(ctx, 0);
9a64fbe4 2438 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2439}
2440
2441/*** Integer load and store strings ***/
9a64fbe4
FB		 2442#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2443#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 2444/* string load & stores are by definition endian-safe */
2445#define gen_op_lswi_le_raw gen_op_lswi_raw
2446#define gen_op_lswi_le_user gen_op_lswi_user
2447#define gen_op_lswi_le_kernel gen_op_lswi_kernel
2448#define gen_op_lswi_le_hypv gen_op_lswi_hypv
2449#define gen_op_lswi_le_64_raw gen_op_lswi_raw
2450#define gen_op_lswi_le_64_user gen_op_lswi_user
2451#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2452#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 2453static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2454 GEN_MEM_FUNCS(lswi),
d9bce9d9 2455};
e7c24003
JM		 2456#define gen_op_lswx_le_raw gen_op_lswx_raw
2457#define gen_op_lswx_le_user gen_op_lswx_user
2458#define gen_op_lswx_le_kernel gen_op_lswx_kernel
2459#define gen_op_lswx_le_hypv gen_op_lswx_hypv
2460#define gen_op_lswx_le_64_raw gen_op_lswx_raw
2461#define gen_op_lswx_le_64_user gen_op_lswx_user
2462#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2463#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 2464static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2465 GEN_MEM_FUNCS(lswx),
d9bce9d9 2466};
e7c24003
JM		 2467#define gen_op_stsw_le_raw gen_op_stsw_raw
2468#define gen_op_stsw_le_user gen_op_stsw_user
2469#define gen_op_stsw_le_kernel gen_op_stsw_kernel
2470#define gen_op_stsw_le_hypv gen_op_stsw_hypv
2471#define gen_op_stsw_le_64_raw gen_op_stsw_raw
2472#define gen_op_stsw_le_64_user gen_op_stsw_user
2473#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2474#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 2475static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2476 GEN_MEM_FUNCS(stsw),
9a64fbe4 2477};
9a64fbe4 2478
79aceca5 2479/* lswi */
3fc6c082 2480/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2481 * rA is in the range of registers to be loaded.
2482 * In an other hand, IBM says this is valid, but rA won't be loaded.
2483 * For now, I'll follow the spec...
2484 */
05332d70 2485GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 2486{
2487 int nb = NB(ctx->opcode);
2488 int start = rD(ctx->opcode);
9a64fbe4 2489 int ra = rA(ctx->opcode);
79aceca5
FB		 2490 int nr;
2491
2492 if (nb == 0)
2493 nb = 32;
2494 nr = nb / 4;
76a66253
JM		 2495 if (unlikely(((start + nr) > 32 &&
2496 start <= ra && (start + nr - 32) > ra) ||
2497 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 2498 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2499 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2500 return;
297d8e62 2501 }
8dd4983c 2502 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2503 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 2504 gen_addr_register(ctx);
2505 gen_op_set_T1(nb);
9a64fbe4 2506 op_ldsts(lswi, start);
79aceca5
FB		 2507}
2508
2509/* lswx */
05332d70 2510GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 2511{
9a64fbe4
FB		 2512 int ra = rA(ctx->opcode);
2513 int rb = rB(ctx->opcode);
2514
76a66253 2515 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2516 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2517 gen_addr_reg_index(ctx);
9a64fbe4 2518 if (ra == 0) {
9a64fbe4 2519 ra = rb;
79aceca5 2520 }
9a64fbe4
FB		 2521 gen_op_load_xer_bc();
2522 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 2523}
2524
2525/* stswi */
05332d70 2526GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 2527{
4b3686fa
FB		 2528 int nb = NB(ctx->opcode);
2529
76a66253 2530 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2531 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2532 gen_addr_register(ctx);
4b3686fa
FB		 2533 if (nb == 0)
2534 nb = 32;
2535 gen_op_set_T1(nb);
9a64fbe4 2536 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2537}
2538
2539/* stswx */
05332d70 2540GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 2541{
8dd4983c 2542 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 2543 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 2544 gen_addr_reg_index(ctx);
2545 gen_op_load_xer_bc();
9a64fbe4 2546 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2547}
2548
2549/*** Memory synchronisation ***/
2550/* eieio */
0db1b20e 2551GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 2552{
79aceca5
FB		 2553}
2554
2555/* isync */
0db1b20e 2556GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 2557{
e1833e1f 2558 GEN_STOP(ctx);
79aceca5
FB		 2559}
2560
111bfab3
FB		 2561#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2562#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 2563static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2564 GEN_MEM_FUNCS(lwarx),
111bfab3 2565};
7863667f
JM		 2566static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2567 GEN_MEM_FUNCS(stwcx),
985a19d6 2568};
9a64fbe4 2569
111bfab3 2570/* lwarx */
76a66253 2571GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 2572{
30032c94
JM		 2573 /* NIP cannot be restored if the memory exception comes from an helper */
2574 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2575 gen_addr_reg_index(ctx);
985a19d6 2576 op_lwarx();
79aceca5 2577 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 2578}
2579
2580/* stwcx. */
c7697e1f 2581GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 2582{
30032c94
JM		 2583 /* NIP cannot be restored if the memory exception comes from an helper */
2584 gen_update_nip(ctx, ctx->nip - 4);
76a66253 2585 gen_addr_reg_index(ctx);
9a64fbe4
FB		 2586 gen_op_load_gpr_T1(rS(ctx->opcode));
2587 op_stwcx();
79aceca5
FB		 2588}
2589
426613db
JM		 2590#if defined(TARGET_PPC64)
2591#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2592#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 2593static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2594 GEN_MEM_FUNCS(ldarx),
426613db 2595};
7863667f
JM		 2596static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2597 GEN_MEM_FUNCS(stdcx),
426613db 2598};
426613db
JM		 2599
2600/* ldarx */
a750fc0b 2601GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 2602{
30032c94
JM		 2603 /* NIP cannot be restored if the memory exception comes from an helper */
2604 gen_update_nip(ctx, ctx->nip - 4);
426613db
JM		 2605 gen_addr_reg_index(ctx);
2606 op_ldarx();
2607 gen_op_store_T1_gpr(rD(ctx->opcode));
2608}
2609
2610/* stdcx. */
c7697e1f 2611GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 2612{
30032c94
JM		 2613 /* NIP cannot be restored if the memory exception comes from an helper */
2614 gen_update_nip(ctx, ctx->nip - 4);
426613db
JM		 2615 gen_addr_reg_index(ctx);
2616 gen_op_load_gpr_T1(rS(ctx->opcode));
2617 op_stdcx();
2618}
2619#endif /* defined(TARGET_PPC64) */
2620
79aceca5 2621/* sync */
a902d886 2622GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 2623{
79aceca5
FB		 2624}
2625
0db1b20e
JM		 2626/* wait */
2627GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
2628{
2629 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 2630 gen_op_wait();
2631 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 2632}
2633
79aceca5 2634/*** Floating-point load ***/
477023a6
JM		 2635#define GEN_LDF(width, opc, type) \
2636GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2637{ \
76a66253 2638 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2639 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2640 return; \
2641 } \
9d53c753 2642 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2643 op_ldst(l##width); \
76a66253 2644 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5
FB		 2645}
2646
477023a6
JM		 2647#define GEN_LDUF(width, opc, type) \
2648GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2649{ \
76a66253 2650 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2651 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2652 return; \
2653 } \
76a66253 2654 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2655 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2656 return; \
9a64fbe4 2657 } \
9d53c753 2658 gen_addr_imm_index(ctx, 0); \
9a64fbe4 2659 op_ldst(l##width); \
76a66253 2660 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5 2661 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2662}
2663
477023a6
JM		 2664#define GEN_LDUXF(width, opc, type) \
2665GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2666{ \
76a66253 2667 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2668 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2669 return; \
2670 } \
76a66253 2671 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2672 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2673 return; \
9a64fbe4 2674 } \
76a66253 2675 gen_addr_reg_index(ctx); \
9a64fbe4 2676 op_ldst(l##width); \
76a66253 2677 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5 2678 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2679}
2680
477023a6
JM		 2681#define GEN_LDXF(width, opc2, opc3, type) \
2682GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2683{ \
76a66253 2684 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2685 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2686 return; \
2687 } \
76a66253 2688 gen_addr_reg_index(ctx); \
9a64fbe4 2689 op_ldst(l##width); \
76a66253 2690 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
79aceca5
FB		 2691}
2692
477023a6 2693#define GEN_LDFS(width, op, type) \
9a64fbe4 2694OP_LD_TABLE(width); \
477023a6
JM		 2695GEN_LDF(width, op | 0x20, type); \
2696GEN_LDUF(width, op | 0x21, type); \
2697GEN_LDUXF(width, op | 0x01, type); \
2698GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 2699
2700/* lfd lfdu lfdux lfdx */
477023a6 2701GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 2702/* lfs lfsu lfsux lfsx */
477023a6 2703GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 2704
2705/*** Floating-point store ***/
477023a6
JM		 2706#define GEN_STF(width, opc, type) \
2707GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2708{ \
76a66253 2709 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2710 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2711 return; \
2712 } \
9d53c753 2713 gen_addr_imm_index(ctx, 0); \
76a66253 2714 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 2715 op_ldst(st##width); \
79aceca5
FB		 2716}
2717
477023a6
JM		 2718#define GEN_STUF(width, opc, type) \
2719GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2720{ \
76a66253 2721 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2722 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2723 return; \
2724 } \
76a66253 2725 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2726 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2727 return; \
9a64fbe4 2728 } \
9d53c753 2729 gen_addr_imm_index(ctx, 0); \
76a66253 2730 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 2731 op_ldst(st##width); \
79aceca5 2732 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2733}
2734
477023a6
JM		 2735#define GEN_STUXF(width, opc, type) \
2736GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 2737{ \
76a66253 2738 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2739 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2740 return; \
2741 } \
76a66253 2742 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2743 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2744 return; \
9a64fbe4 2745 } \
76a66253
JM		 2746 gen_addr_reg_index(ctx); \
2747 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 2748 op_ldst(st##width); \
79aceca5 2749 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 2750}
2751
477023a6
JM		 2752#define GEN_STXF(width, opc2, opc3, type) \
2753GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2754{ \
76a66253 2755 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2756 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 2757 return; \
2758 } \
76a66253
JM		 2759 gen_addr_reg_index(ctx); \
2760 gen_op_load_fpr_FT0(rS(ctx->opcode)); \
9a64fbe4 2761 op_ldst(st##width); \
79aceca5
FB		 2762}
2763
477023a6 2764#define GEN_STFS(width, op, type) \
9a64fbe4 2765OP_ST_TABLE(width); \
477023a6
JM		 2766GEN_STF(width, op | 0x20, type); \
2767GEN_STUF(width, op | 0x21, type); \
2768GEN_STUXF(width, op | 0x01, type); \
2769GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 2770
2771/* stfd stfdu stfdux stfdx */
477023a6 2772GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 2773/* stfs stfsu stfsux stfsx */
477023a6 2774GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 2775
2776/* Optional: */
2777/* stfiwx */
5b8105fa
JM		 2778OP_ST_TABLE(fiw);
2779GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 2780
2781/*** Branch ***/
b068d6a7
JM		 2782static always_inline void gen_goto_tb (DisasContext *ctx, int n,
2783 target_ulong dest)
c1942362
FB		 2784{
2785 TranslationBlock *tb;
2786 tb = ctx->tb;
57fec1fe
FB		 2787 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
2788 !ctx->singlestep_enabled) {
2789 tcg_gen_goto_tb(n);
d9bce9d9
JM		 2790 gen_set_T1(dest);
2791#if defined(TARGET_PPC64)
2792 if (ctx->sf_mode)
2793 gen_op_b_T1_64();
2794 else
2795#endif
2796 gen_op_b_T1();
57fec1fe 2797 tcg_gen_exit_tb((long)tb + n);
c1942362 2798 } else {
d9bce9d9
JM		 2799 gen_set_T1(dest);
2800#if defined(TARGET_PPC64)
2801 if (ctx->sf_mode)
2802 gen_op_b_T1_64();
2803 else
2804#endif
2805 gen_op_b_T1();
ea4e754f
FB		 2806 if (ctx->singlestep_enabled)
2807 gen_op_debug();
57fec1fe 2808 tcg_gen_exit_tb(0);
c1942362 2809 }
c53be334
FB		 2810}
2811
b068d6a7 2812static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 2813{
2814#if defined(TARGET_PPC64)
2815 if (ctx->sf_mode != 0 && (nip >> 32))
2816 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
2817 else
2818#endif
2819 gen_op_setlr(ctx->nip);
2820}
2821
79aceca5
FB		 2822/* b ba bl bla */
2823GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
2824{
76a66253 2825 target_ulong li, target;
38a64f9d
FB		 2826
2827 /* sign extend LI */
76a66253 2828#if defined(TARGET_PPC64)
d9bce9d9
JM		 2829 if (ctx->sf_mode)
2830 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
2831 else
76a66253 2832#endif
d9bce9d9 2833 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 2834 if (likely(AA(ctx->opcode) == 0))
046d6672 2835 target = ctx->nip + li - 4;
79aceca5 2836 else
9a64fbe4 2837 target = li;
d9bce9d9 2838#if defined(TARGET_PPC64)
e1833e1f
JM		 2839 if (!ctx->sf_mode)
2840 target = (uint32_t)target;
d9bce9d9 2841#endif
e1833e1f
JM		 2842 if (LK(ctx->opcode))
2843 gen_setlr(ctx, ctx->nip);
c1942362 2844 gen_goto_tb(ctx, 0, target);
e1833e1f 2845 ctx->exception = POWERPC_EXCP_BRANCH;
79aceca5
FB		 2846}
2847
e98a6e40
FB		 2848#define BCOND_IM 0
2849#define BCOND_LR 1
2850#define BCOND_CTR 2
2851
b068d6a7 2852static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 2853{
76a66253
JM		 2854 target_ulong target = 0;
2855 target_ulong li;
d9bce9d9
JM		 2856 uint32_t bo = BO(ctx->opcode);
2857 uint32_t bi = BI(ctx->opcode);
2858 uint32_t mask;
e98a6e40 2859
e98a6e40 2860 if ((bo & 0x4) == 0)
d9bce9d9 2861 gen_op_dec_ctr();
e98a6e40
FB		 2862 switch(type) {
2863 case BCOND_IM:
76a66253
JM		 2864 li = (target_long)((int16_t)(BD(ctx->opcode)));
2865 if (likely(AA(ctx->opcode) == 0)) {
046d6672 2866 target = ctx->nip + li - 4;
e98a6e40
FB		 2867 } else {
2868 target = li;
2869 }
e1833e1f
JM		 2870#if defined(TARGET_PPC64)
2871 if (!ctx->sf_mode)
2872 target = (uint32_t)target;
2873#endif
e98a6e40
FB		 2874 break;
2875 case BCOND_CTR:
2876 gen_op_movl_T1_ctr();
2877 break;
2878 default:
2879 case BCOND_LR:
2880 gen_op_movl_T1_lr();
2881 break;
2882 }
e1833e1f
JM		 2883 if (LK(ctx->opcode))
2884 gen_setlr(ctx, ctx->nip);
e98a6e40 2885 if (bo & 0x10) {
d9bce9d9
JM		 2886 /* No CR condition */
2887 switch (bo & 0x6) {
2888 case 0:
2889#if defined(TARGET_PPC64)
2890 if (ctx->sf_mode)
2891 gen_op_test_ctr_64();
2892 else
2893#endif
2894 gen_op_test_ctr();
2895 break;
2896 case 2:
2897#if defined(TARGET_PPC64)
2898 if (ctx->sf_mode)
2899 gen_op_test_ctrz_64();
2900 else
2901#endif
2902 gen_op_test_ctrz();
e98a6e40 2903 break;
e98a6e40 2904 default:
d9bce9d9
JM		 2905 case 4:
2906 case 6:
e98a6e40 2907 if (type == BCOND_IM) {
c1942362 2908 gen_goto_tb(ctx, 0, target);
056b05f8 2909 goto out;
e98a6e40 2910 } else {
d9bce9d9
JM		 2911#if defined(TARGET_PPC64)
2912 if (ctx->sf_mode)
2913 gen_op_b_T1_64();
2914 else
2915#endif
2916 gen_op_b_T1();
056b05f8 2917 goto no_test;
e98a6e40 2918 }
056b05f8 2919 break;
e98a6e40 2920 }
d9bce9d9
JM		 2921 } else {
2922 mask = 1 << (3 - (bi & 0x03));
2923 gen_op_load_crf_T0(bi >> 2);
2924 if (bo & 0x8) {
2925 switch (bo & 0x6) {
2926 case 0:
2927#if defined(TARGET_PPC64)
2928 if (ctx->sf_mode)
2929 gen_op_test_ctr_true_64(mask);
2930 else
2931#endif
2932 gen_op_test_ctr_true(mask);
2933 break;
2934 case 2:
2935#if defined(TARGET_PPC64)
2936 if (ctx->sf_mode)
2937 gen_op_test_ctrz_true_64(mask);
2938 else
2939#endif
2940 gen_op_test_ctrz_true(mask);
2941 break;
2942 default:
2943 case 4:
2944 case 6:
e98a6e40 2945 gen_op_test_true(mask);
d9bce9d9
JM		 2946 break;
2947 }
2948 } else {
2949 switch (bo & 0x6) {
2950 case 0:
2951#if defined(TARGET_PPC64)
2952 if (ctx->sf_mode)
2953 gen_op_test_ctr_false_64(mask);
2954 else
2955#endif
2956 gen_op_test_ctr_false(mask);
3b46e624 2957 break;
d9bce9d9
JM		 2958 case 2:
2959#if defined(TARGET_PPC64)
2960 if (ctx->sf_mode)
2961 gen_op_test_ctrz_false_64(mask);
2962 else
2963#endif
2964 gen_op_test_ctrz_false(mask);
2965 break;
e98a6e40 2966 default:
d9bce9d9
JM		 2967 case 4:
2968 case 6:
e98a6e40 2969 gen_op_test_false(mask);
d9bce9d9
JM		 2970 break;
2971 }
2972 }
2973 }
e98a6e40 2974 if (type == BCOND_IM) {
c53be334
FB		 2975 int l1 = gen_new_label();
2976 gen_op_jz_T0(l1);
c1942362 2977 gen_goto_tb(ctx, 0, target);
c53be334 2978 gen_set_label(l1);
c1942362 2979 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 2980 } else {
d9bce9d9
JM		 2981#if defined(TARGET_PPC64)
2982 if (ctx->sf_mode)
2983 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
2984 else
2985#endif
2986 gen_op_btest_T1(ctx->nip);
36081602 2987 no_test:
08e46e54
JM		 2988 if (ctx->singlestep_enabled)
2989 gen_op_debug();
57fec1fe 2990 tcg_gen_exit_tb(0);
08e46e54 2991 }
056b05f8 2992 out:
e1833e1f 2993 ctx->exception = POWERPC_EXCP_BRANCH;
e98a6e40
FB		 2994}
2995
2996GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 2997{
e98a6e40
FB		 2998 gen_bcond(ctx, BCOND_IM);
2999}
3000
3001GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3002{
e98a6e40
FB		 3003 gen_bcond(ctx, BCOND_CTR);
3004}
3005
3006GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3007{
e98a6e40
FB		 3008 gen_bcond(ctx, BCOND_LR);
3009}
79aceca5
FB		 3010
3011/*** Condition register logical ***/
3012#define GEN_CRLOGIC(op, opc) \
3013GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
3014{ \
fc0d441e
JM		 3015 uint8_t bitmask; \
3016 int sh; \
79aceca5 3017 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
fc0d441e
JM		 3018 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3019 if (sh > 0) \
3020 gen_op_srli_T0(sh); \
3021 else if (sh < 0) \
3022 gen_op_sli_T0(-sh); \
79aceca5 3023 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
fc0d441e
JM		 3024 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3025 if (sh > 0) \
3026 gen_op_srli_T1(sh); \
3027 else if (sh < 0) \
3028 gen_op_sli_T1(-sh); \
79aceca5 3029 gen_op_##op(); \
fc0d441e
JM		 3030 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3031 gen_op_andi_T0(bitmask); \
79aceca5 3032 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
fc0d441e
JM		 3033 gen_op_andi_T1(~bitmask); \
3034 gen_op_or(); \
3035 gen_op_store_T0_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 3036}
3037
3038/* crand */
76a66253 3039GEN_CRLOGIC(and, 0x08);
79aceca5 3040/* crandc */
76a66253 3041GEN_CRLOGIC(andc, 0x04);
79aceca5 3042/* creqv */
76a66253 3043GEN_CRLOGIC(eqv, 0x09);
79aceca5 3044/* crnand */
76a66253 3045GEN_CRLOGIC(nand, 0x07);
79aceca5 3046/* crnor */
76a66253 3047GEN_CRLOGIC(nor, 0x01);
79aceca5 3048/* cror */
76a66253 3049GEN_CRLOGIC(or, 0x0E);
79aceca5 3050/* crorc */
76a66253 3051GEN_CRLOGIC(orc, 0x0D);
79aceca5 3052/* crxor */
76a66253 3053GEN_CRLOGIC(xor, 0x06);
79aceca5
FB		 3054/* mcrf */
3055GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3056{
3057 gen_op_load_crf_T0(crfS(ctx->opcode));
3058 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 3059}
3060
3061/*** System linkage ***/
3062/* rfi (supervisor only) */
76a66253 3063GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3064{
9a64fbe4 3065#if defined(CONFIG_USER_ONLY)
e1833e1f 3066 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3067#else
3068 /* Restore CPU state */
76a66253 3069 if (unlikely(!ctx->supervisor)) {
e1833e1f 3070 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3071 return;
9a64fbe4 3072 }
a42bd6cc 3073 gen_op_rfi();
e1833e1f 3074 GEN_SYNC(ctx);
9a64fbe4 3075#endif
79aceca5
FB		 3076}
3077
426613db 3078#if defined(TARGET_PPC64)
a750fc0b 3079GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3080{
3081#if defined(CONFIG_USER_ONLY)
e1833e1f 3082 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3083#else
3084 /* Restore CPU state */
3085 if (unlikely(!ctx->supervisor)) {
e1833e1f 3086 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3087 return;
3088 }
a42bd6cc 3089 gen_op_rfid();
e1833e1f 3090 GEN_SYNC(ctx);
426613db
JM		 3091#endif
3092}
426613db 3093
5b8105fa 3094GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3095{
3096#if defined(CONFIG_USER_ONLY)
3097 GEN_EXCP_PRIVOPC(ctx);
3098#else
3099 /* Restore CPU state */
3100 if (unlikely(ctx->supervisor <= 1)) {
3101 GEN_EXCP_PRIVOPC(ctx);
3102 return;
3103 }
3104 gen_op_hrfid();
3105 GEN_SYNC(ctx);
3106#endif
3107}
3108#endif
3109
79aceca5 3110/* sc */
417bf010
JM		 3111#if defined(CONFIG_USER_ONLY)
3112#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3113#else
3114#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3115#endif
e1833e1f 3116GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3117{
e1833e1f
JM		 3118 uint32_t lev;
3119
3120 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3121 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3122}
3123
3124/*** Trap ***/
3125/* tw */
76a66253 3126GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3127{
9a64fbe4
FB		 3128 gen_op_load_gpr_T0(rA(ctx->opcode));
3129 gen_op_load_gpr_T1(rB(ctx->opcode));
a0ae05aa 3130 /* Update the nip since this might generate a trap exception */
d9bce9d9 3131 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3132 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3133}
3134
3135/* twi */
3136GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3137{
9a64fbe4 3138 gen_op_load_gpr_T0(rA(ctx->opcode));
d9bce9d9
JM		 3139 gen_set_T1(SIMM(ctx->opcode));
3140 /* Update the nip since this might generate a trap exception */
3141 gen_update_nip(ctx, ctx->nip);
76a66253 3142 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3143}
3144
d9bce9d9
JM		 3145#if defined(TARGET_PPC64)
3146/* td */
3147GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3148{
3149 gen_op_load_gpr_T0(rA(ctx->opcode));
3150 gen_op_load_gpr_T1(rB(ctx->opcode));
3151 /* Update the nip since this might generate a trap exception */
3152 gen_update_nip(ctx, ctx->nip);
3153 gen_op_td(TO(ctx->opcode));
3154}
3155
3156/* tdi */
3157GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3158{
3159 gen_op_load_gpr_T0(rA(ctx->opcode));
3160 gen_set_T1(SIMM(ctx->opcode));
3161 /* Update the nip since this might generate a trap exception */
3162 gen_update_nip(ctx, ctx->nip);
3163 gen_op_td(TO(ctx->opcode));
3164}
3165#endif
3166
79aceca5 3167/*** Processor control ***/
79aceca5
FB		 3168/* mcrxr */
3169GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3170{
3171 gen_op_load_xer_cr();
3172 gen_op_store_T0_crf(crfD(ctx->opcode));
e864cabd
JM		 3173 gen_op_clear_xer_ov();
3174 gen_op_clear_xer_ca();
79aceca5
FB		 3175}
3176
3177/* mfcr */
76a66253 3178GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3179{
76a66253 3180 uint32_t crm, crn;
3b46e624 3181
76a66253
JM		 3182 if (likely(ctx->opcode & 0x00100000)) {
3183 crm = CRM(ctx->opcode);
3184 if (likely((crm ^ (crm - 1)) == 0)) {
3185 crn = ffs(crm);
3186 gen_op_load_cro(7 - crn);
3187 }
d9bce9d9
JM		 3188 } else {
3189 gen_op_load_cr();
3190 }
79aceca5 3191 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 3192}
3193
3194/* mfmsr */
3195GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3196{
9a64fbe4 3197#if defined(CONFIG_USER_ONLY)
e1833e1f 3198 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3199#else
76a66253 3200 if (unlikely(!ctx->supervisor)) {
e1833e1f 3201 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3202 return;
9a64fbe4 3203 }
79aceca5
FB		 3204 gen_op_load_msr();
3205 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 3206#endif
79aceca5
FB		 3207}
3208
a11b8151 3209#if 1
6f2d8978 3210#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3211#else
3212static void spr_noaccess (void *opaque, int sprn)
3213{
3214 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3215 printf("ERROR: try to access SPR %d !\n", sprn);
3216}
3217#define SPR_NOACCESS (&spr_noaccess)
3218#endif
3219
79aceca5 3220/* mfspr */
b068d6a7 3221static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3222{
3fc6c082 3223 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3224 uint32_t sprn = SPR(ctx->opcode);
3225
3fc6c082 3226#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3227 if (ctx->supervisor == 2)
3228 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3229 else if (ctx->supervisor)
3fc6c082
FB		 3230 read_cb = ctx->spr_cb[sprn].oea_read;
3231 else
9a64fbe4 3232#endif
3fc6c082 3233 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3234 if (likely(read_cb != NULL)) {
3235 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082
FB		 3236 (*read_cb)(ctx, sprn);
3237 gen_op_store_T0_gpr(rD(ctx->opcode));
3238 } else {
3239 /* Privilege exception */
9fceefa7
JM		 3240 /* This is a hack to avoid warnings when running Linux:
3241 * this OS breaks the PowerPC virtualisation model,
3242 * allowing userland application to read the PVR
3243 */
3244 if (sprn != SPR_PVR) {
3245 if (loglevel != 0) {
6b542af7 3246 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3247 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3248 }
077fc206
JM		 3249 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3250 sprn, sprn, ctx->nip);
f24e5695 3251 }
e1833e1f 3252 GEN_EXCP_PRIVREG(ctx);
79aceca5 3253 }
3fc6c082
FB		 3254 } else {
3255 /* Not defined */
4a057712 3256 if (loglevel != 0) {
077fc206
JM		 3257 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3258 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3259 }
077fc206
JM		 3260 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3261 sprn, sprn, ctx->nip);
e1833e1f
JM		 3262 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3263 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3264 }
79aceca5
FB		 3265}
3266
3fc6c082 3267GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3268{
3fc6c082 3269 gen_op_mfspr(ctx);
76a66253 3270}
3fc6c082
FB		 3271
3272/* mftb */
a750fc0b 3273GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3274{
3275 gen_op_mfspr(ctx);
79aceca5
FB		 3276}
3277
3278/* mtcrf */
8dd4983c 3279GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3280{
76a66253 3281 uint32_t crm, crn;
3b46e624 3282
79aceca5 3283 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 3284 crm = CRM(ctx->opcode);
3285 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3286 crn = ffs(crm);
3287 gen_op_srli_T0(crn * 4);
3288 gen_op_andi_T0(0xF);
3289 gen_op_store_cro(7 - crn);
3290 } else {
3291 gen_op_store_cr(crm);
3292 }
79aceca5
FB		 3293}
3294
3295/* mtmsr */
426613db 3296#if defined(TARGET_PPC64)
be147d08 3297GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3298{
3299#if defined(CONFIG_USER_ONLY)
e1833e1f 3300 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3301#else
3302 if (unlikely(!ctx->supervisor)) {
e1833e1f 3303 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3304 return;
3305 }
426613db 3306 gen_op_load_gpr_T0(rS(ctx->opcode));
be147d08
JM		 3307 if (ctx->opcode & 0x00010000) {
3308 /* Special form that does not need any synchronisation */
3309 gen_op_update_riee();
3310 } else {
056b05f8
JM		 3311 /* XXX: we need to update nip before the store
3312 * if we enter power saving mode, we will exit the loop
3313 * directly from ppc_store_msr
3314 */
be147d08
JM		 3315 gen_update_nip(ctx, ctx->nip);
3316 gen_op_store_msr();
3317 /* Must stop the translation as machine state (may have) changed */
3318 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3319 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3320 }
426613db
JM		 3321#endif
3322}
3323#endif
3324
79aceca5
FB		 3325GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3326{
9a64fbe4 3327#if defined(CONFIG_USER_ONLY)
e1833e1f 3328 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3329#else
76a66253 3330 if (unlikely(!ctx->supervisor)) {
e1833e1f 3331 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3332 return;
9a64fbe4 3333 }
79aceca5 3334 gen_op_load_gpr_T0(rS(ctx->opcode));
be147d08
JM		 3335 if (ctx->opcode & 0x00010000) {
3336 /* Special form that does not need any synchronisation */
3337 gen_op_update_riee();
3338 } else {
056b05f8
JM		 3339 /* XXX: we need to update nip before the store
3340 * if we enter power saving mode, we will exit the loop
3341 * directly from ppc_store_msr
3342 */
be147d08 3343 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3344#if defined(TARGET_PPC64)
be147d08
JM		 3345 if (!ctx->sf_mode)
3346 gen_op_store_msr_32();
3347 else
d9bce9d9 3348#endif
be147d08
JM		 3349 gen_op_store_msr();
3350 /* Must stop the translation as machine state (may have) changed */
3351 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3352 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3353 }
9a64fbe4 3354#endif
79aceca5
FB		 3355}
3356
3357/* mtspr */
3358GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3359{
3fc6c082 3360 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3361 uint32_t sprn = SPR(ctx->opcode);
3362
3fc6c082 3363#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3364 if (ctx->supervisor == 2)
3365 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3366 else if (ctx->supervisor)
3fc6c082
FB		 3367 write_cb = ctx->spr_cb[sprn].oea_write;
3368 else
9a64fbe4 3369#endif
3fc6c082 3370 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3371 if (likely(write_cb != NULL)) {
3372 if (likely(write_cb != SPR_NOACCESS)) {
3fc6c082
FB		 3373 gen_op_load_gpr_T0(rS(ctx->opcode));
3374 (*write_cb)(ctx, sprn);
3375 } else {
3376 /* Privilege exception */
4a057712 3377 if (loglevel != 0) {
077fc206
JM		 3378 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3379 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3380 }
077fc206
JM		 3381 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3382 sprn, sprn, ctx->nip);
e1833e1f 3383 GEN_EXCP_PRIVREG(ctx);
76a66253 3384 }
3fc6c082
FB		 3385 } else {
3386 /* Not defined */
4a057712 3387 if (loglevel != 0) {
077fc206
JM		 3388 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3389 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3390 }
077fc206
JM		 3391 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3392 sprn, sprn, ctx->nip);
e1833e1f
JM		 3393 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3394 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3395 }
79aceca5
FB		 3396}
3397
3398/*** Cache management ***/
79aceca5 3399/* dcbf */
0db1b20e 3400GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3401{
dac454af 3402 /* XXX: specification says this is treated as a load by the MMU */
76a66253 3403 gen_addr_reg_index(ctx);
a541f297 3404 op_ldst(lbz);
79aceca5
FB		 3405}
3406
3407/* dcbi (Supervisor only) */
9a64fbe4 3408GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3409{
a541f297 3410#if defined(CONFIG_USER_ONLY)
e1833e1f 3411 GEN_EXCP_PRIVOPC(ctx);
a541f297 3412#else
76a66253 3413 if (unlikely(!ctx->supervisor)) {
e1833e1f 3414 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3415 return;
9a64fbe4 3416 }
76a66253
JM		 3417 gen_addr_reg_index(ctx);
3418 /* XXX: specification says this should be treated as a store by the MMU */
dac454af 3419 op_ldst(lbz);
a541f297
FB		 3420 op_ldst(stb);
3421#endif
79aceca5
FB		 3422}
3423
3424/* dcdst */
9a64fbe4 3425GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3426{
76a66253
JM		 3427 /* XXX: specification say this is treated as a load by the MMU */
3428 gen_addr_reg_index(ctx);
a541f297 3429 op_ldst(lbz);
79aceca5
FB		 3430}
3431
3432/* dcbt */
0db1b20e 3433GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3434{
0db1b20e 3435 /* interpreted as no-op */
76a66253
JM		 3436 /* XXX: specification say this is treated as a load by the MMU
3437 * but does not generate any exception
3438 */
79aceca5
FB		 3439}
3440
3441/* dcbtst */
0db1b20e 3442GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3443{
0db1b20e 3444 /* interpreted as no-op */
76a66253
JM		 3445 /* XXX: specification say this is treated as a load by the MMU
3446 * but does not generate any exception
3447 */
79aceca5
FB		 3448}
3449
3450/* dcbz */
d63001d1 3451#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 3452static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3453 /* 32 bytes cache line size */
d63001d1 3454 {
7863667f
JM		 3455#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3456#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3457#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3458#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3459#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3460#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3461#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3462#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3463 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 3464 },
7863667f 3465 /* 64 bytes cache line size */
d63001d1 3466 {
7863667f
JM		 3467#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3468#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3469#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3470#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3471#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3472#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3473#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3474#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3475 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 3476 },
7863667f 3477 /* 128 bytes cache line size */
d63001d1 3478 {
7863667f
JM		 3479#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3480#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3481#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3482#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3483#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3484#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3485#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3486#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3487 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 3488 },
7863667f 3489 /* tunable cache line size */
d63001d1 3490 {
7863667f
JM		 3491#define gen_op_dcbz_le_raw gen_op_dcbz_raw
3492#define gen_op_dcbz_le_user gen_op_dcbz_user
3493#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3494#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3495#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3496#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3497#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3498#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3499 GEN_MEM_FUNCS(dcbz),
d63001d1 3500 },
76a66253 3501};
9a64fbe4 3502
b068d6a7
JM		 3503static always_inline void handler_dcbz (DisasContext *ctx,
3504 int dcache_line_size)
d63001d1
JM		 3505{
3506 int n;
3507
3508 switch (dcache_line_size) {
3509 case 32:
3510 n = 0;
3511 break;
3512 case 64:
3513 n = 1;
3514 break;
3515 case 128:
3516 n = 2;
3517 break;
3518 default:
3519 n = 3;
3520 break;
3521 }
3522 op_dcbz(n);
3523}
3524
3525GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 3526{
76a66253 3527 gen_addr_reg_index(ctx);
d63001d1
JM		 3528 handler_dcbz(ctx, ctx->dcache_line_size);
3529 gen_op_check_reservation();
3530}
3531
c7697e1f 3532GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1
JM		 3533{
3534 gen_addr_reg_index(ctx);
3535 if (ctx->opcode & 0x00200000)
3536 handler_dcbz(ctx, ctx->dcache_line_size);
3537 else
3538 handler_dcbz(ctx, -1);
4b3686fa 3539 gen_op_check_reservation();
79aceca5
FB		 3540}
3541
3542/* icbi */
36f69651 3543#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 3544#define gen_op_icbi_le_raw gen_op_icbi_raw
3545#define gen_op_icbi_le_user gen_op_icbi_user
3546#define gen_op_icbi_le_kernel gen_op_icbi_kernel
3547#define gen_op_icbi_le_hypv gen_op_icbi_hypv
3548#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3549#define gen_op_icbi_le_64_user gen_op_icbi_64_user
3550#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3551#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3552static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3553 GEN_MEM_FUNCS(icbi),
36f69651 3554};
e1833e1f 3555
1b413d55 3556GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 3557{
30032c94
JM		 3558 /* NIP cannot be restored if the memory exception comes from an helper */
3559 gen_update_nip(ctx, ctx->nip - 4);
76a66253 3560 gen_addr_reg_index(ctx);
36f69651 3561 op_icbi();
79aceca5
FB		 3562}
3563
3564/* Optional: */
3565/* dcba */
a750fc0b 3566GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 3567{
0db1b20e
JM		 3568 /* interpreted as no-op */
3569 /* XXX: specification say this is treated as a store by the MMU
3570 * but does not generate any exception
3571 */
79aceca5
FB		 3572}
3573
3574/*** Segment register manipulation ***/
3575/* Supervisor only: */
3576/* mfsr */
3577GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
3578{
9a64fbe4 3579#if defined(CONFIG_USER_ONLY)
e1833e1f 3580 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3581#else
76a66253 3582 if (unlikely(!ctx->supervisor)) {
e1833e1f 3583 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3584 return;
9a64fbe4 3585 }
76a66253
JM		 3586 gen_op_set_T1(SR(ctx->opcode));
3587 gen_op_load_sr();
9a64fbe4
FB		 3588 gen_op_store_T0_gpr(rD(ctx->opcode));
3589#endif
79aceca5
FB		 3590}
3591
3592/* mfsrin */
9a64fbe4 3593GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 3594{
9a64fbe4 3595#if defined(CONFIG_USER_ONLY)
e1833e1f 3596 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3597#else
76a66253 3598 if (unlikely(!ctx->supervisor)) {
e1833e1f 3599 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3600 return;
9a64fbe4
FB		 3601 }
3602 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 3603 gen_op_srli_T1(28);
3604 gen_op_load_sr();
9a64fbe4
FB		 3605 gen_op_store_T0_gpr(rD(ctx->opcode));
3606#endif
79aceca5
FB		 3607}
3608
3609/* mtsr */
e63c59cb 3610GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 3611{
9a64fbe4 3612#if defined(CONFIG_USER_ONLY)
e1833e1f 3613 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3614#else
76a66253 3615 if (unlikely(!ctx->supervisor)) {
e1833e1f 3616 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3617 return;
9a64fbe4
FB		 3618 }
3619 gen_op_load_gpr_T0(rS(ctx->opcode));
76a66253
JM		 3620 gen_op_set_T1(SR(ctx->opcode));
3621 gen_op_store_sr();
9a64fbe4 3622#endif
79aceca5
FB		 3623}
3624
3625/* mtsrin */
9a64fbe4 3626GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 3627{
9a64fbe4 3628#if defined(CONFIG_USER_ONLY)
e1833e1f 3629 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3630#else
76a66253 3631 if (unlikely(!ctx->supervisor)) {
e1833e1f 3632 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3633 return;
9a64fbe4
FB		 3634 }
3635 gen_op_load_gpr_T0(rS(ctx->opcode));
3636 gen_op_load_gpr_T1(rB(ctx->opcode));
76a66253
JM		 3637 gen_op_srli_T1(28);
3638 gen_op_store_sr();
9a64fbe4 3639#endif
79aceca5
FB		 3640}
3641
12de9a39
JM		 3642#if defined(TARGET_PPC64)
3643/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
3644/* mfsr */
c7697e1f 3645GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 3646{
3647#if defined(CONFIG_USER_ONLY)
3648 GEN_EXCP_PRIVREG(ctx);
3649#else
3650 if (unlikely(!ctx->supervisor)) {
3651 GEN_EXCP_PRIVREG(ctx);
3652 return;
3653 }
3654 gen_op_set_T1(SR(ctx->opcode));
3655 gen_op_load_slb();
3656 gen_op_store_T0_gpr(rD(ctx->opcode));
3657#endif
3658}
3659
3660/* mfsrin */
c7697e1f
JM		 3661GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
3662 PPC_SEGMENT_64B)
12de9a39
JM		 3663{
3664#if defined(CONFIG_USER_ONLY)
3665 GEN_EXCP_PRIVREG(ctx);
3666#else
3667 if (unlikely(!ctx->supervisor)) {
3668 GEN_EXCP_PRIVREG(ctx);
3669 return;
3670 }
3671 gen_op_load_gpr_T1(rB(ctx->opcode));
3672 gen_op_srli_T1(28);
3673 gen_op_load_slb();
3674 gen_op_store_T0_gpr(rD(ctx->opcode));
3675#endif
3676}
3677
3678/* mtsr */
c7697e1f 3679GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 3680{
3681#if defined(CONFIG_USER_ONLY)
3682 GEN_EXCP_PRIVREG(ctx);
3683#else
3684 if (unlikely(!ctx->supervisor)) {
3685 GEN_EXCP_PRIVREG(ctx);
3686 return;
3687 }
3688 gen_op_load_gpr_T0(rS(ctx->opcode));
3689 gen_op_set_T1(SR(ctx->opcode));
3690 gen_op_store_slb();
3691#endif
3692}
3693
3694/* mtsrin */
c7697e1f
JM		 3695GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
3696 PPC_SEGMENT_64B)
12de9a39
JM		 3697{
3698#if defined(CONFIG_USER_ONLY)
3699 GEN_EXCP_PRIVREG(ctx);
3700#else
3701 if (unlikely(!ctx->supervisor)) {
3702 GEN_EXCP_PRIVREG(ctx);
3703 return;
3704 }
3705 gen_op_load_gpr_T0(rS(ctx->opcode));
3706 gen_op_load_gpr_T1(rB(ctx->opcode));
3707 gen_op_srli_T1(28);
3708 gen_op_store_slb();
3709#endif
3710}
3711#endif /* defined(TARGET_PPC64) */
3712
79aceca5
FB		 3713/*** Lookaside buffer management ***/
3714/* Optional & supervisor only: */
3715/* tlbia */
3fc6c082 3716GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 3717{
9a64fbe4 3718#if defined(CONFIG_USER_ONLY)
e1833e1f 3719 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3720#else
76a66253 3721 if (unlikely(!ctx->supervisor)) {
e1833e1f 3722 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3723 return;
9a64fbe4
FB		 3724 }
3725 gen_op_tlbia();
3726#endif
79aceca5
FB		 3727}
3728
3729/* tlbie */
76a66253 3730GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 3731{
9a64fbe4 3732#if defined(CONFIG_USER_ONLY)
e1833e1f 3733 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3734#else
76a66253 3735 if (unlikely(!ctx->supervisor)) {
e1833e1f 3736 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3737 return;
9a64fbe4
FB		 3738 }
3739 gen_op_load_gpr_T0(rB(ctx->opcode));
d9bce9d9
JM		 3740#if defined(TARGET_PPC64)
3741 if (ctx->sf_mode)
3742 gen_op_tlbie_64();
3743 else
3744#endif
3745 gen_op_tlbie();
9a64fbe4 3746#endif
79aceca5
FB		 3747}
3748
3749/* tlbsync */
76a66253 3750GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 3751{
9a64fbe4 3752#if defined(CONFIG_USER_ONLY)
e1833e1f 3753 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 3754#else
76a66253 3755 if (unlikely(!ctx->supervisor)) {
e1833e1f 3756 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3757 return;
9a64fbe4
FB		 3758 }
3759 /* This has no effect: it should ensure that all previous
3760 * tlbie have completed
3761 */
e1833e1f 3762 GEN_STOP(ctx);
9a64fbe4 3763#endif
79aceca5
FB		 3764}
3765
426613db
JM		 3766#if defined(TARGET_PPC64)
3767/* slbia */
3768GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
3769{
3770#if defined(CONFIG_USER_ONLY)
e1833e1f 3771 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3772#else
3773 if (unlikely(!ctx->supervisor)) {
e1833e1f 3774 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3775 return;
3776 }
3777 gen_op_slbia();
426613db
JM		 3778#endif
3779}
3780
3781/* slbie */
3782GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
3783{
3784#if defined(CONFIG_USER_ONLY)
e1833e1f 3785 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3786#else
3787 if (unlikely(!ctx->supervisor)) {
e1833e1f 3788 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3789 return;
3790 }
3791 gen_op_load_gpr_T0(rB(ctx->opcode));
3792 gen_op_slbie();
426613db
JM		 3793#endif
3794}
3795#endif
3796
79aceca5
FB		 3797/*** External control ***/
3798/* Optional: */
9a64fbe4
FB		 3799#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
3800#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 3801static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
3802 GEN_MEM_FUNCS(eciwx),
111bfab3 3803};
7863667f
JM		 3804static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
3805 GEN_MEM_FUNCS(ecowx),
111bfab3 3806};
9a64fbe4 3807
111bfab3 3808/* eciwx */
79aceca5
FB		 3809GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
3810{
9a64fbe4 3811 /* Should check EAR[E] & alignment ! */
76a66253
JM		 3812 gen_addr_reg_index(ctx);
3813 op_eciwx();
3814 gen_op_store_T0_gpr(rD(ctx->opcode));
3815}
3816
3817/* ecowx */
3818GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
3819{
3820 /* Should check EAR[E] & alignment ! */
3821 gen_addr_reg_index(ctx);
3822 gen_op_load_gpr_T1(rS(ctx->opcode));
3823 op_ecowx();
3824}
3825
3826/* PowerPC 601 specific instructions */
3827/* abs - abs. */
3828GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
3829{
3830 gen_op_load_gpr_T0(rA(ctx->opcode));
3831 gen_op_POWER_abs();
3832 gen_op_store_T0_gpr(rD(ctx->opcode));
3833 if (unlikely(Rc(ctx->opcode) != 0))
3834 gen_set_Rc0(ctx);
3835}
3836
3837/* abso - abso. */
3838GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
3839{
3840 gen_op_load_gpr_T0(rA(ctx->opcode));
3841 gen_op_POWER_abso();
3842 gen_op_store_T0_gpr(rD(ctx->opcode));
3843 if (unlikely(Rc(ctx->opcode) != 0))
3844 gen_set_Rc0(ctx);
3845}
3846
3847/* clcs */
a750fc0b 3848GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253
JM		 3849{
3850 gen_op_load_gpr_T0(rA(ctx->opcode));
3851 gen_op_POWER_clcs();
c7697e1f 3852 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 3853 gen_op_store_T0_gpr(rD(ctx->opcode));
3854}
3855
3856/* div - div. */
3857GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
3858{
3859 gen_op_load_gpr_T0(rA(ctx->opcode));
3860 gen_op_load_gpr_T1(rB(ctx->opcode));
3861 gen_op_POWER_div();
3862 gen_op_store_T0_gpr(rD(ctx->opcode));
3863 if (unlikely(Rc(ctx->opcode) != 0))
3864 gen_set_Rc0(ctx);
3865}
3866
3867/* divo - divo. */
3868GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
3869{
3870 gen_op_load_gpr_T0(rA(ctx->opcode));
3871 gen_op_load_gpr_T1(rB(ctx->opcode));
3872 gen_op_POWER_divo();
3873 gen_op_store_T0_gpr(rD(ctx->opcode));
3874 if (unlikely(Rc(ctx->opcode) != 0))
3875 gen_set_Rc0(ctx);
3876}
3877
3878/* divs - divs. */
3879GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
3880{
3881 gen_op_load_gpr_T0(rA(ctx->opcode));
3882 gen_op_load_gpr_T1(rB(ctx->opcode));
3883 gen_op_POWER_divs();
3884 gen_op_store_T0_gpr(rD(ctx->opcode));
3885 if (unlikely(Rc(ctx->opcode) != 0))
3886 gen_set_Rc0(ctx);
3887}
3888
3889/* divso - divso. */
3890GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
3891{
3892 gen_op_load_gpr_T0(rA(ctx->opcode));
3893 gen_op_load_gpr_T1(rB(ctx->opcode));
3894 gen_op_POWER_divso();
3895 gen_op_store_T0_gpr(rD(ctx->opcode));
3896 if (unlikely(Rc(ctx->opcode) != 0))
3897 gen_set_Rc0(ctx);
3898}
3899
3900/* doz - doz. */
3901GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
3902{
3903 gen_op_load_gpr_T0(rA(ctx->opcode));
3904 gen_op_load_gpr_T1(rB(ctx->opcode));
3905 gen_op_POWER_doz();
3906 gen_op_store_T0_gpr(rD(ctx->opcode));
3907 if (unlikely(Rc(ctx->opcode) != 0))
3908 gen_set_Rc0(ctx);
3909}
3910
3911/* dozo - dozo. */
3912GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
3913{
3914 gen_op_load_gpr_T0(rA(ctx->opcode));
3915 gen_op_load_gpr_T1(rB(ctx->opcode));
3916 gen_op_POWER_dozo();
3917 gen_op_store_T0_gpr(rD(ctx->opcode));
3918 if (unlikely(Rc(ctx->opcode) != 0))
3919 gen_set_Rc0(ctx);
3920}
3921
3922/* dozi */
3923GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
3924{
3925 gen_op_load_gpr_T0(rA(ctx->opcode));
3926 gen_op_set_T1(SIMM(ctx->opcode));
3927 gen_op_POWER_doz();
3928 gen_op_store_T0_gpr(rD(ctx->opcode));
3929}
3930
7863667f
JM		 3931/* As lscbx load from memory byte after byte, it's always endian safe.
3932 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
3933 */
2857068e 3934#define op_POWER_lscbx(start, ra, rb) \
76a66253 3935(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 3936#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
3937#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
3938#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
3939#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
3940#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
3941#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
3942#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
3943#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
3944#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
3945#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
3946#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
3947#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
3948static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
3949 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 3950};
76a66253
JM		 3951
3952/* lscbx - lscbx. */
3953GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
3954{
3955 int ra = rA(ctx->opcode);
3956 int rb = rB(ctx->opcode);
3957
3958 gen_addr_reg_index(ctx);
3959 if (ra == 0) {
3960 ra = rb;
3961 }
3962 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3963 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 3964 gen_op_load_xer_bc();
3965 gen_op_load_xer_cmp();
3966 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3967 gen_op_store_xer_bc();
3968 if (unlikely(Rc(ctx->opcode) != 0))
3969 gen_set_Rc0(ctx);
3970}
3971
3972/* maskg - maskg. */
3973GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
3974{
3975 gen_op_load_gpr_T0(rS(ctx->opcode));
3976 gen_op_load_gpr_T1(rB(ctx->opcode));
3977 gen_op_POWER_maskg();
3978 gen_op_store_T0_gpr(rA(ctx->opcode));
3979 if (unlikely(Rc(ctx->opcode) != 0))
3980 gen_set_Rc0(ctx);
3981}
3982
3983/* maskir - maskir. */
3984GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
3985{
3986 gen_op_load_gpr_T0(rA(ctx->opcode));
3987 gen_op_load_gpr_T1(rS(ctx->opcode));
3988 gen_op_load_gpr_T2(rB(ctx->opcode));
3989 gen_op_POWER_maskir();
3990 gen_op_store_T0_gpr(rA(ctx->opcode));
3991 if (unlikely(Rc(ctx->opcode) != 0))
3992 gen_set_Rc0(ctx);
3993}
3994
3995/* mul - mul. */
3996GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
3997{
3998 gen_op_load_gpr_T0(rA(ctx->opcode));
3999 gen_op_load_gpr_T1(rB(ctx->opcode));
4000 gen_op_POWER_mul();
4001 gen_op_store_T0_gpr(rD(ctx->opcode));
4002 if (unlikely(Rc(ctx->opcode) != 0))
4003 gen_set_Rc0(ctx);
4004}
4005
4006/* mulo - mulo. */
4007GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4008{
4009 gen_op_load_gpr_T0(rA(ctx->opcode));
4010 gen_op_load_gpr_T1(rB(ctx->opcode));
4011 gen_op_POWER_mulo();
4012 gen_op_store_T0_gpr(rD(ctx->opcode));
4013 if (unlikely(Rc(ctx->opcode) != 0))
4014 gen_set_Rc0(ctx);
4015}
4016
4017/* nabs - nabs. */
4018GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4019{
4020 gen_op_load_gpr_T0(rA(ctx->opcode));
4021 gen_op_POWER_nabs();
4022 gen_op_store_T0_gpr(rD(ctx->opcode));
4023 if (unlikely(Rc(ctx->opcode) != 0))
4024 gen_set_Rc0(ctx);
4025}
4026
4027/* nabso - nabso. */
4028GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4029{
4030 gen_op_load_gpr_T0(rA(ctx->opcode));
4031 gen_op_POWER_nabso();
4032 gen_op_store_T0_gpr(rD(ctx->opcode));
4033 if (unlikely(Rc(ctx->opcode) != 0))
4034 gen_set_Rc0(ctx);
4035}
4036
4037/* rlmi - rlmi. */
4038GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4039{
4040 uint32_t mb, me;
4041
4042 mb = MB(ctx->opcode);
4043 me = ME(ctx->opcode);
4044 gen_op_load_gpr_T0(rS(ctx->opcode));
4045 gen_op_load_gpr_T1(rA(ctx->opcode));
4046 gen_op_load_gpr_T2(rB(ctx->opcode));
4047 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
4048 gen_op_store_T0_gpr(rA(ctx->opcode));
4049 if (unlikely(Rc(ctx->opcode) != 0))
4050 gen_set_Rc0(ctx);
4051}
4052
4053/* rrib - rrib. */
4054GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4055{
4056 gen_op_load_gpr_T0(rS(ctx->opcode));
4057 gen_op_load_gpr_T1(rA(ctx->opcode));
4058 gen_op_load_gpr_T2(rB(ctx->opcode));
4059 gen_op_POWER_rrib();
4060 gen_op_store_T0_gpr(rA(ctx->opcode));
4061 if (unlikely(Rc(ctx->opcode) != 0))
4062 gen_set_Rc0(ctx);
4063}
4064
4065/* sle - sle. */
4066GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4067{
4068 gen_op_load_gpr_T0(rS(ctx->opcode));
4069 gen_op_load_gpr_T1(rB(ctx->opcode));
4070 gen_op_POWER_sle();
4071 gen_op_store_T0_gpr(rA(ctx->opcode));
4072 if (unlikely(Rc(ctx->opcode) != 0))
4073 gen_set_Rc0(ctx);
4074}
4075
4076/* sleq - sleq. */
4077GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4078{
4079 gen_op_load_gpr_T0(rS(ctx->opcode));
4080 gen_op_load_gpr_T1(rB(ctx->opcode));
4081 gen_op_POWER_sleq();
4082 gen_op_store_T0_gpr(rA(ctx->opcode));
4083 if (unlikely(Rc(ctx->opcode) != 0))
4084 gen_set_Rc0(ctx);
4085}
4086
4087/* sliq - sliq. */
4088GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4089{
4090 gen_op_load_gpr_T0(rS(ctx->opcode));
4091 gen_op_set_T1(SH(ctx->opcode));
4092 gen_op_POWER_sle();
4093 gen_op_store_T0_gpr(rA(ctx->opcode));
4094 if (unlikely(Rc(ctx->opcode) != 0))
4095 gen_set_Rc0(ctx);
4096}
4097
4098/* slliq - slliq. */
4099GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4100{
4101 gen_op_load_gpr_T0(rS(ctx->opcode));
4102 gen_op_set_T1(SH(ctx->opcode));
4103 gen_op_POWER_sleq();
4104 gen_op_store_T0_gpr(rA(ctx->opcode));
4105 if (unlikely(Rc(ctx->opcode) != 0))
4106 gen_set_Rc0(ctx);
4107}
4108
4109/* sllq - sllq. */
4110GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4111{
4112 gen_op_load_gpr_T0(rS(ctx->opcode));
4113 gen_op_load_gpr_T1(rB(ctx->opcode));
4114 gen_op_POWER_sllq();
4115 gen_op_store_T0_gpr(rA(ctx->opcode));
4116 if (unlikely(Rc(ctx->opcode) != 0))
4117 gen_set_Rc0(ctx);
4118}
4119
4120/* slq - slq. */
4121GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4122{
4123 gen_op_load_gpr_T0(rS(ctx->opcode));
4124 gen_op_load_gpr_T1(rB(ctx->opcode));
4125 gen_op_POWER_slq();
4126 gen_op_store_T0_gpr(rA(ctx->opcode));
4127 if (unlikely(Rc(ctx->opcode) != 0))
4128 gen_set_Rc0(ctx);
4129}
4130
d9bce9d9 4131/* sraiq - sraiq. */
76a66253
JM		 4132GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4133{
4134 gen_op_load_gpr_T0(rS(ctx->opcode));
4135 gen_op_set_T1(SH(ctx->opcode));
4136 gen_op_POWER_sraq();
4137 gen_op_store_T0_gpr(rA(ctx->opcode));
4138 if (unlikely(Rc(ctx->opcode) != 0))
4139 gen_set_Rc0(ctx);
4140}
4141
4142/* sraq - sraq. */
4143GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4144{
4145 gen_op_load_gpr_T0(rS(ctx->opcode));
4146 gen_op_load_gpr_T1(rB(ctx->opcode));
4147 gen_op_POWER_sraq();
4148 gen_op_store_T0_gpr(rA(ctx->opcode));
4149 if (unlikely(Rc(ctx->opcode) != 0))
4150 gen_set_Rc0(ctx);
4151}
4152
4153/* sre - sre. */
4154GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4155{
4156 gen_op_load_gpr_T0(rS(ctx->opcode));
4157 gen_op_load_gpr_T1(rB(ctx->opcode));
4158 gen_op_POWER_sre();
4159 gen_op_store_T0_gpr(rA(ctx->opcode));
4160 if (unlikely(Rc(ctx->opcode) != 0))
4161 gen_set_Rc0(ctx);
4162}
4163
4164/* srea - srea. */
4165GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4166{
4167 gen_op_load_gpr_T0(rS(ctx->opcode));
4168 gen_op_load_gpr_T1(rB(ctx->opcode));
4169 gen_op_POWER_srea();
4170 gen_op_store_T0_gpr(rA(ctx->opcode));
4171 if (unlikely(Rc(ctx->opcode) != 0))
4172 gen_set_Rc0(ctx);
4173}
4174
4175/* sreq */
4176GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4177{
4178 gen_op_load_gpr_T0(rS(ctx->opcode));
4179 gen_op_load_gpr_T1(rB(ctx->opcode));
4180 gen_op_POWER_sreq();
4181 gen_op_store_T0_gpr(rA(ctx->opcode));
4182 if (unlikely(Rc(ctx->opcode) != 0))
4183 gen_set_Rc0(ctx);
4184}
4185
4186/* sriq */
4187GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4188{
4189 gen_op_load_gpr_T0(rS(ctx->opcode));
4190 gen_op_set_T1(SH(ctx->opcode));
4191 gen_op_POWER_srq();
4192 gen_op_store_T0_gpr(rA(ctx->opcode));
4193 if (unlikely(Rc(ctx->opcode) != 0))
4194 gen_set_Rc0(ctx);
4195}
4196
4197/* srliq */
4198GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4199{
4200 gen_op_load_gpr_T0(rS(ctx->opcode));
4201 gen_op_load_gpr_T1(rB(ctx->opcode));
4202 gen_op_set_T1(SH(ctx->opcode));
4203 gen_op_POWER_srlq();
4204 gen_op_store_T0_gpr(rA(ctx->opcode));
4205 if (unlikely(Rc(ctx->opcode) != 0))
4206 gen_set_Rc0(ctx);
4207}
4208
4209/* srlq */
4210GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4211{
4212 gen_op_load_gpr_T0(rS(ctx->opcode));
4213 gen_op_load_gpr_T1(rB(ctx->opcode));
4214 gen_op_POWER_srlq();
4215 gen_op_store_T0_gpr(rA(ctx->opcode));
4216 if (unlikely(Rc(ctx->opcode) != 0))
4217 gen_set_Rc0(ctx);
4218}
4219
4220/* srq */
4221GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4222{
4223 gen_op_load_gpr_T0(rS(ctx->opcode));
4224 gen_op_load_gpr_T1(rB(ctx->opcode));
4225 gen_op_POWER_srq();
4226 gen_op_store_T0_gpr(rA(ctx->opcode));
4227 if (unlikely(Rc(ctx->opcode) != 0))
4228 gen_set_Rc0(ctx);
4229}
4230
4231/* PowerPC 602 specific instructions */
4232/* dsa */
4233GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4234{
4235 /* XXX: TODO */
e1833e1f 4236 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4237}
4238
4239/* esa */
4240GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4241{
4242 /* XXX: TODO */
e1833e1f 4243 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4244}
4245
4246/* mfrom */
4247GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4248{
4249#if defined(CONFIG_USER_ONLY)
e1833e1f 4250 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4251#else
4252 if (unlikely(!ctx->supervisor)) {
e1833e1f 4253 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4254 return;
4255 }
4256 gen_op_load_gpr_T0(rA(ctx->opcode));
4257 gen_op_602_mfrom();
4258 gen_op_store_T0_gpr(rD(ctx->opcode));
4259#endif
4260}
4261
4262/* 602 - 603 - G2 TLB management */
4263/* tlbld */
c7697e1f 4264GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4265{
4266#if defined(CONFIG_USER_ONLY)
e1833e1f 4267 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4268#else
4269 if (unlikely(!ctx->supervisor)) {
e1833e1f 4270 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4271 return;
4272 }
4273 gen_op_load_gpr_T0(rB(ctx->opcode));
4274 gen_op_6xx_tlbld();
76a66253
JM		 4275#endif
4276}
4277
4278/* tlbli */
c7697e1f 4279GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4280{
4281#if defined(CONFIG_USER_ONLY)
e1833e1f 4282 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4283#else
4284 if (unlikely(!ctx->supervisor)) {
e1833e1f 4285 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4286 return;
4287 }
4288 gen_op_load_gpr_T0(rB(ctx->opcode));
4289 gen_op_6xx_tlbli();
76a66253
JM		 4290#endif
4291}
4292
7dbe11ac
JM		 4293/* 74xx TLB management */
4294/* tlbld */
c7697e1f 4295GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4296{
4297#if defined(CONFIG_USER_ONLY)
4298 GEN_EXCP_PRIVOPC(ctx);
4299#else
4300 if (unlikely(!ctx->supervisor)) {
4301 GEN_EXCP_PRIVOPC(ctx);
4302 return;
4303 }
4304 gen_op_load_gpr_T0(rB(ctx->opcode));
4305 gen_op_74xx_tlbld();
4306#endif
4307}
4308
4309/* tlbli */
c7697e1f 4310GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4311{
4312#if defined(CONFIG_USER_ONLY)
4313 GEN_EXCP_PRIVOPC(ctx);
4314#else
4315 if (unlikely(!ctx->supervisor)) {
4316 GEN_EXCP_PRIVOPC(ctx);
4317 return;
4318 }
4319 gen_op_load_gpr_T0(rB(ctx->opcode));
4320 gen_op_74xx_tlbli();
4321#endif
4322}
4323
76a66253
JM		 4324/* POWER instructions not in PowerPC 601 */
4325/* clf */
4326GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4327{
4328 /* Cache line flush: implemented as no-op */
4329}
4330
4331/* cli */
4332GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4333{
7f75ffd3 4334 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4335#if defined(CONFIG_USER_ONLY)
e1833e1f 4336 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4337#else
4338 if (unlikely(!ctx->supervisor)) {
e1833e1f 4339 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4340 return;
4341 }
4342#endif
4343}
4344
4345/* dclst */
4346GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4347{
4348 /* Data cache line store: treated as no-op */
4349}
4350
4351GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4352{
4353#if defined(CONFIG_USER_ONLY)
e1833e1f 4354 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4355#else
4356 if (unlikely(!ctx->supervisor)) {
e1833e1f 4357 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4358 return;
4359 }
4360 int ra = rA(ctx->opcode);
4361 int rd = rD(ctx->opcode);
4362
4363 gen_addr_reg_index(ctx);
4364 gen_op_POWER_mfsri();
4365 gen_op_store_T0_gpr(rd);
4366 if (ra != 0 && ra != rd)
4367 gen_op_store_T1_gpr(ra);
4368#endif
4369}
4370
4371GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4372{
4373#if defined(CONFIG_USER_ONLY)
e1833e1f 4374 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4375#else
4376 if (unlikely(!ctx->supervisor)) {
e1833e1f 4377 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4378 return;
4379 }
4380 gen_addr_reg_index(ctx);
4381 gen_op_POWER_rac();
4382 gen_op_store_T0_gpr(rD(ctx->opcode));
4383#endif
4384}
4385
4386GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4387{
4388#if defined(CONFIG_USER_ONLY)
e1833e1f 4389 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4390#else
4391 if (unlikely(!ctx->supervisor)) {
e1833e1f 4392 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4393 return;
4394 }
4395 gen_op_POWER_rfsvc();
e1833e1f 4396 GEN_SYNC(ctx);
76a66253
JM		 4397#endif
4398}
4399
4400/* svc is not implemented for now */
4401
4402/* POWER2 specific instructions */
4403/* Quad manipulation (load/store two floats at a time) */
7863667f 4404/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 4405#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4406#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 4407#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4408#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4409#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4410#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4411#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4412#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4413#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4414#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4415#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4416#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4417#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4418#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4419#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4420#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4421#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4422#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4423static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4424 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 4425};
7863667f
JM		 4426static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4427 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 4428};
76a66253
JM		 4429
4430/* lfq */
4431GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4432{
4433 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4434 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4435 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4436 op_POWER2_lfq();
4437 gen_op_store_FT0_fpr(rD(ctx->opcode));
4438 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4439}
4440
4441/* lfqu */
4442GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4443{
4444 int ra = rA(ctx->opcode);
4445
4446 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4447 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4448 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4449 op_POWER2_lfq();
4450 gen_op_store_FT0_fpr(rD(ctx->opcode));
4451 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4452 if (ra != 0)
4453 gen_op_store_T0_gpr(ra);
4454}
4455
4456/* lfqux */
4457GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4458{
4459 int ra = rA(ctx->opcode);
4460
4461 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4462 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4463 gen_addr_reg_index(ctx);
4464 op_POWER2_lfq();
4465 gen_op_store_FT0_fpr(rD(ctx->opcode));
4466 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4467 if (ra != 0)
4468 gen_op_store_T0_gpr(ra);
4469}
4470
4471/* lfqx */
4472GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4473{
4474 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4475 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4476 gen_addr_reg_index(ctx);
4477 op_POWER2_lfq();
4478 gen_op_store_FT0_fpr(rD(ctx->opcode));
4479 gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
4480}
4481
4482/* stfq */
4483GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4484{
4485 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4486 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4487 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4488 gen_op_load_fpr_FT0(rS(ctx->opcode));
4489 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4490 op_POWER2_stfq();
4491}
4492
4493/* stfqu */
4494GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4495{
4496 int ra = rA(ctx->opcode);
4497
4498 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4499 gen_update_nip(ctx, ctx->nip - 4);
9d53c753 4500 gen_addr_imm_index(ctx, 0);
76a66253
JM		 4501 gen_op_load_fpr_FT0(rS(ctx->opcode));
4502 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4503 op_POWER2_stfq();
4504 if (ra != 0)
4505 gen_op_store_T0_gpr(ra);
4506}
4507
4508/* stfqux */
4509GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4510{
4511 int ra = rA(ctx->opcode);
4512
4513 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4514 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4515 gen_addr_reg_index(ctx);
4516 gen_op_load_fpr_FT0(rS(ctx->opcode));
4517 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4518 op_POWER2_stfq();
4519 if (ra != 0)
4520 gen_op_store_T0_gpr(ra);
4521}
4522
4523/* stfqx */
4524GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4525{
4526 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4527 gen_update_nip(ctx, ctx->nip - 4);
76a66253
JM		 4528 gen_addr_reg_index(ctx);
4529 gen_op_load_fpr_FT0(rS(ctx->opcode));
4530 gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
4531 op_POWER2_stfq();
4532}
4533
4534/* BookE specific instructions */
2662a059 4535/* XXX: not implemented on 440 ? */
05332d70 4536GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 4537{
4538 /* XXX: TODO */
e1833e1f 4539 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4540}
4541
2662a059 4542/* XXX: not implemented on 440 ? */
05332d70 4543GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 4544{
4545#if defined(CONFIG_USER_ONLY)
e1833e1f 4546 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4547#else
4548 if (unlikely(!ctx->supervisor)) {
e1833e1f 4549 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4550 return;
4551 }
4552 gen_addr_reg_index(ctx);
4553 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 4554#if defined(TARGET_PPC64)
4555 if (ctx->sf_mode)
4556 gen_op_tlbie_64();
4557 else
4558#endif
4559 gen_op_tlbie();
76a66253
JM		 4560#endif
4561}
4562
4563/* All 405 MAC instructions are translated here */
b068d6a7
JM		 4564static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4565 int opc2, int opc3,
4566 int ra, int rb, int rt, int Rc)
76a66253
JM		 4567{
4568 gen_op_load_gpr_T0(ra);
4569 gen_op_load_gpr_T1(rb);
4570 switch (opc3 & 0x0D) {
4571 case 0x05:
4572 /* macchw - macchw. - macchwo - macchwo. */
4573 /* macchws - macchws. - macchwso - macchwso. */
4574 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4575 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
4576 /* mulchw - mulchw. */
4577 gen_op_405_mulchw();
4578 break;
4579 case 0x04:
4580 /* macchwu - macchwu. - macchwuo - macchwuo. */
4581 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
4582 /* mulchwu - mulchwu. */
4583 gen_op_405_mulchwu();
4584 break;
4585 case 0x01:
4586 /* machhw - machhw. - machhwo - machhwo. */
4587 /* machhws - machhws. - machhwso - machhwso. */
4588 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
4589 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
4590 /* mulhhw - mulhhw. */
4591 gen_op_405_mulhhw();
4592 break;
4593 case 0x00:
4594 /* machhwu - machhwu. - machhwuo - machhwuo. */
4595 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
4596 /* mulhhwu - mulhhwu. */
4597 gen_op_405_mulhhwu();
4598 break;
4599 case 0x0D:
4600 /* maclhw - maclhw. - maclhwo - maclhwo. */
4601 /* maclhws - maclhws. - maclhwso - maclhwso. */
4602 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
4603 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
4604 /* mullhw - mullhw. */
4605 gen_op_405_mullhw();
4606 break;
4607 case 0x0C:
4608 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
4609 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
4610 /* mullhwu - mullhwu. */
4611 gen_op_405_mullhwu();
4612 break;
4613 }
4614 if (opc2 & 0x02) {
4615 /* nmultiply-and-accumulate (0x0E) */
4616 gen_op_neg();
4617 }
4618 if (opc2 & 0x04) {
4619 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
4620 gen_op_load_gpr_T2(rt);
4621 gen_op_move_T1_T0();
4622 gen_op_405_add_T0_T2();
4623 }
4624 if (opc3 & 0x10) {
4625 /* Check overflow */
4626 if (opc3 & 0x01)
c3e10c7b 4627 gen_op_check_addo();
76a66253
JM		 4628 else
4629 gen_op_405_check_ovu();
4630 }
4631 if (opc3 & 0x02) {
4632 /* Saturate */
4633 if (opc3 & 0x01)
4634 gen_op_405_check_sat();
4635 else
4636 gen_op_405_check_satu();
4637 }
4638 gen_op_store_T0_gpr(rt);
4639 if (unlikely(Rc) != 0) {
4640 /* Update Rc0 */
4641 gen_set_Rc0(ctx);
4642 }
4643}
4644
a750fc0b
JM		 4645#define GEN_MAC_HANDLER(name, opc2, opc3) \
4646GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 4647{ \
4648 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
4649 rD(ctx->opcode), Rc(ctx->opcode)); \
4650}
4651
4652/* macchw - macchw. */
a750fc0b 4653GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 4654/* macchwo - macchwo. */
a750fc0b 4655GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 4656/* macchws - macchws. */
a750fc0b 4657GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 4658/* macchwso - macchwso. */
a750fc0b 4659GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 4660/* macchwsu - macchwsu. */
a750fc0b 4661GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 4662/* macchwsuo - macchwsuo. */
a750fc0b 4663GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 4664/* macchwu - macchwu. */
a750fc0b 4665GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 4666/* macchwuo - macchwuo. */
a750fc0b 4667GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 4668/* machhw - machhw. */
a750fc0b 4669GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 4670/* machhwo - machhwo. */
a750fc0b 4671GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 4672/* machhws - machhws. */
a750fc0b 4673GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 4674/* machhwso - machhwso. */
a750fc0b 4675GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 4676/* machhwsu - machhwsu. */
a750fc0b 4677GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 4678/* machhwsuo - machhwsuo. */
a750fc0b 4679GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 4680/* machhwu - machhwu. */
a750fc0b 4681GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 4682/* machhwuo - machhwuo. */
a750fc0b 4683GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 4684/* maclhw - maclhw. */
a750fc0b 4685GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 4686/* maclhwo - maclhwo. */
a750fc0b 4687GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 4688/* maclhws - maclhws. */
a750fc0b 4689GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 4690/* maclhwso - maclhwso. */
a750fc0b 4691GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 4692/* maclhwu - maclhwu. */
a750fc0b 4693GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 4694/* maclhwuo - maclhwuo. */
a750fc0b 4695GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 4696/* maclhwsu - maclhwsu. */
a750fc0b 4697GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 4698/* maclhwsuo - maclhwsuo. */
a750fc0b 4699GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 4700/* nmacchw - nmacchw. */
a750fc0b 4701GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 4702/* nmacchwo - nmacchwo. */
a750fc0b 4703GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 4704/* nmacchws - nmacchws. */
a750fc0b 4705GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 4706/* nmacchwso - nmacchwso. */
a750fc0b 4707GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 4708/* nmachhw - nmachhw. */
a750fc0b 4709GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 4710/* nmachhwo - nmachhwo. */
a750fc0b 4711GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 4712/* nmachhws - nmachhws. */
a750fc0b 4713GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 4714/* nmachhwso - nmachhwso. */
a750fc0b 4715GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 4716/* nmaclhw - nmaclhw. */
a750fc0b 4717GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 4718/* nmaclhwo - nmaclhwo. */
a750fc0b 4719GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 4720/* nmaclhws - nmaclhws. */
a750fc0b 4721GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 4722/* nmaclhwso - nmaclhwso. */
a750fc0b 4723GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 4724
4725/* mulchw - mulchw. */
a750fc0b 4726GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 4727/* mulchwu - mulchwu. */
a750fc0b 4728GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 4729/* mulhhw - mulhhw. */
a750fc0b 4730GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 4731/* mulhhwu - mulhhwu. */
a750fc0b 4732GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 4733/* mullhw - mullhw. */
a750fc0b 4734GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 4735/* mullhwu - mullhwu. */
a750fc0b 4736GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 4737
4738/* mfdcr */
05332d70 4739GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 4740{
4741#if defined(CONFIG_USER_ONLY)
e1833e1f 4742 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4743#else
4744 uint32_t dcrn = SPR(ctx->opcode);
4745
4746 if (unlikely(!ctx->supervisor)) {
e1833e1f 4747 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4748 return;
4749 }
a42bd6cc
JM		 4750 gen_op_set_T0(dcrn);
4751 gen_op_load_dcr();
76a66253
JM		 4752 gen_op_store_T0_gpr(rD(ctx->opcode));
4753#endif
4754}
4755
4756/* mtdcr */
05332d70 4757GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 4758{
4759#if defined(CONFIG_USER_ONLY)
e1833e1f 4760 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4761#else
4762 uint32_t dcrn = SPR(ctx->opcode);
4763
4764 if (unlikely(!ctx->supervisor)) {
e1833e1f 4765 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 4766 return;
4767 }
a42bd6cc
JM		 4768 gen_op_set_T0(dcrn);
4769 gen_op_load_gpr_T1(rS(ctx->opcode));
4770 gen_op_store_dcr();
4771#endif
4772}
4773
4774/* mfdcrx */
2662a059 4775/* XXX: not implemented on 440 ? */
05332d70 4776GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 4777{
4778#if defined(CONFIG_USER_ONLY)
e1833e1f 4779 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4780#else
4781 if (unlikely(!ctx->supervisor)) {
e1833e1f 4782 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4783 return;
4784 }
4785 gen_op_load_gpr_T0(rA(ctx->opcode));
4786 gen_op_load_dcr();
4787 gen_op_store_T0_gpr(rD(ctx->opcode));
a750fc0b 4788 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 4789#endif
4790}
4791
4792/* mtdcrx */
2662a059 4793/* XXX: not implemented on 440 ? */
05332d70 4794GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 4795{
4796#if defined(CONFIG_USER_ONLY)
e1833e1f 4797 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4798#else
4799 if (unlikely(!ctx->supervisor)) {
e1833e1f 4800 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 4801 return;
4802 }
4803 gen_op_load_gpr_T0(rA(ctx->opcode));
4804 gen_op_load_gpr_T1(rS(ctx->opcode));
4805 gen_op_store_dcr();
a750fc0b 4806 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 4807#endif
4808}
4809
a750fc0b
JM		 4810/* mfdcrux (PPC 460) : user-mode access to DCR */
4811GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
4812{
4813 gen_op_load_gpr_T0(rA(ctx->opcode));
4814 gen_op_load_dcr();
4815 gen_op_store_T0_gpr(rD(ctx->opcode));
4816 /* Note: Rc update flag set leads to undefined state of Rc0 */
4817}
4818
4819/* mtdcrux (PPC 460) : user-mode access to DCR */
4820GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
4821{
4822 gen_op_load_gpr_T0(rA(ctx->opcode));
4823 gen_op_load_gpr_T1(rS(ctx->opcode));
4824 gen_op_store_dcr();
4825 /* Note: Rc update flag set leads to undefined state of Rc0 */
4826}
4827
76a66253
JM		 4828/* dccci */
4829GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
4830{
4831#if defined(CONFIG_USER_ONLY)
e1833e1f 4832 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4833#else
4834 if (unlikely(!ctx->supervisor)) {
e1833e1f 4835 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4836 return;
4837 }
4838 /* interpreted as no-op */
4839#endif
4840}
4841
4842/* dcread */
4843GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
4844{
4845#if defined(CONFIG_USER_ONLY)
e1833e1f 4846 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4847#else
4848 if (unlikely(!ctx->supervisor)) {
e1833e1f 4849 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4850 return;
4851 }
4852 gen_addr_reg_index(ctx);
4853 op_ldst(lwz);
4854 gen_op_store_T0_gpr(rD(ctx->opcode));
4855#endif
4856}
4857
4858/* icbt */
c7697e1f 4859GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 4860{
4861 /* interpreted as no-op */
4862 /* XXX: specification say this is treated as a load by the MMU
4863 * but does not generate any exception
4864 */
4865}
4866
4867/* iccci */
4868GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
4869{
4870#if defined(CONFIG_USER_ONLY)
e1833e1f 4871 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4872#else
4873 if (unlikely(!ctx->supervisor)) {
e1833e1f 4874 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4875 return;
4876 }
4877 /* interpreted as no-op */
4878#endif
4879}
4880
4881/* icread */
4882GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
4883{
4884#if defined(CONFIG_USER_ONLY)
e1833e1f 4885 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4886#else
4887 if (unlikely(!ctx->supervisor)) {
e1833e1f 4888 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4889 return;
4890 }
4891 /* interpreted as no-op */
4892#endif
4893}
4894
4895/* rfci (supervisor only) */
c7697e1f 4896GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 4897{
4898#if defined(CONFIG_USER_ONLY)
e1833e1f 4899 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4900#else
4901 if (unlikely(!ctx->supervisor)) {
e1833e1f 4902 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4903 return;
4904 }
4905 /* Restore CPU state */
4906 gen_op_40x_rfci();
e1833e1f 4907 GEN_SYNC(ctx);
a42bd6cc
JM		 4908#endif
4909}
4910
4911GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
4912{
4913#if defined(CONFIG_USER_ONLY)
e1833e1f 4914 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4915#else
4916 if (unlikely(!ctx->supervisor)) {
e1833e1f 4917 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4918 return;
4919 }
4920 /* Restore CPU state */
4921 gen_op_rfci();
e1833e1f 4922 GEN_SYNC(ctx);
a42bd6cc
JM		 4923#endif
4924}
4925
4926/* BookE specific */
2662a059 4927/* XXX: not implemented on 440 ? */
05332d70 4928GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 4929{
4930#if defined(CONFIG_USER_ONLY)
e1833e1f 4931 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4932#else
4933 if (unlikely(!ctx->supervisor)) {
e1833e1f 4934 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4935 return;
4936 }
4937 /* Restore CPU state */
a42bd6cc 4938 gen_op_rfdi();
e1833e1f 4939 GEN_SYNC(ctx);
76a66253
JM		 4940#endif
4941}
4942
2662a059 4943/* XXX: not implemented on 440 ? */
a750fc0b 4944GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 4945{
4946#if defined(CONFIG_USER_ONLY)
e1833e1f 4947 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4948#else
4949 if (unlikely(!ctx->supervisor)) {
e1833e1f 4950 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 4951 return;
4952 }
4953 /* Restore CPU state */
4954 gen_op_rfmci();
e1833e1f 4955 GEN_SYNC(ctx);
a42bd6cc
JM		 4956#endif
4957}
5eb7995e 4958
d9bce9d9 4959/* TLB management - PowerPC 405 implementation */
76a66253 4960/* tlbre */
c7697e1f 4961GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 4962{
4963#if defined(CONFIG_USER_ONLY)
e1833e1f 4964 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4965#else
4966 if (unlikely(!ctx->supervisor)) {
e1833e1f 4967 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4968 return;
4969 }
4970 switch (rB(ctx->opcode)) {
4971 case 0:
9a64fbe4 4972 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 4973 gen_op_4xx_tlbre_hi();
4974 gen_op_store_T0_gpr(rD(ctx->opcode));
4975 break;
4976 case 1:
4977 gen_op_load_gpr_T0(rA(ctx->opcode));
4978 gen_op_4xx_tlbre_lo();
4979 gen_op_store_T0_gpr(rD(ctx->opcode));
4980 break;
4981 default:
e1833e1f 4982 GEN_EXCP_INVAL(ctx);
76a66253 4983 break;
9a64fbe4 4984 }
76a66253
JM		 4985#endif
4986}
4987
d9bce9d9 4988/* tlbsx - tlbsx. */
c7697e1f 4989GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 4990{
4991#if defined(CONFIG_USER_ONLY)
e1833e1f 4992 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4993#else
4994 if (unlikely(!ctx->supervisor)) {
e1833e1f 4995 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4996 return;
4997 }
4998 gen_addr_reg_index(ctx);
daf4f96e 4999 gen_op_4xx_tlbsx();
76a66253 5000 if (Rc(ctx->opcode))
daf4f96e 5001 gen_op_4xx_tlbsx_check();
9a64fbe4 5002 gen_op_store_T0_gpr(rD(ctx->opcode));
76a66253 5003#endif
79aceca5
FB		 5004}
5005
76a66253 5006/* tlbwe */
c7697e1f 5007GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5008{
76a66253 5009#if defined(CONFIG_USER_ONLY)
e1833e1f 5010 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5011#else
5012 if (unlikely(!ctx->supervisor)) {
e1833e1f 5013 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5014 return;
5015 }
5016 switch (rB(ctx->opcode)) {
5017 case 0:
9a64fbe4 5018 gen_op_load_gpr_T0(rA(ctx->opcode));
76a66253
JM		 5019 gen_op_load_gpr_T1(rS(ctx->opcode));
5020 gen_op_4xx_tlbwe_hi();
5021 break;
5022 case 1:
5023 gen_op_load_gpr_T0(rA(ctx->opcode));
5024 gen_op_load_gpr_T1(rS(ctx->opcode));
5025 gen_op_4xx_tlbwe_lo();
5026 break;
5027 default:
e1833e1f 5028 GEN_EXCP_INVAL(ctx);
76a66253 5029 break;
9a64fbe4 5030 }
76a66253
JM		 5031#endif
5032}
5033
a4bb6c3e 5034/* TLB management - PowerPC 440 implementation */
5eb7995e 5035/* tlbre */
c7697e1f 5036GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5037{
5038#if defined(CONFIG_USER_ONLY)
e1833e1f 5039 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5040#else
5041 if (unlikely(!ctx->supervisor)) {
e1833e1f 5042 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5043 return;
5044 }
5045 switch (rB(ctx->opcode)) {
5046 case 0:
5eb7995e 5047 case 1:
5eb7995e
JM		 5048 case 2:
5049 gen_op_load_gpr_T0(rA(ctx->opcode));
a4bb6c3e 5050 gen_op_440_tlbre(rB(ctx->opcode));
5eb7995e
JM		 5051 gen_op_store_T0_gpr(rD(ctx->opcode));
5052 break;
5053 default:
e1833e1f 5054 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5055 break;
5056 }
5057#endif
5058}
5059
5060/* tlbsx - tlbsx. */
c7697e1f 5061GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5062{
5063#if defined(CONFIG_USER_ONLY)
e1833e1f 5064 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5065#else
5066 if (unlikely(!ctx->supervisor)) {
e1833e1f 5067 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5068 return;
5069 }
5070 gen_addr_reg_index(ctx);
daf4f96e 5071 gen_op_440_tlbsx();
5eb7995e 5072 if (Rc(ctx->opcode))
daf4f96e 5073 gen_op_4xx_tlbsx_check();
5eb7995e
JM		 5074 gen_op_store_T0_gpr(rD(ctx->opcode));
5075#endif
5076}
5077
5078/* tlbwe */
c7697e1f 5079GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5080{
5081#if defined(CONFIG_USER_ONLY)
e1833e1f 5082 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5083#else
5084 if (unlikely(!ctx->supervisor)) {
e1833e1f 5085 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5086 return;
5087 }
5088 switch (rB(ctx->opcode)) {
5089 case 0:
5eb7995e 5090 case 1:
5eb7995e
JM		 5091 case 2:
5092 gen_op_load_gpr_T0(rA(ctx->opcode));
5093 gen_op_load_gpr_T1(rS(ctx->opcode));
a4bb6c3e 5094 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5095 break;
5096 default:
e1833e1f 5097 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5098 break;
5099 }
5100#endif
5101}
5102
76a66253 5103/* wrtee */
05332d70 5104GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5105{
5106#if defined(CONFIG_USER_ONLY)
e1833e1f 5107 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5108#else
5109 if (unlikely(!ctx->supervisor)) {
e1833e1f 5110 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5111 return;
5112 }
5113 gen_op_load_gpr_T0(rD(ctx->opcode));
a42bd6cc 5114 gen_op_wrte();
dee96f6c
JM		 5115 /* Stop translation to have a chance to raise an exception
5116 * if we just set msr_ee to 1
5117 */
e1833e1f 5118 GEN_STOP(ctx);
76a66253
JM		 5119#endif
5120}
5121
5122/* wrteei */
05332d70 5123GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5124{
5125#if defined(CONFIG_USER_ONLY)
e1833e1f 5126 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5127#else
5128 if (unlikely(!ctx->supervisor)) {
e1833e1f 5129 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5130 return;
5131 }
5132 gen_op_set_T0(ctx->opcode & 0x00010000);
a42bd6cc 5133 gen_op_wrte();
dee96f6c
JM		 5134 /* Stop translation to have a chance to raise an exception
5135 * if we just set msr_ee to 1
5136 */
e1833e1f 5137 GEN_STOP(ctx);
76a66253
JM		 5138#endif
5139}
5140
08e46e54 5141/* PowerPC 440 specific instructions */
76a66253
JM		 5142/* dlmzb */
5143GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5144{
5145 gen_op_load_gpr_T0(rS(ctx->opcode));
5146 gen_op_load_gpr_T1(rB(ctx->opcode));
5147 gen_op_440_dlmzb();
5148 gen_op_store_T0_gpr(rA(ctx->opcode));
5149 gen_op_store_xer_bc();
5150 if (Rc(ctx->opcode)) {
5151 gen_op_440_dlmzb_update_Rc();
5152 gen_op_store_T0_crf(0);
5153 }
5154}
5155
5156/* mbar replaces eieio on 440 */
5157GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5158{
5159 /* interpreted as no-op */
5160}
5161
5162/* msync replaces sync on 440 */
0db1b20e 5163GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5164{
5165 /* interpreted as no-op */
5166}
5167
5168/* icbt */
c7697e1f 5169GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5170{
5171 /* interpreted as no-op */
5172 /* XXX: specification say this is treated as a load by the MMU
5173 * but does not generate any exception
5174 */
79aceca5
FB		 5175}
5176
a9d9eb8f
JM		 5177/*** Altivec vector extension ***/
5178/* Altivec registers moves */
5179GEN32(gen_op_load_avr_A0, gen_op_load_avr_A0_avr);
5180GEN32(gen_op_load_avr_A1, gen_op_load_avr_A1_avr);
5181GEN32(gen_op_load_avr_A2, gen_op_load_avr_A2_avr);
5182
5183GEN32(gen_op_store_A0_avr, gen_op_store_A0_avr_avr);
5184GEN32(gen_op_store_A1_avr, gen_op_store_A1_avr_avr);
5185#if 0 // unused
5186GEN32(gen_op_store_A2_avr, gen_op_store_A2_avr_avr);
5187#endif
5188
5189#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5190#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5191static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5192 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5193};
5194#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5195static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5196 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5197};
a9d9eb8f
JM		 5198
5199#define GEN_VR_LDX(name, opc2, opc3) \
5200GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5201{ \
5202 if (unlikely(!ctx->altivec_enabled)) { \
5203 GEN_EXCP_NO_VR(ctx); \
5204 return; \
5205 } \
5206 gen_addr_reg_index(ctx); \
5207 op_vr_ldst(vr_l##name); \
5208 gen_op_store_A0_avr(rD(ctx->opcode)); \
5209}
5210
5211#define GEN_VR_STX(name, opc2, opc3) \
5212GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5213{ \
5214 if (unlikely(!ctx->altivec_enabled)) { \
5215 GEN_EXCP_NO_VR(ctx); \
5216 return; \
5217 } \
5218 gen_addr_reg_index(ctx); \
5219 gen_op_load_avr_A0(rS(ctx->opcode)); \
5220 op_vr_ldst(vr_st##name); \
5221}
5222
5223OP_VR_LD_TABLE(vx);
5224GEN_VR_LDX(vx, 0x07, 0x03);
5225/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5226#define gen_op_vr_lvxl gen_op_vr_lvx
5227GEN_VR_LDX(vxl, 0x07, 0x0B);
5228
5229OP_VR_ST_TABLE(vx);
5230GEN_VR_STX(vx, 0x07, 0x07);
5231/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5232#define gen_op_vr_stvxl gen_op_vr_stvx
5233GEN_VR_STX(vxl, 0x07, 0x0F);
5234
0487d6a8 5235/*** SPE extension ***/
0487d6a8 5236/* Register moves */
65d6c0f3 5237#if !defined(TARGET_PPC64)
3cd7d1dd 5238
0487d6a8
JM		 5239GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5240GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
5241#if 0 // unused
5242GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
5243#endif
5244
5245GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
5246GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5247#if 0 // unused
5248GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5249#endif
5250
65d6c0f3 5251#else /* !defined(TARGET_PPC64) */
3cd7d1dd
JM		 5252
5253/* No specific load/store functions: GPRs are already 64 bits */
5254#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
5255#define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
5256#if 0 // unused
5257#define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
5258#endif
5259
5260#define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
5261#define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
5262#if 0 // unused
5263#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
5264#endif
5265
65d6c0f3 5266#endif /* !defined(TARGET_PPC64) */
3cd7d1dd 5267
0487d6a8
JM		 5268#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5269GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5270{ \
5271 if (Rc(ctx->opcode)) \
5272 gen_##name1(ctx); \
5273 else \
5274 gen_##name0(ctx); \
5275}
5276
5277/* Handler for undefined SPE opcodes */
b068d6a7 5278static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5279{
e1833e1f 5280 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5281}
5282
5283/* SPE load and stores */
b068d6a7 5284static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
0487d6a8
JM		 5285{
5286 target_long simm = rB(ctx->opcode);
5287
5288 if (rA(ctx->opcode) == 0) {
5289 gen_set_T0(simm << sh);
5290 } else {
5291 gen_op_load_gpr_T0(rA(ctx->opcode));
5292 if (likely(simm != 0))
5293 gen_op_addi(simm << sh);
5294 }
5295}
5296
5297#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5298#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5299static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5300 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5301};
5302#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5303static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5304 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5305};
0487d6a8
JM		 5306
5307#define GEN_SPE_LD(name, sh) \
b068d6a7 5308static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5309{ \
5310 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5311 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5312 return; \
5313 } \
5314 gen_addr_spe_imm_index(ctx, sh); \
5315 op_spe_ldst(spe_l##name); \
5316 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5317}
5318
5319#define GEN_SPE_LDX(name) \
b068d6a7 5320static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 5321{ \
5322 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5323 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5324 return; \
5325 } \
5326 gen_addr_reg_index(ctx); \
5327 op_spe_ldst(spe_l##name); \
5328 gen_op_store_T1_gpr64(rD(ctx->opcode)); \
5329}
5330
5331#define GEN_SPEOP_LD(name, sh) \
5332OP_SPE_LD_TABLE(name); \
5333GEN_SPE_LD(name, sh); \
5334GEN_SPE_LDX(name)
5335
5336#define GEN_SPE_ST(name, sh) \
b068d6a7 5337static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 5338{ \
5339 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5340 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5341 return; \
5342 } \
5343 gen_addr_spe_imm_index(ctx, sh); \
5344 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5345 op_spe_ldst(spe_st##name); \
5346}
5347
5348#define GEN_SPE_STX(name) \
b068d6a7 5349static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 5350{ \
5351 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5352 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5353 return; \
5354 } \
5355 gen_addr_reg_index(ctx); \
5356 gen_op_load_gpr64_T1(rS(ctx->opcode)); \
5357 op_spe_ldst(spe_st##name); \
5358}
5359
5360#define GEN_SPEOP_ST(name, sh) \
5361OP_SPE_ST_TABLE(name); \
5362GEN_SPE_ST(name, sh); \
5363GEN_SPE_STX(name)
5364
5365#define GEN_SPEOP_LDST(name, sh) \
5366GEN_SPEOP_LD(name, sh); \
5367GEN_SPEOP_ST(name, sh)
5368
5369/* SPE arithmetic and logic */
5370#define GEN_SPEOP_ARITH2(name) \
b068d6a7 5371static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5372{ \
5373 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5374 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5375 return; \
5376 } \
5377 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5378 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5379 gen_op_##name(); \
5380 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5381}
5382
5383#define GEN_SPEOP_ARITH1(name) \
b068d6a7 5384static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5385{ \
5386 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5387 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5388 return; \
5389 } \
5390 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5391 gen_op_##name(); \
5392 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5393}
5394
5395#define GEN_SPEOP_COMP(name) \
b068d6a7 5396static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5397{ \
5398 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5399 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5400 return; \
5401 } \
5402 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5403 gen_op_load_gpr64_T1(rB(ctx->opcode)); \
5404 gen_op_##name(); \
5405 gen_op_store_T0_crf(crfD(ctx->opcode)); \
5406}
5407
5408/* Logical */
5409GEN_SPEOP_ARITH2(evand);
5410GEN_SPEOP_ARITH2(evandc);
5411GEN_SPEOP_ARITH2(evxor);
5412GEN_SPEOP_ARITH2(evor);
5413GEN_SPEOP_ARITH2(evnor);
5414GEN_SPEOP_ARITH2(eveqv);
5415GEN_SPEOP_ARITH2(evorc);
5416GEN_SPEOP_ARITH2(evnand);
5417GEN_SPEOP_ARITH2(evsrwu);
5418GEN_SPEOP_ARITH2(evsrws);
5419GEN_SPEOP_ARITH2(evslw);
5420GEN_SPEOP_ARITH2(evrlw);
5421GEN_SPEOP_ARITH2(evmergehi);
5422GEN_SPEOP_ARITH2(evmergelo);
5423GEN_SPEOP_ARITH2(evmergehilo);
5424GEN_SPEOP_ARITH2(evmergelohi);
5425
5426/* Arithmetic */
5427GEN_SPEOP_ARITH2(evaddw);
5428GEN_SPEOP_ARITH2(evsubfw);
5429GEN_SPEOP_ARITH1(evabs);
5430GEN_SPEOP_ARITH1(evneg);
5431GEN_SPEOP_ARITH1(evextsb);
5432GEN_SPEOP_ARITH1(evextsh);
5433GEN_SPEOP_ARITH1(evrndw);
5434GEN_SPEOP_ARITH1(evcntlzw);
5435GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 5436static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 5437{
5438 /* Note: brinc is usable even if SPE is disabled */
3cd7d1dd
JM		 5439 gen_op_load_gpr_T0(rA(ctx->opcode));
5440 gen_op_load_gpr_T1(rB(ctx->opcode));
0487d6a8 5441 gen_op_brinc();
3cd7d1dd 5442 gen_op_store_T0_gpr(rD(ctx->opcode));
0487d6a8
JM		 5443}
5444
5445#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 5446static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5447{ \
5448 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5449 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5450 return; \
5451 } \
5452 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5453 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5454 gen_op_##name(); \
5455 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5456}
5457
5458#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 5459static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5460{ \
5461 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5462 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5463 return; \
5464 } \
5465 gen_op_load_gpr64_T0(rA(ctx->opcode)); \
5466 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5467 gen_op_##name(); \
5468 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5469}
5470
5471GEN_SPEOP_ARITH_IMM2(evaddw);
5472#define gen_evaddiw gen_evaddwi
5473GEN_SPEOP_ARITH_IMM2(evsubfw);
5474#define gen_evsubifw gen_evsubfwi
5475GEN_SPEOP_LOGIC_IMM2(evslw);
5476GEN_SPEOP_LOGIC_IMM2(evsrwu);
5477#define gen_evsrwis gen_evsrwsi
5478GEN_SPEOP_LOGIC_IMM2(evsrws);
5479#define gen_evsrwiu gen_evsrwui
5480GEN_SPEOP_LOGIC_IMM2(evrlw);
5481
b068d6a7 5482static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 5483{
5484 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5485
5486 gen_op_splatwi_T0_64(imm);
5487 gen_op_store_T0_gpr64(rD(ctx->opcode));
5488}
5489
b068d6a7 5490static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 5491{
5492 uint32_t imm = rA(ctx->opcode) << 27;
5493
5494 gen_op_splatwi_T0_64(imm);
5495 gen_op_store_T0_gpr64(rD(ctx->opcode));
5496}
5497
5498/* Comparison */
5499GEN_SPEOP_COMP(evcmpgtu);
5500GEN_SPEOP_COMP(evcmpgts);
5501GEN_SPEOP_COMP(evcmpltu);
5502GEN_SPEOP_COMP(evcmplts);
5503GEN_SPEOP_COMP(evcmpeq);
5504
5505GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5506GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5507GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5508GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5509GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5510GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5511GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5512GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5513GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5514GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5515GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5516GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5517GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5518GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5519GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5520GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5521GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5522GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5523GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5524GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5525GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5526GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5527GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5528GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5529GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5530
b068d6a7 5531static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 5532{
5533 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 5534 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 5535 return;
5536 }
5537 gen_op_load_crf_T0(ctx->opcode & 0x7);
5538 gen_op_load_gpr64_T0(rA(ctx->opcode));
5539 gen_op_load_gpr64_T1(rB(ctx->opcode));
5540 gen_op_evsel();
5541 gen_op_store_T0_gpr64(rD(ctx->opcode));
5542}
5543
c7697e1f 5544GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5545{
5546 gen_evsel(ctx);
5547}
c7697e1f 5548GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5549{
5550 gen_evsel(ctx);
5551}
c7697e1f 5552GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5553{
5554 gen_evsel(ctx);
5555}
c7697e1f 5556GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5557{
5558 gen_evsel(ctx);
5559}
5560
5561/* Load and stores */
5562#if defined(TARGET_PPC64)
5563/* In that case, we already have 64 bits load & stores
5564 * so, spe_ldd is equivalent to ld and spe_std is equivalent to std
5565 */
7863667f
JM		 5566#define gen_op_spe_ldd_raw gen_op_ld_raw
5567#define gen_op_spe_ldd_user gen_op_ld_user
5568#define gen_op_spe_ldd_kernel gen_op_ld_kernel
5569#define gen_op_spe_ldd_hypv gen_op_ld_hypv
5570#define gen_op_spe_ldd_64_raw gen_op_ld_64_raw
5571#define gen_op_spe_ldd_64_user gen_op_ld_64_user
5572#define gen_op_spe_ldd_64_kernel gen_op_ld_64_kernel
5573#define gen_op_spe_ldd_64_hypv gen_op_ld_64_hypv
5574#define gen_op_spe_ldd_le_raw gen_op_ld_le_raw
5575#define gen_op_spe_ldd_le_user gen_op_ld_le_user
5576#define gen_op_spe_ldd_le_kernel gen_op_ld_le_kernel
5577#define gen_op_spe_ldd_le_hypv gen_op_ld_le_hypv
5578#define gen_op_spe_ldd_le_64_raw gen_op_ld_le_64_raw
5579#define gen_op_spe_ldd_le_64_user gen_op_ld_le_64_user
5580#define gen_op_spe_ldd_le_64_kernel gen_op_ld_le_64_kernel
5581#define gen_op_spe_ldd_le_64_hypv gen_op_ld_le_64_hypv
5582#define gen_op_spe_stdd_raw gen_op_std_raw
5583#define gen_op_spe_stdd_user gen_op_std_user
5584#define gen_op_spe_stdd_kernel gen_op_std_kernel
5585#define gen_op_spe_stdd_hypv gen_op_std_hypv
5586#define gen_op_spe_stdd_64_raw gen_op_std_64_raw
5587#define gen_op_spe_stdd_64_user gen_op_std_64_user
5588#define gen_op_spe_stdd_64_kernel gen_op_std_64_kernel
5589#define gen_op_spe_stdd_64_hypv gen_op_std_64_hypv
5590#define gen_op_spe_stdd_le_raw gen_op_std_le_raw
5591#define gen_op_spe_stdd_le_user gen_op_std_le_user
5592#define gen_op_spe_stdd_le_kernel gen_op_std_le_kernel
5593#define gen_op_spe_stdd_le_hypv gen_op_std_le_hypv
5594#define gen_op_spe_stdd_le_64_raw gen_op_std_le_64_raw
5595#define gen_op_spe_stdd_le_64_user gen_op_std_le_64_user
5596#define gen_op_spe_stdd_le_64_kernel gen_op_std_le_64_kernel
5597#define gen_op_spe_stdd_le_64_hypv gen_op_std_le_64_hypv
0487d6a8
JM		 5598#endif /* defined(TARGET_PPC64) */
5599GEN_SPEOP_LDST(dd, 3);
5600GEN_SPEOP_LDST(dw, 3);
5601GEN_SPEOP_LDST(dh, 3);
5602GEN_SPEOP_LDST(whe, 2);
5603GEN_SPEOP_LD(whou, 2);
5604GEN_SPEOP_LD(whos, 2);
5605GEN_SPEOP_ST(who, 2);
5606
5607#if defined(TARGET_PPC64)
5608/* In that case, spe_stwwo is equivalent to stw */
7863667f
JM		 5609#define gen_op_spe_stwwo_raw gen_op_stw_raw
5610#define gen_op_spe_stwwo_user gen_op_stw_user
5611#define gen_op_spe_stwwo_kernel gen_op_stw_kernel
5612#define gen_op_spe_stwwo_hypv gen_op_stw_hypv
5613#define gen_op_spe_stwwo_le_raw gen_op_stw_le_raw
5614#define gen_op_spe_stwwo_le_user gen_op_stw_le_user
5615#define gen_op_spe_stwwo_le_kernel gen_op_stw_le_kernel
5616#define gen_op_spe_stwwo_le_hypv gen_op_stw_le_hypv
5617#define gen_op_spe_stwwo_64_raw gen_op_stw_64_raw
5618#define gen_op_spe_stwwo_64_user gen_op_stw_64_user
5619#define gen_op_spe_stwwo_64_kernel gen_op_stw_64_kernel
5620#define gen_op_spe_stwwo_64_hypv gen_op_stw_64_hypv
5621#define gen_op_spe_stwwo_le_64_raw gen_op_stw_le_64_raw
5622#define gen_op_spe_stwwo_le_64_user gen_op_stw_le_64_user
0487d6a8 5623#define gen_op_spe_stwwo_le_64_kernel gen_op_stw_le_64_kernel
7863667f 5624#define gen_op_spe_stwwo_le_64_hypv gen_op_stw_le_64_hypv
0487d6a8
JM		 5625#endif
5626#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 5627static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 5628{ \
5629 gen_op_srli32_T1_64(); \
5630 gen_op_spe_stwwo_##suffix(); \
5631}
5632#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 5633static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 5634{ \
5635 gen_op_srli32_T1_64(); \
5636 gen_op_spe_stwwo_le_##suffix(); \
5637}
5638#if defined(TARGET_PPC64)
5639#define GEN_OP_SPE_STWWE(suffix) \
5640_GEN_OP_SPE_STWWE(suffix); \
5641_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 5642static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 5643{ \
5644 gen_op_srli32_T1_64(); \
5645 gen_op_spe_stwwo_64_##suffix(); \
5646} \
b068d6a7 5647static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 5648{ \
5649 gen_op_srli32_T1_64(); \
5650 gen_op_spe_stwwo_le_64_##suffix(); \
5651}
5652#else
5653#define GEN_OP_SPE_STWWE(suffix) \
5654_GEN_OP_SPE_STWWE(suffix); \
5655_GEN_OP_SPE_STWWE_LE(suffix)
5656#endif
5657#if defined(CONFIG_USER_ONLY)
5658GEN_OP_SPE_STWWE(raw);
5659#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 5660GEN_OP_SPE_STWWE(user);
7863667f
JM		 5661GEN_OP_SPE_STWWE(kernel);
5662GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 5663#endif /* defined(CONFIG_USER_ONLY) */
5664GEN_SPEOP_ST(wwe, 2);
5665GEN_SPEOP_ST(wwo, 2);
5666
5667#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 5668static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 5669{ \
5670 gen_op_##op##_##suffix(); \
5671 gen_op_splatw_T1_64(); \
5672}
5673
5674#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 5675static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 5676{ \
5677 gen_op_spe_lh_##suffix(); \
5678 gen_op_sli16_T1_64(); \
5679}
5680
5681#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 5682static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 5683{ \
5684 gen_op_spe_lh_##suffix(); \
5685 gen_op_extsh_T1_64(); \
5686}
5687
5688#if defined(CONFIG_USER_ONLY)
5689GEN_OP_SPE_LHE(raw);
5690GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
5691GEN_OP_SPE_LHE(le_raw);
5692GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
5693GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
5694GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
5695GEN_OP_SPE_LHX(raw);
5696GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
5697GEN_OP_SPE_LHX(le_raw);
5698GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
5699#if defined(TARGET_PPC64)
5700GEN_OP_SPE_LHE(64_raw);
5701GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
5702GEN_OP_SPE_LHE(le_64_raw);
5703GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
5704GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
5705GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
5706GEN_OP_SPE_LHX(64_raw);
5707GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
5708GEN_OP_SPE_LHX(le_64_raw);
5709GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
5710#endif
5711#else
0487d6a8 5712GEN_OP_SPE_LHE(user);
7863667f
JM		 5713GEN_OP_SPE_LHE(kernel);
5714GEN_OP_SPE_LHE(hypv);
0487d6a8 5715GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 5716GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
5717GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 5718GEN_OP_SPE_LHE(le_user);
7863667f
JM		 5719GEN_OP_SPE_LHE(le_kernel);
5720GEN_OP_SPE_LHE(le_hypv);
0487d6a8 5721GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 5722GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
5723GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 5724GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 5725GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
5726GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 5727GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 5728GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
5729GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 5730GEN_OP_SPE_LHX(user);
7863667f
JM		 5731GEN_OP_SPE_LHX(kernel);
5732GEN_OP_SPE_LHX(hypv);
0487d6a8 5733GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 5734GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
5735GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 5736GEN_OP_SPE_LHX(le_user);
7863667f
JM		 5737GEN_OP_SPE_LHX(le_kernel);
5738GEN_OP_SPE_LHX(le_hypv);
0487d6a8 5739GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 5740GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
5741GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 5742#if defined(TARGET_PPC64)
0487d6a8 5743GEN_OP_SPE_LHE(64_user);
7863667f
JM		 5744GEN_OP_SPE_LHE(64_kernel);
5745GEN_OP_SPE_LHE(64_hypv);
0487d6a8 5746GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 5747GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
5748GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 5749GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 5750GEN_OP_SPE_LHE(le_64_kernel);
5751GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 5752GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 5753GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
5754GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 5755GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 5756GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
5757GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 5758GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 5759GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
5760GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 5761GEN_OP_SPE_LHX(64_user);
7863667f
JM		 5762GEN_OP_SPE_LHX(64_kernel);
5763GEN_OP_SPE_LHX(64_hypv);
0487d6a8 5764GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 5765GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
5766GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 5767GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 5768GEN_OP_SPE_LHX(le_64_kernel);
5769GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 5770GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 5771GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
5772GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 5773#endif
5774#endif
5775GEN_SPEOP_LD(hhesplat, 1);
5776GEN_SPEOP_LD(hhousplat, 1);
5777GEN_SPEOP_LD(hhossplat, 1);
5778GEN_SPEOP_LD(wwsplat, 2);
5779GEN_SPEOP_LD(whsplat, 2);
5780
5781GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
5782GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
5783GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
5784GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
5785GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
5786GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
5787GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
5788GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
5789GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
5790GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
5791GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
5792GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
5793GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
5794GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
5795GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
5796GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
5797GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
5798GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
5799
5800/* Multiply and add - TODO */
5801#if 0
5802GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
5803GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
5804GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
5805GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
5806GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
5807GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
5808GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
5809GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
5810GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
5811GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
5812GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
5813GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
5814
5815GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
5816GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
5817GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
5818GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
5819GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
5820GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
5821GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
5822GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
5823GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
5824GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
5825GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
5826GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
5827GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
5828GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
5829
5830GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
5831GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
5832GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
5833GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
5834GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
5835GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
5836
5837GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
5838GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
5839GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
5840GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
5841GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
5842GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
5843GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
5844GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
5845GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
5846GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
5847GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
5848GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
5849
5850GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
5851GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
5852GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
5853GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
5854GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
5855
5856GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
5857GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
5858GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
5859GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
5860GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
5861GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
5862GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
5863GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
5864GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
5865GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
5866GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
5867GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
5868
5869GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
5870GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
5871GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
5872GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
5873GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
5874#endif
5875
5876/*** SPE floating-point extension ***/
5877#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 5878static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5879{ \
5880 gen_op_load_gpr64_T0(rB(ctx->opcode)); \
5881 gen_op_##name(); \
5882 gen_op_store_T0_gpr64(rD(ctx->opcode)); \
5883}
5884
5885/* Single precision floating-point vectors operations */
5886/* Arithmetic */
5887GEN_SPEOP_ARITH2(evfsadd);
5888GEN_SPEOP_ARITH2(evfssub);
5889GEN_SPEOP_ARITH2(evfsmul);
5890GEN_SPEOP_ARITH2(evfsdiv);
5891GEN_SPEOP_ARITH1(evfsabs);
5892GEN_SPEOP_ARITH1(evfsnabs);
5893GEN_SPEOP_ARITH1(evfsneg);
5894/* Conversion */
5895GEN_SPEFPUOP_CONV(evfscfui);
5896GEN_SPEFPUOP_CONV(evfscfsi);
5897GEN_SPEFPUOP_CONV(evfscfuf);
5898GEN_SPEFPUOP_CONV(evfscfsf);
5899GEN_SPEFPUOP_CONV(evfsctui);
5900GEN_SPEFPUOP_CONV(evfsctsi);
5901GEN_SPEFPUOP_CONV(evfsctuf);
5902GEN_SPEFPUOP_CONV(evfsctsf);
5903GEN_SPEFPUOP_CONV(evfsctuiz);
5904GEN_SPEFPUOP_CONV(evfsctsiz);
5905/* Comparison */
5906GEN_SPEOP_COMP(evfscmpgt);
5907GEN_SPEOP_COMP(evfscmplt);
5908GEN_SPEOP_COMP(evfscmpeq);
5909GEN_SPEOP_COMP(evfststgt);
5910GEN_SPEOP_COMP(evfststlt);
5911GEN_SPEOP_COMP(evfststeq);
5912
5913/* Opcodes definitions */
5914GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
5915GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
5916GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
5917GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
5918GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
5919GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
5920GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
5921GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
5922GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
5923GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
5924GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
5925GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
5926GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
5927GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
5928
5929/* Single precision floating-point operations */
5930/* Arithmetic */
5931GEN_SPEOP_ARITH2(efsadd);
5932GEN_SPEOP_ARITH2(efssub);
5933GEN_SPEOP_ARITH2(efsmul);
5934GEN_SPEOP_ARITH2(efsdiv);
5935GEN_SPEOP_ARITH1(efsabs);
5936GEN_SPEOP_ARITH1(efsnabs);
5937GEN_SPEOP_ARITH1(efsneg);
5938/* Conversion */
5939GEN_SPEFPUOP_CONV(efscfui);
5940GEN_SPEFPUOP_CONV(efscfsi);
5941GEN_SPEFPUOP_CONV(efscfuf);
5942GEN_SPEFPUOP_CONV(efscfsf);
5943GEN_SPEFPUOP_CONV(efsctui);
5944GEN_SPEFPUOP_CONV(efsctsi);
5945GEN_SPEFPUOP_CONV(efsctuf);
5946GEN_SPEFPUOP_CONV(efsctsf);
5947GEN_SPEFPUOP_CONV(efsctuiz);
5948GEN_SPEFPUOP_CONV(efsctsiz);
5949GEN_SPEFPUOP_CONV(efscfd);
5950/* Comparison */
5951GEN_SPEOP_COMP(efscmpgt);
5952GEN_SPEOP_COMP(efscmplt);
5953GEN_SPEOP_COMP(efscmpeq);
5954GEN_SPEOP_COMP(efststgt);
5955GEN_SPEOP_COMP(efststlt);
5956GEN_SPEOP_COMP(efststeq);
5957
5958/* Opcodes definitions */
05332d70 5959GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 5960GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
5961GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
5962GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
5963GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
5964GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
5965GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
5966GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
5967GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
5968GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
5969GEN_SPE(efsctuiz, efsctsiz, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
5970GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
5971GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
5972
5973/* Double precision floating-point operations */
5974/* Arithmetic */
5975GEN_SPEOP_ARITH2(efdadd);
5976GEN_SPEOP_ARITH2(efdsub);
5977GEN_SPEOP_ARITH2(efdmul);
5978GEN_SPEOP_ARITH2(efddiv);
5979GEN_SPEOP_ARITH1(efdabs);
5980GEN_SPEOP_ARITH1(efdnabs);
5981GEN_SPEOP_ARITH1(efdneg);
5982/* Conversion */
5983
5984GEN_SPEFPUOP_CONV(efdcfui);
5985GEN_SPEFPUOP_CONV(efdcfsi);
5986GEN_SPEFPUOP_CONV(efdcfuf);
5987GEN_SPEFPUOP_CONV(efdcfsf);
5988GEN_SPEFPUOP_CONV(efdctui);
5989GEN_SPEFPUOP_CONV(efdctsi);
5990GEN_SPEFPUOP_CONV(efdctuf);
5991GEN_SPEFPUOP_CONV(efdctsf);
5992GEN_SPEFPUOP_CONV(efdctuiz);
5993GEN_SPEFPUOP_CONV(efdctsiz);
5994GEN_SPEFPUOP_CONV(efdcfs);
5995GEN_SPEFPUOP_CONV(efdcfuid);
5996GEN_SPEFPUOP_CONV(efdcfsid);
5997GEN_SPEFPUOP_CONV(efdctuidz);
5998GEN_SPEFPUOP_CONV(efdctsidz);
5999/* Comparison */
6000GEN_SPEOP_COMP(efdcmpgt);
6001GEN_SPEOP_COMP(efdcmplt);
6002GEN_SPEOP_COMP(efdcmpeq);
6003GEN_SPEOP_COMP(efdtstgt);
6004GEN_SPEOP_COMP(efdtstlt);
6005GEN_SPEOP_COMP(efdtsteq);
6006
6007/* Opcodes definitions */
6008GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6009GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6010GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6011GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6012GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6013GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6014GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6015GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6016GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6017GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6018GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6019GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6020GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6021GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6022GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6023GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6024
79aceca5
FB		 6025/* End opcode list */
6026GEN_OPCODE_MARK(end);
6027
3fc6c082 6028#include "translate_init.c"
0411a972 6029#include "helper_regs.h"
79aceca5 6030
9a64fbe4 6031/*****************************************************************************/
3fc6c082 6032/* Misc PowerPC helpers */
36081602
JM		 6033void cpu_dump_state (CPUState *env, FILE *f,
6034 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6035 int flags)
79aceca5 6036{
3fc6c082
FB		 6037#define RGPL 4
6038#define RFPL 4
3fc6c082 6039
79aceca5
FB		 6040 int i;
6041
077fc206
JM		 6042 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
6043 env->nip, env->lr, env->ctr, hreg_load_xer(env));
6b542af7
JM		 6044 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6045 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 6046#if !defined(NO_TIMER_DUMP)
077fc206 6047 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6048#if !defined(CONFIG_USER_ONLY)
6049 "DECR %08x"
6050#endif
6051 "\n",
077fc206 6052 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6053#if !defined(CONFIG_USER_ONLY)
6054 , cpu_ppc_load_decr(env)
6055#endif
6056 );
077fc206 6057#endif
76a66253 6058 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6059 if ((i & (RGPL - 1)) == 0)
6060 cpu_fprintf(f, "GPR%02d", i);
6b542af7 6061 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 6062 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6063 cpu_fprintf(f, "\n");
76a66253 6064 }
3fc6c082 6065 cpu_fprintf(f, "CR ");
76a66253 6066 for (i = 0; i < 8; i++)
7fe48483
FB		 6067 cpu_fprintf(f, "%01x", env->crf[i]);
6068 cpu_fprintf(f, " [");
76a66253
JM		 6069 for (i = 0; i < 8; i++) {
6070 char a = '-';
6071 if (env->crf[i] & 0x08)
6072 a = 'L';
6073 else if (env->crf[i] & 0x04)
6074 a = 'G';
6075 else if (env->crf[i] & 0x02)
6076 a = 'E';
7fe48483 6077 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6078 }
6b542af7 6079 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 6080 for (i = 0; i < 32; i++) {
6081 if ((i & (RFPL - 1)) == 0)
6082 cpu_fprintf(f, "FPR%02d", i);
26a76461 6083 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6084 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6085 cpu_fprintf(f, "\n");
79aceca5 6086 }
f2e63a42 6087#if !defined(CONFIG_USER_ONLY)
6b542af7 6088 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 6089 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6090#endif
79aceca5 6091
3fc6c082
FB		 6092#undef RGPL
6093#undef RFPL
79aceca5
FB		 6094}
6095
76a66253
JM		 6096void cpu_dump_statistics (CPUState *env, FILE*f,
6097 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6098 int flags)
6099{
6100#if defined(DO_PPC_STATISTICS)
6101 opc_handler_t **t1, **t2, **t3, *handler;
6102 int op1, op2, op3;
6103
6104 t1 = env->opcodes;
6105 for (op1 = 0; op1 < 64; op1++) {
6106 handler = t1[op1];
6107 if (is_indirect_opcode(handler)) {
6108 t2 = ind_table(handler);
6109 for (op2 = 0; op2 < 32; op2++) {
6110 handler = t2[op2];
6111 if (is_indirect_opcode(handler)) {
6112 t3 = ind_table(handler);
6113 for (op3 = 0; op3 < 32; op3++) {
6114 handler = t3[op3];
6115 if (handler->count == 0)
6116 continue;
6117 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6118 "%016llx %lld\n",
6119 op1, op2, op3, op1, (op3 << 5) | op2,
6120 handler->oname,
6121 handler->count, handler->count);
6122 }
6123 } else {
6124 if (handler->count == 0)
6125 continue;
6126 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6127 "%016llx %lld\n",
6128 op1, op2, op1, op2, handler->oname,
6129 handler->count, handler->count);
6130 }
6131 }
6132 } else {
6133 if (handler->count == 0)
6134 continue;
6135 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6136 op1, op1, handler->oname,
6137 handler->count, handler->count);
6138 }
6139 }
6140#endif
6141}
6142
9a64fbe4 6143/*****************************************************************************/
b068d6a7
JM		 6144static always_inline int gen_intermediate_code_internal (CPUState *env,
6145 TranslationBlock *tb,
6146 int search_pc)
79aceca5 6147{
9fddaa0c 6148 DisasContext ctx, *ctxp = &ctx;
79aceca5 6149 opc_handler_t **table, *handler;
0fa85d43 6150 target_ulong pc_start;
79aceca5 6151 uint16_t *gen_opc_end;
056401ea 6152 int supervisor, little_endian;
d26bfc9a 6153 int single_step, branch_step;
79aceca5 6154 int j, lj = -1;
79aceca5
FB		 6155
6156 pc_start = tb->pc;
79aceca5 6157 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 6158#if defined(OPTIMIZE_FPRF_UPDATE)
6159 gen_fprf_ptr = gen_fprf_buf;
6160#endif
046d6672 6161 ctx.nip = pc_start;
79aceca5 6162 ctx.tb = tb;
e1833e1f 6163 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6164 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6165 supervisor = env->mmu_idx;
6166#if !defined(CONFIG_USER_ONLY)
2857068e 6167 ctx.supervisor = supervisor;
d9bce9d9 6168#endif
056401ea 6169 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6170#if defined(TARGET_PPC64)
6171 ctx.sf_mode = msr_sf;
056401ea 6172 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6173#else
056401ea 6174 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6175#endif
d63001d1 6176 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6177 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6178 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6179 ctx.spe_enabled = msr_spe;
6180 else
6181 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6182 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6183 ctx.altivec_enabled = msr_vr;
6184 else
6185 ctx.altivec_enabled = 0;
d26bfc9a
JM		 6186 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
6187 single_step = 1;
6188 else
6189 single_step = 0;
6190 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
6191 branch_step = 1;
6192 else
6193 branch_step = 0;
b33c17e1 6194 ctx.singlestep_enabled = env->singlestep_enabled || single_step == 1;
3fc6c082 6195#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6196 /* Single step trace mode */
6197 msr_se = 1;
6198#endif
6199 /* Set env in case of segfault during code fetch */
e1833e1f 6200 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6201 if (unlikely(env->nb_breakpoints > 0)) {
6202 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6203 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6204 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6205 gen_op_debug();
6206 break;
6207 }
6208 }
6209 }
76a66253 6210 if (unlikely(search_pc)) {
79aceca5
FB		 6211 j = gen_opc_ptr - gen_opc_buf;
6212 if (lj < j) {
6213 lj++;
6214 while (lj < j)
6215 gen_opc_instr_start[lj++] = 0;
046d6672 6216 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 6217 gen_opc_instr_start[lj] = 1;
6218 }
6219 }
9fddaa0c
FB		 6220#if defined PPC_DEBUG_DISAS
6221 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6222 fprintf(logfile, "----------------\n");
1b9eb036 6223 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6224 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6225 }
6226#endif
056401ea
JM		 6227 if (unlikely(little_endian)) {
6228 ctx.opcode = bswap32(ldl_code(ctx.nip));
6229 } else {
6230 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6231 }
9fddaa0c
FB		 6232#if defined PPC_DEBUG_DISAS
6233 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6234 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6235 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6236 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6237 }
6238#endif
046d6672 6239 ctx.nip += 4;
3fc6c082 6240 table = env->opcodes;
79aceca5
FB		 6241 handler = table[opc1(ctx.opcode)];
6242 if (is_indirect_opcode(handler)) {
6243 table = ind_table(handler);
6244 handler = table[opc2(ctx.opcode)];
6245 if (is_indirect_opcode(handler)) {
6246 table = ind_table(handler);
6247 handler = table[opc3(ctx.opcode)];
6248 }
6249 }
6250 /* Is opcode *REALLY* valid ? */
76a66253 6251 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6252 if (loglevel != 0) {
76a66253 6253 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 6254 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 6255 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6256 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6257 } else {
6258 printf("invalid/unsupported opcode: "
6b542af7 6259 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 6260 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6261 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6262 }
76a66253
JM		 6263 } else {
6264 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6265 if (loglevel != 0) {
79aceca5 6266 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 6267 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 6268 ctx.opcode & handler->inval, opc1(ctx.opcode),
6269 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6270 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6271 } else {
6272 printf("invalid bits: %08x for opcode: "
6b542af7 6273 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 6274 ctx.opcode & handler->inval, opc1(ctx.opcode),
6275 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6276 ctx.opcode, ctx.nip - 4);
76a66253 6277 }
e1833e1f 6278 GEN_EXCP_INVAL(ctxp);
4b3686fa 6279 break;
79aceca5 6280 }
79aceca5 6281 }
4b3686fa 6282 (*(handler->handler))(&ctx);
76a66253
JM		 6283#if defined(DO_PPC_STATISTICS)
6284 handler->count++;
6285#endif
9a64fbe4 6286 /* Check trace mode exceptions */
d26bfc9a
JM		 6287 if (unlikely(branch_step != 0 &&
6288 ctx.exception == POWERPC_EXCP_BRANCH)) {
6289 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
6290 } else if (unlikely(single_step != 0 &&
6291 (ctx.nip <= 0x100 || ctx.nip > 0xF00 ||
6292 (ctx.nip & 0xFC) != 0x04) &&
417bf010 6293 ctx.exception != POWERPC_SYSCALL &&
d26bfc9a 6294 ctx.exception != POWERPC_EXCP_TRAP)) {
e1833e1f 6295 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a
JM		 6296 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
6297 (env->singlestep_enabled))) {
6298 /* if we reach a page boundary or are single stepping, stop
6299 * generation
6300 */
8dd4983c 6301 break;
76a66253 6302 }
3fc6c082
FB		 6303#if defined (DO_SINGLE_STEP)
6304 break;
6305#endif
6306 }
e1833e1f 6307 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6308 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6309 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
76a66253 6310 /* Generate the return instruction */
57fec1fe 6311 tcg_gen_exit_tb(0);
9a64fbe4 6312 }
79aceca5 6313 *gen_opc_ptr = INDEX_op_end;
76a66253 6314 if (unlikely(search_pc)) {
9a64fbe4
FB		 6315 j = gen_opc_ptr - gen_opc_buf;
6316 lj++;
6317 while (lj <= j)
6318 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6319 } else {
046d6672 6320 tb->size = ctx.nip - pc_start;
9a64fbe4 6321 }
d9bce9d9 6322#if defined(DEBUG_DISAS)
9fddaa0c 6323 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6324 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6325 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6326 }
6327 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6328 int flags;
237c0af0 6329 flags = env->bfd_mach;
056401ea 6330 flags |= little_endian << 16;
0fa85d43 6331 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6332 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6333 fprintf(logfile, "\n");
9fddaa0c 6334 }
79aceca5 6335#endif
79aceca5
FB		 6336 return 0;
6337}
6338
9a64fbe4 6339int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 6340{
6341 return gen_intermediate_code_internal(env, tb, 0);
6342}
6343
9a64fbe4 6344int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 6345{
6346 return gen_intermediate_code_internal(env, tb, 1);
6347}
d2856f1a
AJ		 6348
6349void gen_pc_load(CPUState *env, TranslationBlock *tb,
6350 unsigned long searched_pc, int pc_pos, void *puc)
6351{
6352 int type, c;
6353 /* for PPC, we need to look at the micro operation to get the
6354 * access type */
6355 env->nip = gen_opc_pc[pc_pos];
6356 c = gen_opc_buf[pc_pos];
6357 switch(c) {
6358#if defined(CONFIG_USER_ONLY)
6359#define CASE3(op)\
6360 case INDEX_op_ ## op ## _raw
6361#else
6362#define CASE3(op)\
6363 case INDEX_op_ ## op ## _user:\
6364 case INDEX_op_ ## op ## _kernel:\
6365 case INDEX_op_ ## op ## _hypv
6366#endif
6367
6368 CASE3(stfd):
6369 CASE3(stfs):
6370 CASE3(lfd):
6371 CASE3(lfs):
6372 type = ACCESS_FLOAT;
6373 break;
6374 CASE3(lwarx):
6375 type = ACCESS_RES;
6376 break;
6377 CASE3(stwcx):
6378 type = ACCESS_RES;
6379 break;
6380 CASE3(eciwx):
6381 CASE3(ecowx):
6382 type = ACCESS_EXT;
6383 break;
6384 default:
6385 type = ACCESS_INT;
6386 break;
6387 }
6388 env->access_type = type;
6389}
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