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Fix regression introduced by r6824
[mirror_qemu.git] / target-ppc / translate.c
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
fad6cb1a 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
79aceca5 19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
57fec1fe 29#include "tcg-op.h"
ca10f867 30#include "qemu-common.h"
0cfe11ea 31#include "host-utils.h"
79aceca5 32
a7812ae4
PB		 33#include "helper.h"
34#define GEN_HELPER 1
35#include "helper.h"
36
8cbcb4fa
AJ		 37#define CPU_SINGLE_STEP 0x1
38#define CPU_BRANCH_STEP 0x2
39#define GDBSTUB_SINGLE_STEP 0x4
40
a750fc0b 41/* Include definitions for instructions classes and implementations flags */
e8fc4fa7 42//#define DO_SINGLE_STEP
9fddaa0c 43//#define PPC_DEBUG_DISAS
76a66253 44//#define DO_PPC_STATISTICS
79aceca5 45
d12d51d5 46#ifdef PPC_DEBUG_DISAS
93fcfe39 47# define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
d12d51d5
AL		 48#else
49# define LOG_DISAS(...) do { } while (0)
50#endif
a750fc0b
JM		 51/*****************************************************************************/
52/* Code translation helpers */
c53be334 53
f78fb44e 54/* global register indexes */
a7812ae4 55static TCGv_ptr cpu_env;
1d542695 56static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 57#if !defined(TARGET_PPC64)
1d542695 58 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 59#endif
a5e26afa 60 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 61 + 2*(10*6 + 22*7) /* AVRh, AVRl */
62 + 8*5 /* CRF */];
f78fb44e
AJ		 63static TCGv cpu_gpr[32];
64#if !defined(TARGET_PPC64)
65static TCGv cpu_gprh[32];
66#endif
a7812ae4
PB		 67static TCGv_i64 cpu_fpr[32];
68static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
69static TCGv_i32 cpu_crf[8];
bd568f18 70static TCGv cpu_nip;
6527f6ea 71static TCGv cpu_msr;
cfdcd37a
AJ		 72static TCGv cpu_ctr;
73static TCGv cpu_lr;
3d7b417e 74static TCGv cpu_xer;
cf360a32 75static TCGv cpu_reserve;
a7812ae4 76static TCGv_i32 cpu_fpscr;
a7859e89 77static TCGv_i32 cpu_access_type;
f78fb44e 78
2e70f6ef
PB		 79#include "gen-icount.h"
80
81void ppc_translate_init(void)
82{
f78fb44e
AJ		 83 int i;
84 char* p;
b2437bf2 85 static int done_init = 0;
f78fb44e 86
2e70f6ef
PB		 87 if (done_init)
88 return;
f78fb44e 89
a7812ae4 90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
a7812ae4 91
f78fb44e 92 p = cpu_reg_names;
47e4661c
AJ		 93
94 for (i = 0; i < 8; i++) {
95 sprintf(p, "crf%d", i);
a7812ae4
PB		 96 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
97 offsetof(CPUState, crf[i]), p);
47e4661c
AJ		 98 p += 5;
99 }
100
f78fb44e
AJ		 101 for (i = 0; i < 32; i++) {
102 sprintf(p, "r%d", i);
a7812ae4 103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
f78fb44e
AJ		 104 offsetof(CPUState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106#if !defined(TARGET_PPC64)
107 sprintf(p, "r%dH", i);
a7812ae4
PB		 108 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
109 offsetof(CPUState, gprh[i]), p);
f78fb44e
AJ		 110 p += (i < 10) ? 4 : 5;
111#endif
1d542695 112
a5e26afa 113 sprintf(p, "fp%d", i);
a7812ae4
PB		 114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUState, fpr[i]), p);
ec1ac72d 116 p += (i < 10) ? 4 : 5;
a5e26afa 117
1d542695 118 sprintf(p, "avr%dH", i);
fe1e5c53
AJ		 119#ifdef WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUState, avr[i].u64[0]), p);
122#else
a7812ae4 123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 124 offsetof(CPUState, avr[i].u64[1]), p);
125#endif
1d542695 126 p += (i < 10) ? 6 : 7;
ec1ac72d 127
1d542695 128 sprintf(p, "avr%dL", i);
fe1e5c53
AJ		 129#ifdef WORDS_BIGENDIAN
130 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
131 offsetof(CPUState, avr[i].u64[1]), p);
132#else
a7812ae4 133 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
fe1e5c53
AJ		 134 offsetof(CPUState, avr[i].u64[0]), p);
135#endif
1d542695 136 p += (i < 10) ? 6 : 7;
f78fb44e 137 }
f10dc08e 138
a7812ae4 139 cpu_nip = tcg_global_mem_new(TCG_AREG0,
bd568f18
AJ		 140 offsetof(CPUState, nip), "nip");
141
6527f6ea
AJ		 142 cpu_msr = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUState, msr), "msr");
144
a7812ae4 145 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 146 offsetof(CPUState, ctr), "ctr");
147
a7812ae4 148 cpu_lr = tcg_global_mem_new(TCG_AREG0,
cfdcd37a
AJ		 149 offsetof(CPUState, lr), "lr");
150
a7812ae4 151 cpu_xer = tcg_global_mem_new(TCG_AREG0,
3d7b417e
AJ		 152 offsetof(CPUState, xer), "xer");
153
cf360a32
AJ		 154 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
155 offsetof(CPUState, reserve), "reserve");
156
a7812ae4
PB		 157 cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
158 offsetof(CPUState, fpscr), "fpscr");
e1571908 159
a7859e89
AJ		 160 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
161 offsetof(CPUState, access_type), "access_type");
162
f10dc08e 163 /* register helpers */
a7812ae4 164#define GEN_HELPER 2
f10dc08e
AJ		 165#include "helper.h"
166
2e70f6ef
PB		 167 done_init = 1;
168}
169
79aceca5
FB		 170/* internal defines */
171typedef struct DisasContext {
172 struct TranslationBlock *tb;
0fa85d43 173 target_ulong nip;
79aceca5 174 uint32_t opcode;
9a64fbe4 175 uint32_t exception;
3cc62370
FB		 176 /* Routine used to access memory */
177 int mem_idx;
76db3ba4 178 int access_type;
3cc62370 179 /* Translation flags */
76db3ba4 180 int le_mode;
d9bce9d9
JM		 181#if defined(TARGET_PPC64)
182 int sf_mode;
9a64fbe4 183#endif
3cc62370 184 int fpu_enabled;
a9d9eb8f 185 int altivec_enabled;
0487d6a8 186 int spe_enabled;
3fc6c082 187 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 188 int singlestep_enabled;
79aceca5
FB		 189} DisasContext;
190
3fc6c082 191struct opc_handler_t {
79aceca5
FB		 192 /* invalid bits */
193 uint32_t inval;
9a64fbe4 194 /* instruction type */
0487d6a8 195 uint64_t type;
79aceca5
FB		 196 /* handler */
197 void (*handler)(DisasContext *ctx);
a750fc0b 198#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 199 const char *oname;
a750fc0b
JM		 200#endif
201#if defined(DO_PPC_STATISTICS)
76a66253
JM		 202 uint64_t count;
203#endif
3fc6c082 204};
79aceca5 205
7c58044c
JM		 206static always_inline void gen_reset_fpstatus (void)
207{
208#ifdef CONFIG_SOFTFLOAT
a44d2ce1 209 gen_helper_reset_fpstatus();
7c58044c
JM		 210#endif
211}
212
0f2f39c2 213static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
7c58044c 214{
0f2f39c2 215 TCGv_i32 t0 = tcg_temp_new_i32();
af12906f 216
7c58044c
JM		 217 if (set_fprf != 0) {
218 /* This case might be optimized later */
0f2f39c2 219 tcg_gen_movi_i32(t0, 1);
af12906f 220 gen_helper_compute_fprf(t0, arg, t0);
a7812ae4 221 if (unlikely(set_rc)) {
0f2f39c2 222 tcg_gen_mov_i32(cpu_crf[1], t0);
a7812ae4 223 }
af12906f 224 gen_helper_float_check_status();
7c58044c
JM		 225 } else if (unlikely(set_rc)) {
226 /* We always need to compute fpcc */
0f2f39c2 227 tcg_gen_movi_i32(t0, 0);
af12906f 228 gen_helper_compute_fprf(t0, arg, t0);
0f2f39c2 229 tcg_gen_mov_i32(cpu_crf[1], t0);
7c58044c 230 }
af12906f 231
0f2f39c2 232 tcg_temp_free_i32(t0);
7c58044c
JM		 233}
234
76db3ba4 235static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
a7859e89 236{
76db3ba4
AJ		 237 if (ctx->access_type != access_type) {
238 tcg_gen_movi_i32(cpu_access_type, access_type);
239 ctx->access_type = access_type;
240 }
a7859e89
AJ		 241}
242
b068d6a7 243static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 244{
245#if defined(TARGET_PPC64)
246 if (ctx->sf_mode)
bd568f18 247 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 248 else
249#endif
bd568f18 250 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 251}
252
e06fcd75
AJ		 253static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
254{
255 TCGv_i32 t0, t1;
256 if (ctx->exception == POWERPC_EXCP_NONE) {
257 gen_update_nip(ctx, ctx->nip);
258 }
259 t0 = tcg_const_i32(excp);
260 t1 = tcg_const_i32(error);
261 gen_helper_raise_exception_err(t0, t1);
262 tcg_temp_free_i32(t0);
263 tcg_temp_free_i32(t1);
264 ctx->exception = (excp);
265}
e1833e1f 266
e06fcd75
AJ		 267static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
268{
269 TCGv_i32 t0;
270 if (ctx->exception == POWERPC_EXCP_NONE) {
271 gen_update_nip(ctx, ctx->nip);
272 }
273 t0 = tcg_const_i32(excp);
274 gen_helper_raise_exception(t0);
275 tcg_temp_free_i32(t0);
276 ctx->exception = (excp);
277}
e1833e1f 278
e06fcd75
AJ		 279static always_inline void gen_debug_exception (DisasContext *ctx)
280{
281 TCGv_i32 t0;
5518f3a6
BS		 282
283 if (ctx->exception != POWERPC_EXCP_BRANCH)
284 gen_update_nip(ctx, ctx->nip);
e06fcd75
AJ		 285 t0 = tcg_const_i32(EXCP_DEBUG);
286 gen_helper_raise_exception(t0);
287 tcg_temp_free_i32(t0);
288}
9a64fbe4 289
e06fcd75
AJ		 290static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
291{
292 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
293}
a9d9eb8f 294
f24e5695 295/* Stop translation */
e06fcd75 296static always_inline void gen_stop_exception (DisasContext *ctx)
3fc6c082 297{
d9bce9d9 298 gen_update_nip(ctx, ctx->nip);
e1833e1f 299 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 300}
301
f24e5695 302/* No need to update nip here, as execution flow will change */
e06fcd75 303static always_inline void gen_sync_exception (DisasContext *ctx)
2be0071f 304{
e1833e1f 305 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 306}
307
79aceca5
FB		 308#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
309static void gen_##name (DisasContext *ctx); \
310GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
311static void gen_##name (DisasContext *ctx)
312
c7697e1f
JM		 313#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
314static void gen_##name (DisasContext *ctx); \
315GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
316static void gen_##name (DisasContext *ctx)
317
79aceca5
FB		 318typedef struct opcode_t {
319 unsigned char opc1, opc2, opc3;
1235fc06 320#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 321 unsigned char pad[5];
322#else
323 unsigned char pad[1];
324#endif
79aceca5 325 opc_handler_t handler;
b55266b5 326 const char *oname;
79aceca5
FB		 327} opcode_t;
328
a750fc0b 329/*****************************************************************************/
79aceca5
FB		 330/*** Instruction decoding ***/
331#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 332static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 333{ \
334 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
335}
336
337#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 338static always_inline int32_t name (uint32_t opcode) \
79aceca5 339{ \
18fba28c 340 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 341}
342
343/* Opcode part 1 */
344EXTRACT_HELPER(opc1, 26, 6);
345/* Opcode part 2 */
346EXTRACT_HELPER(opc2, 1, 5);
347/* Opcode part 3 */
348EXTRACT_HELPER(opc3, 6, 5);
349/* Update Cr0 flags */
350EXTRACT_HELPER(Rc, 0, 1);
351/* Destination */
352EXTRACT_HELPER(rD, 21, 5);
353/* Source */
354EXTRACT_HELPER(rS, 21, 5);
355/* First operand */
356EXTRACT_HELPER(rA, 16, 5);
357/* Second operand */
358EXTRACT_HELPER(rB, 11, 5);
359/* Third operand */
360EXTRACT_HELPER(rC, 6, 5);
361/*** Get CRn ***/
362EXTRACT_HELPER(crfD, 23, 3);
363EXTRACT_HELPER(crfS, 18, 3);
364EXTRACT_HELPER(crbD, 21, 5);
365EXTRACT_HELPER(crbA, 16, 5);
366EXTRACT_HELPER(crbB, 11, 5);
367/* SPR / TBL */
3fc6c082 368EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 369static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 370{
371 uint32_t sprn = _SPR(opcode);
372
373 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
374}
79aceca5
FB		 375/*** Get constants ***/
376EXTRACT_HELPER(IMM, 12, 8);
377/* 16 bits signed immediate value */
378EXTRACT_SHELPER(SIMM, 0, 16);
379/* 16 bits unsigned immediate value */
380EXTRACT_HELPER(UIMM, 0, 16);
21d21583
AJ		 381/* 5 bits signed immediate value */
382EXTRACT_HELPER(SIMM5, 16, 5);
27a4edb3
AJ		 383/* 5 bits signed immediate value */
384EXTRACT_HELPER(UIMM5, 16, 5);
79aceca5
FB		 385/* Bit count */
386EXTRACT_HELPER(NB, 11, 5);
387/* Shift count */
388EXTRACT_HELPER(SH, 11, 5);
cd633b10
AJ		 389/* Vector shift count */
390EXTRACT_HELPER(VSH, 6, 4);
79aceca5
FB		 391/* Mask start */
392EXTRACT_HELPER(MB, 6, 5);
393/* Mask end */
394EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 395/* Trap operand */
396EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 397
398EXTRACT_HELPER(CRM, 12, 8);
399EXTRACT_HELPER(FM, 17, 8);
400EXTRACT_HELPER(SR, 16, 4);
e4bb997e 401EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 402
79aceca5
FB		 403/*** Jump target decoding ***/
404/* Displacement */
405EXTRACT_SHELPER(d, 0, 16);
406/* Immediate address */
b068d6a7 407static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 408{
409 return (opcode >> 0) & 0x03FFFFFC;
410}
411
b068d6a7 412static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 413{
414 return (opcode >> 0) & 0xFFFC;
415}
416
417EXTRACT_HELPER(BO, 21, 5);
418EXTRACT_HELPER(BI, 16, 5);
419/* Absolute/relative address */
420EXTRACT_HELPER(AA, 1, 1);
421/* Link */
422EXTRACT_HELPER(LK, 0, 1);
423
424/* Create a mask between <start> and <end> bits */
b068d6a7 425static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 426{
76a66253 427 target_ulong ret;
79aceca5 428
76a66253
JM		 429#if defined(TARGET_PPC64)
430 if (likely(start == 0)) {
6f2d8978 431 ret = UINT64_MAX << (63 - end);
76a66253 432 } else if (likely(end == 63)) {
6f2d8978 433 ret = UINT64_MAX >> start;
76a66253
JM		 434 }
435#else
436 if (likely(start == 0)) {
6f2d8978 437 ret = UINT32_MAX << (31 - end);
76a66253 438 } else if (likely(end == 31)) {
6f2d8978 439 ret = UINT32_MAX >> start;
76a66253
JM		 440 }
441#endif
442 else {
443 ret = (((target_ulong)(-1ULL)) >> (start)) ^
444 (((target_ulong)(-1ULL) >> (end)) >> 1);
445 if (unlikely(start > end))
446 return ~ret;
447 }
79aceca5
FB		 448
449 return ret;
450}
451
a750fc0b
JM		 452/*****************************************************************************/
453/* PowerPC Instructions types definitions */
454enum {
1b413d55 455 PPC_NONE = 0x0000000000000000ULL,
12de9a39 456 /* PowerPC base instructions set */
1b413d55
JM		 457 PPC_INSNS_BASE = 0x0000000000000001ULL,
458 /* integer operations instructions */
a750fc0b 459#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 460 /* flow control instructions */
a750fc0b 461#define PPC_FLOW PPC_INSNS_BASE
1b413d55 462 /* virtual memory instructions */
a750fc0b 463#define PPC_MEM PPC_INSNS_BASE
1b413d55 464 /* ld/st with reservation instructions */
a750fc0b 465#define PPC_RES PPC_INSNS_BASE
1b413d55 466 /* spr/msr access instructions */
a750fc0b 467#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 468 /* Deprecated instruction sets */
469 /* Original POWER instruction set */
f610349f 470 PPC_POWER = 0x0000000000000002ULL,
1b413d55 471 /* POWER2 instruction set extension */
f610349f 472 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 473 /* Power RTC support */
f610349f 474 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 475 /* Power-to-PowerPC bridge (601) */
f610349f 476 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 477 /* 64 bits PowerPC instruction set */
f610349f 478 PPC_64B = 0x0000000000000020ULL,
1b413d55 479 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 480 PPC_64BX = 0x0000000000000040ULL,
1b413d55 481 /* 64 bits hypervisor extensions */
f610349f 482 PPC_64H = 0x0000000000000080ULL,
1b413d55 483 /* New wait instruction (PowerPC 2.0x) */
f610349f 484 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 485 /* Time base mftb instruction */
f610349f 486 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 487
488 /* Fixed-point unit extensions */
489 /* PowerPC 602 specific */
f610349f 490 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 491 /* isel instruction */
492 PPC_ISEL = 0x0000000000000800ULL,
493 /* popcntb instruction */
494 PPC_POPCNTB = 0x0000000000001000ULL,
495 /* string load / store */
496 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 497
498 /* Floating-point unit extensions */
499 /* Optional floating point instructions */
500 PPC_FLOAT = 0x0000000000010000ULL,
501 /* New floating-point extensions (PowerPC 2.0x) */
502 PPC_FLOAT_EXT = 0x0000000000020000ULL,
503 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
504 PPC_FLOAT_FRES = 0x0000000000080000ULL,
505 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
506 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
507 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
508 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
509
510 /* Vector/SIMD extensions */
511 /* Altivec support */
512 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 513 /* PowerPC 2.03 SPE extension */
05332d70 514 PPC_SPE = 0x0000000002000000ULL,
40569b7e
AJ		 515 /* PowerPC 2.03 SPE single-precision floating-point extension */
516 PPC_SPE_SINGLE = 0x0000000004000000ULL,
517 /* PowerPC 2.03 SPE double-precision floating-point extension */
518 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1b413d55 519
12de9a39 520 /* Optional memory control instructions */
1b413d55
JM		 521 PPC_MEM_TLBIA = 0x0000000010000000ULL,
522 PPC_MEM_TLBIE = 0x0000000020000000ULL,
523 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
524 /* sync instruction */
525 PPC_MEM_SYNC = 0x0000000080000000ULL,
526 /* eieio instruction */
527 PPC_MEM_EIEIO = 0x0000000100000000ULL,
528
529 /* Cache control instructions */
c8623f2e 530 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 531 /* icbi instruction */
05332d70 532 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 533 /* dcbz instruction with fixed cache line size */
05332d70 534 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 535 /* dcbz instruction with tunable cache line size */
05332d70 536 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 537 /* dcba instruction */
05332d70
JM		 538 PPC_CACHE_DCBA = 0x0000002000000000ULL,
539 /* Freescale cache locking instructions */
540 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 541
542 /* MMU related extensions */
543 /* external control instructions */
05332d70 544 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 545 /* segment register access instructions */
05332d70 546 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 547 /* PowerPC 6xx TLB management instructions */
05332d70 548 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 549 /* PowerPC 74xx TLB management instructions */
05332d70 550 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 551 /* PowerPC 40x TLB management instructions */
05332d70 552 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 553 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 554 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 555 /* SLB management */
05332d70 556 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 557
12de9a39 558 /* Embedded PowerPC dedicated instructions */
05332d70 559 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 560 /* PowerPC 40x exception model */
05332d70 561 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 562 /* PowerPC 405 Mac instructions */
05332d70 563 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 564 /* PowerPC 440 specific instructions */
05332d70 565 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 566 /* BookE (embedded) PowerPC specification */
05332d70
JM		 567 PPC_BOOKE = 0x0010000000000000ULL,
568 /* mfapidi instruction */
569 PPC_MFAPIDI = 0x0020000000000000ULL,
570 /* tlbiva instruction */
571 PPC_TLBIVA = 0x0040000000000000ULL,
572 /* tlbivax instruction */
573 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 574 /* PowerPC 4xx dedicated instructions */
05332d70 575 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 576 /* PowerPC 40x ibct instructions */
05332d70 577 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 578 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 579 PPC_RFMCI = 0x0400000000000000ULL,
580 /* rfdi instruction */
581 PPC_RFDI = 0x0800000000000000ULL,
582 /* DCR accesses */
583 PPC_DCR = 0x1000000000000000ULL,
584 /* DCR extended accesse */
585 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 586 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 587 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 588};
589
590/*****************************************************************************/
591/* PowerPC instructions table */
3fc6c082
FB		 592#if HOST_LONG_BITS == 64
593#define OPC_ALIGN 8
594#else
595#define OPC_ALIGN 4
596#endif
1b039c09 597#if defined(__APPLE__)
d9bce9d9 598#define OPCODES_SECTION \
3fc6c082 599 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 600#else
d9bce9d9 601#define OPCODES_SECTION \
3fc6c082 602 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 603#endif
604
76a66253 605#if defined(DO_PPC_STATISTICS)
79aceca5 606#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
50773fd2 607extern opcode_t opc_##name; \
18fba28c 608OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 609 .opc1 = op1, \
610 .opc2 = op2, \
611 .opc3 = op3, \
18fba28c 612 .pad = { 0, }, \
79aceca5
FB		 613 .handler = { \
614 .inval = invl, \
9a64fbe4 615 .type = _typ, \
79aceca5 616 .handler = &gen_##name, \
76a66253 617 .oname = stringify(name), \
79aceca5 618 }, \
3fc6c082 619 .oname = stringify(name), \
79aceca5 620}
c7697e1f
JM		 621#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
622OPCODES_SECTION opcode_t opc_##name = { \
623 .opc1 = op1, \
624 .opc2 = op2, \
625 .opc3 = op3, \
626 .pad = { 0, }, \
627 .handler = { \
628 .inval = invl, \
629 .type = _typ, \
630 .handler = &gen_##name, \
631 .oname = onam, \
632 }, \
633 .oname = onam, \
634}
76a66253
JM		 635#else
636#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
50773fd2 637extern opcode_t opc_##name; \
76a66253
JM		 638OPCODES_SECTION opcode_t opc_##name = { \
639 .opc1 = op1, \
640 .opc2 = op2, \
641 .opc3 = op3, \
642 .pad = { 0, }, \
643 .handler = { \
644 .inval = invl, \
645 .type = _typ, \
646 .handler = &gen_##name, \
647 }, \
648 .oname = stringify(name), \
649}
c7697e1f 650#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
50773fd2 651extern opcode_t opc_##name; \
c7697e1f
JM		 652OPCODES_SECTION opcode_t opc_##name = { \
653 .opc1 = op1, \
654 .opc2 = op2, \
655 .opc3 = op3, \
656 .pad = { 0, }, \
657 .handler = { \
658 .inval = invl, \
659 .type = _typ, \
660 .handler = &gen_##name, \
661 }, \
662 .oname = onam, \
663}
76a66253 664#endif
79aceca5
FB		 665
666#define GEN_OPCODE_MARK(name) \
50773fd2 667extern opcode_t opc_##name; \
18fba28c 668OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 669 .opc1 = 0xFF, \
670 .opc2 = 0xFF, \
671 .opc3 = 0xFF, \
18fba28c 672 .pad = { 0, }, \
79aceca5
FB		 673 .handler = { \
674 .inval = 0x00000000, \
9a64fbe4 675 .type = 0x00, \
79aceca5
FB		 676 .handler = NULL, \
677 }, \
3fc6c082 678 .oname = stringify(name), \
79aceca5
FB		 679}
680
54cdcae6
AJ		 681/* SPR load/store helpers */
682static always_inline void gen_load_spr(TCGv t, int reg)
683{
684 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
685}
686
687static always_inline void gen_store_spr(int reg, TCGv t)
688{
689 tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
690}
691
79aceca5
FB		 692/* Start opcode list */
693GEN_OPCODE_MARK(start);
694
695/* Invalid instruction */
9a64fbe4
FB		 696GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
697{
e06fcd75 698 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
9a64fbe4
FB		 699}
700
79aceca5
FB		 701static opc_handler_t invalid_handler = {
702 .inval = 0xFFFFFFFF,
9a64fbe4 703 .type = PPC_NONE,
79aceca5
FB		 704 .handler = gen_invalid,
705};
706
e1571908
AJ		 707/*** Integer comparison ***/
708
ea363694 709static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 710{
711 int l1, l2, l3;
712
269f3e95
AJ		 713 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
714 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 715 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
716
717 l1 = gen_new_label();
718 l2 = gen_new_label();
719 l3 = gen_new_label();
720 if (s) {
ea363694
AJ		 721 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 723 } else {
ea363694
AJ		 724 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
725 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 726 }
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
728 tcg_gen_br(l3);
729 gen_set_label(l1);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
731 tcg_gen_br(l3);
732 gen_set_label(l2);
733 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
734 gen_set_label(l3);
735}
736
ea363694 737static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 738{
ea363694
AJ		 739 TCGv t0 = tcg_const_local_tl(arg1);
740 gen_op_cmp(arg0, t0, s, crf);
741 tcg_temp_free(t0);
e1571908
AJ		 742}
743
744#if defined(TARGET_PPC64)
ea363694 745static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 746{
ea363694 747 TCGv t0, t1;
a7812ae4
PB		 748 t0 = tcg_temp_local_new();
749 t1 = tcg_temp_local_new();
e1571908 750 if (s) {
ea363694
AJ		 751 tcg_gen_ext32s_tl(t0, arg0);
752 tcg_gen_ext32s_tl(t1, arg1);
e1571908 753 } else {
ea363694
AJ		 754 tcg_gen_ext32u_tl(t0, arg0);
755 tcg_gen_ext32u_tl(t1, arg1);
e1571908 756 }
ea363694
AJ		 757 gen_op_cmp(t0, t1, s, crf);
758 tcg_temp_free(t1);
759 tcg_temp_free(t0);
e1571908
AJ		 760}
761
ea363694 762static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 763{
ea363694
AJ		 764 TCGv t0 = tcg_const_local_tl(arg1);
765 gen_op_cmp32(arg0, t0, s, crf);
766 tcg_temp_free(t0);
e1571908
AJ		 767}
768#endif
769
770static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
771{
772#if defined(TARGET_PPC64)
773 if (!(ctx->sf_mode))
774 gen_op_cmpi32(reg, 0, 1, 0);
775 else
776#endif
777 gen_op_cmpi(reg, 0, 1, 0);
778}
779
780/* cmp */
781GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
782{
783#if defined(TARGET_PPC64)
784 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
785 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787 else
788#endif
789 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
790 1, crfD(ctx->opcode));
791}
792
793/* cmpi */
794GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
795{
796#if defined(TARGET_PPC64)
797 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
798 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800 else
801#endif
802 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
803 1, crfD(ctx->opcode));
804}
805
806/* cmpl */
807GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
808{
809#if defined(TARGET_PPC64)
810 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
811 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813 else
814#endif
815 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
816 0, crfD(ctx->opcode));
817}
818
819/* cmpli */
820GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
821{
822#if defined(TARGET_PPC64)
823 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
824 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826 else
827#endif
828 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
829 0, crfD(ctx->opcode));
830}
831
832/* isel (PowerPC 2.03 specification) */
833GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
834{
835 int l1, l2;
836 uint32_t bi = rC(ctx->opcode);
837 uint32_t mask;
a7812ae4 838 TCGv_i32 t0;
e1571908
AJ		 839
840 l1 = gen_new_label();
841 l2 = gen_new_label();
842
843 mask = 1 << (3 - (bi & 0x03));
a7812ae4 844 t0 = tcg_temp_new_i32();
fea0c503
AJ		 845 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
846 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 847 if (rA(ctx->opcode) == 0)
848 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
849 else
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
851 tcg_gen_br(l2);
852 gen_set_label(l1);
853 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
854 gen_set_label(l2);
a7812ae4 855 tcg_temp_free_i32(t0);
e1571908
AJ		 856}
857
79aceca5 858/*** Integer arithmetic ***/
79aceca5 859
74637406
AJ		 860static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
861{
862 int l1;
863 TCGv t0;
79aceca5 864
74637406
AJ		 865 l1 = gen_new_label();
866 /* Start with XER OV disabled, the most likely case */
867 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
a7812ae4 868 t0 = tcg_temp_local_new();
74637406
AJ		 869 tcg_gen_xor_tl(t0, arg0, arg1);
870#if defined(TARGET_PPC64)
871 if (!ctx->sf_mode)
872 tcg_gen_ext32s_tl(t0, t0);
873#endif
874 if (sub)
875 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
876 else
877 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
878 tcg_gen_xor_tl(t0, arg1, arg2);
879#if defined(TARGET_PPC64)
880 if (!ctx->sf_mode)
881 tcg_gen_ext32s_tl(t0, t0);
882#endif
883 if (sub)
884 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
885 else
886 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
887 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
888 gen_set_label(l1);
889 tcg_temp_free(t0);
79aceca5
FB		 890}
891
74637406
AJ		 892static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
893{
894 int l1 = gen_new_label();
d9bce9d9
JM		 895
896#if defined(TARGET_PPC64)
74637406
AJ		 897 if (!(ctx->sf_mode)) {
898 TCGv t0, t1;
a7812ae4
PB		 899 t0 = tcg_temp_new();
900 t1 = tcg_temp_new();
d9bce9d9 901
74637406
AJ		 902 tcg_gen_ext32u_tl(t0, arg1);
903 tcg_gen_ext32u_tl(t1, arg2);
904 if (sub) {
905 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
bdc4e053 906 } else {
74637406
AJ		 907 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
908 }
a9730017
AJ		 909 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
910 gen_set_label(l1);
911 tcg_temp_free(t0);
912 tcg_temp_free(t1);
74637406
AJ		 913 } else
914#endif
a9730017
AJ		 915 {
916 if (sub) {
917 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
918 } else {
919 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
920 }
921 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
922 gen_set_label(l1);
74637406 923 }
d9bce9d9
JM		 924}
925
74637406
AJ		 926/* Common add function */
927static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
928 int add_ca, int compute_ca, int compute_ov)
929{
930 TCGv t0, t1;
d9bce9d9 931
74637406 932 if ((!compute_ca && !compute_ov) ||
a7812ae4 933 (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406
AJ		 934 t0 = ret;
935 } else {
a7812ae4 936 t0 = tcg_temp_local_new();
74637406 937 }
79aceca5 938
74637406 939 if (add_ca) {
a7812ae4 940 t1 = tcg_temp_local_new();
74637406
AJ		 941 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
942 tcg_gen_shri_tl(t1, t1, XER_CA);
943 }
79aceca5 944
74637406
AJ		 945 if (compute_ca && compute_ov) {
946 /* Start with XER CA and OV disabled, the most likely case */
947 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
948 } else if (compute_ca) {
949 /* Start with XER CA disabled, the most likely case */
950 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
951 } else if (compute_ov) {
952 /* Start with XER OV disabled, the most likely case */
953 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
954 }
79aceca5 955
74637406
AJ		 956 tcg_gen_add_tl(t0, arg1, arg2);
957
958 if (compute_ca) {
959 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
960 }
961 if (add_ca) {
962 tcg_gen_add_tl(t0, t0, t1);
963 gen_op_arith_compute_ca(ctx, t0, t1, 0);
964 tcg_temp_free(t1);
965 }
966 if (compute_ov) {
967 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
968 }
969
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, t0);
972
a7812ae4 973 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 974 tcg_gen_mov_tl(ret, t0);
975 tcg_temp_free(t0);
976 }
39dd32ee 977}
74637406
AJ		 978/* Add functions with two operands */
979#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
980GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
981{ \
982 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 add_ca, compute_ca, compute_ov); \
985}
986/* Add functions with one operand and one immediate */
987#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
988 add_ca, compute_ca, compute_ov) \
989GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
990{ \
991 TCGv t0 = tcg_const_local_tl(const_val); \
992 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
993 cpu_gpr[rA(ctx->opcode)], t0, \
994 add_ca, compute_ca, compute_ov); \
995 tcg_temp_free(t0); \
996}
997
998/* add add. addo addo. */
999GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
1000GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
1001/* addc addc. addco addco. */
1002GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
1003GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
1004/* adde adde. addeo addeo. */
1005GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
1006GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
1007/* addme addme. addmeo addmeo. */
1008GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
1009GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1010/* addze addze. addzeo addzeo.*/
1011GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1012GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1013/* addi */
1014GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1015{
74637406
AJ		 1016 target_long simm = SIMM(ctx->opcode);
1017
1018 if (rA(ctx->opcode) == 0) {
1019 /* li case */
1020 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1021 } else {
1022 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1023 }
d9bce9d9 1024}
74637406
AJ		 1025/* addic addic.*/
1026static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1027 int compute_Rc0)
d9bce9d9 1028{
74637406
AJ		 1029 target_long simm = SIMM(ctx->opcode);
1030
1031 /* Start with XER CA and OV disabled, the most likely case */
1032 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1033
1034 if (likely(simm != 0)) {
a7812ae4 1035 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1036 tcg_gen_addi_tl(t0, arg1, simm);
1037 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1038 tcg_gen_mov_tl(ret, t0);
1039 tcg_temp_free(t0);
1040 } else {
1041 tcg_gen_mov_tl(ret, arg1);
1042 }
1043 if (compute_Rc0) {
1044 gen_set_Rc0(ctx, ret);
1045 }
d9bce9d9 1046}
74637406 1047GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1048{
74637406 1049 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1050}
74637406 1051GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1052{
74637406 1053 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1054}
74637406
AJ		 1055/* addis */
1056GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1057{
74637406
AJ		 1058 target_long simm = SIMM(ctx->opcode);
1059
1060 if (rA(ctx->opcode) == 0) {
1061 /* lis case */
1062 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1063 } else {
1064 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1065 }
d9bce9d9 1066}
74637406
AJ		 1067
1068static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1069 int sign, int compute_ov)
d9bce9d9 1070{
2ef1b120
AJ		 1071 int l1 = gen_new_label();
1072 int l2 = gen_new_label();
a7812ae4
PB		 1073 TCGv_i32 t0 = tcg_temp_local_new_i32();
1074 TCGv_i32 t1 = tcg_temp_local_new_i32();
74637406 1075
2ef1b120
AJ		 1076 tcg_gen_trunc_tl_i32(t0, arg1);
1077 tcg_gen_trunc_tl_i32(t1, arg2);
1078 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
74637406 1079 if (sign) {
2ef1b120
AJ		 1080 int l3 = gen_new_label();
1081 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
1082 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
74637406 1083 gen_set_label(l3);
2ef1b120 1084 tcg_gen_div_i32(t0, t0, t1);
74637406 1085 } else {
2ef1b120 1086 tcg_gen_divu_i32(t0, t0, t1);
74637406
AJ		 1087 }
1088 if (compute_ov) {
1089 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1090 }
1091 tcg_gen_br(l2);
1092 gen_set_label(l1);
1093 if (sign) {
2ef1b120 1094 tcg_gen_sari_i32(t0, t0, 31);
74637406
AJ		 1095 } else {
1096 tcg_gen_movi_i32(t0, 0);
1097 }
1098 if (compute_ov) {
1099 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1100 }
1101 gen_set_label(l2);
2ef1b120 1102 tcg_gen_extu_i32_tl(ret, t0);
a7812ae4
PB		 1103 tcg_temp_free_i32(t0);
1104 tcg_temp_free_i32(t1);
74637406
AJ		 1105 if (unlikely(Rc(ctx->opcode) != 0))
1106 gen_set_Rc0(ctx, ret);
d9bce9d9 1107}
74637406
AJ		 1108/* Div functions */
1109#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1110GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1111{ \
1112 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1113 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1114 sign, compute_ov); \
1115}
1116/* divwu divwu. divwuo divwuo. */
1117GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1118GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1119/* divw divw. divwo divwo. */
1120GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1121GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1122#if defined(TARGET_PPC64)
2ef1b120
AJ		 1123static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1124 int sign, int compute_ov)
d9bce9d9 1125{
2ef1b120
AJ		 1126 int l1 = gen_new_label();
1127 int l2 = gen_new_label();
74637406
AJ		 1128
1129 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1130 if (sign) {
2ef1b120 1131 int l3 = gen_new_label();
74637406
AJ		 1132 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1133 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1134 gen_set_label(l3);
74637406
AJ		 1135 tcg_gen_div_i64(ret, arg1, arg2);
1136 } else {
1137 tcg_gen_divu_i64(ret, arg1, arg2);
1138 }
1139 if (compute_ov) {
1140 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1141 }
1142 tcg_gen_br(l2);
1143 gen_set_label(l1);
1144 if (sign) {
1145 tcg_gen_sari_i64(ret, arg1, 63);
1146 } else {
1147 tcg_gen_movi_i64(ret, 0);
1148 }
1149 if (compute_ov) {
1150 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1151 }
1152 gen_set_label(l2);
1153 if (unlikely(Rc(ctx->opcode) != 0))
1154 gen_set_Rc0(ctx, ret);
d9bce9d9 1155}
74637406
AJ		 1156#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1157GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1158{ \
2ef1b120
AJ		 1159 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1160 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1161 sign, compute_ov); \
74637406
AJ		 1162}
1163/* divwu divwu. divwuo divwuo. */
1164GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1165GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1166/* divw divw. divwo divwo. */
1167GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1168GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1169#endif
74637406
AJ		 1170
1171/* mulhw mulhw. */
1172GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1173{
a7812ae4 1174 TCGv_i64 t0, t1;
74637406 1175
a7812ae4
PB		 1176 t0 = tcg_temp_new_i64();
1177 t1 = tcg_temp_new_i64();
74637406
AJ		 1178#if defined(TARGET_PPC64)
1179 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1180 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1181 tcg_gen_mul_i64(t0, t0, t1);
1182 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1183#else
1184 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1185 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1186 tcg_gen_mul_i64(t0, t0, t1);
1187 tcg_gen_shri_i64(t0, t0, 32);
1188 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1189#endif
a7812ae4
PB		 1190 tcg_temp_free_i64(t0);
1191 tcg_temp_free_i64(t1);
74637406
AJ		 1192 if (unlikely(Rc(ctx->opcode) != 0))
1193 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1194}
74637406
AJ		 1195/* mulhwu mulhwu. */
1196GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1197{
a7812ae4 1198 TCGv_i64 t0, t1;
74637406 1199
a7812ae4
PB		 1200 t0 = tcg_temp_new_i64();
1201 t1 = tcg_temp_new_i64();
d9bce9d9 1202#if defined(TARGET_PPC64)
74637406
AJ		 1203 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1204 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1205 tcg_gen_mul_i64(t0, t0, t1);
1206 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1207#else
1208 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1209 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1210 tcg_gen_mul_i64(t0, t0, t1);
1211 tcg_gen_shri_i64(t0, t0, 32);
1212 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1213#endif
a7812ae4
PB		 1214 tcg_temp_free_i64(t0);
1215 tcg_temp_free_i64(t1);
74637406
AJ		 1216 if (unlikely(Rc(ctx->opcode) != 0))
1217 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1218}
74637406
AJ		 1219/* mullw mullw. */
1220GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1221{
74637406
AJ		 1222 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1223 cpu_gpr[rB(ctx->opcode)]);
1e4c090f 1224 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
74637406
AJ		 1225 if (unlikely(Rc(ctx->opcode) != 0))
1226 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1227}
74637406
AJ		 1228/* mullwo mullwo. */
1229GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1230{
74637406 1231 int l1;
a7812ae4 1232 TCGv_i64 t0, t1;
74637406 1233
a7812ae4
PB		 1234 t0 = tcg_temp_new_i64();
1235 t1 = tcg_temp_new_i64();
74637406
AJ		 1236 l1 = gen_new_label();
1237 /* Start with XER OV disabled, the most likely case */
1238 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1239#if defined(TARGET_PPC64)
1240 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1241 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1242#else
1243 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1244 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1245#endif
74637406
AJ		 1246 tcg_gen_mul_i64(t0, t0, t1);
1247#if defined(TARGET_PPC64)
1248 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1249 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1250#else
1251 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1252 tcg_gen_ext32s_i64(t1, t0);
1253 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1254#endif
1255 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1256 gen_set_label(l1);
a7812ae4
PB		 1257 tcg_temp_free_i64(t0);
1258 tcg_temp_free_i64(t1);
74637406
AJ		 1259 if (unlikely(Rc(ctx->opcode) != 0))
1260 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1261}
74637406
AJ		 1262/* mulli */
1263GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1264{
74637406
AJ		 1265 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1266 SIMM(ctx->opcode));
d9bce9d9
JM		 1267}
1268#if defined(TARGET_PPC64)
74637406
AJ		 1269#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1270GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1271{ \
a7812ae4 1272 gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \
74637406
AJ		 1273 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1274 if (unlikely(Rc(ctx->opcode) != 0)) \
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1276}
74637406
AJ		 1277/* mulhd mulhd. */
1278GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1279/* mulhdu mulhdu. */
1280GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1281/* mulld mulld. */
1282GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1283{
74637406
AJ		 1284 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1285 cpu_gpr[rB(ctx->opcode)]);
1286 if (unlikely(Rc(ctx->opcode) != 0))
1287 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1288}
74637406
AJ		 1289/* mulldo mulldo. */
1290GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1291#endif
74637406
AJ		 1292
1293/* neg neg. nego nego. */
ec6469a3 1294static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1295{
ec6469a3
AJ		 1296 int l1 = gen_new_label();
1297 int l2 = gen_new_label();
a7812ae4 1298 TCGv t0 = tcg_temp_local_new();
d9bce9d9 1299#if defined(TARGET_PPC64)
74637406 1300 if (ctx->sf_mode) {
741a7444 1301 tcg_gen_mov_tl(t0, arg1);
ec6469a3
AJ		 1302 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
1303 } else
1304#endif
1305 {
1306 tcg_gen_ext32s_tl(t0, arg1);
74637406
AJ		 1307 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1308 }
74637406
AJ		 1309 tcg_gen_neg_tl(ret, arg1);
1310 if (ov_check) {
1311 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1312 }
1313 tcg_gen_br(l2);
1314 gen_set_label(l1);
ec6469a3 1315 tcg_gen_mov_tl(ret, t0);
74637406
AJ		 1316 if (ov_check) {
1317 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1318 }
1319 gen_set_label(l2);
ec6469a3 1320 tcg_temp_free(t0);
74637406
AJ		 1321 if (unlikely(Rc(ctx->opcode) != 0))
1322 gen_set_Rc0(ctx, ret);
1323}
1324GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1325{
ec6469a3 1326 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1327}
74637406 1328GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1329{
ec6469a3 1330 gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1331}
74637406
AJ		 1332
1333/* Common subf function */
1334static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1335 int add_ca, int compute_ca, int compute_ov)
79aceca5 1336{
74637406 1337 TCGv t0, t1;
76a66253 1338
74637406 1339 if ((!compute_ca && !compute_ov) ||
a7812ae4 1340 (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) {
74637406 1341 t0 = ret;
e864cabd 1342 } else {
a7812ae4 1343 t0 = tcg_temp_local_new();
d9bce9d9 1344 }
76a66253 1345
74637406 1346 if (add_ca) {
a7812ae4 1347 t1 = tcg_temp_local_new();
74637406
AJ		 1348 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1349 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1350 }
79aceca5 1351
74637406
AJ		 1352 if (compute_ca && compute_ov) {
1353 /* Start with XER CA and OV disabled, the most likely case */
1354 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1355 } else if (compute_ca) {
1356 /* Start with XER CA disabled, the most likely case */
1357 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1358 } else if (compute_ov) {
1359 /* Start with XER OV disabled, the most likely case */
1360 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1361 }
1362
1363 if (add_ca) {
1364 tcg_gen_not_tl(t0, arg1);
1365 tcg_gen_add_tl(t0, t0, arg2);
1366 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1367 tcg_gen_add_tl(t0, t0, t1);
1368 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1369 tcg_temp_free(t1);
79aceca5 1370 } else {
74637406
AJ		 1371 tcg_gen_sub_tl(t0, arg2, arg1);
1372 if (compute_ca) {
1373 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1374 }
1375 }
1376 if (compute_ov) {
1377 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1378 }
1379
1380 if (unlikely(Rc(ctx->opcode) != 0))
1381 gen_set_Rc0(ctx, t0);
1382
a7812ae4 1383 if (!TCGV_EQUAL(t0, ret)) {
74637406
AJ		 1384 tcg_gen_mov_tl(ret, t0);
1385 tcg_temp_free(t0);
79aceca5 1386 }
79aceca5 1387}
74637406
AJ		 1388/* Sub functions with Two operands functions */
1389#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1390GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1391{ \
1392 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1393 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1394 add_ca, compute_ca, compute_ov); \
1395}
1396/* Sub functions with one operand and one immediate */
1397#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1398 add_ca, compute_ca, compute_ov) \
1399GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1400{ \
1401 TCGv t0 = tcg_const_local_tl(const_val); \
1402 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1403 cpu_gpr[rA(ctx->opcode)], t0, \
1404 add_ca, compute_ca, compute_ov); \
1405 tcg_temp_free(t0); \
1406}
1407/* subf subf. subfo subfo. */
1408GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1409GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1410/* subfc subfc. subfco subfco. */
1411GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1412GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1413/* subfe subfe. subfeo subfo. */
1414GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1415GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1416/* subfme subfme. subfmeo subfmeo. */
1417GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1418GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1419/* subfze subfze. subfzeo subfzeo.*/
1420GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1421GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1422/* subfic */
1423GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1424{
74637406
AJ		 1425 /* Start with XER CA and OV disabled, the most likely case */
1426 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
a7812ae4 1427 TCGv t0 = tcg_temp_local_new();
74637406
AJ		 1428 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1429 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1430 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1431 tcg_temp_free(t1);
1432 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1433 tcg_temp_free(t0);
79aceca5
FB		 1434}
1435
79aceca5 1436/*** Integer logical ***/
26d67362
AJ		 1437#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1438GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1439{ \
26d67362
AJ		 1440 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1441 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1442 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1443 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1444}
79aceca5 1445
26d67362 1446#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1447GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1448{ \
26d67362 1449 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1450 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1451 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1452}
1453
1454/* and & and. */
26d67362 1455GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1456/* andc & andc. */
26d67362 1457GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1458/* andi. */
c7697e1f 1459GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1460{
26d67362
AJ		 1461 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1462 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1463}
1464/* andis. */
c7697e1f 1465GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1466{
26d67362
AJ		 1467 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1469}
79aceca5 1470/* cntlzw */
26d67362
AJ		 1471GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1472{
a7812ae4 1473 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362 1474 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1475 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1476}
79aceca5 1477/* eqv & eqv. */
26d67362 1478GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1479/* extsb & extsb. */
26d67362 1480GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1481/* extsh & extsh. */
26d67362 1482GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1483/* nand & nand. */
26d67362 1484GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1485/* nor & nor. */
26d67362 1486GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1487/* or & or. */
9a64fbe4
FB		 1488GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1489{
76a66253
JM		 1490 int rs, ra, rb;
1491
1492 rs = rS(ctx->opcode);
1493 ra = rA(ctx->opcode);
1494 rb = rB(ctx->opcode);
1495 /* Optimisation for mr. ri case */
1496 if (rs != ra || rs != rb) {
26d67362
AJ		 1497 if (rs != rb)
1498 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1499 else
1500 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1501 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1502 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1503 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1504 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1505#if defined(TARGET_PPC64)
1506 } else {
26d67362
AJ		 1507 int prio = 0;
1508
c80f84e3
JM		 1509 switch (rs) {
1510 case 1:
1511 /* Set process priority to low */
26d67362 1512 prio = 2;
c80f84e3
JM		 1513 break;
1514 case 6:
1515 /* Set process priority to medium-low */
26d67362 1516 prio = 3;
c80f84e3
JM		 1517 break;
1518 case 2:
1519 /* Set process priority to normal */
26d67362 1520 prio = 4;
c80f84e3 1521 break;
be147d08
JM		 1522#if !defined(CONFIG_USER_ONLY)
1523 case 31:
76db3ba4 1524 if (ctx->mem_idx > 0) {
be147d08 1525 /* Set process priority to very low */
26d67362 1526 prio = 1;
be147d08
JM		 1527 }
1528 break;
1529 case 5:
76db3ba4 1530 if (ctx->mem_idx > 0) {
be147d08 1531 /* Set process priority to medium-hight */
26d67362 1532 prio = 5;
be147d08
JM		 1533 }
1534 break;
1535 case 3:
76db3ba4 1536 if (ctx->mem_idx > 0) {
be147d08 1537 /* Set process priority to high */
26d67362 1538 prio = 6;
be147d08
JM		 1539 }
1540 break;
be147d08 1541 case 7:
76db3ba4 1542 if (ctx->mem_idx > 1) {
be147d08 1543 /* Set process priority to very high */
26d67362 1544 prio = 7;
be147d08
JM		 1545 }
1546 break;
be147d08 1547#endif
c80f84e3
JM		 1548 default:
1549 /* nop */
1550 break;
1551 }
26d67362 1552 if (prio) {
a7812ae4 1553 TCGv t0 = tcg_temp_new();
54cdcae6 1554 gen_load_spr(t0, SPR_PPR);
ea363694
AJ		 1555 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1556 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
54cdcae6 1557 gen_store_spr(SPR_PPR, t0);
ea363694 1558 tcg_temp_free(t0);
26d67362 1559 }
c80f84e3 1560#endif
9a64fbe4 1561 }
9a64fbe4 1562}
79aceca5 1563/* orc & orc. */
26d67362 1564GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1565/* xor & xor. */
9a64fbe4
FB		 1566GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1567{
9a64fbe4 1568 /* Optimisation for "set to zero" case */
26d67362 1569 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1570 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1571 else
1572 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1573 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1574 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1575}
79aceca5
FB		 1576/* ori */
1577GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1578{
76a66253 1579 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1580
9a64fbe4
FB		 1581 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1582 /* NOP */
76a66253 1583 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1584 return;
76a66253 1585 }
26d67362 1586 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1587}
1588/* oris */
1589GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1590{
76a66253 1591 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1592
9a64fbe4
FB		 1593 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1594 /* NOP */
1595 return;
76a66253 1596 }
26d67362 1597 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1598}
1599/* xori */
1600GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1601{
76a66253 1602 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1603
1604 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1605 /* NOP */
1606 return;
1607 }
26d67362 1608 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1609}
79aceca5
FB		 1610/* xoris */
1611GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1612{
76a66253 1613 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1614
1615 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1616 /* NOP */
1617 return;
1618 }
26d67362 1619 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1620}
d9bce9d9 1621/* popcntb : PowerPC 2.03 specification */
05332d70 1622GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1623{
d9bce9d9
JM		 1624#if defined(TARGET_PPC64)
1625 if (ctx->sf_mode)
a7812ae4 1626 gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1627 else
1628#endif
a7812ae4 1629 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1630}
1631
1632#if defined(TARGET_PPC64)
1633/* extsw & extsw. */
26d67362 1634GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1635/* cntlzd */
26d67362
AJ		 1636GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1637{
a7812ae4 1638 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
26d67362
AJ		 1639 if (unlikely(Rc(ctx->opcode) != 0))
1640 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1641}
d9bce9d9
JM		 1642#endif
1643
79aceca5
FB		 1644/*** Integer rotate ***/
1645/* rlwimi & rlwimi. */
1646GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1647{
76a66253 1648 uint32_t mb, me, sh;
79aceca5
FB		 1649
1650 mb = MB(ctx->opcode);
1651 me = ME(ctx->opcode);
76a66253 1652 sh = SH(ctx->opcode);
d03ef511
AJ		 1653 if (likely(sh == 0 && mb == 0 && me == 31)) {
1654 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1655 } else {
d03ef511 1656 target_ulong mask;
a7812ae4
PB		 1657 TCGv t1;
1658 TCGv t0 = tcg_temp_new();
54843a58 1659#if defined(TARGET_PPC64)
a7812ae4
PB		 1660 TCGv_i32 t2 = tcg_temp_new_i32();
1661 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1662 tcg_gen_rotli_i32(t2, t2, sh);
1663 tcg_gen_extu_i32_i64(t0, t2);
1664 tcg_temp_free_i32(t2);
54843a58
AJ		 1665#else
1666 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1667#endif
76a66253 1668#if defined(TARGET_PPC64)
d03ef511
AJ		 1669 mb += 32;
1670 me += 32;
76a66253 1671#endif
d03ef511 1672 mask = MASK(mb, me);
a7812ae4 1673 t1 = tcg_temp_new();
d03ef511
AJ		 1674 tcg_gen_andi_tl(t0, t0, mask);
1675 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1676 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1677 tcg_temp_free(t0);
1678 tcg_temp_free(t1);
1679 }
76a66253 1680 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1681 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1682}
1683/* rlwinm & rlwinm. */
1684GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1685{
1686 uint32_t mb, me, sh;
3b46e624 1687
79aceca5
FB		 1688 sh = SH(ctx->opcode);
1689 mb = MB(ctx->opcode);
1690 me = ME(ctx->opcode);
d03ef511
AJ		 1691
1692 if (likely(mb == 0 && me == (31 - sh))) {
1693 if (likely(sh == 0)) {
1694 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1695 } else {
a7812ae4 1696 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1697 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1698 tcg_gen_shli_tl(t0, t0, sh);
1699 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1700 tcg_temp_free(t0);
79aceca5 1701 }
d03ef511 1702 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
a7812ae4 1703 TCGv t0 = tcg_temp_new();
d03ef511
AJ		 1704 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1705 tcg_gen_shri_tl(t0, t0, mb);
1706 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1707 tcg_temp_free(t0);
1708 } else {
a7812ae4 1709 TCGv t0 = tcg_temp_new();
54843a58 1710#if defined(TARGET_PPC64)
a7812ae4 1711 TCGv_i32 t1 = tcg_temp_new_i32();
54843a58
AJ		 1712 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1713 tcg_gen_rotli_i32(t1, t1, sh);
1714 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4 1715 tcg_temp_free_i32(t1);
54843a58
AJ		 1716#else
1717 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1718#endif
76a66253 1719#if defined(TARGET_PPC64)
d03ef511
AJ		 1720 mb += 32;
1721 me += 32;
76a66253 1722#endif
d03ef511
AJ		 1723 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1724 tcg_temp_free(t0);
1725 }
76a66253 1726 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1727 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1728}
1729/* rlwnm & rlwnm. */
1730GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1731{
1732 uint32_t mb, me;
54843a58
AJ		 1733 TCGv t0;
1734#if defined(TARGET_PPC64)
a7812ae4 1735 TCGv_i32 t1, t2;
54843a58 1736#endif
79aceca5
FB		 1737
1738 mb = MB(ctx->opcode);
1739 me = ME(ctx->opcode);
a7812ae4 1740 t0 = tcg_temp_new();
d03ef511 1741 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
54843a58 1742#if defined(TARGET_PPC64)
a7812ae4
PB		 1743 t1 = tcg_temp_new_i32();
1744 t2 = tcg_temp_new_i32();
54843a58
AJ		 1745 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1746 tcg_gen_trunc_i64_i32(t2, t0);
1747 tcg_gen_rotl_i32(t1, t1, t2);
1748 tcg_gen_extu_i32_i64(t0, t1);
a7812ae4
PB		 1749 tcg_temp_free_i32(t1);
1750 tcg_temp_free_i32(t2);
54843a58
AJ		 1751#else
1752 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1753#endif
76a66253
JM		 1754 if (unlikely(mb != 0 || me != 31)) {
1755#if defined(TARGET_PPC64)
1756 mb += 32;
1757 me += 32;
1758#endif
54843a58 1759 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
d03ef511 1760 } else {
54843a58 1761 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
79aceca5 1762 }
54843a58 1763 tcg_temp_free(t0);
76a66253 1764 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1765 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1766}
1767
d9bce9d9
JM		 1768#if defined(TARGET_PPC64)
1769#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1770GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1771{ \
1772 gen_##name(ctx, 0); \
1773} \
c7697e1f
JM		 1774GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1775 PPC_64B) \
d9bce9d9
JM		 1776{ \
1777 gen_##name(ctx, 1); \
1778}
1779#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1780GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1781{ \
1782 gen_##name(ctx, 0, 0); \
1783} \
c7697e1f
JM		 1784GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1785 PPC_64B) \
d9bce9d9
JM		 1786{ \
1787 gen_##name(ctx, 0, 1); \
1788} \
c7697e1f
JM		 1789GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1790 PPC_64B) \
d9bce9d9
JM		 1791{ \
1792 gen_##name(ctx, 1, 0); \
1793} \
c7697e1f
JM		 1794GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1795 PPC_64B) \
d9bce9d9
JM		 1796{ \
1797 gen_##name(ctx, 1, 1); \
1798}
51789c41 1799
b068d6a7
JM		 1800static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1801 uint32_t me, uint32_t sh)
51789c41 1802{
d03ef511
AJ		 1803 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1804 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1805 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1806 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1807 } else {
a7812ae4 1808 TCGv t0 = tcg_temp_new();
54843a58 1809 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
d03ef511 1810 if (likely(mb == 0 && me == 63)) {
54843a58 1811 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
d03ef511
AJ		 1812 } else {
1813 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1814 }
d03ef511 1815 tcg_temp_free(t0);
51789c41 1816 }
51789c41 1817 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1818 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1819}
d9bce9d9 1820/* rldicl - rldicl. */
b068d6a7 1821static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1822{
51789c41 1823 uint32_t sh, mb;
d9bce9d9 1824
9d53c753
JM		 1825 sh = SH(ctx->opcode) | (shn << 5);
1826 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1827 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1828}
51789c41 1829GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1830/* rldicr - rldicr. */
b068d6a7 1831static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1832{
51789c41 1833 uint32_t sh, me;
d9bce9d9 1834
9d53c753
JM		 1835 sh = SH(ctx->opcode) | (shn << 5);
1836 me = MB(ctx->opcode) | (men << 5);
51789c41 1837 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1838}
51789c41 1839GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1840/* rldic - rldic. */
b068d6a7 1841static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1842{
51789c41 1843 uint32_t sh, mb;
d9bce9d9 1844
9d53c753
JM		 1845 sh = SH(ctx->opcode) | (shn << 5);
1846 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1847 gen_rldinm(ctx, mb, 63 - sh, sh);
1848}
1849GEN_PPC64_R4(rldic, 0x1E, 0x04);
1850
b068d6a7
JM		 1851static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1852 uint32_t me)
51789c41 1853{
54843a58 1854 TCGv t0;
d03ef511
AJ		 1855
1856 mb = MB(ctx->opcode);
1857 me = ME(ctx->opcode);
a7812ae4 1858 t0 = tcg_temp_new();
d03ef511 1859 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
54843a58 1860 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
51789c41 1861 if (unlikely(mb != 0 || me != 63)) {
54843a58
AJ		 1862 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1863 } else {
1864 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1865 }
1866 tcg_temp_free(t0);
51789c41 1867 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1868 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1869}
51789c41 1870
d9bce9d9 1871/* rldcl - rldcl. */
b068d6a7 1872static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1873{
51789c41 1874 uint32_t mb;
d9bce9d9 1875
9d53c753 1876 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1877 gen_rldnm(ctx, mb, 63);
d9bce9d9 1878}
36081602 1879GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1880/* rldcr - rldcr. */
b068d6a7 1881static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1882{
51789c41 1883 uint32_t me;
d9bce9d9 1884
9d53c753 1885 me = MB(ctx->opcode) | (men << 5);
51789c41 1886 gen_rldnm(ctx, 0, me);
d9bce9d9 1887}
36081602 1888GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1889/* rldimi - rldimi. */
b068d6a7 1890static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1891{
271a916e 1892 uint32_t sh, mb, me;
d9bce9d9 1893
9d53c753
JM		 1894 sh = SH(ctx->opcode) | (shn << 5);
1895 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1896 me = 63 - sh;
d03ef511
AJ		 1897 if (unlikely(sh == 0 && mb == 0)) {
1898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1899 } else {
1900 TCGv t0, t1;
1901 target_ulong mask;
1902
a7812ae4 1903 t0 = tcg_temp_new();
54843a58 1904 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
a7812ae4 1905 t1 = tcg_temp_new();
d03ef511
AJ		 1906 mask = MASK(mb, me);
1907 tcg_gen_andi_tl(t0, t0, mask);
1908 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1909 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1910 tcg_temp_free(t0);
1911 tcg_temp_free(t1);
51789c41 1912 }
51789c41 1913 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1914 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1915}
36081602 1916GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1917#endif
1918
79aceca5
FB		 1919/*** Integer shift ***/
1920/* slw & slw. */
26d67362
AJ		 1921GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1922{
fea0c503 1923 TCGv t0;
26d67362
AJ		 1924 int l1, l2;
1925 l1 = gen_new_label();
1926 l2 = gen_new_label();
1927
a7812ae4 1928 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1929 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1930 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1931 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1932 tcg_gen_br(l2);
1933 gen_set_label(l1);
fea0c503 1934 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1935 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1936 gen_set_label(l2);
fea0c503 1937 tcg_temp_free(t0);
26d67362
AJ		 1938 if (unlikely(Rc(ctx->opcode) != 0))
1939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1940}
79aceca5 1941/* sraw & sraw. */
26d67362
AJ		 1942GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1943{
a7812ae4
PB		 1944 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)],
1945 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1946 if (unlikely(Rc(ctx->opcode) != 0))
1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1948}
79aceca5
FB		 1949/* srawi & srawi. */
1950GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1951{
26d67362
AJ		 1952 int sh = SH(ctx->opcode);
1953 if (sh != 0) {
1954 int l1, l2;
fea0c503 1955 TCGv t0;
26d67362
AJ		 1956 l1 = gen_new_label();
1957 l2 = gen_new_label();
a7812ae4 1958 t0 = tcg_temp_local_new();
fea0c503
AJ		 1959 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1960 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1961 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1962 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1963 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1964 tcg_gen_br(l2);
1965 gen_set_label(l1);
269f3e95 1966 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 1967 gen_set_label(l2);
fea0c503
AJ		 1968 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1969 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
1970 tcg_temp_free(t0);
26d67362
AJ		 1971 } else {
1972 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 1973 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1974 }
76a66253 1975 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1976 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1977}
1978/* srw & srw. */
26d67362
AJ		 1979GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
1980{
fea0c503 1981 TCGv t0, t1;
26d67362
AJ		 1982 int l1, l2;
1983 l1 = gen_new_label();
1984 l2 = gen_new_label();
d9bce9d9 1985
a7812ae4 1986 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 1987 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1988 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1);
26d67362
AJ		 1989 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1990 tcg_gen_br(l2);
1991 gen_set_label(l1);
a7812ae4 1992 t1 = tcg_temp_new();
fea0c503
AJ		 1993 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1994 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
1995 tcg_temp_free(t1);
26d67362 1996 gen_set_label(l2);
fea0c503 1997 tcg_temp_free(t0);
26d67362
AJ		 1998 if (unlikely(Rc(ctx->opcode) != 0))
1999 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2000}
d9bce9d9
JM		 2001#if defined(TARGET_PPC64)
2002/* sld & sld. */
26d67362
AJ		 2003GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2004{
fea0c503 2005 TCGv t0;
26d67362
AJ		 2006 int l1, l2;
2007 l1 = gen_new_label();
2008 l2 = gen_new_label();
2009
a7812ae4 2010 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2011 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2012 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2013 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2014 tcg_gen_br(l2);
2015 gen_set_label(l1);
fea0c503 2016 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2017 gen_set_label(l2);
fea0c503 2018 tcg_temp_free(t0);
26d67362
AJ		 2019 if (unlikely(Rc(ctx->opcode) != 0))
2020 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2021}
d9bce9d9 2022/* srad & srad. */
26d67362
AJ		 2023GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2024{
a7812ae4
PB		 2025 gen_helper_srad(cpu_gpr[rA(ctx->opcode)],
2026 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 2027 if (unlikely(Rc(ctx->opcode) != 0))
2028 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2029}
d9bce9d9 2030/* sradi & sradi. */
b068d6a7 2031static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2032{
26d67362 2033 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2034 if (sh != 0) {
26d67362 2035 int l1, l2;
fea0c503 2036 TCGv t0;
26d67362
AJ		 2037 l1 = gen_new_label();
2038 l2 = gen_new_label();
a7812ae4 2039 t0 = tcg_temp_local_new();
26d67362 2040 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2041 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2042 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2043 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2044 tcg_gen_br(l2);
2045 gen_set_label(l1);
269f3e95 2046 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2047 gen_set_label(l2);
a9730017 2048 tcg_temp_free(t0);
26d67362
AJ		 2049 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2050 } else {
2051 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2052 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2053 }
d9bce9d9 2054 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2055 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2056}
c7697e1f 2057GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2058{
2059 gen_sradi(ctx, 0);
2060}
c7697e1f 2061GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2062{
2063 gen_sradi(ctx, 1);
2064}
2065/* srd & srd. */
26d67362
AJ		 2066GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2067{
fea0c503 2068 TCGv t0;
26d67362
AJ		 2069 int l1, l2;
2070 l1 = gen_new_label();
2071 l2 = gen_new_label();
2072
a7812ae4 2073 t0 = tcg_temp_local_new();
0cfe58cd
AJ		 2074 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2075 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1);
26d67362
AJ		 2076 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2077 tcg_gen_br(l2);
2078 gen_set_label(l1);
fea0c503 2079 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2080 gen_set_label(l2);
fea0c503 2081 tcg_temp_free(t0);
26d67362
AJ		 2082 if (unlikely(Rc(ctx->opcode) != 0))
2083 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2084}
d9bce9d9 2085#endif
79aceca5
FB		 2086
2087/*** Floating-Point arithmetic ***/
7c58044c 2088#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2089GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2090{ \
76a66253 2091 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2092 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2093 return; \
2094 } \
eb44b959
AJ		 2095 /* NIP cannot be restored if the memory exception comes from an helper */ \
2096 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2097 gen_reset_fpstatus(); \
af12906f
AJ		 2098 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2099 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2100 if (isfloat) { \
af12906f 2101 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2102 } \
af12906f
AJ		 2103 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2104 Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2105}
2106
7c58044c
JM		 2107#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2108_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2109_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2110
7c58044c
JM		 2111#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2112GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2113{ \
76a66253 2114 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2115 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2116 return; \
2117 } \
eb44b959
AJ		 2118 /* NIP cannot be restored if the memory exception comes from an helper */ \
2119 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2120 gen_reset_fpstatus(); \
af12906f
AJ		 2121 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2122 cpu_fpr[rB(ctx->opcode)]); \
4ecc3190 2123 if (isfloat) { \
af12906f 2124 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2125 } \
af12906f
AJ		 2126 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2127 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2128}
7c58044c
JM		 2129#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2130_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2131_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2132
7c58044c
JM		 2133#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2134GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2135{ \
76a66253 2136 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2137 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2138 return; \
2139 } \
eb44b959
AJ		 2140 /* NIP cannot be restored if the memory exception comes from an helper */ \
2141 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2142 gen_reset_fpstatus(); \
af12906f
AJ		 2143 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \
2144 cpu_fpr[rC(ctx->opcode)]); \
4ecc3190 2145 if (isfloat) { \
af12906f 2146 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \
4ecc3190 2147 } \
af12906f
AJ		 2148 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2149 set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2150}
7c58044c
JM		 2151#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2152_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2153_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2154
7c58044c 2155#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2156GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2157{ \
76a66253 2158 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2159 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2160 return; \
2161 } \
eb44b959
AJ		 2162 /* NIP cannot be restored if the memory exception comes from an helper */ \
2163 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2164 gen_reset_fpstatus(); \
af12906f
AJ		 2165 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2166 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2167 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2168}
2169
7c58044c 2170#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2171GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2172{ \
76a66253 2173 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 2174 gen_exception(ctx, POWERPC_EXCP_FPU); \
3cc62370
FB		 2175 return; \
2176 } \
eb44b959
AJ		 2177 /* NIP cannot be restored if the memory exception comes from an helper */ \
2178 gen_update_nip(ctx, ctx->nip - 4); \
7c58044c 2179 gen_reset_fpstatus(); \
af12906f
AJ		 2180 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2181 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2182 set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2183}
2184
9a64fbe4 2185/* fadd - fadds */
7c58044c 2186GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2187/* fdiv - fdivs */
7c58044c 2188GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2189/* fmul - fmuls */
7c58044c 2190GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2191
d7e4b87e 2192/* fre */
7c58044c 2193GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2194
a750fc0b 2195/* fres */
7c58044c 2196GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2197
a750fc0b 2198/* frsqrte */
7c58044c
JM		 2199GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2200
2201/* frsqrtes */
af12906f 2202GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES)
7c58044c 2203{
af12906f 2204 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2205 gen_exception(ctx, POWERPC_EXCP_FPU);
af12906f
AJ		 2206 return;
2207 }
eb44b959
AJ		 2208 /* NIP cannot be restored if the memory exception comes from an helper */
2209 gen_update_nip(ctx, ctx->nip - 4);
af12906f
AJ		 2210 gen_reset_fpstatus();
2211 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2212 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2213 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
7c58044c 2214}
79aceca5 2215
a750fc0b 2216/* fsel */
7c58044c 2217_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2218/* fsub - fsubs */
7c58044c 2219GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2220/* Optional: */
2221/* fsqrt */
a750fc0b 2222GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2223{
76a66253 2224 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2225 gen_exception(ctx, POWERPC_EXCP_FPU);
c7d344af
FB		 2226 return;
2227 }
eb44b959
AJ		 2228 /* NIP cannot be restored if the memory exception comes from an helper */
2229 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2230 gen_reset_fpstatus();
af12906f
AJ		 2231 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2232 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
c7d344af 2233}
79aceca5 2234
a750fc0b 2235GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2236{
76a66253 2237 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2238 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2239 return;
2240 }
eb44b959
AJ		 2241 /* NIP cannot be restored if the memory exception comes from an helper */
2242 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2243 gen_reset_fpstatus();
af12906f
AJ		 2244 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2245 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]);
2246 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2247}
2248
2249/*** Floating-Point multiply-and-add ***/
4ecc3190 2250/* fmadd - fmadds */
7c58044c 2251GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2252/* fmsub - fmsubs */
7c58044c 2253GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2254/* fnmadd - fnmadds */
7c58044c 2255GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2256/* fnmsub - fnmsubs */
7c58044c 2257GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2258
2259/*** Floating-Point round & convert ***/
2260/* fctiw */
7c58044c 2261GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2262/* fctiwz */
7c58044c 2263GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2264/* frsp */
7c58044c 2265GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2266#if defined(TARGET_PPC64)
2267/* fcfid */
7c58044c 2268GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2269/* fctid */
7c58044c 2270GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2271/* fctidz */
7c58044c 2272GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2273#endif
79aceca5 2274
d7e4b87e 2275/* frin */
7c58044c 2276GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2277/* friz */
7c58044c 2278GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2279/* frip */
7c58044c 2280GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2281/* frim */
7c58044c 2282GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2283
79aceca5
FB		 2284/*** Floating-Point compare ***/
2285/* fcmpo */
76a66253 2286GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2287{
330c483b 2288 TCGv_i32 crf;
76a66253 2289 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2290 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2291 return;
2292 }
eb44b959
AJ		 2293 /* NIP cannot be restored if the memory exception comes from an helper */
2294 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2295 gen_reset_fpstatus();
9a819377
AJ		 2296 crf = tcg_const_i32(crfD(ctx->opcode));
2297 gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2298 tcg_temp_free_i32(crf);
af12906f 2299 gen_helper_float_check_status();
79aceca5
FB		 2300}
2301
2302/* fcmpu */
76a66253 2303GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2304{
330c483b 2305 TCGv_i32 crf;
76a66253 2306 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2307 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2308 return;
2309 }
eb44b959
AJ		 2310 /* NIP cannot be restored if the memory exception comes from an helper */
2311 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2312 gen_reset_fpstatus();
9a819377
AJ		 2313 crf = tcg_const_i32(crfD(ctx->opcode));
2314 gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf);
330c483b 2315 tcg_temp_free_i32(crf);
af12906f 2316 gen_helper_float_check_status();
79aceca5
FB		 2317}
2318
9a64fbe4
FB		 2319/*** Floating-point move ***/
2320/* fabs */
7c58044c
JM		 2321/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2322GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2323
2324/* fmr - fmr. */
7c58044c 2325/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2326GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2327{
76a66253 2328 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2329 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2330 return;
2331 }
af12906f
AJ		 2332 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2333 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2334}
2335
2336/* fnabs */
7c58044c
JM		 2337/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2338GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2339/* fneg */
7c58044c
JM		 2340/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2341GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2342
79aceca5
FB		 2343/*** Floating-Point status & ctrl register ***/
2344/* mcrfs */
2345GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2346{
7c58044c
JM		 2347 int bfa;
2348
76a66253 2349 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2350 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2351 return;
2352 }
7c58044c 2353 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2354 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2355 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
af12906f 2356 tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
79aceca5
FB		 2357}
2358
2359/* mffs */
2360GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2361{
76a66253 2362 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2363 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2364 return;
2365 }
7c58044c 2366 gen_reset_fpstatus();
af12906f
AJ		 2367 tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2368 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2369}
2370
2371/* mtfsb0 */
2372GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2373{
fb0eaffc 2374 uint8_t crb;
3b46e624 2375
76a66253 2376 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2377 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2378 return;
2379 }
6e35d524 2380 crb = 31 - crbD(ctx->opcode);
7c58044c 2381 gen_reset_fpstatus();
6e35d524 2382 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
eb44b959
AJ		 2383 TCGv_i32 t0;
2384 /* NIP cannot be restored if the memory exception comes from an helper */
2385 gen_update_nip(ctx, ctx->nip - 4);
2386 t0 = tcg_const_i32(crb);
6e35d524
AJ		 2387 gen_helper_fpscr_clrbit(t0);
2388 tcg_temp_free_i32(t0);
2389 }
7c58044c 2390 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2391 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2392 }
79aceca5
FB		 2393}
2394
2395/* mtfsb1 */
2396GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2397{
fb0eaffc 2398 uint8_t crb;
3b46e624 2399
76a66253 2400 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2401 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2402 return;
2403 }
6e35d524 2404 crb = 31 - crbD(ctx->opcode);
7c58044c
JM		 2405 gen_reset_fpstatus();
2406 /* XXX: we pretend we can only do IEEE floating-point computations */
af12906f 2407 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
eb44b959
AJ		 2408 TCGv_i32 t0;
2409 /* NIP cannot be restored if the memory exception comes from an helper */
2410 gen_update_nip(ctx, ctx->nip - 4);
2411 t0 = tcg_const_i32(crb);
af12906f 2412 gen_helper_fpscr_setbit(t0);
0f2f39c2 2413 tcg_temp_free_i32(t0);
af12906f 2414 }
7c58044c 2415 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2416 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2417 }
2418 /* We can raise a differed exception */
af12906f 2419 gen_helper_float_check_status();
79aceca5
FB		 2420}
2421
2422/* mtfsf */
4911012d 2423GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT)
79aceca5 2424{
0f2f39c2 2425 TCGv_i32 t0;
4911012d 2426 int L = ctx->opcode & 0x02000000;
af12906f 2427
76a66253 2428 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2429 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2430 return;
2431 }
eb44b959
AJ		 2432 /* NIP cannot be restored if the memory exception comes from an helper */
2433 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2434 gen_reset_fpstatus();
4911012d
BS		 2435 if (L)
2436 t0 = tcg_const_i32(0xff);
2437 else
2438 t0 = tcg_const_i32(FM(ctx->opcode));
af12906f 2439 gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0);
0f2f39c2 2440 tcg_temp_free_i32(t0);
7c58044c 2441 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2442 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2443 }
2444 /* We can raise a differed exception */
af12906f 2445 gen_helper_float_check_status();
79aceca5
FB		 2446}
2447
2448/* mtfsfi */
2449GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2450{
7c58044c 2451 int bf, sh;
0f2f39c2
AJ		 2452 TCGv_i64 t0;
2453 TCGv_i32 t1;
7c58044c 2454
76a66253 2455 if (unlikely(!ctx->fpu_enabled)) {
e06fcd75 2456 gen_exception(ctx, POWERPC_EXCP_FPU);
3cc62370
FB		 2457 return;
2458 }
7c58044c
JM		 2459 bf = crbD(ctx->opcode) >> 2;
2460 sh = 7 - bf;
eb44b959
AJ		 2461 /* NIP cannot be restored if the memory exception comes from an helper */
2462 gen_update_nip(ctx, ctx->nip - 4);
7c58044c 2463 gen_reset_fpstatus();
0f2f39c2 2464 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
af12906f
AJ		 2465 t1 = tcg_const_i32(1 << sh);
2466 gen_helper_store_fpscr(t0, t1);
0f2f39c2
AJ		 2467 tcg_temp_free_i64(t0);
2468 tcg_temp_free_i32(t1);
7c58044c 2469 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2470 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2471 }
2472 /* We can raise a differed exception */
af12906f 2473 gen_helper_float_check_status();
79aceca5
FB		 2474}
2475
76a66253
JM		 2476/*** Addressing modes ***/
2477/* Register indirect with immediate index : EA = (rA|0) + SIMM */
76db3ba4 2478static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
76a66253
JM		 2479{
2480 target_long simm = SIMM(ctx->opcode);
2481
be147d08 2482 simm &= ~maskl;
76db3ba4
AJ		 2483 if (rA(ctx->opcode) == 0) {
2484#if defined(TARGET_PPC64)
2485 if (!ctx->sf_mode) {
2486 tcg_gen_movi_tl(EA, (uint32_t)simm);
2487 } else
2488#endif
e2be8d8d 2489 tcg_gen_movi_tl(EA, simm);
76db3ba4 2490 } else if (likely(simm != 0)) {
e2be8d8d 2491 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
76db3ba4
AJ		 2492#if defined(TARGET_PPC64)
2493 if (!ctx->sf_mode) {
2494 tcg_gen_ext32u_tl(EA, EA);
2495 }
2496#endif
2497 } else {
2498#if defined(TARGET_PPC64)
2499 if (!ctx->sf_mode) {
2500 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2501 } else
2502#endif
e2be8d8d 2503 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76db3ba4 2504 }
76a66253
JM		 2505}
2506
76db3ba4 2507static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
76a66253 2508{
76db3ba4
AJ		 2509 if (rA(ctx->opcode) == 0) {
2510#if defined(TARGET_PPC64)
2511 if (!ctx->sf_mode) {
2512 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2513 } else
2514#endif
e2be8d8d 2515 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
76db3ba4 2516 } else {
e2be8d8d 2517 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76db3ba4
AJ		 2518#if defined(TARGET_PPC64)
2519 if (!ctx->sf_mode) {
2520 tcg_gen_ext32u_tl(EA, EA);
2521 }
2522#endif
2523 }
76a66253
JM		 2524}
2525
76db3ba4 2526static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
76a66253 2527{
76db3ba4 2528 if (rA(ctx->opcode) == 0) {
e2be8d8d 2529 tcg_gen_movi_tl(EA, 0);
76db3ba4
AJ		 2530 } else {
2531#if defined(TARGET_PPC64)
2532 if (!ctx->sf_mode) {
2533 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2534 } else
2535#endif
2536 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2537 }
2538}
2539
2540static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
2541{
2542 tcg_gen_addi_tl(ret, arg1, val);
2543#if defined(TARGET_PPC64)
2544 if (!ctx->sf_mode) {
2545 tcg_gen_ext32u_tl(ret, ret);
2546 }
2547#endif
76a66253
JM		 2548}
2549
cf360a32
AJ		 2550static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
2551{
2552 int l1 = gen_new_label();
2553 TCGv t0 = tcg_temp_new();
2554 TCGv_i32 t1, t2;
2555 /* NIP cannot be restored if the memory exception comes from an helper */
2556 gen_update_nip(ctx, ctx->nip - 4);
2557 tcg_gen_andi_tl(t0, EA, mask);
2558 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2559 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2560 t2 = tcg_const_i32(0);
2561 gen_helper_raise_exception_err(t1, t2);
2562 tcg_temp_free_i32(t1);
2563 tcg_temp_free_i32(t2);
2564 gen_set_label(l1);
2565 tcg_temp_free(t0);
2566}
2567
7863667f 2568/*** Integer load ***/
76db3ba4
AJ		 2569static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2570{
2571 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2572}
2573
2574static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2575{
2576 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2577}
2578
2579static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2580{
2581 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2582 if (unlikely(ctx->le_mode)) {
b61f2753 2583#if defined(TARGET_PPC64)
76db3ba4
AJ		 2584 TCGv_i32 t0 = tcg_temp_new_i32();
2585 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2586 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2587 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2588 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2589#else
2590 tcg_gen_bswap16_i32(arg1, arg1);
2591#endif
2592 }
b61f2753
AJ		 2593}
2594
76db3ba4 2595static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2596{
76db3ba4
AJ		 2597 if (unlikely(ctx->le_mode)) {
2598#if defined(TARGET_PPC64)
a7812ae4 2599 TCGv_i32 t0;
76db3ba4 2600 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
a7812ae4 2601 t0 = tcg_temp_new_i32();
76db3ba4 2602 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2603 tcg_gen_bswap16_i32(t0, t0);
76db3ba4
AJ		 2604 tcg_gen_extu_i32_tl(arg1, t0);
2605 tcg_gen_ext16s_tl(arg1, arg1);
a7812ae4 2606 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2607#else
2608 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2609 tcg_gen_bswap16_i32(arg1, arg1);
2610 tcg_gen_ext16s_i32(arg1, arg1);
2611#endif
2612 } else {
2613 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2614 }
b61f2753
AJ		 2615}
2616
76db3ba4 2617static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2618{
76db3ba4
AJ		 2619 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2620 if (unlikely(ctx->le_mode)) {
2621#if defined(TARGET_PPC64)
2622 TCGv_i32 t0 = tcg_temp_new_i32();
2623 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2624 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2625 tcg_gen_extu_i32_tl(arg1, t0);
a7812ae4 2626 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2627#else
2628 tcg_gen_bswap_i32(arg1, arg1);
2629#endif
2630 }
b61f2753
AJ		 2631}
2632
76db3ba4
AJ		 2633#if defined(TARGET_PPC64)
2634static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2635{
a457e7ee 2636 if (unlikely(ctx->le_mode)) {
a7812ae4 2637 TCGv_i32 t0;
76db3ba4 2638 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
a7812ae4 2639 t0 = tcg_temp_new_i32();
76db3ba4 2640 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2641 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2642 tcg_gen_ext_i32_tl(arg1, t0);
a7812ae4 2643 tcg_temp_free_i32(t0);
b61f2753 2644 } else
76db3ba4 2645 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
b61f2753 2646}
76db3ba4 2647#endif
b61f2753 2648
76db3ba4 2649static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2650{
76db3ba4
AJ		 2651 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2652 if (unlikely(ctx->le_mode)) {
2653 tcg_gen_bswap_i64(arg1, arg1);
2654 }
b61f2753
AJ		 2655}
2656
76db3ba4 2657static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2658{
76db3ba4 2659 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2660}
2661
76db3ba4 2662static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2663{
76db3ba4
AJ		 2664 if (unlikely(ctx->le_mode)) {
2665#if defined(TARGET_PPC64)
a7812ae4 2666 TCGv_i32 t0;
76db3ba4 2667 TCGv t1;
a7812ae4 2668 t0 = tcg_temp_new_i32();
76db3ba4 2669 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694
AJ		 2670 tcg_gen_ext16u_i32(t0, t0);
2671 tcg_gen_bswap16_i32(t0, t0);
76db3ba4 2672 t1 = tcg_temp_new();
ea363694 2673 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2674 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2675 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
2676 tcg_temp_free(t1);
2677#else
2678 TCGv t0 = tcg_temp_new();
2679 tcg_gen_ext16u_tl(t0, arg1);
2680 tcg_gen_bswap16_i32(t0, t0);
2681 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2682 tcg_temp_free(t0);
2683#endif
2684 } else {
2685 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2686 }
b61f2753
AJ		 2687}
2688
76db3ba4 2689static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2690{
76db3ba4
AJ		 2691 if (unlikely(ctx->le_mode)) {
2692#if defined(TARGET_PPC64)
a7812ae4 2693 TCGv_i32 t0;
76db3ba4 2694 TCGv t1;
a7812ae4 2695 t0 = tcg_temp_new_i32();
76db3ba4 2696 tcg_gen_trunc_tl_i32(t0, arg1);
ea363694 2697 tcg_gen_bswap_i32(t0, t0);
76db3ba4 2698 t1 = tcg_temp_new();
ea363694 2699 tcg_gen_extu_i32_tl(t1, t0);
a7812ae4 2700 tcg_temp_free_i32(t0);
76db3ba4
AJ		 2701 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
2702 tcg_temp_free(t1);
2703#else
2704 TCGv t0 = tcg_temp_new_i32();
2705 tcg_gen_bswap_i32(t0, arg1);
2706 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2707 tcg_temp_free(t0);
2708#endif
2709 } else {
2710 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2711 }
b61f2753
AJ		 2712}
2713
76db3ba4 2714static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
b61f2753 2715{
76db3ba4 2716 if (unlikely(ctx->le_mode)) {
a7812ae4 2717 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4
AJ		 2718 tcg_gen_bswap_i64(t0, arg1);
2719 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
a7812ae4 2720 tcg_temp_free_i64(t0);
b61f2753 2721 } else
76db3ba4 2722 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
b61f2753
AJ		 2723}
2724
0c8aacd4
AJ		 2725#define GEN_LD(name, ldop, opc, type) \
2726GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2727{ \
76db3ba4
AJ		 2728 TCGv EA; \
2729 gen_set_access_type(ctx, ACCESS_INT); \
2730 EA = tcg_temp_new(); \
2731 gen_addr_imm_index(ctx, EA, 0); \
2732 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2733 tcg_temp_free(EA); \
79aceca5
FB		 2734}
2735
0c8aacd4
AJ		 2736#define GEN_LDU(name, ldop, opc, type) \
2737GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2738{ \
b61f2753 2739 TCGv EA; \
76a66253
JM		 2740 if (unlikely(rA(ctx->opcode) == 0 || \
2741 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2742 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2743 return; \
9a64fbe4 2744 } \
76db3ba4 2745 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2746 EA = tcg_temp_new(); \
9d53c753 2747 if (type == PPC_64B) \
76db3ba4 2748 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2749 else \
76db3ba4
AJ		 2750 gen_addr_imm_index(ctx, EA, 0); \
2751 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2752 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2753 tcg_temp_free(EA); \
79aceca5
FB		 2754}
2755
0c8aacd4
AJ		 2756#define GEN_LDUX(name, ldop, opc2, opc3, type) \
2757GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2758{ \
b61f2753 2759 TCGv EA; \
76a66253
JM		 2760 if (unlikely(rA(ctx->opcode) == 0 || \
2761 rA(ctx->opcode) == rD(ctx->opcode))) { \
e06fcd75 2762 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2763 return; \
9a64fbe4 2764 } \
76db3ba4 2765 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2766 EA = tcg_temp_new(); \
76db3ba4
AJ		 2767 gen_addr_reg_index(ctx, EA); \
2768 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753
AJ		 2769 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2770 tcg_temp_free(EA); \
79aceca5
FB		 2771}
2772
0c8aacd4
AJ		 2773#define GEN_LDX(name, ldop, opc2, opc3, type) \
2774GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2775{ \
76db3ba4
AJ		 2776 TCGv EA; \
2777 gen_set_access_type(ctx, ACCESS_INT); \
2778 EA = tcg_temp_new(); \
2779 gen_addr_reg_index(ctx, EA); \
2780 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
b61f2753 2781 tcg_temp_free(EA); \
79aceca5
FB		 2782}
2783
0c8aacd4
AJ		 2784#define GEN_LDS(name, ldop, op, type) \
2785GEN_LD(name, ldop, op | 0x20, type); \
2786GEN_LDU(name, ldop, op | 0x21, type); \
2787GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2788GEN_LDX(name, ldop, 0x17, op | 0x00, type)
79aceca5
FB		 2789
2790/* lbz lbzu lbzux lbzx */
0c8aacd4 2791GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
79aceca5 2792/* lha lhau lhaux lhax */
0c8aacd4 2793GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
79aceca5 2794/* lhz lhzu lhzux lhzx */
0c8aacd4 2795GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
79aceca5 2796/* lwz lwzu lwzux lwzx */
0c8aacd4 2797GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
d9bce9d9 2798#if defined(TARGET_PPC64)
d9bce9d9 2799/* lwaux */
0c8aacd4 2800GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2801/* lwax */
0c8aacd4 2802GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2803/* ldux */
0c8aacd4 2804GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
d9bce9d9 2805/* ldx */
0c8aacd4 2806GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2807GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2808{
b61f2753 2809 TCGv EA;
d9bce9d9
JM		 2810 if (Rc(ctx->opcode)) {
2811 if (unlikely(rA(ctx->opcode) == 0 ||
2812 rA(ctx->opcode) == rD(ctx->opcode))) {
e06fcd75 2813 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2814 return;
2815 }
2816 }
76db3ba4 2817 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2818 EA = tcg_temp_new();
76db3ba4 2819 gen_addr_imm_index(ctx, EA, 0x03);
d9bce9d9
JM		 2820 if (ctx->opcode & 0x02) {
2821 /* lwa (lwau is undefined) */
76db3ba4 2822 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9
JM		 2823 } else {
2824 /* ld - ldu */
76db3ba4 2825 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
d9bce9d9 2826 }
d9bce9d9 2827 if (Rc(ctx->opcode))
b61f2753
AJ		 2828 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2829 tcg_temp_free(EA);
d9bce9d9 2830}
be147d08
JM		 2831/* lq */
2832GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2833{
2834#if defined(CONFIG_USER_ONLY)
e06fcd75 2835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2836#else
2837 int ra, rd;
b61f2753 2838 TCGv EA;
be147d08
JM		 2839
2840 /* Restore CPU state */
76db3ba4 2841 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2842 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2843 return;
2844 }
2845 ra = rA(ctx->opcode);
2846 rd = rD(ctx->opcode);
2847 if (unlikely((rd & 1) || rd == ra)) {
e06fcd75 2848 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2849 return;
2850 }
76db3ba4 2851 if (unlikely(ctx->le_mode)) {
be147d08 2852 /* Little-endian mode is not handled */
e06fcd75 2853 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2854 return;
2855 }
76db3ba4 2856 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2857 EA = tcg_temp_new();
76db3ba4
AJ		 2858 gen_addr_imm_index(ctx, EA, 0x0F);
2859 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2860 gen_addr_add(ctx, EA, EA, 8);
2861 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
b61f2753 2862 tcg_temp_free(EA);
be147d08
JM		 2863#endif
2864}
d9bce9d9 2865#endif
79aceca5
FB		 2866
2867/*** Integer store ***/
0c8aacd4
AJ		 2868#define GEN_ST(name, stop, opc, type) \
2869GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2870{ \
76db3ba4
AJ		 2871 TCGv EA; \
2872 gen_set_access_type(ctx, ACCESS_INT); \
2873 EA = tcg_temp_new(); \
2874 gen_addr_imm_index(ctx, EA, 0); \
2875 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2876 tcg_temp_free(EA); \
79aceca5
FB		 2877}
2878
0c8aacd4
AJ		 2879#define GEN_STU(name, stop, opc, type) \
2880GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2881{ \
b61f2753 2882 TCGv EA; \
76a66253 2883 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2884 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2885 return; \
9a64fbe4 2886 } \
76db3ba4 2887 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2888 EA = tcg_temp_new(); \
9d53c753 2889 if (type == PPC_64B) \
76db3ba4 2890 gen_addr_imm_index(ctx, EA, 0x03); \
9d53c753 2891 else \
76db3ba4
AJ		 2892 gen_addr_imm_index(ctx, EA, 0); \
2893 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2894 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2895 tcg_temp_free(EA); \
79aceca5
FB		 2896}
2897
0c8aacd4
AJ		 2898#define GEN_STUX(name, stop, opc2, opc3, type) \
2899GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2900{ \
b61f2753 2901 TCGv EA; \
76a66253 2902 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 2903 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 2904 return; \
9a64fbe4 2905 } \
76db3ba4 2906 gen_set_access_type(ctx, ACCESS_INT); \
0c8aacd4 2907 EA = tcg_temp_new(); \
76db3ba4
AJ		 2908 gen_addr_reg_index(ctx, EA); \
2909 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753
AJ		 2910 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2911 tcg_temp_free(EA); \
79aceca5
FB		 2912}
2913
0c8aacd4
AJ		 2914#define GEN_STX(name, stop, opc2, opc3, type) \
2915GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2916{ \
76db3ba4
AJ		 2917 TCGv EA; \
2918 gen_set_access_type(ctx, ACCESS_INT); \
2919 EA = tcg_temp_new(); \
2920 gen_addr_reg_index(ctx, EA); \
2921 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
b61f2753 2922 tcg_temp_free(EA); \
79aceca5
FB		 2923}
2924
0c8aacd4
AJ		 2925#define GEN_STS(name, stop, op, type) \
2926GEN_ST(name, stop, op | 0x20, type); \
2927GEN_STU(name, stop, op | 0x21, type); \
2928GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2929GEN_STX(name, stop, 0x17, op | 0x00, type)
79aceca5
FB		 2930
2931/* stb stbu stbux stbx */
0c8aacd4 2932GEN_STS(stb, st8, 0x06, PPC_INTEGER);
79aceca5 2933/* sth sthu sthux sthx */
0c8aacd4 2934GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
79aceca5 2935/* stw stwu stwux stwx */
0c8aacd4 2936GEN_STS(stw, st32, 0x04, PPC_INTEGER);
d9bce9d9 2937#if defined(TARGET_PPC64)
0c8aacd4
AJ		 2938GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2939GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
be147d08 2940GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2941{
be147d08 2942 int rs;
b61f2753 2943 TCGv EA;
be147d08
JM		 2944
2945 rs = rS(ctx->opcode);
2946 if ((ctx->opcode & 0x3) == 0x2) {
2947#if defined(CONFIG_USER_ONLY)
e06fcd75 2948 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2949#else
2950 /* stq */
76db3ba4 2951 if (unlikely(ctx->mem_idx == 0)) {
e06fcd75 2952 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 2953 return;
2954 }
2955 if (unlikely(rs & 1)) {
e06fcd75 2956 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
d9bce9d9
JM		 2957 return;
2958 }
76db3ba4 2959 if (unlikely(ctx->le_mode)) {
be147d08 2960 /* Little-endian mode is not handled */
e06fcd75 2961 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
be147d08
JM		 2962 return;
2963 }
76db3ba4 2964 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2965 EA = tcg_temp_new();
76db3ba4
AJ		 2966 gen_addr_imm_index(ctx, EA, 0x03);
2967 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2968 gen_addr_add(ctx, EA, EA, 8);
2969 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
b61f2753 2970 tcg_temp_free(EA);
be147d08
JM		 2971#endif
2972 } else {
2973 /* std / stdu */
2974 if (Rc(ctx->opcode)) {
2975 if (unlikely(rA(ctx->opcode) == 0)) {
e06fcd75 2976 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
be147d08
JM		 2977 return;
2978 }
2979 }
76db3ba4 2980 gen_set_access_type(ctx, ACCESS_INT);
a7812ae4 2981 EA = tcg_temp_new();
76db3ba4
AJ		 2982 gen_addr_imm_index(ctx, EA, 0x03);
2983 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
be147d08 2984 if (Rc(ctx->opcode))
b61f2753
AJ		 2985 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2986 tcg_temp_free(EA);
d9bce9d9 2987 }
d9bce9d9
JM		 2988}
2989#endif
79aceca5
FB		 2990/*** Integer load and store with byte reverse ***/
2991/* lhbrx */
76db3ba4 2992static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 2993{
76db3ba4
AJ		 2994 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2995 if (likely(!ctx->le_mode)) {
2996#if defined(TARGET_PPC64)
2997 TCGv_i32 t0 = tcg_temp_new_i32();
2998 tcg_gen_trunc_tl_i32(t0, arg1);
2999 tcg_gen_bswap16_i32(t0, t0);
3000 tcg_gen_extu_i32_tl(arg1, t0);
3001 tcg_temp_free_i32(t0);
3002#else
3003 tcg_gen_bswap16_i32(arg1, arg1);
3004#endif
3005 }
b61f2753 3006}
0c8aacd4 3007GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
b61f2753 3008
79aceca5 3009/* lwbrx */
76db3ba4 3010static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3011{
76db3ba4
AJ		 3012 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3013 if (likely(!ctx->le_mode)) {
3014#if defined(TARGET_PPC64)
3015 TCGv_i32 t0 = tcg_temp_new_i32();
3016 tcg_gen_trunc_tl_i32(t0, arg1);
3017 tcg_gen_bswap_i32(t0, t0);
3018 tcg_gen_extu_i32_tl(arg1, t0);
3019 tcg_temp_free_i32(t0);
3020#else
3021 tcg_gen_bswap_i32(arg1, arg1);
3022#endif
3023 }
b61f2753 3024}
0c8aacd4 3025GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
b61f2753 3026
79aceca5 3027/* sthbrx */
76db3ba4 3028static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3029{
76db3ba4
AJ		 3030 if (likely(!ctx->le_mode)) {
3031#if defined(TARGET_PPC64)
3032 TCGv_i32 t0;
3033 TCGv t1;
3034 t0 = tcg_temp_new_i32();
3035 tcg_gen_trunc_tl_i32(t0, arg1);
3036 tcg_gen_ext16u_i32(t0, t0);
3037 tcg_gen_bswap16_i32(t0, t0);
3038 t1 = tcg_temp_new();
3039 tcg_gen_extu_i32_tl(t1, t0);
3040 tcg_temp_free_i32(t0);
3041 tcg_gen_qemu_st16(t1, arg2, ctx->mem_idx);
3042 tcg_temp_free(t1);
3043#else
3044 TCGv t0 = tcg_temp_new();
3045 tcg_gen_ext16u_tl(t0, arg1);
3046 tcg_gen_bswap16_i32(t0, t0);
3047 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3048 tcg_temp_free(t0);
3049#endif
3050 } else {
3051 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3052 }
b61f2753 3053}
0c8aacd4 3054GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
b61f2753 3055
79aceca5 3056/* stwbrx */
76db3ba4 3057static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
b61f2753 3058{
76db3ba4
AJ		 3059 if (likely(!ctx->le_mode)) {
3060#if defined(TARGET_PPC64)
3061 TCGv_i32 t0;
3062 TCGv t1;
3063 t0 = tcg_temp_new_i32();
3064 tcg_gen_trunc_tl_i32(t0, arg1);
3065 tcg_gen_bswap_i32(t0, t0);
3066 t1 = tcg_temp_new();
3067 tcg_gen_extu_i32_tl(t1, t0);
3068 tcg_temp_free_i32(t0);
3069 tcg_gen_qemu_st32(t1, arg2, ctx->mem_idx);
3070 tcg_temp_free(t1);
3071#else
3072 TCGv t0 = tcg_temp_new_i32();
3073 tcg_gen_bswap_i32(t0, arg1);
3074 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3075 tcg_temp_free(t0);
3076#endif
3077 } else {
3078 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3079 }
b61f2753 3080}
0c8aacd4 3081GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3082
3083/*** Integer load and store multiple ***/
3084/* lmw */
3085GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3086{
76db3ba4
AJ		 3087 TCGv t0;
3088 TCGv_i32 t1;
3089 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3090 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3091 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3092 t0 = tcg_temp_new();
3093 t1 = tcg_const_i32(rD(ctx->opcode));
3094 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3095 gen_helper_lmw(t0, t1);
3096 tcg_temp_free(t0);
3097 tcg_temp_free_i32(t1);
79aceca5
FB		 3098}
3099
3100/* stmw */
3101GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3102{
76db3ba4
AJ		 3103 TCGv t0;
3104 TCGv_i32 t1;
3105 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3106 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3107 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3108 t0 = tcg_temp_new();
3109 t1 = tcg_const_i32(rS(ctx->opcode));
3110 gen_addr_imm_index(ctx, t0, 0);
ff4a62cd
AJ		 3111 gen_helper_stmw(t0, t1);
3112 tcg_temp_free(t0);
3113 tcg_temp_free_i32(t1);
79aceca5
FB		 3114}
3115
3116/*** Integer load and store strings ***/
3117/* lswi */
3fc6c082 3118/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3119 * rA is in the range of registers to be loaded.
3120 * In an other hand, IBM says this is valid, but rA won't be loaded.
3121 * For now, I'll follow the spec...
3122 */
05332d70 3123GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5 3124{
dfbc799d
AJ		 3125 TCGv t0;
3126 TCGv_i32 t1, t2;
79aceca5
FB		 3127 int nb = NB(ctx->opcode);
3128 int start = rD(ctx->opcode);
9a64fbe4 3129 int ra = rA(ctx->opcode);
79aceca5
FB		 3130 int nr;
3131
3132 if (nb == 0)
3133 nb = 32;
3134 nr = nb / 4;
76a66253
JM		 3135 if (unlikely(((start + nr) > 32 &&
3136 start <= ra && (start + nr - 32) > ra) ||
3137 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e06fcd75 3138 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3139 return;
297d8e62 3140 }
76db3ba4 3141 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3142 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3143 gen_update_nip(ctx, ctx->nip - 4);
dfbc799d 3144 t0 = tcg_temp_new();
76db3ba4 3145 gen_addr_register(ctx, t0);
dfbc799d
AJ		 3146 t1 = tcg_const_i32(nb);
3147 t2 = tcg_const_i32(start);
3148 gen_helper_lsw(t0, t1, t2);
3149 tcg_temp_free(t0);
3150 tcg_temp_free_i32(t1);
3151 tcg_temp_free_i32(t2);
79aceca5
FB		 3152}
3153
3154/* lswx */
05332d70 3155GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3156{
76db3ba4
AJ		 3157 TCGv t0;
3158 TCGv_i32 t1, t2, t3;
3159 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3160 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3161 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3162 t0 = tcg_temp_new();
3163 gen_addr_reg_index(ctx, t0);
3164 t1 = tcg_const_i32(rD(ctx->opcode));
3165 t2 = tcg_const_i32(rA(ctx->opcode));
3166 t3 = tcg_const_i32(rB(ctx->opcode));
dfbc799d
AJ		 3167 gen_helper_lswx(t0, t1, t2, t3);
3168 tcg_temp_free(t0);
3169 tcg_temp_free_i32(t1);
3170 tcg_temp_free_i32(t2);
3171 tcg_temp_free_i32(t3);
79aceca5
FB		 3172}
3173
3174/* stswi */
05332d70 3175GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3176{
76db3ba4
AJ		 3177 TCGv t0;
3178 TCGv_i32 t1, t2;
4b3686fa 3179 int nb = NB(ctx->opcode);
76db3ba4 3180 gen_set_access_type(ctx, ACCESS_INT);
76a66253 3181 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3182 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3183 t0 = tcg_temp_new();
3184 gen_addr_register(ctx, t0);
4b3686fa
FB		 3185 if (nb == 0)
3186 nb = 32;
dfbc799d 3187 t1 = tcg_const_i32(nb);
76db3ba4 3188 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3189 gen_helper_stsw(t0, t1, t2);
3190 tcg_temp_free(t0);
3191 tcg_temp_free_i32(t1);
3192 tcg_temp_free_i32(t2);
79aceca5
FB		 3193}
3194
3195/* stswx */
05332d70 3196GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3197{
76db3ba4
AJ		 3198 TCGv t0;
3199 TCGv_i32 t1, t2;
3200 gen_set_access_type(ctx, ACCESS_INT);
8dd4983c 3201 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3202 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 3203 t0 = tcg_temp_new();
3204 gen_addr_reg_index(ctx, t0);
3205 t1 = tcg_temp_new_i32();
dfbc799d
AJ		 3206 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3207 tcg_gen_andi_i32(t1, t1, 0x7F);
76db3ba4 3208 t2 = tcg_const_i32(rS(ctx->opcode));
dfbc799d
AJ		 3209 gen_helper_stsw(t0, t1, t2);
3210 tcg_temp_free(t0);
3211 tcg_temp_free_i32(t1);
3212 tcg_temp_free_i32(t2);
79aceca5
FB		 3213}
3214
3215/*** Memory synchronisation ***/
3216/* eieio */
0db1b20e 3217GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3218{
79aceca5
FB		 3219}
3220
3221/* isync */
0db1b20e 3222GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3223{
e06fcd75 3224 gen_stop_exception(ctx);
79aceca5
FB		 3225}
3226
111bfab3 3227/* lwarx */
76a66253 3228GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3229{
76db3ba4
AJ		 3230 TCGv t0;
3231 gen_set_access_type(ctx, ACCESS_RES);
3232 t0 = tcg_temp_local_new();
3233 gen_addr_reg_index(ctx, t0);
cf360a32 3234 gen_check_align(ctx, t0, 0x03);
76db3ba4 3235 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3236 tcg_gen_mov_tl(cpu_reserve, t0);
3237 tcg_temp_free(t0);
79aceca5
FB		 3238}
3239
3240/* stwcx. */
c7697e1f 3241GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3242{
76db3ba4
AJ		 3243 int l1;
3244 TCGv t0;
3245 gen_set_access_type(ctx, ACCESS_RES);
3246 t0 = tcg_temp_local_new();
3247 gen_addr_reg_index(ctx, t0);
cf360a32 3248 gen_check_align(ctx, t0, 0x03);
cf360a32
AJ		 3249 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3250 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3251 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3252 l1 = gen_new_label();
cf360a32
AJ		 3253 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3254 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3255 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3256 gen_set_label(l1);
3257 tcg_gen_movi_tl(cpu_reserve, -1);
3258 tcg_temp_free(t0);
79aceca5
FB		 3259}
3260
426613db 3261#if defined(TARGET_PPC64)
426613db 3262/* ldarx */
a750fc0b 3263GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3264{
76db3ba4
AJ		 3265 TCGv t0;
3266 gen_set_access_type(ctx, ACCESS_RES);
3267 t0 = tcg_temp_local_new();
3268 gen_addr_reg_index(ctx, t0);
cf360a32 3269 gen_check_align(ctx, t0, 0x07);
76db3ba4 3270 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0);
cf360a32
AJ		 3271 tcg_gen_mov_tl(cpu_reserve, t0);
3272 tcg_temp_free(t0);
426613db
JM		 3273}
3274
3275/* stdcx. */
c7697e1f 3276GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3277{
76db3ba4
AJ		 3278 int l1;
3279 TCGv t0;
3280 gen_set_access_type(ctx, ACCESS_RES);
3281 t0 = tcg_temp_local_new();
3282 gen_addr_reg_index(ctx, t0);
cf360a32 3283 gen_check_align(ctx, t0, 0x07);
cf360a32
AJ		 3284 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
3285 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
3286 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
76db3ba4 3287 l1 = gen_new_label();
cf360a32
AJ		 3288 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3289 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
76db3ba4 3290 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
cf360a32
AJ		 3291 gen_set_label(l1);
3292 tcg_gen_movi_tl(cpu_reserve, -1);
3293 tcg_temp_free(t0);
426613db
JM		 3294}
3295#endif /* defined(TARGET_PPC64) */
3296
79aceca5 3297/* sync */
a902d886 3298GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3299{
79aceca5
FB		 3300}
3301
0db1b20e
JM		 3302/* wait */
3303GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3304{
931ff272
AJ		 3305 TCGv_i32 t0 = tcg_temp_new_i32();
3306 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted));
3307 tcg_temp_free_i32(t0);
0db1b20e 3308 /* Stop translation, as the CPU is supposed to sleep from now */
e06fcd75 3309 gen_exception_err(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3310}
3311
79aceca5 3312/*** Floating-point load ***/
a0d7d5a7
AJ		 3313#define GEN_LDF(name, ldop, opc, type) \
3314GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3315{ \
a0d7d5a7 3316 TCGv EA; \
76a66253 3317 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3318 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3319 return; \
3320 } \
76db3ba4 3321 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3322 EA = tcg_temp_new(); \
76db3ba4
AJ		 3323 gen_addr_imm_index(ctx, EA, 0); \
3324 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3325 tcg_temp_free(EA); \
79aceca5
FB		 3326}
3327
a0d7d5a7
AJ		 3328#define GEN_LDUF(name, ldop, opc, type) \
3329GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3330{ \
a0d7d5a7 3331 TCGv EA; \
76a66253 3332 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3333 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3334 return; \
3335 } \
76a66253 3336 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3337 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3338 return; \
9a64fbe4 3339 } \
76db3ba4 3340 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3341 EA = tcg_temp_new(); \
76db3ba4
AJ		 3342 gen_addr_imm_index(ctx, EA, 0); \
3343 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3344 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3345 tcg_temp_free(EA); \
79aceca5
FB		 3346}
3347
a0d7d5a7
AJ		 3348#define GEN_LDUXF(name, ldop, opc, type) \
3349GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3350{ \
a0d7d5a7 3351 TCGv EA; \
76a66253 3352 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3353 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3354 return; \
3355 } \
76a66253 3356 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3357 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3358 return; \
9a64fbe4 3359 } \
76db3ba4 3360 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3361 EA = tcg_temp_new(); \
76db3ba4
AJ		 3362 gen_addr_reg_index(ctx, EA); \
3363 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3364 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3365 tcg_temp_free(EA); \
79aceca5
FB		 3366}
3367
a0d7d5a7
AJ		 3368#define GEN_LDXF(name, ldop, opc2, opc3, type) \
3369GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3370{ \
a0d7d5a7 3371 TCGv EA; \
76a66253 3372 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3373 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3374 return; \
3375 } \
76db3ba4 3376 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3377 EA = tcg_temp_new(); \
76db3ba4
AJ		 3378 gen_addr_reg_index(ctx, EA); \
3379 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
a0d7d5a7 3380 tcg_temp_free(EA); \
79aceca5
FB		 3381}
3382
a0d7d5a7
AJ		 3383#define GEN_LDFS(name, ldop, op, type) \
3384GEN_LDF(name, ldop, op | 0x20, type); \
3385GEN_LDUF(name, ldop, op | 0x21, type); \
3386GEN_LDUXF(name, ldop, op | 0x01, type); \
3387GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3388
76db3ba4 3389static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3390{
3391 TCGv t0 = tcg_temp_new();
3392 TCGv_i32 t1 = tcg_temp_new_i32();
76db3ba4 3393 gen_qemu_ld32u(ctx, t0, arg2);
a0d7d5a7
AJ		 3394 tcg_gen_trunc_tl_i32(t1, t0);
3395 tcg_temp_free(t0);
3396 gen_helper_float32_to_float64(arg1, t1);
3397 tcg_temp_free_i32(t1);
3398}
79aceca5 3399
a0d7d5a7
AJ		 3400 /* lfd lfdu lfdux lfdx */
3401GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3402 /* lfs lfsu lfsux lfsx */
3403GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3404
3405/*** Floating-point store ***/
a0d7d5a7
AJ		 3406#define GEN_STF(name, stop, opc, type) \
3407GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3408{ \
a0d7d5a7 3409 TCGv EA; \
76a66253 3410 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3411 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3412 return; \
3413 } \
76db3ba4 3414 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3415 EA = tcg_temp_new(); \
76db3ba4
AJ		 3416 gen_addr_imm_index(ctx, EA, 0); \
3417 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3418 tcg_temp_free(EA); \
79aceca5
FB		 3419}
3420
a0d7d5a7
AJ		 3421#define GEN_STUF(name, stop, opc, type) \
3422GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3423{ \
a0d7d5a7 3424 TCGv EA; \
76a66253 3425 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3426 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3427 return; \
3428 } \
76a66253 3429 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3430 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3431 return; \
9a64fbe4 3432 } \
76db3ba4 3433 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3434 EA = tcg_temp_new(); \
76db3ba4
AJ		 3435 gen_addr_imm_index(ctx, EA, 0); \
3436 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3437 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3438 tcg_temp_free(EA); \
79aceca5
FB		 3439}
3440
a0d7d5a7
AJ		 3441#define GEN_STUXF(name, stop, opc, type) \
3442GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3443{ \
a0d7d5a7 3444 TCGv EA; \
76a66253 3445 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3446 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3447 return; \
3448 } \
76a66253 3449 if (unlikely(rA(ctx->opcode) == 0)) { \
e06fcd75 3450 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
9fddaa0c 3451 return; \
9a64fbe4 3452 } \
76db3ba4 3453 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3454 EA = tcg_temp_new(); \
76db3ba4
AJ		 3455 gen_addr_reg_index(ctx, EA); \
3456 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7
AJ		 3457 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3458 tcg_temp_free(EA); \
79aceca5
FB		 3459}
3460
a0d7d5a7
AJ		 3461#define GEN_STXF(name, stop, opc2, opc3, type) \
3462GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3463{ \
a0d7d5a7 3464 TCGv EA; \
76a66253 3465 if (unlikely(!ctx->fpu_enabled)) { \
e06fcd75 3466 gen_exception(ctx, POWERPC_EXCP_FPU); \
4ecc3190
FB		 3467 return; \
3468 } \
76db3ba4 3469 gen_set_access_type(ctx, ACCESS_FLOAT); \
a0d7d5a7 3470 EA = tcg_temp_new(); \
76db3ba4
AJ		 3471 gen_addr_reg_index(ctx, EA); \
3472 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
a0d7d5a7 3473 tcg_temp_free(EA); \
79aceca5
FB		 3474}
3475
a0d7d5a7
AJ		 3476#define GEN_STFS(name, stop, op, type) \
3477GEN_STF(name, stop, op | 0x20, type); \
3478GEN_STUF(name, stop, op | 0x21, type); \
3479GEN_STUXF(name, stop, op | 0x01, type); \
3480GEN_STXF(name, stop, 0x17, op | 0x00, type)
3481
76db3ba4 3482static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3483{
3484 TCGv_i32 t0 = tcg_temp_new_i32();
3485 TCGv t1 = tcg_temp_new();
3486 gen_helper_float64_to_float32(t0, arg1);
3487 tcg_gen_extu_i32_tl(t1, t0);
3488 tcg_temp_free_i32(t0);
76db3ba4 3489 gen_qemu_st32(ctx, t1, arg2);
a0d7d5a7
AJ		 3490 tcg_temp_free(t1);
3491}
79aceca5
FB		 3492
3493/* stfd stfdu stfdux stfdx */
a0d7d5a7 3494GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
79aceca5 3495/* stfs stfsu stfsux stfsx */
a0d7d5a7 3496GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3497
3498/* Optional: */
76db3ba4 3499static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
a0d7d5a7
AJ		 3500{
3501 TCGv t0 = tcg_temp_new();
3502 tcg_gen_trunc_i64_tl(t0, arg1),
76db3ba4 3503 gen_qemu_st32(ctx, t0, arg2);
a0d7d5a7
AJ		 3504 tcg_temp_free(t0);
3505}
79aceca5 3506/* stfiwx */
a0d7d5a7 3507GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3508
3509/*** Branch ***/
b068d6a7
JM		 3510static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3511 target_ulong dest)
c1942362
FB		 3512{
3513 TranslationBlock *tb;
3514 tb = ctx->tb;
a2ffb812
AJ		 3515#if defined(TARGET_PPC64)
3516 if (!ctx->sf_mode)
3517 dest = (uint32_t) dest;
3518#endif
57fec1fe 3519 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3520 likely(!ctx->singlestep_enabled)) {
57fec1fe 3521 tcg_gen_goto_tb(n);
a2ffb812 3522 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3523 tcg_gen_exit_tb((long)tb + n);
c1942362 3524 } else {
a2ffb812 3525 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3526 if (unlikely(ctx->singlestep_enabled)) {
3527 if ((ctx->singlestep_enabled &
bdc4e053 3528 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
8cbcb4fa
AJ		 3529 ctx->exception == POWERPC_EXCP_BRANCH) {
3530 target_ulong tmp = ctx->nip;
3531 ctx->nip = dest;
e06fcd75 3532 gen_exception(ctx, POWERPC_EXCP_TRACE);
8cbcb4fa
AJ		 3533 ctx->nip = tmp;
3534 }
3535 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
e06fcd75 3536 gen_debug_exception(ctx);
8cbcb4fa
AJ		 3537 }
3538 }
57fec1fe 3539 tcg_gen_exit_tb(0);
c1942362 3540 }
c53be334
FB		 3541}
3542
b068d6a7 3543static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3544{
3545#if defined(TARGET_PPC64)
a2ffb812
AJ		 3546 if (ctx->sf_mode == 0)
3547 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3548 else
3549#endif
a2ffb812 3550 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3551}
3552
79aceca5
FB		 3553/* b ba bl bla */
3554GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3555{
76a66253 3556 target_ulong li, target;
38a64f9d 3557
8cbcb4fa 3558 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3559 /* sign extend LI */
76a66253 3560#if defined(TARGET_PPC64)
d9bce9d9
JM		 3561 if (ctx->sf_mode)
3562 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3563 else
76a66253 3564#endif
d9bce9d9 3565 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3566 if (likely(AA(ctx->opcode) == 0))
046d6672 3567 target = ctx->nip + li - 4;
79aceca5 3568 else
9a64fbe4 3569 target = li;
e1833e1f
JM		 3570 if (LK(ctx->opcode))
3571 gen_setlr(ctx, ctx->nip);
c1942362 3572 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3573}
3574
e98a6e40
FB		 3575#define BCOND_IM 0
3576#define BCOND_LR 1
3577#define BCOND_CTR 2
3578
b068d6a7 3579static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3580{
d9bce9d9 3581 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3582 int l1 = gen_new_label();
3583 TCGv target;
e98a6e40 3584
8cbcb4fa 3585 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812 3586 if (type == BCOND_LR || type == BCOND_CTR) {
a7812ae4 3587 target = tcg_temp_local_new();
a2ffb812
AJ		 3588 if (type == BCOND_CTR)
3589 tcg_gen_mov_tl(target, cpu_ctr);
3590 else
3591 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3592 }
e1833e1f
JM		 3593 if (LK(ctx->opcode))
3594 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3595 l1 = gen_new_label();
3596 if ((bo & 0x4) == 0) {
3597 /* Decrement and test CTR */
a7812ae4 3598 TCGv temp = tcg_temp_new();
a2ffb812 3599 if (unlikely(type == BCOND_CTR)) {
e06fcd75 3600 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
a2ffb812
AJ		 3601 return;
3602 }
3603 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3604#if defined(TARGET_PPC64)
a2ffb812
AJ		 3605 if (!ctx->sf_mode)
3606 tcg_gen_ext32u_tl(temp, cpu_ctr);
3607 else
d9bce9d9 3608#endif
a2ffb812
AJ		 3609 tcg_gen_mov_tl(temp, cpu_ctr);
3610 if (bo & 0x2) {
3611 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3612 } else {
3613 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3614 }
a7812ae4 3615 tcg_temp_free(temp);
a2ffb812
AJ		 3616 }
3617 if ((bo & 0x10) == 0) {
3618 /* Test CR */
3619 uint32_t bi = BI(ctx->opcode);
3620 uint32_t mask = 1 << (3 - (bi & 0x03));
a7812ae4 3621 TCGv_i32 temp = tcg_temp_new_i32();
a2ffb812 3622
d9bce9d9 3623 if (bo & 0x8) {
a2ffb812
AJ		 3624 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3625 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3626 } else {
a2ffb812
AJ		 3627 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3628 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9 3629 }
a7812ae4 3630 tcg_temp_free_i32(temp);
d9bce9d9 3631 }
e98a6e40 3632 if (type == BCOND_IM) {
a2ffb812
AJ		 3633 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3634 if (likely(AA(ctx->opcode) == 0)) {
3635 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3636 } else {
3637 gen_goto_tb(ctx, 0, li);
3638 }
c53be334 3639 gen_set_label(l1);
c1942362 3640 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3641 } else {
d9bce9d9 3642#if defined(TARGET_PPC64)
a2ffb812
AJ		 3643 if (!(ctx->sf_mode))
3644 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3645 else
3646#endif
3647 tcg_gen_andi_tl(cpu_nip, target, ~3);
3648 tcg_gen_exit_tb(0);
3649 gen_set_label(l1);
3650#if defined(TARGET_PPC64)
3651 if (!(ctx->sf_mode))
3652 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3653 else
3654#endif
a2ffb812 3655 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3656 tcg_gen_exit_tb(0);
08e46e54 3657 }
e98a6e40
FB		 3658}
3659
3660GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3661{
e98a6e40
FB		 3662 gen_bcond(ctx, BCOND_IM);
3663}
3664
3665GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3666{
e98a6e40
FB		 3667 gen_bcond(ctx, BCOND_CTR);
3668}
3669
3670GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3671{
e98a6e40
FB		 3672 gen_bcond(ctx, BCOND_LR);
3673}
79aceca5
FB		 3674
3675/*** Condition register logical ***/
e1571908
AJ		 3676#define GEN_CRLOGIC(name, tcg_op, opc) \
3677GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3678{ \
fc0d441e
JM		 3679 uint8_t bitmask; \
3680 int sh; \
a7812ae4 3681 TCGv_i32 t0, t1; \
fc0d441e 3682 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
a7812ae4 3683 t0 = tcg_temp_new_i32(); \
fc0d441e 3684 if (sh > 0) \
fea0c503 3685 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3686 else if (sh < 0) \
fea0c503 3687 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3688 else \
fea0c503 3689 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
a7812ae4 3690 t1 = tcg_temp_new_i32(); \
fc0d441e
JM		 3691 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3692 if (sh > 0) \
fea0c503 3693 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3694 else if (sh < 0) \
fea0c503 3695 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3696 else \
fea0c503
AJ		 3697 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3698 tcg_op(t0, t0, t1); \
fc0d441e 3699 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3700 tcg_gen_andi_i32(t0, t0, bitmask); \
3701 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3702 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
a7812ae4
PB		 3703 tcg_temp_free_i32(t0); \
3704 tcg_temp_free_i32(t1); \
79aceca5
FB		 3705}
3706
3707/* crand */
e1571908 3708GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3709/* crandc */
e1571908 3710GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3711/* creqv */
e1571908 3712GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3713/* crnand */
e1571908 3714GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3715/* crnor */
e1571908 3716GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3717/* cror */
e1571908 3718GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3719/* crorc */
e1571908 3720GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3721/* crxor */
e1571908 3722GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3723/* mcrf */
3724GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3725{
47e4661c 3726 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3727}
3728
3729/*** System linkage ***/
76db3ba4 3730/* rfi (mem_idx only) */
76a66253 3731GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3732{
9a64fbe4 3733#if defined(CONFIG_USER_ONLY)
e06fcd75 3734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4
FB		 3735#else
3736 /* Restore CPU state */
76db3ba4 3737 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3738 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 3739 return;
9a64fbe4 3740 }
d72a19f7 3741 gen_helper_rfi();
e06fcd75 3742 gen_sync_exception(ctx);
9a64fbe4 3743#endif
79aceca5
FB		 3744}
3745
426613db 3746#if defined(TARGET_PPC64)
a750fc0b 3747GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3748{
3749#if defined(CONFIG_USER_ONLY)
e06fcd75 3750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3751#else
3752 /* Restore CPU state */
76db3ba4 3753 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 3755 return;
3756 }
d72a19f7 3757 gen_helper_rfid();
e06fcd75 3758 gen_sync_exception(ctx);
426613db
JM		 3759#endif
3760}
426613db 3761
5b8105fa 3762GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3763{
3764#if defined(CONFIG_USER_ONLY)
e06fcd75 3765 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3766#else
3767 /* Restore CPU state */
76db3ba4 3768 if (unlikely(ctx->mem_idx <= 1)) {
e06fcd75 3769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
be147d08
JM		 3770 return;
3771 }
d72a19f7 3772 gen_helper_hrfid();
e06fcd75 3773 gen_sync_exception(ctx);
be147d08
JM		 3774#endif
3775}
3776#endif
3777
79aceca5 3778/* sc */
417bf010
JM		 3779#if defined(CONFIG_USER_ONLY)
3780#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3781#else
3782#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3783#endif
e1833e1f 3784GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3785{
e1833e1f
JM		 3786 uint32_t lev;
3787
3788 lev = (ctx->opcode >> 5) & 0x7F;
e06fcd75 3789 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3790}
3791
3792/*** Trap ***/
3793/* tw */
76a66253 3794GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3795{
cab3bee2 3796 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
a0ae05aa 3797 /* Update the nip since this might generate a trap exception */
d9bce9d9 3798 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3799 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3800 tcg_temp_free_i32(t0);
79aceca5
FB		 3801}
3802
3803/* twi */
3804GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3805{
cab3bee2
AJ		 3806 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3807 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3808 /* Update the nip since this might generate a trap exception */
3809 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3810 gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
3811 tcg_temp_free(t0);
3812 tcg_temp_free_i32(t1);
79aceca5
FB		 3813}
3814
d9bce9d9
JM		 3815#if defined(TARGET_PPC64)
3816/* td */
3817GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3818{
cab3bee2 3819 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3820 /* Update the nip since this might generate a trap exception */
3821 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3822 gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
3823 tcg_temp_free_i32(t0);
d9bce9d9
JM		 3824}
3825
3826/* tdi */
3827GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3828{
cab3bee2
AJ		 3829 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3830 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
d9bce9d9
JM		 3831 /* Update the nip since this might generate a trap exception */
3832 gen_update_nip(ctx, ctx->nip);
cab3bee2
AJ		 3833 gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
3834 tcg_temp_free(t0);
3835 tcg_temp_free_i32(t1);
d9bce9d9
JM		 3836}
3837#endif
3838
79aceca5 3839/*** Processor control ***/
79aceca5
FB		 3840/* mcrxr */
3841GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3842{
3d7b417e
AJ		 3843 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3844 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3845 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3846}
3847
0cfe11ea 3848/* mfcr mfocrf */
76a66253 3849GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3850{
76a66253 3851 uint32_t crm, crn;
3b46e624 3852
76a66253
JM		 3853 if (likely(ctx->opcode & 0x00100000)) {
3854 crm = CRM(ctx->opcode);
8dd640e4 3855 if (likely(crm && ((crm & (crm - 1)) == 0))) {
0cfe11ea 3856 crn = ctz32 (crm);
e1571908 3857 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
0497d2f4
AJ		 3858 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3859 cpu_gpr[rD(ctx->opcode)], crn * 4);
76a66253 3860 }
d9bce9d9 3861 } else {
651721b2
AJ		 3862 TCGv_i32 t0 = tcg_temp_new_i32();
3863 tcg_gen_mov_i32(t0, cpu_crf[0]);
3864 tcg_gen_shli_i32(t0, t0, 4);
3865 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3866 tcg_gen_shli_i32(t0, t0, 4);
3867 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3868 tcg_gen_shli_i32(t0, t0, 4);
3869 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3870 tcg_gen_shli_i32(t0, t0, 4);
3871 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3872 tcg_gen_shli_i32(t0, t0, 4);
3873 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3874 tcg_gen_shli_i32(t0, t0, 4);
3875 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3876 tcg_gen_shli_i32(t0, t0, 4);
3877 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3878 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3879 tcg_temp_free_i32(t0);
d9bce9d9 3880 }
79aceca5
FB		 3881}
3882
3883/* mfmsr */
3884GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3885{
9a64fbe4 3886#if defined(CONFIG_USER_ONLY)
e06fcd75 3887 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 3888#else
76db3ba4 3889 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 3891 return;
9a64fbe4 3892 }
6527f6ea 3893 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
9a64fbe4 3894#endif
79aceca5
FB		 3895}
3896
a11b8151 3897#if 1
6f2d8978 3898#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3899#else
3900static void spr_noaccess (void *opaque, int sprn)
3901{
3902 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3903 printf("ERROR: try to access SPR %d !\n", sprn);
3904}
3905#define SPR_NOACCESS (&spr_noaccess)
3906#endif
3907
79aceca5 3908/* mfspr */
b068d6a7 3909static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3910{
45d827d2 3911 void (*read_cb)(void *opaque, int gprn, int sprn);
79aceca5
FB		 3912 uint32_t sprn = SPR(ctx->opcode);
3913
3fc6c082 3914#if !defined(CONFIG_USER_ONLY)
76db3ba4 3915 if (ctx->mem_idx == 2)
be147d08 3916 read_cb = ctx->spr_cb[sprn].hea_read;
76db3ba4 3917 else if (ctx->mem_idx)
3fc6c082
FB		 3918 read_cb = ctx->spr_cb[sprn].oea_read;
3919 else
9a64fbe4 3920#endif
3fc6c082 3921 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3922 if (likely(read_cb != NULL)) {
3923 if (likely(read_cb != SPR_NOACCESS)) {
45d827d2 3924 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3fc6c082
FB		 3925 } else {
3926 /* Privilege exception */
9fceefa7
JM		 3927 /* This is a hack to avoid warnings when running Linux:
3928 * this OS breaks the PowerPC virtualisation model,
3929 * allowing userland application to read the PVR
3930 */
3931 if (sprn != SPR_PVR) {
93fcfe39 3932 qemu_log("Trying to read privileged spr %d %03x at "
077fc206 3933 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3934 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3935 sprn, sprn, ctx->nip);
f24e5695 3936 }
e06fcd75 3937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
79aceca5 3938 }
3fc6c082
FB		 3939 } else {
3940 /* Not defined */
93fcfe39 3941 qemu_log("Trying to read invalid spr %d %03x at "
077fc206 3942 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 3943 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3944 sprn, sprn, ctx->nip);
e06fcd75 3945 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 3946 }
79aceca5
FB		 3947}
3948
3fc6c082 3949GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3950{
3fc6c082 3951 gen_op_mfspr(ctx);
76a66253 3952}
3fc6c082
FB		 3953
3954/* mftb */
a750fc0b 3955GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3956{
3957 gen_op_mfspr(ctx);
79aceca5
FB		 3958}
3959
0cfe11ea 3960/* mtcrf mtocrf*/
8dd4983c 3961GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3962{
76a66253 3963 uint32_t crm, crn;
3b46e624 3964
76a66253 3965 crm = CRM(ctx->opcode);
8dd640e4 3966 if (likely((ctx->opcode & 0x00100000))) {
3967 if (crm && ((crm & (crm - 1)) == 0)) {
3968 TCGv_i32 temp = tcg_temp_new_i32();
0cfe11ea 3969 crn = ctz32 (crm);
8dd640e4 3970 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
0cfe11ea
AJ		 3971 tcg_gen_shri_i32(temp, temp, crn * 4);
3972 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
8dd640e4 3973 tcg_temp_free_i32(temp);
3974 }
76a66253 3975 } else {
651721b2
AJ		 3976 TCGv_i32 temp = tcg_temp_new_i32();
3977 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3978 for (crn = 0 ; crn < 8 ; crn++) {
3979 if (crm & (1 << crn)) {
3980 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3981 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3982 }
3983 }
a7812ae4 3984 tcg_temp_free_i32(temp);
76a66253 3985 }
79aceca5
FB		 3986}
3987
3988/* mtmsr */
426613db 3989#if defined(TARGET_PPC64)
be147d08 3990GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3991{
3992#if defined(CONFIG_USER_ONLY)
e06fcd75 3993 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db 3994#else
76db3ba4 3995 if (unlikely(!ctx->mem_idx)) {
e06fcd75 3996 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
426613db
JM		 3997 return;
3998 }
be147d08
JM		 3999 if (ctx->opcode & 0x00010000) {
4000 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4001 TCGv t0 = tcg_temp_new();
4002 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4003 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4004 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4005 tcg_temp_free(t0);
be147d08 4006 } else {
056b05f8
JM		 4007 /* XXX: we need to update nip before the store
4008 * if we enter power saving mode, we will exit the loop
4009 * directly from ppc_store_msr
4010 */
be147d08 4011 gen_update_nip(ctx, ctx->nip);
6527f6ea 4012 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 4013 /* Must stop the translation as machine state (may have) changed */
4014 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4015 gen_stop_exception(ctx);
be147d08 4016 }
426613db
JM		 4017#endif
4018}
4019#endif
4020
79aceca5
FB		 4021GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
4022{
9a64fbe4 4023#if defined(CONFIG_USER_ONLY)
e06fcd75 4024 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4025#else
76db3ba4 4026 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4027 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4028 return;
9a64fbe4 4029 }
be147d08
JM		 4030 if (ctx->opcode & 0x00010000) {
4031 /* Special form that does not need any synchronisation */
6527f6ea
AJ		 4032 TCGv t0 = tcg_temp_new();
4033 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4034 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4035 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4036 tcg_temp_free(t0);
be147d08 4037 } else {
056b05f8
JM		 4038 /* XXX: we need to update nip before the store
4039 * if we enter power saving mode, we will exit the loop
4040 * directly from ppc_store_msr
4041 */
be147d08 4042 gen_update_nip(ctx, ctx->nip);
d9bce9d9 4043#if defined(TARGET_PPC64)
6527f6ea
AJ		 4044 if (!ctx->sf_mode) {
4045 TCGv t0 = tcg_temp_new();
4046 TCGv t1 = tcg_temp_new();
4047 tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL);
4048 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
4049 tcg_gen_or_tl(t0, t0, t1);
4050 tcg_temp_free(t1);
4051 gen_helper_store_msr(t0);
4052 tcg_temp_free(t0);
4053 } else
d9bce9d9 4054#endif
6527f6ea 4055 gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]);
be147d08 4056 /* Must stop the translation as machine state (may have) changed */
6527f6ea 4057 /* Note that mtmsr is not always defined as context-synchronizing */
e06fcd75 4058 gen_stop_exception(ctx);
be147d08 4059 }
9a64fbe4 4060#endif
79aceca5
FB		 4061}
4062
4063/* mtspr */
4064GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
4065{
45d827d2 4066 void (*write_cb)(void *opaque, int sprn, int gprn);
79aceca5
FB		 4067 uint32_t sprn = SPR(ctx->opcode);
4068
3fc6c082 4069#if !defined(CONFIG_USER_ONLY)
76db3ba4 4070 if (ctx->mem_idx == 2)
be147d08 4071 write_cb = ctx->spr_cb[sprn].hea_write;
76db3ba4 4072 else if (ctx->mem_idx)
3fc6c082
FB		 4073 write_cb = ctx->spr_cb[sprn].oea_write;
4074 else
9a64fbe4 4075#endif
3fc6c082 4076 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4077 if (likely(write_cb != NULL)) {
4078 if (likely(write_cb != SPR_NOACCESS)) {
45d827d2 4079 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3fc6c082
FB		 4080 } else {
4081 /* Privilege exception */
93fcfe39 4082 qemu_log("Trying to write privileged spr %d %03x at "
077fc206 4083 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 4084 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4085 sprn, sprn, ctx->nip);
e06fcd75 4086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 4087 }
3fc6c082
FB		 4088 } else {
4089 /* Not defined */
93fcfe39 4090 qemu_log("Trying to write invalid spr %d %03x at "
077fc206 4091 ADDRX "\n", sprn, sprn, ctx->nip);
077fc206
JM		 4092 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4093 sprn, sprn, ctx->nip);
e06fcd75 4094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
79aceca5 4095 }
79aceca5
FB		 4096}
4097
4098/*** Cache management ***/
79aceca5 4099/* dcbf */
0db1b20e 4100GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4101{
dac454af 4102 /* XXX: specification says this is treated as a load by the MMU */
76db3ba4
AJ		 4103 TCGv t0;
4104 gen_set_access_type(ctx, ACCESS_CACHE);
4105 t0 = tcg_temp_new();
4106 gen_addr_reg_index(ctx, t0);
4107 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4108 tcg_temp_free(t0);
79aceca5
FB		 4109}
4110
4111/* dcbi (Supervisor only) */
9a64fbe4 4112GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4113{
a541f297 4114#if defined(CONFIG_USER_ONLY)
e06fcd75 4115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a541f297 4116#else
b61f2753 4117 TCGv EA, val;
76db3ba4 4118 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4119 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4120 return;
9a64fbe4 4121 }
a7812ae4 4122 EA = tcg_temp_new();
76db3ba4
AJ		 4123 gen_set_access_type(ctx, ACCESS_CACHE);
4124 gen_addr_reg_index(ctx, EA);
a7812ae4 4125 val = tcg_temp_new();
76a66253 4126 /* XXX: specification says this should be treated as a store by the MMU */
76db3ba4
AJ		 4127 gen_qemu_ld8u(ctx, val, EA);
4128 gen_qemu_st8(ctx, val, EA);
b61f2753
AJ		 4129 tcg_temp_free(val);
4130 tcg_temp_free(EA);
a541f297 4131#endif
79aceca5
FB		 4132}
4133
4134/* dcdst */
9a64fbe4 4135GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4136{
76a66253 4137 /* XXX: specification say this is treated as a load by the MMU */
76db3ba4
AJ		 4138 TCGv t0;
4139 gen_set_access_type(ctx, ACCESS_CACHE);
4140 t0 = tcg_temp_new();
4141 gen_addr_reg_index(ctx, t0);
4142 gen_qemu_ld8u(ctx, t0, t0);
fea0c503 4143 tcg_temp_free(t0);
79aceca5
FB		 4144}
4145
4146/* dcbt */
0db1b20e 4147GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4148{
0db1b20e 4149 /* interpreted as no-op */
76a66253
JM		 4150 /* XXX: specification say this is treated as a load by the MMU
4151 * but does not generate any exception
4152 */
79aceca5
FB		 4153}
4154
4155/* dcbtst */
0db1b20e 4156GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4157{
0db1b20e 4158 /* interpreted as no-op */
76a66253
JM		 4159 /* XXX: specification say this is treated as a load by the MMU
4160 * but does not generate any exception
4161 */
79aceca5
FB		 4162}
4163
4164/* dcbz */
d63001d1 4165GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4166{
76db3ba4
AJ		 4167 TCGv t0;
4168 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4169 /* NIP cannot be restored if the memory exception comes from an helper */
4170 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4171 t0 = tcg_temp_new();
4172 gen_addr_reg_index(ctx, t0);
799a8c8d
AJ		 4173 gen_helper_dcbz(t0);
4174 tcg_temp_free(t0);
d63001d1
JM		 4175}
4176
c7697e1f 4177GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4178{
76db3ba4
AJ		 4179 TCGv t0;
4180 gen_set_access_type(ctx, ACCESS_CACHE);
799a8c8d
AJ		 4181 /* NIP cannot be restored if the memory exception comes from an helper */
4182 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4183 t0 = tcg_temp_new();
4184 gen_addr_reg_index(ctx, t0);
d63001d1 4185 if (ctx->opcode & 0x00200000)
799a8c8d 4186 gen_helper_dcbz(t0);
d63001d1 4187 else
799a8c8d
AJ		 4188 gen_helper_dcbz_970(t0);
4189 tcg_temp_free(t0);
79aceca5
FB		 4190}
4191
ae1c1a3d
AJ		 4192/* dst / dstt */
4193GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC)
4194{
4195 if (rA(ctx->opcode) == 0) {
4196 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4197 } else {
4198 /* interpreted as no-op */
4199 }
4200}
4201
4202/* dstst /dststt */
4203GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC)
4204{
4205 if (rA(ctx->opcode) == 0) {
4206 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4207 } else {
4208 /* interpreted as no-op */
4209 }
4210
4211}
4212
4213/* dss / dssall */
4214GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC)
4215{
4216 /* interpreted as no-op */
4217}
4218
79aceca5 4219/* icbi */
1b413d55 4220GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4221{
76db3ba4
AJ		 4222 TCGv t0;
4223 gen_set_access_type(ctx, ACCESS_CACHE);
30032c94
JM		 4224 /* NIP cannot be restored if the memory exception comes from an helper */
4225 gen_update_nip(ctx, ctx->nip - 4);
76db3ba4
AJ		 4226 t0 = tcg_temp_new();
4227 gen_addr_reg_index(ctx, t0);
37d269df
AJ		 4228 gen_helper_icbi(t0);
4229 tcg_temp_free(t0);
79aceca5
FB		 4230}
4231
4232/* Optional: */
4233/* dcba */
a750fc0b 4234GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4235{
0db1b20e
JM		 4236 /* interpreted as no-op */
4237 /* XXX: specification say this is treated as a store by the MMU
4238 * but does not generate any exception
4239 */
79aceca5
FB		 4240}
4241
4242/*** Segment register manipulation ***/
4243/* Supervisor only: */
4244/* mfsr */
4245GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4246{
9a64fbe4 4247#if defined(CONFIG_USER_ONLY)
e06fcd75 4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4249#else
74d37793 4250 TCGv t0;
76db3ba4 4251 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4253 return;
9a64fbe4 4254 }
74d37793
AJ		 4255 t0 = tcg_const_tl(SR(ctx->opcode));
4256 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4257 tcg_temp_free(t0);
9a64fbe4 4258#endif
79aceca5
FB		 4259}
4260
4261/* mfsrin */
9a64fbe4 4262GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4263{
9a64fbe4 4264#if defined(CONFIG_USER_ONLY)
e06fcd75 4265 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4266#else
74d37793 4267 TCGv t0;
76db3ba4 4268 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4269 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4270 return;
9a64fbe4 4271 }
74d37793
AJ		 4272 t0 = tcg_temp_new();
4273 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4274 tcg_gen_andi_tl(t0, t0, 0xF);
4275 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
4276 tcg_temp_free(t0);
9a64fbe4 4277#endif
79aceca5
FB		 4278}
4279
4280/* mtsr */
e63c59cb 4281GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4282{
9a64fbe4 4283#if defined(CONFIG_USER_ONLY)
e06fcd75 4284 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4285#else
74d37793 4286 TCGv t0;
76db3ba4 4287 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4289 return;
9a64fbe4 4290 }
74d37793
AJ		 4291 t0 = tcg_const_tl(SR(ctx->opcode));
4292 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
4293 tcg_temp_free(t0);
9a64fbe4 4294#endif
79aceca5
FB		 4295}
4296
4297/* mtsrin */
9a64fbe4 4298GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4299{
9a64fbe4 4300#if defined(CONFIG_USER_ONLY)
e06fcd75 4301 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9a64fbe4 4302#else
74d37793 4303 TCGv t0;
76db3ba4 4304 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4305 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
9fddaa0c 4306 return;
9a64fbe4 4307 }
74d37793
AJ		 4308 t0 = tcg_temp_new();
4309 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4310 tcg_gen_andi_tl(t0, t0, 0xF);
4311 gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]);
4312 tcg_temp_free(t0);
9a64fbe4 4313#endif
79aceca5
FB		 4314}
4315
12de9a39
JM		 4316#if defined(TARGET_PPC64)
4317/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4318/* mfsr */
c7697e1f 4319GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4320{
4321#if defined(CONFIG_USER_ONLY)
e06fcd75 4322 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4323#else
74d37793 4324 TCGv t0;
76db3ba4 4325 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4327 return;
4328 }
74d37793 4329 t0 = tcg_const_tl(SR(ctx->opcode));
f6b868fc 4330 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
74d37793 4331 tcg_temp_free(t0);
12de9a39
JM		 4332#endif
4333}
4334
4335/* mfsrin */
c7697e1f
JM		 4336GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4337 PPC_SEGMENT_64B)
12de9a39
JM		 4338{
4339#if defined(CONFIG_USER_ONLY)
e06fcd75 4340 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4341#else
74d37793 4342 TCGv t0;
76db3ba4 4343 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4345 return;
4346 }
74d37793
AJ		 4347 t0 = tcg_temp_new();
4348 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4349 tcg_gen_andi_tl(t0, t0, 0xF);
f6b868fc 4350 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0);
74d37793 4351 tcg_temp_free(t0);
12de9a39
JM		 4352#endif
4353}
4354
4355/* mtsr */
c7697e1f 4356GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4357{
4358#if defined(CONFIG_USER_ONLY)
e06fcd75 4359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4360#else
74d37793 4361 TCGv t0;
76db3ba4 4362 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4363 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4364 return;
4365 }
74d37793 4366 t0 = tcg_const_tl(SR(ctx->opcode));
f6b868fc 4367 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4368 tcg_temp_free(t0);
12de9a39
JM		 4369#endif
4370}
4371
4372/* mtsrin */
c7697e1f
JM		 4373GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4374 PPC_SEGMENT_64B)
12de9a39
JM		 4375{
4376#if defined(CONFIG_USER_ONLY)
e06fcd75 4377 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39 4378#else
74d37793 4379 TCGv t0;
76db3ba4 4380 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4381 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
12de9a39
JM		 4382 return;
4383 }
74d37793
AJ		 4384 t0 = tcg_temp_new();
4385 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4386 tcg_gen_andi_tl(t0, t0, 0xF);
f6b868fc 4387 gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]);
74d37793 4388 tcg_temp_free(t0);
12de9a39
JM		 4389#endif
4390}
f6b868fc
BS		 4391
4392/* slbmte */
4393GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B)
4394{
4395#if defined(CONFIG_USER_ONLY)
4396 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4397#else
4398 if (unlikely(!ctx->mem_idx)) {
4399 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4400 return;
4401 }
4402 gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
4403#endif
4404}
4405
12de9a39
JM		 4406#endif /* defined(TARGET_PPC64) */
4407
79aceca5 4408/*** Lookaside buffer management ***/
76db3ba4 4409/* Optional & mem_idx only: */
79aceca5 4410/* tlbia */
3fc6c082 4411GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4412{
9a64fbe4 4413#if defined(CONFIG_USER_ONLY)
e06fcd75 4414 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4415#else
76db3ba4 4416 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4417 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4418 return;
9a64fbe4 4419 }
74d37793 4420 gen_helper_tlbia();
9a64fbe4 4421#endif
79aceca5
FB		 4422}
4423
bf14b1ce
BS		 4424/* tlbiel */
4425GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE)
4426{
4427#if defined(CONFIG_USER_ONLY)
4428 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4429#else
4430 if (unlikely(!ctx->mem_idx)) {
4431 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4432 return;
4433 }
4434 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
4435#endif
4436}
4437
79aceca5 4438/* tlbie */
76a66253 4439GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4440{
9a64fbe4 4441#if defined(CONFIG_USER_ONLY)
e06fcd75 4442 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4443#else
76db3ba4 4444 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4445 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4446 return;
9a64fbe4 4447 }
d9bce9d9 4448#if defined(TARGET_PPC64)
74d37793
AJ		 4449 if (!ctx->sf_mode) {
4450 TCGv t0 = tcg_temp_new();
4451 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4452 gen_helper_tlbie(t0);
4453 tcg_temp_free(t0);
4454 } else
d9bce9d9 4455#endif
74d37793 4456 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
9a64fbe4 4457#endif
79aceca5
FB		 4458}
4459
4460/* tlbsync */
76a66253 4461GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4462{
9a64fbe4 4463#if defined(CONFIG_USER_ONLY)
e06fcd75 4464 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9a64fbe4 4465#else
76db3ba4 4466 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4467 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
9fddaa0c 4468 return;
9a64fbe4
FB		 4469 }
4470 /* This has no effect: it should ensure that all previous
4471 * tlbie have completed
4472 */
e06fcd75 4473 gen_stop_exception(ctx);
9a64fbe4 4474#endif
79aceca5
FB		 4475}
4476
426613db
JM		 4477#if defined(TARGET_PPC64)
4478/* slbia */
4479GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4480{
4481#if defined(CONFIG_USER_ONLY)
e06fcd75 4482 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4483#else
76db3ba4 4484 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4485 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4486 return;
4487 }
74d37793 4488 gen_helper_slbia();
426613db
JM		 4489#endif
4490}
4491
4492/* slbie */
4493GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4494{
4495#if defined(CONFIG_USER_ONLY)
e06fcd75 4496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db 4497#else
76db3ba4 4498 if (unlikely(!ctx->mem_idx)) {
e06fcd75 4499 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
426613db
JM		 4500 return;
4501 }
74d37793 4502 gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]);
426613db
JM		 4503#endif
4504}
4505#endif
4506
79aceca5
FB		 4507/*** External control ***/
4508/* Optional: */
111bfab3 4509/* eciwx */
79aceca5
FB		 4510GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4511{
76db3ba4 4512 TCGv t0;
fa407c03 4513 /* Should check EAR[E] ! */
76db3ba4
AJ		 4514 gen_set_access_type(ctx, ACCESS_EXT);
4515 t0 = tcg_temp_new();
4516 gen_addr_reg_index(ctx, t0);
fa407c03 4517 gen_check_align(ctx, t0, 0x03);
76db3ba4 4518 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4519 tcg_temp_free(t0);
76a66253
JM		 4520}
4521
4522/* ecowx */
4523GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4524{
76db3ba4 4525 TCGv t0;
fa407c03 4526 /* Should check EAR[E] ! */
76db3ba4
AJ		 4527 gen_set_access_type(ctx, ACCESS_EXT);
4528 t0 = tcg_temp_new();
4529 gen_addr_reg_index(ctx, t0);
fa407c03 4530 gen_check_align(ctx, t0, 0x03);
76db3ba4 4531 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
fa407c03 4532 tcg_temp_free(t0);
76a66253
JM		 4533}
4534
4535/* PowerPC 601 specific instructions */
4536/* abs - abs. */
4537GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4538{
22e0e173
AJ		 4539 int l1 = gen_new_label();
4540 int l2 = gen_new_label();
4541 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4542 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4543 tcg_gen_br(l2);
4544 gen_set_label(l1);
4545 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4546 gen_set_label(l2);
76a66253 4547 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4548 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4549}
4550
4551/* abso - abso. */
4552GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4553{
22e0e173
AJ		 4554 int l1 = gen_new_label();
4555 int l2 = gen_new_label();
4556 int l3 = gen_new_label();
4557 /* Start with XER OV disabled, the most likely case */
4558 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4559 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4560 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4561 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4562 tcg_gen_br(l2);
4563 gen_set_label(l1);
4564 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4565 tcg_gen_br(l3);
4566 gen_set_label(l2);
4567 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4568 gen_set_label(l3);
76a66253 4569 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4570 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4571}
4572
4573/* clcs */
a750fc0b 4574GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4575{
22e0e173
AJ		 4576 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4577 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0);
4578 tcg_temp_free_i32(t0);
c7697e1f 4579 /* Rc=1 sets CR0 to an undefined state */
76a66253
JM		 4580}
4581
4582/* div - div. */
4583GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4584{
22e0e173 4585 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4586 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4587 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4588}
4589
4590/* divo - divo. */
4591GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4592{
22e0e173 4593 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4594 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4595 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4596}
4597
4598/* divs - divs. */
4599GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4600{
22e0e173 4601 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4602 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4603 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4604}
4605
4606/* divso - divso. */
4607GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4608{
22e0e173 4609 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253 4610 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4611 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4612}
4613
4614/* doz - doz. */
4615GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4616{
22e0e173
AJ		 4617 int l1 = gen_new_label();
4618 int l2 = gen_new_label();
4619 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4620 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4621 tcg_gen_br(l2);
4622 gen_set_label(l1);
4623 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4624 gen_set_label(l2);
76a66253 4625 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4626 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4627}
4628
4629/* dozo - dozo. */
4630GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4631{
22e0e173
AJ		 4632 int l1 = gen_new_label();
4633 int l2 = gen_new_label();
4634 TCGv t0 = tcg_temp_new();
4635 TCGv t1 = tcg_temp_new();
4636 TCGv t2 = tcg_temp_new();
4637 /* Start with XER OV disabled, the most likely case */
4638 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4639 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4640 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4641 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4642 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4643 tcg_gen_andc_tl(t1, t1, t2);
4644 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4645 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4646 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4647 tcg_gen_br(l2);
4648 gen_set_label(l1);
4649 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4650 gen_set_label(l2);
4651 tcg_temp_free(t0);
4652 tcg_temp_free(t1);
4653 tcg_temp_free(t2);
76a66253 4654 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4655 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4656}
4657
4658/* dozi */
4659GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4660{
22e0e173
AJ		 4661 target_long simm = SIMM(ctx->opcode);
4662 int l1 = gen_new_label();
4663 int l2 = gen_new_label();
4664 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4665 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4666 tcg_gen_br(l2);
4667 gen_set_label(l1);
4668 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4669 gen_set_label(l2);
4670 if (unlikely(Rc(ctx->opcode) != 0))
4671 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4672}
4673
76a66253
JM		 4674/* lscbx - lscbx. */
4675GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4676{
bdb4b689
AJ		 4677 TCGv t0 = tcg_temp_new();
4678 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4679 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4680 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
76a66253 4681
76db3ba4 4682 gen_addr_reg_index(ctx, t0);
76a66253 4683 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4684 gen_update_nip(ctx, ctx->nip - 4);
bdb4b689
AJ		 4685 gen_helper_lscbx(t0, t0, t1, t2, t3);
4686 tcg_temp_free_i32(t1);
4687 tcg_temp_free_i32(t2);
4688 tcg_temp_free_i32(t3);
3d7b417e 4689 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
bdb4b689 4690 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
76a66253 4691 if (unlikely(Rc(ctx->opcode) != 0))
bdb4b689
AJ		 4692 gen_set_Rc0(ctx, t0);
4693 tcg_temp_free(t0);
76a66253
JM		 4694}
4695
4696/* maskg - maskg. */
4697GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4698{
22e0e173
AJ		 4699 int l1 = gen_new_label();
4700 TCGv t0 = tcg_temp_new();
4701 TCGv t1 = tcg_temp_new();
4702 TCGv t2 = tcg_temp_new();
4703 TCGv t3 = tcg_temp_new();
4704 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4705 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4706 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4707 tcg_gen_addi_tl(t2, t0, 1);
4708 tcg_gen_shr_tl(t2, t3, t2);
4709 tcg_gen_shr_tl(t3, t3, t1);
4710 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4711 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4712 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4713 gen_set_label(l1);
4714 tcg_temp_free(t0);
4715 tcg_temp_free(t1);
4716 tcg_temp_free(t2);
4717 tcg_temp_free(t3);
76a66253 4718 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4719 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4720}
4721
4722/* maskir - maskir. */
4723GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4724{
22e0e173
AJ		 4725 TCGv t0 = tcg_temp_new();
4726 TCGv t1 = tcg_temp_new();
4727 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4728 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4729 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4730 tcg_temp_free(t0);
4731 tcg_temp_free(t1);
76a66253 4732 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4733 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4734}
4735
4736/* mul - mul. */
4737GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4738{
22e0e173
AJ		 4739 TCGv_i64 t0 = tcg_temp_new_i64();
4740 TCGv_i64 t1 = tcg_temp_new_i64();
4741 TCGv t2 = tcg_temp_new();
4742 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4743 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4744 tcg_gen_mul_i64(t0, t0, t1);
4745 tcg_gen_trunc_i64_tl(t2, t0);
4746 gen_store_spr(SPR_MQ, t2);
4747 tcg_gen_shri_i64(t1, t0, 32);
4748 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4749 tcg_temp_free_i64(t0);
4750 tcg_temp_free_i64(t1);
4751 tcg_temp_free(t2);
76a66253 4752 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4753 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4754}
4755
4756/* mulo - mulo. */
4757GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4758{
22e0e173
AJ		 4759 int l1 = gen_new_label();
4760 TCGv_i64 t0 = tcg_temp_new_i64();
4761 TCGv_i64 t1 = tcg_temp_new_i64();
4762 TCGv t2 = tcg_temp_new();
4763 /* Start with XER OV disabled, the most likely case */
4764 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
4765 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4766 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4767 tcg_gen_mul_i64(t0, t0, t1);
4768 tcg_gen_trunc_i64_tl(t2, t0);
4769 gen_store_spr(SPR_MQ, t2);
4770 tcg_gen_shri_i64(t1, t0, 32);
4771 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4772 tcg_gen_ext32s_i64(t1, t0);
4773 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4774 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
4775 gen_set_label(l1);
4776 tcg_temp_free_i64(t0);
4777 tcg_temp_free_i64(t1);
4778 tcg_temp_free(t2);
76a66253 4779 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4780 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4781}
4782
4783/* nabs - nabs. */
4784GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4785{
22e0e173
AJ		 4786 int l1 = gen_new_label();
4787 int l2 = gen_new_label();
4788 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4789 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4790 tcg_gen_br(l2);
4791 gen_set_label(l1);
4792 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4793 gen_set_label(l2);
76a66253 4794 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4795 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4796}
4797
4798/* nabso - nabso. */
4799GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4800{
22e0e173
AJ		 4801 int l1 = gen_new_label();
4802 int l2 = gen_new_label();
4803 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4804 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4805 tcg_gen_br(l2);
4806 gen_set_label(l1);
4807 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4808 gen_set_label(l2);
4809 /* nabs never overflows */
4810 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
76a66253 4811 if (unlikely(Rc(ctx->opcode) != 0))
22e0e173 4812 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
76a66253
JM		 4813}
4814
4815/* rlmi - rlmi. */
4816GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4817{
7487953d
AJ		 4818 uint32_t mb = MB(ctx->opcode);
4819 uint32_t me = ME(ctx->opcode);
4820 TCGv t0 = tcg_temp_new();
4821 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4822 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4823 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4824 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4825 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4826 tcg_temp_free(t0);
76a66253 4827 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4828 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4829}
4830
4831/* rrib - rrib. */
4832GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4833{
7487953d
AJ		 4834 TCGv t0 = tcg_temp_new();
4835 TCGv t1 = tcg_temp_new();
4836 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4837 tcg_gen_movi_tl(t1, 0x80000000);
4838 tcg_gen_shr_tl(t1, t1, t0);
4839 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4840 tcg_gen_and_tl(t0, t0, t1);
4841 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4842 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4843 tcg_temp_free(t0);
4844 tcg_temp_free(t1);
76a66253 4845 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4846 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4847}
4848
4849/* sle - sle. */
4850GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4851{
7487953d
AJ		 4852 TCGv t0 = tcg_temp_new();
4853 TCGv t1 = tcg_temp_new();
4854 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4855 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4856 tcg_gen_subfi_tl(t1, 32, t1);
4857 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4858 tcg_gen_or_tl(t1, t0, t1);
4859 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4860 gen_store_spr(SPR_MQ, t1);
4861 tcg_temp_free(t0);
4862 tcg_temp_free(t1);
76a66253 4863 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4864 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4865}
4866
4867/* sleq - sleq. */
4868GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4869{
7487953d
AJ		 4870 TCGv t0 = tcg_temp_new();
4871 TCGv t1 = tcg_temp_new();
4872 TCGv t2 = tcg_temp_new();
4873 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4874 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4875 tcg_gen_shl_tl(t2, t2, t0);
4876 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4877 gen_load_spr(t1, SPR_MQ);
4878 gen_store_spr(SPR_MQ, t0);
4879 tcg_gen_and_tl(t0, t0, t2);
4880 tcg_gen_andc_tl(t1, t1, t2);
4881 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4882 tcg_temp_free(t0);
4883 tcg_temp_free(t1);
4884 tcg_temp_free(t2);
76a66253 4885 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4886 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4887}
4888
4889/* sliq - sliq. */
4890GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4891{
7487953d
AJ		 4892 int sh = SH(ctx->opcode);
4893 TCGv t0 = tcg_temp_new();
4894 TCGv t1 = tcg_temp_new();
4895 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4896 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4897 tcg_gen_or_tl(t1, t0, t1);
4898 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4899 gen_store_spr(SPR_MQ, t1);
4900 tcg_temp_free(t0);
4901 tcg_temp_free(t1);
76a66253 4902 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4903 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4904}
4905
4906/* slliq - slliq. */
4907GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4908{
7487953d
AJ		 4909 int sh = SH(ctx->opcode);
4910 TCGv t0 = tcg_temp_new();
4911 TCGv t1 = tcg_temp_new();
4912 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4913 gen_load_spr(t1, SPR_MQ);
4914 gen_store_spr(SPR_MQ, t0);
4915 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4916 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4917 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4918 tcg_temp_free(t0);
4919 tcg_temp_free(t1);
76a66253 4920 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4921 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4922}
4923
4924/* sllq - sllq. */
4925GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4926{
7487953d
AJ		 4927 int l1 = gen_new_label();
4928 int l2 = gen_new_label();
4929 TCGv t0 = tcg_temp_local_new();
4930 TCGv t1 = tcg_temp_local_new();
4931 TCGv t2 = tcg_temp_local_new();
4932 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4933 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4934 tcg_gen_shl_tl(t1, t1, t2);
4935 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4936 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4937 gen_load_spr(t0, SPR_MQ);
4938 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4939 tcg_gen_br(l2);
4940 gen_set_label(l1);
4941 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4942 gen_load_spr(t2, SPR_MQ);
4943 tcg_gen_andc_tl(t1, t2, t1);
4944 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4945 gen_set_label(l2);
4946 tcg_temp_free(t0);
4947 tcg_temp_free(t1);
4948 tcg_temp_free(t2);
76a66253 4949 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4950 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4951}
4952
4953/* slq - slq. */
4954GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4955{
7487953d
AJ		 4956 int l1 = gen_new_label();
4957 TCGv t0 = tcg_temp_new();
4958 TCGv t1 = tcg_temp_new();
4959 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4960 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4961 tcg_gen_subfi_tl(t1, 32, t1);
4962 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4963 tcg_gen_or_tl(t1, t0, t1);
4964 gen_store_spr(SPR_MQ, t1);
4965 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4966 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4967 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4968 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4969 gen_set_label(l1);
4970 tcg_temp_free(t0);
4971 tcg_temp_free(t1);
76a66253 4972 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4974}
4975
d9bce9d9 4976/* sraiq - sraiq. */
76a66253
JM		 4977GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4978{
7487953d
AJ		 4979 int sh = SH(ctx->opcode);
4980 int l1 = gen_new_label();
4981 TCGv t0 = tcg_temp_new();
4982 TCGv t1 = tcg_temp_new();
4983 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4984 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4985 tcg_gen_or_tl(t0, t0, t1);
4986 gen_store_spr(SPR_MQ, t0);
4987 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
4988 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4989 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4990 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
4991 gen_set_label(l1);
4992 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4993 tcg_temp_free(t0);
4994 tcg_temp_free(t1);
76a66253 4995 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 4996 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 4997}
4998
4999/* sraq - sraq. */
5000GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
5001{
7487953d
AJ		 5002 int l1 = gen_new_label();
5003 int l2 = gen_new_label();
5004 TCGv t0 = tcg_temp_new();
5005 TCGv t1 = tcg_temp_local_new();
5006 TCGv t2 = tcg_temp_local_new();
5007 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5008 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5009 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5010 tcg_gen_subfi_tl(t2, 32, t2);
5011 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5012 tcg_gen_or_tl(t0, t0, t2);
5013 gen_store_spr(SPR_MQ, t0);
5014 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5015 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5016 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5017 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5018 gen_set_label(l1);
5019 tcg_temp_free(t0);
5020 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5021 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
5022 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5023 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5024 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA));
5025 gen_set_label(l2);
5026 tcg_temp_free(t1);
5027 tcg_temp_free(t2);
76a66253 5028 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5029 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5030}
5031
5032/* sre - sre. */
5033GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
5034{
7487953d
AJ		 5035 TCGv t0 = tcg_temp_new();
5036 TCGv t1 = tcg_temp_new();
5037 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5038 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5039 tcg_gen_subfi_tl(t1, 32, t1);
5040 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5041 tcg_gen_or_tl(t1, t0, t1);
5042 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5043 gen_store_spr(SPR_MQ, t1);
5044 tcg_temp_free(t0);
5045 tcg_temp_free(t1);
76a66253 5046 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5047 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5048}
5049
5050/* srea - srea. */
5051GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
5052{
7487953d
AJ		 5053 TCGv t0 = tcg_temp_new();
5054 TCGv t1 = tcg_temp_new();
5055 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5056 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5057 gen_store_spr(SPR_MQ, t0);
5058 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5059 tcg_temp_free(t0);
5060 tcg_temp_free(t1);
76a66253 5061 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5062 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5063}
5064
5065/* sreq */
5066GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
5067{
7487953d
AJ		 5068 TCGv t0 = tcg_temp_new();
5069 TCGv t1 = tcg_temp_new();
5070 TCGv t2 = tcg_temp_new();
5071 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5072 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5073 tcg_gen_shr_tl(t1, t1, t0);
5074 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5075 gen_load_spr(t2, SPR_MQ);
5076 gen_store_spr(SPR_MQ, t0);
5077 tcg_gen_and_tl(t0, t0, t1);
5078 tcg_gen_andc_tl(t2, t2, t1);
5079 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5080 tcg_temp_free(t0);
5081 tcg_temp_free(t1);
5082 tcg_temp_free(t2);
76a66253 5083 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5084 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5085}
5086
5087/* sriq */
5088GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
5089{
7487953d
AJ		 5090 int sh = SH(ctx->opcode);
5091 TCGv t0 = tcg_temp_new();
5092 TCGv t1 = tcg_temp_new();
5093 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5094 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5095 tcg_gen_or_tl(t1, t0, t1);
5096 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5097 gen_store_spr(SPR_MQ, t1);
5098 tcg_temp_free(t0);
5099 tcg_temp_free(t1);
76a66253 5100 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5101 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5102}
5103
5104/* srliq */
5105GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
5106{
7487953d
AJ		 5107 int sh = SH(ctx->opcode);
5108 TCGv t0 = tcg_temp_new();
5109 TCGv t1 = tcg_temp_new();
5110 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5111 gen_load_spr(t1, SPR_MQ);
5112 gen_store_spr(SPR_MQ, t0);
5113 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5114 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5115 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5116 tcg_temp_free(t0);
5117 tcg_temp_free(t1);
76a66253 5118 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5119 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5120}
5121
5122/* srlq */
5123GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
5124{
7487953d
AJ		 5125 int l1 = gen_new_label();
5126 int l2 = gen_new_label();
5127 TCGv t0 = tcg_temp_local_new();
5128 TCGv t1 = tcg_temp_local_new();
5129 TCGv t2 = tcg_temp_local_new();
5130 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5131 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5132 tcg_gen_shr_tl(t2, t1, t2);
5133 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5134 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5135 gen_load_spr(t0, SPR_MQ);
5136 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5137 tcg_gen_br(l2);
5138 gen_set_label(l1);
5139 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5140 tcg_gen_and_tl(t0, t0, t2);
5141 gen_load_spr(t1, SPR_MQ);
5142 tcg_gen_andc_tl(t1, t1, t2);
5143 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5144 gen_set_label(l2);
5145 tcg_temp_free(t0);
5146 tcg_temp_free(t1);
5147 tcg_temp_free(t2);
76a66253 5148 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5149 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5150}
5151
5152/* srq */
5153GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
5154{
7487953d
AJ		 5155 int l1 = gen_new_label();
5156 TCGv t0 = tcg_temp_new();
5157 TCGv t1 = tcg_temp_new();
5158 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5159 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5160 tcg_gen_subfi_tl(t1, 32, t1);
5161 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5162 tcg_gen_or_tl(t1, t0, t1);
5163 gen_store_spr(SPR_MQ, t1);
5164 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5165 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5166 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5167 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5168 gen_set_label(l1);
5169 tcg_temp_free(t0);
5170 tcg_temp_free(t1);
76a66253 5171 if (unlikely(Rc(ctx->opcode) != 0))
7487953d 5172 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5173}
5174
5175/* PowerPC 602 specific instructions */
5176/* dsa */
5177GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
5178{
5179 /* XXX: TODO */
e06fcd75 5180 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5181}
5182
5183/* esa */
5184GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
5185{
5186 /* XXX: TODO */
e06fcd75 5187 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5188}
5189
5190/* mfrom */
5191GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
5192{
5193#if defined(CONFIG_USER_ONLY)
e06fcd75 5194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5195#else
76db3ba4 5196 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5198 return;
5199 }
cf02a65c 5200 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5201#endif
5202}
5203
5204/* 602 - 603 - G2 TLB management */
5205/* tlbld */
c7697e1f 5206GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5207{
5208#if defined(CONFIG_USER_ONLY)
e06fcd75 5209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5210#else
76db3ba4 5211 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5212 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5213 return;
5214 }
74d37793 5215 gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5216#endif
5217}
5218
5219/* tlbli */
c7697e1f 5220GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 5221{
5222#if defined(CONFIG_USER_ONLY)
e06fcd75 5223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5224#else
76db3ba4 5225 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5227 return;
5228 }
74d37793 5229 gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 5230#endif
5231}
5232
7dbe11ac
JM		 5233/* 74xx TLB management */
5234/* tlbld */
c7697e1f 5235GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5236{
5237#if defined(CONFIG_USER_ONLY)
e06fcd75 5238 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5239#else
76db3ba4 5240 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5241 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5242 return;
5243 }
74d37793 5244 gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5245#endif
5246}
5247
5248/* tlbli */
c7697e1f 5249GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 5250{
5251#if defined(CONFIG_USER_ONLY)
e06fcd75 5252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac 5253#else
76db3ba4 5254 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5255 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
7dbe11ac
JM		 5256 return;
5257 }
74d37793 5258 gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 5259#endif
5260}
5261
76a66253
JM		 5262/* POWER instructions not in PowerPC 601 */
5263/* clf */
5264GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
5265{
5266 /* Cache line flush: implemented as no-op */
5267}
5268
5269/* cli */
5270GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
5271{
7f75ffd3 5272 /* Cache line invalidate: privileged and treated as no-op */
76a66253 5273#if defined(CONFIG_USER_ONLY)
e06fcd75 5274 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5275#else
76db3ba4 5276 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5277 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5278 return;
5279 }
5280#endif
5281}
5282
5283/* dclst */
5284GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
5285{
5286 /* Data cache line store: treated as no-op */
5287}
5288
5289GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5290{
5291#if defined(CONFIG_USER_ONLY)
e06fcd75 5292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5293#else
74d37793
AJ		 5294 int ra = rA(ctx->opcode);
5295 int rd = rD(ctx->opcode);
5296 TCGv t0;
76db3ba4 5297 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5298 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5299 return;
5300 }
74d37793 5301 t0 = tcg_temp_new();
76db3ba4 5302 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5303 tcg_gen_shri_tl(t0, t0, 28);
5304 tcg_gen_andi_tl(t0, t0, 0xF);
5305 gen_helper_load_sr(cpu_gpr[rd], t0);
5306 tcg_temp_free(t0);
76a66253 5307 if (ra != 0 && ra != rd)
74d37793 5308 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
76a66253
JM		 5309#endif
5310}
5311
5312GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5313{
5314#if defined(CONFIG_USER_ONLY)
e06fcd75 5315 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5316#else
22e0e173 5317 TCGv t0;
76db3ba4 5318 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5319 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5320 return;
5321 }
22e0e173 5322 t0 = tcg_temp_new();
76db3ba4 5323 gen_addr_reg_index(ctx, t0);
22e0e173
AJ		 5324 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0);
5325 tcg_temp_free(t0);
76a66253
JM		 5326#endif
5327}
5328
5329GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5330{
5331#if defined(CONFIG_USER_ONLY)
e06fcd75 5332 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5333#else
76db3ba4 5334 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5335 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5336 return;
5337 }
d72a19f7 5338 gen_helper_rfsvc();
e06fcd75 5339 gen_sync_exception(ctx);
76a66253
JM		 5340#endif
5341}
5342
5343/* svc is not implemented for now */
5344
5345/* POWER2 specific instructions */
5346/* Quad manipulation (load/store two floats at a time) */
76a66253
JM		 5347
5348/* lfq */
5349GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5350{
01a4afeb 5351 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5352 TCGv t0;
5353 gen_set_access_type(ctx, ACCESS_FLOAT);
5354 t0 = tcg_temp_new();
5355 gen_addr_imm_index(ctx, t0, 0);
5356 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5357 gen_addr_add(ctx, t0, t0, 8);
5358 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5359 tcg_temp_free(t0);
76a66253
JM		 5360}
5361
5362/* lfqu */
5363GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5364{
5365 int ra = rA(ctx->opcode);
01a4afeb 5366 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5367 TCGv t0, t1;
5368 gen_set_access_type(ctx, ACCESS_FLOAT);
5369 t0 = tcg_temp_new();
5370 t1 = tcg_temp_new();
5371 gen_addr_imm_index(ctx, t0, 0);
5372 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5373 gen_addr_add(ctx, t1, t0, 8);
5374 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
76a66253 5375 if (ra != 0)
01a4afeb
AJ		 5376 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5377 tcg_temp_free(t0);
5378 tcg_temp_free(t1);
76a66253
JM		 5379}
5380
5381/* lfqux */
5382GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5383{
5384 int ra = rA(ctx->opcode);
01a4afeb 5385 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5386 gen_set_access_type(ctx, ACCESS_FLOAT);
5387 TCGv t0, t1;
5388 t0 = tcg_temp_new();
5389 gen_addr_reg_index(ctx, t0);
5390 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5391 t1 = tcg_temp_new();
5392 gen_addr_add(ctx, t1, t0, 8);
5393 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5394 tcg_temp_free(t1);
76a66253 5395 if (ra != 0)
01a4afeb
AJ		 5396 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5397 tcg_temp_free(t0);
76a66253
JM		 5398}
5399
5400/* lfqx */
5401GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5402{
01a4afeb 5403 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5404 TCGv t0;
5405 gen_set_access_type(ctx, ACCESS_FLOAT);
5406 t0 = tcg_temp_new();
5407 gen_addr_reg_index(ctx, t0);
5408 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5409 gen_addr_add(ctx, t0, t0, 8);
5410 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5411 tcg_temp_free(t0);
76a66253
JM		 5412}
5413
5414/* stfq */
5415GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5416{
01a4afeb 5417 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5418 TCGv t0;
5419 gen_set_access_type(ctx, ACCESS_FLOAT);
5420 t0 = tcg_temp_new();
5421 gen_addr_imm_index(ctx, t0, 0);
5422 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5423 gen_addr_add(ctx, t0, t0, 8);
5424 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5425 tcg_temp_free(t0);
76a66253
JM		 5426}
5427
5428/* stfqu */
5429GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5430{
5431 int ra = rA(ctx->opcode);
01a4afeb 5432 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5433 TCGv t0, t1;
5434 gen_set_access_type(ctx, ACCESS_FLOAT);
5435 t0 = tcg_temp_new();
5436 gen_addr_imm_index(ctx, t0, 0);
5437 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5438 t1 = tcg_temp_new();
5439 gen_addr_add(ctx, t1, t0, 8);
5440 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5441 tcg_temp_free(t1);
76a66253 5442 if (ra != 0)
01a4afeb
AJ		 5443 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5444 tcg_temp_free(t0);
76a66253
JM		 5445}
5446
5447/* stfqux */
5448GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5449{
5450 int ra = rA(ctx->opcode);
01a4afeb 5451 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5452 TCGv t0, t1;
5453 gen_set_access_type(ctx, ACCESS_FLOAT);
5454 t0 = tcg_temp_new();
5455 gen_addr_reg_index(ctx, t0);
5456 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5457 t1 = tcg_temp_new();
5458 gen_addr_add(ctx, t1, t0, 8);
5459 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5460 tcg_temp_free(t1);
76a66253 5461 if (ra != 0)
01a4afeb
AJ		 5462 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5463 tcg_temp_free(t0);
76a66253
JM		 5464}
5465
5466/* stfqx */
5467GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5468{
01a4afeb 5469 int rd = rD(ctx->opcode);
76db3ba4
AJ		 5470 TCGv t0;
5471 gen_set_access_type(ctx, ACCESS_FLOAT);
5472 t0 = tcg_temp_new();
5473 gen_addr_reg_index(ctx, t0);
5474 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5475 gen_addr_add(ctx, t0, t0, 8);
5476 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
01a4afeb 5477 tcg_temp_free(t0);
76a66253
JM		 5478}
5479
5480/* BookE specific instructions */
2662a059 5481/* XXX: not implemented on 440 ? */
05332d70 5482GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5483{
5484 /* XXX: TODO */
e06fcd75 5485 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253
JM		 5486}
5487
2662a059 5488/* XXX: not implemented on 440 ? */
05332d70 5489GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5490{
5491#if defined(CONFIG_USER_ONLY)
e06fcd75 5492 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5493#else
74d37793 5494 TCGv t0;
76db3ba4 5495 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5496 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5497 return;
5498 }
ec72e276 5499 t0 = tcg_temp_new();
76db3ba4 5500 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5501 gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]);
5502 tcg_temp_free(t0);
76a66253
JM		 5503#endif
5504}
5505
5506/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5507static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5508 int opc2, int opc3,
5509 int ra, int rb, int rt, int Rc)
76a66253 5510{
182608d4
AJ		 5511 TCGv t0, t1;
5512
a7812ae4
PB		 5513 t0 = tcg_temp_local_new();
5514 t1 = tcg_temp_local_new();
182608d4 5515
76a66253
JM		 5516 switch (opc3 & 0x0D) {
5517 case 0x05:
5518 /* macchw - macchw. - macchwo - macchwo. */
5519 /* macchws - macchws. - macchwso - macchwso. */
5520 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5521 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5522 /* mulchw - mulchw. */
182608d4
AJ		 5523 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5524 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5525 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5526 break;
5527 case 0x04:
5528 /* macchwu - macchwu. - macchwuo - macchwuo. */
5529 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5530 /* mulchwu - mulchwu. */
182608d4
AJ		 5531 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5532 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5533 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5534 break;
5535 case 0x01:
5536 /* machhw - machhw. - machhwo - machhwo. */
5537 /* machhws - machhws. - machhwso - machhwso. */
5538 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5539 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5540 /* mulhhw - mulhhw. */
182608d4
AJ		 5541 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5542 tcg_gen_ext16s_tl(t0, t0);
5543 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5544 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5545 break;
5546 case 0x00:
5547 /* machhwu - machhwu. - machhwuo - machhwuo. */
5548 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5549 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5550 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5551 tcg_gen_ext16u_tl(t0, t0);
5552 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5553 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5554 break;
5555 case 0x0D:
5556 /* maclhw - maclhw. - maclhwo - maclhwo. */
5557 /* maclhws - maclhws. - maclhwso - maclhwso. */
5558 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5559 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5560 /* mullhw - mullhw. */
182608d4
AJ		 5561 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5562 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5563 break;
5564 case 0x0C:
5565 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5566 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5567 /* mullhwu - mullhwu. */
182608d4
AJ		 5568 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5569 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5570 break;
5571 }
76a66253 5572 if (opc2 & 0x04) {
182608d4
AJ		 5573 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5574 tcg_gen_mul_tl(t1, t0, t1);
5575 if (opc2 & 0x02) {
5576 /* nmultiply-and-accumulate (0x0E) */
5577 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5578 } else {
5579 /* multiply-and-accumulate (0x0C) */
5580 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5581 }
5582
5583 if (opc3 & 0x12) {
5584 /* Check overflow and/or saturate */
5585 int l1 = gen_new_label();
5586
5587 if (opc3 & 0x10) {
5588 /* Start with XER OV disabled, the most likely case */
5589 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5590 }
5591 if (opc3 & 0x01) {
5592 /* Signed */
5593 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5594 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5595 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5596 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
bdc4e053 5597 if (opc3 & 0x02) {
182608d4
AJ		 5598 /* Saturate */
5599 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5600 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5601 }
5602 } else {
5603 /* Unsigned */
5604 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
bdc4e053 5605 if (opc3 & 0x02) {
182608d4
AJ		 5606 /* Saturate */
5607 tcg_gen_movi_tl(t0, UINT32_MAX);
5608 }
5609 }
5610 if (opc3 & 0x10) {
5611 /* Check overflow */
5612 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5613 }
5614 gen_set_label(l1);
5615 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5616 }
5617 } else {
5618 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5619 }
182608d4
AJ		 5620 tcg_temp_free(t0);
5621 tcg_temp_free(t1);
76a66253
JM		 5622 if (unlikely(Rc) != 0) {
5623 /* Update Rc0 */
182608d4 5624 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5625 }
5626}
5627
a750fc0b
JM		 5628#define GEN_MAC_HANDLER(name, opc2, opc3) \
5629GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5630{ \
5631 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5632 rD(ctx->opcode), Rc(ctx->opcode)); \
5633}
5634
5635/* macchw - macchw. */
a750fc0b 5636GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5637/* macchwo - macchwo. */
a750fc0b 5638GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5639/* macchws - macchws. */
a750fc0b 5640GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5641/* macchwso - macchwso. */
a750fc0b 5642GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5643/* macchwsu - macchwsu. */
a750fc0b 5644GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5645/* macchwsuo - macchwsuo. */
a750fc0b 5646GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5647/* macchwu - macchwu. */
a750fc0b 5648GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5649/* macchwuo - macchwuo. */
a750fc0b 5650GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5651/* machhw - machhw. */
a750fc0b 5652GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5653/* machhwo - machhwo. */
a750fc0b 5654GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5655/* machhws - machhws. */
a750fc0b 5656GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5657/* machhwso - machhwso. */
a750fc0b 5658GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5659/* machhwsu - machhwsu. */
a750fc0b 5660GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5661/* machhwsuo - machhwsuo. */
a750fc0b 5662GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5663/* machhwu - machhwu. */
a750fc0b 5664GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5665/* machhwuo - machhwuo. */
a750fc0b 5666GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5667/* maclhw - maclhw. */
a750fc0b 5668GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5669/* maclhwo - maclhwo. */
a750fc0b 5670GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5671/* maclhws - maclhws. */
a750fc0b 5672GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5673/* maclhwso - maclhwso. */
a750fc0b 5674GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5675/* maclhwu - maclhwu. */
a750fc0b 5676GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5677/* maclhwuo - maclhwuo. */
a750fc0b 5678GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5679/* maclhwsu - maclhwsu. */
a750fc0b 5680GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5681/* maclhwsuo - maclhwsuo. */
a750fc0b 5682GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5683/* nmacchw - nmacchw. */
a750fc0b 5684GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5685/* nmacchwo - nmacchwo. */
a750fc0b 5686GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5687/* nmacchws - nmacchws. */
a750fc0b 5688GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5689/* nmacchwso - nmacchwso. */
a750fc0b 5690GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5691/* nmachhw - nmachhw. */
a750fc0b 5692GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5693/* nmachhwo - nmachhwo. */
a750fc0b 5694GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5695/* nmachhws - nmachhws. */
a750fc0b 5696GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5697/* nmachhwso - nmachhwso. */
a750fc0b 5698GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5699/* nmaclhw - nmaclhw. */
a750fc0b 5700GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5701/* nmaclhwo - nmaclhwo. */
a750fc0b 5702GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5703/* nmaclhws - nmaclhws. */
a750fc0b 5704GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5705/* nmaclhwso - nmaclhwso. */
a750fc0b 5706GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5707
5708/* mulchw - mulchw. */
a750fc0b 5709GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5710/* mulchwu - mulchwu. */
a750fc0b 5711GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5712/* mulhhw - mulhhw. */
a750fc0b 5713GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5714/* mulhhwu - mulhhwu. */
a750fc0b 5715GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5716/* mullhw - mullhw. */
a750fc0b 5717GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5718/* mullhwu - mullhwu. */
a750fc0b 5719GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5720
5721/* mfdcr */
05332d70 5722GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5723{
5724#if defined(CONFIG_USER_ONLY)
e06fcd75 5725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5726#else
06dca6a7 5727 TCGv dcrn;
76db3ba4 5728 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5730 return;
5731 }
06dca6a7
AJ		 5732 /* NIP cannot be restored if the memory exception comes from an helper */
5733 gen_update_nip(ctx, ctx->nip - 4);
5734 dcrn = tcg_const_tl(SPR(ctx->opcode));
5735 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn);
5736 tcg_temp_free(dcrn);
76a66253
JM		 5737#endif
5738}
5739
5740/* mtdcr */
05332d70 5741GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5742{
5743#if defined(CONFIG_USER_ONLY)
e06fcd75 5744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253 5745#else
06dca6a7 5746 TCGv dcrn;
76db3ba4 5747 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5748 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
76a66253
JM		 5749 return;
5750 }
06dca6a7
AJ		 5751 /* NIP cannot be restored if the memory exception comes from an helper */
5752 gen_update_nip(ctx, ctx->nip - 4);
5753 dcrn = tcg_const_tl(SPR(ctx->opcode));
5754 gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]);
5755 tcg_temp_free(dcrn);
a42bd6cc
JM		 5756#endif
5757}
5758
5759/* mfdcrx */
2662a059 5760/* XXX: not implemented on 440 ? */
05332d70 5761GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5762{
5763#if defined(CONFIG_USER_ONLY)
e06fcd75 5764 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5765#else
76db3ba4 5766 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5767 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5768 return;
5769 }
06dca6a7
AJ		 5770 /* NIP cannot be restored if the memory exception comes from an helper */
5771 gen_update_nip(ctx, ctx->nip - 4);
5772 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5773 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5774#endif
5775}
5776
5777/* mtdcrx */
2662a059 5778/* XXX: not implemented on 440 ? */
05332d70 5779GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5780{
5781#if defined(CONFIG_USER_ONLY)
e06fcd75 5782 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc 5783#else
76db3ba4 5784 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5785 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
a42bd6cc
JM		 5786 return;
5787 }
06dca6a7
AJ		 5788 /* NIP cannot be restored if the memory exception comes from an helper */
5789 gen_update_nip(ctx, ctx->nip - 4);
5790 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b 5791 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5792#endif
5793}
5794
a750fc0b
JM		 5795/* mfdcrux (PPC 460) : user-mode access to DCR */
5796GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5797{
06dca6a7
AJ		 5798 /* NIP cannot be restored if the memory exception comes from an helper */
5799 gen_update_nip(ctx, ctx->nip - 4);
5800 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
a750fc0b
JM		 5801 /* Note: Rc update flag set leads to undefined state of Rc0 */
5802}
5803
5804/* mtdcrux (PPC 460) : user-mode access to DCR */
5805GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5806{
06dca6a7
AJ		 5807 /* NIP cannot be restored if the memory exception comes from an helper */
5808 gen_update_nip(ctx, ctx->nip - 4);
5809 gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5810 /* Note: Rc update flag set leads to undefined state of Rc0 */
5811}
5812
76a66253
JM		 5813/* dccci */
5814GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5815{
5816#if defined(CONFIG_USER_ONLY)
e06fcd75 5817 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5818#else
76db3ba4 5819 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5821 return;
5822 }
5823 /* interpreted as no-op */
5824#endif
5825}
5826
5827/* dcread */
5828GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5829{
5830#if defined(CONFIG_USER_ONLY)
e06fcd75 5831 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5832#else
b61f2753 5833 TCGv EA, val;
76db3ba4 5834 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5836 return;
5837 }
76db3ba4 5838 gen_set_access_type(ctx, ACCESS_CACHE);
a7812ae4 5839 EA = tcg_temp_new();
76db3ba4 5840 gen_addr_reg_index(ctx, EA);
a7812ae4 5841 val = tcg_temp_new();
76db3ba4 5842 gen_qemu_ld32u(ctx, val, EA);
b61f2753
AJ		 5843 tcg_temp_free(val);
5844 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5845 tcg_temp_free(EA);
76a66253
JM		 5846#endif
5847}
5848
5849/* icbt */
c7697e1f 5850GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5851{
5852 /* interpreted as no-op */
5853 /* XXX: specification say this is treated as a load by the MMU
5854 * but does not generate any exception
5855 */
5856}
5857
5858/* iccci */
5859GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5860{
5861#if defined(CONFIG_USER_ONLY)
e06fcd75 5862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5863#else
76db3ba4 5864 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5866 return;
5867 }
5868 /* interpreted as no-op */
5869#endif
5870}
5871
5872/* icread */
5873GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5874{
5875#if defined(CONFIG_USER_ONLY)
e06fcd75 5876 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5877#else
76db3ba4 5878 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5880 return;
5881 }
5882 /* interpreted as no-op */
5883#endif
5884}
5885
76db3ba4 5886/* rfci (mem_idx only) */
c7697e1f 5887GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5888{
5889#if defined(CONFIG_USER_ONLY)
e06fcd75 5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5891#else
76db3ba4 5892 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5894 return;
5895 }
5896 /* Restore CPU state */
d72a19f7 5897 gen_helper_40x_rfci();
e06fcd75 5898 gen_sync_exception(ctx);
a42bd6cc
JM		 5899#endif
5900}
5901
5902GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5903{
5904#if defined(CONFIG_USER_ONLY)
e06fcd75 5905 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5906#else
76db3ba4 5907 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5908 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5909 return;
5910 }
5911 /* Restore CPU state */
d72a19f7 5912 gen_helper_rfci();
e06fcd75 5913 gen_sync_exception(ctx);
a42bd6cc
JM		 5914#endif
5915}
5916
5917/* BookE specific */
2662a059 5918/* XXX: not implemented on 440 ? */
05332d70 5919GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5920{
5921#if defined(CONFIG_USER_ONLY)
e06fcd75 5922 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5923#else
76db3ba4 5924 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5925 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5926 return;
5927 }
5928 /* Restore CPU state */
d72a19f7 5929 gen_helper_rfdi();
e06fcd75 5930 gen_sync_exception(ctx);
76a66253
JM		 5931#endif
5932}
5933
2662a059 5934/* XXX: not implemented on 440 ? */
a750fc0b 5935GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5936{
5937#if defined(CONFIG_USER_ONLY)
e06fcd75 5938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc 5939#else
76db3ba4 5940 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5941 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
a42bd6cc
JM		 5942 return;
5943 }
5944 /* Restore CPU state */
d72a19f7 5945 gen_helper_rfmci();
e06fcd75 5946 gen_sync_exception(ctx);
a42bd6cc
JM		 5947#endif
5948}
5eb7995e 5949
d9bce9d9 5950/* TLB management - PowerPC 405 implementation */
76a66253 5951/* tlbre */
c7697e1f 5952GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5953{
5954#if defined(CONFIG_USER_ONLY)
e06fcd75 5955 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5956#else
76db3ba4 5957 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5958 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5959 return;
5960 }
5961 switch (rB(ctx->opcode)) {
5962 case 0:
74d37793 5963 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5964 break;
5965 case 1:
74d37793 5966 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 5967 break;
5968 default:
e06fcd75 5969 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 5970 break;
9a64fbe4 5971 }
76a66253
JM		 5972#endif
5973}
5974
d9bce9d9 5975/* tlbsx - tlbsx. */
c7697e1f 5976GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5977{
5978#if defined(CONFIG_USER_ONLY)
e06fcd75 5979 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 5980#else
74d37793 5981 TCGv t0;
76db3ba4 5982 if (unlikely(!ctx->mem_idx)) {
e06fcd75 5983 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 5984 return;
5985 }
74d37793 5986 t0 = tcg_temp_new();
76db3ba4 5987 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 5988 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
5989 tcg_temp_free(t0);
5990 if (Rc(ctx->opcode)) {
5991 int l1 = gen_new_label();
5992 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
5993 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
5994 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
5995 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5996 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5997 gen_set_label(l1);
5998 }
76a66253 5999#endif
79aceca5
FB		 6000}
6001
76a66253 6002/* tlbwe */
c7697e1f 6003GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 6004{
76a66253 6005#if defined(CONFIG_USER_ONLY)
e06fcd75 6006 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6007#else
76db3ba4 6008 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6009 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6010 return;
6011 }
6012 switch (rB(ctx->opcode)) {
6013 case 0:
74d37793 6014 gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6015 break;
6016 case 1:
74d37793 6017 gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 6018 break;
6019 default:
e06fcd75 6020 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
76a66253 6021 break;
9a64fbe4 6022 }
76a66253
JM		 6023#endif
6024}
6025
a4bb6c3e 6026/* TLB management - PowerPC 440 implementation */
5eb7995e 6027/* tlbre */
c7697e1f 6028GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 6029{
6030#if defined(CONFIG_USER_ONLY)
e06fcd75 6031 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6032#else
76db3ba4 6033 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6034 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6035 return;
6036 }
6037 switch (rB(ctx->opcode)) {
6038 case 0:
5eb7995e 6039 case 1:
5eb7995e 6040 case 2:
74d37793
AJ		 6041 {
6042 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6043 gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6044 tcg_temp_free_i32(t0);
6045 }
5eb7995e
JM		 6046 break;
6047 default:
e06fcd75 6048 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6049 break;
6050 }
6051#endif
6052}
6053
6054/* tlbsx - tlbsx. */
c7697e1f 6055GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 6056{
6057#if defined(CONFIG_USER_ONLY)
e06fcd75 6058 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6059#else
74d37793 6060 TCGv t0;
76db3ba4 6061 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6062 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6063 return;
6064 }
74d37793 6065 t0 = tcg_temp_new();
76db3ba4 6066 gen_addr_reg_index(ctx, t0);
74d37793
AJ		 6067 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0);
6068 tcg_temp_free(t0);
6069 if (Rc(ctx->opcode)) {
6070 int l1 = gen_new_label();
6071 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer);
6072 tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO);
6073 tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1);
6074 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6075 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6076 gen_set_label(l1);
6077 }
5eb7995e
JM		 6078#endif
6079}
6080
6081/* tlbwe */
c7697e1f 6082GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 6083{
6084#if defined(CONFIG_USER_ONLY)
e06fcd75 6085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e 6086#else
76db3ba4 6087 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6088 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5eb7995e
JM		 6089 return;
6090 }
6091 switch (rB(ctx->opcode)) {
6092 case 0:
5eb7995e 6093 case 1:
5eb7995e 6094 case 2:
74d37793
AJ		 6095 {
6096 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6097 gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
6098 tcg_temp_free_i32(t0);
6099 }
5eb7995e
JM		 6100 break;
6101 default:
e06fcd75 6102 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5eb7995e
JM		 6103 break;
6104 }
6105#endif
6106}
6107
76a66253 6108/* wrtee */
05332d70 6109GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 6110{
6111#if defined(CONFIG_USER_ONLY)
e06fcd75 6112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6113#else
6527f6ea 6114 TCGv t0;
76db3ba4 6115 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6116 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6117 return;
6118 }
6527f6ea
AJ		 6119 t0 = tcg_temp_new();
6120 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6121 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6122 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6123 tcg_temp_free(t0);
dee96f6c
JM		 6124 /* Stop translation to have a chance to raise an exception
6125 * if we just set msr_ee to 1
6126 */
e06fcd75 6127 gen_stop_exception(ctx);
76a66253
JM		 6128#endif
6129}
6130
6131/* wrteei */
05332d70 6132GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 6133{
6134#if defined(CONFIG_USER_ONLY)
e06fcd75 6135 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253 6136#else
76db3ba4 6137 if (unlikely(!ctx->mem_idx)) {
e06fcd75 6138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
76a66253
JM		 6139 return;
6140 }
6527f6ea
AJ		 6141 if (ctx->opcode & 0x00010000) {
6142 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6143 /* Stop translation to have a chance to raise an exception */
e06fcd75 6144 gen_stop_exception(ctx);
6527f6ea 6145 } else {
1b6e5f99 6146 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6527f6ea 6147 }
76a66253
JM		 6148#endif
6149}
6150
08e46e54 6151/* PowerPC 440 specific instructions */
76a66253
JM		 6152/* dlmzb */
6153GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
6154{
ef0d51af
AJ		 6155 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6156 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
6157 cpu_gpr[rB(ctx->opcode)], t0);
6158 tcg_temp_free_i32(t0);
76a66253
JM		 6159}
6160
6161/* mbar replaces eieio on 440 */
26370046 6162GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE)
76a66253
JM		 6163{
6164 /* interpreted as no-op */
6165}
6166
6167/* msync replaces sync on 440 */
0db1b20e 6168GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 6169{
6170 /* interpreted as no-op */
6171}
6172
6173/* icbt */
c7697e1f 6174GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 6175{
6176 /* interpreted as no-op */
6177 /* XXX: specification say this is treated as a load by the MMU
6178 * but does not generate any exception
6179 */
79aceca5
FB		 6180}
6181
a9d9eb8f
JM		 6182/*** Altivec vector extension ***/
6183/* Altivec registers moves */
a9d9eb8f 6184
564e571a
AJ		 6185static always_inline TCGv_ptr gen_avr_ptr(int reg)
6186{
e4704b3b 6187 TCGv_ptr r = tcg_temp_new_ptr();
564e571a
AJ		 6188 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6189 return r;
6190}
6191
a9d9eb8f 6192#define GEN_VR_LDX(name, opc2, opc3) \
fe1e5c53 6193GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
a9d9eb8f 6194{ \
fe1e5c53 6195 TCGv EA; \
a9d9eb8f 6196 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6197 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6198 return; \
6199 } \
76db3ba4 6200 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6201 EA = tcg_temp_new(); \
76db3ba4 6202 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6203 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6204 if (ctx->le_mode) { \
6205 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6206 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6207 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6208 } else { \
76db3ba4 6209 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6210 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6211 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6212 } \
6213 tcg_temp_free(EA); \
a9d9eb8f
JM		 6214}
6215
6216#define GEN_VR_STX(name, opc2, opc3) \
6217GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6218{ \
fe1e5c53 6219 TCGv EA; \
a9d9eb8f 6220 if (unlikely(!ctx->altivec_enabled)) { \
e06fcd75 6221 gen_exception(ctx, POWERPC_EXCP_VPU); \
a9d9eb8f
JM		 6222 return; \
6223 } \
76db3ba4 6224 gen_set_access_type(ctx, ACCESS_INT); \
fe1e5c53 6225 EA = tcg_temp_new(); \
76db3ba4 6226 gen_addr_reg_index(ctx, EA); \
fe1e5c53 6227 tcg_gen_andi_tl(EA, EA, ~0xf); \
76db3ba4
AJ		 6228 if (ctx->le_mode) { \
6229 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53 6230 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6231 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6232 } else { \
76db3ba4 6233 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
fe1e5c53 6234 tcg_gen_addi_tl(EA, EA, 8); \
76db3ba4 6235 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
fe1e5c53
AJ		 6236 } \
6237 tcg_temp_free(EA); \
a9d9eb8f
JM		 6238}
6239
cbfb6ae9
AJ		 6240#define GEN_VR_LVE(name, opc2, opc3) \
6241 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6242 { \
6243 TCGv EA; \
6244 TCGv_ptr rs; \
6245 if (unlikely(!ctx->altivec_enabled)) { \
6246 gen_exception(ctx, POWERPC_EXCP_VPU); \
6247 return; \
6248 } \
6249 gen_set_access_type(ctx, ACCESS_INT); \
6250 EA = tcg_temp_new(); \
6251 gen_addr_reg_index(ctx, EA); \
6252 rs = gen_avr_ptr(rS(ctx->opcode)); \
6253 gen_helper_lve##name (rs, EA); \
6254 tcg_temp_free(EA); \
6255 tcg_temp_free_ptr(rs); \
6256 }
6257
6258#define GEN_VR_STVE(name, opc2, opc3) \
6259 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
6260 { \
6261 TCGv EA; \
6262 TCGv_ptr rs; \
6263 if (unlikely(!ctx->altivec_enabled)) { \
6264 gen_exception(ctx, POWERPC_EXCP_VPU); \
6265 return; \
6266 } \
6267 gen_set_access_type(ctx, ACCESS_INT); \
6268 EA = tcg_temp_new(); \
6269 gen_addr_reg_index(ctx, EA); \
6270 rs = gen_avr_ptr(rS(ctx->opcode)); \
6271 gen_helper_stve##name (rs, EA); \
6272 tcg_temp_free(EA); \
6273 tcg_temp_free_ptr(rs); \
6274 }
6275
fe1e5c53 6276GEN_VR_LDX(lvx, 0x07, 0x03);
a9d9eb8f 6277/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
fe1e5c53 6278GEN_VR_LDX(lvxl, 0x07, 0x0B);
a9d9eb8f 6279
cbfb6ae9
AJ		 6280GEN_VR_LVE(bx, 0x07, 0x00);
6281GEN_VR_LVE(hx, 0x07, 0x01);
6282GEN_VR_LVE(wx, 0x07, 0x02);
6283
fe1e5c53 6284GEN_VR_STX(svx, 0x07, 0x07);
a9d9eb8f 6285/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
fe1e5c53 6286GEN_VR_STX(svxl, 0x07, 0x0F);
a9d9eb8f 6287
cbfb6ae9
AJ		 6288GEN_VR_STVE(bx, 0x07, 0x04);
6289GEN_VR_STVE(hx, 0x07, 0x05);
6290GEN_VR_STVE(wx, 0x07, 0x06);
6291
bf8d8ded
AJ		 6292GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
6293{
6294 TCGv_ptr rd;
6295 TCGv EA;
6296 if (unlikely(!ctx->altivec_enabled)) {
6297 gen_exception(ctx, POWERPC_EXCP_VPU);
6298 return;
6299 }
6300 EA = tcg_temp_new();
6301 gen_addr_reg_index(ctx, EA);
6302 rd = gen_avr_ptr(rD(ctx->opcode));
6303 gen_helper_lvsl(rd, EA);
6304 tcg_temp_free(EA);
6305 tcg_temp_free_ptr(rd);
6306}
6307
6308GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
6309{
6310 TCGv_ptr rd;
6311 TCGv EA;
6312 if (unlikely(!ctx->altivec_enabled)) {
6313 gen_exception(ctx, POWERPC_EXCP_VPU);
6314 return;
6315 }
6316 EA = tcg_temp_new();
6317 gen_addr_reg_index(ctx, EA);
6318 rd = gen_avr_ptr(rD(ctx->opcode));
6319 gen_helper_lvsr(rd, EA);
6320 tcg_temp_free(EA);
6321 tcg_temp_free_ptr(rd);
6322}
6323
785f451b
AJ		 6324GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC)
6325{
6326 TCGv_i32 t;
6327 if (unlikely(!ctx->altivec_enabled)) {
6328 gen_exception(ctx, POWERPC_EXCP_VPU);
6329 return;
6330 }
6331 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6332 t = tcg_temp_new_i32();
6333 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr));
6334 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
fce5ecb7 6335 tcg_temp_free_i32(t);
785f451b
AJ		 6336}
6337
6338GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC)
6339{
6e87b7c7 6340 TCGv_ptr p;
785f451b
AJ		 6341 if (unlikely(!ctx->altivec_enabled)) {
6342 gen_exception(ctx, POWERPC_EXCP_VPU);
6343 return;
6344 }
6e87b7c7
AJ		 6345 p = gen_avr_ptr(rD(ctx->opcode));
6346 gen_helper_mtvscr(p);
6347 tcg_temp_free_ptr(p);
785f451b
AJ		 6348}
6349
7a9b96cf
AJ		 6350/* Logical operations */
6351#define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6352GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6353{ \
6354 if (unlikely(!ctx->altivec_enabled)) { \
6355 gen_exception(ctx, POWERPC_EXCP_VPU); \
6356 return; \
6357 } \
6358 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6359 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6360}
6361
6362GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6363GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6364GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6365GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6366GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6367
8e27dd6f
AJ		 6368#define GEN_VXFORM(name, opc2, opc3) \
6369GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6370{ \
6371 TCGv_ptr ra, rb, rd; \
6372 if (unlikely(!ctx->altivec_enabled)) { \
6373 gen_exception(ctx, POWERPC_EXCP_VPU); \
6374 return; \
6375 } \
6376 ra = gen_avr_ptr(rA(ctx->opcode)); \
6377 rb = gen_avr_ptr(rB(ctx->opcode)); \
6378 rd = gen_avr_ptr(rD(ctx->opcode)); \
6379 gen_helper_##name (rd, ra, rb); \
6380 tcg_temp_free_ptr(ra); \
6381 tcg_temp_free_ptr(rb); \
6382 tcg_temp_free_ptr(rd); \
6383}
6384
7872c51c
AJ		 6385GEN_VXFORM(vaddubm, 0, 0);
6386GEN_VXFORM(vadduhm, 0, 1);
6387GEN_VXFORM(vadduwm, 0, 2);
6388GEN_VXFORM(vsububm, 0, 16);
6389GEN_VXFORM(vsubuhm, 0, 17);
6390GEN_VXFORM(vsubuwm, 0, 18);
e4039339
AJ		 6391GEN_VXFORM(vmaxub, 1, 0);
6392GEN_VXFORM(vmaxuh, 1, 1);
6393GEN_VXFORM(vmaxuw, 1, 2);
6394GEN_VXFORM(vmaxsb, 1, 4);
6395GEN_VXFORM(vmaxsh, 1, 5);
6396GEN_VXFORM(vmaxsw, 1, 6);
6397GEN_VXFORM(vminub, 1, 8);
6398GEN_VXFORM(vminuh, 1, 9);
6399GEN_VXFORM(vminuw, 1, 10);
6400GEN_VXFORM(vminsb, 1, 12);
6401GEN_VXFORM(vminsh, 1, 13);
6402GEN_VXFORM(vminsw, 1, 14);
fab3cbe9
AJ		 6403GEN_VXFORM(vavgub, 1, 16);
6404GEN_VXFORM(vavguh, 1, 17);
6405GEN_VXFORM(vavguw, 1, 18);
6406GEN_VXFORM(vavgsb, 1, 20);
6407GEN_VXFORM(vavgsh, 1, 21);
6408GEN_VXFORM(vavgsw, 1, 22);
3b430048
AJ		 6409GEN_VXFORM(vmrghb, 6, 0);
6410GEN_VXFORM(vmrghh, 6, 1);
6411GEN_VXFORM(vmrghw, 6, 2);
6412GEN_VXFORM(vmrglb, 6, 4);
6413GEN_VXFORM(vmrglh, 6, 5);
6414GEN_VXFORM(vmrglw, 6, 6);
2c277908
AJ		 6415GEN_VXFORM(vmuloub, 4, 0);
6416GEN_VXFORM(vmulouh, 4, 1);
6417GEN_VXFORM(vmulosb, 4, 4);
6418GEN_VXFORM(vmulosh, 4, 5);
6419GEN_VXFORM(vmuleub, 4, 8);
6420GEN_VXFORM(vmuleuh, 4, 9);
6421GEN_VXFORM(vmulesb, 4, 12);
6422GEN_VXFORM(vmulesh, 4, 13);
d79f0809
AJ		 6423GEN_VXFORM(vslb, 2, 4);
6424GEN_VXFORM(vslh, 2, 5);
6425GEN_VXFORM(vslw, 2, 6);
07ef34c3
AJ		 6426GEN_VXFORM(vsrb, 2, 8);
6427GEN_VXFORM(vsrh, 2, 9);
6428GEN_VXFORM(vsrw, 2, 10);
6429GEN_VXFORM(vsrab, 2, 12);
6430GEN_VXFORM(vsrah, 2, 13);
6431GEN_VXFORM(vsraw, 2, 14);
7b239bec
AJ		 6432GEN_VXFORM(vslo, 6, 16);
6433GEN_VXFORM(vsro, 6, 17);
e343da72
AJ		 6434GEN_VXFORM(vaddcuw, 0, 6);
6435GEN_VXFORM(vsubcuw, 0, 22);
5ab09f33
AJ		 6436GEN_VXFORM(vaddubs, 0, 8);
6437GEN_VXFORM(vadduhs, 0, 9);
6438GEN_VXFORM(vadduws, 0, 10);
6439GEN_VXFORM(vaddsbs, 0, 12);
6440GEN_VXFORM(vaddshs, 0, 13);
6441GEN_VXFORM(vaddsws, 0, 14);
6442GEN_VXFORM(vsububs, 0, 24);
6443GEN_VXFORM(vsubuhs, 0, 25);
6444GEN_VXFORM(vsubuws, 0, 26);
6445GEN_VXFORM(vsubsbs, 0, 28);
6446GEN_VXFORM(vsubshs, 0, 29);
6447GEN_VXFORM(vsubsws, 0, 30);
5e1d0985
AJ		 6448GEN_VXFORM(vrlb, 2, 0);
6449GEN_VXFORM(vrlh, 2, 1);
6450GEN_VXFORM(vrlw, 2, 2);
d9430add
AJ		 6451GEN_VXFORM(vsl, 2, 7);
6452GEN_VXFORM(vsr, 2, 11);
5335a145
AJ		 6453GEN_VXFORM(vpkuhum, 7, 0);
6454GEN_VXFORM(vpkuwum, 7, 1);
6455GEN_VXFORM(vpkuhus, 7, 2);
6456GEN_VXFORM(vpkuwus, 7, 3);
6457GEN_VXFORM(vpkshus, 7, 4);
6458GEN_VXFORM(vpkswus, 7, 5);
6459GEN_VXFORM(vpkshss, 7, 6);
6460GEN_VXFORM(vpkswss, 7, 7);
1dd9ffb9 6461GEN_VXFORM(vpkpx, 7, 12);
8142cddd
AJ		 6462GEN_VXFORM(vsum4ubs, 4, 24);
6463GEN_VXFORM(vsum4sbs, 4, 28);
6464GEN_VXFORM(vsum4shs, 4, 25);
6465GEN_VXFORM(vsum2sws, 4, 26);
6466GEN_VXFORM(vsumsws, 4, 30);
56fdd213
AJ		 6467GEN_VXFORM(vaddfp, 5, 0);
6468GEN_VXFORM(vsubfp, 5, 1);
1536ff64
AJ		 6469GEN_VXFORM(vmaxfp, 5, 16);
6470GEN_VXFORM(vminfp, 5, 17);
fab3cbe9 6471
0cbcd906
AJ		 6472#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6473 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6474 { \
6475 TCGv_ptr ra, rb, rd; \
6476 if (unlikely(!ctx->altivec_enabled)) { \
6477 gen_exception(ctx, POWERPC_EXCP_VPU); \
6478 return; \
6479 } \
6480 ra = gen_avr_ptr(rA(ctx->opcode)); \
6481 rb = gen_avr_ptr(rB(ctx->opcode)); \
6482 rd = gen_avr_ptr(rD(ctx->opcode)); \
6483 gen_helper_##opname (rd, ra, rb); \
6484 tcg_temp_free_ptr(ra); \
6485 tcg_temp_free_ptr(rb); \
6486 tcg_temp_free_ptr(rd); \
6487 }
6488
6489#define GEN_VXRFORM(name, opc2, opc3) \
6490 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6491 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6492
1add6e23
AJ		 6493GEN_VXRFORM(vcmpequb, 3, 0)
6494GEN_VXRFORM(vcmpequh, 3, 1)
6495GEN_VXRFORM(vcmpequw, 3, 2)
6496GEN_VXRFORM(vcmpgtsb, 3, 12)
6497GEN_VXRFORM(vcmpgtsh, 3, 13)
6498GEN_VXRFORM(vcmpgtsw, 3, 14)
6499GEN_VXRFORM(vcmpgtub, 3, 8)
6500GEN_VXRFORM(vcmpgtuh, 3, 9)
6501GEN_VXRFORM(vcmpgtuw, 3, 10)
819ca121
AJ		 6502GEN_VXRFORM(vcmpeqfp, 3, 3)
6503GEN_VXRFORM(vcmpgefp, 3, 7)
6504GEN_VXRFORM(vcmpgtfp, 3, 11)
6505GEN_VXRFORM(vcmpbfp, 3, 15)
1add6e23 6506
c026766b
AJ		 6507#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6508 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6509 { \
6510 TCGv_ptr rd; \
6511 TCGv_i32 simm; \
6512 if (unlikely(!ctx->altivec_enabled)) { \
6513 gen_exception(ctx, POWERPC_EXCP_VPU); \
6514 return; \
6515 } \
6516 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6517 rd = gen_avr_ptr(rD(ctx->opcode)); \
6518 gen_helper_##name (rd, simm); \
6519 tcg_temp_free_i32(simm); \
6520 tcg_temp_free_ptr(rd); \
6521 }
6522
6523GEN_VXFORM_SIMM(vspltisb, 6, 12);
6524GEN_VXFORM_SIMM(vspltish, 6, 13);
6525GEN_VXFORM_SIMM(vspltisw, 6, 14);
6526
de5f2484
AJ		 6527#define GEN_VXFORM_NOA(name, opc2, opc3) \
6528 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC) \
6529 { \
6530 TCGv_ptr rb, rd; \
6531 if (unlikely(!ctx->altivec_enabled)) { \
6532 gen_exception(ctx, POWERPC_EXCP_VPU); \
6533 return; \
6534 } \
6535 rb = gen_avr_ptr(rB(ctx->opcode)); \
6536 rd = gen_avr_ptr(rD(ctx->opcode)); \
6537 gen_helper_##name (rd, rb); \
6538 tcg_temp_free_ptr(rb); \
6539 tcg_temp_free_ptr(rd); \
6540 }
6541
6cf1c6e5
AJ		 6542GEN_VXFORM_NOA(vupkhsb, 7, 8);
6543GEN_VXFORM_NOA(vupkhsh, 7, 9);
6544GEN_VXFORM_NOA(vupklsb, 7, 10);
6545GEN_VXFORM_NOA(vupklsh, 7, 11);
79f85c3a
AJ		 6546GEN_VXFORM_NOA(vupkhpx, 7, 13);
6547GEN_VXFORM_NOA(vupklpx, 7, 15);
bdfbac35 6548GEN_VXFORM_NOA(vrefp, 5, 4);
071fc3b1 6549GEN_VXFORM_NOA(vrsqrtefp, 5, 5);
b580763f 6550GEN_VXFORM_NOA(vlogefp, 5, 7);
f6b19645
AJ		 6551GEN_VXFORM_NOA(vrfim, 5, 8);
6552GEN_VXFORM_NOA(vrfin, 5, 9);
6553GEN_VXFORM_NOA(vrfip, 5, 10);
6554GEN_VXFORM_NOA(vrfiz, 5, 11);
79f85c3a 6555
21d21583
AJ		 6556#define GEN_VXFORM_SIMM(name, opc2, opc3) \
6557 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6558 { \
6559 TCGv_ptr rd; \
6560 TCGv_i32 simm; \
6561 if (unlikely(!ctx->altivec_enabled)) { \
6562 gen_exception(ctx, POWERPC_EXCP_VPU); \
6563 return; \
6564 } \
6565 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6566 rd = gen_avr_ptr(rD(ctx->opcode)); \
6567 gen_helper_##name (rd, simm); \
6568 tcg_temp_free_i32(simm); \
6569 tcg_temp_free_ptr(rd); \
6570 }
6571
27a4edb3
AJ		 6572#define GEN_VXFORM_UIMM(name, opc2, opc3) \
6573 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \
6574 { \
6575 TCGv_ptr rb, rd; \
6576 TCGv_i32 uimm; \
6577 if (unlikely(!ctx->altivec_enabled)) { \
6578 gen_exception(ctx, POWERPC_EXCP_VPU); \
6579 return; \
6580 } \
6581 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6582 rb = gen_avr_ptr(rB(ctx->opcode)); \
6583 rd = gen_avr_ptr(rD(ctx->opcode)); \
6584 gen_helper_##name (rd, rb, uimm); \
6585 tcg_temp_free_i32(uimm); \
6586 tcg_temp_free_ptr(rb); \
6587 tcg_temp_free_ptr(rd); \
6588 }
6589
e4e6bee7
AJ		 6590GEN_VXFORM_UIMM(vspltb, 6, 8);
6591GEN_VXFORM_UIMM(vsplth, 6, 9);
6592GEN_VXFORM_UIMM(vspltw, 6, 10);
e140632e
AJ		 6593GEN_VXFORM_UIMM(vcfux, 5, 12);
6594GEN_VXFORM_UIMM(vcfsx, 5, 13);
875b31db
AJ		 6595GEN_VXFORM_UIMM(vctuxs, 5, 14);
6596GEN_VXFORM_UIMM(vctsxs, 5, 15);
e4e6bee7 6597
cd633b10
AJ		 6598GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC)
6599{
6600 TCGv_ptr ra, rb, rd;
fce5ecb7 6601 TCGv_i32 sh;
cd633b10
AJ		 6602 if (unlikely(!ctx->altivec_enabled)) {
6603 gen_exception(ctx, POWERPC_EXCP_VPU);
6604 return;
6605 }
6606 ra = gen_avr_ptr(rA(ctx->opcode));
6607 rb = gen_avr_ptr(rB(ctx->opcode));
6608 rd = gen_avr_ptr(rD(ctx->opcode));
6609 sh = tcg_const_i32(VSH(ctx->opcode));
6610 gen_helper_vsldoi (rd, ra, rb, sh);
6611 tcg_temp_free_ptr(ra);
6612 tcg_temp_free_ptr(rb);
6613 tcg_temp_free_ptr(rd);
fce5ecb7 6614 tcg_temp_free_i32(sh);
cd633b10
AJ		 6615}
6616
707cec33
AJ		 6617#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6618 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC) \
6619 { \
6620 TCGv_ptr ra, rb, rc, rd; \
6621 if (unlikely(!ctx->altivec_enabled)) { \
6622 gen_exception(ctx, POWERPC_EXCP_VPU); \
6623 return; \
6624 } \
6625 ra = gen_avr_ptr(rA(ctx->opcode)); \
6626 rb = gen_avr_ptr(rB(ctx->opcode)); \
6627 rc = gen_avr_ptr(rC(ctx->opcode)); \
6628 rd = gen_avr_ptr(rD(ctx->opcode)); \
6629 if (Rc(ctx->opcode)) { \
6630 gen_helper_##name1 (rd, ra, rb, rc); \
6631 } else { \
6632 gen_helper_##name0 (rd, ra, rb, rc); \
6633 } \
6634 tcg_temp_free_ptr(ra); \
6635 tcg_temp_free_ptr(rb); \
6636 tcg_temp_free_ptr(rc); \
6637 tcg_temp_free_ptr(rd); \
6638 }
6639
b161ae27
AJ		 6640GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6641
bcd2ee23
AJ		 6642GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC)
6643{
6644 TCGv_ptr ra, rb, rc, rd;
6645 if (unlikely(!ctx->altivec_enabled)) {
6646 gen_exception(ctx, POWERPC_EXCP_VPU);
6647 return;
6648 }
6649 ra = gen_avr_ptr(rA(ctx->opcode));
6650 rb = gen_avr_ptr(rB(ctx->opcode));
6651 rc = gen_avr_ptr(rC(ctx->opcode));
6652 rd = gen_avr_ptr(rD(ctx->opcode));
6653 gen_helper_vmladduhm(rd, ra, rb, rc);
6654 tcg_temp_free_ptr(ra);
6655 tcg_temp_free_ptr(rb);
6656 tcg_temp_free_ptr(rc);
6657 tcg_temp_free_ptr(rd);
6658}
6659
b04ae981 6660GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
4d9903b6 6661GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
eae07261 6662GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
d1258698 6663GEN_VAFORM_PAIRED(vsel, vperm, 21)
35cf7c7e 6664GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
b04ae981 6665
0487d6a8 6666/*** SPE extension ***/
0487d6a8 6667/* Register moves */
3cd7d1dd 6668
a7812ae4 6669static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
f78fb44e
AJ		 6670#if defined(TARGET_PPC64)
6671 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6672#else
36aa55dc 6673 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 6674#endif
f78fb44e 6675}
3cd7d1dd 6676
a7812ae4 6677static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
f78fb44e
AJ		 6678#if defined(TARGET_PPC64)
6679 tcg_gen_mov_i64(cpu_gpr[reg], t);
6680#else
a7812ae4 6681 TCGv_i64 tmp = tcg_temp_new_i64();
f78fb44e 6682 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
f78fb44e
AJ		 6683 tcg_gen_shri_i64(tmp, t, 32);
6684 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
a7812ae4 6685 tcg_temp_free_i64(tmp);
3cd7d1dd 6686#endif
f78fb44e 6687}
3cd7d1dd 6688
0487d6a8
JM		 6689#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
6690GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
6691{ \
6692 if (Rc(ctx->opcode)) \
6693 gen_##name1(ctx); \
6694 else \
6695 gen_##name0(ctx); \
6696}
6697
6698/* Handler for undefined SPE opcodes */
b068d6a7 6699static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 6700{
e06fcd75 6701 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
0487d6a8
JM		 6702}
6703
57951c27
AJ		 6704/* SPE logic */
6705#if defined(TARGET_PPC64)
6706#define GEN_SPEOP_LOGIC2(name, tcg_op) \
b068d6a7 6707static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6708{ \
6709 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6710 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6711 return; \
6712 } \
57951c27
AJ		 6713 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6714 cpu_gpr[rB(ctx->opcode)]); \
6715}
6716#else
6717#define GEN_SPEOP_LOGIC2(name, tcg_op) \
6718static always_inline void gen_##name (DisasContext *ctx) \
6719{ \
6720 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6721 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6722 return; \
6723 } \
6724 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6725 cpu_gpr[rB(ctx->opcode)]); \
6726 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6727 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6728}
57951c27
AJ		 6729#endif
6730
6731GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6732GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6733GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6734GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6735GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6736GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6737GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6738GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
0487d6a8 6739
57951c27
AJ		 6740/* SPE logic immediate */
6741#if defined(TARGET_PPC64)
6742#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
3d3a6a0a
AJ		 6743static always_inline void gen_##name (DisasContext *ctx) \
6744{ \
6745 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6746 gen_exception(ctx, POWERPC_EXCP_APU); \
3d3a6a0a
AJ		 6747 return; \
6748 } \
a7812ae4
PB		 6749 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6750 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6751 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6752 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6753 tcg_opi(t0, t0, rB(ctx->opcode)); \
6754 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6755 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6756 tcg_temp_free_i64(t2); \
57951c27
AJ		 6757 tcg_opi(t1, t1, rB(ctx->opcode)); \
6758 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6759 tcg_temp_free_i32(t0); \
6760 tcg_temp_free_i32(t1); \
3d3a6a0a 6761}
57951c27
AJ		 6762#else
6763#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
b068d6a7 6764static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6765{ \
6766 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6767 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6768 return; \
6769 } \
57951c27
AJ		 6770 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6771 rB(ctx->opcode)); \
6772 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6773 rB(ctx->opcode)); \
0487d6a8 6774}
57951c27
AJ		 6775#endif
6776GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6777GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6778GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6779GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
0487d6a8 6780
57951c27
AJ		 6781/* SPE arithmetic */
6782#if defined(TARGET_PPC64)
6783#define GEN_SPEOP_ARITH1(name, tcg_op) \
b068d6a7 6784static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6785{ \
6786 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6787 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6788 return; \
6789 } \
a7812ae4
PB		 6790 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6791 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6792 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6793 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6794 tcg_op(t0, t0); \
6795 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6796 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 6797 tcg_temp_free_i64(t2); \
57951c27
AJ		 6798 tcg_op(t1, t1); \
6799 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6800 tcg_temp_free_i32(t0); \
6801 tcg_temp_free_i32(t1); \
0487d6a8 6802}
57951c27 6803#else
a7812ae4 6804#define GEN_SPEOP_ARITH1(name, tcg_op) \
57951c27
AJ		 6805static always_inline void gen_##name (DisasContext *ctx) \
6806{ \
6807 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6808 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6809 return; \
6810 } \
6811 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6812 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6813}
6814#endif
0487d6a8 6815
a7812ae4 6816static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
57951c27
AJ		 6817{
6818 int l1 = gen_new_label();
6819 int l2 = gen_new_label();
0487d6a8 6820
57951c27
AJ		 6821 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6822 tcg_gen_neg_i32(ret, arg1);
6823 tcg_gen_br(l2);
6824 gen_set_label(l1);
a7812ae4 6825 tcg_gen_mov_i32(ret, arg1);
57951c27
AJ		 6826 gen_set_label(l2);
6827}
6828GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6829GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6830GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6831GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
a7812ae4 6832static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
0487d6a8 6833{
57951c27
AJ		 6834 tcg_gen_addi_i32(ret, arg1, 0x8000);
6835 tcg_gen_ext16u_i32(ret, ret);
6836}
6837GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
a7812ae4
PB		 6838GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6839GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
0487d6a8 6840
57951c27
AJ		 6841#if defined(TARGET_PPC64)
6842#define GEN_SPEOP_ARITH2(name, tcg_op) \
6843static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6844{ \
6845 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6846 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6847 return; \
6848 } \
a7812ae4
PB		 6849 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6850 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6851 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
501e23c4 6852 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6853 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6854 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6855 tcg_op(t0, t0, t2); \
6856 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6857 tcg_gen_trunc_i64_i32(t1, t3); \
6858 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6859 tcg_gen_trunc_i64_i32(t2, t3); \
a7812ae4 6860 tcg_temp_free_i64(t3); \
57951c27 6861 tcg_op(t1, t1, t2); \
a7812ae4 6862 tcg_temp_free_i32(t2); \
57951c27 6863 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6864 tcg_temp_free_i32(t0); \
6865 tcg_temp_free_i32(t1); \
0487d6a8 6866}
57951c27
AJ		 6867#else
6868#define GEN_SPEOP_ARITH2(name, tcg_op) \
6869static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6870{ \
6871 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6872 gen_exception(ctx, POWERPC_EXCP_APU); \
0487d6a8
JM		 6873 return; \
6874 } \
57951c27
AJ		 6875 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6876 cpu_gpr[rB(ctx->opcode)]); \
6877 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6878 cpu_gprh[rB(ctx->opcode)]); \
0487d6a8 6879}
57951c27 6880#endif
0487d6a8 6881
a7812ae4 6882static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6883{
a7812ae4 6884 TCGv_i32 t0;
57951c27 6885 int l1, l2;
0487d6a8 6886
57951c27
AJ		 6887 l1 = gen_new_label();
6888 l2 = gen_new_label();
a7812ae4 6889 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6890 /* No error here: 6 bits are used */
6891 tcg_gen_andi_i32(t0, arg2, 0x3F);
6892 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6893 tcg_gen_shr_i32(ret, arg1, t0);
6894 tcg_gen_br(l2);
6895 gen_set_label(l1);
6896 tcg_gen_movi_i32(ret, 0);
6897 tcg_gen_br(l2);
a7812ae4 6898 tcg_temp_free_i32(t0);
57951c27
AJ		 6899}
6900GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
a7812ae4 6901static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6902{
a7812ae4 6903 TCGv_i32 t0;
57951c27
AJ		 6904 int l1, l2;
6905
6906 l1 = gen_new_label();
6907 l2 = gen_new_label();
a7812ae4 6908 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6909 /* No error here: 6 bits are used */
6910 tcg_gen_andi_i32(t0, arg2, 0x3F);
6911 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6912 tcg_gen_sar_i32(ret, arg1, t0);
6913 tcg_gen_br(l2);
6914 gen_set_label(l1);
6915 tcg_gen_movi_i32(ret, 0);
6916 tcg_gen_br(l2);
a7812ae4 6917 tcg_temp_free_i32(t0);
57951c27
AJ		 6918}
6919GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
a7812ae4 6920static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6921{
a7812ae4 6922 TCGv_i32 t0;
57951c27
AJ		 6923 int l1, l2;
6924
6925 l1 = gen_new_label();
6926 l2 = gen_new_label();
a7812ae4 6927 t0 = tcg_temp_local_new_i32();
57951c27
AJ		 6928 /* No error here: 6 bits are used */
6929 tcg_gen_andi_i32(t0, arg2, 0x3F);
6930 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
6931 tcg_gen_shl_i32(ret, arg1, t0);
6932 tcg_gen_br(l2);
6933 gen_set_label(l1);
6934 tcg_gen_movi_i32(ret, 0);
6935 tcg_gen_br(l2);
a7812ae4 6936 tcg_temp_free_i32(t0);
57951c27
AJ		 6937}
6938GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
a7812ae4 6939static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
57951c27 6940{
a7812ae4 6941 TCGv_i32 t0 = tcg_temp_new_i32();
57951c27
AJ		 6942 tcg_gen_andi_i32(t0, arg2, 0x1F);
6943 tcg_gen_rotl_i32(ret, arg1, t0);
a7812ae4 6944 tcg_temp_free_i32(t0);
57951c27
AJ		 6945}
6946GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
6947static always_inline void gen_evmergehi (DisasContext *ctx)
6948{
6949 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 6950 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 6951 return;
6952 }
6953#if defined(TARGET_PPC64)
a7812ae4
PB		 6954 TCGv t0 = tcg_temp_new();
6955 TCGv t1 = tcg_temp_new();
57951c27
AJ		 6956 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
6957 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
6958 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
6959 tcg_temp_free(t0);
6960 tcg_temp_free(t1);
6961#else
6962 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6963 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6964#endif
6965}
6966GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
a7812ae4 6967static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
0487d6a8 6968{
57951c27
AJ		 6969 tcg_gen_sub_i32(ret, arg2, arg1);
6970}
6971GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
0487d6a8 6972
57951c27
AJ		 6973/* SPE arithmetic immediate */
6974#if defined(TARGET_PPC64)
6975#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6976static always_inline void gen_##name (DisasContext *ctx) \
6977{ \
6978 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 6979 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 6980 return; \
6981 } \
a7812ae4
PB		 6982 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6983 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6984 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 6985 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
6986 tcg_op(t0, t0, rA(ctx->opcode)); \
6987 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
6988 tcg_gen_trunc_i64_i32(t1, t2); \
e06fcd75 6989 tcg_temp_free_i64(t2); \
57951c27
AJ		 6990 tcg_op(t1, t1, rA(ctx->opcode)); \
6991 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
a7812ae4
PB		 6992 tcg_temp_free_i32(t0); \
6993 tcg_temp_free_i32(t1); \
57951c27
AJ		 6994}
6995#else
6996#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
6997static always_inline void gen_##name (DisasContext *ctx) \
6998{ \
6999 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7000 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7001 return; \
7002 } \
7003 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7004 rA(ctx->opcode)); \
7005 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7006 rA(ctx->opcode)); \
7007}
7008#endif
7009GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7010GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7011
7012/* SPE comparison */
7013#if defined(TARGET_PPC64)
7014#define GEN_SPEOP_COMP(name, tcg_cond) \
7015static always_inline void gen_##name (DisasContext *ctx) \
7016{ \
7017 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7018 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7019 return; \
7020 } \
7021 int l1 = gen_new_label(); \
7022 int l2 = gen_new_label(); \
7023 int l3 = gen_new_label(); \
7024 int l4 = gen_new_label(); \
a7812ae4
PB		 7025 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7026 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7027 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
57951c27
AJ		 7028 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7029 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7030 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
a7812ae4 7031 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
57951c27
AJ		 7032 tcg_gen_br(l2); \
7033 gen_set_label(l1); \
7034 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7035 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7036 gen_set_label(l2); \
7037 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7038 tcg_gen_trunc_i64_i32(t0, t2); \
7039 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7040 tcg_gen_trunc_i64_i32(t1, t2); \
a7812ae4 7041 tcg_temp_free_i64(t2); \
57951c27
AJ		 7042 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7043 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7044 ~(CRF_CH | CRF_CH_AND_CL)); \
7045 tcg_gen_br(l4); \
7046 gen_set_label(l3); \
7047 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7048 CRF_CH | CRF_CH_OR_CL); \
7049 gen_set_label(l4); \
a7812ae4
PB		 7050 tcg_temp_free_i32(t0); \
7051 tcg_temp_free_i32(t1); \
57951c27
AJ		 7052}
7053#else
7054#define GEN_SPEOP_COMP(name, tcg_cond) \
7055static always_inline void gen_##name (DisasContext *ctx) \
7056{ \
7057 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7058 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7059 return; \
7060 } \
7061 int l1 = gen_new_label(); \
7062 int l2 = gen_new_label(); \
7063 int l3 = gen_new_label(); \
7064 int l4 = gen_new_label(); \
7065 \
7066 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7067 cpu_gpr[rB(ctx->opcode)], l1); \
7068 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7069 tcg_gen_br(l2); \
7070 gen_set_label(l1); \
7071 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7072 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7073 gen_set_label(l2); \
7074 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7075 cpu_gprh[rB(ctx->opcode)], l3); \
7076 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7077 ~(CRF_CH | CRF_CH_AND_CL)); \
7078 tcg_gen_br(l4); \
7079 gen_set_label(l3); \
7080 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7081 CRF_CH | CRF_CH_OR_CL); \
7082 gen_set_label(l4); \
7083}
7084#endif
7085GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7086GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7087GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7088GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7089GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7090
7091/* SPE misc */
7092static always_inline void gen_brinc (DisasContext *ctx)
7093{
7094 /* Note: brinc is usable even if SPE is disabled */
a7812ae4
PB		 7095 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7096 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 7097}
57951c27
AJ		 7098static always_inline void gen_evmergelo (DisasContext *ctx)
7099{
7100 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7101 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7102 return;
7103 }
7104#if defined(TARGET_PPC64)
a7812ae4
PB		 7105 TCGv t0 = tcg_temp_new();
7106 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7107 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7108 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7109 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7110 tcg_temp_free(t0);
7111 tcg_temp_free(t1);
7112#else
7113 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7114 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7115#endif
7116}
7117static always_inline void gen_evmergehilo (DisasContext *ctx)
7118{
7119 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7120 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7121 return;
7122 }
7123#if defined(TARGET_PPC64)
a7812ae4
PB		 7124 TCGv t0 = tcg_temp_new();
7125 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7126 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL);
7127 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7128 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7129 tcg_temp_free(t0);
7130 tcg_temp_free(t1);
7131#else
7132 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7133 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7134#endif
7135}
7136static always_inline void gen_evmergelohi (DisasContext *ctx)
7137{
7138 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7139 gen_exception(ctx, POWERPC_EXCP_APU);
57951c27
AJ		 7140 return;
7141 }
7142#if defined(TARGET_PPC64)
a7812ae4
PB		 7143 TCGv t0 = tcg_temp_new();
7144 TCGv t1 = tcg_temp_new();
57951c27
AJ		 7145 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7146 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7147 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7148 tcg_temp_free(t0);
7149 tcg_temp_free(t1);
7150#else
7151 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7152 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7153#endif
7154}
7155static always_inline void gen_evsplati (DisasContext *ctx)
7156{
38d14952 7157 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
0487d6a8 7158
57951c27 7159#if defined(TARGET_PPC64)
38d14952 7160 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7161#else
7162 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7163 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7164#endif
7165}
b068d6a7 7166static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8 7167{
38d14952 7168 uint64_t imm = rA(ctx->opcode) << 11;
0487d6a8 7169
57951c27 7170#if defined(TARGET_PPC64)
38d14952 7171 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
57951c27
AJ		 7172#else
7173 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7174 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7175#endif
0487d6a8
JM		 7176}
7177
57951c27
AJ		 7178static always_inline void gen_evsel (DisasContext *ctx)
7179{
7180 int l1 = gen_new_label();
7181 int l2 = gen_new_label();
7182 int l3 = gen_new_label();
7183 int l4 = gen_new_label();
a7812ae4 7184 TCGv_i32 t0 = tcg_temp_local_new_i32();
57951c27 7185#if defined(TARGET_PPC64)
a7812ae4
PB		 7186 TCGv t1 = tcg_temp_local_new();
7187 TCGv t2 = tcg_temp_local_new();
57951c27
AJ		 7188#endif
7189 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7190 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7191#if defined(TARGET_PPC64)
7192 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7193#else
7194 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7195#endif
7196 tcg_gen_br(l2);
7197 gen_set_label(l1);
7198#if defined(TARGET_PPC64)
7199 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7200#else
7201 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7202#endif
7203 gen_set_label(l2);
7204 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7205 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7206#if defined(TARGET_PPC64)
7207 tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL);
7208#else
7209 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7210#endif
7211 tcg_gen_br(l4);
7212 gen_set_label(l3);
7213#if defined(TARGET_PPC64)
7214 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL);
7215#else
7216 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7217#endif
7218 gen_set_label(l4);
a7812ae4 7219 tcg_temp_free_i32(t0);
57951c27
AJ		 7220#if defined(TARGET_PPC64)
7221 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7222 tcg_temp_free(t1);
7223 tcg_temp_free(t2);
7224#endif
7225}
7226GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
7227{
7228 gen_evsel(ctx);
7229}
7230GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
7231{
7232 gen_evsel(ctx);
7233}
7234GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
7235{
7236 gen_evsel(ctx);
7237}
7238GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
7239{
7240 gen_evsel(ctx);
7241}
0487d6a8
JM		 7242
7243GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
7244GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
7245GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
7246GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
7247GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
7248GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
7249GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
7250GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
7251GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
7252GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
7253GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
7254GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
7255GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
7256GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
7257GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
7258GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
7259GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
7260GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
7261GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
7262GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
7263GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
7264GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
7265GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
7266GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
7267GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
7268
6a6ae23f 7269/* SPE load and stores */
76db3ba4 7270static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
6a6ae23f
AJ		 7271{
7272 target_ulong uimm = rB(ctx->opcode);
7273
76db3ba4 7274 if (rA(ctx->opcode) == 0) {
6a6ae23f 7275 tcg_gen_movi_tl(EA, uimm << sh);
76db3ba4 7276 } else {
6a6ae23f 7277 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
76db3ba4
AJ		 7278#if defined(TARGET_PPC64)
7279 if (!ctx->sf_mode) {
7280 tcg_gen_ext32u_tl(EA, EA);
7281 }
7282#endif
7283 }
0487d6a8 7284}
6a6ae23f
AJ		 7285
7286static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7287{
7288#if defined(TARGET_PPC64)
76db3ba4 7289 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7290#else
7291 TCGv_i64 t0 = tcg_temp_new_i64();
76db3ba4 7292 gen_qemu_ld64(ctx, t0, addr);
6a6ae23f
AJ		 7293 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7294 tcg_gen_shri_i64(t0, t0, 32);
7295 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7296 tcg_temp_free_i64(t0);
7297#endif
0487d6a8 7298}
6a6ae23f
AJ		 7299
7300static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7301{
0487d6a8 7302#if defined(TARGET_PPC64)
6a6ae23f 7303 TCGv t0 = tcg_temp_new();
76db3ba4 7304 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f 7305 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
76db3ba4
AJ		 7306 gen_addr_add(ctx, addr, addr, 4);
7307 gen_qemu_ld32u(ctx, t0, addr);
6a6ae23f
AJ		 7308 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7309 tcg_temp_free(t0);
7310#else
76db3ba4
AJ		 7311 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7312 gen_addr_add(ctx, addr, addr, 4);
7313 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f 7314#endif
0487d6a8 7315}
6a6ae23f
AJ		 7316
7317static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7318{
7319 TCGv t0 = tcg_temp_new();
7320#if defined(TARGET_PPC64)
76db3ba4 7321 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7322 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7323 gen_addr_add(ctx, addr, addr, 2);
7324 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7325 tcg_gen_shli_tl(t0, t0, 32);
7326 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7327 gen_addr_add(ctx, addr, addr, 2);
7328 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7329 tcg_gen_shli_tl(t0, t0, 16);
7330 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7331 gen_addr_add(ctx, addr, addr, 2);
7332 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7333 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7334#else
76db3ba4 7335 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7336 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7337 gen_addr_add(ctx, addr, addr, 2);
7338 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7339 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7340 gen_addr_add(ctx, addr, addr, 2);
7341 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7342 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7343 gen_addr_add(ctx, addr, addr, 2);
7344 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7345 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
0487d6a8 7346#endif
6a6ae23f 7347 tcg_temp_free(t0);
0487d6a8
JM		 7348}
7349
6a6ae23f
AJ		 7350static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7351{
7352 TCGv t0 = tcg_temp_new();
76db3ba4 7353 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7354#if defined(TARGET_PPC64)
7355 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7356 tcg_gen_shli_tl(t0, t0, 16);
7357 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7358#else
7359 tcg_gen_shli_tl(t0, t0, 16);
7360 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7361 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7362#endif
7363 tcg_temp_free(t0);
0487d6a8
JM		 7364}
7365
6a6ae23f
AJ		 7366static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7367{
7368 TCGv t0 = tcg_temp_new();
76db3ba4 7369 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7370#if defined(TARGET_PPC64)
7371 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7372 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7373#else
7374 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7375 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7376#endif
7377 tcg_temp_free(t0);
0487d6a8
JM		 7378}
7379
6a6ae23f
AJ		 7380static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7381{
7382 TCGv t0 = tcg_temp_new();
76db3ba4 7383 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7384#if defined(TARGET_PPC64)
7385 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7386 tcg_gen_ext32u_tl(t0, t0);
7387 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7388#else
7389 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7390 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7391#endif
7392 tcg_temp_free(t0);
7393}
7394
7395static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7396{
7397 TCGv t0 = tcg_temp_new();
7398#if defined(TARGET_PPC64)
76db3ba4 7399 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7400 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
76db3ba4
AJ		 7401 gen_addr_add(ctx, addr, addr, 2);
7402 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7403 tcg_gen_shli_tl(t0, t0, 16);
7404 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7405#else
76db3ba4 7406 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f 7407 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
76db3ba4
AJ		 7408 gen_addr_add(ctx, addr, addr, 2);
7409 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7410 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7411#endif
7412 tcg_temp_free(t0);
7413}
7414
7415static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7416{
7417#if defined(TARGET_PPC64)
7418 TCGv t0 = tcg_temp_new();
76db3ba4
AJ		 7419 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7420 gen_addr_add(ctx, addr, addr, 2);
7421 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7422 tcg_gen_shli_tl(t0, t0, 32);
7423 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7424 tcg_temp_free(t0);
7425#else
76db3ba4
AJ		 7426 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7427 gen_addr_add(ctx, addr, addr, 2);
7428 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7429#endif
7430}
7431
7432static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7433{
7434#if defined(TARGET_PPC64)
7435 TCGv t0 = tcg_temp_new();
76db3ba4 7436 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f 7437 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7438 gen_addr_add(ctx, addr, addr, 2);
7439 gen_qemu_ld16s(ctx, t0, addr);
6a6ae23f
AJ		 7440 tcg_gen_shli_tl(t0, t0, 32);
7441 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7442 tcg_temp_free(t0);
7443#else
76db3ba4
AJ		 7444 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7445 gen_addr_add(ctx, addr, addr, 2);
7446 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
6a6ae23f
AJ		 7447#endif
7448}
7449
7450static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7451{
7452 TCGv t0 = tcg_temp_new();
76db3ba4 7453 gen_qemu_ld32u(ctx, t0, addr);
0487d6a8 7454#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7455 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7456 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7457#else
7458 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7459 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7460#endif
7461 tcg_temp_free(t0);
7462}
7463
7464static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7465{
7466 TCGv t0 = tcg_temp_new();
7467#if defined(TARGET_PPC64)
76db3ba4 7468 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7469 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7470 tcg_gen_shli_tl(t0, t0, 32);
7471 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7472 gen_addr_add(ctx, addr, addr, 2);
7473 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7474 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7475 tcg_gen_shli_tl(t0, t0, 16);
7476 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7477#else
76db3ba4 7478 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7479 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7480 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
76db3ba4
AJ		 7481 gen_addr_add(ctx, addr, addr, 2);
7482 gen_qemu_ld16u(ctx, t0, addr);
6a6ae23f
AJ		 7483 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7484 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
0487d6a8 7485#endif
6a6ae23f
AJ		 7486 tcg_temp_free(t0);
7487}
7488
7489static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7490{
7491#if defined(TARGET_PPC64)
76db3ba4 7492 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
0487d6a8 7493#else
6a6ae23f
AJ		 7494 TCGv_i64 t0 = tcg_temp_new_i64();
7495 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
76db3ba4 7496 gen_qemu_st64(ctx, t0, addr);
6a6ae23f
AJ		 7497 tcg_temp_free_i64(t0);
7498#endif
7499}
7500
7501static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7502{
0487d6a8 7503#if defined(TARGET_PPC64)
6a6ae23f
AJ		 7504 TCGv t0 = tcg_temp_new();
7505 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7506 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7507 tcg_temp_free(t0);
7508#else
76db3ba4 7509 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7510#endif
76db3ba4
AJ		 7511 gen_addr_add(ctx, addr, addr, 4);
7512 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7513}
7514
7515static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7516{
7517 TCGv t0 = tcg_temp_new();
7518#if defined(TARGET_PPC64)
7519 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7520#else
7521 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7522#endif
76db3ba4
AJ		 7523 gen_qemu_st16(ctx, t0, addr);
7524 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f
AJ		 7525#if defined(TARGET_PPC64)
7526 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7527 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7528#else
76db3ba4 7529 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7530#endif
76db3ba4 7531 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7532 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7533 gen_qemu_st16(ctx, t0, addr);
6a6ae23f 7534 tcg_temp_free(t0);
76db3ba4
AJ		 7535 gen_addr_add(ctx, addr, addr, 2);
7536 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7537}
7538
7539static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7540{
7541 TCGv t0 = tcg_temp_new();
7542#if defined(TARGET_PPC64)
7543 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7544#else
7545 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7546#endif
76db3ba4
AJ		 7547 gen_qemu_st16(ctx, t0, addr);
7548 gen_addr_add(ctx, addr, addr, 2);
6a6ae23f 7549 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
76db3ba4 7550 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7551 tcg_temp_free(t0);
7552}
7553
7554static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7555{
7556#if defined(TARGET_PPC64)
7557 TCGv t0 = tcg_temp_new();
7558 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7559 gen_qemu_st16(ctx, t0, addr);
6a6ae23f
AJ		 7560 tcg_temp_free(t0);
7561#else
76db3ba4 7562 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f 7563#endif
76db3ba4
AJ		 7564 gen_addr_add(ctx, addr, addr, 2);
7565 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7566}
7567
7568static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7569{
7570#if defined(TARGET_PPC64)
7571 TCGv t0 = tcg_temp_new();
7572 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
76db3ba4 7573 gen_qemu_st32(ctx, t0, addr);
6a6ae23f
AJ		 7574 tcg_temp_free(t0);
7575#else
76db3ba4 7576 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7577#endif
7578}
7579
7580static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7581{
76db3ba4 7582 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
6a6ae23f
AJ		 7583}
7584
7585#define GEN_SPEOP_LDST(name, opc2, sh) \
76db3ba4 7586GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE) \
6a6ae23f
AJ		 7587{ \
7588 TCGv t0; \
7589 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7590 gen_exception(ctx, POWERPC_EXCP_APU); \
6a6ae23f
AJ		 7591 return; \
7592 } \
76db3ba4 7593 gen_set_access_type(ctx, ACCESS_INT); \
6a6ae23f
AJ		 7594 t0 = tcg_temp_new(); \
7595 if (Rc(ctx->opcode)) { \
76db3ba4 7596 gen_addr_spe_imm_index(ctx, t0, sh); \
6a6ae23f 7597 } else { \
76db3ba4 7598 gen_addr_reg_index(ctx, t0); \
6a6ae23f
AJ		 7599 } \
7600 gen_op_##name(ctx, t0); \
7601 tcg_temp_free(t0); \
7602}
7603
7604GEN_SPEOP_LDST(evldd, 0x00, 3);
7605GEN_SPEOP_LDST(evldw, 0x01, 3);
7606GEN_SPEOP_LDST(evldh, 0x02, 3);
7607GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7608GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7609GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7610GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7611GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7612GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7613GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7614GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7615
7616GEN_SPEOP_LDST(evstdd, 0x10, 3);
7617GEN_SPEOP_LDST(evstdw, 0x11, 3);
7618GEN_SPEOP_LDST(evstdh, 0x12, 3);
7619GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7620GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7621GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7622GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
0487d6a8
JM		 7623
7624/* Multiply and add - TODO */
7625#if 0
7626GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
7627GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
7628GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
7629GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
7630GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
7631GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
7632GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
7633GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
7634GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
7635GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
7636GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
7637GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
7638
7639GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
7640GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
7641GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
7642GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
7643GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
7644GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
7645GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
7646GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
7647GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
7648GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
7649GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
7650GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
7651GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
7652GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
7653
7654GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
7655GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
7656GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
7657GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
7658GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
7659GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
7660
7661GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
7662GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
7663GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
7664GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
7665GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
7666GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
7667GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
7668GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
7669GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
7670GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
7671GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
7672GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
7673
7674GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
7675GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
7676GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
7677GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
7678GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
7679
7680GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
7681GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
7682GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
7683GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
7684GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
7685GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
7686GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
7687GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
7688GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
7689GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
7690GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
7691GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
7692
7693GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
7694GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
7695GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
7696GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
7697GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
7698#endif
7699
7700/*** SPE floating-point extension ***/
1c97856d
AJ		 7701#if defined(TARGET_PPC64)
7702#define GEN_SPEFPUOP_CONV_32_32(name) \
b068d6a7 7703static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 7704{ \
1c97856d
AJ		 7705 TCGv_i32 t0; \
7706 TCGv t1; \
7707 t0 = tcg_temp_new_i32(); \
7708 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7709 gen_helper_##name(t0, t0); \
7710 t1 = tcg_temp_new(); \
7711 tcg_gen_extu_i32_tl(t1, t0); \
7712 tcg_temp_free_i32(t0); \
7713 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7714 0xFFFFFFFF00000000ULL); \
7715 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7716 tcg_temp_free(t1); \
0487d6a8 7717}
1c97856d
AJ		 7718#define GEN_SPEFPUOP_CONV_32_64(name) \
7719static always_inline void gen_##name (DisasContext *ctx) \
7720{ \
7721 TCGv_i32 t0; \
7722 TCGv t1; \
7723 t0 = tcg_temp_new_i32(); \
7724 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7725 t1 = tcg_temp_new(); \
7726 tcg_gen_extu_i32_tl(t1, t0); \
7727 tcg_temp_free_i32(t0); \
7728 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7729 0xFFFFFFFF00000000ULL); \
7730 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
7731 tcg_temp_free(t1); \
7732}
7733#define GEN_SPEFPUOP_CONV_64_32(name) \
7734static always_inline void gen_##name (DisasContext *ctx) \
7735{ \
7736 TCGv_i32 t0 = tcg_temp_new_i32(); \
7737 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7738 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7739 tcg_temp_free_i32(t0); \
7740}
7741#define GEN_SPEFPUOP_CONV_64_64(name) \
7742static always_inline void gen_##name (DisasContext *ctx) \
7743{ \
7744 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7745}
7746#define GEN_SPEFPUOP_ARITH2_32_32(name) \
57951c27
AJ		 7747static always_inline void gen_##name (DisasContext *ctx) \
7748{ \
1c97856d
AJ		 7749 TCGv_i32 t0, t1; \
7750 TCGv_i64 t2; \
57951c27 7751 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7752 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7753 return; \
7754 } \
1c97856d
AJ		 7755 t0 = tcg_temp_new_i32(); \
7756 t1 = tcg_temp_new_i32(); \
7757 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7758 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7759 gen_helper_##name(t0, t0, t1); \
7760 tcg_temp_free_i32(t1); \
7761 t2 = tcg_temp_new(); \
7762 tcg_gen_extu_i32_tl(t2, t0); \
7763 tcg_temp_free_i32(t0); \
7764 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
7765 0xFFFFFFFF00000000ULL); \
7766 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
7767 tcg_temp_free(t2); \
57951c27 7768}
1c97856d 7769#define GEN_SPEFPUOP_ARITH2_64_64(name) \
57951c27
AJ		 7770static always_inline void gen_##name (DisasContext *ctx) \
7771{ \
7772 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7773 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7774 return; \
7775 } \
1c97856d
AJ		 7776 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7777 cpu_gpr[rB(ctx->opcode)]); \
57951c27 7778}
1c97856d 7779#define GEN_SPEFPUOP_COMP_32(name) \
57951c27
AJ		 7780static always_inline void gen_##name (DisasContext *ctx) \
7781{ \
1c97856d 7782 TCGv_i32 t0, t1; \
57951c27 7783 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7784 gen_exception(ctx, POWERPC_EXCP_APU); \
57951c27
AJ		 7785 return; \
7786 } \
1c97856d
AJ		 7787 t0 = tcg_temp_new_i32(); \
7788 t1 = tcg_temp_new_i32(); \
7789 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7790 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7791 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7792 tcg_temp_free_i32(t0); \
7793 tcg_temp_free_i32(t1); \
7794}
7795#define GEN_SPEFPUOP_COMP_64(name) \
7796static always_inline void gen_##name (DisasContext *ctx) \
7797{ \
7798 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7799 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7800 return; \
7801 } \
7802 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7803 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7804}
7805#else
7806#define GEN_SPEFPUOP_CONV_32_32(name) \
7807static always_inline void gen_##name (DisasContext *ctx) \
7808{ \
7809 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
57951c27 7810}
1c97856d
AJ		 7811#define GEN_SPEFPUOP_CONV_32_64(name) \
7812static always_inline void gen_##name (DisasContext *ctx) \
7813{ \
7814 TCGv_i64 t0 = tcg_temp_new_i64(); \
7815 gen_load_gpr64(t0, rB(ctx->opcode)); \
7816 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \
7817 tcg_temp_free_i64(t0); \
7818}
7819#define GEN_SPEFPUOP_CONV_64_32(name) \
7820static always_inline void gen_##name (DisasContext *ctx) \
7821{ \
7822 TCGv_i64 t0 = tcg_temp_new_i64(); \
7823 gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
7824 gen_store_gpr64(rD(ctx->opcode), t0); \
7825 tcg_temp_free_i64(t0); \
7826}
7827#define GEN_SPEFPUOP_CONV_64_64(name) \
7828static always_inline void gen_##name (DisasContext *ctx) \
7829{ \
7830 TCGv_i64 t0 = tcg_temp_new_i64(); \
7831 gen_load_gpr64(t0, rB(ctx->opcode)); \
7832 gen_helper_##name(t0, t0); \
7833 gen_store_gpr64(rD(ctx->opcode), t0); \
7834 tcg_temp_free_i64(t0); \
7835}
7836#define GEN_SPEFPUOP_ARITH2_32_32(name) \
7837static always_inline void gen_##name (DisasContext *ctx) \
7838{ \
7839 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7840 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7841 return; \
7842 } \
7843 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \
7844 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7845}
7846#define GEN_SPEFPUOP_ARITH2_64_64(name) \
7847static always_inline void gen_##name (DisasContext *ctx) \
7848{ \
7849 TCGv_i64 t0, t1; \
7850 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7851 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7852 return; \
7853 } \
7854 t0 = tcg_temp_new_i64(); \
7855 t1 = tcg_temp_new_i64(); \
7856 gen_load_gpr64(t0, rA(ctx->opcode)); \
7857 gen_load_gpr64(t1, rB(ctx->opcode)); \
7858 gen_helper_##name(t0, t0, t1); \
7859 gen_store_gpr64(rD(ctx->opcode), t0); \
7860 tcg_temp_free_i64(t0); \
7861 tcg_temp_free_i64(t1); \
7862}
7863#define GEN_SPEFPUOP_COMP_32(name) \
7864static always_inline void gen_##name (DisasContext *ctx) \
7865{ \
7866 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7867 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7868 return; \
7869 } \
7870 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
7871 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
7872}
7873#define GEN_SPEFPUOP_COMP_64(name) \
7874static always_inline void gen_##name (DisasContext *ctx) \
7875{ \
7876 TCGv_i64 t0, t1; \
7877 if (unlikely(!ctx->spe_enabled)) { \
e06fcd75 7878 gen_exception(ctx, POWERPC_EXCP_APU); \
1c97856d
AJ		 7879 return; \
7880 } \
7881 t0 = tcg_temp_new_i64(); \
7882 t1 = tcg_temp_new_i64(); \
7883 gen_load_gpr64(t0, rA(ctx->opcode)); \
7884 gen_load_gpr64(t1, rB(ctx->opcode)); \
7885 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \
7886 tcg_temp_free_i64(t0); \
7887 tcg_temp_free_i64(t1); \
7888}
7889#endif
57951c27 7890
0487d6a8
JM		 7891/* Single precision floating-point vectors operations */
7892/* Arithmetic */
1c97856d
AJ		 7893GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
7894GEN_SPEFPUOP_ARITH2_64_64(evfssub);
7895GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
7896GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
7897static always_inline void gen_evfsabs (DisasContext *ctx)
7898{
7899 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7900 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7901 return;
7902 }
7903#if defined(TARGET_PPC64)
7904 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
7905#else
7906 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
7907 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
7908#endif
7909}
7910static always_inline void gen_evfsnabs (DisasContext *ctx)
7911{
7912 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7913 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7914 return;
7915 }
7916#if defined(TARGET_PPC64)
7917 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7918#else
7919 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7920 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7921#endif
7922}
7923static always_inline void gen_evfsneg (DisasContext *ctx)
7924{
7925 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7926 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7927 return;
7928 }
7929#if defined(TARGET_PPC64)
7930 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
7931#else
7932 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7933 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
7934#endif
7935}
7936
0487d6a8 7937/* Conversion */
1c97856d
AJ		 7938GEN_SPEFPUOP_CONV_64_64(evfscfui);
7939GEN_SPEFPUOP_CONV_64_64(evfscfsi);
7940GEN_SPEFPUOP_CONV_64_64(evfscfuf);
7941GEN_SPEFPUOP_CONV_64_64(evfscfsf);
7942GEN_SPEFPUOP_CONV_64_64(evfsctui);
7943GEN_SPEFPUOP_CONV_64_64(evfsctsi);
7944GEN_SPEFPUOP_CONV_64_64(evfsctuf);
7945GEN_SPEFPUOP_CONV_64_64(evfsctsf);
7946GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
7947GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
7948
0487d6a8 7949/* Comparison */
1c97856d
AJ		 7950GEN_SPEFPUOP_COMP_64(evfscmpgt);
7951GEN_SPEFPUOP_COMP_64(evfscmplt);
7952GEN_SPEFPUOP_COMP_64(evfscmpeq);
7953GEN_SPEFPUOP_COMP_64(evfststgt);
7954GEN_SPEFPUOP_COMP_64(evfststlt);
7955GEN_SPEFPUOP_COMP_64(evfststeq);
0487d6a8
JM		 7956
7957/* Opcodes definitions */
40569b7e
AJ		 7958GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7959GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7960GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); //
7961GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); //
7962GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7963GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7964GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7965GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7966GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7967GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7968GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7969GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); //
7970GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
7971GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 7972
7973/* Single precision floating-point operations */
7974/* Arithmetic */
1c97856d
AJ		 7975GEN_SPEFPUOP_ARITH2_32_32(efsadd);
7976GEN_SPEFPUOP_ARITH2_32_32(efssub);
7977GEN_SPEFPUOP_ARITH2_32_32(efsmul);
7978GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
7979static always_inline void gen_efsabs (DisasContext *ctx)
7980{
7981 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7982 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7983 return;
7984 }
7985 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
7986}
7987static always_inline void gen_efsnabs (DisasContext *ctx)
7988{
7989 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7990 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7991 return;
7992 }
7993 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
7994}
7995static always_inline void gen_efsneg (DisasContext *ctx)
7996{
7997 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 7998 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 7999 return;
8000 }
8001 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8002}
8003
0487d6a8 8004/* Conversion */
1c97856d
AJ		 8005GEN_SPEFPUOP_CONV_32_32(efscfui);
8006GEN_SPEFPUOP_CONV_32_32(efscfsi);
8007GEN_SPEFPUOP_CONV_32_32(efscfuf);
8008GEN_SPEFPUOP_CONV_32_32(efscfsf);
8009GEN_SPEFPUOP_CONV_32_32(efsctui);
8010GEN_SPEFPUOP_CONV_32_32(efsctsi);
8011GEN_SPEFPUOP_CONV_32_32(efsctuf);
8012GEN_SPEFPUOP_CONV_32_32(efsctsf);
8013GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8014GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8015GEN_SPEFPUOP_CONV_32_64(efscfd);
8016
0487d6a8 8017/* Comparison */
1c97856d
AJ		 8018GEN_SPEFPUOP_COMP_32(efscmpgt);
8019GEN_SPEFPUOP_COMP_32(efscmplt);
8020GEN_SPEFPUOP_COMP_32(efscmpeq);
8021GEN_SPEFPUOP_COMP_32(efststgt);
8022GEN_SPEFPUOP_COMP_32(efststlt);
8023GEN_SPEFPUOP_COMP_32(efststeq);
0487d6a8
JM		 8024
8025/* Opcodes definitions */
40569b7e
AJ		 8026GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8027GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8028GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); //
8029GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); //
8030GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8031GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8032GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8033GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8034GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8035GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8036GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8037GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); //
8038GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
8039GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); //
0487d6a8
JM		 8040
8041/* Double precision floating-point operations */
8042/* Arithmetic */
1c97856d
AJ		 8043GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8044GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8045GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8046GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8047static always_inline void gen_efdabs (DisasContext *ctx)
8048{
8049 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 8050 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 8051 return;
8052 }
8053#if defined(TARGET_PPC64)
8054 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8055#else
8056 tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8057#endif
8058}
8059static always_inline void gen_efdnabs (DisasContext *ctx)
8060{
8061 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 8062 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 8063 return;
8064 }
8065#if defined(TARGET_PPC64)
8066 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8067#else
8068 tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8069#endif
8070}
8071static always_inline void gen_efdneg (DisasContext *ctx)
8072{
8073 if (unlikely(!ctx->spe_enabled)) {
e06fcd75 8074 gen_exception(ctx, POWERPC_EXCP_APU);
1c97856d
AJ		 8075 return;
8076 }
8077#if defined(TARGET_PPC64)
8078 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8079#else
8080 tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8081#endif
8082}
8083
0487d6a8 8084/* Conversion */
1c97856d
AJ		 8085GEN_SPEFPUOP_CONV_64_32(efdcfui);
8086GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8087GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8088GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8089GEN_SPEFPUOP_CONV_32_64(efdctui);
8090GEN_SPEFPUOP_CONV_32_64(efdctsi);
8091GEN_SPEFPUOP_CONV_32_64(efdctuf);
8092GEN_SPEFPUOP_CONV_32_64(efdctsf);
8093GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8094GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8095GEN_SPEFPUOP_CONV_64_32(efdcfs);
8096GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8097GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8098GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8099GEN_SPEFPUOP_CONV_64_64(efdctsidz);
0487d6a8 8100
0487d6a8 8101/* Comparison */
1c97856d
AJ		 8102GEN_SPEFPUOP_COMP_64(efdcmpgt);
8103GEN_SPEFPUOP_COMP_64(efdcmplt);
8104GEN_SPEFPUOP_COMP_64(efdcmpeq);
8105GEN_SPEFPUOP_COMP_64(efdtstgt);
8106GEN_SPEFPUOP_COMP_64(efdtstlt);
8107GEN_SPEFPUOP_COMP_64(efdtsteq);
0487d6a8
JM		 8108
8109/* Opcodes definitions */
40569b7e
AJ		 8110GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8111GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8112GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8113GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); //
8114GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); //
8115GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8116GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8117GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8118GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8119GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8120GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8121GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8122GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8123GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); //
8124GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
8125GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); //
0487d6a8 8126
79aceca5
FB		 8127/* End opcode list */
8128GEN_OPCODE_MARK(end);
8129
3fc6c082 8130#include "translate_init.c"
0411a972 8131#include "helper_regs.h"
79aceca5 8132
9a64fbe4 8133/*****************************************************************************/
3fc6c082 8134/* Misc PowerPC helpers */
36081602
JM		 8135void cpu_dump_state (CPUState *env, FILE *f,
8136 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8137 int flags)
79aceca5 8138{
3fc6c082
FB		 8139#define RGPL 4
8140#define RFPL 4
3fc6c082 8141
79aceca5
FB		 8142 int i;
8143
077fc206 8144 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 8145 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 8146 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
8147 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 8148#if !defined(NO_TIMER_DUMP)
077fc206 8149 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 8150#if !defined(CONFIG_USER_ONLY)
8151 "DECR %08x"
8152#endif
8153 "\n",
077fc206 8154 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 8155#if !defined(CONFIG_USER_ONLY)
8156 , cpu_ppc_load_decr(env)
8157#endif
8158 );
077fc206 8159#endif
76a66253 8160 for (i = 0; i < 32; i++) {
3fc6c082
FB		 8161 if ((i & (RGPL - 1)) == 0)
8162 cpu_fprintf(f, "GPR%02d", i);
6b542af7 8163 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 8164 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 8165 cpu_fprintf(f, "\n");
76a66253 8166 }
3fc6c082 8167 cpu_fprintf(f, "CR ");
76a66253 8168 for (i = 0; i < 8; i++)
7fe48483
FB		 8169 cpu_fprintf(f, "%01x", env->crf[i]);
8170 cpu_fprintf(f, " [");
76a66253
JM		 8171 for (i = 0; i < 8; i++) {
8172 char a = '-';
8173 if (env->crf[i] & 0x08)
8174 a = 'L';
8175 else if (env->crf[i] & 0x04)
8176 a = 'G';
8177 else if (env->crf[i] & 0x02)
8178 a = 'E';
7fe48483 8179 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 8180 }
6b542af7 8181 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 8182 for (i = 0; i < 32; i++) {
8183 if ((i & (RFPL - 1)) == 0)
8184 cpu_fprintf(f, "FPR%02d", i);
26a76461 8185 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 8186 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 8187 cpu_fprintf(f, "\n");
79aceca5 8188 }
7889270a 8189 cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
f2e63a42 8190#if !defined(CONFIG_USER_ONLY)
6b542af7 8191 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 8192 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 8193#endif
79aceca5 8194
3fc6c082
FB		 8195#undef RGPL
8196#undef RFPL
79aceca5
FB		 8197}
8198
76a66253
JM		 8199void cpu_dump_statistics (CPUState *env, FILE*f,
8200 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
8201 int flags)
8202{
8203#if defined(DO_PPC_STATISTICS)
8204 opc_handler_t **t1, **t2, **t3, *handler;
8205 int op1, op2, op3;
8206
8207 t1 = env->opcodes;
8208 for (op1 = 0; op1 < 64; op1++) {
8209 handler = t1[op1];
8210 if (is_indirect_opcode(handler)) {
8211 t2 = ind_table(handler);
8212 for (op2 = 0; op2 < 32; op2++) {
8213 handler = t2[op2];
8214 if (is_indirect_opcode(handler)) {
8215 t3 = ind_table(handler);
8216 for (op3 = 0; op3 < 32; op3++) {
8217 handler = t3[op3];
8218 if (handler->count == 0)
8219 continue;
8220 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
8221 "%016llx %lld\n",
8222 op1, op2, op3, op1, (op3 << 5) | op2,
8223 handler->oname,
8224 handler->count, handler->count);
8225 }
8226 } else {
8227 if (handler->count == 0)
8228 continue;
8229 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
8230 "%016llx %lld\n",
8231 op1, op2, op1, op2, handler->oname,
8232 handler->count, handler->count);
8233 }
8234 }
8235 } else {
8236 if (handler->count == 0)
8237 continue;
8238 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
8239 op1, op1, handler->oname,
8240 handler->count, handler->count);
8241 }
8242 }
8243#endif
8244}
8245
9a64fbe4 8246/*****************************************************************************/
2cfc5f17
TS		 8247static always_inline void gen_intermediate_code_internal (CPUState *env,
8248 TranslationBlock *tb,
8249 int search_pc)
79aceca5 8250{
9fddaa0c 8251 DisasContext ctx, *ctxp = &ctx;
79aceca5 8252 opc_handler_t **table, *handler;
0fa85d43 8253 target_ulong pc_start;
79aceca5 8254 uint16_t *gen_opc_end;
a1d1bb31 8255 CPUBreakpoint *bp;
79aceca5 8256 int j, lj = -1;
2e70f6ef
PB		 8257 int num_insns;
8258 int max_insns;
79aceca5
FB		 8259
8260 pc_start = tb->pc;
79aceca5 8261 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
046d6672 8262 ctx.nip = pc_start;
79aceca5 8263 ctx.tb = tb;
e1833e1f 8264 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 8265 ctx.spr_cb = env->spr_cb;
76db3ba4
AJ		 8266 ctx.mem_idx = env->mmu_idx;
8267 ctx.access_type = -1;
8268 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 8269#if defined(TARGET_PPC64)
8270 ctx.sf_mode = msr_sf;
9a64fbe4 8271#endif
3cc62370 8272 ctx.fpu_enabled = msr_fp;
a9d9eb8f 8273 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 8274 ctx.spe_enabled = msr_spe;
8275 else
8276 ctx.spe_enabled = 0;
a9d9eb8f
JM		 8277 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
8278 ctx.altivec_enabled = msr_vr;
8279 else
8280 ctx.altivec_enabled = 0;
d26bfc9a 8281 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 8282 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 8283 else
8cbcb4fa 8284 ctx.singlestep_enabled = 0;
d26bfc9a 8285 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 8286 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
8287 if (unlikely(env->singlestep_enabled))
8288 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 8289#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 8290 /* Single step trace mode */
8291 msr_se = 1;
8292#endif
2e70f6ef
PB		 8293 num_insns = 0;
8294 max_insns = tb->cflags & CF_COUNT_MASK;
8295 if (max_insns == 0)
8296 max_insns = CF_COUNT_MASK;
8297
8298 gen_icount_start();
9a64fbe4 8299 /* Set env in case of segfault during code fetch */
e1833e1f 8300 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
c0ce998e
AL		 8301 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
8302 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
a1d1bb31 8303 if (bp->pc == ctx.nip) {
e06fcd75 8304 gen_debug_exception(ctxp);
ea4e754f
FB		 8305 break;
8306 }
8307 }
8308 }
76a66253 8309 if (unlikely(search_pc)) {
79aceca5
FB		 8310 j = gen_opc_ptr - gen_opc_buf;
8311 if (lj < j) {
8312 lj++;
8313 while (lj < j)
8314 gen_opc_instr_start[lj++] = 0;
046d6672 8315 gen_opc_pc[lj] = ctx.nip;
79aceca5 8316 gen_opc_instr_start[lj] = 1;
2e70f6ef 8317 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 8318 }
8319 }
d12d51d5
AL		 8320 LOG_DISAS("----------------\n");
8321 LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
8322 ctx.nip, ctx.mem_idx, (int)msr_ir);
2e70f6ef
PB		 8323 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8324 gen_io_start();
76db3ba4 8325 if (unlikely(ctx.le_mode)) {
056401ea
JM		 8326 ctx.opcode = bswap32(ldl_code(ctx.nip));
8327 } else {
8328 ctx.opcode = ldl_code(ctx.nip);
111bfab3 8329 }
d12d51d5 8330 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 8331 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 8332 opc3(ctx.opcode), little_endian ? "little" : "big");
046d6672 8333 ctx.nip += 4;
3fc6c082 8334 table = env->opcodes;
2e70f6ef 8335 num_insns++;
79aceca5
FB		 8336 handler = table[opc1(ctx.opcode)];
8337 if (is_indirect_opcode(handler)) {
8338 table = ind_table(handler);
8339 handler = table[opc2(ctx.opcode)];
8340 if (is_indirect_opcode(handler)) {
8341 table = ind_table(handler);
8342 handler = table[opc3(ctx.opcode)];
8343 }
8344 }
8345 /* Is opcode *REALLY* valid ? */
76a66253 8346 if (unlikely(handler->handler == &gen_invalid)) {
93fcfe39
AL		 8347 if (qemu_log_enabled()) {
8348 qemu_log("invalid/unsupported opcode: "
8349 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
8350 opc1(ctx.opcode), opc2(ctx.opcode),
8351 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 8352 } else {
8353 printf("invalid/unsupported opcode: "
6b542af7 8354 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 8355 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 8356 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 8357 }
76a66253
JM		 8358 } else {
8359 if (unlikely((ctx.opcode & handler->inval) != 0)) {
93fcfe39
AL		 8360 if (qemu_log_enabled()) {
8361 qemu_log("invalid bits: %08x for opcode: "
8362 "%02x - %02x - %02x (%08x) " ADDRX "\n",
8363 ctx.opcode & handler->inval, opc1(ctx.opcode),
8364 opc2(ctx.opcode), opc3(ctx.opcode),
8365 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 8366 } else {
8367 printf("invalid bits: %08x for opcode: "
6b542af7 8368 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 8369 ctx.opcode & handler->inval, opc1(ctx.opcode),
8370 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 8371 ctx.opcode, ctx.nip - 4);
76a66253 8372 }
e06fcd75 8373 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
4b3686fa 8374 break;
79aceca5 8375 }
79aceca5 8376 }
4b3686fa 8377 (*(handler->handler))(&ctx);
76a66253
JM		 8378#if defined(DO_PPC_STATISTICS)
8379 handler->count++;
8380#endif
9a64fbe4 8381 /* Check trace mode exceptions */
8cbcb4fa
AJ		 8382 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
8383 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
8384 ctx.exception != POWERPC_SYSCALL &&
8385 ctx.exception != POWERPC_EXCP_TRAP &&
8386 ctx.exception != POWERPC_EXCP_BRANCH)) {
e06fcd75 8387 gen_exception(ctxp, POWERPC_EXCP_TRACE);
d26bfc9a 8388 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 8389 (env->singlestep_enabled) ||
8390 num_insns >= max_insns)) {
d26bfc9a
JM		 8391 /* if we reach a page boundary or are single stepping, stop
8392 * generation
8393 */
8dd4983c 8394 break;
76a66253 8395 }
3fc6c082
FB		 8396#if defined (DO_SINGLE_STEP)
8397 break;
8398#endif
8399 }
2e70f6ef
PB		 8400 if (tb->cflags & CF_LAST_IO)
8401 gen_io_end();
e1833e1f 8402 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 8403 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 8404 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa 8405 if (unlikely(env->singlestep_enabled)) {
e06fcd75 8406 gen_debug_exception(ctxp);
8cbcb4fa 8407 }
76a66253 8408 /* Generate the return instruction */
57fec1fe 8409 tcg_gen_exit_tb(0);
9a64fbe4 8410 }
2e70f6ef 8411 gen_icount_end(tb, num_insns);
79aceca5 8412 *gen_opc_ptr = INDEX_op_end;
76a66253 8413 if (unlikely(search_pc)) {
9a64fbe4
FB		 8414 j = gen_opc_ptr - gen_opc_buf;
8415 lj++;
8416 while (lj <= j)
8417 gen_opc_instr_start[lj++] = 0;
9a64fbe4 8418 } else {
046d6672 8419 tb->size = ctx.nip - pc_start;
2e70f6ef 8420 tb->icount = num_insns;
9a64fbe4 8421 }
d9bce9d9 8422#if defined(DEBUG_DISAS)
93fcfe39
AL		 8423 qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception);
8424 log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0);
8fec2b8c 8425 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
76a66253 8426 int flags;
237c0af0 8427 flags = env->bfd_mach;
76db3ba4 8428 flags |= ctx.le_mode << 16;
93fcfe39
AL		 8429 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8430 log_target_disas(pc_start, ctx.nip - pc_start, flags);
8431 qemu_log("\n");
9fddaa0c 8432 }
79aceca5 8433#endif
79aceca5
FB		 8434}
8435
2cfc5f17 8436void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 8437{
2cfc5f17 8438 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 8439}
8440
2cfc5f17 8441void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 8442{
2cfc5f17 8443 gen_intermediate_code_internal(env, tb, 1);
79aceca5 8444}
d2856f1a
AJ		 8445
8446void gen_pc_load(CPUState *env, TranslationBlock *tb,
8447 unsigned long searched_pc, int pc_pos, void *puc)
8448{
d2856f1a 8449 env->nip = gen_opc_pc[pc_pos];
d2856f1a 8450}
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