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Commit | Line | Data |
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79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
79aceca5 FB |
5 | * |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, write to the Free Software | |
fad6cb1a | 18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
79aceca5 | 19 | */ |
c6a1c22b FB |
20 | #include <stdarg.h> |
21 | #include <stdlib.h> | |
22 | #include <stdio.h> | |
23 | #include <string.h> | |
24 | #include <inttypes.h> | |
25 | ||
79aceca5 | 26 | #include "cpu.h" |
c6a1c22b | 27 | #include "exec-all.h" |
79aceca5 | 28 | #include "disas.h" |
57fec1fe | 29 | #include "tcg-op.h" |
ca10f867 | 30 | #include "qemu-common.h" |
0cfe11ea | 31 | #include "host-utils.h" |
79aceca5 | 32 | |
a7812ae4 PB |
33 | #include "helper.h" |
34 | #define GEN_HELPER 1 | |
35 | #include "helper.h" | |
36 | ||
8cbcb4fa AJ |
37 | #define CPU_SINGLE_STEP 0x1 |
38 | #define CPU_BRANCH_STEP 0x2 | |
39 | #define GDBSTUB_SINGLE_STEP 0x4 | |
40 | ||
a750fc0b | 41 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 42 | //#define PPC_DEBUG_DISAS |
76a66253 | 43 | //#define DO_PPC_STATISTICS |
79aceca5 | 44 | |
d12d51d5 | 45 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 46 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
47 | #else |
48 | # define LOG_DISAS(...) do { } while (0) | |
49 | #endif | |
a750fc0b JM |
50 | /*****************************************************************************/ |
51 | /* Code translation helpers */ | |
c53be334 | 52 | |
f78fb44e | 53 | /* global register indexes */ |
a7812ae4 | 54 | static TCGv_ptr cpu_env; |
1d542695 | 55 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
f78fb44e | 56 | #if !defined(TARGET_PPC64) |
1d542695 | 57 | + 10*4 + 22*5 /* SPE GPRh */ |
f78fb44e | 58 | #endif |
a5e26afa | 59 | + 10*4 + 22*5 /* FPR */ |
47e4661c AJ |
60 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
61 | + 8*5 /* CRF */]; | |
f78fb44e AJ |
62 | static TCGv cpu_gpr[32]; |
63 | #if !defined(TARGET_PPC64) | |
64 | static TCGv cpu_gprh[32]; | |
65 | #endif | |
a7812ae4 PB |
66 | static TCGv_i64 cpu_fpr[32]; |
67 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
68 | static TCGv_i32 cpu_crf[8]; | |
bd568f18 | 69 | static TCGv cpu_nip; |
6527f6ea | 70 | static TCGv cpu_msr; |
cfdcd37a AJ |
71 | static TCGv cpu_ctr; |
72 | static TCGv cpu_lr; | |
3d7b417e | 73 | static TCGv cpu_xer; |
cf360a32 | 74 | static TCGv cpu_reserve; |
a7812ae4 | 75 | static TCGv_i32 cpu_fpscr; |
a7859e89 | 76 | static TCGv_i32 cpu_access_type; |
f78fb44e | 77 | |
2e70f6ef PB |
78 | #include "gen-icount.h" |
79 | ||
80 | void ppc_translate_init(void) | |
81 | { | |
f78fb44e AJ |
82 | int i; |
83 | char* p; | |
2dc766da | 84 | size_t cpu_reg_names_size; |
b2437bf2 | 85 | static int done_init = 0; |
f78fb44e | 86 | |
2e70f6ef PB |
87 | if (done_init) |
88 | return; | |
f78fb44e | 89 | |
a7812ae4 | 90 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
a7812ae4 | 91 | |
f78fb44e | 92 | p = cpu_reg_names; |
2dc766da | 93 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
94 | |
95 | for (i = 0; i < 8; i++) { | |
2dc766da | 96 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
a7812ae4 PB |
97 | cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0, |
98 | offsetof(CPUState, crf[i]), p); | |
47e4661c | 99 | p += 5; |
2dc766da | 100 | cpu_reg_names_size -= 5; |
47e4661c AJ |
101 | } |
102 | ||
f78fb44e | 103 | for (i = 0; i < 32; i++) { |
2dc766da | 104 | snprintf(p, cpu_reg_names_size, "r%d", i); |
a7812ae4 | 105 | cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0, |
f78fb44e AJ |
106 | offsetof(CPUState, gpr[i]), p); |
107 | p += (i < 10) ? 3 : 4; | |
2dc766da | 108 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
f78fb44e | 109 | #if !defined(TARGET_PPC64) |
2dc766da | 110 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
a7812ae4 PB |
111 | cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0, |
112 | offsetof(CPUState, gprh[i]), p); | |
f78fb44e | 113 | p += (i < 10) ? 4 : 5; |
2dc766da | 114 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
f78fb44e | 115 | #endif |
1d542695 | 116 | |
2dc766da | 117 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
a7812ae4 PB |
118 | cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0, |
119 | offsetof(CPUState, fpr[i]), p); | |
ec1ac72d | 120 | p += (i < 10) ? 4 : 5; |
2dc766da | 121 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 122 | |
2dc766da | 123 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
fe1e5c53 AJ |
124 | #ifdef WORDS_BIGENDIAN |
125 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
126 | offsetof(CPUState, avr[i].u64[0]), p); | |
127 | #else | |
a7812ae4 | 128 | cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0, |
fe1e5c53 AJ |
129 | offsetof(CPUState, avr[i].u64[1]), p); |
130 | #endif | |
1d542695 | 131 | p += (i < 10) ? 6 : 7; |
2dc766da | 132 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 133 | |
2dc766da | 134 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
fe1e5c53 AJ |
135 | #ifdef WORDS_BIGENDIAN |
136 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, | |
137 | offsetof(CPUState, avr[i].u64[1]), p); | |
138 | #else | |
a7812ae4 | 139 | cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0, |
fe1e5c53 AJ |
140 | offsetof(CPUState, avr[i].u64[0]), p); |
141 | #endif | |
1d542695 | 142 | p += (i < 10) ? 6 : 7; |
2dc766da | 143 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
f78fb44e | 144 | } |
f10dc08e | 145 | |
a7812ae4 | 146 | cpu_nip = tcg_global_mem_new(TCG_AREG0, |
bd568f18 AJ |
147 | offsetof(CPUState, nip), "nip"); |
148 | ||
6527f6ea AJ |
149 | cpu_msr = tcg_global_mem_new(TCG_AREG0, |
150 | offsetof(CPUState, msr), "msr"); | |
151 | ||
a7812ae4 | 152 | cpu_ctr = tcg_global_mem_new(TCG_AREG0, |
cfdcd37a AJ |
153 | offsetof(CPUState, ctr), "ctr"); |
154 | ||
a7812ae4 | 155 | cpu_lr = tcg_global_mem_new(TCG_AREG0, |
cfdcd37a AJ |
156 | offsetof(CPUState, lr), "lr"); |
157 | ||
a7812ae4 | 158 | cpu_xer = tcg_global_mem_new(TCG_AREG0, |
3d7b417e AJ |
159 | offsetof(CPUState, xer), "xer"); |
160 | ||
cf360a32 AJ |
161 | cpu_reserve = tcg_global_mem_new(TCG_AREG0, |
162 | offsetof(CPUState, reserve), "reserve"); | |
163 | ||
a7812ae4 PB |
164 | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
165 | offsetof(CPUState, fpscr), "fpscr"); | |
e1571908 | 166 | |
a7859e89 AJ |
167 | cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, |
168 | offsetof(CPUState, access_type), "access_type"); | |
169 | ||
f10dc08e | 170 | /* register helpers */ |
a7812ae4 | 171 | #define GEN_HELPER 2 |
f10dc08e AJ |
172 | #include "helper.h" |
173 | ||
2e70f6ef PB |
174 | done_init = 1; |
175 | } | |
176 | ||
79aceca5 FB |
177 | /* internal defines */ |
178 | typedef struct DisasContext { | |
179 | struct TranslationBlock *tb; | |
0fa85d43 | 180 | target_ulong nip; |
79aceca5 | 181 | uint32_t opcode; |
9a64fbe4 | 182 | uint32_t exception; |
3cc62370 FB |
183 | /* Routine used to access memory */ |
184 | int mem_idx; | |
76db3ba4 | 185 | int access_type; |
3cc62370 | 186 | /* Translation flags */ |
76db3ba4 | 187 | int le_mode; |
d9bce9d9 JM |
188 | #if defined(TARGET_PPC64) |
189 | int sf_mode; | |
9a64fbe4 | 190 | #endif |
3cc62370 | 191 | int fpu_enabled; |
a9d9eb8f | 192 | int altivec_enabled; |
0487d6a8 | 193 | int spe_enabled; |
3fc6c082 | 194 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 195 | int singlestep_enabled; |
79aceca5 FB |
196 | } DisasContext; |
197 | ||
3fc6c082 | 198 | struct opc_handler_t { |
79aceca5 FB |
199 | /* invalid bits */ |
200 | uint32_t inval; | |
9a64fbe4 | 201 | /* instruction type */ |
0487d6a8 | 202 | uint64_t type; |
79aceca5 FB |
203 | /* handler */ |
204 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 205 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 206 | const char *oname; |
a750fc0b JM |
207 | #endif |
208 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
209 | uint64_t count; |
210 | #endif | |
3fc6c082 | 211 | }; |
79aceca5 | 212 | |
7c58044c JM |
213 | static always_inline void gen_reset_fpstatus (void) |
214 | { | |
215 | #ifdef CONFIG_SOFTFLOAT | |
a44d2ce1 | 216 | gen_helper_reset_fpstatus(); |
7c58044c JM |
217 | #endif |
218 | } | |
219 | ||
0f2f39c2 | 220 | static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc) |
7c58044c | 221 | { |
0f2f39c2 | 222 | TCGv_i32 t0 = tcg_temp_new_i32(); |
af12906f | 223 | |
7c58044c JM |
224 | if (set_fprf != 0) { |
225 | /* This case might be optimized later */ | |
0f2f39c2 | 226 | tcg_gen_movi_i32(t0, 1); |
af12906f | 227 | gen_helper_compute_fprf(t0, arg, t0); |
a7812ae4 | 228 | if (unlikely(set_rc)) { |
0f2f39c2 | 229 | tcg_gen_mov_i32(cpu_crf[1], t0); |
a7812ae4 | 230 | } |
af12906f | 231 | gen_helper_float_check_status(); |
7c58044c JM |
232 | } else if (unlikely(set_rc)) { |
233 | /* We always need to compute fpcc */ | |
0f2f39c2 | 234 | tcg_gen_movi_i32(t0, 0); |
af12906f | 235 | gen_helper_compute_fprf(t0, arg, t0); |
0f2f39c2 | 236 | tcg_gen_mov_i32(cpu_crf[1], t0); |
7c58044c | 237 | } |
af12906f | 238 | |
0f2f39c2 | 239 | tcg_temp_free_i32(t0); |
7c58044c JM |
240 | } |
241 | ||
76db3ba4 | 242 | static always_inline void gen_set_access_type (DisasContext *ctx, int access_type) |
a7859e89 | 243 | { |
76db3ba4 AJ |
244 | if (ctx->access_type != access_type) { |
245 | tcg_gen_movi_i32(cpu_access_type, access_type); | |
246 | ctx->access_type = access_type; | |
247 | } | |
a7859e89 AJ |
248 | } |
249 | ||
b068d6a7 | 250 | static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip) |
d9bce9d9 JM |
251 | { |
252 | #if defined(TARGET_PPC64) | |
253 | if (ctx->sf_mode) | |
bd568f18 | 254 | tcg_gen_movi_tl(cpu_nip, nip); |
d9bce9d9 JM |
255 | else |
256 | #endif | |
bd568f18 | 257 | tcg_gen_movi_tl(cpu_nip, (uint32_t)nip); |
d9bce9d9 JM |
258 | } |
259 | ||
e06fcd75 AJ |
260 | static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error) |
261 | { | |
262 | TCGv_i32 t0, t1; | |
263 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
264 | gen_update_nip(ctx, ctx->nip); | |
265 | } | |
266 | t0 = tcg_const_i32(excp); | |
267 | t1 = tcg_const_i32(error); | |
268 | gen_helper_raise_exception_err(t0, t1); | |
269 | tcg_temp_free_i32(t0); | |
270 | tcg_temp_free_i32(t1); | |
271 | ctx->exception = (excp); | |
272 | } | |
e1833e1f | 273 | |
e06fcd75 AJ |
274 | static always_inline void gen_exception (DisasContext *ctx, uint32_t excp) |
275 | { | |
276 | TCGv_i32 t0; | |
277 | if (ctx->exception == POWERPC_EXCP_NONE) { | |
278 | gen_update_nip(ctx, ctx->nip); | |
279 | } | |
280 | t0 = tcg_const_i32(excp); | |
281 | gen_helper_raise_exception(t0); | |
282 | tcg_temp_free_i32(t0); | |
283 | ctx->exception = (excp); | |
284 | } | |
e1833e1f | 285 | |
e06fcd75 AJ |
286 | static always_inline void gen_debug_exception (DisasContext *ctx) |
287 | { | |
288 | TCGv_i32 t0; | |
5518f3a6 BS |
289 | |
290 | if (ctx->exception != POWERPC_EXCP_BRANCH) | |
291 | gen_update_nip(ctx, ctx->nip); | |
e06fcd75 AJ |
292 | t0 = tcg_const_i32(EXCP_DEBUG); |
293 | gen_helper_raise_exception(t0); | |
294 | tcg_temp_free_i32(t0); | |
295 | } | |
9a64fbe4 | 296 | |
e06fcd75 AJ |
297 | static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error) |
298 | { | |
299 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error); | |
300 | } | |
a9d9eb8f | 301 | |
f24e5695 | 302 | /* Stop translation */ |
e06fcd75 | 303 | static always_inline void gen_stop_exception (DisasContext *ctx) |
3fc6c082 | 304 | { |
d9bce9d9 | 305 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 306 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
307 | } |
308 | ||
f24e5695 | 309 | /* No need to update nip here, as execution flow will change */ |
e06fcd75 | 310 | static always_inline void gen_sync_exception (DisasContext *ctx) |
2be0071f | 311 | { |
e1833e1f | 312 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f FB |
313 | } |
314 | ||
79aceca5 FB |
315 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
316 | static void gen_##name (DisasContext *ctx); \ | |
99e300ef | 317 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type); |
79aceca5 | 318 | |
c7697e1f JM |
319 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
320 | static void gen_##name (DisasContext *ctx); \ | |
321 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \ | |
c7697e1f | 322 | |
79aceca5 FB |
323 | typedef struct opcode_t { |
324 | unsigned char opc1, opc2, opc3; | |
1235fc06 | 325 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
18fba28c FB |
326 | unsigned char pad[5]; |
327 | #else | |
328 | unsigned char pad[1]; | |
329 | #endif | |
79aceca5 | 330 | opc_handler_t handler; |
b55266b5 | 331 | const char *oname; |
79aceca5 FB |
332 | } opcode_t; |
333 | ||
a750fc0b | 334 | /*****************************************************************************/ |
79aceca5 FB |
335 | /*** Instruction decoding ***/ |
336 | #define EXTRACT_HELPER(name, shift, nb) \ | |
b068d6a7 | 337 | static always_inline uint32_t name (uint32_t opcode) \ |
79aceca5 FB |
338 | { \ |
339 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
340 | } | |
341 | ||
342 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
b068d6a7 | 343 | static always_inline int32_t name (uint32_t opcode) \ |
79aceca5 | 344 | { \ |
18fba28c | 345 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
346 | } |
347 | ||
348 | /* Opcode part 1 */ | |
349 | EXTRACT_HELPER(opc1, 26, 6); | |
350 | /* Opcode part 2 */ | |
351 | EXTRACT_HELPER(opc2, 1, 5); | |
352 | /* Opcode part 3 */ | |
353 | EXTRACT_HELPER(opc3, 6, 5); | |
354 | /* Update Cr0 flags */ | |
355 | EXTRACT_HELPER(Rc, 0, 1); | |
356 | /* Destination */ | |
357 | EXTRACT_HELPER(rD, 21, 5); | |
358 | /* Source */ | |
359 | EXTRACT_HELPER(rS, 21, 5); | |
360 | /* First operand */ | |
361 | EXTRACT_HELPER(rA, 16, 5); | |
362 | /* Second operand */ | |
363 | EXTRACT_HELPER(rB, 11, 5); | |
364 | /* Third operand */ | |
365 | EXTRACT_HELPER(rC, 6, 5); | |
366 | /*** Get CRn ***/ | |
367 | EXTRACT_HELPER(crfD, 23, 3); | |
368 | EXTRACT_HELPER(crfS, 18, 3); | |
369 | EXTRACT_HELPER(crbD, 21, 5); | |
370 | EXTRACT_HELPER(crbA, 16, 5); | |
371 | EXTRACT_HELPER(crbB, 11, 5); | |
372 | /* SPR / TBL */ | |
3fc6c082 | 373 | EXTRACT_HELPER(_SPR, 11, 10); |
b068d6a7 | 374 | static always_inline uint32_t SPR (uint32_t opcode) |
3fc6c082 FB |
375 | { |
376 | uint32_t sprn = _SPR(opcode); | |
377 | ||
378 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
379 | } | |
79aceca5 FB |
380 | /*** Get constants ***/ |
381 | EXTRACT_HELPER(IMM, 12, 8); | |
382 | /* 16 bits signed immediate value */ | |
383 | EXTRACT_SHELPER(SIMM, 0, 16); | |
384 | /* 16 bits unsigned immediate value */ | |
385 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
386 | /* 5 bits signed immediate value */ |
387 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
388 | /* 5 bits signed immediate value */ |
389 | EXTRACT_HELPER(UIMM5, 16, 5); | |
79aceca5 FB |
390 | /* Bit count */ |
391 | EXTRACT_HELPER(NB, 11, 5); | |
392 | /* Shift count */ | |
393 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
394 | /* Vector shift count */ |
395 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
396 | /* Mask start */ |
397 | EXTRACT_HELPER(MB, 6, 5); | |
398 | /* Mask end */ | |
399 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
400 | /* Trap operand */ |
401 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
402 | |
403 | EXTRACT_HELPER(CRM, 12, 8); | |
404 | EXTRACT_HELPER(FM, 17, 8); | |
405 | EXTRACT_HELPER(SR, 16, 4); | |
e4bb997e | 406 | EXTRACT_HELPER(FPIMM, 12, 4); |
fb0eaffc | 407 | |
79aceca5 FB |
408 | /*** Jump target decoding ***/ |
409 | /* Displacement */ | |
410 | EXTRACT_SHELPER(d, 0, 16); | |
411 | /* Immediate address */ | |
b068d6a7 | 412 | static always_inline target_ulong LI (uint32_t opcode) |
79aceca5 FB |
413 | { |
414 | return (opcode >> 0) & 0x03FFFFFC; | |
415 | } | |
416 | ||
b068d6a7 | 417 | static always_inline uint32_t BD (uint32_t opcode) |
79aceca5 FB |
418 | { |
419 | return (opcode >> 0) & 0xFFFC; | |
420 | } | |
421 | ||
422 | EXTRACT_HELPER(BO, 21, 5); | |
423 | EXTRACT_HELPER(BI, 16, 5); | |
424 | /* Absolute/relative address */ | |
425 | EXTRACT_HELPER(AA, 1, 1); | |
426 | /* Link */ | |
427 | EXTRACT_HELPER(LK, 0, 1); | |
428 | ||
429 | /* Create a mask between <start> and <end> bits */ | |
b068d6a7 | 430 | static always_inline target_ulong MASK (uint32_t start, uint32_t end) |
79aceca5 | 431 | { |
76a66253 | 432 | target_ulong ret; |
79aceca5 | 433 | |
76a66253 JM |
434 | #if defined(TARGET_PPC64) |
435 | if (likely(start == 0)) { | |
6f2d8978 | 436 | ret = UINT64_MAX << (63 - end); |
76a66253 | 437 | } else if (likely(end == 63)) { |
6f2d8978 | 438 | ret = UINT64_MAX >> start; |
76a66253 JM |
439 | } |
440 | #else | |
441 | if (likely(start == 0)) { | |
6f2d8978 | 442 | ret = UINT32_MAX << (31 - end); |
76a66253 | 443 | } else if (likely(end == 31)) { |
6f2d8978 | 444 | ret = UINT32_MAX >> start; |
76a66253 JM |
445 | } |
446 | #endif | |
447 | else { | |
448 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
449 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
450 | if (unlikely(start > end)) | |
451 | return ~ret; | |
452 | } | |
79aceca5 FB |
453 | |
454 | return ret; | |
455 | } | |
456 | ||
a750fc0b | 457 | /*****************************************************************************/ |
a750fc0b | 458 | /* PowerPC instructions table */ |
3fc6c082 FB |
459 | #if HOST_LONG_BITS == 64 |
460 | #define OPC_ALIGN 8 | |
461 | #else | |
462 | #define OPC_ALIGN 4 | |
463 | #endif | |
1b039c09 | 464 | #if defined(__APPLE__) |
d9bce9d9 | 465 | #define OPCODES_SECTION \ |
3fc6c082 | 466 | __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) )) |
933dc6eb | 467 | #else |
d9bce9d9 | 468 | #define OPCODES_SECTION \ |
3fc6c082 | 469 | __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) )) |
933dc6eb FB |
470 | #endif |
471 | ||
76a66253 | 472 | #if defined(DO_PPC_STATISTICS) |
79aceca5 | 473 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ |
50773fd2 | 474 | extern opcode_t opc_##name; \ |
18fba28c | 475 | OPCODES_SECTION opcode_t opc_##name = { \ |
79aceca5 FB |
476 | .opc1 = op1, \ |
477 | .opc2 = op2, \ | |
478 | .opc3 = op3, \ | |
18fba28c | 479 | .pad = { 0, }, \ |
79aceca5 FB |
480 | .handler = { \ |
481 | .inval = invl, \ | |
9a64fbe4 | 482 | .type = _typ, \ |
79aceca5 | 483 | .handler = &gen_##name, \ |
76a66253 | 484 | .oname = stringify(name), \ |
79aceca5 | 485 | }, \ |
3fc6c082 | 486 | .oname = stringify(name), \ |
79aceca5 | 487 | } |
c7697e1f JM |
488 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \ |
489 | OPCODES_SECTION opcode_t opc_##name = { \ | |
490 | .opc1 = op1, \ | |
491 | .opc2 = op2, \ | |
492 | .opc3 = op3, \ | |
493 | .pad = { 0, }, \ | |
494 | .handler = { \ | |
495 | .inval = invl, \ | |
496 | .type = _typ, \ | |
497 | .handler = &gen_##name, \ | |
498 | .oname = onam, \ | |
499 | }, \ | |
500 | .oname = onam, \ | |
501 | } | |
76a66253 JM |
502 | #else |
503 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \ | |
50773fd2 | 504 | extern opcode_t opc_##name; \ |
76a66253 JM |
505 | OPCODES_SECTION opcode_t opc_##name = { \ |
506 | .opc1 = op1, \ | |
507 | .opc2 = op2, \ | |
508 | .opc3 = op3, \ | |
509 | .pad = { 0, }, \ | |
510 | .handler = { \ | |
511 | .inval = invl, \ | |
512 | .type = _typ, \ | |
513 | .handler = &gen_##name, \ | |
514 | }, \ | |
515 | .oname = stringify(name), \ | |
516 | } | |
c7697e1f | 517 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \ |
50773fd2 | 518 | extern opcode_t opc_##name; \ |
c7697e1f JM |
519 | OPCODES_SECTION opcode_t opc_##name = { \ |
520 | .opc1 = op1, \ | |
521 | .opc2 = op2, \ | |
522 | .opc3 = op3, \ | |
523 | .pad = { 0, }, \ | |
524 | .handler = { \ | |
525 | .inval = invl, \ | |
526 | .type = _typ, \ | |
527 | .handler = &gen_##name, \ | |
528 | }, \ | |
529 | .oname = onam, \ | |
530 | } | |
76a66253 | 531 | #endif |
79aceca5 FB |
532 | |
533 | #define GEN_OPCODE_MARK(name) \ | |
50773fd2 | 534 | extern opcode_t opc_##name; \ |
18fba28c | 535 | OPCODES_SECTION opcode_t opc_##name = { \ |
79aceca5 FB |
536 | .opc1 = 0xFF, \ |
537 | .opc2 = 0xFF, \ | |
538 | .opc3 = 0xFF, \ | |
18fba28c | 539 | .pad = { 0, }, \ |
79aceca5 FB |
540 | .handler = { \ |
541 | .inval = 0x00000000, \ | |
9a64fbe4 | 542 | .type = 0x00, \ |
79aceca5 FB |
543 | .handler = NULL, \ |
544 | }, \ | |
3fc6c082 | 545 | .oname = stringify(name), \ |
79aceca5 FB |
546 | } |
547 | ||
54cdcae6 AJ |
548 | /* SPR load/store helpers */ |
549 | static always_inline void gen_load_spr(TCGv t, int reg) | |
550 | { | |
551 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg])); | |
552 | } | |
553 | ||
554 | static always_inline void gen_store_spr(int reg, TCGv t) | |
555 | { | |
556 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg])); | |
557 | } | |
558 | ||
79aceca5 FB |
559 | /* Start opcode list */ |
560 | GEN_OPCODE_MARK(start); | |
99e300ef | 561 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE); |
54623277 BS |
562 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER); |
563 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER); | |
564 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER); | |
565 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER); | |
566 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL); | |
567 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
568 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
569 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
570 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
571 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER); | |
572 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER); | |
573 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER); | |
574 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER); | |
575 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
576 | #if defined(TARGET_PPC64) | |
577 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B); | |
578 | #endif | |
579 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER); | |
580 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER); | |
581 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
582 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
583 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
584 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER); | |
585 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER); | |
586 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER); | |
587 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
588 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
589 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
590 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
591 | GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB); | |
592 | #if defined(TARGET_PPC64) | |
593 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B); | |
594 | #endif | |
595 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
596 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
597 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
598 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER); | |
599 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER); | |
600 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER); | |
601 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER); | |
602 | #if defined(TARGET_PPC64) | |
603 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B); | |
604 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B); | |
605 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B); | |
606 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B); | |
607 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B); | |
608 | #endif | |
609 | GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES); | |
610 | GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT); | |
611 | GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT); | |
612 | GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT); | |
613 | GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT); | |
614 | GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT); | |
615 | GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT); | |
616 | GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT); | |
617 | GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT); | |
618 | GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT); | |
619 | GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT); | |
620 | GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT); | |
621 | #if defined(TARGET_PPC64) | |
622 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B); | |
623 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX); | |
624 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B); | |
625 | #endif | |
626 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
627 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER); | |
628 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING); | |
629 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING); | |
630 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING); | |
631 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING); | |
632 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO); | |
633 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM); | |
634 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES); | |
635 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES); | |
636 | #if defined(TARGET_PPC64) | |
637 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B); | |
638 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B); | |
639 | #endif | |
640 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC); | |
641 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT); | |
642 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW); | |
643 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW); | |
644 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW); | |
645 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW); | |
646 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER); | |
647 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW); | |
648 | #if defined(TARGET_PPC64) | |
649 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B); | |
650 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H); | |
651 | #endif | |
652 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW); | |
653 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW); | |
654 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW); | |
655 | #if defined(TARGET_PPC64) | |
656 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B); | |
657 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B); | |
658 | #endif | |
659 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC); | |
660 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC); | |
661 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC); | |
662 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC); | |
663 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB); | |
664 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC); | |
665 | #if defined(TARGET_PPC64) | |
666 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B); | |
667 | #endif | |
668 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC); | |
669 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC); | |
670 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE); | |
671 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE); | |
672 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE); | |
673 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE); | |
674 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE); | |
675 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ); | |
676 | GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT); | |
677 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC); | |
678 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC); | |
679 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC); | |
680 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI); | |
681 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA); | |
682 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT); | |
683 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT); | |
684 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT); | |
685 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT); | |
686 | #if defined(TARGET_PPC64) | |
687 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B); | |
688 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
689 | PPC_SEGMENT_64B); | |
690 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B); | |
691 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
692 | PPC_SEGMENT_64B); | |
693 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x00000000, PPC_SEGMENT_64B); | |
694 | #endif | |
695 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA); | |
696 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE); | |
697 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE); | |
698 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC); | |
699 | #if defined(TARGET_PPC64) | |
700 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI); | |
701 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI); | |
702 | #endif | |
703 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN); | |
704 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN); | |
705 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR); | |
706 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR); | |
707 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR); | |
708 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR); | |
709 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR); | |
710 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR); | |
711 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR); | |
712 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR); | |
713 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR); | |
714 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR); | |
715 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR); | |
716 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR); | |
717 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR); | |
718 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR); | |
719 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR); | |
720 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR); | |
721 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR); | |
722 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR); | |
723 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR); | |
724 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR); | |
725 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR); | |
726 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR); | |
727 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR); | |
728 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR); | |
729 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR); | |
730 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR); | |
731 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR); | |
732 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR); | |
733 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR); | |
734 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR); | |
735 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR); | |
736 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR); | |
737 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR); | |
738 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR); | |
739 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC); | |
740 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC); | |
741 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC); | |
742 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB); | |
743 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB); | |
744 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB); | |
745 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB); | |
746 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER); | |
747 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER); | |
748 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER); | |
749 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER); | |
750 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER); | |
751 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER); | |
752 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2); | |
753 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2); | |
754 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2); | |
755 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2); | |
756 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2); | |
757 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2); | |
758 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2); | |
759 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2); | |
760 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI); | |
761 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA); | |
762 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR); | |
763 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR); | |
764 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX); | |
765 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX); | |
766 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX); | |
767 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX); | |
768 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON); | |
769 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON); | |
770 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT); | |
771 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON); | |
772 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON); | |
773 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP); | |
774 | GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE); | |
775 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI); | |
776 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI); | |
777 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB); | |
778 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB); | |
779 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB); | |
780 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE); | |
781 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE); | |
782 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE); | |
783 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE); | |
784 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE); | |
785 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC); | |
786 | GEN_HANDLER(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE); | |
787 | GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE); | |
788 | GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE); | |
789 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC); | |
790 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC); | |
791 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC); | |
792 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC); | |
793 | GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC); | |
794 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC); | |
795 | GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE); | |
796 | GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE); | |
797 | GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE); | |
798 | GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE); | |
99e300ef | 799 | |
54623277 | 800 | /* Invalid instruction */ |
99e300ef | 801 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 802 | { |
e06fcd75 | 803 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
804 | } |
805 | ||
79aceca5 FB |
806 | static opc_handler_t invalid_handler = { |
807 | .inval = 0xFFFFFFFF, | |
9a64fbe4 | 808 | .type = PPC_NONE, |
79aceca5 FB |
809 | .handler = gen_invalid, |
810 | }; | |
811 | ||
e1571908 AJ |
812 | /*** Integer comparison ***/ |
813 | ||
ea363694 | 814 | static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 AJ |
815 | { |
816 | int l1, l2, l3; | |
817 | ||
269f3e95 AJ |
818 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer); |
819 | tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO); | |
e1571908 AJ |
820 | tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1); |
821 | ||
822 | l1 = gen_new_label(); | |
823 | l2 = gen_new_label(); | |
824 | l3 = gen_new_label(); | |
825 | if (s) { | |
ea363694 AJ |
826 | tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1); |
827 | tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2); | |
e1571908 | 828 | } else { |
ea363694 AJ |
829 | tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1); |
830 | tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2); | |
e1571908 AJ |
831 | } |
832 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ); | |
833 | tcg_gen_br(l3); | |
834 | gen_set_label(l1); | |
835 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT); | |
836 | tcg_gen_br(l3); | |
837 | gen_set_label(l2); | |
838 | tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT); | |
839 | gen_set_label(l3); | |
840 | } | |
841 | ||
ea363694 | 842 | static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 843 | { |
ea363694 AJ |
844 | TCGv t0 = tcg_const_local_tl(arg1); |
845 | gen_op_cmp(arg0, t0, s, crf); | |
846 | tcg_temp_free(t0); | |
e1571908 AJ |
847 | } |
848 | ||
849 | #if defined(TARGET_PPC64) | |
ea363694 | 850 | static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 851 | { |
ea363694 | 852 | TCGv t0, t1; |
a7812ae4 PB |
853 | t0 = tcg_temp_local_new(); |
854 | t1 = tcg_temp_local_new(); | |
e1571908 | 855 | if (s) { |
ea363694 AJ |
856 | tcg_gen_ext32s_tl(t0, arg0); |
857 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 858 | } else { |
ea363694 AJ |
859 | tcg_gen_ext32u_tl(t0, arg0); |
860 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 861 | } |
ea363694 AJ |
862 | gen_op_cmp(t0, t1, s, crf); |
863 | tcg_temp_free(t1); | |
864 | tcg_temp_free(t0); | |
e1571908 AJ |
865 | } |
866 | ||
ea363694 | 867 | static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 868 | { |
ea363694 AJ |
869 | TCGv t0 = tcg_const_local_tl(arg1); |
870 | gen_op_cmp32(arg0, t0, s, crf); | |
871 | tcg_temp_free(t0); | |
e1571908 AJ |
872 | } |
873 | #endif | |
874 | ||
875 | static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg) | |
876 | { | |
877 | #if defined(TARGET_PPC64) | |
878 | if (!(ctx->sf_mode)) | |
879 | gen_op_cmpi32(reg, 0, 1, 0); | |
880 | else | |
881 | #endif | |
882 | gen_op_cmpi(reg, 0, 1, 0); | |
883 | } | |
884 | ||
885 | /* cmp */ | |
99e300ef | 886 | static void gen_cmp(DisasContext *ctx) |
e1571908 AJ |
887 | { |
888 | #if defined(TARGET_PPC64) | |
889 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
890 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
891 | 1, crfD(ctx->opcode)); | |
892 | else | |
893 | #endif | |
894 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
895 | 1, crfD(ctx->opcode)); | |
896 | } | |
897 | ||
898 | /* cmpi */ | |
99e300ef | 899 | static void gen_cmpi(DisasContext *ctx) |
e1571908 AJ |
900 | { |
901 | #if defined(TARGET_PPC64) | |
902 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
903 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
904 | 1, crfD(ctx->opcode)); | |
905 | else | |
906 | #endif | |
907 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
908 | 1, crfD(ctx->opcode)); | |
909 | } | |
910 | ||
911 | /* cmpl */ | |
99e300ef | 912 | static void gen_cmpl(DisasContext *ctx) |
e1571908 AJ |
913 | { |
914 | #if defined(TARGET_PPC64) | |
915 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
916 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
917 | 0, crfD(ctx->opcode)); | |
918 | else | |
919 | #endif | |
920 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
921 | 0, crfD(ctx->opcode)); | |
922 | } | |
923 | ||
924 | /* cmpli */ | |
99e300ef | 925 | static void gen_cmpli(DisasContext *ctx) |
e1571908 AJ |
926 | { |
927 | #if defined(TARGET_PPC64) | |
928 | if (!(ctx->sf_mode && (ctx->opcode & 0x00200000))) | |
929 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
930 | 0, crfD(ctx->opcode)); | |
931 | else | |
932 | #endif | |
933 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
934 | 0, crfD(ctx->opcode)); | |
935 | } | |
936 | ||
937 | /* isel (PowerPC 2.03 specification) */ | |
99e300ef | 938 | static void gen_isel(DisasContext *ctx) |
e1571908 AJ |
939 | { |
940 | int l1, l2; | |
941 | uint32_t bi = rC(ctx->opcode); | |
942 | uint32_t mask; | |
a7812ae4 | 943 | TCGv_i32 t0; |
e1571908 AJ |
944 | |
945 | l1 = gen_new_label(); | |
946 | l2 = gen_new_label(); | |
947 | ||
948 | mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 949 | t0 = tcg_temp_new_i32(); |
fea0c503 AJ |
950 | tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); |
951 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
e1571908 AJ |
952 | if (rA(ctx->opcode) == 0) |
953 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
954 | else | |
955 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
956 | tcg_gen_br(l2); | |
957 | gen_set_label(l1); | |
958 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
959 | gen_set_label(l2); | |
a7812ae4 | 960 | tcg_temp_free_i32(t0); |
e1571908 AJ |
961 | } |
962 | ||
79aceca5 | 963 | /*** Integer arithmetic ***/ |
79aceca5 | 964 | |
74637406 AJ |
965 | static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub) |
966 | { | |
967 | int l1; | |
968 | TCGv t0; | |
79aceca5 | 969 | |
74637406 AJ |
970 | l1 = gen_new_label(); |
971 | /* Start with XER OV disabled, the most likely case */ | |
972 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
a7812ae4 | 973 | t0 = tcg_temp_local_new(); |
74637406 AJ |
974 | tcg_gen_xor_tl(t0, arg0, arg1); |
975 | #if defined(TARGET_PPC64) | |
976 | if (!ctx->sf_mode) | |
977 | tcg_gen_ext32s_tl(t0, t0); | |
978 | #endif | |
979 | if (sub) | |
980 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); | |
981 | else | |
982 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
983 | tcg_gen_xor_tl(t0, arg1, arg2); | |
984 | #if defined(TARGET_PPC64) | |
985 | if (!ctx->sf_mode) | |
986 | tcg_gen_ext32s_tl(t0, t0); | |
987 | #endif | |
988 | if (sub) | |
989 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
990 | else | |
991 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1); | |
992 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
993 | gen_set_label(l1); | |
994 | tcg_temp_free(t0); | |
79aceca5 FB |
995 | } |
996 | ||
74637406 AJ |
997 | static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub) |
998 | { | |
999 | int l1 = gen_new_label(); | |
d9bce9d9 JM |
1000 | |
1001 | #if defined(TARGET_PPC64) | |
74637406 AJ |
1002 | if (!(ctx->sf_mode)) { |
1003 | TCGv t0, t1; | |
a7812ae4 PB |
1004 | t0 = tcg_temp_new(); |
1005 | t1 = tcg_temp_new(); | |
d9bce9d9 | 1006 | |
74637406 AJ |
1007 | tcg_gen_ext32u_tl(t0, arg1); |
1008 | tcg_gen_ext32u_tl(t1, arg2); | |
1009 | if (sub) { | |
1010 | tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); | |
bdc4e053 | 1011 | } else { |
74637406 AJ |
1012 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
1013 | } | |
a9730017 AJ |
1014 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
1015 | gen_set_label(l1); | |
1016 | tcg_temp_free(t0); | |
1017 | tcg_temp_free(t1); | |
74637406 AJ |
1018 | } else |
1019 | #endif | |
a9730017 AJ |
1020 | { |
1021 | if (sub) { | |
1022 | tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1); | |
1023 | } else { | |
1024 | tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1); | |
1025 | } | |
1026 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); | |
1027 | gen_set_label(l1); | |
74637406 | 1028 | } |
d9bce9d9 JM |
1029 | } |
1030 | ||
74637406 AJ |
1031 | /* Common add function */ |
1032 | static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, | |
1033 | int add_ca, int compute_ca, int compute_ov) | |
1034 | { | |
1035 | TCGv t0, t1; | |
d9bce9d9 | 1036 | |
74637406 | 1037 | if ((!compute_ca && !compute_ov) || |
a7812ae4 | 1038 | (!TCGV_EQUAL(ret,arg1) && !TCGV_EQUAL(ret, arg2))) { |
74637406 AJ |
1039 | t0 = ret; |
1040 | } else { | |
a7812ae4 | 1041 | t0 = tcg_temp_local_new(); |
74637406 | 1042 | } |
79aceca5 | 1043 | |
74637406 | 1044 | if (add_ca) { |
a7812ae4 | 1045 | t1 = tcg_temp_local_new(); |
74637406 AJ |
1046 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); |
1047 | tcg_gen_shri_tl(t1, t1, XER_CA); | |
1048 | } | |
79aceca5 | 1049 | |
74637406 AJ |
1050 | if (compute_ca && compute_ov) { |
1051 | /* Start with XER CA and OV disabled, the most likely case */ | |
1052 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); | |
1053 | } else if (compute_ca) { | |
1054 | /* Start with XER CA disabled, the most likely case */ | |
1055 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1056 | } else if (compute_ov) { | |
1057 | /* Start with XER OV disabled, the most likely case */ | |
1058 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1059 | } | |
79aceca5 | 1060 | |
74637406 AJ |
1061 | tcg_gen_add_tl(t0, arg1, arg2); |
1062 | ||
1063 | if (compute_ca) { | |
1064 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
1065 | } | |
1066 | if (add_ca) { | |
1067 | tcg_gen_add_tl(t0, t0, t1); | |
1068 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
1069 | tcg_temp_free(t1); | |
1070 | } | |
1071 | if (compute_ov) { | |
1072 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
1073 | } | |
1074 | ||
1075 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1076 | gen_set_Rc0(ctx, t0); | |
1077 | ||
a7812ae4 | 1078 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1079 | tcg_gen_mov_tl(ret, t0); |
1080 | tcg_temp_free(t0); | |
1081 | } | |
39dd32ee | 1082 | } |
74637406 AJ |
1083 | /* Add functions with two operands */ |
1084 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
99e300ef BS |
1085 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER); \ |
1086 | \ | |
1087 | static void glue(gen_, name)(DisasContext *ctx) \ | |
74637406 AJ |
1088 | { \ |
1089 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1090 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1091 | add_ca, compute_ca, compute_ov); \ | |
1092 | } | |
1093 | /* Add functions with one operand and one immediate */ | |
1094 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
1095 | add_ca, compute_ca, compute_ov) \ | |
99e300ef BS |
1096 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER); \ |
1097 | \ | |
1098 | static void glue(gen_, name)(DisasContext *ctx) \ | |
74637406 AJ |
1099 | { \ |
1100 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
1101 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1102 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
1103 | add_ca, compute_ca, compute_ov); \ | |
1104 | tcg_temp_free(t0); \ | |
1105 | } | |
1106 | ||
1107 | /* add add. addo addo. */ | |
1108 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
1109 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
1110 | /* addc addc. addco addco. */ | |
1111 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
1112 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
1113 | /* adde adde. addeo addeo. */ | |
1114 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
1115 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
1116 | /* addme addme. addmeo addmeo. */ | |
1117 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
1118 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
1119 | /* addze addze. addzeo addzeo.*/ | |
1120 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
1121 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
1122 | /* addi */ | |
99e300ef | 1123 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 1124 | { |
74637406 AJ |
1125 | target_long simm = SIMM(ctx->opcode); |
1126 | ||
1127 | if (rA(ctx->opcode) == 0) { | |
1128 | /* li case */ | |
1129 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
1130 | } else { | |
1131 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm); | |
1132 | } | |
d9bce9d9 | 1133 | } |
74637406 AJ |
1134 | /* addic addic.*/ |
1135 | static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1, | |
1136 | int compute_Rc0) | |
d9bce9d9 | 1137 | { |
74637406 AJ |
1138 | target_long simm = SIMM(ctx->opcode); |
1139 | ||
1140 | /* Start with XER CA and OV disabled, the most likely case */ | |
1141 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1142 | ||
1143 | if (likely(simm != 0)) { | |
a7812ae4 | 1144 | TCGv t0 = tcg_temp_local_new(); |
74637406 AJ |
1145 | tcg_gen_addi_tl(t0, arg1, simm); |
1146 | gen_op_arith_compute_ca(ctx, t0, arg1, 0); | |
1147 | tcg_gen_mov_tl(ret, t0); | |
1148 | tcg_temp_free(t0); | |
1149 | } else { | |
1150 | tcg_gen_mov_tl(ret, arg1); | |
1151 | } | |
1152 | if (compute_Rc0) { | |
1153 | gen_set_Rc0(ctx, ret); | |
1154 | } | |
d9bce9d9 | 1155 | } |
99e300ef BS |
1156 | |
1157 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 1158 | { |
74637406 | 1159 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
d9bce9d9 | 1160 | } |
e8eaa2c0 BS |
1161 | |
1162 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 1163 | { |
74637406 | 1164 | gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
d9bce9d9 | 1165 | } |
99e300ef | 1166 | |
54623277 | 1167 | /* addis */ |
99e300ef | 1168 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 1169 | { |
74637406 AJ |
1170 | target_long simm = SIMM(ctx->opcode); |
1171 | ||
1172 | if (rA(ctx->opcode) == 0) { | |
1173 | /* lis case */ | |
1174 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
1175 | } else { | |
1176 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16); | |
1177 | } | |
d9bce9d9 | 1178 | } |
74637406 AJ |
1179 | |
1180 | static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, | |
1181 | int sign, int compute_ov) | |
d9bce9d9 | 1182 | { |
2ef1b120 AJ |
1183 | int l1 = gen_new_label(); |
1184 | int l2 = gen_new_label(); | |
a7812ae4 PB |
1185 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
1186 | TCGv_i32 t1 = tcg_temp_local_new_i32(); | |
74637406 | 1187 | |
2ef1b120 AJ |
1188 | tcg_gen_trunc_tl_i32(t0, arg1); |
1189 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1190 | tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); | |
74637406 | 1191 | if (sign) { |
2ef1b120 AJ |
1192 | int l3 = gen_new_label(); |
1193 | tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); | |
1194 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); | |
74637406 | 1195 | gen_set_label(l3); |
2ef1b120 | 1196 | tcg_gen_div_i32(t0, t0, t1); |
74637406 | 1197 | } else { |
2ef1b120 | 1198 | tcg_gen_divu_i32(t0, t0, t1); |
74637406 AJ |
1199 | } |
1200 | if (compute_ov) { | |
1201 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1202 | } | |
1203 | tcg_gen_br(l2); | |
1204 | gen_set_label(l1); | |
1205 | if (sign) { | |
2ef1b120 | 1206 | tcg_gen_sari_i32(t0, t0, 31); |
74637406 AJ |
1207 | } else { |
1208 | tcg_gen_movi_i32(t0, 0); | |
1209 | } | |
1210 | if (compute_ov) { | |
1211 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1212 | } | |
1213 | gen_set_label(l2); | |
2ef1b120 | 1214 | tcg_gen_extu_i32_tl(ret, t0); |
a7812ae4 PB |
1215 | tcg_temp_free_i32(t0); |
1216 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1217 | if (unlikely(Rc(ctx->opcode) != 0)) |
1218 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1219 | } |
74637406 AJ |
1220 | /* Div functions */ |
1221 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef BS |
1222 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER); \ |
1223 | \ | |
1224 | static void glue(gen_, name)(DisasContext *ctx) \ | |
74637406 AJ |
1225 | { \ |
1226 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1227 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1228 | sign, compute_ov); \ | |
1229 | } | |
1230 | /* divwu divwu. divwuo divwuo. */ | |
1231 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1232 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1233 | /* divw divw. divwo divwo. */ | |
1234 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1235 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
d9bce9d9 | 1236 | #if defined(TARGET_PPC64) |
2ef1b120 AJ |
1237 | static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, |
1238 | int sign, int compute_ov) | |
d9bce9d9 | 1239 | { |
2ef1b120 AJ |
1240 | int l1 = gen_new_label(); |
1241 | int l2 = gen_new_label(); | |
74637406 AJ |
1242 | |
1243 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1); | |
1244 | if (sign) { | |
2ef1b120 | 1245 | int l3 = gen_new_label(); |
74637406 AJ |
1246 | tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3); |
1247 | tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1); | |
1248 | gen_set_label(l3); | |
74637406 AJ |
1249 | tcg_gen_div_i64(ret, arg1, arg2); |
1250 | } else { | |
1251 | tcg_gen_divu_i64(ret, arg1, arg2); | |
1252 | } | |
1253 | if (compute_ov) { | |
1254 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1255 | } | |
1256 | tcg_gen_br(l2); | |
1257 | gen_set_label(l1); | |
1258 | if (sign) { | |
1259 | tcg_gen_sari_i64(ret, arg1, 63); | |
1260 | } else { | |
1261 | tcg_gen_movi_i64(ret, 0); | |
1262 | } | |
1263 | if (compute_ov) { | |
1264 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1265 | } | |
1266 | gen_set_label(l2); | |
1267 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1268 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1269 | } |
74637406 | 1270 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef BS |
1271 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B); \ |
1272 | \ | |
1273 | static void glue(gen_, name)(DisasContext *ctx) \ | |
74637406 | 1274 | { \ |
2ef1b120 AJ |
1275 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1276 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1277 | sign, compute_ov); \ | |
74637406 AJ |
1278 | } |
1279 | /* divwu divwu. divwuo divwuo. */ | |
1280 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1281 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1282 | /* divw divw. divwo divwo. */ | |
1283 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1284 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
d9bce9d9 | 1285 | #endif |
74637406 AJ |
1286 | |
1287 | /* mulhw mulhw. */ | |
99e300ef | 1288 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1289 | { |
a7812ae4 | 1290 | TCGv_i64 t0, t1; |
74637406 | 1291 | |
a7812ae4 PB |
1292 | t0 = tcg_temp_new_i64(); |
1293 | t1 = tcg_temp_new_i64(); | |
74637406 AJ |
1294 | #if defined(TARGET_PPC64) |
1295 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1296 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1297 | tcg_gen_mul_i64(t0, t0, t1); | |
1298 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
1299 | #else | |
1300 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1301 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1302 | tcg_gen_mul_i64(t0, t0, t1); | |
1303 | tcg_gen_shri_i64(t0, t0, 32); | |
1304 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1305 | #endif | |
a7812ae4 PB |
1306 | tcg_temp_free_i64(t0); |
1307 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1308 | if (unlikely(Rc(ctx->opcode) != 0)) |
1309 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1310 | } |
99e300ef | 1311 | |
54623277 | 1312 | /* mulhwu mulhwu. */ |
99e300ef | 1313 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1314 | { |
a7812ae4 | 1315 | TCGv_i64 t0, t1; |
74637406 | 1316 | |
a7812ae4 PB |
1317 | t0 = tcg_temp_new_i64(); |
1318 | t1 = tcg_temp_new_i64(); | |
d9bce9d9 | 1319 | #if defined(TARGET_PPC64) |
74637406 AJ |
1320 | tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
1321 | tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1322 | tcg_gen_mul_i64(t0, t0, t1); | |
1323 | tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
1324 | #else | |
1325 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1326 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1327 | tcg_gen_mul_i64(t0, t0, t1); | |
1328 | tcg_gen_shri_i64(t0, t0, 32); | |
1329 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1330 | #endif | |
a7812ae4 PB |
1331 | tcg_temp_free_i64(t0); |
1332 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1333 | if (unlikely(Rc(ctx->opcode) != 0)) |
1334 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1335 | } |
99e300ef | 1336 | |
54623277 | 1337 | /* mullw mullw. */ |
99e300ef | 1338 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1339 | { |
74637406 AJ |
1340 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1341 | cpu_gpr[rB(ctx->opcode)]); | |
1e4c090f | 1342 | tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]); |
74637406 AJ |
1343 | if (unlikely(Rc(ctx->opcode) != 0)) |
1344 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1345 | } |
99e300ef | 1346 | |
54623277 | 1347 | /* mullwo mullwo. */ |
99e300ef | 1348 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1349 | { |
74637406 | 1350 | int l1; |
a7812ae4 | 1351 | TCGv_i64 t0, t1; |
74637406 | 1352 | |
a7812ae4 PB |
1353 | t0 = tcg_temp_new_i64(); |
1354 | t1 = tcg_temp_new_i64(); | |
74637406 AJ |
1355 | l1 = gen_new_label(); |
1356 | /* Start with XER OV disabled, the most likely case */ | |
1357 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1358 | #if defined(TARGET_PPC64) | |
1359 | tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1360 | tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
1361 | #else | |
1362 | tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
1363 | tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
d9bce9d9 | 1364 | #endif |
74637406 AJ |
1365 | tcg_gen_mul_i64(t0, t0, t1); |
1366 | #if defined(TARGET_PPC64) | |
1367 | tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1368 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1); | |
1369 | #else | |
1370 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1371 | tcg_gen_ext32s_i64(t1, t0); | |
1372 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
1373 | #endif | |
1374 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1375 | gen_set_label(l1); | |
a7812ae4 PB |
1376 | tcg_temp_free_i64(t0); |
1377 | tcg_temp_free_i64(t1); | |
74637406 AJ |
1378 | if (unlikely(Rc(ctx->opcode) != 0)) |
1379 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1380 | } |
99e300ef | 1381 | |
54623277 | 1382 | /* mulli */ |
99e300ef | 1383 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1384 | { |
74637406 AJ |
1385 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1386 | SIMM(ctx->opcode)); | |
d9bce9d9 JM |
1387 | } |
1388 | #if defined(TARGET_PPC64) | |
74637406 | 1389 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ |
99e300ef BS |
1390 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B); \ |
1391 | \ | |
1392 | static void glue(gen_, name)(DisasContext *ctx) \ | |
74637406 | 1393 | { \ |
a7812ae4 | 1394 | gen_helper_##name (cpu_gpr[rD(ctx->opcode)], \ |
74637406 AJ |
1395 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ |
1396 | if (unlikely(Rc(ctx->opcode) != 0)) \ | |
1397 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
d9bce9d9 | 1398 | } |
74637406 AJ |
1399 | /* mulhd mulhd. */ |
1400 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00); | |
1401 | /* mulhdu mulhdu. */ | |
1402 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02); | |
99e300ef | 1403 | |
54623277 | 1404 | /* mulld mulld. */ |
99e300ef | 1405 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1406 | { |
74637406 AJ |
1407 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1408 | cpu_gpr[rB(ctx->opcode)]); | |
1409 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1410 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1411 | } |
74637406 AJ |
1412 | /* mulldo mulldo. */ |
1413 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17); | |
d9bce9d9 | 1414 | #endif |
74637406 AJ |
1415 | |
1416 | /* neg neg. nego nego. */ | |
ec6469a3 | 1417 | static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check) |
d9bce9d9 | 1418 | { |
ec6469a3 AJ |
1419 | int l1 = gen_new_label(); |
1420 | int l2 = gen_new_label(); | |
a7812ae4 | 1421 | TCGv t0 = tcg_temp_local_new(); |
d9bce9d9 | 1422 | #if defined(TARGET_PPC64) |
74637406 | 1423 | if (ctx->sf_mode) { |
741a7444 | 1424 | tcg_gen_mov_tl(t0, arg1); |
ec6469a3 AJ |
1425 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1); |
1426 | } else | |
1427 | #endif | |
1428 | { | |
1429 | tcg_gen_ext32s_tl(t0, arg1); | |
74637406 AJ |
1430 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1); |
1431 | } | |
74637406 AJ |
1432 | tcg_gen_neg_tl(ret, arg1); |
1433 | if (ov_check) { | |
1434 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1435 | } | |
1436 | tcg_gen_br(l2); | |
1437 | gen_set_label(l1); | |
ec6469a3 | 1438 | tcg_gen_mov_tl(ret, t0); |
74637406 AJ |
1439 | if (ov_check) { |
1440 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
1441 | } | |
1442 | gen_set_label(l2); | |
ec6469a3 | 1443 | tcg_temp_free(t0); |
74637406 AJ |
1444 | if (unlikely(Rc(ctx->opcode) != 0)) |
1445 | gen_set_Rc0(ctx, ret); | |
1446 | } | |
99e300ef BS |
1447 | |
1448 | static void gen_neg(DisasContext *ctx) | |
d9bce9d9 | 1449 | { |
ec6469a3 | 1450 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0); |
d9bce9d9 | 1451 | } |
99e300ef BS |
1452 | |
1453 | static void gen_nego(DisasContext *ctx) | |
79aceca5 | 1454 | { |
ec6469a3 | 1455 | gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1); |
79aceca5 | 1456 | } |
74637406 AJ |
1457 | |
1458 | /* Common subf function */ | |
1459 | static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2, | |
1460 | int add_ca, int compute_ca, int compute_ov) | |
79aceca5 | 1461 | { |
74637406 | 1462 | TCGv t0, t1; |
76a66253 | 1463 | |
74637406 | 1464 | if ((!compute_ca && !compute_ov) || |
a7812ae4 | 1465 | (!TCGV_EQUAL(ret, arg1) && !TCGV_EQUAL(ret, arg2))) { |
74637406 | 1466 | t0 = ret; |
e864cabd | 1467 | } else { |
a7812ae4 | 1468 | t0 = tcg_temp_local_new(); |
d9bce9d9 | 1469 | } |
76a66253 | 1470 | |
74637406 | 1471 | if (add_ca) { |
a7812ae4 | 1472 | t1 = tcg_temp_local_new(); |
74637406 AJ |
1473 | tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA)); |
1474 | tcg_gen_shri_tl(t1, t1, XER_CA); | |
d9bce9d9 | 1475 | } |
79aceca5 | 1476 | |
74637406 AJ |
1477 | if (compute_ca && compute_ov) { |
1478 | /* Start with XER CA and OV disabled, the most likely case */ | |
1479 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV))); | |
1480 | } else if (compute_ca) { | |
1481 | /* Start with XER CA disabled, the most likely case */ | |
1482 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
1483 | } else if (compute_ov) { | |
1484 | /* Start with XER OV disabled, the most likely case */ | |
1485 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
1486 | } | |
1487 | ||
1488 | if (add_ca) { | |
1489 | tcg_gen_not_tl(t0, arg1); | |
1490 | tcg_gen_add_tl(t0, t0, arg2); | |
1491 | gen_op_arith_compute_ca(ctx, t0, arg2, 0); | |
1492 | tcg_gen_add_tl(t0, t0, t1); | |
1493 | gen_op_arith_compute_ca(ctx, t0, t1, 0); | |
1494 | tcg_temp_free(t1); | |
79aceca5 | 1495 | } else { |
74637406 AJ |
1496 | tcg_gen_sub_tl(t0, arg2, arg1); |
1497 | if (compute_ca) { | |
1498 | gen_op_arith_compute_ca(ctx, t0, arg2, 1); | |
1499 | } | |
1500 | } | |
1501 | if (compute_ov) { | |
1502 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1503 | } | |
1504 | ||
1505 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1506 | gen_set_Rc0(ctx, t0); | |
1507 | ||
a7812ae4 | 1508 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1509 | tcg_gen_mov_tl(ret, t0); |
1510 | tcg_temp_free(t0); | |
79aceca5 | 1511 | } |
79aceca5 | 1512 | } |
74637406 AJ |
1513 | /* Sub functions with Two operands functions */ |
1514 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
99e300ef BS |
1515 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER); \ |
1516 | \ | |
1517 | static void glue(gen_, name)(DisasContext *ctx) \ | |
74637406 AJ |
1518 | { \ |
1519 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1520 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1521 | add_ca, compute_ca, compute_ov); \ | |
1522 | } | |
1523 | /* Sub functions with one operand and one immediate */ | |
1524 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1525 | add_ca, compute_ca, compute_ov) \ | |
99e300ef BS |
1526 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER); \ |
1527 | \ | |
1528 | static void glue(gen_, name)(DisasContext *ctx) \ | |
74637406 AJ |
1529 | { \ |
1530 | TCGv t0 = tcg_const_local_tl(const_val); \ | |
1531 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1532 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
1533 | add_ca, compute_ca, compute_ov); \ | |
1534 | tcg_temp_free(t0); \ | |
1535 | } | |
1536 | /* subf subf. subfo subfo. */ | |
1537 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1538 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1539 | /* subfc subfc. subfco subfco. */ | |
1540 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1541 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1542 | /* subfe subfe. subfeo subfo. */ | |
1543 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1544 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1545 | /* subfme subfme. subfmeo subfmeo. */ | |
1546 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1547 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1548 | /* subfze subfze. subfzeo subfzeo.*/ | |
1549 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1550 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1551 | |
54623277 | 1552 | /* subfic */ |
99e300ef | 1553 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1554 | { |
74637406 AJ |
1555 | /* Start with XER CA and OV disabled, the most likely case */ |
1556 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
a7812ae4 | 1557 | TCGv t0 = tcg_temp_local_new(); |
74637406 AJ |
1558 | TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode)); |
1559 | tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]); | |
1560 | gen_op_arith_compute_ca(ctx, t0, t1, 1); | |
1561 | tcg_temp_free(t1); | |
1562 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
1563 | tcg_temp_free(t0); | |
79aceca5 FB |
1564 | } |
1565 | ||
79aceca5 | 1566 | /*** Integer logical ***/ |
26d67362 | 1567 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef BS |
1568 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type); \ |
1569 | \ | |
1570 | static void glue(gen_, name)(DisasContext *ctx) \ | |
79aceca5 | 1571 | { \ |
26d67362 AJ |
1572 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1573 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1574 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1575 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1576 | } |
79aceca5 | 1577 | |
26d67362 | 1578 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef BS |
1579 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type); \ |
1580 | \ | |
1581 | static void glue(gen_, name)(DisasContext *ctx) \ | |
79aceca5 | 1582 | { \ |
26d67362 | 1583 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1584 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1585 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1586 | } |
1587 | ||
1588 | /* and & and. */ | |
26d67362 | 1589 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1590 | /* andc & andc. */ |
26d67362 | 1591 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1592 | |
54623277 | 1593 | /* andi. */ |
e8eaa2c0 | 1594 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1595 | { |
26d67362 AJ |
1596 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1597 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1598 | } |
e8eaa2c0 | 1599 | |
54623277 | 1600 | /* andis. */ |
e8eaa2c0 | 1601 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1602 | { |
26d67362 AJ |
1603 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1604 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1605 | } |
99e300ef | 1606 | |
54623277 | 1607 | /* cntlzw */ |
99e300ef | 1608 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1609 | { |
a7812ae4 | 1610 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1611 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1612 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1613 | } |
79aceca5 | 1614 | /* eqv & eqv. */ |
26d67362 | 1615 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1616 | /* extsb & extsb. */ |
26d67362 | 1617 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1618 | /* extsh & extsh. */ |
26d67362 | 1619 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1620 | /* nand & nand. */ |
26d67362 | 1621 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1622 | /* nor & nor. */ |
26d67362 | 1623 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1624 | |
54623277 | 1625 | /* or & or. */ |
99e300ef | 1626 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1627 | { |
76a66253 JM |
1628 | int rs, ra, rb; |
1629 | ||
1630 | rs = rS(ctx->opcode); | |
1631 | ra = rA(ctx->opcode); | |
1632 | rb = rB(ctx->opcode); | |
1633 | /* Optimisation for mr. ri case */ | |
1634 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1635 | if (rs != rb) |
1636 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1637 | else | |
1638 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1639 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1640 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1641 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1642 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 JM |
1643 | #if defined(TARGET_PPC64) |
1644 | } else { | |
26d67362 AJ |
1645 | int prio = 0; |
1646 | ||
c80f84e3 JM |
1647 | switch (rs) { |
1648 | case 1: | |
1649 | /* Set process priority to low */ | |
26d67362 | 1650 | prio = 2; |
c80f84e3 JM |
1651 | break; |
1652 | case 6: | |
1653 | /* Set process priority to medium-low */ | |
26d67362 | 1654 | prio = 3; |
c80f84e3 JM |
1655 | break; |
1656 | case 2: | |
1657 | /* Set process priority to normal */ | |
26d67362 | 1658 | prio = 4; |
c80f84e3 | 1659 | break; |
be147d08 JM |
1660 | #if !defined(CONFIG_USER_ONLY) |
1661 | case 31: | |
76db3ba4 | 1662 | if (ctx->mem_idx > 0) { |
be147d08 | 1663 | /* Set process priority to very low */ |
26d67362 | 1664 | prio = 1; |
be147d08 JM |
1665 | } |
1666 | break; | |
1667 | case 5: | |
76db3ba4 | 1668 | if (ctx->mem_idx > 0) { |
be147d08 | 1669 | /* Set process priority to medium-hight */ |
26d67362 | 1670 | prio = 5; |
be147d08 JM |
1671 | } |
1672 | break; | |
1673 | case 3: | |
76db3ba4 | 1674 | if (ctx->mem_idx > 0) { |
be147d08 | 1675 | /* Set process priority to high */ |
26d67362 | 1676 | prio = 6; |
be147d08 JM |
1677 | } |
1678 | break; | |
be147d08 | 1679 | case 7: |
76db3ba4 | 1680 | if (ctx->mem_idx > 1) { |
be147d08 | 1681 | /* Set process priority to very high */ |
26d67362 | 1682 | prio = 7; |
be147d08 JM |
1683 | } |
1684 | break; | |
be147d08 | 1685 | #endif |
c80f84e3 JM |
1686 | default: |
1687 | /* nop */ | |
1688 | break; | |
1689 | } | |
26d67362 | 1690 | if (prio) { |
a7812ae4 | 1691 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1692 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1693 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1694 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1695 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1696 | tcg_temp_free(t0); |
26d67362 | 1697 | } |
c80f84e3 | 1698 | #endif |
9a64fbe4 | 1699 | } |
9a64fbe4 | 1700 | } |
79aceca5 | 1701 | /* orc & orc. */ |
26d67362 | 1702 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1703 | |
54623277 | 1704 | /* xor & xor. */ |
99e300ef | 1705 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1706 | { |
9a64fbe4 | 1707 | /* Optimisation for "set to zero" case */ |
26d67362 | 1708 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1709 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1710 | else |
1711 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1712 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1713 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1714 | } |
99e300ef | 1715 | |
54623277 | 1716 | /* ori */ |
99e300ef | 1717 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1718 | { |
76a66253 | 1719 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1720 | |
9a64fbe4 FB |
1721 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1722 | /* NOP */ | |
76a66253 | 1723 | /* XXX: should handle special NOPs for POWER series */ |
9a64fbe4 | 1724 | return; |
76a66253 | 1725 | } |
26d67362 | 1726 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1727 | } |
99e300ef | 1728 | |
54623277 | 1729 | /* oris */ |
99e300ef | 1730 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1731 | { |
76a66253 | 1732 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1733 | |
9a64fbe4 FB |
1734 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1735 | /* NOP */ | |
1736 | return; | |
76a66253 | 1737 | } |
26d67362 | 1738 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1739 | } |
99e300ef | 1740 | |
54623277 | 1741 | /* xori */ |
99e300ef | 1742 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1743 | { |
76a66253 | 1744 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1745 | |
1746 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1747 | /* NOP */ | |
1748 | return; | |
1749 | } | |
26d67362 | 1750 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1751 | } |
99e300ef | 1752 | |
54623277 | 1753 | /* xoris */ |
99e300ef | 1754 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1755 | { |
76a66253 | 1756 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1757 | |
1758 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1759 | /* NOP */ | |
1760 | return; | |
1761 | } | |
26d67362 | 1762 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1763 | } |
99e300ef | 1764 | |
54623277 | 1765 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1766 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1767 | { |
d9bce9d9 JM |
1768 | #if defined(TARGET_PPC64) |
1769 | if (ctx->sf_mode) | |
a7812ae4 | 1770 | gen_helper_popcntb_64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
d9bce9d9 JM |
1771 | else |
1772 | #endif | |
a7812ae4 | 1773 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
d9bce9d9 JM |
1774 | } |
1775 | ||
1776 | #if defined(TARGET_PPC64) | |
1777 | /* extsw & extsw. */ | |
26d67362 | 1778 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1779 | |
54623277 | 1780 | /* cntlzd */ |
99e300ef | 1781 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1782 | { |
a7812ae4 | 1783 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1784 | if (unlikely(Rc(ctx->opcode) != 0)) |
1785 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1786 | } | |
d9bce9d9 JM |
1787 | #endif |
1788 | ||
79aceca5 | 1789 | /*** Integer rotate ***/ |
99e300ef | 1790 | |
54623277 | 1791 | /* rlwimi & rlwimi. */ |
99e300ef | 1792 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1793 | { |
76a66253 | 1794 | uint32_t mb, me, sh; |
79aceca5 FB |
1795 | |
1796 | mb = MB(ctx->opcode); | |
1797 | me = ME(ctx->opcode); | |
76a66253 | 1798 | sh = SH(ctx->opcode); |
d03ef511 AJ |
1799 | if (likely(sh == 0 && mb == 0 && me == 31)) { |
1800 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1801 | } else { | |
d03ef511 | 1802 | target_ulong mask; |
a7812ae4 PB |
1803 | TCGv t1; |
1804 | TCGv t0 = tcg_temp_new(); | |
54843a58 | 1805 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1806 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1807 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]); | |
1808 | tcg_gen_rotli_i32(t2, t2, sh); | |
1809 | tcg_gen_extu_i32_i64(t0, t2); | |
1810 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1811 | #else |
1812 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1813 | #endif | |
76a66253 | 1814 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1815 | mb += 32; |
1816 | me += 32; | |
76a66253 | 1817 | #endif |
d03ef511 | 1818 | mask = MASK(mb, me); |
a7812ae4 | 1819 | t1 = tcg_temp_new(); |
d03ef511 AJ |
1820 | tcg_gen_andi_tl(t0, t0, mask); |
1821 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
1822 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
1823 | tcg_temp_free(t0); | |
1824 | tcg_temp_free(t1); | |
1825 | } | |
76a66253 | 1826 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1827 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1828 | } |
99e300ef | 1829 | |
54623277 | 1830 | /* rlwinm & rlwinm. */ |
99e300ef | 1831 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 FB |
1832 | { |
1833 | uint32_t mb, me, sh; | |
3b46e624 | 1834 | |
79aceca5 FB |
1835 | sh = SH(ctx->opcode); |
1836 | mb = MB(ctx->opcode); | |
1837 | me = ME(ctx->opcode); | |
d03ef511 AJ |
1838 | |
1839 | if (likely(mb == 0 && me == (31 - sh))) { | |
1840 | if (likely(sh == 0)) { | |
1841 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1842 | } else { | |
a7812ae4 | 1843 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1844 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1845 | tcg_gen_shli_tl(t0, t0, sh); | |
1846 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1847 | tcg_temp_free(t0); | |
79aceca5 | 1848 | } |
d03ef511 | 1849 | } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) { |
a7812ae4 | 1850 | TCGv t0 = tcg_temp_new(); |
d03ef511 AJ |
1851 | tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
1852 | tcg_gen_shri_tl(t0, t0, mb); | |
1853 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
1854 | tcg_temp_free(t0); | |
1855 | } else { | |
a7812ae4 | 1856 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1857 | #if defined(TARGET_PPC64) |
a7812ae4 | 1858 | TCGv_i32 t1 = tcg_temp_new_i32(); |
54843a58 AJ |
1859 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1860 | tcg_gen_rotli_i32(t1, t1, sh); | |
1861 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 | 1862 | tcg_temp_free_i32(t1); |
54843a58 AJ |
1863 | #else |
1864 | tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
1865 | #endif | |
76a66253 | 1866 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1867 | mb += 32; |
1868 | me += 32; | |
76a66253 | 1869 | #endif |
d03ef511 AJ |
1870 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
1871 | tcg_temp_free(t0); | |
1872 | } | |
76a66253 | 1873 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1874 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 1875 | } |
99e300ef | 1876 | |
54623277 | 1877 | /* rlwnm & rlwnm. */ |
99e300ef | 1878 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 FB |
1879 | { |
1880 | uint32_t mb, me; | |
54843a58 AJ |
1881 | TCGv t0; |
1882 | #if defined(TARGET_PPC64) | |
a7812ae4 | 1883 | TCGv_i32 t1, t2; |
54843a58 | 1884 | #endif |
79aceca5 FB |
1885 | |
1886 | mb = MB(ctx->opcode); | |
1887 | me = ME(ctx->opcode); | |
a7812ae4 | 1888 | t0 = tcg_temp_new(); |
d03ef511 | 1889 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f); |
54843a58 | 1890 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
1891 | t1 = tcg_temp_new_i32(); |
1892 | t2 = tcg_temp_new_i32(); | |
54843a58 AJ |
1893 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]); |
1894 | tcg_gen_trunc_i64_i32(t2, t0); | |
1895 | tcg_gen_rotl_i32(t1, t1, t2); | |
1896 | tcg_gen_extu_i32_i64(t0, t1); | |
a7812ae4 PB |
1897 | tcg_temp_free_i32(t1); |
1898 | tcg_temp_free_i32(t2); | |
54843a58 AJ |
1899 | #else |
1900 | tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
1901 | #endif | |
76a66253 JM |
1902 | if (unlikely(mb != 0 || me != 31)) { |
1903 | #if defined(TARGET_PPC64) | |
1904 | mb += 32; | |
1905 | me += 32; | |
1906 | #endif | |
54843a58 | 1907 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
d03ef511 | 1908 | } else { |
54843a58 | 1909 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
79aceca5 | 1910 | } |
54843a58 | 1911 | tcg_temp_free(t0); |
76a66253 | 1912 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1913 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 FB |
1914 | } |
1915 | ||
d9bce9d9 JM |
1916 | #if defined(TARGET_PPC64) |
1917 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 BS |
1918 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B);\ |
1919 | \ | |
1920 | static void glue(gen_, name##0)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1921 | { \ |
1922 | gen_##name(ctx, 0); \ | |
1923 | } \ | |
c7697e1f | 1924 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
e8eaa2c0 BS |
1925 | PPC_64B); \ |
1926 | \ | |
1927 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1928 | { \ |
1929 | gen_##name(ctx, 1); \ | |
1930 | } | |
1931 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 BS |
1932 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B);\ |
1933 | \ | |
1934 | static void glue(gen_, name##0)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1935 | { \ |
1936 | gen_##name(ctx, 0, 0); \ | |
1937 | } \ | |
c7697e1f | 1938 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
e8eaa2c0 BS |
1939 | PPC_64B); \ |
1940 | \ | |
1941 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1942 | { \ |
1943 | gen_##name(ctx, 0, 1); \ | |
1944 | } \ | |
c7697e1f | 1945 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
e8eaa2c0 BS |
1946 | PPC_64B); \ |
1947 | \ | |
1948 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1949 | { \ |
1950 | gen_##name(ctx, 1, 0); \ | |
1951 | } \ | |
c7697e1f JM |
1952 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
1953 | PPC_64B) \ | |
e8eaa2c0 BS |
1954 | \ |
1955 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
1956 | { \ |
1957 | gen_##name(ctx, 1, 1); \ | |
1958 | } | |
51789c41 | 1959 | |
b068d6a7 JM |
1960 | static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb, |
1961 | uint32_t me, uint32_t sh) | |
51789c41 | 1962 | { |
d03ef511 AJ |
1963 | if (likely(sh != 0 && mb == 0 && me == (63 - sh))) { |
1964 | tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
1965 | } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) { | |
1966 | tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb); | |
1967 | } else { | |
a7812ae4 | 1968 | TCGv t0 = tcg_temp_new(); |
54843a58 | 1969 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
d03ef511 | 1970 | if (likely(mb == 0 && me == 63)) { |
54843a58 | 1971 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
d03ef511 AJ |
1972 | } else { |
1973 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); | |
51789c41 | 1974 | } |
d03ef511 | 1975 | tcg_temp_free(t0); |
51789c41 | 1976 | } |
51789c41 | 1977 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 1978 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
51789c41 | 1979 | } |
d9bce9d9 | 1980 | /* rldicl - rldicl. */ |
b068d6a7 | 1981 | static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 1982 | { |
51789c41 | 1983 | uint32_t sh, mb; |
d9bce9d9 | 1984 | |
9d53c753 JM |
1985 | sh = SH(ctx->opcode) | (shn << 5); |
1986 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 1987 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 1988 | } |
51789c41 | 1989 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
d9bce9d9 | 1990 | /* rldicr - rldicr. */ |
b068d6a7 | 1991 | static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn) |
d9bce9d9 | 1992 | { |
51789c41 | 1993 | uint32_t sh, me; |
d9bce9d9 | 1994 | |
9d53c753 JM |
1995 | sh = SH(ctx->opcode) | (shn << 5); |
1996 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 1997 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 1998 | } |
51789c41 | 1999 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
d9bce9d9 | 2000 | /* rldic - rldic. */ |
b068d6a7 | 2001 | static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2002 | { |
51789c41 | 2003 | uint32_t sh, mb; |
d9bce9d9 | 2004 | |
9d53c753 JM |
2005 | sh = SH(ctx->opcode) | (shn << 5); |
2006 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
2007 | gen_rldinm(ctx, mb, 63 - sh, sh); |
2008 | } | |
2009 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
2010 | ||
b068d6a7 JM |
2011 | static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb, |
2012 | uint32_t me) | |
51789c41 | 2013 | { |
54843a58 | 2014 | TCGv t0; |
d03ef511 AJ |
2015 | |
2016 | mb = MB(ctx->opcode); | |
2017 | me = ME(ctx->opcode); | |
a7812ae4 | 2018 | t0 = tcg_temp_new(); |
d03ef511 | 2019 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
54843a58 | 2020 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
51789c41 | 2021 | if (unlikely(mb != 0 || me != 63)) { |
54843a58 AJ |
2022 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me)); |
2023 | } else { | |
2024 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
2025 | } | |
2026 | tcg_temp_free(t0); | |
51789c41 | 2027 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 2028 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 2029 | } |
51789c41 | 2030 | |
d9bce9d9 | 2031 | /* rldcl - rldcl. */ |
b068d6a7 | 2032 | static always_inline void gen_rldcl (DisasContext *ctx, int mbn) |
d9bce9d9 | 2033 | { |
51789c41 | 2034 | uint32_t mb; |
d9bce9d9 | 2035 | |
9d53c753 | 2036 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 2037 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 2038 | } |
36081602 | 2039 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
d9bce9d9 | 2040 | /* rldcr - rldcr. */ |
b068d6a7 | 2041 | static always_inline void gen_rldcr (DisasContext *ctx, int men) |
d9bce9d9 | 2042 | { |
51789c41 | 2043 | uint32_t me; |
d9bce9d9 | 2044 | |
9d53c753 | 2045 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 2046 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 2047 | } |
36081602 | 2048 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
d9bce9d9 | 2049 | /* rldimi - rldimi. */ |
b068d6a7 | 2050 | static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2051 | { |
271a916e | 2052 | uint32_t sh, mb, me; |
d9bce9d9 | 2053 | |
9d53c753 JM |
2054 | sh = SH(ctx->opcode) | (shn << 5); |
2055 | mb = MB(ctx->opcode) | (mbn << 5); | |
271a916e | 2056 | me = 63 - sh; |
d03ef511 AJ |
2057 | if (unlikely(sh == 0 && mb == 0)) { |
2058 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
2059 | } else { | |
2060 | TCGv t0, t1; | |
2061 | target_ulong mask; | |
2062 | ||
a7812ae4 | 2063 | t0 = tcg_temp_new(); |
54843a58 | 2064 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
a7812ae4 | 2065 | t1 = tcg_temp_new(); |
d03ef511 AJ |
2066 | mask = MASK(mb, me); |
2067 | tcg_gen_andi_tl(t0, t0, mask); | |
2068 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask); | |
2069 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2070 | tcg_temp_free(t0); | |
2071 | tcg_temp_free(t1); | |
51789c41 | 2072 | } |
51789c41 | 2073 | if (unlikely(Rc(ctx->opcode) != 0)) |
d03ef511 | 2074 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 2075 | } |
36081602 | 2076 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
2077 | #endif |
2078 | ||
79aceca5 | 2079 | /*** Integer shift ***/ |
99e300ef | 2080 | |
54623277 | 2081 | /* slw & slw. */ |
99e300ef | 2082 | static void gen_slw(DisasContext *ctx) |
26d67362 | 2083 | { |
fea0c503 | 2084 | TCGv t0; |
26d67362 AJ |
2085 | int l1, l2; |
2086 | l1 = gen_new_label(); | |
2087 | l2 = gen_new_label(); | |
2088 | ||
a7812ae4 | 2089 | t0 = tcg_temp_local_new(); |
0cfe58cd AJ |
2090 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
2091 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1); | |
26d67362 AJ |
2092 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
2093 | tcg_gen_br(l2); | |
2094 | gen_set_label(l1); | |
fea0c503 | 2095 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0); |
26d67362 AJ |
2096 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
2097 | gen_set_label(l2); | |
fea0c503 | 2098 | tcg_temp_free(t0); |
26d67362 AJ |
2099 | if (unlikely(Rc(ctx->opcode) != 0)) |
2100 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2101 | } | |
99e300ef | 2102 | |
54623277 | 2103 | /* sraw & sraw. */ |
99e300ef | 2104 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 2105 | { |
a7812ae4 PB |
2106 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], |
2107 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
26d67362 AJ |
2108 | if (unlikely(Rc(ctx->opcode) != 0)) |
2109 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2110 | } | |
99e300ef | 2111 | |
54623277 | 2112 | /* srawi & srawi. */ |
99e300ef | 2113 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 2114 | { |
26d67362 AJ |
2115 | int sh = SH(ctx->opcode); |
2116 | if (sh != 0) { | |
2117 | int l1, l2; | |
fea0c503 | 2118 | TCGv t0; |
26d67362 AJ |
2119 | l1 = gen_new_label(); |
2120 | l2 = gen_new_label(); | |
a7812ae4 | 2121 | t0 = tcg_temp_local_new(); |
fea0c503 AJ |
2122 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
2123 | tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1); | |
2124 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); | |
2125 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
269f3e95 | 2126 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
26d67362 AJ |
2127 | tcg_gen_br(l2); |
2128 | gen_set_label(l1); | |
269f3e95 | 2129 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
26d67362 | 2130 | gen_set_label(l2); |
fea0c503 AJ |
2131 | tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]); |
2132 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh); | |
2133 | tcg_temp_free(t0); | |
26d67362 AJ |
2134 | } else { |
2135 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
269f3e95 | 2136 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
d9bce9d9 | 2137 | } |
76a66253 | 2138 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 2139 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
79aceca5 | 2140 | } |
99e300ef | 2141 | |
54623277 | 2142 | /* srw & srw. */ |
99e300ef | 2143 | static void gen_srw(DisasContext *ctx) |
26d67362 | 2144 | { |
fea0c503 | 2145 | TCGv t0, t1; |
26d67362 AJ |
2146 | int l1, l2; |
2147 | l1 = gen_new_label(); | |
2148 | l2 = gen_new_label(); | |
d9bce9d9 | 2149 | |
a7812ae4 | 2150 | t0 = tcg_temp_local_new(); |
0cfe58cd AJ |
2151 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f); |
2152 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x20, l1); | |
26d67362 AJ |
2153 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
2154 | tcg_gen_br(l2); | |
2155 | gen_set_label(l1); | |
a7812ae4 | 2156 | t1 = tcg_temp_new(); |
fea0c503 AJ |
2157 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); |
2158 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0); | |
2159 | tcg_temp_free(t1); | |
26d67362 | 2160 | gen_set_label(l2); |
fea0c503 | 2161 | tcg_temp_free(t0); |
26d67362 AJ |
2162 | if (unlikely(Rc(ctx->opcode) != 0)) |
2163 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2164 | } | |
54623277 | 2165 | |
d9bce9d9 JM |
2166 | #if defined(TARGET_PPC64) |
2167 | /* sld & sld. */ | |
99e300ef | 2168 | static void gen_sld(DisasContext *ctx) |
26d67362 | 2169 | { |
fea0c503 | 2170 | TCGv t0; |
26d67362 AJ |
2171 | int l1, l2; |
2172 | l1 = gen_new_label(); | |
2173 | l2 = gen_new_label(); | |
2174 | ||
a7812ae4 | 2175 | t0 = tcg_temp_local_new(); |
0cfe58cd AJ |
2176 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f); |
2177 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1); | |
26d67362 AJ |
2178 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
2179 | tcg_gen_br(l2); | |
2180 | gen_set_label(l1); | |
fea0c503 | 2181 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0); |
26d67362 | 2182 | gen_set_label(l2); |
fea0c503 | 2183 | tcg_temp_free(t0); |
26d67362 AJ |
2184 | if (unlikely(Rc(ctx->opcode) != 0)) |
2185 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2186 | } | |
99e300ef | 2187 | |
54623277 | 2188 | /* srad & srad. */ |
99e300ef | 2189 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2190 | { |
a7812ae4 PB |
2191 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], |
2192 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
26d67362 AJ |
2193 | if (unlikely(Rc(ctx->opcode) != 0)) |
2194 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2195 | } | |
d9bce9d9 | 2196 | /* sradi & sradi. */ |
b068d6a7 | 2197 | static always_inline void gen_sradi (DisasContext *ctx, int n) |
d9bce9d9 | 2198 | { |
26d67362 | 2199 | int sh = SH(ctx->opcode) + (n << 5); |
d9bce9d9 | 2200 | if (sh != 0) { |
26d67362 | 2201 | int l1, l2; |
fea0c503 | 2202 | TCGv t0; |
26d67362 AJ |
2203 | l1 = gen_new_label(); |
2204 | l2 = gen_new_label(); | |
a7812ae4 | 2205 | t0 = tcg_temp_local_new(); |
26d67362 | 2206 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); |
fea0c503 AJ |
2207 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1); |
2208 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
269f3e95 | 2209 | tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA); |
26d67362 AJ |
2210 | tcg_gen_br(l2); |
2211 | gen_set_label(l1); | |
269f3e95 | 2212 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
26d67362 | 2213 | gen_set_label(l2); |
a9730017 | 2214 | tcg_temp_free(t0); |
26d67362 AJ |
2215 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
2216 | } else { | |
2217 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
269f3e95 | 2218 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); |
d9bce9d9 | 2219 | } |
d9bce9d9 | 2220 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 2221 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
d9bce9d9 | 2222 | } |
e8eaa2c0 BS |
2223 | |
2224 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2225 | { |
2226 | gen_sradi(ctx, 0); | |
2227 | } | |
e8eaa2c0 BS |
2228 | |
2229 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2230 | { |
2231 | gen_sradi(ctx, 1); | |
2232 | } | |
99e300ef | 2233 | |
54623277 | 2234 | /* srd & srd. */ |
99e300ef | 2235 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2236 | { |
fea0c503 | 2237 | TCGv t0; |
26d67362 AJ |
2238 | int l1, l2; |
2239 | l1 = gen_new_label(); | |
2240 | l2 = gen_new_label(); | |
2241 | ||
a7812ae4 | 2242 | t0 = tcg_temp_local_new(); |
0cfe58cd AJ |
2243 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f); |
2244 | tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0x40, l1); | |
26d67362 AJ |
2245 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
2246 | tcg_gen_br(l2); | |
2247 | gen_set_label(l1); | |
fea0c503 | 2248 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0); |
26d67362 | 2249 | gen_set_label(l2); |
fea0c503 | 2250 | tcg_temp_free(t0); |
26d67362 AJ |
2251 | if (unlikely(Rc(ctx->opcode) != 0)) |
2252 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2253 | } | |
d9bce9d9 | 2254 | #endif |
79aceca5 FB |
2255 | |
2256 | /*** Floating-Point arithmetic ***/ | |
7c58044c | 2257 | #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \ |
99e300ef BS |
2258 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type); \ |
2259 | \ | |
2260 | static void gen_f##name(DisasContext *ctx) \ | |
9a64fbe4 | 2261 | { \ |
76a66253 | 2262 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2263 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2264 | return; \ |
2265 | } \ | |
eb44b959 AJ |
2266 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2267 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2268 | gen_reset_fpstatus(); \ |
af12906f AJ |
2269 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
2270 | cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ | |
4ecc3190 | 2271 | if (isfloat) { \ |
af12906f | 2272 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
4ecc3190 | 2273 | } \ |
af12906f AJ |
2274 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \ |
2275 | Rc(ctx->opcode) != 0); \ | |
9a64fbe4 FB |
2276 | } |
2277 | ||
7c58044c JM |
2278 | #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \ |
2279 | _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \ | |
2280 | _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type); | |
9a64fbe4 | 2281 | |
7c58044c | 2282 | #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef BS |
2283 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type); \ |
2284 | \ | |
2285 | static void gen_f##name(DisasContext *ctx) \ | |
9a64fbe4 | 2286 | { \ |
76a66253 | 2287 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2288 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2289 | return; \ |
2290 | } \ | |
eb44b959 AJ |
2291 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2292 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2293 | gen_reset_fpstatus(); \ |
af12906f AJ |
2294 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
2295 | cpu_fpr[rB(ctx->opcode)]); \ | |
4ecc3190 | 2296 | if (isfloat) { \ |
af12906f | 2297 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
4ecc3190 | 2298 | } \ |
af12906f AJ |
2299 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2300 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2301 | } |
7c58044c JM |
2302 | #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \ |
2303 | _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2304 | _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2305 | |
7c58044c | 2306 | #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \ |
99e300ef BS |
2307 | GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type); \ |
2308 | \ | |
2309 | static void gen_f##name(DisasContext *ctx) \ | |
9a64fbe4 | 2310 | { \ |
76a66253 | 2311 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2312 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2313 | return; \ |
2314 | } \ | |
eb44b959 AJ |
2315 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2316 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2317 | gen_reset_fpstatus(); \ |
af12906f AJ |
2318 | gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], \ |
2319 | cpu_fpr[rC(ctx->opcode)]); \ | |
4ecc3190 | 2320 | if (isfloat) { \ |
af12906f | 2321 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); \ |
4ecc3190 | 2322 | } \ |
af12906f AJ |
2323 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ |
2324 | set_fprf, Rc(ctx->opcode) != 0); \ | |
9a64fbe4 | 2325 | } |
7c58044c JM |
2326 | #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \ |
2327 | _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \ | |
2328 | _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type); | |
9a64fbe4 | 2329 | |
7c58044c | 2330 | #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \ |
99e300ef BS |
2331 | GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type); \ |
2332 | \ | |
2333 | static void gen_f##name(DisasContext *ctx) \ | |
9a64fbe4 | 2334 | { \ |
76a66253 | 2335 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2336 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2337 | return; \ |
2338 | } \ | |
eb44b959 AJ |
2339 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2340 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2341 | gen_reset_fpstatus(); \ |
af12906f AJ |
2342 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2343 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ | |
2344 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2345 | } |
2346 | ||
7c58044c | 2347 | #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \ |
99e300ef BS |
2348 | GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type); \ |
2349 | \ | |
2350 | static void gen_f##name(DisasContext *ctx) \ | |
9a64fbe4 | 2351 | { \ |
76a66253 | 2352 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 2353 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
3cc62370 FB |
2354 | return; \ |
2355 | } \ | |
eb44b959 AJ |
2356 | /* NIP cannot be restored if the memory exception comes from an helper */ \ |
2357 | gen_update_nip(ctx, ctx->nip - 4); \ | |
7c58044c | 2358 | gen_reset_fpstatus(); \ |
af12906f AJ |
2359 | gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \ |
2360 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \ | |
2361 | set_fprf, Rc(ctx->opcode) != 0); \ | |
79aceca5 FB |
2362 | } |
2363 | ||
9a64fbe4 | 2364 | /* fadd - fadds */ |
7c58044c | 2365 | GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2366 | /* fdiv - fdivs */ |
7c58044c | 2367 | GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT); |
4ecc3190 | 2368 | /* fmul - fmuls */ |
7c58044c | 2369 | GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT); |
79aceca5 | 2370 | |
d7e4b87e | 2371 | /* fre */ |
7c58044c | 2372 | GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2373 | |
a750fc0b | 2374 | /* fres */ |
7c58044c | 2375 | GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES); |
79aceca5 | 2376 | |
a750fc0b | 2377 | /* frsqrte */ |
7c58044c JM |
2378 | GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE); |
2379 | ||
2380 | /* frsqrtes */ | |
99e300ef | 2381 | static void gen_frsqrtes(DisasContext *ctx) |
7c58044c | 2382 | { |
af12906f | 2383 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2384 | gen_exception(ctx, POWERPC_EXCP_FPU); |
af12906f AJ |
2385 | return; |
2386 | } | |
eb44b959 AJ |
2387 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2388 | gen_update_nip(ctx, ctx->nip - 4); | |
af12906f AJ |
2389 | gen_reset_fpstatus(); |
2390 | gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); | |
2391 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); | |
2392 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); | |
7c58044c | 2393 | } |
79aceca5 | 2394 | |
a750fc0b | 2395 | /* fsel */ |
7c58044c | 2396 | _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL); |
4ecc3190 | 2397 | /* fsub - fsubs */ |
7c58044c | 2398 | GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT); |
79aceca5 | 2399 | /* Optional: */ |
99e300ef | 2400 | |
54623277 | 2401 | /* fsqrt */ |
99e300ef | 2402 | static void gen_fsqrt(DisasContext *ctx) |
c7d344af | 2403 | { |
76a66253 | 2404 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2405 | gen_exception(ctx, POWERPC_EXCP_FPU); |
c7d344af FB |
2406 | return; |
2407 | } | |
eb44b959 AJ |
2408 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2409 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2410 | gen_reset_fpstatus(); |
af12906f AJ |
2411 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2412 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); | |
c7d344af | 2413 | } |
79aceca5 | 2414 | |
99e300ef | 2415 | static void gen_fsqrts(DisasContext *ctx) |
79aceca5 | 2416 | { |
76a66253 | 2417 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2418 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2419 | return; |
2420 | } | |
eb44b959 AJ |
2421 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2422 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2423 | gen_reset_fpstatus(); |
af12906f AJ |
2424 | gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2425 | gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rD(ctx->opcode)]); | |
2426 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0); | |
79aceca5 FB |
2427 | } |
2428 | ||
2429 | /*** Floating-Point multiply-and-add ***/ | |
4ecc3190 | 2430 | /* fmadd - fmadds */ |
7c58044c | 2431 | GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT); |
4ecc3190 | 2432 | /* fmsub - fmsubs */ |
7c58044c | 2433 | GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT); |
4ecc3190 | 2434 | /* fnmadd - fnmadds */ |
7c58044c | 2435 | GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT); |
4ecc3190 | 2436 | /* fnmsub - fnmsubs */ |
7c58044c | 2437 | GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT); |
79aceca5 FB |
2438 | |
2439 | /*** Floating-Point round & convert ***/ | |
2440 | /* fctiw */ | |
7c58044c | 2441 | GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2442 | /* fctiwz */ |
7c58044c | 2443 | GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT); |
79aceca5 | 2444 | /* frsp */ |
7c58044c | 2445 | GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT); |
426613db JM |
2446 | #if defined(TARGET_PPC64) |
2447 | /* fcfid */ | |
7c58044c | 2448 | GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B); |
426613db | 2449 | /* fctid */ |
7c58044c | 2450 | GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B); |
426613db | 2451 | /* fctidz */ |
7c58044c | 2452 | GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B); |
426613db | 2453 | #endif |
79aceca5 | 2454 | |
d7e4b87e | 2455 | /* frin */ |
7c58044c | 2456 | GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2457 | /* friz */ |
7c58044c | 2458 | GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2459 | /* frip */ |
7c58044c | 2460 | GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2461 | /* frim */ |
7c58044c | 2462 | GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT); |
d7e4b87e | 2463 | |
79aceca5 | 2464 | /*** Floating-Point compare ***/ |
99e300ef | 2465 | |
54623277 | 2466 | /* fcmpo */ |
99e300ef | 2467 | static void gen_fcmpo(DisasContext *ctx) |
79aceca5 | 2468 | { |
330c483b | 2469 | TCGv_i32 crf; |
76a66253 | 2470 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2471 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2472 | return; |
2473 | } | |
eb44b959 AJ |
2474 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2475 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2476 | gen_reset_fpstatus(); |
9a819377 AJ |
2477 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2478 | gen_helper_fcmpo(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2479 | tcg_temp_free_i32(crf); |
af12906f | 2480 | gen_helper_float_check_status(); |
79aceca5 FB |
2481 | } |
2482 | ||
2483 | /* fcmpu */ | |
99e300ef | 2484 | static void gen_fcmpu(DisasContext *ctx) |
79aceca5 | 2485 | { |
330c483b | 2486 | TCGv_i32 crf; |
76a66253 | 2487 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2488 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2489 | return; |
2490 | } | |
eb44b959 AJ |
2491 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2492 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2493 | gen_reset_fpstatus(); |
9a819377 AJ |
2494 | crf = tcg_const_i32(crfD(ctx->opcode)); |
2495 | gen_helper_fcmpu(cpu_fpr[rA(ctx->opcode)], cpu_fpr[rB(ctx->opcode)], crf); | |
330c483b | 2496 | tcg_temp_free_i32(crf); |
af12906f | 2497 | gen_helper_float_check_status(); |
79aceca5 FB |
2498 | } |
2499 | ||
9a64fbe4 FB |
2500 | /*** Floating-point move ***/ |
2501 | /* fabs */ | |
7c58044c JM |
2502 | /* XXX: beware that fabs never checks for NaNs nor update FPSCR */ |
2503 | GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT); | |
9a64fbe4 FB |
2504 | |
2505 | /* fmr - fmr. */ | |
7c58044c | 2506 | /* XXX: beware that fmr never checks for NaNs nor update FPSCR */ |
99e300ef | 2507 | static void gen_fmr(DisasContext *ctx) |
9a64fbe4 | 2508 | { |
76a66253 | 2509 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2510 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2511 | return; |
2512 | } | |
af12906f AJ |
2513 | tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); |
2514 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
9a64fbe4 FB |
2515 | } |
2516 | ||
2517 | /* fnabs */ | |
7c58044c JM |
2518 | /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */ |
2519 | GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT); | |
9a64fbe4 | 2520 | /* fneg */ |
7c58044c JM |
2521 | /* XXX: beware that fneg never checks for NaNs nor update FPSCR */ |
2522 | GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); | |
9a64fbe4 | 2523 | |
79aceca5 | 2524 | /*** Floating-Point status & ctrl register ***/ |
99e300ef | 2525 | |
54623277 | 2526 | /* mcrfs */ |
99e300ef | 2527 | static void gen_mcrfs(DisasContext *ctx) |
79aceca5 | 2528 | { |
7c58044c JM |
2529 | int bfa; |
2530 | ||
76a66253 | 2531 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2532 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2533 | return; |
2534 | } | |
7c58044c | 2535 | bfa = 4 * (7 - crfS(ctx->opcode)); |
e1571908 AJ |
2536 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); |
2537 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); | |
af12906f | 2538 | tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); |
79aceca5 FB |
2539 | } |
2540 | ||
2541 | /* mffs */ | |
99e300ef | 2542 | static void gen_mffs(DisasContext *ctx) |
79aceca5 | 2543 | { |
76a66253 | 2544 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2545 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2546 | return; |
2547 | } | |
7c58044c | 2548 | gen_reset_fpstatus(); |
af12906f AJ |
2549 | tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); |
2550 | gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); | |
79aceca5 FB |
2551 | } |
2552 | ||
2553 | /* mtfsb0 */ | |
99e300ef | 2554 | static void gen_mtfsb0(DisasContext *ctx) |
79aceca5 | 2555 | { |
fb0eaffc | 2556 | uint8_t crb; |
3b46e624 | 2557 | |
76a66253 | 2558 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2559 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2560 | return; |
2561 | } | |
6e35d524 | 2562 | crb = 31 - crbD(ctx->opcode); |
7c58044c | 2563 | gen_reset_fpstatus(); |
6e35d524 | 2564 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) { |
eb44b959 AJ |
2565 | TCGv_i32 t0; |
2566 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2567 | gen_update_nip(ctx, ctx->nip - 4); | |
2568 | t0 = tcg_const_i32(crb); | |
6e35d524 AJ |
2569 | gen_helper_fpscr_clrbit(t0); |
2570 | tcg_temp_free_i32(t0); | |
2571 | } | |
7c58044c | 2572 | if (unlikely(Rc(ctx->opcode) != 0)) { |
e1571908 | 2573 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
7c58044c | 2574 | } |
79aceca5 FB |
2575 | } |
2576 | ||
2577 | /* mtfsb1 */ | |
99e300ef | 2578 | static void gen_mtfsb1(DisasContext *ctx) |
79aceca5 | 2579 | { |
fb0eaffc | 2580 | uint8_t crb; |
3b46e624 | 2581 | |
76a66253 | 2582 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2583 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2584 | return; |
2585 | } | |
6e35d524 | 2586 | crb = 31 - crbD(ctx->opcode); |
7c58044c JM |
2587 | gen_reset_fpstatus(); |
2588 | /* XXX: we pretend we can only do IEEE floating-point computations */ | |
af12906f | 2589 | if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) { |
eb44b959 AJ |
2590 | TCGv_i32 t0; |
2591 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2592 | gen_update_nip(ctx, ctx->nip - 4); | |
2593 | t0 = tcg_const_i32(crb); | |
af12906f | 2594 | gen_helper_fpscr_setbit(t0); |
0f2f39c2 | 2595 | tcg_temp_free_i32(t0); |
af12906f | 2596 | } |
7c58044c | 2597 | if (unlikely(Rc(ctx->opcode) != 0)) { |
e1571908 | 2598 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
7c58044c JM |
2599 | } |
2600 | /* We can raise a differed exception */ | |
af12906f | 2601 | gen_helper_float_check_status(); |
79aceca5 FB |
2602 | } |
2603 | ||
2604 | /* mtfsf */ | |
99e300ef | 2605 | static void gen_mtfsf(DisasContext *ctx) |
79aceca5 | 2606 | { |
0f2f39c2 | 2607 | TCGv_i32 t0; |
4911012d | 2608 | int L = ctx->opcode & 0x02000000; |
af12906f | 2609 | |
76a66253 | 2610 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2611 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2612 | return; |
2613 | } | |
eb44b959 AJ |
2614 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2615 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2616 | gen_reset_fpstatus(); |
4911012d BS |
2617 | if (L) |
2618 | t0 = tcg_const_i32(0xff); | |
2619 | else | |
2620 | t0 = tcg_const_i32(FM(ctx->opcode)); | |
af12906f | 2621 | gen_helper_store_fpscr(cpu_fpr[rB(ctx->opcode)], t0); |
0f2f39c2 | 2622 | tcg_temp_free_i32(t0); |
7c58044c | 2623 | if (unlikely(Rc(ctx->opcode) != 0)) { |
e1571908 | 2624 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
7c58044c JM |
2625 | } |
2626 | /* We can raise a differed exception */ | |
af12906f | 2627 | gen_helper_float_check_status(); |
79aceca5 FB |
2628 | } |
2629 | ||
2630 | /* mtfsfi */ | |
99e300ef | 2631 | static void gen_mtfsfi(DisasContext *ctx) |
79aceca5 | 2632 | { |
7c58044c | 2633 | int bf, sh; |
0f2f39c2 AJ |
2634 | TCGv_i64 t0; |
2635 | TCGv_i32 t1; | |
7c58044c | 2636 | |
76a66253 | 2637 | if (unlikely(!ctx->fpu_enabled)) { |
e06fcd75 | 2638 | gen_exception(ctx, POWERPC_EXCP_FPU); |
3cc62370 FB |
2639 | return; |
2640 | } | |
7c58044c JM |
2641 | bf = crbD(ctx->opcode) >> 2; |
2642 | sh = 7 - bf; | |
eb44b959 AJ |
2643 | /* NIP cannot be restored if the memory exception comes from an helper */ |
2644 | gen_update_nip(ctx, ctx->nip - 4); | |
7c58044c | 2645 | gen_reset_fpstatus(); |
0f2f39c2 | 2646 | t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh)); |
af12906f AJ |
2647 | t1 = tcg_const_i32(1 << sh); |
2648 | gen_helper_store_fpscr(t0, t1); | |
0f2f39c2 AJ |
2649 | tcg_temp_free_i64(t0); |
2650 | tcg_temp_free_i32(t1); | |
7c58044c | 2651 | if (unlikely(Rc(ctx->opcode) != 0)) { |
e1571908 | 2652 | tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); |
7c58044c JM |
2653 | } |
2654 | /* We can raise a differed exception */ | |
af12906f | 2655 | gen_helper_float_check_status(); |
79aceca5 FB |
2656 | } |
2657 | ||
76a66253 JM |
2658 | /*** Addressing modes ***/ |
2659 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
76db3ba4 | 2660 | static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl) |
76a66253 JM |
2661 | { |
2662 | target_long simm = SIMM(ctx->opcode); | |
2663 | ||
be147d08 | 2664 | simm &= ~maskl; |
76db3ba4 AJ |
2665 | if (rA(ctx->opcode) == 0) { |
2666 | #if defined(TARGET_PPC64) | |
2667 | if (!ctx->sf_mode) { | |
2668 | tcg_gen_movi_tl(EA, (uint32_t)simm); | |
2669 | } else | |
2670 | #endif | |
e2be8d8d | 2671 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2672 | } else if (likely(simm != 0)) { |
e2be8d8d | 2673 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
76db3ba4 AJ |
2674 | #if defined(TARGET_PPC64) |
2675 | if (!ctx->sf_mode) { | |
2676 | tcg_gen_ext32u_tl(EA, EA); | |
2677 | } | |
2678 | #endif | |
2679 | } else { | |
2680 | #if defined(TARGET_PPC64) | |
2681 | if (!ctx->sf_mode) { | |
2682 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2683 | } else | |
2684 | #endif | |
e2be8d8d | 2685 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 | 2686 | } |
76a66253 JM |
2687 | } |
2688 | ||
76db3ba4 | 2689 | static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA) |
76a66253 | 2690 | { |
76db3ba4 AJ |
2691 | if (rA(ctx->opcode) == 0) { |
2692 | #if defined(TARGET_PPC64) | |
2693 | if (!ctx->sf_mode) { | |
2694 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2695 | } else | |
2696 | #endif | |
e2be8d8d | 2697 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 | 2698 | } else { |
e2be8d8d | 2699 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76db3ba4 AJ |
2700 | #if defined(TARGET_PPC64) |
2701 | if (!ctx->sf_mode) { | |
2702 | tcg_gen_ext32u_tl(EA, EA); | |
2703 | } | |
2704 | #endif | |
2705 | } | |
76a66253 JM |
2706 | } |
2707 | ||
76db3ba4 | 2708 | static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA) |
76a66253 | 2709 | { |
76db3ba4 | 2710 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2711 | tcg_gen_movi_tl(EA, 0); |
76db3ba4 AJ |
2712 | } else { |
2713 | #if defined(TARGET_PPC64) | |
2714 | if (!ctx->sf_mode) { | |
2715 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2716 | } else | |
2717 | #endif | |
2718 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2719 | } | |
2720 | } | |
2721 | ||
2722 | static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val) | |
2723 | { | |
2724 | tcg_gen_addi_tl(ret, arg1, val); | |
2725 | #if defined(TARGET_PPC64) | |
2726 | if (!ctx->sf_mode) { | |
2727 | tcg_gen_ext32u_tl(ret, ret); | |
2728 | } | |
2729 | #endif | |
76a66253 JM |
2730 | } |
2731 | ||
cf360a32 AJ |
2732 | static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask) |
2733 | { | |
2734 | int l1 = gen_new_label(); | |
2735 | TCGv t0 = tcg_temp_new(); | |
2736 | TCGv_i32 t1, t2; | |
2737 | /* NIP cannot be restored if the memory exception comes from an helper */ | |
2738 | gen_update_nip(ctx, ctx->nip - 4); | |
2739 | tcg_gen_andi_tl(t0, EA, mask); | |
2740 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2741 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
2742 | t2 = tcg_const_i32(0); | |
2743 | gen_helper_raise_exception_err(t1, t2); | |
2744 | tcg_temp_free_i32(t1); | |
2745 | tcg_temp_free_i32(t2); | |
2746 | gen_set_label(l1); | |
2747 | tcg_temp_free(t0); | |
2748 | } | |
2749 | ||
7863667f | 2750 | /*** Integer load ***/ |
76db3ba4 AJ |
2751 | static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
2752 | { | |
2753 | tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); | |
2754 | } | |
2755 | ||
2756 | static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2757 | { | |
2758 | tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx); | |
2759 | } | |
2760 | ||
2761 | static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
2762 | { | |
2763 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); | |
2764 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2765 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2766 | } |
b61f2753 AJ |
2767 | } |
2768 | ||
76db3ba4 | 2769 | static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2770 | { |
76db3ba4 | 2771 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2772 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
fa3966a3 | 2773 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 2774 | tcg_gen_ext16s_tl(arg1, arg1); |
76db3ba4 AJ |
2775 | } else { |
2776 | tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx); | |
2777 | } | |
b61f2753 AJ |
2778 | } |
2779 | ||
76db3ba4 | 2780 | static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2781 | { |
76db3ba4 AJ |
2782 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
2783 | if (unlikely(ctx->le_mode)) { | |
fa3966a3 | 2784 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 2785 | } |
b61f2753 AJ |
2786 | } |
2787 | ||
76db3ba4 AJ |
2788 | #if defined(TARGET_PPC64) |
2789 | static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) | |
b61f2753 | 2790 | { |
a457e7ee | 2791 | if (unlikely(ctx->le_mode)) { |
76db3ba4 | 2792 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
fa3966a3 AJ |
2793 | tcg_gen_bswap32_tl(arg1, arg1); |
2794 | tcg_gen_ext32s_tl(arg1, arg1); | |
b61f2753 | 2795 | } else |
76db3ba4 | 2796 | tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); |
b61f2753 | 2797 | } |
76db3ba4 | 2798 | #endif |
b61f2753 | 2799 | |
76db3ba4 | 2800 | static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2801 | { |
76db3ba4 AJ |
2802 | tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx); |
2803 | if (unlikely(ctx->le_mode)) { | |
66896cb8 | 2804 | tcg_gen_bswap64_i64(arg1, arg1); |
76db3ba4 | 2805 | } |
b61f2753 AJ |
2806 | } |
2807 | ||
76db3ba4 | 2808 | static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2809 | { |
76db3ba4 | 2810 | tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2811 | } |
2812 | ||
76db3ba4 | 2813 | static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2814 | { |
76db3ba4 | 2815 | if (unlikely(ctx->le_mode)) { |
76db3ba4 AJ |
2816 | TCGv t0 = tcg_temp_new(); |
2817 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 2818 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
2819 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
2820 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2821 | } else { |
2822 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
2823 | } | |
b61f2753 AJ |
2824 | } |
2825 | ||
76db3ba4 | 2826 | static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 2827 | { |
76db3ba4 | 2828 | if (unlikely(ctx->le_mode)) { |
fa3966a3 AJ |
2829 | TCGv t0 = tcg_temp_new(); |
2830 | tcg_gen_ext32u_tl(t0, arg1); | |
2831 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
2832 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
2833 | tcg_temp_free(t0); | |
76db3ba4 AJ |
2834 | } else { |
2835 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
2836 | } | |
b61f2753 AJ |
2837 | } |
2838 | ||
76db3ba4 | 2839 | static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
b61f2753 | 2840 | { |
76db3ba4 | 2841 | if (unlikely(ctx->le_mode)) { |
a7812ae4 | 2842 | TCGv_i64 t0 = tcg_temp_new_i64(); |
66896cb8 | 2843 | tcg_gen_bswap64_i64(t0, arg1); |
76db3ba4 | 2844 | tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx); |
a7812ae4 | 2845 | tcg_temp_free_i64(t0); |
b61f2753 | 2846 | } else |
76db3ba4 | 2847 | tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx); |
b61f2753 AJ |
2848 | } |
2849 | ||
0c8aacd4 | 2850 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef BS |
2851 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type); \ |
2852 | \ | |
2853 | static void glue(gen_, name)(DisasContext *ctx) \ | |
79aceca5 | 2854 | { \ |
76db3ba4 AJ |
2855 | TCGv EA; \ |
2856 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2857 | EA = tcg_temp_new(); \ | |
2858 | gen_addr_imm_index(ctx, EA, 0); \ | |
2859 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2860 | tcg_temp_free(EA); \ |
79aceca5 FB |
2861 | } |
2862 | ||
0c8aacd4 | 2863 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef BS |
2864 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type); \ |
2865 | \ | |
2866 | static void glue(gen_, name##u)(DisasContext *ctx) \ | |
79aceca5 | 2867 | { \ |
b61f2753 | 2868 | TCGv EA; \ |
76a66253 JM |
2869 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2870 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2871 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2872 | return; \ |
9a64fbe4 | 2873 | } \ |
76db3ba4 | 2874 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2875 | EA = tcg_temp_new(); \ |
9d53c753 | 2876 | if (type == PPC_64B) \ |
76db3ba4 | 2877 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2878 | else \ |
76db3ba4 AJ |
2879 | gen_addr_imm_index(ctx, EA, 0); \ |
2880 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2881 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2882 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2883 | } |
2884 | ||
0c8aacd4 | 2885 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef BS |
2886 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type); \ |
2887 | \ | |
2888 | static void glue(gen_, name##ux)(DisasContext *ctx) \ | |
79aceca5 | 2889 | { \ |
b61f2753 | 2890 | TCGv EA; \ |
76a66253 JM |
2891 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2892 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2893 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2894 | return; \ |
9a64fbe4 | 2895 | } \ |
76db3ba4 | 2896 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2897 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2898 | gen_addr_reg_index(ctx, EA); \ |
2899 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2900 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2901 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2902 | } |
2903 | ||
0c8aacd4 | 2904 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
99e300ef BS |
2905 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type); \ |
2906 | \ | |
2907 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 2908 | { \ |
76db3ba4 AJ |
2909 | TCGv EA; \ |
2910 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2911 | EA = tcg_temp_new(); \ | |
2912 | gen_addr_reg_index(ctx, EA); \ | |
2913 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2914 | tcg_temp_free(EA); \ |
79aceca5 FB |
2915 | } |
2916 | ||
0c8aacd4 AJ |
2917 | #define GEN_LDS(name, ldop, op, type) \ |
2918 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2919 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2920 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2921 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2922 | |
2923 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2924 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2925 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2926 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2927 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2928 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2929 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2930 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2931 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2932 | /* lwaux */ |
0c8aacd4 | 2933 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2934 | /* lwax */ |
0c8aacd4 | 2935 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2936 | /* ldux */ |
0c8aacd4 | 2937 | GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2938 | /* ldx */ |
0c8aacd4 | 2939 | GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B); |
99e300ef BS |
2940 | |
2941 | static void gen_ld(DisasContext *ctx) | |
d9bce9d9 | 2942 | { |
b61f2753 | 2943 | TCGv EA; |
d9bce9d9 JM |
2944 | if (Rc(ctx->opcode)) { |
2945 | if (unlikely(rA(ctx->opcode) == 0 || | |
2946 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2947 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2948 | return; |
2949 | } | |
2950 | } | |
76db3ba4 | 2951 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2952 | EA = tcg_temp_new(); |
76db3ba4 | 2953 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2954 | if (ctx->opcode & 0x02) { |
2955 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2956 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2957 | } else { |
2958 | /* ld - ldu */ | |
76db3ba4 | 2959 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2960 | } |
d9bce9d9 | 2961 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2962 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2963 | tcg_temp_free(EA); | |
d9bce9d9 | 2964 | } |
99e300ef | 2965 | |
54623277 | 2966 | /* lq */ |
99e300ef | 2967 | static void gen_lq(DisasContext *ctx) |
be147d08 JM |
2968 | { |
2969 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 2970 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2971 | #else |
2972 | int ra, rd; | |
b61f2753 | 2973 | TCGv EA; |
be147d08 JM |
2974 | |
2975 | /* Restore CPU state */ | |
76db3ba4 | 2976 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 2977 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2978 | return; |
2979 | } | |
2980 | ra = rA(ctx->opcode); | |
2981 | rd = rD(ctx->opcode); | |
2982 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2983 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2984 | return; |
2985 | } | |
76db3ba4 | 2986 | if (unlikely(ctx->le_mode)) { |
be147d08 | 2987 | /* Little-endian mode is not handled */ |
e06fcd75 | 2988 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
2989 | return; |
2990 | } | |
76db3ba4 | 2991 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2992 | EA = tcg_temp_new(); |
76db3ba4 AJ |
2993 | gen_addr_imm_index(ctx, EA, 0x0F); |
2994 | gen_qemu_ld64(ctx, cpu_gpr[rd], EA); | |
2995 | gen_addr_add(ctx, EA, EA, 8); | |
2996 | gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA); | |
b61f2753 | 2997 | tcg_temp_free(EA); |
be147d08 JM |
2998 | #endif |
2999 | } | |
d9bce9d9 | 3000 | #endif |
79aceca5 FB |
3001 | |
3002 | /*** Integer store ***/ | |
0c8aacd4 | 3003 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef BS |
3004 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type); \ |
3005 | \ | |
3006 | static void glue(gen_, name)(DisasContext *ctx) \ | |
79aceca5 | 3007 | { \ |
76db3ba4 AJ |
3008 | TCGv EA; \ |
3009 | gen_set_access_type(ctx, ACCESS_INT); \ | |
3010 | EA = tcg_temp_new(); \ | |
3011 | gen_addr_imm_index(ctx, EA, 0); \ | |
3012 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 3013 | tcg_temp_free(EA); \ |
79aceca5 FB |
3014 | } |
3015 | ||
0c8aacd4 | 3016 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef BS |
3017 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type); \ |
3018 | \ | |
3019 | static void glue(gen_, stop##u)(DisasContext *ctx) \ | |
79aceca5 | 3020 | { \ |
b61f2753 | 3021 | TCGv EA; \ |
76a66253 | 3022 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3023 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3024 | return; \ |
9a64fbe4 | 3025 | } \ |
76db3ba4 | 3026 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 3027 | EA = tcg_temp_new(); \ |
9d53c753 | 3028 | if (type == PPC_64B) \ |
76db3ba4 | 3029 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 3030 | else \ |
76db3ba4 AJ |
3031 | gen_addr_imm_index(ctx, EA, 0); \ |
3032 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
3033 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3034 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3035 | } |
3036 | ||
0c8aacd4 | 3037 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef BS |
3038 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type); \ |
3039 | \ | |
3040 | static void glue(gen_, name##ux)(DisasContext *ctx) \ | |
79aceca5 | 3041 | { \ |
b61f2753 | 3042 | TCGv EA; \ |
76a66253 | 3043 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3044 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3045 | return; \ |
9a64fbe4 | 3046 | } \ |
76db3ba4 | 3047 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 3048 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3049 | gen_addr_reg_index(ctx, EA); \ |
3050 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
3051 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3052 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3053 | } |
3054 | ||
0c8aacd4 | 3055 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
99e300ef BS |
3056 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type); \ |
3057 | \ | |
3058 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 3059 | { \ |
76db3ba4 AJ |
3060 | TCGv EA; \ |
3061 | gen_set_access_type(ctx, ACCESS_INT); \ | |
3062 | EA = tcg_temp_new(); \ | |
3063 | gen_addr_reg_index(ctx, EA); \ | |
3064 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 3065 | tcg_temp_free(EA); \ |
79aceca5 FB |
3066 | } |
3067 | ||
0c8aacd4 AJ |
3068 | #define GEN_STS(name, stop, op, type) \ |
3069 | GEN_ST(name, stop, op | 0x20, type); \ | |
3070 | GEN_STU(name, stop, op | 0x21, type); \ | |
3071 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
3072 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
3073 | |
3074 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 3075 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 3076 | /* sth sthu sthux sthx */ |
0c8aacd4 | 3077 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 3078 | /* stw stwu stwux stwx */ |
0c8aacd4 | 3079 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 3080 | #if defined(TARGET_PPC64) |
0c8aacd4 AJ |
3081 | GEN_STUX(std, st64, 0x15, 0x05, PPC_64B); |
3082 | GEN_STX(std, st64, 0x15, 0x04, PPC_64B); | |
99e300ef BS |
3083 | |
3084 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 3085 | { |
be147d08 | 3086 | int rs; |
b61f2753 | 3087 | TCGv EA; |
be147d08 JM |
3088 | |
3089 | rs = rS(ctx->opcode); | |
3090 | if ((ctx->opcode & 0x3) == 0x2) { | |
3091 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3092 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3093 | #else |
3094 | /* stq */ | |
76db3ba4 | 3095 | if (unlikely(ctx->mem_idx == 0)) { |
e06fcd75 | 3096 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3097 | return; |
3098 | } | |
3099 | if (unlikely(rs & 1)) { | |
e06fcd75 | 3100 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
3101 | return; |
3102 | } | |
76db3ba4 | 3103 | if (unlikely(ctx->le_mode)) { |
be147d08 | 3104 | /* Little-endian mode is not handled */ |
e06fcd75 | 3105 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE); |
be147d08 JM |
3106 | return; |
3107 | } | |
76db3ba4 | 3108 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 3109 | EA = tcg_temp_new(); |
76db3ba4 AJ |
3110 | gen_addr_imm_index(ctx, EA, 0x03); |
3111 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
3112 | gen_addr_add(ctx, EA, EA, 8); | |
3113 | gen_qemu_st64(ctx, cpu_gpr[rs+1], EA); | |
b61f2753 | 3114 | tcg_temp_free(EA); |
be147d08 JM |
3115 | #endif |
3116 | } else { | |
3117 | /* std / stdu */ | |
3118 | if (Rc(ctx->opcode)) { | |
3119 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 3120 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
3121 | return; |
3122 | } | |
3123 | } | |
76db3ba4 | 3124 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 3125 | EA = tcg_temp_new(); |
76db3ba4 AJ |
3126 | gen_addr_imm_index(ctx, EA, 0x03); |
3127 | gen_qemu_st64(ctx, cpu_gpr[rs], EA); | |
be147d08 | 3128 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
3129 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
3130 | tcg_temp_free(EA); | |
d9bce9d9 | 3131 | } |
d9bce9d9 JM |
3132 | } |
3133 | #endif | |
79aceca5 FB |
3134 | /*** Integer load and store with byte reverse ***/ |
3135 | /* lhbrx */ | |
76db3ba4 | 3136 | static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3137 | { |
76db3ba4 AJ |
3138 | tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx); |
3139 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 3140 | tcg_gen_bswap16_tl(arg1, arg1); |
76db3ba4 | 3141 | } |
b61f2753 | 3142 | } |
0c8aacd4 | 3143 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 3144 | |
79aceca5 | 3145 | /* lwbrx */ |
76db3ba4 | 3146 | static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3147 | { |
76db3ba4 AJ |
3148 | tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx); |
3149 | if (likely(!ctx->le_mode)) { | |
fa3966a3 | 3150 | tcg_gen_bswap32_tl(arg1, arg1); |
76db3ba4 | 3151 | } |
b61f2753 | 3152 | } |
0c8aacd4 | 3153 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 3154 | |
79aceca5 | 3155 | /* sthbrx */ |
76db3ba4 | 3156 | static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3157 | { |
76db3ba4 | 3158 | if (likely(!ctx->le_mode)) { |
76db3ba4 AJ |
3159 | TCGv t0 = tcg_temp_new(); |
3160 | tcg_gen_ext16u_tl(t0, arg1); | |
fa3966a3 | 3161 | tcg_gen_bswap16_tl(t0, t0); |
76db3ba4 AJ |
3162 | tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx); |
3163 | tcg_temp_free(t0); | |
76db3ba4 AJ |
3164 | } else { |
3165 | tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx); | |
3166 | } | |
b61f2753 | 3167 | } |
0c8aacd4 | 3168 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
b61f2753 | 3169 | |
79aceca5 | 3170 | /* stwbrx */ |
76db3ba4 | 3171 | static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2) |
b61f2753 | 3172 | { |
76db3ba4 | 3173 | if (likely(!ctx->le_mode)) { |
fa3966a3 AJ |
3174 | TCGv t0 = tcg_temp_new(); |
3175 | tcg_gen_ext32u_tl(t0, arg1); | |
3176 | tcg_gen_bswap32_tl(t0, t0); | |
76db3ba4 AJ |
3177 | tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx); |
3178 | tcg_temp_free(t0); | |
76db3ba4 AJ |
3179 | } else { |
3180 | tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx); | |
3181 | } | |
b61f2753 | 3182 | } |
0c8aacd4 | 3183 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 FB |
3184 | |
3185 | /*** Integer load and store multiple ***/ | |
99e300ef | 3186 | |
54623277 | 3187 | /* lmw */ |
99e300ef | 3188 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 3189 | { |
76db3ba4 AJ |
3190 | TCGv t0; |
3191 | TCGv_i32 t1; | |
3192 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3193 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3194 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3195 | t0 = tcg_temp_new(); |
3196 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3197 | gen_addr_imm_index(ctx, t0, 0); | |
ff4a62cd AJ |
3198 | gen_helper_lmw(t0, t1); |
3199 | tcg_temp_free(t0); | |
3200 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3201 | } |
3202 | ||
3203 | /* stmw */ | |
99e300ef | 3204 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 3205 | { |
76db3ba4 AJ |
3206 | TCGv t0; |
3207 | TCGv_i32 t1; | |
3208 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3209 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3210 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3211 | t0 = tcg_temp_new(); |
3212 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
3213 | gen_addr_imm_index(ctx, t0, 0); | |
ff4a62cd AJ |
3214 | gen_helper_stmw(t0, t1); |
3215 | tcg_temp_free(t0); | |
3216 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3217 | } |
3218 | ||
3219 | /*** Integer load and store strings ***/ | |
54623277 | 3220 | |
79aceca5 | 3221 | /* lswi */ |
3fc6c082 | 3222 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
3223 | * rA is in the range of registers to be loaded. |
3224 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
3225 | * For now, I'll follow the spec... | |
3226 | */ | |
99e300ef | 3227 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 3228 | { |
dfbc799d AJ |
3229 | TCGv t0; |
3230 | TCGv_i32 t1, t2; | |
79aceca5 FB |
3231 | int nb = NB(ctx->opcode); |
3232 | int start = rD(ctx->opcode); | |
9a64fbe4 | 3233 | int ra = rA(ctx->opcode); |
79aceca5 FB |
3234 | int nr; |
3235 | ||
3236 | if (nb == 0) | |
3237 | nb = 32; | |
3238 | nr = nb / 4; | |
76a66253 JM |
3239 | if (unlikely(((start + nr) > 32 && |
3240 | start <= ra && (start + nr - 32) > ra) || | |
3241 | ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { | |
e06fcd75 | 3242 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 3243 | return; |
297d8e62 | 3244 | } |
76db3ba4 | 3245 | gen_set_access_type(ctx, ACCESS_INT); |
8dd4983c | 3246 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3247 | gen_update_nip(ctx, ctx->nip - 4); |
dfbc799d | 3248 | t0 = tcg_temp_new(); |
76db3ba4 | 3249 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
3250 | t1 = tcg_const_i32(nb); |
3251 | t2 = tcg_const_i32(start); | |
3252 | gen_helper_lsw(t0, t1, t2); | |
3253 | tcg_temp_free(t0); | |
3254 | tcg_temp_free_i32(t1); | |
3255 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3256 | } |
3257 | ||
3258 | /* lswx */ | |
99e300ef | 3259 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 3260 | { |
76db3ba4 AJ |
3261 | TCGv t0; |
3262 | TCGv_i32 t1, t2, t3; | |
3263 | gen_set_access_type(ctx, ACCESS_INT); | |
76a66253 | 3264 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3265 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3266 | t0 = tcg_temp_new(); |
3267 | gen_addr_reg_index(ctx, t0); | |
3268 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
3269 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
3270 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
dfbc799d AJ |
3271 | gen_helper_lswx(t0, t1, t2, t3); |
3272 | tcg_temp_free(t0); | |
3273 | tcg_temp_free_i32(t1); | |
3274 | tcg_temp_free_i32(t2); | |
3275 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
3276 | } |
3277 | ||
3278 | /* stswi */ | |
99e300ef | 3279 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 3280 | { |
76db3ba4 AJ |
3281 | TCGv t0; |
3282 | TCGv_i32 t1, t2; | |
4b3686fa | 3283 | int nb = NB(ctx->opcode); |
76db3ba4 | 3284 | gen_set_access_type(ctx, ACCESS_INT); |
76a66253 | 3285 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 3286 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3287 | t0 = tcg_temp_new(); |
3288 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
3289 | if (nb == 0) |
3290 | nb = 32; | |
dfbc799d | 3291 | t1 = tcg_const_i32(nb); |
76db3ba4 | 3292 | t2 = tcg_const_i32(rS(ctx->opcode)); |
dfbc799d AJ |
3293 | gen_helper_stsw(t0, t1, t2); |
3294 | tcg_temp_free(t0); | |
3295 | tcg_temp_free_i32(t1); | |
3296 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3297 | } |
3298 | ||
3299 | /* stswx */ | |
99e300ef | 3300 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 3301 | { |
76db3ba4 AJ |
3302 | TCGv t0; |
3303 | TCGv_i32 t1, t2; | |
3304 | gen_set_access_type(ctx, ACCESS_INT); | |
8dd4983c | 3305 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5fafdf24 | 3306 | gen_update_nip(ctx, ctx->nip - 4); |
76db3ba4 AJ |
3307 | t0 = tcg_temp_new(); |
3308 | gen_addr_reg_index(ctx, t0); | |
3309 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3310 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3311 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3312 | t2 = tcg_const_i32(rS(ctx->opcode)); |
dfbc799d AJ |
3313 | gen_helper_stsw(t0, t1, t2); |
3314 | tcg_temp_free(t0); | |
3315 | tcg_temp_free_i32(t1); | |
3316 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3317 | } |
3318 | ||
3319 | /*** Memory synchronisation ***/ | |
3320 | /* eieio */ | |
99e300ef | 3321 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3322 | { |
79aceca5 FB |
3323 | } |
3324 | ||
3325 | /* isync */ | |
99e300ef | 3326 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3327 | { |
e06fcd75 | 3328 | gen_stop_exception(ctx); |
79aceca5 FB |
3329 | } |
3330 | ||
111bfab3 | 3331 | /* lwarx */ |
99e300ef | 3332 | static void gen_lwarx(DisasContext *ctx) |
79aceca5 | 3333 | { |
76db3ba4 AJ |
3334 | TCGv t0; |
3335 | gen_set_access_type(ctx, ACCESS_RES); | |
3336 | t0 = tcg_temp_local_new(); | |
3337 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3338 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 3339 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
cf360a32 AJ |
3340 | tcg_gen_mov_tl(cpu_reserve, t0); |
3341 | tcg_temp_free(t0); | |
79aceca5 FB |
3342 | } |
3343 | ||
3344 | /* stwcx. */ | |
e8eaa2c0 | 3345 | static void gen_stwcx_(DisasContext *ctx) |
79aceca5 | 3346 | { |
76db3ba4 AJ |
3347 | int l1; |
3348 | TCGv t0; | |
3349 | gen_set_access_type(ctx, ACCESS_RES); | |
3350 | t0 = tcg_temp_local_new(); | |
3351 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3352 | gen_check_align(ctx, t0, 0x03); |
cf360a32 AJ |
3353 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); |
3354 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
3355 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
76db3ba4 | 3356 | l1 = gen_new_label(); |
cf360a32 AJ |
3357 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
3358 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
76db3ba4 | 3359 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
cf360a32 AJ |
3360 | gen_set_label(l1); |
3361 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3362 | tcg_temp_free(t0); | |
79aceca5 FB |
3363 | } |
3364 | ||
426613db | 3365 | #if defined(TARGET_PPC64) |
426613db | 3366 | /* ldarx */ |
99e300ef | 3367 | static void gen_ldarx(DisasContext *ctx) |
426613db | 3368 | { |
76db3ba4 AJ |
3369 | TCGv t0; |
3370 | gen_set_access_type(ctx, ACCESS_RES); | |
3371 | t0 = tcg_temp_local_new(); | |
3372 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3373 | gen_check_align(ctx, t0, 0x07); |
76db3ba4 | 3374 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
cf360a32 AJ |
3375 | tcg_gen_mov_tl(cpu_reserve, t0); |
3376 | tcg_temp_free(t0); | |
426613db JM |
3377 | } |
3378 | ||
3379 | /* stdcx. */ | |
e8eaa2c0 | 3380 | static void gen_stdcx_(DisasContext *ctx) |
426613db | 3381 | { |
76db3ba4 AJ |
3382 | int l1; |
3383 | TCGv t0; | |
3384 | gen_set_access_type(ctx, ACCESS_RES); | |
3385 | t0 = tcg_temp_local_new(); | |
3386 | gen_addr_reg_index(ctx, t0); | |
cf360a32 | 3387 | gen_check_align(ctx, t0, 0x07); |
cf360a32 AJ |
3388 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); |
3389 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
3390 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
76db3ba4 | 3391 | l1 = gen_new_label(); |
cf360a32 AJ |
3392 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
3393 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
76db3ba4 | 3394 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0); |
cf360a32 AJ |
3395 | gen_set_label(l1); |
3396 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3397 | tcg_temp_free(t0); | |
426613db JM |
3398 | } |
3399 | #endif /* defined(TARGET_PPC64) */ | |
3400 | ||
79aceca5 | 3401 | /* sync */ |
99e300ef | 3402 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3403 | { |
79aceca5 FB |
3404 | } |
3405 | ||
0db1b20e | 3406 | /* wait */ |
99e300ef | 3407 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3408 | { |
931ff272 AJ |
3409 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3410 | tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, halted)); | |
3411 | tcg_temp_free_i32(t0); | |
0db1b20e | 3412 | /* Stop translation, as the CPU is supposed to sleep from now */ |
e06fcd75 | 3413 | gen_exception_err(ctx, EXCP_HLT, 1); |
0db1b20e JM |
3414 | } |
3415 | ||
79aceca5 | 3416 | /*** Floating-point load ***/ |
a0d7d5a7 | 3417 | #define GEN_LDF(name, ldop, opc, type) \ |
99e300ef BS |
3418 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type); \ |
3419 | \ | |
3420 | static void glue(gen_, name)(DisasContext *ctx) \ | |
79aceca5 | 3421 | { \ |
a0d7d5a7 | 3422 | TCGv EA; \ |
76a66253 | 3423 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3424 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3425 | return; \ |
3426 | } \ | |
76db3ba4 | 3427 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3428 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3429 | gen_addr_imm_index(ctx, EA, 0); \ |
3430 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3431 | tcg_temp_free(EA); \ |
79aceca5 FB |
3432 | } |
3433 | ||
a0d7d5a7 | 3434 | #define GEN_LDUF(name, ldop, opc, type) \ |
99e300ef BS |
3435 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type); \ |
3436 | \ | |
3437 | static void glue(gen_, name##u)(DisasContext *ctx) \ | |
79aceca5 | 3438 | { \ |
a0d7d5a7 | 3439 | TCGv EA; \ |
76a66253 | 3440 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3441 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3442 | return; \ |
3443 | } \ | |
76a66253 | 3444 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3445 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3446 | return; \ |
9a64fbe4 | 3447 | } \ |
76db3ba4 | 3448 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3449 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3450 | gen_addr_imm_index(ctx, EA, 0); \ |
3451 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3452 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3453 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3454 | } |
3455 | ||
a0d7d5a7 | 3456 | #define GEN_LDUXF(name, ldop, opc, type) \ |
99e300ef BS |
3457 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type); \ |
3458 | \ | |
3459 | static void glue(gen_, name##ux)(DisasContext *ctx) \ | |
79aceca5 | 3460 | { \ |
a0d7d5a7 | 3461 | TCGv EA; \ |
76a66253 | 3462 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3463 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3464 | return; \ |
3465 | } \ | |
76a66253 | 3466 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3467 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3468 | return; \ |
9a64fbe4 | 3469 | } \ |
76db3ba4 | 3470 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3471 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3472 | gen_addr_reg_index(ctx, EA); \ |
3473 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3474 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3475 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3476 | } |
3477 | ||
a0d7d5a7 | 3478 | #define GEN_LDXF(name, ldop, opc2, opc3, type) \ |
99e300ef BS |
3479 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type); \ |
3480 | \ | |
3481 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 3482 | { \ |
a0d7d5a7 | 3483 | TCGv EA; \ |
76a66253 | 3484 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3485 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3486 | return; \ |
3487 | } \ | |
76db3ba4 | 3488 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3489 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3490 | gen_addr_reg_index(ctx, EA); \ |
3491 | gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3492 | tcg_temp_free(EA); \ |
79aceca5 FB |
3493 | } |
3494 | ||
a0d7d5a7 AJ |
3495 | #define GEN_LDFS(name, ldop, op, type) \ |
3496 | GEN_LDF(name, ldop, op | 0x20, type); \ | |
3497 | GEN_LDUF(name, ldop, op | 0x21, type); \ | |
3498 | GEN_LDUXF(name, ldop, op | 0x01, type); \ | |
3499 | GEN_LDXF(name, ldop, 0x17, op | 0x00, type) | |
3500 | ||
76db3ba4 | 3501 | static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3502 | { |
3503 | TCGv t0 = tcg_temp_new(); | |
3504 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
76db3ba4 | 3505 | gen_qemu_ld32u(ctx, t0, arg2); |
a0d7d5a7 AJ |
3506 | tcg_gen_trunc_tl_i32(t1, t0); |
3507 | tcg_temp_free(t0); | |
3508 | gen_helper_float32_to_float64(arg1, t1); | |
3509 | tcg_temp_free_i32(t1); | |
3510 | } | |
79aceca5 | 3511 | |
a0d7d5a7 AJ |
3512 | /* lfd lfdu lfdux lfdx */ |
3513 | GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); | |
3514 | /* lfs lfsu lfsux lfsx */ | |
3515 | GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); | |
79aceca5 FB |
3516 | |
3517 | /*** Floating-point store ***/ | |
a0d7d5a7 | 3518 | #define GEN_STF(name, stop, opc, type) \ |
99e300ef BS |
3519 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type); \ |
3520 | \ | |
3521 | static void glue(gen_, name)(DisasContext *ctx) \ | |
79aceca5 | 3522 | { \ |
a0d7d5a7 | 3523 | TCGv EA; \ |
76a66253 | 3524 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3525 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3526 | return; \ |
3527 | } \ | |
76db3ba4 | 3528 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3529 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3530 | gen_addr_imm_index(ctx, EA, 0); \ |
3531 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3532 | tcg_temp_free(EA); \ |
79aceca5 FB |
3533 | } |
3534 | ||
a0d7d5a7 | 3535 | #define GEN_STUF(name, stop, opc, type) \ |
99e300ef BS |
3536 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type); \ |
3537 | \ | |
3538 | static void glue(gen_, name##u)(DisasContext *ctx) \ | |
79aceca5 | 3539 | { \ |
a0d7d5a7 | 3540 | TCGv EA; \ |
76a66253 | 3541 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3542 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3543 | return; \ |
3544 | } \ | |
76a66253 | 3545 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3546 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3547 | return; \ |
9a64fbe4 | 3548 | } \ |
76db3ba4 | 3549 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3550 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3551 | gen_addr_imm_index(ctx, EA, 0); \ |
3552 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3553 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3554 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3555 | } |
3556 | ||
a0d7d5a7 | 3557 | #define GEN_STUXF(name, stop, opc, type) \ |
99e300ef BS |
3558 | GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type); \ |
3559 | \ | |
3560 | static void glue(gen_, name##ux)(DisasContext *ctx) \ | |
79aceca5 | 3561 | { \ |
a0d7d5a7 | 3562 | TCGv EA; \ |
76a66253 | 3563 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3564 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3565 | return; \ |
3566 | } \ | |
76a66253 | 3567 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 3568 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 3569 | return; \ |
9a64fbe4 | 3570 | } \ |
76db3ba4 | 3571 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3572 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3573 | gen_addr_reg_index(ctx, EA); \ |
3574 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 AJ |
3575 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
3576 | tcg_temp_free(EA); \ | |
79aceca5 FB |
3577 | } |
3578 | ||
a0d7d5a7 | 3579 | #define GEN_STXF(name, stop, opc2, opc3, type) \ |
99e300ef BS |
3580 | GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type); \ |
3581 | \ | |
3582 | static void glue(gen_, name##x)(DisasContext *ctx) \ | |
79aceca5 | 3583 | { \ |
a0d7d5a7 | 3584 | TCGv EA; \ |
76a66253 | 3585 | if (unlikely(!ctx->fpu_enabled)) { \ |
e06fcd75 | 3586 | gen_exception(ctx, POWERPC_EXCP_FPU); \ |
4ecc3190 FB |
3587 | return; \ |
3588 | } \ | |
76db3ba4 | 3589 | gen_set_access_type(ctx, ACCESS_FLOAT); \ |
a0d7d5a7 | 3590 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
3591 | gen_addr_reg_index(ctx, EA); \ |
3592 | gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \ | |
a0d7d5a7 | 3593 | tcg_temp_free(EA); \ |
79aceca5 FB |
3594 | } |
3595 | ||
a0d7d5a7 AJ |
3596 | #define GEN_STFS(name, stop, op, type) \ |
3597 | GEN_STF(name, stop, op | 0x20, type); \ | |
3598 | GEN_STUF(name, stop, op | 0x21, type); \ | |
3599 | GEN_STUXF(name, stop, op | 0x01, type); \ | |
3600 | GEN_STXF(name, stop, 0x17, op | 0x00, type) | |
3601 | ||
76db3ba4 | 3602 | static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3603 | { |
3604 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
3605 | TCGv t1 = tcg_temp_new(); | |
3606 | gen_helper_float64_to_float32(t0, arg1); | |
3607 | tcg_gen_extu_i32_tl(t1, t0); | |
3608 | tcg_temp_free_i32(t0); | |
76db3ba4 | 3609 | gen_qemu_st32(ctx, t1, arg2); |
a0d7d5a7 AJ |
3610 | tcg_temp_free(t1); |
3611 | } | |
79aceca5 FB |
3612 | |
3613 | /* stfd stfdu stfdux stfdx */ | |
a0d7d5a7 | 3614 | GEN_STFS(stfd, st64, 0x16, PPC_FLOAT); |
79aceca5 | 3615 | /* stfs stfsu stfsux stfsx */ |
a0d7d5a7 | 3616 | GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT); |
79aceca5 FB |
3617 | |
3618 | /* Optional: */ | |
76db3ba4 | 3619 | static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) |
a0d7d5a7 AJ |
3620 | { |
3621 | TCGv t0 = tcg_temp_new(); | |
3622 | tcg_gen_trunc_i64_tl(t0, arg1), | |
76db3ba4 | 3623 | gen_qemu_st32(ctx, t0, arg2); |
a0d7d5a7 AJ |
3624 | tcg_temp_free(t0); |
3625 | } | |
79aceca5 | 3626 | /* stfiwx */ |
a0d7d5a7 | 3627 | GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX); |
79aceca5 FB |
3628 | |
3629 | /*** Branch ***/ | |
b068d6a7 JM |
3630 | static always_inline void gen_goto_tb (DisasContext *ctx, int n, |
3631 | target_ulong dest) | |
c1942362 FB |
3632 | { |
3633 | TranslationBlock *tb; | |
3634 | tb = ctx->tb; | |
a2ffb812 AJ |
3635 | #if defined(TARGET_PPC64) |
3636 | if (!ctx->sf_mode) | |
3637 | dest = (uint32_t) dest; | |
3638 | #endif | |
57fec1fe | 3639 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) && |
8cbcb4fa | 3640 | likely(!ctx->singlestep_enabled)) { |
57fec1fe | 3641 | tcg_gen_goto_tb(n); |
a2ffb812 | 3642 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
57fec1fe | 3643 | tcg_gen_exit_tb((long)tb + n); |
c1942362 | 3644 | } else { |
a2ffb812 | 3645 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3646 | if (unlikely(ctx->singlestep_enabled)) { |
3647 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3648 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
8cbcb4fa AJ |
3649 | ctx->exception == POWERPC_EXCP_BRANCH) { |
3650 | target_ulong tmp = ctx->nip; | |
3651 | ctx->nip = dest; | |
e06fcd75 | 3652 | gen_exception(ctx, POWERPC_EXCP_TRACE); |
8cbcb4fa AJ |
3653 | ctx->nip = tmp; |
3654 | } | |
3655 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3656 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3657 | } |
3658 | } | |
57fec1fe | 3659 | tcg_gen_exit_tb(0); |
c1942362 | 3660 | } |
c53be334 FB |
3661 | } |
3662 | ||
b068d6a7 | 3663 | static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip) |
e1833e1f JM |
3664 | { |
3665 | #if defined(TARGET_PPC64) | |
a2ffb812 AJ |
3666 | if (ctx->sf_mode == 0) |
3667 | tcg_gen_movi_tl(cpu_lr, (uint32_t)nip); | |
e1833e1f JM |
3668 | else |
3669 | #endif | |
a2ffb812 | 3670 | tcg_gen_movi_tl(cpu_lr, nip); |
e1833e1f JM |
3671 | } |
3672 | ||
79aceca5 | 3673 | /* b ba bl bla */ |
99e300ef | 3674 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3675 | { |
76a66253 | 3676 | target_ulong li, target; |
38a64f9d | 3677 | |
8cbcb4fa | 3678 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3679 | /* sign extend LI */ |
76a66253 | 3680 | #if defined(TARGET_PPC64) |
d9bce9d9 JM |
3681 | if (ctx->sf_mode) |
3682 | li = ((int64_t)LI(ctx->opcode) << 38) >> 38; | |
3683 | else | |
76a66253 | 3684 | #endif |
d9bce9d9 | 3685 | li = ((int32_t)LI(ctx->opcode) << 6) >> 6; |
76a66253 | 3686 | if (likely(AA(ctx->opcode) == 0)) |
046d6672 | 3687 | target = ctx->nip + li - 4; |
79aceca5 | 3688 | else |
9a64fbe4 | 3689 | target = li; |
e1833e1f JM |
3690 | if (LK(ctx->opcode)) |
3691 | gen_setlr(ctx, ctx->nip); | |
c1942362 | 3692 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3693 | } |
3694 | ||
e98a6e40 FB |
3695 | #define BCOND_IM 0 |
3696 | #define BCOND_LR 1 | |
3697 | #define BCOND_CTR 2 | |
3698 | ||
b068d6a7 | 3699 | static always_inline void gen_bcond (DisasContext *ctx, int type) |
d9bce9d9 | 3700 | { |
d9bce9d9 | 3701 | uint32_t bo = BO(ctx->opcode); |
a2ffb812 AJ |
3702 | int l1 = gen_new_label(); |
3703 | TCGv target; | |
e98a6e40 | 3704 | |
8cbcb4fa | 3705 | ctx->exception = POWERPC_EXCP_BRANCH; |
a2ffb812 | 3706 | if (type == BCOND_LR || type == BCOND_CTR) { |
a7812ae4 | 3707 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3708 | if (type == BCOND_CTR) |
3709 | tcg_gen_mov_tl(target, cpu_ctr); | |
3710 | else | |
3711 | tcg_gen_mov_tl(target, cpu_lr); | |
e98a6e40 | 3712 | } |
e1833e1f JM |
3713 | if (LK(ctx->opcode)) |
3714 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3715 | l1 = gen_new_label(); |
3716 | if ((bo & 0x4) == 0) { | |
3717 | /* Decrement and test CTR */ | |
a7812ae4 | 3718 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3719 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3720 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3721 | return; |
3722 | } | |
3723 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
d9bce9d9 | 3724 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3725 | if (!ctx->sf_mode) |
3726 | tcg_gen_ext32u_tl(temp, cpu_ctr); | |
3727 | else | |
d9bce9d9 | 3728 | #endif |
a2ffb812 AJ |
3729 | tcg_gen_mov_tl(temp, cpu_ctr); |
3730 | if (bo & 0x2) { | |
3731 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3732 | } else { | |
3733 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3734 | } |
a7812ae4 | 3735 | tcg_temp_free(temp); |
a2ffb812 AJ |
3736 | } |
3737 | if ((bo & 0x10) == 0) { | |
3738 | /* Test CR */ | |
3739 | uint32_t bi = BI(ctx->opcode); | |
3740 | uint32_t mask = 1 << (3 - (bi & 0x03)); | |
a7812ae4 | 3741 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3742 | |
d9bce9d9 | 3743 | if (bo & 0x8) { |
a2ffb812 AJ |
3744 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3745 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3746 | } else { |
a2ffb812 AJ |
3747 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3748 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3749 | } |
a7812ae4 | 3750 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3751 | } |
e98a6e40 | 3752 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3753 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3754 | if (likely(AA(ctx->opcode) == 0)) { | |
3755 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3756 | } else { | |
3757 | gen_goto_tb(ctx, 0, li); | |
3758 | } | |
c53be334 | 3759 | gen_set_label(l1); |
c1942362 | 3760 | gen_goto_tb(ctx, 1, ctx->nip); |
e98a6e40 | 3761 | } else { |
d9bce9d9 | 3762 | #if defined(TARGET_PPC64) |
a2ffb812 AJ |
3763 | if (!(ctx->sf_mode)) |
3764 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); | |
3765 | else | |
3766 | #endif | |
3767 | tcg_gen_andi_tl(cpu_nip, target, ~3); | |
3768 | tcg_gen_exit_tb(0); | |
3769 | gen_set_label(l1); | |
3770 | #if defined(TARGET_PPC64) | |
3771 | if (!(ctx->sf_mode)) | |
3772 | tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip); | |
d9bce9d9 JM |
3773 | else |
3774 | #endif | |
a2ffb812 | 3775 | tcg_gen_movi_tl(cpu_nip, ctx->nip); |
57fec1fe | 3776 | tcg_gen_exit_tb(0); |
08e46e54 | 3777 | } |
e98a6e40 FB |
3778 | } |
3779 | ||
99e300ef | 3780 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3781 | { |
e98a6e40 FB |
3782 | gen_bcond(ctx, BCOND_IM); |
3783 | } | |
3784 | ||
99e300ef | 3785 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3786 | { |
e98a6e40 FB |
3787 | gen_bcond(ctx, BCOND_CTR); |
3788 | } | |
3789 | ||
99e300ef | 3790 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3791 | { |
e98a6e40 FB |
3792 | gen_bcond(ctx, BCOND_LR); |
3793 | } | |
79aceca5 FB |
3794 | |
3795 | /*** Condition register logical ***/ | |
e1571908 | 3796 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef BS |
3797 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER); \ |
3798 | \ | |
3799 | static void glue(gen_, name)(DisasContext *ctx) \ | |
79aceca5 | 3800 | { \ |
fc0d441e JM |
3801 | uint8_t bitmask; \ |
3802 | int sh; \ | |
a7812ae4 | 3803 | TCGv_i32 t0, t1; \ |
fc0d441e | 3804 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3805 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3806 | if (sh > 0) \ |
fea0c503 | 3807 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3808 | else if (sh < 0) \ |
fea0c503 | 3809 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3810 | else \ |
fea0c503 | 3811 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3812 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3813 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3814 | if (sh > 0) \ | |
fea0c503 | 3815 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3816 | else if (sh < 0) \ |
fea0c503 | 3817 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3818 | else \ |
fea0c503 AJ |
3819 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3820 | tcg_op(t0, t0, t1); \ | |
fc0d441e | 3821 | bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ |
fea0c503 AJ |
3822 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3823 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3824 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3825 | tcg_temp_free_i32(t0); \ |
3826 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3827 | } |
3828 | ||
3829 | /* crand */ | |
e1571908 | 3830 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3831 | /* crandc */ |
e1571908 | 3832 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3833 | /* creqv */ |
e1571908 | 3834 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3835 | /* crnand */ |
e1571908 | 3836 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3837 | /* crnor */ |
e1571908 | 3838 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3839 | /* cror */ |
e1571908 | 3840 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3841 | /* crorc */ |
e1571908 | 3842 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3843 | /* crxor */ |
e1571908 | 3844 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3845 | |
54623277 | 3846 | /* mcrf */ |
99e300ef | 3847 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3848 | { |
47e4661c | 3849 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3850 | } |
3851 | ||
3852 | /*** System linkage ***/ | |
99e300ef | 3853 | |
54623277 | 3854 | /* rfi (mem_idx only) */ |
99e300ef | 3855 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3856 | { |
9a64fbe4 | 3857 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 3858 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 FB |
3859 | #else |
3860 | /* Restore CPU state */ | |
76db3ba4 | 3861 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3862 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 3863 | return; |
9a64fbe4 | 3864 | } |
d72a19f7 | 3865 | gen_helper_rfi(); |
e06fcd75 | 3866 | gen_sync_exception(ctx); |
9a64fbe4 | 3867 | #endif |
79aceca5 FB |
3868 | } |
3869 | ||
426613db | 3870 | #if defined(TARGET_PPC64) |
99e300ef | 3871 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3872 | { |
3873 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3874 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3875 | #else |
3876 | /* Restore CPU state */ | |
76db3ba4 | 3877 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 3878 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
3879 | return; |
3880 | } | |
d72a19f7 | 3881 | gen_helper_rfid(); |
e06fcd75 | 3882 | gen_sync_exception(ctx); |
426613db JM |
3883 | #endif |
3884 | } | |
426613db | 3885 | |
99e300ef | 3886 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3887 | { |
3888 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 3889 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3890 | #else |
3891 | /* Restore CPU state */ | |
76db3ba4 | 3892 | if (unlikely(ctx->mem_idx <= 1)) { |
e06fcd75 | 3893 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
3894 | return; |
3895 | } | |
d72a19f7 | 3896 | gen_helper_hrfid(); |
e06fcd75 | 3897 | gen_sync_exception(ctx); |
be147d08 JM |
3898 | #endif |
3899 | } | |
3900 | #endif | |
3901 | ||
79aceca5 | 3902 | /* sc */ |
417bf010 JM |
3903 | #if defined(CONFIG_USER_ONLY) |
3904 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3905 | #else | |
3906 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3907 | #endif | |
99e300ef | 3908 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3909 | { |
e1833e1f JM |
3910 | uint32_t lev; |
3911 | ||
3912 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3913 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3914 | } |
3915 | ||
3916 | /*** Trap ***/ | |
99e300ef | 3917 | |
54623277 | 3918 | /* tw */ |
99e300ef | 3919 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3920 | { |
cab3bee2 | 3921 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
a0ae05aa | 3922 | /* Update the nip since this might generate a trap exception */ |
d9bce9d9 | 3923 | gen_update_nip(ctx, ctx->nip); |
cab3bee2 AJ |
3924 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3925 | tcg_temp_free_i32(t0); | |
79aceca5 FB |
3926 | } |
3927 | ||
3928 | /* twi */ | |
99e300ef | 3929 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3930 | { |
cab3bee2 AJ |
3931 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3932 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
d9bce9d9 JM |
3933 | /* Update the nip since this might generate a trap exception */ |
3934 | gen_update_nip(ctx, ctx->nip); | |
cab3bee2 AJ |
3935 | gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3936 | tcg_temp_free(t0); | |
3937 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3938 | } |
3939 | ||
d9bce9d9 JM |
3940 | #if defined(TARGET_PPC64) |
3941 | /* td */ | |
99e300ef | 3942 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3943 | { |
cab3bee2 | 3944 | TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode)); |
d9bce9d9 JM |
3945 | /* Update the nip since this might generate a trap exception */ |
3946 | gen_update_nip(ctx, ctx->nip); | |
cab3bee2 AJ |
3947 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
3948 | tcg_temp_free_i32(t0); | |
d9bce9d9 JM |
3949 | } |
3950 | ||
3951 | /* tdi */ | |
99e300ef | 3952 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3953 | { |
cab3bee2 AJ |
3954 | TCGv t0 = tcg_const_tl(SIMM(ctx->opcode)); |
3955 | TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode)); | |
d9bce9d9 JM |
3956 | /* Update the nip since this might generate a trap exception */ |
3957 | gen_update_nip(ctx, ctx->nip); | |
cab3bee2 AJ |
3958 | gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1); |
3959 | tcg_temp_free(t0); | |
3960 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3961 | } |
3962 | #endif | |
3963 | ||
79aceca5 | 3964 | /*** Processor control ***/ |
99e300ef | 3965 | |
54623277 | 3966 | /* mcrxr */ |
99e300ef | 3967 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3968 | { |
3d7b417e AJ |
3969 | tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer); |
3970 | tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA); | |
269f3e95 | 3971 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA)); |
79aceca5 FB |
3972 | } |
3973 | ||
0cfe11ea | 3974 | /* mfcr mfocrf */ |
99e300ef | 3975 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3976 | { |
76a66253 | 3977 | uint32_t crm, crn; |
3b46e624 | 3978 | |
76a66253 JM |
3979 | if (likely(ctx->opcode & 0x00100000)) { |
3980 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3981 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3982 | crn = ctz32 (crm); |
e1571908 | 3983 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3984 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3985 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3986 | } |
d9bce9d9 | 3987 | } else { |
651721b2 AJ |
3988 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3989 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3990 | tcg_gen_shli_i32(t0, t0, 4); | |
3991 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3992 | tcg_gen_shli_i32(t0, t0, 4); | |
3993 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3994 | tcg_gen_shli_i32(t0, t0, 4); | |
3995 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3996 | tcg_gen_shli_i32(t0, t0, 4); | |
3997 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3998 | tcg_gen_shli_i32(t0, t0, 4); | |
3999 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
4000 | tcg_gen_shli_i32(t0, t0, 4); | |
4001 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
4002 | tcg_gen_shli_i32(t0, t0, 4); | |
4003 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
4004 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4005 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 4006 | } |
79aceca5 FB |
4007 | } |
4008 | ||
4009 | /* mfmsr */ | |
99e300ef | 4010 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 4011 | { |
9a64fbe4 | 4012 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4013 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4014 | #else |
76db3ba4 | 4015 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4016 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4017 | return; |
9a64fbe4 | 4018 | } |
6527f6ea | 4019 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
9a64fbe4 | 4020 | #endif |
79aceca5 FB |
4021 | } |
4022 | ||
a11b8151 | 4023 | #if 1 |
6f2d8978 | 4024 | #define SPR_NOACCESS ((void *)(-1UL)) |
3fc6c082 FB |
4025 | #else |
4026 | static void spr_noaccess (void *opaque, int sprn) | |
4027 | { | |
4028 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
4029 | printf("ERROR: try to access SPR %d !\n", sprn); | |
4030 | } | |
4031 | #define SPR_NOACCESS (&spr_noaccess) | |
4032 | #endif | |
4033 | ||
79aceca5 | 4034 | /* mfspr */ |
b068d6a7 | 4035 | static always_inline void gen_op_mfspr (DisasContext *ctx) |
79aceca5 | 4036 | { |
45d827d2 | 4037 | void (*read_cb)(void *opaque, int gprn, int sprn); |
79aceca5 FB |
4038 | uint32_t sprn = SPR(ctx->opcode); |
4039 | ||
3fc6c082 | 4040 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4041 | if (ctx->mem_idx == 2) |
be147d08 | 4042 | read_cb = ctx->spr_cb[sprn].hea_read; |
76db3ba4 | 4043 | else if (ctx->mem_idx) |
3fc6c082 FB |
4044 | read_cb = ctx->spr_cb[sprn].oea_read; |
4045 | else | |
9a64fbe4 | 4046 | #endif |
3fc6c082 | 4047 | read_cb = ctx->spr_cb[sprn].uea_read; |
76a66253 JM |
4048 | if (likely(read_cb != NULL)) { |
4049 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 4050 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
4051 | } else { |
4052 | /* Privilege exception */ | |
9fceefa7 JM |
4053 | /* This is a hack to avoid warnings when running Linux: |
4054 | * this OS breaks the PowerPC virtualisation model, | |
4055 | * allowing userland application to read the PVR | |
4056 | */ | |
4057 | if (sprn != SPR_PVR) { | |
93fcfe39 | 4058 | qemu_log("Trying to read privileged spr %d %03x at " |
077fc206 | 4059 | ADDRX "\n", sprn, sprn, ctx->nip); |
077fc206 JM |
4060 | printf("Trying to read privileged spr %d %03x at " ADDRX "\n", |
4061 | sprn, sprn, ctx->nip); | |
f24e5695 | 4062 | } |
e06fcd75 | 4063 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 4064 | } |
3fc6c082 FB |
4065 | } else { |
4066 | /* Not defined */ | |
93fcfe39 | 4067 | qemu_log("Trying to read invalid spr %d %03x at " |
077fc206 | 4068 | ADDRX "\n", sprn, sprn, ctx->nip); |
077fc206 JM |
4069 | printf("Trying to read invalid spr %d %03x at " ADDRX "\n", |
4070 | sprn, sprn, ctx->nip); | |
e06fcd75 | 4071 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4072 | } |
79aceca5 FB |
4073 | } |
4074 | ||
99e300ef | 4075 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 4076 | { |
3fc6c082 | 4077 | gen_op_mfspr(ctx); |
76a66253 | 4078 | } |
3fc6c082 FB |
4079 | |
4080 | /* mftb */ | |
99e300ef | 4081 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
4082 | { |
4083 | gen_op_mfspr(ctx); | |
79aceca5 FB |
4084 | } |
4085 | ||
0cfe11ea | 4086 | /* mtcrf mtocrf*/ |
99e300ef | 4087 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 4088 | { |
76a66253 | 4089 | uint32_t crm, crn; |
3b46e624 | 4090 | |
76a66253 | 4091 | crm = CRM(ctx->opcode); |
8dd640e4 | 4092 | if (likely((ctx->opcode & 0x00100000))) { |
4093 | if (crm && ((crm & (crm - 1)) == 0)) { | |
4094 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 4095 | crn = ctz32 (crm); |
8dd640e4 | 4096 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
4097 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4098 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 4099 | tcg_temp_free_i32(temp); |
4100 | } | |
76a66253 | 4101 | } else { |
651721b2 AJ |
4102 | TCGv_i32 temp = tcg_temp_new_i32(); |
4103 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
4104 | for (crn = 0 ; crn < 8 ; crn++) { | |
4105 | if (crm & (1 << crn)) { | |
4106 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
4107 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
4108 | } | |
4109 | } | |
a7812ae4 | 4110 | tcg_temp_free_i32(temp); |
76a66253 | 4111 | } |
79aceca5 FB |
4112 | } |
4113 | ||
4114 | /* mtmsr */ | |
426613db | 4115 | #if defined(TARGET_PPC64) |
99e300ef | 4116 | static void gen_mtmsrd(DisasContext *ctx) |
426613db JM |
4117 | { |
4118 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4119 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db | 4120 | #else |
76db3ba4 | 4121 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4122 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
426613db JM |
4123 | return; |
4124 | } | |
be147d08 JM |
4125 | if (ctx->opcode & 0x00010000) { |
4126 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4127 | TCGv t0 = tcg_temp_new(); |
4128 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4129 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4130 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4131 | tcg_temp_free(t0); | |
be147d08 | 4132 | } else { |
056b05f8 JM |
4133 | /* XXX: we need to update nip before the store |
4134 | * if we enter power saving mode, we will exit the loop | |
4135 | * directly from ppc_store_msr | |
4136 | */ | |
be147d08 | 4137 | gen_update_nip(ctx, ctx->nip); |
6527f6ea | 4138 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
4139 | /* Must stop the translation as machine state (may have) changed */ |
4140 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 4141 | gen_stop_exception(ctx); |
be147d08 | 4142 | } |
426613db JM |
4143 | #endif |
4144 | } | |
4145 | #endif | |
4146 | ||
99e300ef | 4147 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 4148 | { |
9a64fbe4 | 4149 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4150 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4151 | #else |
76db3ba4 | 4152 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4153 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4154 | return; |
9a64fbe4 | 4155 | } |
be147d08 JM |
4156 | if (ctx->opcode & 0x00010000) { |
4157 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
4158 | TCGv t0 = tcg_temp_new(); |
4159 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
4160 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE))); | |
4161 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
4162 | tcg_temp_free(t0); | |
be147d08 | 4163 | } else { |
056b05f8 JM |
4164 | /* XXX: we need to update nip before the store |
4165 | * if we enter power saving mode, we will exit the loop | |
4166 | * directly from ppc_store_msr | |
4167 | */ | |
be147d08 | 4168 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 4169 | #if defined(TARGET_PPC64) |
6527f6ea AJ |
4170 | if (!ctx->sf_mode) { |
4171 | TCGv t0 = tcg_temp_new(); | |
4172 | TCGv t1 = tcg_temp_new(); | |
4173 | tcg_gen_andi_tl(t0, cpu_msr, 0xFFFFFFFF00000000ULL); | |
4174 | tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]); | |
4175 | tcg_gen_or_tl(t0, t0, t1); | |
4176 | tcg_temp_free(t1); | |
4177 | gen_helper_store_msr(t0); | |
4178 | tcg_temp_free(t0); | |
4179 | } else | |
d9bce9d9 | 4180 | #endif |
6527f6ea | 4181 | gen_helper_store_msr(cpu_gpr[rS(ctx->opcode)]); |
be147d08 | 4182 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 4183 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 4184 | gen_stop_exception(ctx); |
be147d08 | 4185 | } |
9a64fbe4 | 4186 | #endif |
79aceca5 FB |
4187 | } |
4188 | ||
4189 | /* mtspr */ | |
99e300ef | 4190 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 4191 | { |
45d827d2 | 4192 | void (*write_cb)(void *opaque, int sprn, int gprn); |
79aceca5 FB |
4193 | uint32_t sprn = SPR(ctx->opcode); |
4194 | ||
3fc6c082 | 4195 | #if !defined(CONFIG_USER_ONLY) |
76db3ba4 | 4196 | if (ctx->mem_idx == 2) |
be147d08 | 4197 | write_cb = ctx->spr_cb[sprn].hea_write; |
76db3ba4 | 4198 | else if (ctx->mem_idx) |
3fc6c082 FB |
4199 | write_cb = ctx->spr_cb[sprn].oea_write; |
4200 | else | |
9a64fbe4 | 4201 | #endif |
3fc6c082 | 4202 | write_cb = ctx->spr_cb[sprn].uea_write; |
76a66253 JM |
4203 | if (likely(write_cb != NULL)) { |
4204 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 4205 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
4206 | } else { |
4207 | /* Privilege exception */ | |
93fcfe39 | 4208 | qemu_log("Trying to write privileged spr %d %03x at " |
077fc206 | 4209 | ADDRX "\n", sprn, sprn, ctx->nip); |
077fc206 JM |
4210 | printf("Trying to write privileged spr %d %03x at " ADDRX "\n", |
4211 | sprn, sprn, ctx->nip); | |
e06fcd75 | 4212 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 4213 | } |
3fc6c082 FB |
4214 | } else { |
4215 | /* Not defined */ | |
93fcfe39 | 4216 | qemu_log("Trying to write invalid spr %d %03x at " |
077fc206 | 4217 | ADDRX "\n", sprn, sprn, ctx->nip); |
077fc206 JM |
4218 | printf("Trying to write invalid spr %d %03x at " ADDRX "\n", |
4219 | sprn, sprn, ctx->nip); | |
e06fcd75 | 4220 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
79aceca5 | 4221 | } |
79aceca5 FB |
4222 | } |
4223 | ||
4224 | /*** Cache management ***/ | |
99e300ef | 4225 | |
54623277 | 4226 | /* dcbf */ |
99e300ef | 4227 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4228 | { |
dac454af | 4229 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4230 | TCGv t0; |
4231 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4232 | t0 = tcg_temp_new(); | |
4233 | gen_addr_reg_index(ctx, t0); | |
4234 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4235 | tcg_temp_free(t0); |
79aceca5 FB |
4236 | } |
4237 | ||
4238 | /* dcbi (Supervisor only) */ | |
99e300ef | 4239 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4240 | { |
a541f297 | 4241 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4242 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a541f297 | 4243 | #else |
b61f2753 | 4244 | TCGv EA, val; |
76db3ba4 | 4245 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4246 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4247 | return; |
9a64fbe4 | 4248 | } |
a7812ae4 | 4249 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4250 | gen_set_access_type(ctx, ACCESS_CACHE); |
4251 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4252 | val = tcg_temp_new(); |
76a66253 | 4253 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4254 | gen_qemu_ld8u(ctx, val, EA); |
4255 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4256 | tcg_temp_free(val); |
4257 | tcg_temp_free(EA); | |
a541f297 | 4258 | #endif |
79aceca5 FB |
4259 | } |
4260 | ||
4261 | /* dcdst */ | |
99e300ef | 4262 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4263 | { |
76a66253 | 4264 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4265 | TCGv t0; |
4266 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4267 | t0 = tcg_temp_new(); | |
4268 | gen_addr_reg_index(ctx, t0); | |
4269 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4270 | tcg_temp_free(t0); |
79aceca5 FB |
4271 | } |
4272 | ||
4273 | /* dcbt */ | |
99e300ef | 4274 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4275 | { |
0db1b20e | 4276 | /* interpreted as no-op */ |
76a66253 JM |
4277 | /* XXX: specification say this is treated as a load by the MMU |
4278 | * but does not generate any exception | |
4279 | */ | |
79aceca5 FB |
4280 | } |
4281 | ||
4282 | /* dcbtst */ | |
99e300ef | 4283 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4284 | { |
0db1b20e | 4285 | /* interpreted as no-op */ |
76a66253 JM |
4286 | /* XXX: specification say this is treated as a load by the MMU |
4287 | * but does not generate any exception | |
4288 | */ | |
79aceca5 FB |
4289 | } |
4290 | ||
4291 | /* dcbz */ | |
99e300ef | 4292 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4293 | { |
76db3ba4 AJ |
4294 | TCGv t0; |
4295 | gen_set_access_type(ctx, ACCESS_CACHE); | |
799a8c8d AJ |
4296 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4297 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4298 | t0 = tcg_temp_new(); |
4299 | gen_addr_reg_index(ctx, t0); | |
799a8c8d AJ |
4300 | gen_helper_dcbz(t0); |
4301 | tcg_temp_free(t0); | |
d63001d1 JM |
4302 | } |
4303 | ||
e8eaa2c0 | 4304 | static void gen_dcbz_970(DisasContext *ctx) |
d63001d1 | 4305 | { |
76db3ba4 AJ |
4306 | TCGv t0; |
4307 | gen_set_access_type(ctx, ACCESS_CACHE); | |
799a8c8d AJ |
4308 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4309 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4310 | t0 = tcg_temp_new(); |
4311 | gen_addr_reg_index(ctx, t0); | |
d63001d1 | 4312 | if (ctx->opcode & 0x00200000) |
799a8c8d | 4313 | gen_helper_dcbz(t0); |
d63001d1 | 4314 | else |
799a8c8d AJ |
4315 | gen_helper_dcbz_970(t0); |
4316 | tcg_temp_free(t0); | |
79aceca5 FB |
4317 | } |
4318 | ||
ae1c1a3d | 4319 | /* dst / dstt */ |
99e300ef | 4320 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4321 | { |
4322 | if (rA(ctx->opcode) == 0) { | |
4323 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4324 | } else { | |
4325 | /* interpreted as no-op */ | |
4326 | } | |
4327 | } | |
4328 | ||
4329 | /* dstst /dststt */ | |
99e300ef | 4330 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4331 | { |
4332 | if (rA(ctx->opcode) == 0) { | |
4333 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); | |
4334 | } else { | |
4335 | /* interpreted as no-op */ | |
4336 | } | |
4337 | ||
4338 | } | |
4339 | ||
4340 | /* dss / dssall */ | |
99e300ef | 4341 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4342 | { |
4343 | /* interpreted as no-op */ | |
4344 | } | |
4345 | ||
79aceca5 | 4346 | /* icbi */ |
99e300ef | 4347 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4348 | { |
76db3ba4 AJ |
4349 | TCGv t0; |
4350 | gen_set_access_type(ctx, ACCESS_CACHE); | |
30032c94 JM |
4351 | /* NIP cannot be restored if the memory exception comes from an helper */ |
4352 | gen_update_nip(ctx, ctx->nip - 4); | |
76db3ba4 AJ |
4353 | t0 = tcg_temp_new(); |
4354 | gen_addr_reg_index(ctx, t0); | |
37d269df AJ |
4355 | gen_helper_icbi(t0); |
4356 | tcg_temp_free(t0); | |
79aceca5 FB |
4357 | } |
4358 | ||
4359 | /* Optional: */ | |
4360 | /* dcba */ | |
99e300ef | 4361 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4362 | { |
0db1b20e JM |
4363 | /* interpreted as no-op */ |
4364 | /* XXX: specification say this is treated as a store by the MMU | |
4365 | * but does not generate any exception | |
4366 | */ | |
79aceca5 FB |
4367 | } |
4368 | ||
4369 | /*** Segment register manipulation ***/ | |
4370 | /* Supervisor only: */ | |
99e300ef | 4371 | |
54623277 | 4372 | /* mfsr */ |
99e300ef | 4373 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4374 | { |
9a64fbe4 | 4375 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4376 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4377 | #else |
74d37793 | 4378 | TCGv t0; |
76db3ba4 | 4379 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4380 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4381 | return; |
9a64fbe4 | 4382 | } |
74d37793 AJ |
4383 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4384 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); | |
4385 | tcg_temp_free(t0); | |
9a64fbe4 | 4386 | #endif |
79aceca5 FB |
4387 | } |
4388 | ||
4389 | /* mfsrin */ | |
99e300ef | 4390 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4391 | { |
9a64fbe4 | 4392 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4393 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4394 | #else |
74d37793 | 4395 | TCGv t0; |
76db3ba4 | 4396 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4397 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4398 | return; |
9a64fbe4 | 4399 | } |
74d37793 AJ |
4400 | t0 = tcg_temp_new(); |
4401 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4402 | tcg_gen_andi_tl(t0, t0, 0xF); | |
4403 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); | |
4404 | tcg_temp_free(t0); | |
9a64fbe4 | 4405 | #endif |
79aceca5 FB |
4406 | } |
4407 | ||
4408 | /* mtsr */ | |
99e300ef | 4409 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4410 | { |
9a64fbe4 | 4411 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4412 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4413 | #else |
74d37793 | 4414 | TCGv t0; |
76db3ba4 | 4415 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4416 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4417 | return; |
9a64fbe4 | 4418 | } |
74d37793 AJ |
4419 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4420 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); | |
4421 | tcg_temp_free(t0); | |
9a64fbe4 | 4422 | #endif |
79aceca5 FB |
4423 | } |
4424 | ||
4425 | /* mtsrin */ | |
99e300ef | 4426 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4427 | { |
9a64fbe4 | 4428 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4429 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9a64fbe4 | 4430 | #else |
74d37793 | 4431 | TCGv t0; |
76db3ba4 | 4432 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4433 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
9fddaa0c | 4434 | return; |
9a64fbe4 | 4435 | } |
74d37793 AJ |
4436 | t0 = tcg_temp_new(); |
4437 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4438 | tcg_gen_andi_tl(t0, t0, 0xF); | |
4439 | gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]); | |
4440 | tcg_temp_free(t0); | |
9a64fbe4 | 4441 | #endif |
79aceca5 FB |
4442 | } |
4443 | ||
12de9a39 JM |
4444 | #if defined(TARGET_PPC64) |
4445 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4446 | |
54623277 | 4447 | /* mfsr */ |
e8eaa2c0 | 4448 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4449 | { |
4450 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4451 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4452 | #else |
74d37793 | 4453 | TCGv t0; |
76db3ba4 | 4454 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4455 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4456 | return; |
4457 | } | |
74d37793 | 4458 | t0 = tcg_const_tl(SR(ctx->opcode)); |
f6b868fc | 4459 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
74d37793 | 4460 | tcg_temp_free(t0); |
12de9a39 JM |
4461 | #endif |
4462 | } | |
4463 | ||
4464 | /* mfsrin */ | |
e8eaa2c0 | 4465 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4466 | { |
4467 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4468 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4469 | #else |
74d37793 | 4470 | TCGv t0; |
76db3ba4 | 4471 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4472 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4473 | return; |
4474 | } | |
74d37793 AJ |
4475 | t0 = tcg_temp_new(); |
4476 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4477 | tcg_gen_andi_tl(t0, t0, 0xF); | |
f6b868fc | 4478 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); |
74d37793 | 4479 | tcg_temp_free(t0); |
12de9a39 JM |
4480 | #endif |
4481 | } | |
4482 | ||
4483 | /* mtsr */ | |
e8eaa2c0 | 4484 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4485 | { |
4486 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4487 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4488 | #else |
74d37793 | 4489 | TCGv t0; |
76db3ba4 | 4490 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4491 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4492 | return; |
4493 | } | |
74d37793 | 4494 | t0 = tcg_const_tl(SR(ctx->opcode)); |
f6b868fc | 4495 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4496 | tcg_temp_free(t0); |
12de9a39 JM |
4497 | #endif |
4498 | } | |
4499 | ||
4500 | /* mtsrin */ | |
e8eaa2c0 | 4501 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4502 | { |
4503 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4504 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 | 4505 | #else |
74d37793 | 4506 | TCGv t0; |
76db3ba4 | 4507 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4508 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
12de9a39 JM |
4509 | return; |
4510 | } | |
74d37793 AJ |
4511 | t0 = tcg_temp_new(); |
4512 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4513 | tcg_gen_andi_tl(t0, t0, 0xF); | |
f6b868fc | 4514 | gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4515 | tcg_temp_free(t0); |
12de9a39 JM |
4516 | #endif |
4517 | } | |
f6b868fc BS |
4518 | |
4519 | /* slbmte */ | |
e8eaa2c0 | 4520 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4521 | { |
4522 | #if defined(CONFIG_USER_ONLY) | |
4523 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4524 | #else | |
4525 | if (unlikely(!ctx->mem_idx)) { | |
4526 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4527 | return; | |
4528 | } | |
4529 | gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
4530 | #endif | |
4531 | } | |
4532 | ||
12de9a39 JM |
4533 | #endif /* defined(TARGET_PPC64) */ |
4534 | ||
79aceca5 | 4535 | /*** Lookaside buffer management ***/ |
76db3ba4 | 4536 | /* Optional & mem_idx only: */ |
99e300ef | 4537 | |
54623277 | 4538 | /* tlbia */ |
99e300ef | 4539 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4540 | { |
9a64fbe4 | 4541 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4542 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4543 | #else |
76db3ba4 | 4544 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4545 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4546 | return; |
9a64fbe4 | 4547 | } |
74d37793 | 4548 | gen_helper_tlbia(); |
9a64fbe4 | 4549 | #endif |
79aceca5 FB |
4550 | } |
4551 | ||
bf14b1ce | 4552 | /* tlbiel */ |
99e300ef | 4553 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4554 | { |
4555 | #if defined(CONFIG_USER_ONLY) | |
4556 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4557 | #else | |
4558 | if (unlikely(!ctx->mem_idx)) { | |
4559 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); | |
4560 | return; | |
4561 | } | |
4562 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); | |
4563 | #endif | |
4564 | } | |
4565 | ||
79aceca5 | 4566 | /* tlbie */ |
99e300ef | 4567 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4568 | { |
9a64fbe4 | 4569 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4570 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4571 | #else |
76db3ba4 | 4572 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4573 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4574 | return; |
9a64fbe4 | 4575 | } |
d9bce9d9 | 4576 | #if defined(TARGET_PPC64) |
74d37793 AJ |
4577 | if (!ctx->sf_mode) { |
4578 | TCGv t0 = tcg_temp_new(); | |
4579 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
4580 | gen_helper_tlbie(t0); | |
4581 | tcg_temp_free(t0); | |
4582 | } else | |
d9bce9d9 | 4583 | #endif |
74d37793 | 4584 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
9a64fbe4 | 4585 | #endif |
79aceca5 FB |
4586 | } |
4587 | ||
4588 | /* tlbsync */ | |
99e300ef | 4589 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4590 | { |
9a64fbe4 | 4591 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 4592 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9a64fbe4 | 4593 | #else |
76db3ba4 | 4594 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4595 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
9fddaa0c | 4596 | return; |
9a64fbe4 FB |
4597 | } |
4598 | /* This has no effect: it should ensure that all previous | |
4599 | * tlbie have completed | |
4600 | */ | |
e06fcd75 | 4601 | gen_stop_exception(ctx); |
9a64fbe4 | 4602 | #endif |
79aceca5 FB |
4603 | } |
4604 | ||
426613db JM |
4605 | #if defined(TARGET_PPC64) |
4606 | /* slbia */ | |
99e300ef | 4607 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4608 | { |
4609 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4610 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4611 | #else |
76db3ba4 | 4612 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4613 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4614 | return; |
4615 | } | |
74d37793 | 4616 | gen_helper_slbia(); |
426613db JM |
4617 | #endif |
4618 | } | |
4619 | ||
4620 | /* slbie */ | |
99e300ef | 4621 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4622 | { |
4623 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 4624 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db | 4625 | #else |
76db3ba4 | 4626 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 4627 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
426613db JM |
4628 | return; |
4629 | } | |
74d37793 | 4630 | gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]); |
426613db JM |
4631 | #endif |
4632 | } | |
4633 | #endif | |
4634 | ||
79aceca5 FB |
4635 | /*** External control ***/ |
4636 | /* Optional: */ | |
99e300ef | 4637 | |
54623277 | 4638 | /* eciwx */ |
99e300ef | 4639 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4640 | { |
76db3ba4 | 4641 | TCGv t0; |
fa407c03 | 4642 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4643 | gen_set_access_type(ctx, ACCESS_EXT); |
4644 | t0 = tcg_temp_new(); | |
4645 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4646 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4647 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4648 | tcg_temp_free(t0); |
76a66253 JM |
4649 | } |
4650 | ||
4651 | /* ecowx */ | |
99e300ef | 4652 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4653 | { |
76db3ba4 | 4654 | TCGv t0; |
fa407c03 | 4655 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4656 | gen_set_access_type(ctx, ACCESS_EXT); |
4657 | t0 = tcg_temp_new(); | |
4658 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4659 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4660 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4661 | tcg_temp_free(t0); |
76a66253 JM |
4662 | } |
4663 | ||
4664 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4665 | |
54623277 | 4666 | /* abs - abs. */ |
99e300ef | 4667 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4668 | { |
22e0e173 AJ |
4669 | int l1 = gen_new_label(); |
4670 | int l2 = gen_new_label(); | |
4671 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4672 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4673 | tcg_gen_br(l2); | |
4674 | gen_set_label(l1); | |
4675 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4676 | gen_set_label(l2); | |
76a66253 | 4677 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4678 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4679 | } |
4680 | ||
4681 | /* abso - abso. */ | |
99e300ef | 4682 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4683 | { |
22e0e173 AJ |
4684 | int l1 = gen_new_label(); |
4685 | int l2 = gen_new_label(); | |
4686 | int l3 = gen_new_label(); | |
4687 | /* Start with XER OV disabled, the most likely case */ | |
4688 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
4689 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); | |
4690 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
4691 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
4692 | tcg_gen_br(l2); | |
4693 | gen_set_label(l1); | |
4694 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4695 | tcg_gen_br(l3); | |
4696 | gen_set_label(l2); | |
4697 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4698 | gen_set_label(l3); | |
76a66253 | 4699 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4700 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4701 | } |
4702 | ||
4703 | /* clcs */ | |
99e300ef | 4704 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4705 | { |
22e0e173 AJ |
4706 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
4707 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], t0); | |
4708 | tcg_temp_free_i32(t0); | |
c7697e1f | 4709 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4710 | } |
4711 | ||
4712 | /* div - div. */ | |
99e300ef | 4713 | static void gen_div(DisasContext *ctx) |
76a66253 | 4714 | { |
22e0e173 | 4715 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76a66253 | 4716 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4717 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4718 | } |
4719 | ||
4720 | /* divo - divo. */ | |
99e300ef | 4721 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4722 | { |
22e0e173 | 4723 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76a66253 | 4724 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4725 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4726 | } |
4727 | ||
4728 | /* divs - divs. */ | |
99e300ef | 4729 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4730 | { |
22e0e173 | 4731 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76a66253 | 4732 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4733 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4734 | } |
4735 | ||
4736 | /* divso - divso. */ | |
99e300ef | 4737 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4738 | { |
22e0e173 | 4739 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
76a66253 | 4740 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4741 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4742 | } |
4743 | ||
4744 | /* doz - doz. */ | |
99e300ef | 4745 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4746 | { |
22e0e173 AJ |
4747 | int l1 = gen_new_label(); |
4748 | int l2 = gen_new_label(); | |
4749 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4750 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4751 | tcg_gen_br(l2); | |
4752 | gen_set_label(l1); | |
4753 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4754 | gen_set_label(l2); | |
76a66253 | 4755 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4756 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4757 | } |
4758 | ||
4759 | /* dozo - dozo. */ | |
99e300ef | 4760 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4761 | { |
22e0e173 AJ |
4762 | int l1 = gen_new_label(); |
4763 | int l2 = gen_new_label(); | |
4764 | TCGv t0 = tcg_temp_new(); | |
4765 | TCGv t1 = tcg_temp_new(); | |
4766 | TCGv t2 = tcg_temp_new(); | |
4767 | /* Start with XER OV disabled, the most likely case */ | |
4768 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
4769 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); | |
4770 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4771 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4772 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4773 | tcg_gen_andc_tl(t1, t1, t2); | |
4774 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4775 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
4776 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
4777 | tcg_gen_br(l2); | |
4778 | gen_set_label(l1); | |
4779 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4780 | gen_set_label(l2); | |
4781 | tcg_temp_free(t0); | |
4782 | tcg_temp_free(t1); | |
4783 | tcg_temp_free(t2); | |
76a66253 | 4784 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4785 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4786 | } |
4787 | ||
4788 | /* dozi */ | |
99e300ef | 4789 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4790 | { |
22e0e173 AJ |
4791 | target_long simm = SIMM(ctx->opcode); |
4792 | int l1 = gen_new_label(); | |
4793 | int l2 = gen_new_label(); | |
4794 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); | |
4795 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4796 | tcg_gen_br(l2); | |
4797 | gen_set_label(l1); | |
4798 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4799 | gen_set_label(l2); | |
4800 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4801 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4802 | } |
4803 | ||
76a66253 | 4804 | /* lscbx - lscbx. */ |
99e300ef | 4805 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4806 | { |
bdb4b689 AJ |
4807 | TCGv t0 = tcg_temp_new(); |
4808 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4809 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4810 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4811 | |
76db3ba4 | 4812 | gen_addr_reg_index(ctx, t0); |
76a66253 | 4813 | /* NIP cannot be restored if the memory exception comes from an helper */ |
d9bce9d9 | 4814 | gen_update_nip(ctx, ctx->nip - 4); |
bdb4b689 AJ |
4815 | gen_helper_lscbx(t0, t0, t1, t2, t3); |
4816 | tcg_temp_free_i32(t1); | |
4817 | tcg_temp_free_i32(t2); | |
4818 | tcg_temp_free_i32(t3); | |
3d7b417e | 4819 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4820 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4821 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4822 | gen_set_Rc0(ctx, t0); |
4823 | tcg_temp_free(t0); | |
76a66253 JM |
4824 | } |
4825 | ||
4826 | /* maskg - maskg. */ | |
99e300ef | 4827 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4828 | { |
22e0e173 AJ |
4829 | int l1 = gen_new_label(); |
4830 | TCGv t0 = tcg_temp_new(); | |
4831 | TCGv t1 = tcg_temp_new(); | |
4832 | TCGv t2 = tcg_temp_new(); | |
4833 | TCGv t3 = tcg_temp_new(); | |
4834 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4835 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4836 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4837 | tcg_gen_addi_tl(t2, t0, 1); | |
4838 | tcg_gen_shr_tl(t2, t3, t2); | |
4839 | tcg_gen_shr_tl(t3, t3, t1); | |
4840 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4841 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4842 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4843 | gen_set_label(l1); | |
4844 | tcg_temp_free(t0); | |
4845 | tcg_temp_free(t1); | |
4846 | tcg_temp_free(t2); | |
4847 | tcg_temp_free(t3); | |
76a66253 | 4848 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4849 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4850 | } |
4851 | ||
4852 | /* maskir - maskir. */ | |
99e300ef | 4853 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4854 | { |
22e0e173 AJ |
4855 | TCGv t0 = tcg_temp_new(); |
4856 | TCGv t1 = tcg_temp_new(); | |
4857 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4858 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4859 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4860 | tcg_temp_free(t0); | |
4861 | tcg_temp_free(t1); | |
76a66253 | 4862 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4863 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4864 | } |
4865 | ||
4866 | /* mul - mul. */ | |
99e300ef | 4867 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4868 | { |
22e0e173 AJ |
4869 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4870 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4871 | TCGv t2 = tcg_temp_new(); | |
4872 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4873 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4874 | tcg_gen_mul_i64(t0, t0, t1); | |
4875 | tcg_gen_trunc_i64_tl(t2, t0); | |
4876 | gen_store_spr(SPR_MQ, t2); | |
4877 | tcg_gen_shri_i64(t1, t0, 32); | |
4878 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4879 | tcg_temp_free_i64(t0); | |
4880 | tcg_temp_free_i64(t1); | |
4881 | tcg_temp_free(t2); | |
76a66253 | 4882 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4883 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4884 | } |
4885 | ||
4886 | /* mulo - mulo. */ | |
99e300ef | 4887 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4888 | { |
22e0e173 AJ |
4889 | int l1 = gen_new_label(); |
4890 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
4891 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4892 | TCGv t2 = tcg_temp_new(); | |
4893 | /* Start with XER OV disabled, the most likely case */ | |
4894 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
4895 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4896 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4897 | tcg_gen_mul_i64(t0, t0, t1); | |
4898 | tcg_gen_trunc_i64_tl(t2, t0); | |
4899 | gen_store_spr(SPR_MQ, t2); | |
4900 | tcg_gen_shri_i64(t1, t0, 32); | |
4901 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4902 | tcg_gen_ext32s_i64(t1, t0); | |
4903 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
4904 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
4905 | gen_set_label(l1); | |
4906 | tcg_temp_free_i64(t0); | |
4907 | tcg_temp_free_i64(t1); | |
4908 | tcg_temp_free(t2); | |
76a66253 | 4909 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4910 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4911 | } |
4912 | ||
4913 | /* nabs - nabs. */ | |
99e300ef | 4914 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4915 | { |
22e0e173 AJ |
4916 | int l1 = gen_new_label(); |
4917 | int l2 = gen_new_label(); | |
4918 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4919 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4920 | tcg_gen_br(l2); | |
4921 | gen_set_label(l1); | |
4922 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4923 | gen_set_label(l2); | |
76a66253 | 4924 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4925 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4926 | } |
4927 | ||
4928 | /* nabso - nabso. */ | |
99e300ef | 4929 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4930 | { |
22e0e173 AJ |
4931 | int l1 = gen_new_label(); |
4932 | int l2 = gen_new_label(); | |
4933 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); | |
4934 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4935 | tcg_gen_br(l2); | |
4936 | gen_set_label(l1); | |
4937 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4938 | gen_set_label(l2); | |
4939 | /* nabs never overflows */ | |
4940 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
76a66253 | 4941 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4942 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4943 | } |
4944 | ||
4945 | /* rlmi - rlmi. */ | |
99e300ef | 4946 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4947 | { |
7487953d AJ |
4948 | uint32_t mb = MB(ctx->opcode); |
4949 | uint32_t me = ME(ctx->opcode); | |
4950 | TCGv t0 = tcg_temp_new(); | |
4951 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4952 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4953 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4954 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4955 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4956 | tcg_temp_free(t0); | |
76a66253 | 4957 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4958 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4959 | } |
4960 | ||
4961 | /* rrib - rrib. */ | |
99e300ef | 4962 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4963 | { |
7487953d AJ |
4964 | TCGv t0 = tcg_temp_new(); |
4965 | TCGv t1 = tcg_temp_new(); | |
4966 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4967 | tcg_gen_movi_tl(t1, 0x80000000); | |
4968 | tcg_gen_shr_tl(t1, t1, t0); | |
4969 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4970 | tcg_gen_and_tl(t0, t0, t1); | |
4971 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4972 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4973 | tcg_temp_free(t0); | |
4974 | tcg_temp_free(t1); | |
76a66253 | 4975 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4976 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4977 | } |
4978 | ||
4979 | /* sle - sle. */ | |
99e300ef | 4980 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4981 | { |
7487953d AJ |
4982 | TCGv t0 = tcg_temp_new(); |
4983 | TCGv t1 = tcg_temp_new(); | |
4984 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4985 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4986 | tcg_gen_subfi_tl(t1, 32, t1); | |
4987 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4988 | tcg_gen_or_tl(t1, t0, t1); | |
4989 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4990 | gen_store_spr(SPR_MQ, t1); | |
4991 | tcg_temp_free(t0); | |
4992 | tcg_temp_free(t1); | |
76a66253 | 4993 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4994 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4995 | } |
4996 | ||
4997 | /* sleq - sleq. */ | |
99e300ef | 4998 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4999 | { |
7487953d AJ |
5000 | TCGv t0 = tcg_temp_new(); |
5001 | TCGv t1 = tcg_temp_new(); | |
5002 | TCGv t2 = tcg_temp_new(); | |
5003 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5004 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
5005 | tcg_gen_shl_tl(t2, t2, t0); | |
5006 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5007 | gen_load_spr(t1, SPR_MQ); | |
5008 | gen_store_spr(SPR_MQ, t0); | |
5009 | tcg_gen_and_tl(t0, t0, t2); | |
5010 | tcg_gen_andc_tl(t1, t1, t2); | |
5011 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5012 | tcg_temp_free(t0); | |
5013 | tcg_temp_free(t1); | |
5014 | tcg_temp_free(t2); | |
76a66253 | 5015 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5016 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5017 | } |
5018 | ||
5019 | /* sliq - sliq. */ | |
99e300ef | 5020 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 5021 | { |
7487953d AJ |
5022 | int sh = SH(ctx->opcode); |
5023 | TCGv t0 = tcg_temp_new(); | |
5024 | TCGv t1 = tcg_temp_new(); | |
5025 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5026 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5027 | tcg_gen_or_tl(t1, t0, t1); | |
5028 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5029 | gen_store_spr(SPR_MQ, t1); | |
5030 | tcg_temp_free(t0); | |
5031 | tcg_temp_free(t1); | |
76a66253 | 5032 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5033 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5034 | } |
5035 | ||
5036 | /* slliq - slliq. */ | |
99e300ef | 5037 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 5038 | { |
7487953d AJ |
5039 | int sh = SH(ctx->opcode); |
5040 | TCGv t0 = tcg_temp_new(); | |
5041 | TCGv t1 = tcg_temp_new(); | |
5042 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5043 | gen_load_spr(t1, SPR_MQ); | |
5044 | gen_store_spr(SPR_MQ, t0); | |
5045 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
5046 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
5047 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5048 | tcg_temp_free(t0); | |
5049 | tcg_temp_free(t1); | |
76a66253 | 5050 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5051 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5052 | } |
5053 | ||
5054 | /* sllq - sllq. */ | |
99e300ef | 5055 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 5056 | { |
7487953d AJ |
5057 | int l1 = gen_new_label(); |
5058 | int l2 = gen_new_label(); | |
5059 | TCGv t0 = tcg_temp_local_new(); | |
5060 | TCGv t1 = tcg_temp_local_new(); | |
5061 | TCGv t2 = tcg_temp_local_new(); | |
5062 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5063 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5064 | tcg_gen_shl_tl(t1, t1, t2); | |
5065 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5066 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5067 | gen_load_spr(t0, SPR_MQ); | |
5068 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5069 | tcg_gen_br(l2); | |
5070 | gen_set_label(l1); | |
5071 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5072 | gen_load_spr(t2, SPR_MQ); | |
5073 | tcg_gen_andc_tl(t1, t2, t1); | |
5074 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5075 | gen_set_label(l2); | |
5076 | tcg_temp_free(t0); | |
5077 | tcg_temp_free(t1); | |
5078 | tcg_temp_free(t2); | |
76a66253 | 5079 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5080 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5081 | } |
5082 | ||
5083 | /* slq - slq. */ | |
99e300ef | 5084 | static void gen_slq(DisasContext *ctx) |
76a66253 | 5085 | { |
7487953d AJ |
5086 | int l1 = gen_new_label(); |
5087 | TCGv t0 = tcg_temp_new(); | |
5088 | TCGv t1 = tcg_temp_new(); | |
5089 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5090 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5091 | tcg_gen_subfi_tl(t1, 32, t1); | |
5092 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5093 | tcg_gen_or_tl(t1, t0, t1); | |
5094 | gen_store_spr(SPR_MQ, t1); | |
5095 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5096 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5097 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5098 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5099 | gen_set_label(l1); | |
5100 | tcg_temp_free(t0); | |
5101 | tcg_temp_free(t1); | |
76a66253 | 5102 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5103 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5104 | } |
5105 | ||
d9bce9d9 | 5106 | /* sraiq - sraiq. */ |
99e300ef | 5107 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 5108 | { |
7487953d AJ |
5109 | int sh = SH(ctx->opcode); |
5110 | int l1 = gen_new_label(); | |
5111 | TCGv t0 = tcg_temp_new(); | |
5112 | TCGv t1 = tcg_temp_new(); | |
5113 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5114 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5115 | tcg_gen_or_tl(t0, t0, t1); | |
5116 | gen_store_spr(SPR_MQ, t0); | |
5117 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
5118 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
5119 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
5120 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA)); | |
5121 | gen_set_label(l1); | |
5122 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
5123 | tcg_temp_free(t0); | |
5124 | tcg_temp_free(t1); | |
76a66253 | 5125 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5126 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5127 | } |
5128 | ||
5129 | /* sraq - sraq. */ | |
99e300ef | 5130 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 5131 | { |
7487953d AJ |
5132 | int l1 = gen_new_label(); |
5133 | int l2 = gen_new_label(); | |
5134 | TCGv t0 = tcg_temp_new(); | |
5135 | TCGv t1 = tcg_temp_local_new(); | |
5136 | TCGv t2 = tcg_temp_local_new(); | |
5137 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5138 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5139 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
5140 | tcg_gen_subfi_tl(t2, 32, t2); | |
5141 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
5142 | tcg_gen_or_tl(t0, t0, t2); | |
5143 | gen_store_spr(SPR_MQ, t0); | |
5144 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5145 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
5146 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
5147 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
5148 | gen_set_label(l1); | |
5149 | tcg_temp_free(t0); | |
5150 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
5151 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA)); | |
5152 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
5153 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
5154 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_CA)); | |
5155 | gen_set_label(l2); | |
5156 | tcg_temp_free(t1); | |
5157 | tcg_temp_free(t2); | |
76a66253 | 5158 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5159 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5160 | } |
5161 | ||
5162 | /* sre - sre. */ | |
99e300ef | 5163 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5164 | { |
7487953d AJ |
5165 | TCGv t0 = tcg_temp_new(); |
5166 | TCGv t1 = tcg_temp_new(); | |
5167 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5168 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5169 | tcg_gen_subfi_tl(t1, 32, t1); | |
5170 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5171 | tcg_gen_or_tl(t1, t0, t1); | |
5172 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5173 | gen_store_spr(SPR_MQ, t1); | |
5174 | tcg_temp_free(t0); | |
5175 | tcg_temp_free(t1); | |
76a66253 | 5176 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5177 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5178 | } |
5179 | ||
5180 | /* srea - srea. */ | |
99e300ef | 5181 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5182 | { |
7487953d AJ |
5183 | TCGv t0 = tcg_temp_new(); |
5184 | TCGv t1 = tcg_temp_new(); | |
5185 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5186 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5187 | gen_store_spr(SPR_MQ, t0); | |
5188 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5189 | tcg_temp_free(t0); | |
5190 | tcg_temp_free(t1); | |
76a66253 | 5191 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5192 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5193 | } |
5194 | ||
5195 | /* sreq */ | |
99e300ef | 5196 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5197 | { |
7487953d AJ |
5198 | TCGv t0 = tcg_temp_new(); |
5199 | TCGv t1 = tcg_temp_new(); | |
5200 | TCGv t2 = tcg_temp_new(); | |
5201 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5202 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5203 | tcg_gen_shr_tl(t1, t1, t0); | |
5204 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5205 | gen_load_spr(t2, SPR_MQ); | |
5206 | gen_store_spr(SPR_MQ, t0); | |
5207 | tcg_gen_and_tl(t0, t0, t1); | |
5208 | tcg_gen_andc_tl(t2, t2, t1); | |
5209 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5210 | tcg_temp_free(t0); | |
5211 | tcg_temp_free(t1); | |
5212 | tcg_temp_free(t2); | |
76a66253 | 5213 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5214 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5215 | } |
5216 | ||
5217 | /* sriq */ | |
99e300ef | 5218 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5219 | { |
7487953d AJ |
5220 | int sh = SH(ctx->opcode); |
5221 | TCGv t0 = tcg_temp_new(); | |
5222 | TCGv t1 = tcg_temp_new(); | |
5223 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5224 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5225 | tcg_gen_or_tl(t1, t0, t1); | |
5226 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5227 | gen_store_spr(SPR_MQ, t1); | |
5228 | tcg_temp_free(t0); | |
5229 | tcg_temp_free(t1); | |
76a66253 | 5230 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5231 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5232 | } |
5233 | ||
5234 | /* srliq */ | |
99e300ef | 5235 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5236 | { |
7487953d AJ |
5237 | int sh = SH(ctx->opcode); |
5238 | TCGv t0 = tcg_temp_new(); | |
5239 | TCGv t1 = tcg_temp_new(); | |
5240 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5241 | gen_load_spr(t1, SPR_MQ); | |
5242 | gen_store_spr(SPR_MQ, t0); | |
5243 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5244 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5245 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5246 | tcg_temp_free(t0); | |
5247 | tcg_temp_free(t1); | |
76a66253 | 5248 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5249 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5250 | } |
5251 | ||
5252 | /* srlq */ | |
99e300ef | 5253 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5254 | { |
7487953d AJ |
5255 | int l1 = gen_new_label(); |
5256 | int l2 = gen_new_label(); | |
5257 | TCGv t0 = tcg_temp_local_new(); | |
5258 | TCGv t1 = tcg_temp_local_new(); | |
5259 | TCGv t2 = tcg_temp_local_new(); | |
5260 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5261 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5262 | tcg_gen_shr_tl(t2, t1, t2); | |
5263 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5264 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5265 | gen_load_spr(t0, SPR_MQ); | |
5266 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5267 | tcg_gen_br(l2); | |
5268 | gen_set_label(l1); | |
5269 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5270 | tcg_gen_and_tl(t0, t0, t2); | |
5271 | gen_load_spr(t1, SPR_MQ); | |
5272 | tcg_gen_andc_tl(t1, t1, t2); | |
5273 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5274 | gen_set_label(l2); | |
5275 | tcg_temp_free(t0); | |
5276 | tcg_temp_free(t1); | |
5277 | tcg_temp_free(t2); | |
76a66253 | 5278 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5279 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5280 | } |
5281 | ||
5282 | /* srq */ | |
99e300ef | 5283 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5284 | { |
7487953d AJ |
5285 | int l1 = gen_new_label(); |
5286 | TCGv t0 = tcg_temp_new(); | |
5287 | TCGv t1 = tcg_temp_new(); | |
5288 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5289 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5290 | tcg_gen_subfi_tl(t1, 32, t1); | |
5291 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5292 | tcg_gen_or_tl(t1, t0, t1); | |
5293 | gen_store_spr(SPR_MQ, t1); | |
5294 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5295 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5296 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5297 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5298 | gen_set_label(l1); | |
5299 | tcg_temp_free(t0); | |
5300 | tcg_temp_free(t1); | |
76a66253 | 5301 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5302 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5303 | } |
5304 | ||
5305 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5306 | |
54623277 | 5307 | /* dsa */ |
99e300ef | 5308 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5309 | { |
5310 | /* XXX: TODO */ | |
e06fcd75 | 5311 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5312 | } |
5313 | ||
5314 | /* esa */ | |
99e300ef | 5315 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5316 | { |
5317 | /* XXX: TODO */ | |
e06fcd75 | 5318 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5319 | } |
5320 | ||
5321 | /* mfrom */ | |
99e300ef | 5322 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5323 | { |
5324 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5325 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5326 | #else |
76db3ba4 | 5327 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5328 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5329 | return; |
5330 | } | |
cf02a65c | 5331 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5332 | #endif |
5333 | } | |
5334 | ||
5335 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5336 | |
54623277 | 5337 | /* tlbld */ |
e8eaa2c0 | 5338 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5339 | { |
5340 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5341 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5342 | #else |
76db3ba4 | 5343 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5344 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5345 | return; |
5346 | } | |
74d37793 | 5347 | gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5348 | #endif |
5349 | } | |
5350 | ||
5351 | /* tlbli */ | |
e8eaa2c0 | 5352 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5353 | { |
5354 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5355 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5356 | #else |
76db3ba4 | 5357 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5358 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5359 | return; |
5360 | } | |
74d37793 | 5361 | gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
76a66253 JM |
5362 | #endif |
5363 | } | |
5364 | ||
7dbe11ac | 5365 | /* 74xx TLB management */ |
e8eaa2c0 | 5366 | |
54623277 | 5367 | /* tlbld */ |
e8eaa2c0 | 5368 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5369 | { |
5370 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5371 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5372 | #else |
76db3ba4 | 5373 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5374 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5375 | return; |
5376 | } | |
74d37793 | 5377 | gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5378 | #endif |
5379 | } | |
5380 | ||
5381 | /* tlbli */ | |
e8eaa2c0 | 5382 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5383 | { |
5384 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5385 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac | 5386 | #else |
76db3ba4 | 5387 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5388 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
7dbe11ac JM |
5389 | return; |
5390 | } | |
74d37793 | 5391 | gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]); |
7dbe11ac JM |
5392 | #endif |
5393 | } | |
5394 | ||
76a66253 | 5395 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5396 | |
54623277 | 5397 | /* clf */ |
99e300ef | 5398 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5399 | { |
5400 | /* Cache line flush: implemented as no-op */ | |
5401 | } | |
5402 | ||
5403 | /* cli */ | |
99e300ef | 5404 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5405 | { |
7f75ffd3 | 5406 | /* Cache line invalidate: privileged and treated as no-op */ |
76a66253 | 5407 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 5408 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5409 | #else |
76db3ba4 | 5410 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5411 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5412 | return; |
5413 | } | |
5414 | #endif | |
5415 | } | |
5416 | ||
5417 | /* dclst */ | |
99e300ef | 5418 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5419 | { |
5420 | /* Data cache line store: treated as no-op */ | |
5421 | } | |
5422 | ||
99e300ef | 5423 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5424 | { |
5425 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5426 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5427 | #else |
74d37793 AJ |
5428 | int ra = rA(ctx->opcode); |
5429 | int rd = rD(ctx->opcode); | |
5430 | TCGv t0; | |
76db3ba4 | 5431 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5432 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5433 | return; |
5434 | } | |
74d37793 | 5435 | t0 = tcg_temp_new(); |
76db3ba4 | 5436 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5437 | tcg_gen_shri_tl(t0, t0, 28); |
5438 | tcg_gen_andi_tl(t0, t0, 0xF); | |
5439 | gen_helper_load_sr(cpu_gpr[rd], t0); | |
5440 | tcg_temp_free(t0); | |
76a66253 | 5441 | if (ra != 0 && ra != rd) |
74d37793 | 5442 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
76a66253 JM |
5443 | #endif |
5444 | } | |
5445 | ||
99e300ef | 5446 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5447 | { |
5448 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5449 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5450 | #else |
22e0e173 | 5451 | TCGv t0; |
76db3ba4 | 5452 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5453 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5454 | return; |
5455 | } | |
22e0e173 | 5456 | t0 = tcg_temp_new(); |
76db3ba4 | 5457 | gen_addr_reg_index(ctx, t0); |
22e0e173 AJ |
5458 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0); |
5459 | tcg_temp_free(t0); | |
76a66253 JM |
5460 | #endif |
5461 | } | |
5462 | ||
99e300ef | 5463 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5464 | { |
5465 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5466 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5467 | #else |
76db3ba4 | 5468 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5469 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5470 | return; |
5471 | } | |
d72a19f7 | 5472 | gen_helper_rfsvc(); |
e06fcd75 | 5473 | gen_sync_exception(ctx); |
76a66253 JM |
5474 | #endif |
5475 | } | |
5476 | ||
5477 | /* svc is not implemented for now */ | |
5478 | ||
5479 | /* POWER2 specific instructions */ | |
5480 | /* Quad manipulation (load/store two floats at a time) */ | |
76a66253 JM |
5481 | |
5482 | /* lfq */ | |
99e300ef | 5483 | static void gen_lfq(DisasContext *ctx) |
76a66253 | 5484 | { |
01a4afeb | 5485 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5486 | TCGv t0; |
5487 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5488 | t0 = tcg_temp_new(); | |
5489 | gen_addr_imm_index(ctx, t0, 0); | |
5490 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5491 | gen_addr_add(ctx, t0, t0, 8); | |
5492 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5493 | tcg_temp_free(t0); |
76a66253 JM |
5494 | } |
5495 | ||
5496 | /* lfqu */ | |
99e300ef | 5497 | static void gen_lfqu(DisasContext *ctx) |
76a66253 JM |
5498 | { |
5499 | int ra = rA(ctx->opcode); | |
01a4afeb | 5500 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5501 | TCGv t0, t1; |
5502 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5503 | t0 = tcg_temp_new(); | |
5504 | t1 = tcg_temp_new(); | |
5505 | gen_addr_imm_index(ctx, t0, 0); | |
5506 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5507 | gen_addr_add(ctx, t1, t0, 8); | |
5508 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
76a66253 | 5509 | if (ra != 0) |
01a4afeb AJ |
5510 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5511 | tcg_temp_free(t0); | |
5512 | tcg_temp_free(t1); | |
76a66253 JM |
5513 | } |
5514 | ||
5515 | /* lfqux */ | |
99e300ef | 5516 | static void gen_lfqux(DisasContext *ctx) |
76a66253 JM |
5517 | { |
5518 | int ra = rA(ctx->opcode); | |
01a4afeb | 5519 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5520 | gen_set_access_type(ctx, ACCESS_FLOAT); |
5521 | TCGv t0, t1; | |
5522 | t0 = tcg_temp_new(); | |
5523 | gen_addr_reg_index(ctx, t0); | |
5524 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5525 | t1 = tcg_temp_new(); | |
5526 | gen_addr_add(ctx, t1, t0, 8); | |
5527 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5528 | tcg_temp_free(t1); | |
76a66253 | 5529 | if (ra != 0) |
01a4afeb AJ |
5530 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5531 | tcg_temp_free(t0); | |
76a66253 JM |
5532 | } |
5533 | ||
5534 | /* lfqx */ | |
99e300ef | 5535 | static void gen_lfqx(DisasContext *ctx) |
76a66253 | 5536 | { |
01a4afeb | 5537 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5538 | TCGv t0; |
5539 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5540 | t0 = tcg_temp_new(); | |
5541 | gen_addr_reg_index(ctx, t0); | |
5542 | gen_qemu_ld64(ctx, cpu_fpr[rd], t0); | |
5543 | gen_addr_add(ctx, t0, t0, 8); | |
5544 | gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5545 | tcg_temp_free(t0); |
76a66253 JM |
5546 | } |
5547 | ||
5548 | /* stfq */ | |
99e300ef | 5549 | static void gen_stfq(DisasContext *ctx) |
76a66253 | 5550 | { |
01a4afeb | 5551 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5552 | TCGv t0; |
5553 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5554 | t0 = tcg_temp_new(); | |
5555 | gen_addr_imm_index(ctx, t0, 0); | |
5556 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5557 | gen_addr_add(ctx, t0, t0, 8); | |
5558 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5559 | tcg_temp_free(t0); |
76a66253 JM |
5560 | } |
5561 | ||
5562 | /* stfqu */ | |
99e300ef | 5563 | static void gen_stfqu(DisasContext *ctx) |
76a66253 JM |
5564 | { |
5565 | int ra = rA(ctx->opcode); | |
01a4afeb | 5566 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5567 | TCGv t0, t1; |
5568 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5569 | t0 = tcg_temp_new(); | |
5570 | gen_addr_imm_index(ctx, t0, 0); | |
5571 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5572 | t1 = tcg_temp_new(); | |
5573 | gen_addr_add(ctx, t1, t0, 8); | |
5574 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5575 | tcg_temp_free(t1); | |
76a66253 | 5576 | if (ra != 0) |
01a4afeb AJ |
5577 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5578 | tcg_temp_free(t0); | |
76a66253 JM |
5579 | } |
5580 | ||
5581 | /* stfqux */ | |
99e300ef | 5582 | static void gen_stfqux(DisasContext *ctx) |
76a66253 JM |
5583 | { |
5584 | int ra = rA(ctx->opcode); | |
01a4afeb | 5585 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5586 | TCGv t0, t1; |
5587 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5588 | t0 = tcg_temp_new(); | |
5589 | gen_addr_reg_index(ctx, t0); | |
5590 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5591 | t1 = tcg_temp_new(); | |
5592 | gen_addr_add(ctx, t1, t0, 8); | |
5593 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1); | |
5594 | tcg_temp_free(t1); | |
76a66253 | 5595 | if (ra != 0) |
01a4afeb AJ |
5596 | tcg_gen_mov_tl(cpu_gpr[ra], t0); |
5597 | tcg_temp_free(t0); | |
76a66253 JM |
5598 | } |
5599 | ||
5600 | /* stfqx */ | |
99e300ef | 5601 | static void gen_stfqx(DisasContext *ctx) |
76a66253 | 5602 | { |
01a4afeb | 5603 | int rd = rD(ctx->opcode); |
76db3ba4 AJ |
5604 | TCGv t0; |
5605 | gen_set_access_type(ctx, ACCESS_FLOAT); | |
5606 | t0 = tcg_temp_new(); | |
5607 | gen_addr_reg_index(ctx, t0); | |
5608 | gen_qemu_st64(ctx, cpu_fpr[rd], t0); | |
5609 | gen_addr_add(ctx, t0, t0, 8); | |
5610 | gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0); | |
01a4afeb | 5611 | tcg_temp_free(t0); |
76a66253 JM |
5612 | } |
5613 | ||
5614 | /* BookE specific instructions */ | |
99e300ef | 5615 | |
54623277 | 5616 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5617 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5618 | { |
5619 | /* XXX: TODO */ | |
e06fcd75 | 5620 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5621 | } |
5622 | ||
2662a059 | 5623 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5624 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5625 | { |
5626 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5627 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5628 | #else |
74d37793 | 5629 | TCGv t0; |
76db3ba4 | 5630 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5631 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5632 | return; |
5633 | } | |
ec72e276 | 5634 | t0 = tcg_temp_new(); |
76db3ba4 | 5635 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5636 | gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); |
5637 | tcg_temp_free(t0); | |
76a66253 JM |
5638 | #endif |
5639 | } | |
5640 | ||
5641 | /* All 405 MAC instructions are translated here */ | |
b068d6a7 JM |
5642 | static always_inline void gen_405_mulladd_insn (DisasContext *ctx, |
5643 | int opc2, int opc3, | |
5644 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5645 | { |
182608d4 AJ |
5646 | TCGv t0, t1; |
5647 | ||
a7812ae4 PB |
5648 | t0 = tcg_temp_local_new(); |
5649 | t1 = tcg_temp_local_new(); | |
182608d4 | 5650 | |
76a66253 JM |
5651 | switch (opc3 & 0x0D) { |
5652 | case 0x05: | |
5653 | /* macchw - macchw. - macchwo - macchwo. */ | |
5654 | /* macchws - macchws. - macchwso - macchwso. */ | |
5655 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5656 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5657 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5658 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5659 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5660 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5661 | break; |
5662 | case 0x04: | |
5663 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5664 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5665 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5666 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5667 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5668 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5669 | break; |
5670 | case 0x01: | |
5671 | /* machhw - machhw. - machhwo - machhwo. */ | |
5672 | /* machhws - machhws. - machhwso - machhwso. */ | |
5673 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5674 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5675 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5676 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5677 | tcg_gen_ext16s_tl(t0, t0); | |
5678 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5679 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5680 | break; |
5681 | case 0x00: | |
5682 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5683 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5684 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5685 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5686 | tcg_gen_ext16u_tl(t0, t0); | |
5687 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5688 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5689 | break; |
5690 | case 0x0D: | |
5691 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5692 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5693 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5694 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5695 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5696 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5697 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5698 | break; |
5699 | case 0x0C: | |
5700 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5701 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5702 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5703 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5704 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5705 | break; |
5706 | } | |
76a66253 | 5707 | if (opc2 & 0x04) { |
182608d4 AJ |
5708 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5709 | tcg_gen_mul_tl(t1, t0, t1); | |
5710 | if (opc2 & 0x02) { | |
5711 | /* nmultiply-and-accumulate (0x0E) */ | |
5712 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5713 | } else { | |
5714 | /* multiply-and-accumulate (0x0C) */ | |
5715 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5716 | } | |
5717 | ||
5718 | if (opc3 & 0x12) { | |
5719 | /* Check overflow and/or saturate */ | |
5720 | int l1 = gen_new_label(); | |
5721 | ||
5722 | if (opc3 & 0x10) { | |
5723 | /* Start with XER OV disabled, the most likely case */ | |
5724 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV)); | |
5725 | } | |
5726 | if (opc3 & 0x01) { | |
5727 | /* Signed */ | |
5728 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5729 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5730 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5731 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5732 | if (opc3 & 0x02) { |
182608d4 AJ |
5733 | /* Saturate */ |
5734 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5735 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5736 | } | |
5737 | } else { | |
5738 | /* Unsigned */ | |
5739 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5740 | if (opc3 & 0x02) { |
182608d4 AJ |
5741 | /* Saturate */ |
5742 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5743 | } | |
5744 | } | |
5745 | if (opc3 & 0x10) { | |
5746 | /* Check overflow */ | |
5747 | tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO)); | |
5748 | } | |
5749 | gen_set_label(l1); | |
5750 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5751 | } | |
5752 | } else { | |
5753 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5754 | } |
182608d4 AJ |
5755 | tcg_temp_free(t0); |
5756 | tcg_temp_free(t1); | |
76a66253 JM |
5757 | if (unlikely(Rc) != 0) { |
5758 | /* Update Rc0 */ | |
182608d4 | 5759 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5760 | } |
5761 | } | |
5762 | ||
a750fc0b | 5763 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef BS |
5764 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC); \ |
5765 | \ | |
5766 | static void glue(gen_, name)(DisasContext *ctx) \ | |
76a66253 JM |
5767 | { \ |
5768 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5769 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5770 | } | |
5771 | ||
5772 | /* macchw - macchw. */ | |
a750fc0b | 5773 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5774 | /* macchwo - macchwo. */ |
a750fc0b | 5775 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5776 | /* macchws - macchws. */ |
a750fc0b | 5777 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5778 | /* macchwso - macchwso. */ |
a750fc0b | 5779 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5780 | /* macchwsu - macchwsu. */ |
a750fc0b | 5781 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5782 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5783 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5784 | /* macchwu - macchwu. */ |
a750fc0b | 5785 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5786 | /* macchwuo - macchwuo. */ |
a750fc0b | 5787 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5788 | /* machhw - machhw. */ |
a750fc0b | 5789 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5790 | /* machhwo - machhwo. */ |
a750fc0b | 5791 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5792 | /* machhws - machhws. */ |
a750fc0b | 5793 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5794 | /* machhwso - machhwso. */ |
a750fc0b | 5795 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5796 | /* machhwsu - machhwsu. */ |
a750fc0b | 5797 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5798 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5799 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5800 | /* machhwu - machhwu. */ |
a750fc0b | 5801 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5802 | /* machhwuo - machhwuo. */ |
a750fc0b | 5803 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5804 | /* maclhw - maclhw. */ |
a750fc0b | 5805 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5806 | /* maclhwo - maclhwo. */ |
a750fc0b | 5807 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5808 | /* maclhws - maclhws. */ |
a750fc0b | 5809 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5810 | /* maclhwso - maclhwso. */ |
a750fc0b | 5811 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5812 | /* maclhwu - maclhwu. */ |
a750fc0b | 5813 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5814 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5815 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5816 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5817 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5818 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5819 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5820 | /* nmacchw - nmacchw. */ |
a750fc0b | 5821 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5822 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5823 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5824 | /* nmacchws - nmacchws. */ |
a750fc0b | 5825 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5826 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5827 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5828 | /* nmachhw - nmachhw. */ |
a750fc0b | 5829 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5830 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5831 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5832 | /* nmachhws - nmachhws. */ |
a750fc0b | 5833 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5834 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5835 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5836 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5837 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5838 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5839 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5840 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5841 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5842 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5843 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5844 | |
5845 | /* mulchw - mulchw. */ | |
a750fc0b | 5846 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5847 | /* mulchwu - mulchwu. */ |
a750fc0b | 5848 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5849 | /* mulhhw - mulhhw. */ |
a750fc0b | 5850 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5851 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5852 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5853 | /* mullhw - mullhw. */ |
a750fc0b | 5854 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5855 | /* mullhwu - mullhwu. */ |
a750fc0b | 5856 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5857 | |
5858 | /* mfdcr */ | |
99e300ef | 5859 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5860 | { |
5861 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5862 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5863 | #else |
06dca6a7 | 5864 | TCGv dcrn; |
76db3ba4 | 5865 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5866 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5867 | return; |
5868 | } | |
06dca6a7 AJ |
5869 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5870 | gen_update_nip(ctx, ctx->nip - 4); | |
5871 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
5872 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], dcrn); | |
5873 | tcg_temp_free(dcrn); | |
76a66253 JM |
5874 | #endif |
5875 | } | |
5876 | ||
5877 | /* mtdcr */ | |
99e300ef | 5878 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5879 | { |
5880 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5881 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 5882 | #else |
06dca6a7 | 5883 | TCGv dcrn; |
76db3ba4 | 5884 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5885 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 JM |
5886 | return; |
5887 | } | |
06dca6a7 AJ |
5888 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5889 | gen_update_nip(ctx, ctx->nip - 4); | |
5890 | dcrn = tcg_const_tl(SPR(ctx->opcode)); | |
5891 | gen_helper_store_dcr(dcrn, cpu_gpr[rS(ctx->opcode)]); | |
5892 | tcg_temp_free(dcrn); | |
a42bd6cc JM |
5893 | #endif |
5894 | } | |
5895 | ||
5896 | /* mfdcrx */ | |
2662a059 | 5897 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5898 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5899 | { |
5900 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5901 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5902 | #else |
76db3ba4 | 5903 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5904 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5905 | return; |
5906 | } | |
06dca6a7 AJ |
5907 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5908 | gen_update_nip(ctx, ctx->nip - 4); | |
5909 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5910 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
a42bd6cc JM |
5911 | #endif |
5912 | } | |
5913 | ||
5914 | /* mtdcrx */ | |
2662a059 | 5915 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5916 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5917 | { |
5918 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5919 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc | 5920 | #else |
76db3ba4 | 5921 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5922 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
a42bd6cc JM |
5923 | return; |
5924 | } | |
06dca6a7 AJ |
5925 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5926 | gen_update_nip(ctx, ctx->nip - 4); | |
5927 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5928 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
76a66253 JM |
5929 | #endif |
5930 | } | |
5931 | ||
a750fc0b | 5932 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5933 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5934 | { |
06dca6a7 AJ |
5935 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5936 | gen_update_nip(ctx, ctx->nip - 4); | |
5937 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5938 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5939 | } | |
5940 | ||
5941 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5942 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5943 | { |
06dca6a7 AJ |
5944 | /* NIP cannot be restored if the memory exception comes from an helper */ |
5945 | gen_update_nip(ctx, ctx->nip - 4); | |
5946 | gen_helper_store_dcr(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b JM |
5947 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5948 | } | |
5949 | ||
76a66253 | 5950 | /* dccci */ |
99e300ef | 5951 | static void gen_dccci(DisasContext *ctx) |
76a66253 JM |
5952 | { |
5953 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5954 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5955 | #else |
76db3ba4 | 5956 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5957 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5958 | return; |
5959 | } | |
5960 | /* interpreted as no-op */ | |
5961 | #endif | |
5962 | } | |
5963 | ||
5964 | /* dcread */ | |
99e300ef | 5965 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5966 | { |
5967 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5968 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 5969 | #else |
b61f2753 | 5970 | TCGv EA, val; |
76db3ba4 | 5971 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 5972 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
5973 | return; |
5974 | } | |
76db3ba4 | 5975 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5976 | EA = tcg_temp_new(); |
76db3ba4 | 5977 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5978 | val = tcg_temp_new(); |
76db3ba4 | 5979 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5980 | tcg_temp_free(val); |
5981 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5982 | tcg_temp_free(EA); | |
76a66253 JM |
5983 | #endif |
5984 | } | |
5985 | ||
5986 | /* icbt */ | |
e8eaa2c0 | 5987 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5988 | { |
5989 | /* interpreted as no-op */ | |
5990 | /* XXX: specification say this is treated as a load by the MMU | |
5991 | * but does not generate any exception | |
5992 | */ | |
5993 | } | |
5994 | ||
5995 | /* iccci */ | |
99e300ef | 5996 | static void gen_iccci(DisasContext *ctx) |
76a66253 JM |
5997 | { |
5998 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 5999 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6000 | #else |
76db3ba4 | 6001 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6002 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6003 | return; |
6004 | } | |
6005 | /* interpreted as no-op */ | |
6006 | #endif | |
6007 | } | |
6008 | ||
6009 | /* icread */ | |
99e300ef | 6010 | static void gen_icread(DisasContext *ctx) |
76a66253 JM |
6011 | { |
6012 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6013 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6014 | #else |
76db3ba4 | 6015 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6016 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6017 | return; |
6018 | } | |
6019 | /* interpreted as no-op */ | |
6020 | #endif | |
6021 | } | |
6022 | ||
76db3ba4 | 6023 | /* rfci (mem_idx only) */ |
e8eaa2c0 | 6024 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
6025 | { |
6026 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6027 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6028 | #else |
76db3ba4 | 6029 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6030 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6031 | return; |
6032 | } | |
6033 | /* Restore CPU state */ | |
d72a19f7 | 6034 | gen_helper_40x_rfci(); |
e06fcd75 | 6035 | gen_sync_exception(ctx); |
a42bd6cc JM |
6036 | #endif |
6037 | } | |
6038 | ||
99e300ef | 6039 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
6040 | { |
6041 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6042 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6043 | #else |
76db3ba4 | 6044 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6045 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6046 | return; |
6047 | } | |
6048 | /* Restore CPU state */ | |
d72a19f7 | 6049 | gen_helper_rfci(); |
e06fcd75 | 6050 | gen_sync_exception(ctx); |
a42bd6cc JM |
6051 | #endif |
6052 | } | |
6053 | ||
6054 | /* BookE specific */ | |
99e300ef | 6055 | |
54623277 | 6056 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6057 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
6058 | { |
6059 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6060 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6061 | #else |
76db3ba4 | 6062 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6063 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6064 | return; |
6065 | } | |
6066 | /* Restore CPU state */ | |
d72a19f7 | 6067 | gen_helper_rfdi(); |
e06fcd75 | 6068 | gen_sync_exception(ctx); |
76a66253 JM |
6069 | #endif |
6070 | } | |
6071 | ||
2662a059 | 6072 | /* XXX: not implemented on 440 ? */ |
99e300ef | 6073 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
6074 | { |
6075 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6076 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc | 6077 | #else |
76db3ba4 | 6078 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6079 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
a42bd6cc JM |
6080 | return; |
6081 | } | |
6082 | /* Restore CPU state */ | |
d72a19f7 | 6083 | gen_helper_rfmci(); |
e06fcd75 | 6084 | gen_sync_exception(ctx); |
a42bd6cc JM |
6085 | #endif |
6086 | } | |
5eb7995e | 6087 | |
d9bce9d9 | 6088 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 6089 | |
54623277 | 6090 | /* tlbre */ |
e8eaa2c0 | 6091 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
6092 | { |
6093 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6094 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6095 | #else |
76db3ba4 | 6096 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6097 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6098 | return; |
6099 | } | |
6100 | switch (rB(ctx->opcode)) { | |
6101 | case 0: | |
74d37793 | 6102 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
6103 | break; |
6104 | case 1: | |
74d37793 | 6105 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
6106 | break; |
6107 | default: | |
e06fcd75 | 6108 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6109 | break; |
9a64fbe4 | 6110 | } |
76a66253 JM |
6111 | #endif |
6112 | } | |
6113 | ||
d9bce9d9 | 6114 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 6115 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
6116 | { |
6117 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6118 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6119 | #else |
74d37793 | 6120 | TCGv t0; |
76db3ba4 | 6121 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6122 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6123 | return; |
6124 | } | |
74d37793 | 6125 | t0 = tcg_temp_new(); |
76db3ba4 | 6126 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
6127 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
6128 | tcg_temp_free(t0); | |
6129 | if (Rc(ctx->opcode)) { | |
6130 | int l1 = gen_new_label(); | |
6131 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
6132 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
6133 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
6134 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); | |
6135 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6136 | gen_set_label(l1); | |
6137 | } | |
76a66253 | 6138 | #endif |
79aceca5 FB |
6139 | } |
6140 | ||
76a66253 | 6141 | /* tlbwe */ |
e8eaa2c0 | 6142 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 6143 | { |
76a66253 | 6144 | #if defined(CONFIG_USER_ONLY) |
e06fcd75 | 6145 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6146 | #else |
76db3ba4 | 6147 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6148 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6149 | return; |
6150 | } | |
6151 | switch (rB(ctx->opcode)) { | |
6152 | case 0: | |
74d37793 | 6153 | gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
76a66253 JM |
6154 | break; |
6155 | case 1: | |
74d37793 | 6156 | gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
76a66253 JM |
6157 | break; |
6158 | default: | |
e06fcd75 | 6159 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 6160 | break; |
9a64fbe4 | 6161 | } |
76a66253 JM |
6162 | #endif |
6163 | } | |
6164 | ||
a4bb6c3e | 6165 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 6166 | |
54623277 | 6167 | /* tlbre */ |
e8eaa2c0 | 6168 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
6169 | { |
6170 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6171 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6172 | #else |
76db3ba4 | 6173 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6174 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6175 | return; |
6176 | } | |
6177 | switch (rB(ctx->opcode)) { | |
6178 | case 0: | |
5eb7995e | 6179 | case 1: |
5eb7995e | 6180 | case 2: |
74d37793 AJ |
6181 | { |
6182 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
6183 | gen_helper_440_tlbwe(t0, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
6184 | tcg_temp_free_i32(t0); | |
6185 | } | |
5eb7995e JM |
6186 | break; |
6187 | default: | |
e06fcd75 | 6188 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6189 | break; |
6190 | } | |
6191 | #endif | |
6192 | } | |
6193 | ||
6194 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 6195 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
6196 | { |
6197 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6198 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6199 | #else |
74d37793 | 6200 | TCGv t0; |
76db3ba4 | 6201 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6202 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6203 | return; |
6204 | } | |
74d37793 | 6205 | t0 = tcg_temp_new(); |
76db3ba4 | 6206 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
6207 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); |
6208 | tcg_temp_free(t0); | |
6209 | if (Rc(ctx->opcode)) { | |
6210 | int l1 = gen_new_label(); | |
6211 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_xer); | |
6212 | tcg_gen_shri_i32(cpu_crf[0], cpu_crf[0], XER_SO); | |
6213 | tcg_gen_andi_i32(cpu_crf[0], cpu_crf[0], 1); | |
6214 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); | |
6215 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
6216 | gen_set_label(l1); | |
6217 | } | |
5eb7995e JM |
6218 | #endif |
6219 | } | |
6220 | ||
6221 | /* tlbwe */ | |
e8eaa2c0 | 6222 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
6223 | { |
6224 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6225 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e | 6226 | #else |
76db3ba4 | 6227 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6228 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
5eb7995e JM |
6229 | return; |
6230 | } | |
6231 | switch (rB(ctx->opcode)) { | |
6232 | case 0: | |
5eb7995e | 6233 | case 1: |
5eb7995e | 6234 | case 2: |
74d37793 AJ |
6235 | { |
6236 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
6237 | gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
6238 | tcg_temp_free_i32(t0); | |
6239 | } | |
5eb7995e JM |
6240 | break; |
6241 | default: | |
e06fcd75 | 6242 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
6243 | break; |
6244 | } | |
6245 | #endif | |
6246 | } | |
6247 | ||
76a66253 | 6248 | /* wrtee */ |
99e300ef | 6249 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
6250 | { |
6251 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6252 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6253 | #else |
6527f6ea | 6254 | TCGv t0; |
76db3ba4 | 6255 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6256 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6257 | return; |
6258 | } | |
6527f6ea AJ |
6259 | t0 = tcg_temp_new(); |
6260 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
6261 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
6262 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
6263 | tcg_temp_free(t0); | |
dee96f6c JM |
6264 | /* Stop translation to have a chance to raise an exception |
6265 | * if we just set msr_ee to 1 | |
6266 | */ | |
e06fcd75 | 6267 | gen_stop_exception(ctx); |
76a66253 JM |
6268 | #endif |
6269 | } | |
6270 | ||
6271 | /* wrteei */ | |
99e300ef | 6272 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
6273 | { |
6274 | #if defined(CONFIG_USER_ONLY) | |
e06fcd75 | 6275 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 | 6276 | #else |
76db3ba4 | 6277 | if (unlikely(!ctx->mem_idx)) { |
e06fcd75 | 6278 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
76a66253 JM |
6279 | return; |
6280 | } | |
6527f6ea AJ |
6281 | if (ctx->opcode & 0x00010000) { |
6282 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); | |
6283 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 6284 | gen_stop_exception(ctx); |
6527f6ea | 6285 | } else { |
1b6e5f99 | 6286 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 6287 | } |
76a66253 JM |
6288 | #endif |
6289 | } | |
6290 | ||
08e46e54 | 6291 | /* PowerPC 440 specific instructions */ |
99e300ef | 6292 | |
54623277 | 6293 | /* dlmzb */ |
99e300ef | 6294 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6295 | { |
ef0d51af AJ |
6296 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
6297 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
6298 | cpu_gpr[rB(ctx->opcode)], t0); | |
6299 | tcg_temp_free_i32(t0); | |
76a66253 JM |
6300 | } |
6301 | ||
6302 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6303 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6304 | { |
6305 | /* interpreted as no-op */ | |
6306 | } | |
6307 | ||
6308 | /* msync replaces sync on 440 */ | |
99e300ef | 6309 | static void gen_msync(DisasContext *ctx) |
76a66253 JM |
6310 | { |
6311 | /* interpreted as no-op */ | |
6312 | } | |
6313 | ||
6314 | /* icbt */ | |
e8eaa2c0 | 6315 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6316 | { |
6317 | /* interpreted as no-op */ | |
6318 | /* XXX: specification say this is treated as a load by the MMU | |
6319 | * but does not generate any exception | |
6320 | */ | |
79aceca5 FB |
6321 | } |
6322 | ||
a9d9eb8f JM |
6323 | /*** Altivec vector extension ***/ |
6324 | /* Altivec registers moves */ | |
a9d9eb8f | 6325 | |
564e571a AJ |
6326 | static always_inline TCGv_ptr gen_avr_ptr(int reg) |
6327 | { | |
e4704b3b | 6328 | TCGv_ptr r = tcg_temp_new_ptr(); |
564e571a AJ |
6329 | tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg])); |
6330 | return r; | |
6331 | } | |
6332 | ||
a9d9eb8f | 6333 | #define GEN_VR_LDX(name, opc2, opc3) \ |
99e300ef BS |
6334 | GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC); \ |
6335 | \ | |
6336 | static void glue(gen_, name)(DisasContext *ctx) \ | |
a9d9eb8f | 6337 | { \ |
fe1e5c53 | 6338 | TCGv EA; \ |
a9d9eb8f | 6339 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6340 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6341 | return; \ |
6342 | } \ | |
76db3ba4 | 6343 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6344 | EA = tcg_temp_new(); \ |
76db3ba4 | 6345 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6346 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6347 | if (ctx->le_mode) { \ |
6348 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6349 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6350 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6351 | } else { \ |
76db3ba4 | 6352 | gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6353 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6354 | gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6355 | } \ |
6356 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6357 | } |
6358 | ||
6359 | #define GEN_VR_STX(name, opc2, opc3) \ | |
99e300ef BS |
6360 | GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC); \ |
6361 | \ | |
6362 | static void gen_st##name(DisasContext *ctx) \ | |
a9d9eb8f | 6363 | { \ |
fe1e5c53 | 6364 | TCGv EA; \ |
a9d9eb8f | 6365 | if (unlikely(!ctx->altivec_enabled)) { \ |
e06fcd75 | 6366 | gen_exception(ctx, POWERPC_EXCP_VPU); \ |
a9d9eb8f JM |
6367 | return; \ |
6368 | } \ | |
76db3ba4 | 6369 | gen_set_access_type(ctx, ACCESS_INT); \ |
fe1e5c53 | 6370 | EA = tcg_temp_new(); \ |
76db3ba4 | 6371 | gen_addr_reg_index(ctx, EA); \ |
fe1e5c53 | 6372 | tcg_gen_andi_tl(EA, EA, ~0xf); \ |
76db3ba4 AJ |
6373 | if (ctx->le_mode) { \ |
6374 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ | |
fe1e5c53 | 6375 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6376 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6377 | } else { \ |
76db3ba4 | 6378 | gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \ |
fe1e5c53 | 6379 | tcg_gen_addi_tl(EA, EA, 8); \ |
76db3ba4 | 6380 | gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \ |
fe1e5c53 AJ |
6381 | } \ |
6382 | tcg_temp_free(EA); \ | |
a9d9eb8f JM |
6383 | } |
6384 | ||
cbfb6ae9 | 6385 | #define GEN_VR_LVE(name, opc2, opc3) \ |
99e300ef BS |
6386 | GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC); \ |
6387 | \ | |
6388 | static void gen_lve##name(DisasContext *ctx) \ | |
cbfb6ae9 AJ |
6389 | { \ |
6390 | TCGv EA; \ | |
6391 | TCGv_ptr rs; \ | |
6392 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6393 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6394 | return; \ | |
6395 | } \ | |
6396 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6397 | EA = tcg_temp_new(); \ | |
6398 | gen_addr_reg_index(ctx, EA); \ | |
6399 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
6400 | gen_helper_lve##name (rs, EA); \ | |
6401 | tcg_temp_free(EA); \ | |
6402 | tcg_temp_free_ptr(rs); \ | |
6403 | } | |
6404 | ||
6405 | #define GEN_VR_STVE(name, opc2, opc3) \ | |
99e300ef BS |
6406 | GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC); \ |
6407 | \ | |
6408 | static void gen_stve##name(DisasContext *ctx) \ | |
cbfb6ae9 AJ |
6409 | { \ |
6410 | TCGv EA; \ | |
6411 | TCGv_ptr rs; \ | |
6412 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6413 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6414 | return; \ | |
6415 | } \ | |
6416 | gen_set_access_type(ctx, ACCESS_INT); \ | |
6417 | EA = tcg_temp_new(); \ | |
6418 | gen_addr_reg_index(ctx, EA); \ | |
6419 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
6420 | gen_helper_stve##name (rs, EA); \ | |
6421 | tcg_temp_free(EA); \ | |
6422 | tcg_temp_free_ptr(rs); \ | |
6423 | } | |
6424 | ||
fe1e5c53 | 6425 | GEN_VR_LDX(lvx, 0x07, 0x03); |
a9d9eb8f | 6426 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ |
fe1e5c53 | 6427 | GEN_VR_LDX(lvxl, 0x07, 0x0B); |
a9d9eb8f | 6428 | |
cbfb6ae9 AJ |
6429 | GEN_VR_LVE(bx, 0x07, 0x00); |
6430 | GEN_VR_LVE(hx, 0x07, 0x01); | |
6431 | GEN_VR_LVE(wx, 0x07, 0x02); | |
6432 | ||
fe1e5c53 | 6433 | GEN_VR_STX(svx, 0x07, 0x07); |
a9d9eb8f | 6434 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ |
fe1e5c53 | 6435 | GEN_VR_STX(svxl, 0x07, 0x0F); |
a9d9eb8f | 6436 | |
cbfb6ae9 AJ |
6437 | GEN_VR_STVE(bx, 0x07, 0x04); |
6438 | GEN_VR_STVE(hx, 0x07, 0x05); | |
6439 | GEN_VR_STVE(wx, 0x07, 0x06); | |
6440 | ||
99e300ef | 6441 | static void gen_lvsl(DisasContext *ctx) |
bf8d8ded AJ |
6442 | { |
6443 | TCGv_ptr rd; | |
6444 | TCGv EA; | |
6445 | if (unlikely(!ctx->altivec_enabled)) { | |
6446 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6447 | return; | |
6448 | } | |
6449 | EA = tcg_temp_new(); | |
6450 | gen_addr_reg_index(ctx, EA); | |
6451 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6452 | gen_helper_lvsl(rd, EA); | |
6453 | tcg_temp_free(EA); | |
6454 | tcg_temp_free_ptr(rd); | |
6455 | } | |
6456 | ||
99e300ef | 6457 | static void gen_lvsr(DisasContext *ctx) |
bf8d8ded AJ |
6458 | { |
6459 | TCGv_ptr rd; | |
6460 | TCGv EA; | |
6461 | if (unlikely(!ctx->altivec_enabled)) { | |
6462 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6463 | return; | |
6464 | } | |
6465 | EA = tcg_temp_new(); | |
6466 | gen_addr_reg_index(ctx, EA); | |
6467 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6468 | gen_helper_lvsr(rd, EA); | |
6469 | tcg_temp_free(EA); | |
6470 | tcg_temp_free_ptr(rd); | |
6471 | } | |
6472 | ||
99e300ef | 6473 | static void gen_mfvscr(DisasContext *ctx) |
785f451b AJ |
6474 | { |
6475 | TCGv_i32 t; | |
6476 | if (unlikely(!ctx->altivec_enabled)) { | |
6477 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6478 | return; | |
6479 | } | |
6480 | tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); | |
6481 | t = tcg_temp_new_i32(); | |
6482 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr)); | |
6483 | tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); | |
fce5ecb7 | 6484 | tcg_temp_free_i32(t); |
785f451b AJ |
6485 | } |
6486 | ||
99e300ef | 6487 | static void gen_mtvscr(DisasContext *ctx) |
785f451b | 6488 | { |
6e87b7c7 | 6489 | TCGv_ptr p; |
785f451b AJ |
6490 | if (unlikely(!ctx->altivec_enabled)) { |
6491 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6492 | return; | |
6493 | } | |
6e87b7c7 AJ |
6494 | p = gen_avr_ptr(rD(ctx->opcode)); |
6495 | gen_helper_mtvscr(p); | |
6496 | tcg_temp_free_ptr(p); | |
785f451b AJ |
6497 | } |
6498 | ||
7a9b96cf AJ |
6499 | /* Logical operations */ |
6500 | #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ | |
99e300ef BS |
6501 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \ |
6502 | \ | |
6503 | static void glue(gen_, name)(DisasContext *ctx) \ | |
7a9b96cf AJ |
6504 | { \ |
6505 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6506 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6507 | return; \ | |
6508 | } \ | |
6509 | tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \ | |
6510 | tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \ | |
6511 | } | |
6512 | ||
6513 | GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16); | |
6514 | GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17); | |
6515 | GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18); | |
6516 | GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19); | |
6517 | GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20); | |
6518 | ||
8e27dd6f | 6519 | #define GEN_VXFORM(name, opc2, opc3) \ |
99e300ef BS |
6520 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \ |
6521 | \ | |
6522 | static void glue(gen_, name)(DisasContext *ctx) \ | |
8e27dd6f AJ |
6523 | { \ |
6524 | TCGv_ptr ra, rb, rd; \ | |
6525 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6526 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6527 | return; \ | |
6528 | } \ | |
6529 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6530 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6531 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6532 | gen_helper_##name (rd, ra, rb); \ | |
6533 | tcg_temp_free_ptr(ra); \ | |
6534 | tcg_temp_free_ptr(rb); \ | |
6535 | tcg_temp_free_ptr(rd); \ | |
6536 | } | |
6537 | ||
7872c51c AJ |
6538 | GEN_VXFORM(vaddubm, 0, 0); |
6539 | GEN_VXFORM(vadduhm, 0, 1); | |
6540 | GEN_VXFORM(vadduwm, 0, 2); | |
6541 | GEN_VXFORM(vsububm, 0, 16); | |
6542 | GEN_VXFORM(vsubuhm, 0, 17); | |
6543 | GEN_VXFORM(vsubuwm, 0, 18); | |
e4039339 AJ |
6544 | GEN_VXFORM(vmaxub, 1, 0); |
6545 | GEN_VXFORM(vmaxuh, 1, 1); | |
6546 | GEN_VXFORM(vmaxuw, 1, 2); | |
6547 | GEN_VXFORM(vmaxsb, 1, 4); | |
6548 | GEN_VXFORM(vmaxsh, 1, 5); | |
6549 | GEN_VXFORM(vmaxsw, 1, 6); | |
6550 | GEN_VXFORM(vminub, 1, 8); | |
6551 | GEN_VXFORM(vminuh, 1, 9); | |
6552 | GEN_VXFORM(vminuw, 1, 10); | |
6553 | GEN_VXFORM(vminsb, 1, 12); | |
6554 | GEN_VXFORM(vminsh, 1, 13); | |
6555 | GEN_VXFORM(vminsw, 1, 14); | |
fab3cbe9 AJ |
6556 | GEN_VXFORM(vavgub, 1, 16); |
6557 | GEN_VXFORM(vavguh, 1, 17); | |
6558 | GEN_VXFORM(vavguw, 1, 18); | |
6559 | GEN_VXFORM(vavgsb, 1, 20); | |
6560 | GEN_VXFORM(vavgsh, 1, 21); | |
6561 | GEN_VXFORM(vavgsw, 1, 22); | |
3b430048 AJ |
6562 | GEN_VXFORM(vmrghb, 6, 0); |
6563 | GEN_VXFORM(vmrghh, 6, 1); | |
6564 | GEN_VXFORM(vmrghw, 6, 2); | |
6565 | GEN_VXFORM(vmrglb, 6, 4); | |
6566 | GEN_VXFORM(vmrglh, 6, 5); | |
6567 | GEN_VXFORM(vmrglw, 6, 6); | |
2c277908 AJ |
6568 | GEN_VXFORM(vmuloub, 4, 0); |
6569 | GEN_VXFORM(vmulouh, 4, 1); | |
6570 | GEN_VXFORM(vmulosb, 4, 4); | |
6571 | GEN_VXFORM(vmulosh, 4, 5); | |
6572 | GEN_VXFORM(vmuleub, 4, 8); | |
6573 | GEN_VXFORM(vmuleuh, 4, 9); | |
6574 | GEN_VXFORM(vmulesb, 4, 12); | |
6575 | GEN_VXFORM(vmulesh, 4, 13); | |
d79f0809 AJ |
6576 | GEN_VXFORM(vslb, 2, 4); |
6577 | GEN_VXFORM(vslh, 2, 5); | |
6578 | GEN_VXFORM(vslw, 2, 6); | |
07ef34c3 AJ |
6579 | GEN_VXFORM(vsrb, 2, 8); |
6580 | GEN_VXFORM(vsrh, 2, 9); | |
6581 | GEN_VXFORM(vsrw, 2, 10); | |
6582 | GEN_VXFORM(vsrab, 2, 12); | |
6583 | GEN_VXFORM(vsrah, 2, 13); | |
6584 | GEN_VXFORM(vsraw, 2, 14); | |
7b239bec AJ |
6585 | GEN_VXFORM(vslo, 6, 16); |
6586 | GEN_VXFORM(vsro, 6, 17); | |
e343da72 AJ |
6587 | GEN_VXFORM(vaddcuw, 0, 6); |
6588 | GEN_VXFORM(vsubcuw, 0, 22); | |
5ab09f33 AJ |
6589 | GEN_VXFORM(vaddubs, 0, 8); |
6590 | GEN_VXFORM(vadduhs, 0, 9); | |
6591 | GEN_VXFORM(vadduws, 0, 10); | |
6592 | GEN_VXFORM(vaddsbs, 0, 12); | |
6593 | GEN_VXFORM(vaddshs, 0, 13); | |
6594 | GEN_VXFORM(vaddsws, 0, 14); | |
6595 | GEN_VXFORM(vsububs, 0, 24); | |
6596 | GEN_VXFORM(vsubuhs, 0, 25); | |
6597 | GEN_VXFORM(vsubuws, 0, 26); | |
6598 | GEN_VXFORM(vsubsbs, 0, 28); | |
6599 | GEN_VXFORM(vsubshs, 0, 29); | |
6600 | GEN_VXFORM(vsubsws, 0, 30); | |
5e1d0985 AJ |
6601 | GEN_VXFORM(vrlb, 2, 0); |
6602 | GEN_VXFORM(vrlh, 2, 1); | |
6603 | GEN_VXFORM(vrlw, 2, 2); | |
d9430add AJ |
6604 | GEN_VXFORM(vsl, 2, 7); |
6605 | GEN_VXFORM(vsr, 2, 11); | |
5335a145 AJ |
6606 | GEN_VXFORM(vpkuhum, 7, 0); |
6607 | GEN_VXFORM(vpkuwum, 7, 1); | |
6608 | GEN_VXFORM(vpkuhus, 7, 2); | |
6609 | GEN_VXFORM(vpkuwus, 7, 3); | |
6610 | GEN_VXFORM(vpkshus, 7, 4); | |
6611 | GEN_VXFORM(vpkswus, 7, 5); | |
6612 | GEN_VXFORM(vpkshss, 7, 6); | |
6613 | GEN_VXFORM(vpkswss, 7, 7); | |
1dd9ffb9 | 6614 | GEN_VXFORM(vpkpx, 7, 12); |
8142cddd AJ |
6615 | GEN_VXFORM(vsum4ubs, 4, 24); |
6616 | GEN_VXFORM(vsum4sbs, 4, 28); | |
6617 | GEN_VXFORM(vsum4shs, 4, 25); | |
6618 | GEN_VXFORM(vsum2sws, 4, 26); | |
6619 | GEN_VXFORM(vsumsws, 4, 30); | |
56fdd213 AJ |
6620 | GEN_VXFORM(vaddfp, 5, 0); |
6621 | GEN_VXFORM(vsubfp, 5, 1); | |
1536ff64 AJ |
6622 | GEN_VXFORM(vmaxfp, 5, 16); |
6623 | GEN_VXFORM(vminfp, 5, 17); | |
fab3cbe9 | 6624 | |
0cbcd906 | 6625 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ |
e8eaa2c0 BS |
6626 | GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC); \ |
6627 | \ | |
6628 | static void glue(gen_, name)(DisasContext *ctx) \ | |
0cbcd906 AJ |
6629 | { \ |
6630 | TCGv_ptr ra, rb, rd; \ | |
6631 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6632 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6633 | return; \ | |
6634 | } \ | |
6635 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6636 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6637 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6638 | gen_helper_##opname (rd, ra, rb); \ | |
6639 | tcg_temp_free_ptr(ra); \ | |
6640 | tcg_temp_free_ptr(rb); \ | |
6641 | tcg_temp_free_ptr(rd); \ | |
6642 | } | |
6643 | ||
6644 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
6645 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
6646 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
6647 | ||
1add6e23 AJ |
6648 | GEN_VXRFORM(vcmpequb, 3, 0) |
6649 | GEN_VXRFORM(vcmpequh, 3, 1) | |
6650 | GEN_VXRFORM(vcmpequw, 3, 2) | |
6651 | GEN_VXRFORM(vcmpgtsb, 3, 12) | |
6652 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
6653 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
6654 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
6655 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
6656 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
819ca121 AJ |
6657 | GEN_VXRFORM(vcmpeqfp, 3, 3) |
6658 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
6659 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
6660 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
1add6e23 | 6661 | |
c026766b | 6662 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef BS |
6663 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \ |
6664 | \ | |
6665 | static void glue(gen_, name)(DisasContext *ctx) \ | |
c026766b AJ |
6666 | { \ |
6667 | TCGv_ptr rd; \ | |
6668 | TCGv_i32 simm; \ | |
6669 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6670 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6671 | return; \ | |
6672 | } \ | |
6673 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6674 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6675 | gen_helper_##name (rd, simm); \ | |
6676 | tcg_temp_free_i32(simm); \ | |
6677 | tcg_temp_free_ptr(rd); \ | |
6678 | } | |
6679 | ||
6680 | GEN_VXFORM_SIMM(vspltisb, 6, 12); | |
6681 | GEN_VXFORM_SIMM(vspltish, 6, 13); | |
6682 | GEN_VXFORM_SIMM(vspltisw, 6, 14); | |
6683 | ||
de5f2484 | 6684 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ |
99e300ef BS |
6685 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC); \ |
6686 | \ | |
6687 | static void glue(gen_, name)(DisasContext *ctx) \ | |
de5f2484 AJ |
6688 | { \ |
6689 | TCGv_ptr rb, rd; \ | |
6690 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6691 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6692 | return; \ | |
6693 | } \ | |
6694 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6695 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6696 | gen_helper_##name (rd, rb); \ | |
6697 | tcg_temp_free_ptr(rb); \ | |
6698 | tcg_temp_free_ptr(rd); \ | |
6699 | } | |
6700 | ||
6cf1c6e5 AJ |
6701 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
6702 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
6703 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
6704 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
79f85c3a AJ |
6705 | GEN_VXFORM_NOA(vupkhpx, 7, 13); |
6706 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
bdfbac35 | 6707 | GEN_VXFORM_NOA(vrefp, 5, 4); |
071fc3b1 | 6708 | GEN_VXFORM_NOA(vrsqrtefp, 5, 5); |
b580763f | 6709 | GEN_VXFORM_NOA(vlogefp, 5, 7); |
f6b19645 AJ |
6710 | GEN_VXFORM_NOA(vrfim, 5, 8); |
6711 | GEN_VXFORM_NOA(vrfin, 5, 9); | |
6712 | GEN_VXFORM_NOA(vrfip, 5, 10); | |
6713 | GEN_VXFORM_NOA(vrfiz, 5, 11); | |
79f85c3a | 6714 | |
21d21583 | 6715 | #define GEN_VXFORM_SIMM(name, opc2, opc3) \ |
99e300ef BS |
6716 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \ |
6717 | \ | |
6718 | static void glue(gen_, name)(DisasContext *ctx) \ | |
21d21583 AJ |
6719 | { \ |
6720 | TCGv_ptr rd; \ | |
6721 | TCGv_i32 simm; \ | |
6722 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6723 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6724 | return; \ | |
6725 | } \ | |
6726 | simm = tcg_const_i32(SIMM5(ctx->opcode)); \ | |
6727 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6728 | gen_helper_##name (rd, simm); \ | |
6729 | tcg_temp_free_i32(simm); \ | |
6730 | tcg_temp_free_ptr(rd); \ | |
6731 | } | |
6732 | ||
27a4edb3 | 6733 | #define GEN_VXFORM_UIMM(name, opc2, opc3) \ |
99e300ef BS |
6734 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC); \ |
6735 | \ | |
6736 | static void glue(gen_, name)(DisasContext *ctx) \ | |
27a4edb3 AJ |
6737 | { \ |
6738 | TCGv_ptr rb, rd; \ | |
6739 | TCGv_i32 uimm; \ | |
6740 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6741 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6742 | return; \ | |
6743 | } \ | |
6744 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
6745 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6746 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6747 | gen_helper_##name (rd, rb, uimm); \ | |
6748 | tcg_temp_free_i32(uimm); \ | |
6749 | tcg_temp_free_ptr(rb); \ | |
6750 | tcg_temp_free_ptr(rd); \ | |
6751 | } | |
6752 | ||
e4e6bee7 AJ |
6753 | GEN_VXFORM_UIMM(vspltb, 6, 8); |
6754 | GEN_VXFORM_UIMM(vsplth, 6, 9); | |
6755 | GEN_VXFORM_UIMM(vspltw, 6, 10); | |
e140632e AJ |
6756 | GEN_VXFORM_UIMM(vcfux, 5, 12); |
6757 | GEN_VXFORM_UIMM(vcfsx, 5, 13); | |
875b31db AJ |
6758 | GEN_VXFORM_UIMM(vctuxs, 5, 14); |
6759 | GEN_VXFORM_UIMM(vctsxs, 5, 15); | |
e4e6bee7 | 6760 | |
99e300ef | 6761 | static void gen_vsldoi(DisasContext *ctx) |
cd633b10 AJ |
6762 | { |
6763 | TCGv_ptr ra, rb, rd; | |
fce5ecb7 | 6764 | TCGv_i32 sh; |
cd633b10 AJ |
6765 | if (unlikely(!ctx->altivec_enabled)) { |
6766 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6767 | return; | |
6768 | } | |
6769 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6770 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6771 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6772 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
6773 | gen_helper_vsldoi (rd, ra, rb, sh); | |
6774 | tcg_temp_free_ptr(ra); | |
6775 | tcg_temp_free_ptr(rb); | |
6776 | tcg_temp_free_ptr(rd); | |
fce5ecb7 | 6777 | tcg_temp_free_i32(sh); |
cd633b10 AJ |
6778 | } |
6779 | ||
707cec33 | 6780 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ |
99e300ef BS |
6781 | GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC);\ |
6782 | \ | |
6783 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
707cec33 AJ |
6784 | { \ |
6785 | TCGv_ptr ra, rb, rc, rd; \ | |
6786 | if (unlikely(!ctx->altivec_enabled)) { \ | |
6787 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
6788 | return; \ | |
6789 | } \ | |
6790 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
6791 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
6792 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
6793 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
6794 | if (Rc(ctx->opcode)) { \ | |
6795 | gen_helper_##name1 (rd, ra, rb, rc); \ | |
6796 | } else { \ | |
6797 | gen_helper_##name0 (rd, ra, rb, rc); \ | |
6798 | } \ | |
6799 | tcg_temp_free_ptr(ra); \ | |
6800 | tcg_temp_free_ptr(rb); \ | |
6801 | tcg_temp_free_ptr(rc); \ | |
6802 | tcg_temp_free_ptr(rd); \ | |
6803 | } | |
6804 | ||
b161ae27 AJ |
6805 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) |
6806 | ||
99e300ef | 6807 | static void gen_vmladduhm(DisasContext *ctx) |
bcd2ee23 AJ |
6808 | { |
6809 | TCGv_ptr ra, rb, rc, rd; | |
6810 | if (unlikely(!ctx->altivec_enabled)) { | |
6811 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
6812 | return; | |
6813 | } | |
6814 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
6815 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
6816 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
6817 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
6818 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
6819 | tcg_temp_free_ptr(ra); | |
6820 | tcg_temp_free_ptr(rb); | |
6821 | tcg_temp_free_ptr(rc); | |
6822 | tcg_temp_free_ptr(rd); | |
6823 | } | |
6824 | ||
b04ae981 | 6825 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
4d9903b6 | 6826 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) |
eae07261 | 6827 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) |
d1258698 | 6828 | GEN_VAFORM_PAIRED(vsel, vperm, 21) |
35cf7c7e | 6829 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) |
b04ae981 | 6830 | |
0487d6a8 | 6831 | /*** SPE extension ***/ |
0487d6a8 | 6832 | /* Register moves */ |
3cd7d1dd | 6833 | |
a7812ae4 | 6834 | static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) { |
f78fb44e AJ |
6835 | #if defined(TARGET_PPC64) |
6836 | tcg_gen_mov_i64(t, cpu_gpr[reg]); | |
6837 | #else | |
36aa55dc | 6838 | tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]); |
3cd7d1dd | 6839 | #endif |
f78fb44e | 6840 | } |
3cd7d1dd | 6841 | |
a7812ae4 | 6842 | static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) { |
f78fb44e AJ |
6843 | #if defined(TARGET_PPC64) |
6844 | tcg_gen_mov_i64(cpu_gpr[reg], t); | |
6845 | #else | |
a7812ae4 | 6846 | TCGv_i64 tmp = tcg_temp_new_i64(); |
f78fb44e | 6847 | tcg_gen_trunc_i64_i32(cpu_gpr[reg], t); |
f78fb44e AJ |
6848 | tcg_gen_shri_i64(tmp, t, 32); |
6849 | tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp); | |
a7812ae4 | 6850 | tcg_temp_free_i64(tmp); |
3cd7d1dd | 6851 | #endif |
f78fb44e | 6852 | } |
3cd7d1dd | 6853 | |
0487d6a8 | 6854 | #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \ |
99e300ef BS |
6855 | GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type); \ |
6856 | \ | |
6857 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
0487d6a8 JM |
6858 | { \ |
6859 | if (Rc(ctx->opcode)) \ | |
6860 | gen_##name1(ctx); \ | |
6861 | else \ | |
6862 | gen_##name0(ctx); \ | |
6863 | } | |
6864 | ||
6865 | /* Handler for undefined SPE opcodes */ | |
b068d6a7 | 6866 | static always_inline void gen_speundef (DisasContext *ctx) |
0487d6a8 | 6867 | { |
e06fcd75 | 6868 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
0487d6a8 JM |
6869 | } |
6870 | ||
57951c27 AJ |
6871 | /* SPE logic */ |
6872 | #if defined(TARGET_PPC64) | |
6873 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
b068d6a7 | 6874 | static always_inline void gen_##name (DisasContext *ctx) \ |
0487d6a8 JM |
6875 | { \ |
6876 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6877 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
6878 | return; \ |
6879 | } \ | |
57951c27 AJ |
6880 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6881 | cpu_gpr[rB(ctx->opcode)]); \ | |
6882 | } | |
6883 | #else | |
6884 | #define GEN_SPEOP_LOGIC2(name, tcg_op) \ | |
6885 | static always_inline void gen_##name (DisasContext *ctx) \ | |
6886 | { \ | |
6887 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6888 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
6889 | return; \ |
6890 | } \ | |
6891 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ | |
6892 | cpu_gpr[rB(ctx->opcode)]); \ | |
6893 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6894 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 6895 | } |
57951c27 AJ |
6896 | #endif |
6897 | ||
6898 | GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl); | |
6899 | GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl); | |
6900 | GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl); | |
6901 | GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl); | |
6902 | GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl); | |
6903 | GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl); | |
6904 | GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl); | |
6905 | GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl); | |
0487d6a8 | 6906 | |
57951c27 AJ |
6907 | /* SPE logic immediate */ |
6908 | #if defined(TARGET_PPC64) | |
6909 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
3d3a6a0a AJ |
6910 | static always_inline void gen_##name (DisasContext *ctx) \ |
6911 | { \ | |
6912 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6913 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
3d3a6a0a AJ |
6914 | return; \ |
6915 | } \ | |
a7812ae4 PB |
6916 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6917 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6918 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6919 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6920 | tcg_opi(t0, t0, rB(ctx->opcode)); \ | |
6921 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6922 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6923 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6924 | tcg_opi(t1, t1, rB(ctx->opcode)); \ |
6925 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6926 | tcg_temp_free_i32(t0); \ |
6927 | tcg_temp_free_i32(t1); \ | |
3d3a6a0a | 6928 | } |
57951c27 AJ |
6929 | #else |
6930 | #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \ | |
b068d6a7 | 6931 | static always_inline void gen_##name (DisasContext *ctx) \ |
0487d6a8 JM |
6932 | { \ |
6933 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6934 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
6935 | return; \ |
6936 | } \ | |
57951c27 AJ |
6937 | tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
6938 | rB(ctx->opcode)); \ | |
6939 | tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
6940 | rB(ctx->opcode)); \ | |
0487d6a8 | 6941 | } |
57951c27 AJ |
6942 | #endif |
6943 | GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32); | |
6944 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32); | |
6945 | GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32); | |
6946 | GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32); | |
0487d6a8 | 6947 | |
57951c27 AJ |
6948 | /* SPE arithmetic */ |
6949 | #if defined(TARGET_PPC64) | |
6950 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ | |
b068d6a7 | 6951 | static always_inline void gen_##name (DisasContext *ctx) \ |
0487d6a8 JM |
6952 | { \ |
6953 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6954 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
6955 | return; \ |
6956 | } \ | |
a7812ae4 PB |
6957 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
6958 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
6959 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
6960 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
6961 | tcg_op(t0, t0); \ | |
6962 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
6963 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 6964 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
6965 | tcg_op(t1, t1); \ |
6966 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
6967 | tcg_temp_free_i32(t0); \ |
6968 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 6969 | } |
57951c27 | 6970 | #else |
a7812ae4 | 6971 | #define GEN_SPEOP_ARITH1(name, tcg_op) \ |
57951c27 AJ |
6972 | static always_inline void gen_##name (DisasContext *ctx) \ |
6973 | { \ | |
6974 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 6975 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
6976 | return; \ |
6977 | } \ | |
6978 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \ | |
6979 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \ | |
6980 | } | |
6981 | #endif | |
0487d6a8 | 6982 | |
a7812ae4 | 6983 | static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1) |
57951c27 AJ |
6984 | { |
6985 | int l1 = gen_new_label(); | |
6986 | int l2 = gen_new_label(); | |
0487d6a8 | 6987 | |
57951c27 AJ |
6988 | tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1); |
6989 | tcg_gen_neg_i32(ret, arg1); | |
6990 | tcg_gen_br(l2); | |
6991 | gen_set_label(l1); | |
a7812ae4 | 6992 | tcg_gen_mov_i32(ret, arg1); |
57951c27 AJ |
6993 | gen_set_label(l2); |
6994 | } | |
6995 | GEN_SPEOP_ARITH1(evabs, gen_op_evabs); | |
6996 | GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32); | |
6997 | GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32); | |
6998 | GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32); | |
a7812ae4 | 6999 | static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1) |
0487d6a8 | 7000 | { |
57951c27 AJ |
7001 | tcg_gen_addi_i32(ret, arg1, 0x8000); |
7002 | tcg_gen_ext16u_i32(ret, ret); | |
7003 | } | |
7004 | GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw); | |
a7812ae4 PB |
7005 | GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32); |
7006 | GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32); | |
0487d6a8 | 7007 | |
57951c27 AJ |
7008 | #if defined(TARGET_PPC64) |
7009 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
7010 | static always_inline void gen_##name (DisasContext *ctx) \ | |
0487d6a8 JM |
7011 | { \ |
7012 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7013 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
7014 | return; \ |
7015 | } \ | |
a7812ae4 PB |
7016 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7017 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7018 | TCGv_i32 t2 = tcg_temp_local_new_i32(); \ | |
501e23c4 | 7019 | TCGv_i64 t3 = tcg_temp_local_new_i64(); \ |
57951c27 AJ |
7020 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7021 | tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \ | |
7022 | tcg_op(t0, t0, t2); \ | |
7023 | tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7024 | tcg_gen_trunc_i64_i32(t1, t3); \ | |
7025 | tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7026 | tcg_gen_trunc_i64_i32(t2, t3); \ | |
a7812ae4 | 7027 | tcg_temp_free_i64(t3); \ |
57951c27 | 7028 | tcg_op(t1, t1, t2); \ |
a7812ae4 | 7029 | tcg_temp_free_i32(t2); \ |
57951c27 | 7030 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ |
a7812ae4 PB |
7031 | tcg_temp_free_i32(t0); \ |
7032 | tcg_temp_free_i32(t1); \ | |
0487d6a8 | 7033 | } |
57951c27 AJ |
7034 | #else |
7035 | #define GEN_SPEOP_ARITH2(name, tcg_op) \ | |
7036 | static always_inline void gen_##name (DisasContext *ctx) \ | |
0487d6a8 JM |
7037 | { \ |
7038 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7039 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
0487d6a8 JM |
7040 | return; \ |
7041 | } \ | |
57951c27 AJ |
7042 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7043 | cpu_gpr[rB(ctx->opcode)]); \ | |
7044 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ | |
7045 | cpu_gprh[rB(ctx->opcode)]); \ | |
0487d6a8 | 7046 | } |
57951c27 | 7047 | #endif |
0487d6a8 | 7048 | |
a7812ae4 | 7049 | static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7050 | { |
a7812ae4 | 7051 | TCGv_i32 t0; |
57951c27 | 7052 | int l1, l2; |
0487d6a8 | 7053 | |
57951c27 AJ |
7054 | l1 = gen_new_label(); |
7055 | l2 = gen_new_label(); | |
a7812ae4 | 7056 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7057 | /* No error here: 6 bits are used */ |
7058 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7059 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7060 | tcg_gen_shr_i32(ret, arg1, t0); | |
7061 | tcg_gen_br(l2); | |
7062 | gen_set_label(l1); | |
7063 | tcg_gen_movi_i32(ret, 0); | |
7064 | tcg_gen_br(l2); | |
a7812ae4 | 7065 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7066 | } |
7067 | GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu); | |
a7812ae4 | 7068 | static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7069 | { |
a7812ae4 | 7070 | TCGv_i32 t0; |
57951c27 AJ |
7071 | int l1, l2; |
7072 | ||
7073 | l1 = gen_new_label(); | |
7074 | l2 = gen_new_label(); | |
a7812ae4 | 7075 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7076 | /* No error here: 6 bits are used */ |
7077 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7078 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7079 | tcg_gen_sar_i32(ret, arg1, t0); | |
7080 | tcg_gen_br(l2); | |
7081 | gen_set_label(l1); | |
7082 | tcg_gen_movi_i32(ret, 0); | |
7083 | tcg_gen_br(l2); | |
a7812ae4 | 7084 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7085 | } |
7086 | GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws); | |
a7812ae4 | 7087 | static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7088 | { |
a7812ae4 | 7089 | TCGv_i32 t0; |
57951c27 AJ |
7090 | int l1, l2; |
7091 | ||
7092 | l1 = gen_new_label(); | |
7093 | l2 = gen_new_label(); | |
a7812ae4 | 7094 | t0 = tcg_temp_local_new_i32(); |
57951c27 AJ |
7095 | /* No error here: 6 bits are used */ |
7096 | tcg_gen_andi_i32(t0, arg2, 0x3F); | |
7097 | tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1); | |
7098 | tcg_gen_shl_i32(ret, arg1, t0); | |
7099 | tcg_gen_br(l2); | |
7100 | gen_set_label(l1); | |
7101 | tcg_gen_movi_i32(ret, 0); | |
7102 | tcg_gen_br(l2); | |
a7812ae4 | 7103 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7104 | } |
7105 | GEN_SPEOP_ARITH2(evslw, gen_op_evslw); | |
a7812ae4 | 7106 | static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
57951c27 | 7107 | { |
a7812ae4 | 7108 | TCGv_i32 t0 = tcg_temp_new_i32(); |
57951c27 AJ |
7109 | tcg_gen_andi_i32(t0, arg2, 0x1F); |
7110 | tcg_gen_rotl_i32(ret, arg1, t0); | |
a7812ae4 | 7111 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7112 | } |
7113 | GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw); | |
7114 | static always_inline void gen_evmergehi (DisasContext *ctx) | |
7115 | { | |
7116 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 7117 | gen_exception(ctx, POWERPC_EXCP_APU); |
57951c27 AJ |
7118 | return; |
7119 | } | |
7120 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7121 | TCGv t0 = tcg_temp_new(); |
7122 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7123 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7124 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
7125 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7126 | tcg_temp_free(t0); | |
7127 | tcg_temp_free(t1); | |
7128 | #else | |
7129 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7130 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7131 | #endif | |
7132 | } | |
7133 | GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32); | |
a7812ae4 | 7134 | static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
0487d6a8 | 7135 | { |
57951c27 AJ |
7136 | tcg_gen_sub_i32(ret, arg2, arg1); |
7137 | } | |
7138 | GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf); | |
0487d6a8 | 7139 | |
57951c27 AJ |
7140 | /* SPE arithmetic immediate */ |
7141 | #if defined(TARGET_PPC64) | |
7142 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
7143 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7144 | { \ | |
7145 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7146 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7147 | return; \ |
7148 | } \ | |
a7812ae4 PB |
7149 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7150 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7151 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7152 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ |
7153 | tcg_op(t0, t0, rA(ctx->opcode)); \ | |
7154 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7155 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
e06fcd75 | 7156 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7157 | tcg_op(t1, t1, rA(ctx->opcode)); \ |
7158 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \ | |
a7812ae4 PB |
7159 | tcg_temp_free_i32(t0); \ |
7160 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7161 | } |
7162 | #else | |
7163 | #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \ | |
7164 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7165 | { \ | |
7166 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7167 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7168 | return; \ |
7169 | } \ | |
7170 | tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
7171 | rA(ctx->opcode)); \ | |
7172 | tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \ | |
7173 | rA(ctx->opcode)); \ | |
7174 | } | |
7175 | #endif | |
7176 | GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32); | |
7177 | GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32); | |
7178 | ||
7179 | /* SPE comparison */ | |
7180 | #if defined(TARGET_PPC64) | |
7181 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
7182 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7183 | { \ | |
7184 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7185 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7186 | return; \ |
7187 | } \ | |
7188 | int l1 = gen_new_label(); \ | |
7189 | int l2 = gen_new_label(); \ | |
7190 | int l3 = gen_new_label(); \ | |
7191 | int l4 = gen_new_label(); \ | |
a7812ae4 PB |
7192 | TCGv_i32 t0 = tcg_temp_local_new_i32(); \ |
7193 | TCGv_i32 t1 = tcg_temp_local_new_i32(); \ | |
7194 | TCGv_i64 t2 = tcg_temp_local_new_i64(); \ | |
57951c27 AJ |
7195 | tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ |
7196 | tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7197 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \ | |
a7812ae4 | 7198 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \ |
57951c27 AJ |
7199 | tcg_gen_br(l2); \ |
7200 | gen_set_label(l1); \ | |
7201 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7202 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7203 | gen_set_label(l2); \ | |
7204 | tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \ | |
7205 | tcg_gen_trunc_i64_i32(t0, t2); \ | |
7206 | tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \ | |
7207 | tcg_gen_trunc_i64_i32(t1, t2); \ | |
a7812ae4 | 7208 | tcg_temp_free_i64(t2); \ |
57951c27 AJ |
7209 | tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \ |
7210 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7211 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7212 | tcg_gen_br(l4); \ | |
7213 | gen_set_label(l3); \ | |
7214 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7215 | CRF_CH | CRF_CH_OR_CL); \ | |
7216 | gen_set_label(l4); \ | |
a7812ae4 PB |
7217 | tcg_temp_free_i32(t0); \ |
7218 | tcg_temp_free_i32(t1); \ | |
57951c27 AJ |
7219 | } |
7220 | #else | |
7221 | #define GEN_SPEOP_COMP(name, tcg_cond) \ | |
7222 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7223 | { \ | |
7224 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7225 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7226 | return; \ |
7227 | } \ | |
7228 | int l1 = gen_new_label(); \ | |
7229 | int l2 = gen_new_label(); \ | |
7230 | int l3 = gen_new_label(); \ | |
7231 | int l4 = gen_new_label(); \ | |
7232 | \ | |
7233 | tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \ | |
7234 | cpu_gpr[rB(ctx->opcode)], l1); \ | |
7235 | tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \ | |
7236 | tcg_gen_br(l2); \ | |
7237 | gen_set_label(l1); \ | |
7238 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \ | |
7239 | CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \ | |
7240 | gen_set_label(l2); \ | |
7241 | tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \ | |
7242 | cpu_gprh[rB(ctx->opcode)], l3); \ | |
7243 | tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7244 | ~(CRF_CH | CRF_CH_AND_CL)); \ | |
7245 | tcg_gen_br(l4); \ | |
7246 | gen_set_label(l3); \ | |
7247 | tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ | |
7248 | CRF_CH | CRF_CH_OR_CL); \ | |
7249 | gen_set_label(l4); \ | |
7250 | } | |
7251 | #endif | |
7252 | GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU); | |
7253 | GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT); | |
7254 | GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU); | |
7255 | GEN_SPEOP_COMP(evcmplts, TCG_COND_LT); | |
7256 | GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ); | |
7257 | ||
7258 | /* SPE misc */ | |
7259 | static always_inline void gen_brinc (DisasContext *ctx) | |
7260 | { | |
7261 | /* Note: brinc is usable even if SPE is disabled */ | |
a7812ae4 PB |
7262 | gen_helper_brinc(cpu_gpr[rD(ctx->opcode)], |
7263 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
0487d6a8 | 7264 | } |
57951c27 AJ |
7265 | static always_inline void gen_evmergelo (DisasContext *ctx) |
7266 | { | |
7267 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 7268 | gen_exception(ctx, POWERPC_EXCP_APU); |
57951c27 AJ |
7269 | return; |
7270 | } | |
7271 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7272 | TCGv t0 = tcg_temp_new(); |
7273 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7274 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL); |
7275 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
7276 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7277 | tcg_temp_free(t0); | |
7278 | tcg_temp_free(t1); | |
7279 | #else | |
7280 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7281 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7282 | #endif | |
7283 | } | |
7284 | static always_inline void gen_evmergehilo (DisasContext *ctx) | |
7285 | { | |
7286 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 7287 | gen_exception(ctx, POWERPC_EXCP_APU); |
57951c27 AJ |
7288 | return; |
7289 | } | |
7290 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7291 | TCGv t0 = tcg_temp_new(); |
7292 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7293 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL); |
7294 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); | |
7295 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7296 | tcg_temp_free(t0); | |
7297 | tcg_temp_free(t1); | |
7298 | #else | |
7299 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7300 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7301 | #endif | |
7302 | } | |
7303 | static always_inline void gen_evmergelohi (DisasContext *ctx) | |
7304 | { | |
7305 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 7306 | gen_exception(ctx, POWERPC_EXCP_APU); |
57951c27 AJ |
7307 | return; |
7308 | } | |
7309 | #if defined(TARGET_PPC64) | |
a7812ae4 PB |
7310 | TCGv t0 = tcg_temp_new(); |
7311 | TCGv t1 = tcg_temp_new(); | |
57951c27 AJ |
7312 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32); |
7313 | tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); | |
7314 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
7315 | tcg_temp_free(t0); | |
7316 | tcg_temp_free(t1); | |
7317 | #else | |
7318 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7319 | tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7320 | #endif | |
7321 | } | |
7322 | static always_inline void gen_evsplati (DisasContext *ctx) | |
7323 | { | |
38d14952 | 7324 | uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27; |
0487d6a8 | 7325 | |
57951c27 | 7326 | #if defined(TARGET_PPC64) |
38d14952 | 7327 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7328 | #else |
7329 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7330 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7331 | #endif | |
7332 | } | |
b068d6a7 | 7333 | static always_inline void gen_evsplatfi (DisasContext *ctx) |
0487d6a8 | 7334 | { |
38d14952 | 7335 | uint64_t imm = rA(ctx->opcode) << 11; |
0487d6a8 | 7336 | |
57951c27 | 7337 | #if defined(TARGET_PPC64) |
38d14952 | 7338 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm); |
57951c27 AJ |
7339 | #else |
7340 | tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm); | |
7341 | tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm); | |
7342 | #endif | |
0487d6a8 JM |
7343 | } |
7344 | ||
57951c27 AJ |
7345 | static always_inline void gen_evsel (DisasContext *ctx) |
7346 | { | |
7347 | int l1 = gen_new_label(); | |
7348 | int l2 = gen_new_label(); | |
7349 | int l3 = gen_new_label(); | |
7350 | int l4 = gen_new_label(); | |
a7812ae4 | 7351 | TCGv_i32 t0 = tcg_temp_local_new_i32(); |
57951c27 | 7352 | #if defined(TARGET_PPC64) |
a7812ae4 PB |
7353 | TCGv t1 = tcg_temp_local_new(); |
7354 | TCGv t2 = tcg_temp_local_new(); | |
57951c27 AJ |
7355 | #endif |
7356 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); | |
7357 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); | |
7358 | #if defined(TARGET_PPC64) | |
7359 | tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7360 | #else | |
7361 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); | |
7362 | #endif | |
7363 | tcg_gen_br(l2); | |
7364 | gen_set_label(l1); | |
7365 | #if defined(TARGET_PPC64) | |
7366 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL); | |
7367 | #else | |
7368 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); | |
7369 | #endif | |
7370 | gen_set_label(l2); | |
7371 | tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); | |
7372 | tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); | |
7373 | #if defined(TARGET_PPC64) | |
7374 | tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL); | |
7375 | #else | |
7376 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
7377 | #endif | |
7378 | tcg_gen_br(l4); | |
7379 | gen_set_label(l3); | |
7380 | #if defined(TARGET_PPC64) | |
7381 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL); | |
7382 | #else | |
7383 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
7384 | #endif | |
7385 | gen_set_label(l4); | |
a7812ae4 | 7386 | tcg_temp_free_i32(t0); |
57951c27 AJ |
7387 | #if defined(TARGET_PPC64) |
7388 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2); | |
7389 | tcg_temp_free(t1); | |
7390 | tcg_temp_free(t2); | |
7391 | #endif | |
7392 | } | |
e8eaa2c0 BS |
7393 | |
7394 | static void gen_evsel0(DisasContext *ctx) | |
57951c27 AJ |
7395 | { |
7396 | gen_evsel(ctx); | |
7397 | } | |
e8eaa2c0 BS |
7398 | |
7399 | static void gen_evsel1(DisasContext *ctx) | |
57951c27 AJ |
7400 | { |
7401 | gen_evsel(ctx); | |
7402 | } | |
e8eaa2c0 BS |
7403 | |
7404 | static void gen_evsel2(DisasContext *ctx) | |
57951c27 AJ |
7405 | { |
7406 | gen_evsel(ctx); | |
7407 | } | |
e8eaa2c0 BS |
7408 | |
7409 | static void gen_evsel3(DisasContext *ctx) | |
57951c27 AJ |
7410 | { |
7411 | gen_evsel(ctx); | |
7412 | } | |
0487d6a8 JM |
7413 | |
7414 | GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); //// | |
7415 | GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE); | |
7416 | GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); //// | |
7417 | GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE); | |
7418 | GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); //// | |
7419 | GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); //// | |
7420 | GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); //// | |
7421 | GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); // | |
7422 | GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); //// | |
7423 | GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); //// | |
7424 | GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); //// | |
7425 | GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); //// | |
7426 | GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); //// | |
7427 | GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); //// | |
7428 | GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); //// | |
7429 | GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE); | |
7430 | GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); //// | |
7431 | GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE); | |
7432 | GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); // | |
7433 | GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE); | |
7434 | GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); //// | |
7435 | GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); //// | |
7436 | GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); //// | |
7437 | GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); //// | |
7438 | GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); //// | |
7439 | ||
6a6ae23f | 7440 | /* SPE load and stores */ |
76db3ba4 | 7441 | static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh) |
6a6ae23f AJ |
7442 | { |
7443 | target_ulong uimm = rB(ctx->opcode); | |
7444 | ||
76db3ba4 | 7445 | if (rA(ctx->opcode) == 0) { |
6a6ae23f | 7446 | tcg_gen_movi_tl(EA, uimm << sh); |
76db3ba4 | 7447 | } else { |
6a6ae23f | 7448 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh); |
76db3ba4 AJ |
7449 | #if defined(TARGET_PPC64) |
7450 | if (!ctx->sf_mode) { | |
7451 | tcg_gen_ext32u_tl(EA, EA); | |
7452 | } | |
7453 | #endif | |
7454 | } | |
0487d6a8 | 7455 | } |
6a6ae23f AJ |
7456 | |
7457 | static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr) | |
7458 | { | |
7459 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7460 | gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
6a6ae23f AJ |
7461 | #else |
7462 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
76db3ba4 | 7463 | gen_qemu_ld64(ctx, t0, addr); |
6a6ae23f AJ |
7464 | tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0); |
7465 | tcg_gen_shri_i64(t0, t0, 32); | |
7466 | tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0); | |
7467 | tcg_temp_free_i64(t0); | |
7468 | #endif | |
0487d6a8 | 7469 | } |
6a6ae23f AJ |
7470 | |
7471 | static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr) | |
7472 | { | |
0487d6a8 | 7473 | #if defined(TARGET_PPC64) |
6a6ae23f | 7474 | TCGv t0 = tcg_temp_new(); |
76db3ba4 | 7475 | gen_qemu_ld32u(ctx, t0, addr); |
6a6ae23f | 7476 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
76db3ba4 AJ |
7477 | gen_addr_add(ctx, addr, addr, 4); |
7478 | gen_qemu_ld32u(ctx, t0, addr); | |
6a6ae23f AJ |
7479 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7480 | tcg_temp_free(t0); | |
7481 | #else | |
76db3ba4 AJ |
7482 | gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7483 | gen_addr_add(ctx, addr, addr, 4); | |
7484 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f | 7485 | #endif |
0487d6a8 | 7486 | } |
6a6ae23f AJ |
7487 | |
7488 | static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr) | |
7489 | { | |
7490 | TCGv t0 = tcg_temp_new(); | |
7491 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7492 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7493 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7494 | gen_addr_add(ctx, addr, addr, 2); |
7495 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7496 | tcg_gen_shli_tl(t0, t0, 32); |
7497 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7498 | gen_addr_add(ctx, addr, addr, 2); |
7499 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7500 | tcg_gen_shli_tl(t0, t0, 16); |
7501 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7502 | gen_addr_add(ctx, addr, addr, 2); |
7503 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7504 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7505 | #else |
76db3ba4 | 7506 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7507 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7508 | gen_addr_add(ctx, addr, addr, 2); |
7509 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7510 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7511 | gen_addr_add(ctx, addr, addr, 2); |
7512 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7513 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7514 | gen_addr_add(ctx, addr, addr, 2); |
7515 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f | 7516 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
0487d6a8 | 7517 | #endif |
6a6ae23f | 7518 | tcg_temp_free(t0); |
0487d6a8 JM |
7519 | } |
7520 | ||
6a6ae23f AJ |
7521 | static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr) |
7522 | { | |
7523 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7524 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7525 | #if defined(TARGET_PPC64) |
7526 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); | |
7527 | tcg_gen_shli_tl(t0, t0, 16); | |
7528 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7529 | #else | |
7530 | tcg_gen_shli_tl(t0, t0, 16); | |
7531 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7532 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7533 | #endif | |
7534 | tcg_temp_free(t0); | |
0487d6a8 JM |
7535 | } |
7536 | ||
6a6ae23f AJ |
7537 | static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr) |
7538 | { | |
7539 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7540 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7541 | #if defined(TARGET_PPC64) |
7542 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7543 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7544 | #else | |
7545 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7546 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7547 | #endif | |
7548 | tcg_temp_free(t0); | |
0487d6a8 JM |
7549 | } |
7550 | ||
6a6ae23f AJ |
7551 | static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr) |
7552 | { | |
7553 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7554 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f AJ |
7555 | #if defined(TARGET_PPC64) |
7556 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); | |
7557 | tcg_gen_ext32u_tl(t0, t0); | |
7558 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7559 | #else | |
7560 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7561 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7562 | #endif | |
7563 | tcg_temp_free(t0); | |
7564 | } | |
7565 | ||
7566 | static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr) | |
7567 | { | |
7568 | TCGv t0 = tcg_temp_new(); | |
7569 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7570 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7571 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
76db3ba4 AJ |
7572 | gen_addr_add(ctx, addr, addr, 2); |
7573 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7574 | tcg_gen_shli_tl(t0, t0, 16); |
7575 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7576 | #else | |
76db3ba4 | 7577 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f | 7578 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
76db3ba4 AJ |
7579 | gen_addr_add(ctx, addr, addr, 2); |
7580 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7581 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7582 | #endif | |
7583 | tcg_temp_free(t0); | |
7584 | } | |
7585 | ||
7586 | static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr) | |
7587 | { | |
7588 | #if defined(TARGET_PPC64) | |
7589 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 AJ |
7590 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); |
7591 | gen_addr_add(ctx, addr, addr, 2); | |
7592 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7593 | tcg_gen_shli_tl(t0, t0, 32); |
7594 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7595 | tcg_temp_free(t0); | |
7596 | #else | |
76db3ba4 AJ |
7597 | gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7598 | gen_addr_add(ctx, addr, addr, 2); | |
7599 | gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7600 | #endif |
7601 | } | |
7602 | ||
7603 | static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr) | |
7604 | { | |
7605 | #if defined(TARGET_PPC64) | |
7606 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7607 | gen_qemu_ld16s(ctx, t0, addr); |
6a6ae23f | 7608 | tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0); |
76db3ba4 AJ |
7609 | gen_addr_add(ctx, addr, addr, 2); |
7610 | gen_qemu_ld16s(ctx, t0, addr); | |
6a6ae23f AJ |
7611 | tcg_gen_shli_tl(t0, t0, 32); |
7612 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7613 | tcg_temp_free(t0); | |
7614 | #else | |
76db3ba4 AJ |
7615 | gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr); |
7616 | gen_addr_add(ctx, addr, addr, 2); | |
7617 | gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr); | |
6a6ae23f AJ |
7618 | #endif |
7619 | } | |
7620 | ||
7621 | static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr) | |
7622 | { | |
7623 | TCGv t0 = tcg_temp_new(); | |
76db3ba4 | 7624 | gen_qemu_ld32u(ctx, t0, addr); |
0487d6a8 | 7625 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7626 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32); |
7627 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7628 | #else | |
7629 | tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0); | |
7630 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
7631 | #endif | |
7632 | tcg_temp_free(t0); | |
7633 | } | |
7634 | ||
7635 | static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr) | |
7636 | { | |
7637 | TCGv t0 = tcg_temp_new(); | |
7638 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7639 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7640 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48); |
7641 | tcg_gen_shli_tl(t0, t0, 32); | |
7642 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7643 | gen_addr_add(ctx, addr, addr, 2); |
7644 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7645 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); |
7646 | tcg_gen_shli_tl(t0, t0, 16); | |
7647 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0); | |
7648 | #else | |
76db3ba4 | 7649 | gen_qemu_ld16u(ctx, t0, addr); |
6a6ae23f AJ |
7650 | tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16); |
7651 | tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
76db3ba4 AJ |
7652 | gen_addr_add(ctx, addr, addr, 2); |
7653 | gen_qemu_ld16u(ctx, t0, addr); | |
6a6ae23f AJ |
7654 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16); |
7655 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0); | |
0487d6a8 | 7656 | #endif |
6a6ae23f AJ |
7657 | tcg_temp_free(t0); |
7658 | } | |
7659 | ||
7660 | static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr) | |
7661 | { | |
7662 | #if defined(TARGET_PPC64) | |
76db3ba4 | 7663 | gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
0487d6a8 | 7664 | #else |
6a6ae23f AJ |
7665 | TCGv_i64 t0 = tcg_temp_new_i64(); |
7666 | tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]); | |
76db3ba4 | 7667 | gen_qemu_st64(ctx, t0, addr); |
6a6ae23f AJ |
7668 | tcg_temp_free_i64(t0); |
7669 | #endif | |
7670 | } | |
7671 | ||
7672 | static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr) | |
7673 | { | |
0487d6a8 | 7674 | #if defined(TARGET_PPC64) |
6a6ae23f AJ |
7675 | TCGv t0 = tcg_temp_new(); |
7676 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7677 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7678 | tcg_temp_free(t0); |
7679 | #else | |
76db3ba4 | 7680 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7681 | #endif |
76db3ba4 AJ |
7682 | gen_addr_add(ctx, addr, addr, 4); |
7683 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7684 | } |
7685 | ||
7686 | static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr) | |
7687 | { | |
7688 | TCGv t0 = tcg_temp_new(); | |
7689 | #if defined(TARGET_PPC64) | |
7690 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7691 | #else | |
7692 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7693 | #endif | |
76db3ba4 AJ |
7694 | gen_qemu_st16(ctx, t0, addr); |
7695 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f AJ |
7696 | #if defined(TARGET_PPC64) |
7697 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7698 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7699 | #else |
76db3ba4 | 7700 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7701 | #endif |
76db3ba4 | 7702 | gen_addr_add(ctx, addr, addr, 2); |
6a6ae23f | 7703 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7704 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f | 7705 | tcg_temp_free(t0); |
76db3ba4 AJ |
7706 | gen_addr_add(ctx, addr, addr, 2); |
7707 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7708 | } |
7709 | ||
7710 | static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr) | |
7711 | { | |
7712 | TCGv t0 = tcg_temp_new(); | |
7713 | #if defined(TARGET_PPC64) | |
7714 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48); | |
7715 | #else | |
7716 | tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16); | |
7717 | #endif | |
76db3ba4 AJ |
7718 | gen_qemu_st16(ctx, t0, addr); |
7719 | gen_addr_add(ctx, addr, addr, 2); | |
6a6ae23f | 7720 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16); |
76db3ba4 | 7721 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7722 | tcg_temp_free(t0); |
7723 | } | |
7724 | ||
7725 | static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr) | |
7726 | { | |
7727 | #if defined(TARGET_PPC64) | |
7728 | TCGv t0 = tcg_temp_new(); | |
7729 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7730 | gen_qemu_st16(ctx, t0, addr); |
6a6ae23f AJ |
7731 | tcg_temp_free(t0); |
7732 | #else | |
76db3ba4 | 7733 | gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f | 7734 | #endif |
76db3ba4 AJ |
7735 | gen_addr_add(ctx, addr, addr, 2); |
7736 | gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr); | |
6a6ae23f AJ |
7737 | } |
7738 | ||
7739 | static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr) | |
7740 | { | |
7741 | #if defined(TARGET_PPC64) | |
7742 | TCGv t0 = tcg_temp_new(); | |
7743 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32); | |
76db3ba4 | 7744 | gen_qemu_st32(ctx, t0, addr); |
6a6ae23f AJ |
7745 | tcg_temp_free(t0); |
7746 | #else | |
76db3ba4 | 7747 | gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7748 | #endif |
7749 | } | |
7750 | ||
7751 | static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr) | |
7752 | { | |
76db3ba4 | 7753 | gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr); |
6a6ae23f AJ |
7754 | } |
7755 | ||
7756 | #define GEN_SPEOP_LDST(name, opc2, sh) \ | |
99e300ef BS |
7757 | GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE); \ |
7758 | \ | |
7759 | static void glue(gen_, name)(DisasContext *ctx) \ | |
6a6ae23f AJ |
7760 | { \ |
7761 | TCGv t0; \ | |
7762 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7763 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
6a6ae23f AJ |
7764 | return; \ |
7765 | } \ | |
76db3ba4 | 7766 | gen_set_access_type(ctx, ACCESS_INT); \ |
6a6ae23f AJ |
7767 | t0 = tcg_temp_new(); \ |
7768 | if (Rc(ctx->opcode)) { \ | |
76db3ba4 | 7769 | gen_addr_spe_imm_index(ctx, t0, sh); \ |
6a6ae23f | 7770 | } else { \ |
76db3ba4 | 7771 | gen_addr_reg_index(ctx, t0); \ |
6a6ae23f AJ |
7772 | } \ |
7773 | gen_op_##name(ctx, t0); \ | |
7774 | tcg_temp_free(t0); \ | |
7775 | } | |
7776 | ||
7777 | GEN_SPEOP_LDST(evldd, 0x00, 3); | |
7778 | GEN_SPEOP_LDST(evldw, 0x01, 3); | |
7779 | GEN_SPEOP_LDST(evldh, 0x02, 3); | |
7780 | GEN_SPEOP_LDST(evlhhesplat, 0x04, 1); | |
7781 | GEN_SPEOP_LDST(evlhhousplat, 0x06, 1); | |
7782 | GEN_SPEOP_LDST(evlhhossplat, 0x07, 1); | |
7783 | GEN_SPEOP_LDST(evlwhe, 0x08, 2); | |
7784 | GEN_SPEOP_LDST(evlwhou, 0x0A, 2); | |
7785 | GEN_SPEOP_LDST(evlwhos, 0x0B, 2); | |
7786 | GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2); | |
7787 | GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2); | |
7788 | ||
7789 | GEN_SPEOP_LDST(evstdd, 0x10, 3); | |
7790 | GEN_SPEOP_LDST(evstdw, 0x11, 3); | |
7791 | GEN_SPEOP_LDST(evstdh, 0x12, 3); | |
7792 | GEN_SPEOP_LDST(evstwhe, 0x18, 2); | |
7793 | GEN_SPEOP_LDST(evstwho, 0x1A, 2); | |
7794 | GEN_SPEOP_LDST(evstwwe, 0x1C, 2); | |
7795 | GEN_SPEOP_LDST(evstwwo, 0x1E, 2); | |
0487d6a8 JM |
7796 | |
7797 | /* Multiply and add - TODO */ | |
7798 | #if 0 | |
7799 | GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE); | |
7800 | GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE); | |
7801 | GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE); | |
7802 | GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE); | |
7803 | GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE); | |
7804 | GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE); | |
7805 | GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE); | |
7806 | GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE); | |
7807 | GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE); | |
7808 | GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE); | |
7809 | GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE); | |
7810 | GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE); | |
7811 | ||
7812 | GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE); | |
7813 | GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE); | |
7814 | GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE); | |
7815 | GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE); | |
7816 | GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE); | |
7817 | GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE); | |
7818 | GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE); | |
7819 | GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE); | |
7820 | GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE); | |
7821 | GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE); | |
7822 | GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE); | |
7823 | GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE); | |
7824 | GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE); | |
7825 | GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE); | |
7826 | ||
7827 | GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE); | |
7828 | GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE); | |
7829 | GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE); | |
7830 | GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE); | |
7831 | GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE); | |
7832 | GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE); | |
7833 | ||
7834 | GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE); | |
7835 | GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE); | |
7836 | GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE); | |
7837 | GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE); | |
7838 | GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE); | |
7839 | GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE); | |
7840 | GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE); | |
7841 | GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE); | |
7842 | GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE); | |
7843 | GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE); | |
7844 | GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE); | |
7845 | GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE); | |
7846 | ||
7847 | GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE); | |
7848 | GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE); | |
7849 | GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE); | |
7850 | GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE); | |
7851 | GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE); | |
7852 | ||
7853 | GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE); | |
7854 | GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE); | |
7855 | GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE); | |
7856 | GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE); | |
7857 | GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE); | |
7858 | GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE); | |
7859 | GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE); | |
7860 | GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE); | |
7861 | GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE); | |
7862 | GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE); | |
7863 | GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE); | |
7864 | GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE); | |
7865 | ||
7866 | GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE); | |
7867 | GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE); | |
7868 | GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE); | |
7869 | GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE); | |
7870 | GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE); | |
7871 | #endif | |
7872 | ||
7873 | /*** SPE floating-point extension ***/ | |
1c97856d AJ |
7874 | #if defined(TARGET_PPC64) |
7875 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
b068d6a7 | 7876 | static always_inline void gen_##name (DisasContext *ctx) \ |
0487d6a8 | 7877 | { \ |
1c97856d AJ |
7878 | TCGv_i32 t0; \ |
7879 | TCGv t1; \ | |
7880 | t0 = tcg_temp_new_i32(); \ | |
7881 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
7882 | gen_helper_##name(t0, t0); \ | |
7883 | t1 = tcg_temp_new(); \ | |
7884 | tcg_gen_extu_i32_tl(t1, t0); \ | |
7885 | tcg_temp_free_i32(t0); \ | |
7886 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
7887 | 0xFFFFFFFF00000000ULL); \ | |
7888 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
7889 | tcg_temp_free(t1); \ | |
0487d6a8 | 7890 | } |
1c97856d AJ |
7891 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
7892 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7893 | { \ | |
7894 | TCGv_i32 t0; \ | |
7895 | TCGv t1; \ | |
7896 | t0 = tcg_temp_new_i32(); \ | |
7897 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
7898 | t1 = tcg_temp_new(); \ | |
7899 | tcg_gen_extu_i32_tl(t1, t0); \ | |
7900 | tcg_temp_free_i32(t0); \ | |
7901 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
7902 | 0xFFFFFFFF00000000ULL); \ | |
7903 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \ | |
7904 | tcg_temp_free(t1); \ | |
7905 | } | |
7906 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
7907 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7908 | { \ | |
7909 | TCGv_i32 t0 = tcg_temp_new_i32(); \ | |
7910 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
7911 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ | |
7912 | tcg_temp_free_i32(t0); \ | |
7913 | } | |
7914 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
7915 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7916 | { \ | |
7917 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
7918 | } | |
7919 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
57951c27 AJ |
7920 | static always_inline void gen_##name (DisasContext *ctx) \ |
7921 | { \ | |
1c97856d AJ |
7922 | TCGv_i32 t0, t1; \ |
7923 | TCGv_i64 t2; \ | |
57951c27 | 7924 | if (unlikely(!ctx->spe_enabled)) { \ |
e06fcd75 | 7925 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7926 | return; \ |
7927 | } \ | |
1c97856d AJ |
7928 | t0 = tcg_temp_new_i32(); \ |
7929 | t1 = tcg_temp_new_i32(); \ | |
7930 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
7931 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7932 | gen_helper_##name(t0, t0, t1); \ | |
7933 | tcg_temp_free_i32(t1); \ | |
7934 | t2 = tcg_temp_new(); \ | |
7935 | tcg_gen_extu_i32_tl(t2, t0); \ | |
7936 | tcg_temp_free_i32(t0); \ | |
7937 | tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \ | |
7938 | 0xFFFFFFFF00000000ULL); \ | |
7939 | tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \ | |
7940 | tcg_temp_free(t2); \ | |
57951c27 | 7941 | } |
1c97856d | 7942 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ |
57951c27 AJ |
7943 | static always_inline void gen_##name (DisasContext *ctx) \ |
7944 | { \ | |
7945 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7946 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7947 | return; \ |
7948 | } \ | |
1c97856d AJ |
7949 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ |
7950 | cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 7951 | } |
1c97856d | 7952 | #define GEN_SPEFPUOP_COMP_32(name) \ |
57951c27 AJ |
7953 | static always_inline void gen_##name (DisasContext *ctx) \ |
7954 | { \ | |
1c97856d | 7955 | TCGv_i32 t0, t1; \ |
57951c27 | 7956 | if (unlikely(!ctx->spe_enabled)) { \ |
e06fcd75 | 7957 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
57951c27 AJ |
7958 | return; \ |
7959 | } \ | |
1c97856d AJ |
7960 | t0 = tcg_temp_new_i32(); \ |
7961 | t1 = tcg_temp_new_i32(); \ | |
7962 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \ | |
7963 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \ | |
7964 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ | |
7965 | tcg_temp_free_i32(t0); \ | |
7966 | tcg_temp_free_i32(t1); \ | |
7967 | } | |
7968 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
7969 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7970 | { \ | |
7971 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 7972 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
7973 | return; \ |
7974 | } \ | |
7975 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
7976 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
7977 | } | |
7978 | #else | |
7979 | #define GEN_SPEFPUOP_CONV_32_32(name) \ | |
7980 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7981 | { \ | |
7982 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
57951c27 | 7983 | } |
1c97856d AJ |
7984 | #define GEN_SPEFPUOP_CONV_32_64(name) \ |
7985 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7986 | { \ | |
7987 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
7988 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
7989 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], t0); \ | |
7990 | tcg_temp_free_i64(t0); \ | |
7991 | } | |
7992 | #define GEN_SPEFPUOP_CONV_64_32(name) \ | |
7993 | static always_inline void gen_##name (DisasContext *ctx) \ | |
7994 | { \ | |
7995 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
7996 | gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \ | |
7997 | gen_store_gpr64(rD(ctx->opcode), t0); \ | |
7998 | tcg_temp_free_i64(t0); \ | |
7999 | } | |
8000 | #define GEN_SPEFPUOP_CONV_64_64(name) \ | |
8001 | static always_inline void gen_##name (DisasContext *ctx) \ | |
8002 | { \ | |
8003 | TCGv_i64 t0 = tcg_temp_new_i64(); \ | |
8004 | gen_load_gpr64(t0, rB(ctx->opcode)); \ | |
8005 | gen_helper_##name(t0, t0); \ | |
8006 | gen_store_gpr64(rD(ctx->opcode), t0); \ | |
8007 | tcg_temp_free_i64(t0); \ | |
8008 | } | |
8009 | #define GEN_SPEFPUOP_ARITH2_32_32(name) \ | |
8010 | static always_inline void gen_##name (DisasContext *ctx) \ | |
8011 | { \ | |
8012 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 8013 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
8014 | return; \ |
8015 | } \ | |
8016 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], \ | |
8017 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
8018 | } | |
8019 | #define GEN_SPEFPUOP_ARITH2_64_64(name) \ | |
8020 | static always_inline void gen_##name (DisasContext *ctx) \ | |
8021 | { \ | |
8022 | TCGv_i64 t0, t1; \ | |
8023 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 8024 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
8025 | return; \ |
8026 | } \ | |
8027 | t0 = tcg_temp_new_i64(); \ | |
8028 | t1 = tcg_temp_new_i64(); \ | |
8029 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8030 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8031 | gen_helper_##name(t0, t0, t1); \ | |
8032 | gen_store_gpr64(rD(ctx->opcode), t0); \ | |
8033 | tcg_temp_free_i64(t0); \ | |
8034 | tcg_temp_free_i64(t1); \ | |
8035 | } | |
8036 | #define GEN_SPEFPUOP_COMP_32(name) \ | |
8037 | static always_inline void gen_##name (DisasContext *ctx) \ | |
8038 | { \ | |
8039 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 8040 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
8041 | return; \ |
8042 | } \ | |
8043 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \ | |
8044 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \ | |
8045 | } | |
8046 | #define GEN_SPEFPUOP_COMP_64(name) \ | |
8047 | static always_inline void gen_##name (DisasContext *ctx) \ | |
8048 | { \ | |
8049 | TCGv_i64 t0, t1; \ | |
8050 | if (unlikely(!ctx->spe_enabled)) { \ | |
e06fcd75 | 8051 | gen_exception(ctx, POWERPC_EXCP_APU); \ |
1c97856d AJ |
8052 | return; \ |
8053 | } \ | |
8054 | t0 = tcg_temp_new_i64(); \ | |
8055 | t1 = tcg_temp_new_i64(); \ | |
8056 | gen_load_gpr64(t0, rA(ctx->opcode)); \ | |
8057 | gen_load_gpr64(t1, rB(ctx->opcode)); \ | |
8058 | gen_helper_##name(cpu_crf[crfD(ctx->opcode)], t0, t1); \ | |
8059 | tcg_temp_free_i64(t0); \ | |
8060 | tcg_temp_free_i64(t1); \ | |
8061 | } | |
8062 | #endif | |
57951c27 | 8063 | |
0487d6a8 JM |
8064 | /* Single precision floating-point vectors operations */ |
8065 | /* Arithmetic */ | |
1c97856d AJ |
8066 | GEN_SPEFPUOP_ARITH2_64_64(evfsadd); |
8067 | GEN_SPEFPUOP_ARITH2_64_64(evfssub); | |
8068 | GEN_SPEFPUOP_ARITH2_64_64(evfsmul); | |
8069 | GEN_SPEFPUOP_ARITH2_64_64(evfsdiv); | |
8070 | static always_inline void gen_evfsabs (DisasContext *ctx) | |
8071 | { | |
8072 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8073 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8074 | return; |
8075 | } | |
8076 | #if defined(TARGET_PPC64) | |
8077 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL); | |
8078 | #else | |
8079 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000); | |
8080 | tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
8081 | #endif | |
8082 | } | |
8083 | static always_inline void gen_evfsnabs (DisasContext *ctx) | |
8084 | { | |
8085 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8086 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8087 | return; |
8088 | } | |
8089 | #if defined(TARGET_PPC64) | |
8090 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); | |
8091 | #else | |
8092 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); | |
8093 | tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
8094 | #endif | |
8095 | } | |
8096 | static always_inline void gen_evfsneg (DisasContext *ctx) | |
8097 | { | |
8098 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8099 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8100 | return; |
8101 | } | |
8102 | #if defined(TARGET_PPC64) | |
8103 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL); | |
8104 | #else | |
8105 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); | |
8106 | tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
8107 | #endif | |
8108 | } | |
8109 | ||
0487d6a8 | 8110 | /* Conversion */ |
1c97856d AJ |
8111 | GEN_SPEFPUOP_CONV_64_64(evfscfui); |
8112 | GEN_SPEFPUOP_CONV_64_64(evfscfsi); | |
8113 | GEN_SPEFPUOP_CONV_64_64(evfscfuf); | |
8114 | GEN_SPEFPUOP_CONV_64_64(evfscfsf); | |
8115 | GEN_SPEFPUOP_CONV_64_64(evfsctui); | |
8116 | GEN_SPEFPUOP_CONV_64_64(evfsctsi); | |
8117 | GEN_SPEFPUOP_CONV_64_64(evfsctuf); | |
8118 | GEN_SPEFPUOP_CONV_64_64(evfsctsf); | |
8119 | GEN_SPEFPUOP_CONV_64_64(evfsctuiz); | |
8120 | GEN_SPEFPUOP_CONV_64_64(evfsctsiz); | |
8121 | ||
0487d6a8 | 8122 | /* Comparison */ |
1c97856d AJ |
8123 | GEN_SPEFPUOP_COMP_64(evfscmpgt); |
8124 | GEN_SPEFPUOP_COMP_64(evfscmplt); | |
8125 | GEN_SPEFPUOP_COMP_64(evfscmpeq); | |
8126 | GEN_SPEFPUOP_COMP_64(evfststgt); | |
8127 | GEN_SPEFPUOP_COMP_64(evfststlt); | |
8128 | GEN_SPEFPUOP_COMP_64(evfststeq); | |
0487d6a8 JM |
8129 | |
8130 | /* Opcodes definitions */ | |
40569b7e AJ |
8131 | GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPE_SINGLE); // |
8132 | GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // | |
8133 | GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPE_SINGLE); // | |
8134 | GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPE_SINGLE); // | |
8135 | GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPE_SINGLE); // | |
8136 | GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPE_SINGLE); // | |
8137 | GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8138 | GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8139 | GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8140 | GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8141 | GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8142 | GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPE_SINGLE); // | |
8143 | GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPE_SINGLE); // | |
8144 | GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8145 | |
8146 | /* Single precision floating-point operations */ | |
8147 | /* Arithmetic */ | |
1c97856d AJ |
8148 | GEN_SPEFPUOP_ARITH2_32_32(efsadd); |
8149 | GEN_SPEFPUOP_ARITH2_32_32(efssub); | |
8150 | GEN_SPEFPUOP_ARITH2_32_32(efsmul); | |
8151 | GEN_SPEFPUOP_ARITH2_32_32(efsdiv); | |
8152 | static always_inline void gen_efsabs (DisasContext *ctx) | |
8153 | { | |
8154 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8155 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8156 | return; |
8157 | } | |
8158 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL); | |
8159 | } | |
8160 | static always_inline void gen_efsnabs (DisasContext *ctx) | |
8161 | { | |
8162 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8163 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8164 | return; |
8165 | } | |
8166 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); | |
8167 | } | |
8168 | static always_inline void gen_efsneg (DisasContext *ctx) | |
8169 | { | |
8170 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8171 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8172 | return; |
8173 | } | |
8174 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000); | |
8175 | } | |
8176 | ||
0487d6a8 | 8177 | /* Conversion */ |
1c97856d AJ |
8178 | GEN_SPEFPUOP_CONV_32_32(efscfui); |
8179 | GEN_SPEFPUOP_CONV_32_32(efscfsi); | |
8180 | GEN_SPEFPUOP_CONV_32_32(efscfuf); | |
8181 | GEN_SPEFPUOP_CONV_32_32(efscfsf); | |
8182 | GEN_SPEFPUOP_CONV_32_32(efsctui); | |
8183 | GEN_SPEFPUOP_CONV_32_32(efsctsi); | |
8184 | GEN_SPEFPUOP_CONV_32_32(efsctuf); | |
8185 | GEN_SPEFPUOP_CONV_32_32(efsctsf); | |
8186 | GEN_SPEFPUOP_CONV_32_32(efsctuiz); | |
8187 | GEN_SPEFPUOP_CONV_32_32(efsctsiz); | |
8188 | GEN_SPEFPUOP_CONV_32_64(efscfd); | |
8189 | ||
0487d6a8 | 8190 | /* Comparison */ |
1c97856d AJ |
8191 | GEN_SPEFPUOP_COMP_32(efscmpgt); |
8192 | GEN_SPEFPUOP_COMP_32(efscmplt); | |
8193 | GEN_SPEFPUOP_COMP_32(efscmpeq); | |
8194 | GEN_SPEFPUOP_COMP_32(efststgt); | |
8195 | GEN_SPEFPUOP_COMP_32(efststlt); | |
8196 | GEN_SPEFPUOP_COMP_32(efststeq); | |
0487d6a8 JM |
8197 | |
8198 | /* Opcodes definitions */ | |
40569b7e AJ |
8199 | GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPE_SINGLE); // |
8200 | GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // | |
8201 | GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPE_SINGLE); // | |
8202 | GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPE_SINGLE); // | |
8203 | GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPE_SINGLE); // | |
8204 | GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPE_SINGLE); // | |
8205 | GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8206 | GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8207 | GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8208 | GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8209 | GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8210 | GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPE_SINGLE); // | |
8211 | GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPE_SINGLE); // | |
8212 | GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPE_SINGLE); // | |
0487d6a8 JM |
8213 | |
8214 | /* Double precision floating-point operations */ | |
8215 | /* Arithmetic */ | |
1c97856d AJ |
8216 | GEN_SPEFPUOP_ARITH2_64_64(efdadd); |
8217 | GEN_SPEFPUOP_ARITH2_64_64(efdsub); | |
8218 | GEN_SPEFPUOP_ARITH2_64_64(efdmul); | |
8219 | GEN_SPEFPUOP_ARITH2_64_64(efddiv); | |
8220 | static always_inline void gen_efdabs (DisasContext *ctx) | |
8221 | { | |
8222 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8223 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8224 | return; |
8225 | } | |
8226 | #if defined(TARGET_PPC64) | |
8227 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL); | |
8228 | #else | |
8229 | tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000); | |
8230 | #endif | |
8231 | } | |
8232 | static always_inline void gen_efdnabs (DisasContext *ctx) | |
8233 | { | |
8234 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8235 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8236 | return; |
8237 | } | |
8238 | #if defined(TARGET_PPC64) | |
8239 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); | |
8240 | #else | |
8241 | tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
8242 | #endif | |
8243 | } | |
8244 | static always_inline void gen_efdneg (DisasContext *ctx) | |
8245 | { | |
8246 | if (unlikely(!ctx->spe_enabled)) { | |
e06fcd75 | 8247 | gen_exception(ctx, POWERPC_EXCP_APU); |
1c97856d AJ |
8248 | return; |
8249 | } | |
8250 | #if defined(TARGET_PPC64) | |
8251 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL); | |
8252 | #else | |
8253 | tcg_gen_xori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000); | |
8254 | #endif | |
8255 | } | |
8256 | ||
0487d6a8 | 8257 | /* Conversion */ |
1c97856d AJ |
8258 | GEN_SPEFPUOP_CONV_64_32(efdcfui); |
8259 | GEN_SPEFPUOP_CONV_64_32(efdcfsi); | |
8260 | GEN_SPEFPUOP_CONV_64_32(efdcfuf); | |
8261 | GEN_SPEFPUOP_CONV_64_32(efdcfsf); | |
8262 | GEN_SPEFPUOP_CONV_32_64(efdctui); | |
8263 | GEN_SPEFPUOP_CONV_32_64(efdctsi); | |
8264 | GEN_SPEFPUOP_CONV_32_64(efdctuf); | |
8265 | GEN_SPEFPUOP_CONV_32_64(efdctsf); | |
8266 | GEN_SPEFPUOP_CONV_32_64(efdctuiz); | |
8267 | GEN_SPEFPUOP_CONV_32_64(efdctsiz); | |
8268 | GEN_SPEFPUOP_CONV_64_32(efdcfs); | |
8269 | GEN_SPEFPUOP_CONV_64_64(efdcfuid); | |
8270 | GEN_SPEFPUOP_CONV_64_64(efdcfsid); | |
8271 | GEN_SPEFPUOP_CONV_64_64(efdctuidz); | |
8272 | GEN_SPEFPUOP_CONV_64_64(efdctsidz); | |
0487d6a8 | 8273 | |
0487d6a8 | 8274 | /* Comparison */ |
1c97856d AJ |
8275 | GEN_SPEFPUOP_COMP_64(efdcmpgt); |
8276 | GEN_SPEFPUOP_COMP_64(efdcmplt); | |
8277 | GEN_SPEFPUOP_COMP_64(efdcmpeq); | |
8278 | GEN_SPEFPUOP_COMP_64(efdtstgt); | |
8279 | GEN_SPEFPUOP_COMP_64(efdtstlt); | |
8280 | GEN_SPEFPUOP_COMP_64(efdtsteq); | |
0487d6a8 JM |
8281 | |
8282 | /* Opcodes definitions */ | |
40569b7e AJ |
8283 | GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // |
8284 | GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8285 | GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // | |
8286 | GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPE_DOUBLE); // | |
8287 | GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPE_DOUBLE); // | |
8288 | GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8289 | GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // | |
8290 | GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // | |
8291 | GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8292 | GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8293 | GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8294 | GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8295 | GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8296 | GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPE_DOUBLE); // | |
8297 | GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // | |
8298 | GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPE_DOUBLE); // | |
0487d6a8 | 8299 | |
79aceca5 FB |
8300 | /* End opcode list */ |
8301 | GEN_OPCODE_MARK(end); | |
8302 | ||
3fc6c082 | 8303 | #include "translate_init.c" |
0411a972 | 8304 | #include "helper_regs.h" |
79aceca5 | 8305 | |
9a64fbe4 | 8306 | /*****************************************************************************/ |
3fc6c082 | 8307 | /* Misc PowerPC helpers */ |
36081602 JM |
8308 | void cpu_dump_state (CPUState *env, FILE *f, |
8309 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
8310 | int flags) | |
79aceca5 | 8311 | { |
3fc6c082 FB |
8312 | #define RGPL 4 |
8313 | #define RFPL 4 | |
3fc6c082 | 8314 | |
79aceca5 FB |
8315 | int i; |
8316 | ||
077fc206 | 8317 | cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n", |
3d7b417e | 8318 | env->nip, env->lr, env->ctr, env->xer); |
6b542af7 JM |
8319 | cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n", |
8320 | env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx); | |
d9bce9d9 | 8321 | #if !defined(NO_TIMER_DUMP) |
077fc206 | 8322 | cpu_fprintf(f, "TB %08x %08x " |
76a66253 JM |
8323 | #if !defined(CONFIG_USER_ONLY) |
8324 | "DECR %08x" | |
8325 | #endif | |
8326 | "\n", | |
077fc206 | 8327 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
8328 | #if !defined(CONFIG_USER_ONLY) |
8329 | , cpu_ppc_load_decr(env) | |
8330 | #endif | |
8331 | ); | |
077fc206 | 8332 | #endif |
76a66253 | 8333 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
8334 | if ((i & (RGPL - 1)) == 0) |
8335 | cpu_fprintf(f, "GPR%02d", i); | |
6b542af7 | 8336 | cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i)); |
3fc6c082 | 8337 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 8338 | cpu_fprintf(f, "\n"); |
76a66253 | 8339 | } |
3fc6c082 | 8340 | cpu_fprintf(f, "CR "); |
76a66253 | 8341 | for (i = 0; i < 8; i++) |
7fe48483 FB |
8342 | cpu_fprintf(f, "%01x", env->crf[i]); |
8343 | cpu_fprintf(f, " ["); | |
76a66253 JM |
8344 | for (i = 0; i < 8; i++) { |
8345 | char a = '-'; | |
8346 | if (env->crf[i] & 0x08) | |
8347 | a = 'L'; | |
8348 | else if (env->crf[i] & 0x04) | |
8349 | a = 'G'; | |
8350 | else if (env->crf[i] & 0x02) | |
8351 | a = 'E'; | |
7fe48483 | 8352 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 8353 | } |
6b542af7 | 8354 | cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve); |
3fc6c082 FB |
8355 | for (i = 0; i < 32; i++) { |
8356 | if ((i & (RFPL - 1)) == 0) | |
8357 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 8358 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 8359 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 8360 | cpu_fprintf(f, "\n"); |
79aceca5 | 8361 | } |
7889270a | 8362 | cpu_fprintf(f, "FPSCR %08x\n", env->fpscr); |
f2e63a42 | 8363 | #if !defined(CONFIG_USER_ONLY) |
6b542af7 | 8364 | cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n", |
3fc6c082 | 8365 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1); |
f2e63a42 | 8366 | #endif |
79aceca5 | 8367 | |
3fc6c082 FB |
8368 | #undef RGPL |
8369 | #undef RFPL | |
79aceca5 FB |
8370 | } |
8371 | ||
76a66253 JM |
8372 | void cpu_dump_statistics (CPUState *env, FILE*f, |
8373 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), | |
8374 | int flags) | |
8375 | { | |
8376 | #if defined(DO_PPC_STATISTICS) | |
8377 | opc_handler_t **t1, **t2, **t3, *handler; | |
8378 | int op1, op2, op3; | |
8379 | ||
8380 | t1 = env->opcodes; | |
8381 | for (op1 = 0; op1 < 64; op1++) { | |
8382 | handler = t1[op1]; | |
8383 | if (is_indirect_opcode(handler)) { | |
8384 | t2 = ind_table(handler); | |
8385 | for (op2 = 0; op2 < 32; op2++) { | |
8386 | handler = t2[op2]; | |
8387 | if (is_indirect_opcode(handler)) { | |
8388 | t3 = ind_table(handler); | |
8389 | for (op3 = 0; op3 < 32; op3++) { | |
8390 | handler = t3[op3]; | |
8391 | if (handler->count == 0) | |
8392 | continue; | |
8393 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
8394 | "%016llx %lld\n", | |
8395 | op1, op2, op3, op1, (op3 << 5) | op2, | |
8396 | handler->oname, | |
8397 | handler->count, handler->count); | |
8398 | } | |
8399 | } else { | |
8400 | if (handler->count == 0) | |
8401 | continue; | |
8402 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
8403 | "%016llx %lld\n", | |
8404 | op1, op2, op1, op2, handler->oname, | |
8405 | handler->count, handler->count); | |
8406 | } | |
8407 | } | |
8408 | } else { | |
8409 | if (handler->count == 0) | |
8410 | continue; | |
8411 | cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n", | |
8412 | op1, op1, handler->oname, | |
8413 | handler->count, handler->count); | |
8414 | } | |
8415 | } | |
8416 | #endif | |
8417 | } | |
8418 | ||
9a64fbe4 | 8419 | /*****************************************************************************/ |
2cfc5f17 TS |
8420 | static always_inline void gen_intermediate_code_internal (CPUState *env, |
8421 | TranslationBlock *tb, | |
8422 | int search_pc) | |
79aceca5 | 8423 | { |
9fddaa0c | 8424 | DisasContext ctx, *ctxp = &ctx; |
79aceca5 | 8425 | opc_handler_t **table, *handler; |
0fa85d43 | 8426 | target_ulong pc_start; |
79aceca5 | 8427 | uint16_t *gen_opc_end; |
a1d1bb31 | 8428 | CPUBreakpoint *bp; |
79aceca5 | 8429 | int j, lj = -1; |
2e70f6ef PB |
8430 | int num_insns; |
8431 | int max_insns; | |
79aceca5 FB |
8432 | |
8433 | pc_start = tb->pc; | |
79aceca5 | 8434 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
046d6672 | 8435 | ctx.nip = pc_start; |
79aceca5 | 8436 | ctx.tb = tb; |
e1833e1f | 8437 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 8438 | ctx.spr_cb = env->spr_cb; |
76db3ba4 AJ |
8439 | ctx.mem_idx = env->mmu_idx; |
8440 | ctx.access_type = -1; | |
8441 | ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0; | |
d9bce9d9 JM |
8442 | #if defined(TARGET_PPC64) |
8443 | ctx.sf_mode = msr_sf; | |
9a64fbe4 | 8444 | #endif |
3cc62370 | 8445 | ctx.fpu_enabled = msr_fp; |
a9d9eb8f | 8446 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
d26bfc9a JM |
8447 | ctx.spe_enabled = msr_spe; |
8448 | else | |
8449 | ctx.spe_enabled = 0; | |
a9d9eb8f JM |
8450 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
8451 | ctx.altivec_enabled = msr_vr; | |
8452 | else | |
8453 | ctx.altivec_enabled = 0; | |
d26bfc9a | 8454 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 8455 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 8456 | else |
8cbcb4fa | 8457 | ctx.singlestep_enabled = 0; |
d26bfc9a | 8458 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa AJ |
8459 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
8460 | if (unlikely(env->singlestep_enabled)) | |
8461 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; | |
3fc6c082 | 8462 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
8463 | /* Single step trace mode */ |
8464 | msr_se = 1; | |
8465 | #endif | |
2e70f6ef PB |
8466 | num_insns = 0; |
8467 | max_insns = tb->cflags & CF_COUNT_MASK; | |
8468 | if (max_insns == 0) | |
8469 | max_insns = CF_COUNT_MASK; | |
8470 | ||
8471 | gen_icount_start(); | |
9a64fbe4 | 8472 | /* Set env in case of segfault during code fetch */ |
e1833e1f | 8473 | while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) { |
c0ce998e AL |
8474 | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { |
8475 | TAILQ_FOREACH(bp, &env->breakpoints, entry) { | |
a1d1bb31 | 8476 | if (bp->pc == ctx.nip) { |
e06fcd75 | 8477 | gen_debug_exception(ctxp); |
ea4e754f FB |
8478 | break; |
8479 | } | |
8480 | } | |
8481 | } | |
76a66253 | 8482 | if (unlikely(search_pc)) { |
79aceca5 FB |
8483 | j = gen_opc_ptr - gen_opc_buf; |
8484 | if (lj < j) { | |
8485 | lj++; | |
8486 | while (lj < j) | |
8487 | gen_opc_instr_start[lj++] = 0; | |
79aceca5 | 8488 | } |
af4b6c54 AJ |
8489 | gen_opc_pc[lj] = ctx.nip; |
8490 | gen_opc_instr_start[lj] = 1; | |
8491 | gen_opc_icount[lj] = num_insns; | |
79aceca5 | 8492 | } |
d12d51d5 AL |
8493 | LOG_DISAS("----------------\n"); |
8494 | LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n", | |
8495 | ctx.nip, ctx.mem_idx, (int)msr_ir); | |
2e70f6ef PB |
8496 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
8497 | gen_io_start(); | |
76db3ba4 | 8498 | if (unlikely(ctx.le_mode)) { |
056401ea JM |
8499 | ctx.opcode = bswap32(ldl_code(ctx.nip)); |
8500 | } else { | |
8501 | ctx.opcode = ldl_code(ctx.nip); | |
111bfab3 | 8502 | } |
d12d51d5 | 8503 | LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", |
9a64fbe4 | 8504 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), |
056401ea | 8505 | opc3(ctx.opcode), little_endian ? "little" : "big"); |
046d6672 | 8506 | ctx.nip += 4; |
3fc6c082 | 8507 | table = env->opcodes; |
2e70f6ef | 8508 | num_insns++; |
79aceca5 FB |
8509 | handler = table[opc1(ctx.opcode)]; |
8510 | if (is_indirect_opcode(handler)) { | |
8511 | table = ind_table(handler); | |
8512 | handler = table[opc2(ctx.opcode)]; | |
8513 | if (is_indirect_opcode(handler)) { | |
8514 | table = ind_table(handler); | |
8515 | handler = table[opc3(ctx.opcode)]; | |
8516 | } | |
8517 | } | |
8518 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 8519 | if (unlikely(handler->handler == &gen_invalid)) { |
93fcfe39 AL |
8520 | if (qemu_log_enabled()) { |
8521 | qemu_log("invalid/unsupported opcode: " | |
8522 | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", | |
8523 | opc1(ctx.opcode), opc2(ctx.opcode), | |
8524 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
4b3686fa FB |
8525 | } else { |
8526 | printf("invalid/unsupported opcode: " | |
6b542af7 | 8527 | "%02x - %02x - %02x (%08x) " ADDRX " %d\n", |
4b3686fa | 8528 | opc1(ctx.opcode), opc2(ctx.opcode), |
0411a972 | 8529 | opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir); |
4b3686fa | 8530 | } |
76a66253 JM |
8531 | } else { |
8532 | if (unlikely((ctx.opcode & handler->inval) != 0)) { | |
93fcfe39 AL |
8533 | if (qemu_log_enabled()) { |
8534 | qemu_log("invalid bits: %08x for opcode: " | |
8535 | "%02x - %02x - %02x (%08x) " ADDRX "\n", | |
8536 | ctx.opcode & handler->inval, opc1(ctx.opcode), | |
8537 | opc2(ctx.opcode), opc3(ctx.opcode), | |
8538 | ctx.opcode, ctx.nip - 4); | |
9a64fbe4 FB |
8539 | } else { |
8540 | printf("invalid bits: %08x for opcode: " | |
6b542af7 | 8541 | "%02x - %02x - %02x (%08x) " ADDRX "\n", |
76a66253 JM |
8542 | ctx.opcode & handler->inval, opc1(ctx.opcode), |
8543 | opc2(ctx.opcode), opc3(ctx.opcode), | |
046d6672 | 8544 | ctx.opcode, ctx.nip - 4); |
76a66253 | 8545 | } |
e06fcd75 | 8546 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 8547 | break; |
79aceca5 | 8548 | } |
79aceca5 | 8549 | } |
4b3686fa | 8550 | (*(handler->handler))(&ctx); |
76a66253 JM |
8551 | #if defined(DO_PPC_STATISTICS) |
8552 | handler->count++; | |
8553 | #endif | |
9a64fbe4 | 8554 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
8555 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
8556 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
8557 | ctx.exception != POWERPC_SYSCALL && | |
8558 | ctx.exception != POWERPC_EXCP_TRAP && | |
8559 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
e06fcd75 | 8560 | gen_exception(ctxp, POWERPC_EXCP_TRACE); |
d26bfc9a | 8561 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
2e70f6ef | 8562 | (env->singlestep_enabled) || |
1b530a6d | 8563 | singlestep || |
2e70f6ef | 8564 | num_insns >= max_insns)) { |
d26bfc9a JM |
8565 | /* if we reach a page boundary or are single stepping, stop |
8566 | * generation | |
8567 | */ | |
8dd4983c | 8568 | break; |
76a66253 | 8569 | } |
3fc6c082 | 8570 | } |
2e70f6ef PB |
8571 | if (tb->cflags & CF_LAST_IO) |
8572 | gen_io_end(); | |
e1833e1f | 8573 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 8574 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 8575 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
8cbcb4fa | 8576 | if (unlikely(env->singlestep_enabled)) { |
e06fcd75 | 8577 | gen_debug_exception(ctxp); |
8cbcb4fa | 8578 | } |
76a66253 | 8579 | /* Generate the return instruction */ |
57fec1fe | 8580 | tcg_gen_exit_tb(0); |
9a64fbe4 | 8581 | } |
2e70f6ef | 8582 | gen_icount_end(tb, num_insns); |
79aceca5 | 8583 | *gen_opc_ptr = INDEX_op_end; |
76a66253 | 8584 | if (unlikely(search_pc)) { |
9a64fbe4 FB |
8585 | j = gen_opc_ptr - gen_opc_buf; |
8586 | lj++; | |
8587 | while (lj <= j) | |
8588 | gen_opc_instr_start[lj++] = 0; | |
9a64fbe4 | 8589 | } else { |
046d6672 | 8590 | tb->size = ctx.nip - pc_start; |
2e70f6ef | 8591 | tb->icount = num_insns; |
9a64fbe4 | 8592 | } |
d9bce9d9 | 8593 | #if defined(DEBUG_DISAS) |
93fcfe39 AL |
8594 | qemu_log_mask(CPU_LOG_TB_CPU, "---------------- excp: %04x\n", ctx.exception); |
8595 | log_cpu_state_mask(CPU_LOG_TB_CPU, env, 0); | |
8fec2b8c | 8596 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
76a66253 | 8597 | int flags; |
237c0af0 | 8598 | flags = env->bfd_mach; |
76db3ba4 | 8599 | flags |= ctx.le_mode << 16; |
93fcfe39 AL |
8600 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
8601 | log_target_disas(pc_start, ctx.nip - pc_start, flags); | |
8602 | qemu_log("\n"); | |
9fddaa0c | 8603 | } |
79aceca5 | 8604 | #endif |
79aceca5 FB |
8605 | } |
8606 | ||
2cfc5f17 | 8607 | void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
79aceca5 | 8608 | { |
2cfc5f17 | 8609 | gen_intermediate_code_internal(env, tb, 0); |
79aceca5 FB |
8610 | } |
8611 | ||
2cfc5f17 | 8612 | void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
79aceca5 | 8613 | { |
2cfc5f17 | 8614 | gen_intermediate_code_internal(env, tb, 1); |
79aceca5 | 8615 | } |
d2856f1a AJ |
8616 | |
8617 | void gen_pc_load(CPUState *env, TranslationBlock *tb, | |
8618 | unsigned long searched_pc, int pc_pos, void *puc) | |
8619 | { | |
d2856f1a | 8620 | env->nip = gen_opc_pc[pc_pos]; |
d2856f1a | 8621 | } |