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x86-64 port (Jocelyn Mayer)
[mirror_qemu.git] / target-ppc / translate.c
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79aceca5
FB		 1/*
2 * PPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include "dyngen-exec.h"
21#include "cpu.h"
22#include "exec.h"
23#include "disas.h"
24
25//#define DO_SINGLE_STEP
26//#define DO_STEP_FLUSH
9a64fbe4 27//#define DEBUG_DISAS
79aceca5
FB		 28
29enum {
30#define DEF(s, n, copy_size) INDEX_op_ ## s,
31#include "opc.h"
32#undef DEF
33 NB_OPS,
34};
35
36static uint16_t *gen_opc_ptr;
37static uint32_t *gen_opparam_ptr;
38
39#include "gen-op.h"
28b6751f 40
28b6751f 41#define GEN8(func, NAME) \
9a64fbe4
FB		 42static GenOpFunc *NAME ## _table [8] = { \
43NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
44NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
45}; \
46static inline void func(int n) \
47{ \
48 NAME ## _table[n](); \
49}
50
51#define GEN16(func, NAME) \
52static GenOpFunc *NAME ## _table [16] = { \
53NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
54NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
55NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
56NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
57}; \
58static inline void func(int n) \
59{ \
60 NAME ## _table[n](); \
28b6751f
FB		 61}
62
63#define GEN32(func, NAME) \
9a64fbe4
FB		 64static GenOpFunc *NAME ## _table [32] = { \
65NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
66NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
67NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
68NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
69NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
70NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
71NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
72NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
73}; \
74static inline void func(int n) \
75{ \
76 NAME ## _table[n](); \
77}
78
79/* Condition register moves */
80GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
81GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
82GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
83GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
28b6751f 84
fb0eaffc
FB		 85/* Floating point condition and status register moves */
86GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
87GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
88GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
89static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
90 &gen_op_store_T0_fpscri_fpscr0,
91 &gen_op_store_T0_fpscri_fpscr1,
92 &gen_op_store_T0_fpscri_fpscr2,
93 &gen_op_store_T0_fpscri_fpscr3,
94 &gen_op_store_T0_fpscri_fpscr4,
95 &gen_op_store_T0_fpscri_fpscr5,
96 &gen_op_store_T0_fpscri_fpscr6,
97 &gen_op_store_T0_fpscri_fpscr7,
98};
99static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
100{
101 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
102}
103
9a64fbe4
FB		 104/* Segment register moves */
105GEN16(gen_op_load_sr, gen_op_load_sr);
106GEN16(gen_op_store_sr, gen_op_store_sr);
28b6751f 107
9a64fbe4
FB		 108/* General purpose registers moves */
109GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
110GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
111GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
112
113GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
114GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
115GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
28b6751f 116
fb0eaffc
FB		 117/* floating point registers moves */
118GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
119GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
120GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
121GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
122GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
123GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
79aceca5
FB		 124
125static uint8_t spr_access[1024 / 2];
126
127/* internal defines */
128typedef struct DisasContext {
129 struct TranslationBlock *tb;
130 uint32_t *nip;
131 uint32_t opcode;
9a64fbe4
FB		 132 uint32_t exception;
133 /* Time base offset */
79aceca5 134 uint32_t tb_offset;
9a64fbe4
FB		 135 /* Decrementer offset */
136 uint32_t decr_offset;
137 /* Execution mode */
138#if !defined(CONFIG_USER_ONLY)
79aceca5 139 int supervisor;
9a64fbe4
FB		 140#endif
141 /* Routine used to access memory */
142 int mem_idx;
79aceca5
FB		 143} DisasContext;
144
145typedef struct opc_handler_t {
146 /* invalid bits */
147 uint32_t inval;
9a64fbe4
FB		 148 /* instruction type */
149 uint32_t type;
79aceca5
FB		 150 /* handler */
151 void (*handler)(DisasContext *ctx);
152} opc_handler_t;
153
9a64fbe4 154#define RET_EXCP(excp, error) \
79aceca5 155do { \
9a64fbe4
FB		 156 gen_op_queue_exception_err(excp, error); \
157 ctx->exception = excp; \
79aceca5
FB		 158 return; \
159} while (0)
160
9a64fbe4
FB		 161#define RET_INVAL() \
162RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
163
164#define RET_PRIVOPC() \
165RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
166
167#define RET_PRIVREG() \
168RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
79aceca5
FB		 169
170#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
171static void gen_##name (DisasContext *ctx); \
172GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
173static void gen_##name (DisasContext *ctx)
174
79aceca5
FB		 175typedef struct opcode_t {
176 unsigned char opc1, opc2, opc3;
79aceca5
FB		 177 opc_handler_t handler;
178} opcode_t;
179
180/* XXX: move that elsewhere */
181extern FILE *logfile;
182extern int loglevel;
183
79aceca5
FB		 184/*** Instruction decoding ***/
185#define EXTRACT_HELPER(name, shift, nb) \
186static inline uint32_t name (uint32_t opcode) \
187{ \
188 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
189}
190
191#define EXTRACT_SHELPER(name, shift, nb) \
192static inline int32_t name (uint32_t opcode) \
193{ \
194 return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \
195}
196
197/* Opcode part 1 */
198EXTRACT_HELPER(opc1, 26, 6);
199/* Opcode part 2 */
200EXTRACT_HELPER(opc2, 1, 5);
201/* Opcode part 3 */
202EXTRACT_HELPER(opc3, 6, 5);
203/* Update Cr0 flags */
204EXTRACT_HELPER(Rc, 0, 1);
205/* Destination */
206EXTRACT_HELPER(rD, 21, 5);
207/* Source */
208EXTRACT_HELPER(rS, 21, 5);
209/* First operand */
210EXTRACT_HELPER(rA, 16, 5);
211/* Second operand */
212EXTRACT_HELPER(rB, 11, 5);
213/* Third operand */
214EXTRACT_HELPER(rC, 6, 5);
215/*** Get CRn ***/
216EXTRACT_HELPER(crfD, 23, 3);
217EXTRACT_HELPER(crfS, 18, 3);
218EXTRACT_HELPER(crbD, 21, 5);
219EXTRACT_HELPER(crbA, 16, 5);
220EXTRACT_HELPER(crbB, 11, 5);
221/* SPR / TBL */
222EXTRACT_HELPER(SPR, 11, 10);
223/*** Get constants ***/
224EXTRACT_HELPER(IMM, 12, 8);
225/* 16 bits signed immediate value */
226EXTRACT_SHELPER(SIMM, 0, 16);
227/* 16 bits unsigned immediate value */
228EXTRACT_HELPER(UIMM, 0, 16);
229/* Bit count */
230EXTRACT_HELPER(NB, 11, 5);
231/* Shift count */
232EXTRACT_HELPER(SH, 11, 5);
233/* Mask start */
234EXTRACT_HELPER(MB, 6, 5);
235/* Mask end */
236EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 237/* Trap operand */
238EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 239
240EXTRACT_HELPER(CRM, 12, 8);
241EXTRACT_HELPER(FM, 17, 8);
242EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 243EXTRACT_HELPER(FPIMM, 20, 4);
244
79aceca5
FB		 245/*** Jump target decoding ***/
246/* Displacement */
247EXTRACT_SHELPER(d, 0, 16);
248/* Immediate address */
249static inline uint32_t LI (uint32_t opcode)
250{
251 return (opcode >> 0) & 0x03FFFFFC;
252}
253
254static inline uint32_t BD (uint32_t opcode)
255{
256 return (opcode >> 0) & 0xFFFC;
257}
258
259EXTRACT_HELPER(BO, 21, 5);
260EXTRACT_HELPER(BI, 16, 5);
261/* Absolute/relative address */
262EXTRACT_HELPER(AA, 1, 1);
263/* Link */
264EXTRACT_HELPER(LK, 0, 1);
265
266/* Create a mask between <start> and <end> bits */
267static inline uint32_t MASK (uint32_t start, uint32_t end)
268{
269 uint32_t ret;
270
271 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
272 if (start > end)
273 return ~ret;
274
275 return ret;
276}
277
278#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
279__attribute__ ((section(".opcodes"), unused)) \
280static opcode_t opc_##name = { \
281 .opc1 = op1, \
282 .opc2 = op2, \
283 .opc3 = op3, \
79aceca5
FB		 284 .handler = { \
285 .inval = invl, \
9a64fbe4 286 .type = _typ, \
79aceca5
FB		 287 .handler = &gen_##name, \
288 }, \
289}
290
291#define GEN_OPCODE_MARK(name) \
292__attribute__ ((section(".opcodes"), unused)) \
293static opcode_t opc_##name = { \
294 .opc1 = 0xFF, \
295 .opc2 = 0xFF, \
296 .opc3 = 0xFF, \
79aceca5
FB		 297 .handler = { \
298 .inval = 0x00000000, \
9a64fbe4 299 .type = 0x00, \
79aceca5
FB		 300 .handler = NULL, \
301 }, \
302}
303
304/* Start opcode list */
305GEN_OPCODE_MARK(start);
306
307/* Invalid instruction */
9a64fbe4
FB		 308GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
309{
310 RET_INVAL();
311}
312
313/* Special opcode to stop emulation */
314GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
79aceca5 315{
9a64fbe4
FB		 316 gen_op_queue_exception(EXCP_HLT);
317 ctx->exception = EXCP_HLT;
318}
319
320/* Special opcode to call open-firmware */
321GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
322{
323 gen_op_queue_exception(EXCP_OFCALL);
324 ctx->exception = EXCP_OFCALL;
325}
326
327/* Special opcode to call RTAS */
328GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
329{
330 printf("RTAS entry point !\n");
331 gen_op_queue_exception(EXCP_RTASCALL);
332 ctx->exception = EXCP_RTASCALL;
79aceca5
FB		 333}
334
335static opc_handler_t invalid_handler = {
336 .inval = 0xFFFFFFFF,
9a64fbe4 337 .type = PPC_NONE,
79aceca5
FB		 338 .handler = gen_invalid,
339};
340
341/*** Integer arithmetic ***/
342#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
343GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
344{ \
345 gen_op_load_gpr_T0(rA(ctx->opcode)); \
346 gen_op_load_gpr_T1(rB(ctx->opcode)); \
347 gen_op_##name(); \
348 if (Rc(ctx->opcode) != 0) \
349 gen_op_set_Rc0(); \
350 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 351}
352
353#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
354GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
355{ \
356 gen_op_load_gpr_T0(rA(ctx->opcode)); \
357 gen_op_load_gpr_T1(rB(ctx->opcode)); \
358 gen_op_##name(); \
359 if (Rc(ctx->opcode) != 0) \
360 gen_op_set_Rc0_ov(); \
361 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 362}
363
364#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
365GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
366{ \
367 gen_op_load_gpr_T0(rA(ctx->opcode)); \
368 gen_op_##name(); \
369 if (Rc(ctx->opcode) != 0) \
370 gen_op_set_Rc0(); \
371 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 372}
373#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
374GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
375{ \
376 gen_op_load_gpr_T0(rA(ctx->opcode)); \
377 gen_op_##name(); \
378 if (Rc(ctx->opcode) != 0) \
379 gen_op_set_Rc0_ov(); \
380 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 381}
382
383/* Two operands arithmetic functions */
384#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
385__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
386__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
387
388/* Two operands arithmetic functions with no overflow allowed */
389#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
390__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
391
392/* One operand arithmetic functions */
393#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
394__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
395__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
396
397/* add add. addo addo. */
398GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
399/* addc addc. addco addco. */
400GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
401/* adde adde. addeo addeo. */
402GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
403/* addme addme. addmeo addmeo. */
404GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
405/* addze addze. addzeo addzeo. */
406GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
407/* divw divw. divwo divwo. */
408GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
409/* divwu divwu. divwuo divwuo. */
410GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
411/* mulhw mulhw. */
412GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
413/* mulhwu mulhwu. */
414GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
415/* mullw mullw. mullwo mullwo. */
416GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
417/* neg neg. nego nego. */
418GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
419/* subf subf. subfo subfo. */
420GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
421/* subfc subfc. subfco subfco. */
422GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
423/* subfe subfe. subfeo subfeo. */
424GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
425/* subfme subfme. subfmeo subfmeo. */
426GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
427/* subfze subfze. subfzeo subfzeo. */
428GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
429/* addi */
430GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
431{
432 int32_t simm = SIMM(ctx->opcode);
433
434 if (rA(ctx->opcode) == 0) {
435 gen_op_set_T0(simm);
436 } else {
437 gen_op_load_gpr_T0(rA(ctx->opcode));
438 gen_op_addi(simm);
439 }
440 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 441}
442/* addic */
443GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
444{
445 gen_op_load_gpr_T0(rA(ctx->opcode));
446 gen_op_addic(SIMM(ctx->opcode));
447 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 448}
449/* addic. */
450GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
451{
452 gen_op_load_gpr_T0(rA(ctx->opcode));
453 gen_op_addic(SIMM(ctx->opcode));
454 gen_op_set_Rc0();
455 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 456}
457/* addis */
458GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
459{
460 int32_t simm = SIMM(ctx->opcode);
461
462 if (rA(ctx->opcode) == 0) {
463 gen_op_set_T0(simm << 16);
464 } else {
465 gen_op_load_gpr_T0(rA(ctx->opcode));
466 gen_op_addi(simm << 16);
467 }
468 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 469}
470/* mulli */
471GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
472{
473 gen_op_load_gpr_T0(rA(ctx->opcode));
474 gen_op_mulli(SIMM(ctx->opcode));
475 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 476}
477/* subfic */
478GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
479{
480 gen_op_load_gpr_T0(rA(ctx->opcode));
481 gen_op_subfic(SIMM(ctx->opcode));
482 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 483}
484
485/*** Integer comparison ***/
486#define GEN_CMP(name, opc) \
487GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
488{ \
489 gen_op_load_gpr_T0(rA(ctx->opcode)); \
490 gen_op_load_gpr_T1(rB(ctx->opcode)); \
491 gen_op_##name(); \
492 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5
FB		 493}
494
495/* cmp */
496GEN_CMP(cmp, 0x00);
497/* cmpi */
498GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
499{
500 gen_op_load_gpr_T0(rA(ctx->opcode));
501 gen_op_cmpi(SIMM(ctx->opcode));
502 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 503}
504/* cmpl */
505GEN_CMP(cmpl, 0x01);
506/* cmpli */
507GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
508{
509 gen_op_load_gpr_T0(rA(ctx->opcode));
510 gen_op_cmpli(UIMM(ctx->opcode));
511 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 512}
513
514/*** Integer logical ***/
515#define __GEN_LOGICAL2(name, opc2, opc3) \
516GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
517{ \
518 gen_op_load_gpr_T0(rS(ctx->opcode)); \
519 gen_op_load_gpr_T1(rB(ctx->opcode)); \
520 gen_op_##name(); \
521 if (Rc(ctx->opcode) != 0) \
522 gen_op_set_Rc0(); \
523 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 524}
525#define GEN_LOGICAL2(name, opc) \
526__GEN_LOGICAL2(name, 0x1C, opc)
527
528#define GEN_LOGICAL1(name, opc) \
529GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
530{ \
531 gen_op_load_gpr_T0(rS(ctx->opcode)); \
532 gen_op_##name(); \
533 if (Rc(ctx->opcode) != 0) \
534 gen_op_set_Rc0(); \
535 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 536}
537
538/* and & and. */
539GEN_LOGICAL2(and, 0x00);
540/* andc & andc. */
541GEN_LOGICAL2(andc, 0x01);
542/* andi. */
543GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
544{
545 gen_op_load_gpr_T0(rS(ctx->opcode));
546 gen_op_andi_(UIMM(ctx->opcode));
547 gen_op_set_Rc0();
548 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 549}
550/* andis. */
551GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
552{
553 gen_op_load_gpr_T0(rS(ctx->opcode));
554 gen_op_andi_(UIMM(ctx->opcode) << 16);
555 gen_op_set_Rc0();
556 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 557}
558
559/* cntlzw */
560GEN_LOGICAL1(cntlzw, 0x00);
561/* eqv & eqv. */
562GEN_LOGICAL2(eqv, 0x08);
563/* extsb & extsb. */
564GEN_LOGICAL1(extsb, 0x1D);
565/* extsh & extsh. */
566GEN_LOGICAL1(extsh, 0x1C);
567/* nand & nand. */
568GEN_LOGICAL2(nand, 0x0E);
569/* nor & nor. */
570GEN_LOGICAL2(nor, 0x03);
9a64fbe4 571
79aceca5 572/* or & or. */
9a64fbe4
FB		 573GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
574{
575 gen_op_load_gpr_T0(rS(ctx->opcode));
576 /* Optimisation for mr case */
577 if (rS(ctx->opcode) != rB(ctx->opcode)) {
578 gen_op_load_gpr_T1(rB(ctx->opcode));
579 gen_op_or();
580 }
581 if (Rc(ctx->opcode) != 0)
582 gen_op_set_Rc0();
583 gen_op_store_T0_gpr(rA(ctx->opcode));
584}
585
79aceca5
FB		 586/* orc & orc. */
587GEN_LOGICAL2(orc, 0x0C);
588/* xor & xor. */
9a64fbe4
FB		 589GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
590{
591 gen_op_load_gpr_T0(rS(ctx->opcode));
592 /* Optimisation for "set to zero" case */
593 if (rS(ctx->opcode) != rB(ctx->opcode)) {
594 gen_op_load_gpr_T1(rB(ctx->opcode));
595 gen_op_xor();
596 } else {
597 gen_op_set_T0(0);
598 }
599 if (Rc(ctx->opcode) != 0)
600 gen_op_set_Rc0();
601 gen_op_store_T0_gpr(rA(ctx->opcode));
602}
79aceca5
FB		 603/* ori */
604GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
605{
606 uint32_t uimm = UIMM(ctx->opcode);
607
9a64fbe4
FB		 608 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
609 /* NOP */
610 return;
79aceca5 611 }
79aceca5 612 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 613 if (uimm != 0)
79aceca5
FB		 614 gen_op_ori(uimm);
615 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 616}
617/* oris */
618GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
619{
620 uint32_t uimm = UIMM(ctx->opcode);
621
9a64fbe4
FB		 622 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
623 /* NOP */
624 return;
79aceca5 625 }
79aceca5 626 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 627 if (uimm != 0)
79aceca5
FB		 628 gen_op_ori(uimm << 16);
629 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 630}
631/* xori */
632GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
633{
9a64fbe4
FB		 634 uint32_t uimm = UIMM(ctx->opcode);
635
636 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
637 /* NOP */
638 return;
639 }
79aceca5 640 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 641 if (uimm != 0)
79aceca5
FB		 642 gen_op_xori(UIMM(ctx->opcode));
643 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 644}
645
646/* xoris */
647GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
648{
9a64fbe4
FB		 649 uint32_t uimm = UIMM(ctx->opcode);
650
651 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
652 /* NOP */
653 return;
654 }
79aceca5 655 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 656 if (uimm != 0)
79aceca5
FB		 657 gen_op_xori(UIMM(ctx->opcode) << 16);
658 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 659}
660
661/*** Integer rotate ***/
662/* rlwimi & rlwimi. */
663GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
664{
665 uint32_t mb, me;
666
667 mb = MB(ctx->opcode);
668 me = ME(ctx->opcode);
669 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 670 gen_op_load_gpr_T1(rA(ctx->opcode));
79aceca5
FB		 671 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
672 if (Rc(ctx->opcode) != 0)
673 gen_op_set_Rc0();
674 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 675}
676/* rlwinm & rlwinm. */
677GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
678{
679 uint32_t mb, me, sh;
680
681 sh = SH(ctx->opcode);
682 mb = MB(ctx->opcode);
683 me = ME(ctx->opcode);
684 gen_op_load_gpr_T0(rS(ctx->opcode));
79aceca5
FB		 685 if (mb == 0) {
686 if (me == 31) {
687 gen_op_rotlwi(sh);
688 goto store;
689 } else if (me == (31 - sh)) {
690 gen_op_slwi(sh);
691 goto store;
692 } else if (sh == 0) {
693 gen_op_andi_(MASK(0, me));
694 goto store;
695 }
696 } else if (me == 31) {
697 if (sh == (32 - mb)) {
698 gen_op_srwi(mb);
699 goto store;
700 } else if (sh == 0) {
701 gen_op_andi_(MASK(mb, 31));
702 goto store;
703 }
704 }
705 gen_op_rlwinm(sh, MASK(mb, me));
706store:
707 if (Rc(ctx->opcode) != 0)
708 gen_op_set_Rc0();
709 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 710}
711/* rlwnm & rlwnm. */
712GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
713{
714 uint32_t mb, me;
715
716 mb = MB(ctx->opcode);
717 me = ME(ctx->opcode);
718 gen_op_load_gpr_T0(rS(ctx->opcode));
719 gen_op_load_gpr_T1(rB(ctx->opcode));
720 if (mb == 0 && me == 31) {
721 gen_op_rotl();
722 } else
723 {
724 gen_op_rlwnm(MASK(mb, me));
725 }
726 if (Rc(ctx->opcode) != 0)
727 gen_op_set_Rc0();
728 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 729}
730
731/*** Integer shift ***/
732/* slw & slw. */
733__GEN_LOGICAL2(slw, 0x18, 0x00);
734/* sraw & sraw. */
735__GEN_LOGICAL2(sraw, 0x18, 0x18);
736/* srawi & srawi. */
737GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
738{
739 gen_op_load_gpr_T0(rS(ctx->opcode));
740 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
741 if (Rc(ctx->opcode) != 0)
742 gen_op_set_Rc0();
743 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 744}
745/* srw & srw. */
746__GEN_LOGICAL2(srw, 0x18, 0x10);
747
748/*** Floating-Point arithmetic ***/
9a64fbe4
FB		 749#define _GEN_FLOAT_ACB(name, op1, op2) \
750GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
751{ \
752 gen_op_reset_scrfx(); \
753 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
754 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
755 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
756 gen_op_f##name(); \
757 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
758 if (Rc(ctx->opcode)) \
759 gen_op_set_Rc1(); \
760}
761
762#define GEN_FLOAT_ACB(name, op2) \
763_GEN_FLOAT_ACB(name, 0x3F, op2); \
764_GEN_FLOAT_ACB(name##s, 0x3B, op2);
765
766#define _GEN_FLOAT_AB(name, op1, op2, inval) \
767GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
768{ \
769 gen_op_reset_scrfx(); \
770 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
771 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
772 gen_op_f##name(); \
773 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
774 if (Rc(ctx->opcode)) \
775 gen_op_set_Rc1(); \
776}
777#define GEN_FLOAT_AB(name, op2, inval) \
778_GEN_FLOAT_AB(name, 0x3F, op2, inval); \
779_GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
780
781#define _GEN_FLOAT_AC(name, op1, op2, inval) \
782GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
783{ \
784 gen_op_reset_scrfx(); \
785 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
786 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
787 gen_op_f##name(); \
788 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
789 if (Rc(ctx->opcode)) \
790 gen_op_set_Rc1(); \
791}
792#define GEN_FLOAT_AC(name, op2, inval) \
793_GEN_FLOAT_AC(name, 0x3F, op2, inval); \
794_GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
795
796#define GEN_FLOAT_B(name, op2, op3) \
797GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
798{ \
799 gen_op_reset_scrfx(); \
800 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
801 gen_op_f##name(); \
802 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
803 if (Rc(ctx->opcode)) \
804 gen_op_set_Rc1(); \
79aceca5
FB		 805}
806
9a64fbe4
FB		 807#define GEN_FLOAT_BS(name, op2) \
808GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
809{ \
810 gen_op_reset_scrfx(); \
811 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
812 gen_op_f##name(); \
813 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
814 if (Rc(ctx->opcode)) \
815 gen_op_set_Rc1(); \
79aceca5
FB		 816}
817
9a64fbe4
FB		 818/* fadd - fadds */
819GEN_FLOAT_AB(add, 0x15, 0x000007C0);
79aceca5 820/* fdiv */
9a64fbe4 821GEN_FLOAT_AB(div, 0x12, 0x000007C0);
79aceca5 822/* fmul */
9a64fbe4 823GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
79aceca5
FB		 824
825/* fres */
9a64fbe4 826GEN_FLOAT_BS(res, 0x18);
79aceca5
FB		 827
828/* frsqrte */
9a64fbe4 829GEN_FLOAT_BS(rsqrte, 0x1A);
79aceca5
FB		 830
831/* fsel */
9a64fbe4 832_GEN_FLOAT_ACB(sel, 0x3F, 0x17);
79aceca5 833/* fsub */
9a64fbe4 834GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
79aceca5
FB		 835/* Optional: */
836/* fsqrt */
9a64fbe4 837GEN_FLOAT_BS(sqrt, 0x16);
79aceca5 838
9a64fbe4 839GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
79aceca5 840{
9a64fbe4
FB		 841 gen_op_reset_scrfx();
842 gen_op_load_fpr_FT0(rB(ctx->opcode));
843 gen_op_fsqrts();
844 gen_op_store_FT0_fpr(rD(ctx->opcode));
845 if (Rc(ctx->opcode))
846 gen_op_set_Rc1();
79aceca5
FB		 847}
848
849/*** Floating-Point multiply-and-add ***/
850/* fmadd */
9a64fbe4 851GEN_FLOAT_ACB(madd, 0x1D);
79aceca5 852/* fmsub */
9a64fbe4 853GEN_FLOAT_ACB(msub, 0x1C);
79aceca5 854/* fnmadd */
9a64fbe4 855GEN_FLOAT_ACB(nmadd, 0x1F);
79aceca5 856/* fnmsub */
9a64fbe4 857GEN_FLOAT_ACB(nmsub, 0x1E);
79aceca5
FB		 858
859/*** Floating-Point round & convert ***/
860/* fctiw */
9a64fbe4 861GEN_FLOAT_B(ctiw, 0x0E, 0x00);
79aceca5 862/* fctiwz */
9a64fbe4 863GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
79aceca5 864/* frsp */
9a64fbe4 865GEN_FLOAT_B(rsp, 0x0C, 0x00);
79aceca5
FB		 866
867/*** Floating-Point compare ***/
868/* fcmpo */
869GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
870{
9a64fbe4
FB		 871 gen_op_reset_scrfx();
872 gen_op_load_fpr_FT0(rA(ctx->opcode));
873 gen_op_load_fpr_FT1(rB(ctx->opcode));
874 gen_op_fcmpo();
875 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 876}
877
878/* fcmpu */
879GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
880{
9a64fbe4
FB		 881 gen_op_reset_scrfx();
882 gen_op_load_fpr_FT0(rA(ctx->opcode));
883 gen_op_load_fpr_FT1(rB(ctx->opcode));
884 gen_op_fcmpu();
885 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 886}
887
9a64fbe4
FB		 888/*** Floating-point move ***/
889/* fabs */
890GEN_FLOAT_B(abs, 0x08, 0x08);
891
892/* fmr - fmr. */
893GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
894{
895 gen_op_reset_scrfx();
896 gen_op_load_fpr_FT0(rB(ctx->opcode));
897 gen_op_store_FT0_fpr(rD(ctx->opcode));
898 if (Rc(ctx->opcode))
899 gen_op_set_Rc1();
900}
901
902/* fnabs */
903GEN_FLOAT_B(nabs, 0x08, 0x04);
904/* fneg */
905GEN_FLOAT_B(neg, 0x08, 0x01);
906
79aceca5
FB		 907/*** Floating-Point status & ctrl register ***/
908/* mcrfs */
909GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
910{
fb0eaffc
FB		 911 gen_op_load_fpscr_T0(crfS(ctx->opcode));
912 gen_op_store_T0_crf(crfD(ctx->opcode));
913 gen_op_clear_fpscr(crfS(ctx->opcode));
79aceca5
FB		 914}
915
916/* mffs */
917GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
918{
28b6751f 919 gen_op_load_fpscr();
fb0eaffc
FB		 920 gen_op_store_FT0_fpr(rD(ctx->opcode));
921 if (Rc(ctx->opcode))
922 gen_op_set_Rc1();
79aceca5
FB		 923}
924
925/* mtfsb0 */
926GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
927{
fb0eaffc
FB		 928 uint8_t crb;
929
930 crb = crbD(ctx->opcode) >> 2;
931 gen_op_load_fpscr_T0(crb);
932 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
933 gen_op_store_T0_fpscr(crb);
934 if (Rc(ctx->opcode))
935 gen_op_set_Rc1();
79aceca5
FB		 936}
937
938/* mtfsb1 */
939GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
940{
fb0eaffc
FB		 941 uint8_t crb;
942
943 crb = crbD(ctx->opcode) >> 2;
944 gen_op_load_fpscr_T0(crb);
945 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
946 gen_op_store_T0_fpscr(crb);
947 if (Rc(ctx->opcode))
948 gen_op_set_Rc1();
79aceca5
FB		 949}
950
951/* mtfsf */
952GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
953{
fb0eaffc 954 gen_op_load_fpr_FT0(rB(ctx->opcode));
28b6751f 955 gen_op_store_fpscr(FM(ctx->opcode));
fb0eaffc
FB		 956 if (Rc(ctx->opcode))
957 gen_op_set_Rc1();
79aceca5
FB		 958}
959
960/* mtfsfi */
961GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
962{
fb0eaffc
FB		 963 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
964 if (Rc(ctx->opcode))
965 gen_op_set_Rc1();
79aceca5
FB		 966}
967
968/*** Integer load ***/
9a64fbe4
FB		 969#if defined(CONFIG_USER_ONLY)
970#define op_ldst(name) gen_op_##name##_raw()
971#define OP_LD_TABLE(width)
972#define OP_ST_TABLE(width)
973#else
974#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
975#define OP_LD_TABLE(width) \
976static GenOpFunc *gen_op_l##width[] = { \
977 &gen_op_l##width##_user, \
978 &gen_op_l##width##_kernel, \
979}
980#define OP_ST_TABLE(width) \
981static GenOpFunc *gen_op_st##width[] = { \
982 &gen_op_st##width##_user, \
983 &gen_op_st##width##_kernel, \
984}
985#endif
986
987#define GEN_LD(width, opc) \
79aceca5
FB		 988GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
989{ \
990 uint32_t simm = SIMM(ctx->opcode); \
991 if (rA(ctx->opcode) == 0) { \
9a64fbe4 992 gen_op_set_T0(simm); \
79aceca5
FB		 993 } else { \
994 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 995 if (simm != 0) \
996 gen_op_addi(simm); \
79aceca5 997 } \
9a64fbe4 998 op_ldst(l##width); \
79aceca5 999 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1000}
1001
9a64fbe4 1002#define GEN_LDU(width, opc) \
79aceca5
FB		 1003GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1004{ \
9a64fbe4 1005 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1006 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1007 rA(ctx->opcode) == rD(ctx->opcode)) { \
1008 RET_INVAL(); \
1009 } \
79aceca5 1010 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1011 if (simm != 0) \
1012 gen_op_addi(simm); \
1013 op_ldst(l##width); \
79aceca5
FB		 1014 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1015 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1016}
1017
9a64fbe4 1018#define GEN_LDUX(width, opc) \
79aceca5
FB		 1019GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1020{ \
1021 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1022 rA(ctx->opcode) == rD(ctx->opcode)) { \
1023 RET_INVAL(); \
1024 } \
79aceca5
FB		 1025 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1026 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1027 gen_op_add(); \
1028 op_ldst(l##width); \
79aceca5
FB		 1029 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1030 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1031}
1032
9a64fbe4 1033#define GEN_LDX(width, opc2, opc3) \
79aceca5
FB		 1034GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1035{ \
1036 if (rA(ctx->opcode) == 0) { \
1037 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1038 } else { \
1039 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1040 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1041 gen_op_add(); \
79aceca5 1042 } \
9a64fbe4 1043 op_ldst(l##width); \
79aceca5 1044 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1045}
1046
9a64fbe4
FB		 1047#define GEN_LDS(width, op) \
1048OP_LD_TABLE(width); \
1049GEN_LD(width, op | 0x20); \
1050GEN_LDU(width, op | 0x21); \
1051GEN_LDUX(width, op | 0x01); \
1052GEN_LDX(width, 0x17, op | 0x00)
79aceca5
FB		 1053
1054/* lbz lbzu lbzux lbzx */
9a64fbe4 1055GEN_LDS(bz, 0x02);
79aceca5 1056/* lha lhau lhaux lhax */
9a64fbe4 1057GEN_LDS(ha, 0x0A);
79aceca5 1058/* lhz lhzu lhzux lhzx */
9a64fbe4 1059GEN_LDS(hz, 0x08);
79aceca5 1060/* lwz lwzu lwzux lwzx */
9a64fbe4 1061GEN_LDS(wz, 0x00);
79aceca5
FB		 1062
1063/*** Integer store ***/
9a64fbe4 1064#define GEN_ST(width, opc) \
79aceca5
FB		 1065GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1066{ \
1067 uint32_t simm = SIMM(ctx->opcode); \
1068 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1069 gen_op_set_T0(simm); \
79aceca5
FB		 1070 } else { \
1071 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1072 if (simm != 0) \
1073 gen_op_addi(simm); \
79aceca5 1074 } \
9a64fbe4
FB		 1075 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1076 op_ldst(st##width); \
79aceca5
FB		 1077}
1078
9a64fbe4 1079#define GEN_STU(width, opc) \
79aceca5
FB		 1080GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1081{ \
9a64fbe4
FB		 1082 uint32_t simm = SIMM(ctx->opcode); \
1083 if (rA(ctx->opcode) == 0) { \
1084 RET_INVAL(); \
1085 } \
79aceca5 1086 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1087 if (simm != 0) \
1088 gen_op_addi(simm); \
79aceca5 1089 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 1090 op_ldst(st##width); \
79aceca5 1091 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1092}
1093
9a64fbe4 1094#define GEN_STUX(width, opc) \
79aceca5
FB		 1095GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1096{ \
9a64fbe4
FB		 1097 if (rA(ctx->opcode) == 0) { \
1098 RET_INVAL(); \
1099 } \
79aceca5
FB		 1100 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1101 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1102 gen_op_add(); \
1103 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1104 op_ldst(st##width); \
79aceca5 1105 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1106}
1107
9a64fbe4 1108#define GEN_STX(width, opc2, opc3) \
79aceca5
FB		 1109GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1110{ \
1111 if (rA(ctx->opcode) == 0) { \
1112 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1113 } else { \
1114 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1115 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1116 gen_op_add(); \
79aceca5 1117 } \
9a64fbe4
FB		 1118 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1119 op_ldst(st##width); \
79aceca5
FB		 1120}
1121
9a64fbe4
FB		 1122#define GEN_STS(width, op) \
1123OP_ST_TABLE(width); \
1124GEN_ST(width, op | 0x20); \
1125GEN_STU(width, op | 0x21); \
1126GEN_STUX(width, op | 0x01); \
1127GEN_STX(width, 0x17, op | 0x00)
79aceca5
FB		 1128
1129/* stb stbu stbux stbx */
9a64fbe4 1130GEN_STS(b, 0x06);
79aceca5 1131/* sth sthu sthux sthx */
9a64fbe4 1132GEN_STS(h, 0x0C);
79aceca5 1133/* stw stwu stwux stwx */
9a64fbe4 1134GEN_STS(w, 0x04);
79aceca5
FB		 1135
1136/*** Integer load and store with byte reverse ***/
1137/* lhbrx */
9a64fbe4
FB		 1138OP_LD_TABLE(hbr);
1139GEN_LDX(hbr, 0x16, 0x18);
79aceca5 1140/* lwbrx */
9a64fbe4
FB		 1141OP_LD_TABLE(wbr);
1142GEN_LDX(wbr, 0x16, 0x10);
79aceca5 1143/* sthbrx */
9a64fbe4
FB		 1144OP_ST_TABLE(hbr);
1145GEN_STX(hbr, 0x16, 0x1C);
79aceca5 1146/* stwbrx */
9a64fbe4
FB		 1147OP_ST_TABLE(wbr);
1148GEN_STX(wbr, 0x16, 0x14);
79aceca5
FB		 1149
1150/*** Integer load and store multiple ***/
9a64fbe4
FB		 1151#if defined(CONFIG_USER_ONLY)
1152#define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1153#else
1154#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1155static GenOpFunc1 *gen_op_lmw[] = {
1156 &gen_op_lmw_user,
1157 &gen_op_lmw_kernel,
1158};
1159static GenOpFunc1 *gen_op_stmw[] = {
1160 &gen_op_stmw_user,
1161 &gen_op_stmw_kernel,
1162};
1163#endif
1164
79aceca5
FB		 1165/* lmw */
1166GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1167{
9a64fbe4
FB		 1168 int simm = SIMM(ctx->opcode);
1169
79aceca5 1170 if (rA(ctx->opcode) == 0) {
9a64fbe4 1171 gen_op_set_T0(simm);
79aceca5
FB		 1172 } else {
1173 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1174 if (simm != 0)
1175 gen_op_addi(simm);
79aceca5 1176 }
9a64fbe4 1177 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 1178}
1179
1180/* stmw */
1181GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1182{
9a64fbe4
FB		 1183 int simm = SIMM(ctx->opcode);
1184
79aceca5 1185 if (rA(ctx->opcode) == 0) {
9a64fbe4 1186 gen_op_set_T0(simm);
79aceca5
FB		 1187 } else {
1188 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1189 if (simm != 0)
1190 gen_op_addi(simm);
79aceca5 1191 }
9a64fbe4 1192 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 1193}
1194
1195/*** Integer load and store strings ***/
9a64fbe4
FB		 1196#if defined(CONFIG_USER_ONLY)
1197#define op_ldsts(name, start) gen_op_##name##_raw(start)
1198#define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1199#else
1200#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1201#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1202static GenOpFunc1 *gen_op_lswi[] = {
1203 &gen_op_lswi_user,
1204 &gen_op_lswi_kernel,
1205};
1206static GenOpFunc3 *gen_op_lswx[] = {
1207 &gen_op_lswx_user,
1208 &gen_op_lswx_kernel,
1209};
1210static GenOpFunc1 *gen_op_stsw[] = {
1211 &gen_op_stsw_user,
1212 &gen_op_stsw_kernel,
1213};
1214#endif
1215
79aceca5 1216/* lswi */
9a64fbe4
FB		 1217/* PPC32 specification says we must generate an exception if
1218 * rA is in the range of registers to be loaded.
1219 * In an other hand, IBM says this is valid, but rA won't be loaded.
1220 * For now, I'll follow the spec...
1221 */
79aceca5
FB		 1222GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1223{
1224 int nb = NB(ctx->opcode);
1225 int start = rD(ctx->opcode);
9a64fbe4 1226 int ra = rA(ctx->opcode);
79aceca5
FB		 1227 int nr;
1228
1229 if (nb == 0)
1230 nb = 32;
1231 nr = nb / 4;
297d8e62
FB		 1232 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1233 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
9a64fbe4 1234 RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
297d8e62 1235 }
9a64fbe4 1236 if (ra == 0) {
79aceca5
FB		 1237 gen_op_set_T0(0);
1238 } else {
9a64fbe4 1239 gen_op_load_gpr_T0(ra);
79aceca5 1240 }
9a64fbe4
FB		 1241 gen_op_set_T1(nb);
1242 op_ldsts(lswi, start);
79aceca5
FB		 1243}
1244
1245/* lswx */
1246GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1247{
9a64fbe4
FB		 1248 int ra = rA(ctx->opcode);
1249 int rb = rB(ctx->opcode);
1250
1251 if (ra == 0) {
1252 gen_op_load_gpr_T0(rb);
1253 ra = rb;
79aceca5 1254 } else {
9a64fbe4
FB		 1255 gen_op_load_gpr_T0(ra);
1256 gen_op_load_gpr_T1(rb);
1257 gen_op_add();
79aceca5 1258 }
9a64fbe4
FB		 1259 gen_op_load_xer_bc();
1260 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 1261}
1262
1263/* stswi */
1264GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1265{
79aceca5
FB		 1266 if (rA(ctx->opcode) == 0) {
1267 gen_op_set_T0(0);
1268 } else {
1269 gen_op_load_gpr_T0(rA(ctx->opcode));
1270 }
9a64fbe4
FB		 1271 gen_op_set_T1(NB(ctx->opcode));
1272 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1273}
1274
1275/* stswx */
1276GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1277{
9a64fbe4
FB		 1278 int ra = rA(ctx->opcode);
1279
1280 if (ra == 0) {
1281 gen_op_load_gpr_T0(rB(ctx->opcode));
1282 ra = rB(ctx->opcode);
79aceca5 1283 } else {
9a64fbe4
FB		 1284 gen_op_load_gpr_T0(ra);
1285 gen_op_load_gpr_T1(rB(ctx->opcode));
1286 gen_op_add();
79aceca5 1287 }
9a64fbe4
FB		 1288 gen_op_load_xer_bc();
1289 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1290}
1291
1292/*** Memory synchronisation ***/
1293/* eieio */
1294GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1295{
79aceca5
FB		 1296}
1297
1298/* isync */
1299GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1300{
79aceca5
FB		 1301}
1302
1303/* lwarx */
9a64fbe4 1304#if defined(CONFIG_USER_ONLY)
985a19d6 1305#define op_lwarx() gen_op_lwarx_raw()
9a64fbe4
FB		 1306#define op_stwcx() gen_op_stwcx_raw()
1307#else
985a19d6
FB		 1308#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1309static GenOpFunc *gen_op_lwarx[] = {
1310 &gen_op_lwarx_user,
1311 &gen_op_lwarx_kernel,
1312};
9a64fbe4
FB		 1313#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1314static GenOpFunc *gen_op_stwcx[] = {
1315 &gen_op_stwcx_user,
1316 &gen_op_stwcx_kernel,
1317};
1318#endif
1319
1320GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
79aceca5 1321{
79aceca5
FB		 1322 if (rA(ctx->opcode) == 0) {
1323 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1324 } else {
1325 gen_op_load_gpr_T0(rA(ctx->opcode));
1326 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1327 gen_op_add();
79aceca5 1328 }
985a19d6 1329 op_lwarx();
79aceca5 1330 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 1331}
1332
1333/* stwcx. */
9a64fbe4 1334GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 1335{
79aceca5
FB		 1336 if (rA(ctx->opcode) == 0) {
1337 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1338 } else {
1339 gen_op_load_gpr_T0(rA(ctx->opcode));
1340 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1341 gen_op_add();
79aceca5 1342 }
9a64fbe4
FB		 1343 gen_op_load_gpr_T1(rS(ctx->opcode));
1344 op_stwcx();
79aceca5
FB		 1345}
1346
1347/* sync */
1348GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1349{
79aceca5
FB		 1350}
1351
1352/*** Floating-point load ***/
9a64fbe4
FB		 1353#define GEN_LDF(width, opc) \
1354GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1355{ \
1356 uint32_t simm = SIMM(ctx->opcode); \
1357 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1358 gen_op_set_T0(simm); \
79aceca5
FB		 1359 } else { \
1360 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1361 if (simm != 0) \
1362 gen_op_addi(simm); \
79aceca5 1363 } \
9a64fbe4
FB		 1364 op_ldst(l##width); \
1365 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1366}
1367
9a64fbe4
FB		 1368#define GEN_LDUF(width, opc) \
1369GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1370{ \
9a64fbe4 1371 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1372 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1373 rA(ctx->opcode) == rD(ctx->opcode)) { \
1374 RET_INVAL(); \
1375 } \
79aceca5 1376 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1377 if (simm != 0) \
1378 gen_op_addi(simm); \
1379 op_ldst(l##width); \
1380 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1381 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1382}
1383
9a64fbe4
FB		 1384#define GEN_LDUXF(width, opc) \
1385GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1386{ \
1387 if (rA(ctx->opcode) == 0 || \
9a64fbe4
FB		 1388 rA(ctx->opcode) == rD(ctx->opcode)) { \
1389 RET_INVAL(); \
1390 } \
79aceca5
FB		 1391 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1392 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1393 gen_op_add(); \
1394 op_ldst(l##width); \
1395 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1396 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1397}
1398
9a64fbe4
FB		 1399#define GEN_LDXF(width, opc2, opc3) \
1400GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1401{ \
1402 if (rA(ctx->opcode) == 0) { \
1403 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1404 } else { \
1405 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1406 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1407 gen_op_add(); \
79aceca5 1408 } \
9a64fbe4
FB		 1409 op_ldst(l##width); \
1410 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1411}
1412
9a64fbe4
FB		 1413#define GEN_LDFS(width, op) \
1414OP_LD_TABLE(width); \
1415GEN_LDF(width, op | 0x20); \
1416GEN_LDUF(width, op | 0x21); \
1417GEN_LDUXF(width, op | 0x01); \
1418GEN_LDXF(width, 0x17, op | 0x00)
79aceca5
FB		 1419
1420/* lfd lfdu lfdux lfdx */
9a64fbe4 1421GEN_LDFS(fd, 0x12);
79aceca5 1422/* lfs lfsu lfsux lfsx */
9a64fbe4 1423GEN_LDFS(fs, 0x10);
79aceca5
FB		 1424
1425/*** Floating-point store ***/
1426#define GEN_STF(width, opc) \
9a64fbe4 1427GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1428{ \
1429 uint32_t simm = SIMM(ctx->opcode); \
1430 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1431 gen_op_set_T0(simm); \
79aceca5
FB		 1432 } else { \
1433 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1434 if (simm != 0) \
1435 gen_op_addi(simm); \
79aceca5 1436 } \
9a64fbe4
FB		 1437 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1438 op_ldst(st##width); \
79aceca5
FB		 1439}
1440
9a64fbe4
FB		 1441#define GEN_STUF(width, opc) \
1442GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1443{ \
9a64fbe4
FB		 1444 uint32_t simm = SIMM(ctx->opcode); \
1445 if (rA(ctx->opcode) == 0) { \
1446 RET_INVAL(); \
1447 } \
79aceca5 1448 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1449 if (simm != 0) \
1450 gen_op_addi(simm); \
1451 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1452 op_ldst(st##width); \
79aceca5 1453 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1454}
1455
9a64fbe4
FB		 1456#define GEN_STUXF(width, opc) \
1457GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5 1458{ \
9a64fbe4
FB		 1459 if (rA(ctx->opcode) == 0) { \
1460 RET_INVAL(); \
1461 } \
79aceca5
FB		 1462 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1463 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1464 gen_op_add(); \
1465 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1466 op_ldst(st##width); \
79aceca5 1467 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1468}
1469
9a64fbe4
FB		 1470#define GEN_STXF(width, opc2, opc3) \
1471GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1472{ \
1473 if (rA(ctx->opcode) == 0) { \
1474 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1475 } else { \
1476 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1477 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1478 gen_op_add(); \
79aceca5 1479 } \
9a64fbe4
FB		 1480 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1481 op_ldst(st##width); \
79aceca5
FB		 1482}
1483
9a64fbe4
FB		 1484#define GEN_STFS(width, op) \
1485OP_ST_TABLE(width); \
1486GEN_STF(width, op | 0x20); \
1487GEN_STUF(width, op | 0x21); \
1488GEN_STUXF(width, op | 0x01); \
1489GEN_STXF(width, 0x17, op | 0x00)
79aceca5
FB		 1490
1491/* stfd stfdu stfdux stfdx */
9a64fbe4 1492GEN_STFS(fd, 0x16);
79aceca5 1493/* stfs stfsu stfsux stfsx */
9a64fbe4 1494GEN_STFS(fs, 0x14);
79aceca5
FB		 1495
1496/* Optional: */
1497/* stfiwx */
1498GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1499{
9a64fbe4 1500 RET_INVAL();
79aceca5
FB		 1501}
1502
1503/*** Branch ***/
79aceca5
FB		 1504
1505/* b ba bl bla */
1506GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1507{
1508 uint32_t li = s_ext24(LI(ctx->opcode)), target;
1509
9a64fbe4
FB		 1510 gen_op_update_tb(ctx->tb_offset);
1511 gen_op_update_decr(ctx->decr_offset);
1512 gen_op_process_exceptions((uint32_t)ctx->nip - 4);
79aceca5
FB		 1513 if (AA(ctx->opcode) == 0)
1514 target = (uint32_t)ctx->nip + li - 4;
1515 else
9a64fbe4 1516 target = li;
9a64fbe4 1517 if (LK(ctx->opcode)) {
e98a6e40 1518 gen_op_setlr((uint32_t)ctx->nip);
9a64fbe4 1519 }
e98a6e40 1520 gen_op_b((long)ctx->tb, target);
9a64fbe4 1521 ctx->exception = EXCP_BRANCH;
79aceca5
FB		 1522}
1523
e98a6e40
FB		 1524#define BCOND_IM 0
1525#define BCOND_LR 1
1526#define BCOND_CTR 2
1527
1528static inline void gen_bcond(DisasContext *ctx, int type)
1529{
1530 uint32_t target = 0;
1531 uint32_t bo = BO(ctx->opcode);
1532 uint32_t bi = BI(ctx->opcode);
1533 uint32_t mask;
1534 uint32_t li;
1535
1536 gen_op_update_tb(ctx->tb_offset);
1537 gen_op_update_decr(ctx->decr_offset);
1538 gen_op_process_exceptions((uint32_t)ctx->nip - 4);
1539
1540 if ((bo & 0x4) == 0)
1541 gen_op_dec_ctr();
1542 switch(type) {
1543 case BCOND_IM:
1544 li = s_ext16(BD(ctx->opcode));
1545 if (AA(ctx->opcode) == 0) {
1546 target = (uint32_t)ctx->nip + li - 4;
1547 } else {
1548 target = li;
1549 }
1550 break;
1551 case BCOND_CTR:
1552 gen_op_movl_T1_ctr();
1553 break;
1554 default:
1555 case BCOND_LR:
1556 gen_op_movl_T1_lr();
1557 break;
1558 }
1559 if (LK(ctx->opcode)) {
1560 gen_op_setlr((uint32_t)ctx->nip);
1561 }
1562 if (bo & 0x10) {
1563 /* No CR condition */
1564 switch (bo & 0x6) {
1565 case 0:
1566 gen_op_test_ctr();
1567 break;
1568 case 2:
1569 gen_op_test_ctrz();
1570 break;
1571 default:
1572 case 4:
1573 case 6:
1574 if (type == BCOND_IM) {
1575 gen_op_b((long)ctx->tb, target);
1576 } else {
1577 gen_op_b_T1();
e98a6e40
FB		 1578 }
1579 goto no_test;
1580 }
1581 } else {
1582 mask = 1 << (3 - (bi & 0x03));
1583 gen_op_load_crf_T0(bi >> 2);
1584 if (bo & 0x8) {
1585 switch (bo & 0x6) {
1586 case 0:
1587 gen_op_test_ctr_true(mask);
1588 break;
1589 case 2:
1590 gen_op_test_ctrz_true(mask);
1591 break;
1592 default:
1593 case 4:
1594 case 6:
1595 gen_op_test_true(mask);
1596 break;
1597 }
1598 } else {
1599 switch (bo & 0x6) {
1600 case 0:
1601 gen_op_test_ctr_false(mask);
1602 break;
1603 case 2:
1604 gen_op_test_ctrz_false(mask);
1605 break;
1606 default:
1607 case 4:
1608 case 6:
1609 gen_op_test_false(mask);
1610 break;
1611 }
1612 }
1613 }
1614 if (type == BCOND_IM) {
1615 gen_op_btest((long)ctx->tb, target, (uint32_t)ctx->nip);
1616 } else {
1617 gen_op_btest_T1((uint32_t)ctx->nip);
1618 }
1619 no_test:
1620 ctx->exception = EXCP_BRANCH;
1621}
1622
1623GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1624{
1625 gen_bcond(ctx, BCOND_IM);
1626}
1627
1628GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1629{
1630 gen_bcond(ctx, BCOND_CTR);
1631}
1632
1633GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1634{
1635 gen_bcond(ctx, BCOND_LR);
1636}
79aceca5
FB		 1637
1638/*** Condition register logical ***/
1639#define GEN_CRLOGIC(op, opc) \
1640GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1641{ \
1642 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1643 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1644 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1645 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1646 gen_op_##op(); \
1647 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1648 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1649 3 - (crbD(ctx->opcode) & 0x03)); \
1650 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 1651}
1652
1653/* crand */
1654GEN_CRLOGIC(and, 0x08)
1655/* crandc */
1656GEN_CRLOGIC(andc, 0x04)
1657/* creqv */
1658GEN_CRLOGIC(eqv, 0x09)
1659/* crnand */
1660GEN_CRLOGIC(nand, 0x07)
1661/* crnor */
1662GEN_CRLOGIC(nor, 0x01)
1663/* cror */
1664GEN_CRLOGIC(or, 0x0E)
1665/* crorc */
1666GEN_CRLOGIC(orc, 0x0D)
1667/* crxor */
1668GEN_CRLOGIC(xor, 0x06)
1669/* mcrf */
1670GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1671{
1672 gen_op_load_crf_T0(crfS(ctx->opcode));
1673 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1674}
1675
1676/*** System linkage ***/
1677/* rfi (supervisor only) */
1678GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1679{
9a64fbe4
FB		 1680#if defined(CONFIG_USER_ONLY)
1681 RET_PRIVOPC();
1682#else
1683 /* Restore CPU state */
1684 if (!ctx->supervisor) {
1685 RET_PRIVOPC();
1686 }
1687 gen_op_rfi();
1688 ctx->exception = EXCP_RFI;
1689#endif
79aceca5
FB		 1690}
1691
1692/* sc */
1693GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1694{
9a64fbe4
FB		 1695#if defined(CONFIG_USER_ONLY)
1696 gen_op_queue_exception(EXCP_SYSCALL_USER);
1697#else
1698 gen_op_queue_exception(EXCP_SYSCALL);
1699#endif
1700 ctx->exception = EXCP_SYSCALL;
79aceca5
FB		 1701}
1702
1703/*** Trap ***/
1704/* tw */
1705GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1706{
9a64fbe4
FB		 1707 gen_op_load_gpr_T0(rA(ctx->opcode));
1708 gen_op_load_gpr_T1(rB(ctx->opcode));
1709 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 1710}
1711
1712/* twi */
1713GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1714{
9a64fbe4
FB		 1715 gen_op_load_gpr_T0(rA(ctx->opcode));
1716#if 0
1717 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1718 SIMM(ctx->opcode), TO(ctx->opcode));
1719#endif
1720 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
79aceca5
FB		 1721}
1722
1723/*** Processor control ***/
1724static inline int check_spr_access (int spr, int rw, int supervisor)
1725{
1726 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1727
9a64fbe4
FB		 1728#if 0
1729 if (spr != LR && spr != CTR) {
1730 if (loglevel > 0) {
1731 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1732 SPR_ENCODE(spr), supervisor, rw, rights,
1733 (rights >> ((2 * supervisor) + rw)) & 1);
1734 } else {
1735 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1736 SPR_ENCODE(spr), supervisor, rw, rights,
1737 (rights >> ((2 * supervisor) + rw)) & 1);
1738 }
1739 }
1740#endif
1741 if (rights == 0)
1742 return -1;
79aceca5
FB		 1743 rights = rights >> (2 * supervisor);
1744 rights = rights >> rw;
1745
1746 return rights & 1;
1747}
1748
1749/* mcrxr */
1750GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1751{
1752 gen_op_load_xer_cr();
1753 gen_op_store_T0_crf(crfD(ctx->opcode));
1754 gen_op_clear_xer_cr();
79aceca5
FB		 1755}
1756
1757/* mfcr */
1758GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1759{
1760 gen_op_load_cr();
1761 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1762}
1763
1764/* mfmsr */
1765GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1766{
9a64fbe4
FB		 1767#if defined(CONFIG_USER_ONLY)
1768 RET_PRIVREG();
1769#else
1770 if (!ctx->supervisor) {
1771 RET_PRIVREG();
1772 }
79aceca5
FB		 1773 gen_op_load_msr();
1774 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 1775#endif
79aceca5
FB		 1776}
1777
1778/* mfspr */
1779GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1780{
1781 uint32_t sprn = SPR(ctx->opcode);
1782
9a64fbe4
FB		 1783#if defined(CONFIG_USER_ONLY)
1784 switch (check_spr_access(sprn, 0, 0))
1785#else
1786 switch (check_spr_access(sprn, 0, ctx->supervisor))
1787#endif
1788 {
1789 case -1:
1790 RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1791 break;
1792 case 0:
1793 RET_PRIVREG();
1794 break;
1795 default:
1796 break;
79aceca5 1797 }
9a64fbe4
FB		 1798 switch (sprn) {
1799 case XER:
79aceca5
FB		 1800 gen_op_load_xer();
1801 break;
9a64fbe4
FB		 1802 case LR:
1803 gen_op_load_lr();
1804 break;
1805 case CTR:
1806 gen_op_load_ctr();
1807 break;
1808 case IBAT0U:
1809 gen_op_load_ibat(0, 0);
1810 break;
1811 case IBAT1U:
1812 gen_op_load_ibat(0, 1);
1813 break;
1814 case IBAT2U:
1815 gen_op_load_ibat(0, 2);
1816 break;
1817 case IBAT3U:
1818 gen_op_load_ibat(0, 3);
1819 break;
1820 case IBAT4U:
1821 gen_op_load_ibat(0, 4);
1822 break;
1823 case IBAT5U:
1824 gen_op_load_ibat(0, 5);
1825 break;
1826 case IBAT6U:
1827 gen_op_load_ibat(0, 6);
1828 break;
1829 case IBAT7U:
1830 gen_op_load_ibat(0, 7);
1831 break;
1832 case IBAT0L:
1833 gen_op_load_ibat(1, 0);
1834 break;
1835 case IBAT1L:
1836 gen_op_load_ibat(1, 1);
1837 break;
1838 case IBAT2L:
1839 gen_op_load_ibat(1, 2);
1840 break;
1841 case IBAT3L:
1842 gen_op_load_ibat(1, 3);
1843 break;
1844 case IBAT4L:
1845 gen_op_load_ibat(1, 4);
1846 break;
1847 case IBAT5L:
1848 gen_op_load_ibat(1, 5);
1849 break;
1850 case IBAT6L:
1851 gen_op_load_ibat(1, 6);
1852 break;
1853 case IBAT7L:
1854 gen_op_load_ibat(1, 7);
1855 break;
1856 case DBAT0U:
1857 gen_op_load_dbat(0, 0);
1858 break;
1859 case DBAT1U:
1860 gen_op_load_dbat(0, 1);
1861 break;
1862 case DBAT2U:
1863 gen_op_load_dbat(0, 2);
1864 break;
1865 case DBAT3U:
1866 gen_op_load_dbat(0, 3);
1867 break;
1868 case DBAT4U:
1869 gen_op_load_dbat(0, 4);
1870 break;
1871 case DBAT5U:
1872 gen_op_load_dbat(0, 5);
1873 break;
1874 case DBAT6U:
1875 gen_op_load_dbat(0, 6);
1876 break;
1877 case DBAT7U:
1878 gen_op_load_dbat(0, 7);
1879 break;
1880 case DBAT0L:
1881 gen_op_load_dbat(1, 0);
1882 break;
1883 case DBAT1L:
1884 gen_op_load_dbat(1, 1);
1885 break;
1886 case DBAT2L:
1887 gen_op_load_dbat(1, 2);
1888 break;
1889 case DBAT3L:
1890 gen_op_load_dbat(1, 3);
1891 break;
1892 case DBAT4L:
1893 gen_op_load_dbat(1, 4);
1894 break;
1895 case DBAT5L:
1896 gen_op_load_dbat(1, 5);
1897 break;
1898 case DBAT6L:
1899 gen_op_load_dbat(1, 6);
1900 break;
1901 case DBAT7L:
1902 gen_op_load_dbat(1, 7);
1903 break;
1904 case SDR1:
1905 gen_op_load_sdr1();
1906 break;
1907 case V_TBL:
79aceca5
FB		 1908 gen_op_update_tb(ctx->tb_offset);
1909 ctx->tb_offset = 0;
9a64fbe4 1910 /* TBL is still in T0 */
79aceca5 1911 break;
9a64fbe4 1912 case V_TBU:
79aceca5
FB		 1913 gen_op_update_tb(ctx->tb_offset);
1914 ctx->tb_offset = 0;
9a64fbe4
FB		 1915 gen_op_load_tb(1);
1916 break;
1917 case DECR:
1918 gen_op_update_decr(ctx->decr_offset);
1919 ctx->decr_offset = 0;
1920 /* decr is still in T0 */
79aceca5
FB		 1921 break;
1922 default:
1923 gen_op_load_spr(sprn);
1924 break;
1925 }
9a64fbe4 1926 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1927}
1928
1929/* mftb */
1930GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
1931{
1932 uint32_t sprn = SPR(ctx->opcode);
1933
79aceca5 1934 /* We need to update the time base before reading it */
9a64fbe4
FB		 1935 switch (sprn) {
1936 case V_TBL:
79aceca5 1937 gen_op_update_tb(ctx->tb_offset);
9a64fbe4 1938 /* TBL is still in T0 */
79aceca5 1939 break;
9a64fbe4 1940 case V_TBU:
79aceca5 1941 gen_op_update_tb(ctx->tb_offset);
9a64fbe4 1942 gen_op_load_tb(1);
79aceca5
FB		 1943 break;
1944 default:
9a64fbe4 1945 RET_INVAL();
79aceca5
FB		 1946 break;
1947 }
9a64fbe4
FB		 1948 ctx->tb_offset = 0;
1949 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1950}
1951
1952/* mtcrf */
1953GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
1954{
1955 gen_op_load_gpr_T0(rS(ctx->opcode));
1956 gen_op_store_cr(CRM(ctx->opcode));
79aceca5
FB		 1957}
1958
1959/* mtmsr */
1960GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
1961{
9a64fbe4
FB		 1962#if defined(CONFIG_USER_ONLY)
1963 RET_PRIVREG();
1964#else
1965 if (!ctx->supervisor) {
1966 RET_PRIVREG();
1967 }
79aceca5
FB		 1968 gen_op_load_gpr_T0(rS(ctx->opcode));
1969 gen_op_store_msr();
1970 /* Must stop the translation as machine state (may have) changed */
9a64fbe4
FB		 1971 ctx->exception = EXCP_MTMSR;
1972#endif
79aceca5
FB		 1973}
1974
1975/* mtspr */
1976GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
1977{
1978 uint32_t sprn = SPR(ctx->opcode);
1979
9a64fbe4
FB		 1980#if 0
1981 if (loglevel > 0) {
1982 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
1983 rS(ctx->opcode), sprn);
1984 }
1985#endif
1986#if defined(CONFIG_USER_ONLY)
1987 switch (check_spr_access(sprn, 1, 0))
1988#else
1989 switch (check_spr_access(sprn, 1, ctx->supervisor))
1990#endif
1991 {
1992 case -1:
1993 RET_EXCP(EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1994 break;
1995 case 0:
1996 RET_PRIVREG();
1997 break;
1998 default:
1999 break;
2000 }
79aceca5 2001 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4
FB		 2002 switch (sprn) {
2003 case XER:
79aceca5 2004 gen_op_store_xer();
9a64fbe4
FB		 2005 break;
2006 case LR:
2007 gen_op_andi_(~0x03);
2008 gen_op_store_lr();
2009 break;
2010 case CTR:
2011 gen_op_store_ctr();
2012 break;
2013 case IBAT0U:
2014 gen_op_store_ibat(0, 0);
2015 gen_op_tlbia();
2016 break;
2017 case IBAT1U:
2018 gen_op_store_ibat(0, 1);
2019 gen_op_tlbia();
2020 break;
2021 case IBAT2U:
2022 gen_op_store_ibat(0, 2);
2023 gen_op_tlbia();
2024 break;
2025 case IBAT3U:
2026 gen_op_store_ibat(0, 3);
2027 gen_op_tlbia();
2028 break;
2029 case IBAT4U:
2030 gen_op_store_ibat(0, 4);
2031 gen_op_tlbia();
2032 break;
2033 case IBAT5U:
2034 gen_op_store_ibat(0, 5);
2035 gen_op_tlbia();
2036 break;
2037 case IBAT6U:
2038 gen_op_store_ibat(0, 6);
2039 gen_op_tlbia();
2040 break;
2041 case IBAT7U:
2042 gen_op_store_ibat(0, 7);
2043 gen_op_tlbia();
2044 break;
2045 case IBAT0L:
2046 gen_op_store_ibat(1, 0);
2047 gen_op_tlbia();
2048 break;
2049 case IBAT1L:
2050 gen_op_store_ibat(1, 1);
2051 gen_op_tlbia();
2052 break;
2053 case IBAT2L:
2054 gen_op_store_ibat(1, 2);
2055 gen_op_tlbia();
2056 break;
2057 case IBAT3L:
2058 gen_op_store_ibat(1, 3);
2059 gen_op_tlbia();
2060 break;
2061 case IBAT4L:
2062 gen_op_store_ibat(1, 4);
2063 gen_op_tlbia();
2064 break;
2065 case IBAT5L:
2066 gen_op_store_ibat(1, 5);
2067 gen_op_tlbia();
2068 break;
2069 case IBAT6L:
2070 gen_op_store_ibat(1, 6);
2071 gen_op_tlbia();
2072 break;
2073 case IBAT7L:
2074 gen_op_store_ibat(1, 7);
2075 gen_op_tlbia();
2076 break;
2077 case DBAT0U:
2078 gen_op_store_dbat(0, 0);
2079 gen_op_tlbia();
2080 break;
2081 case DBAT1U:
2082 gen_op_store_dbat(0, 1);
2083 gen_op_tlbia();
2084 break;
2085 case DBAT2U:
2086 gen_op_store_dbat(0, 2);
2087 gen_op_tlbia();
2088 break;
2089 case DBAT3U:
2090 gen_op_store_dbat(0, 3);
2091 gen_op_tlbia();
2092 break;
2093 case DBAT4U:
2094 gen_op_store_dbat(0, 4);
2095 gen_op_tlbia();
2096 break;
2097 case DBAT5U:
2098 gen_op_store_dbat(0, 5);
2099 gen_op_tlbia();
2100 break;
2101 case DBAT6U:
2102 gen_op_store_dbat(0, 6);
2103 gen_op_tlbia();
2104 break;
2105 case DBAT7U:
2106 gen_op_store_dbat(0, 7);
2107 gen_op_tlbia();
2108 break;
2109 case DBAT0L:
2110 gen_op_store_dbat(1, 0);
2111 gen_op_tlbia();
2112 break;
2113 case DBAT1L:
2114 gen_op_store_dbat(1, 1);
2115 gen_op_tlbia();
2116 break;
2117 case DBAT2L:
2118 gen_op_store_dbat(1, 2);
2119 gen_op_tlbia();
2120 break;
2121 case DBAT3L:
2122 gen_op_store_dbat(1, 3);
2123 gen_op_tlbia();
2124 break;
2125 case DBAT4L:
2126 gen_op_store_dbat(1, 4);
2127 gen_op_tlbia();
2128 break;
2129 case DBAT5L:
2130 gen_op_store_dbat(1, 5);
2131 gen_op_tlbia();
2132 break;
2133 case DBAT6L:
2134 gen_op_store_dbat(1, 6);
2135 gen_op_tlbia();
2136 break;
2137 case DBAT7L:
2138 gen_op_store_dbat(1, 7);
2139 gen_op_tlbia();
2140 break;
2141 case SDR1:
2142 gen_op_store_sdr1();
2143 gen_op_tlbia();
2144 break;
2145 case O_TBL:
2146 gen_op_store_tb(0);
2147 ctx->tb_offset = 0;
2148 break;
2149 case O_TBU:
2150 gen_op_store_tb(1);
2151 ctx->tb_offset = 0;
2152 break;
2153 case DECR:
2154 gen_op_store_decr();
2155 ctx->decr_offset = 0;
2156 break;
2157 default:
79aceca5 2158 gen_op_store_spr(sprn);
9a64fbe4 2159 break;
79aceca5 2160 }
79aceca5
FB		 2161}
2162
2163/*** Cache management ***/
2164/* For now, all those will be implemented as nop:
2165 * this is valid, regarding the PowerPC specs...
9a64fbe4 2166 * We just have to flush tb while invalidating instruction cache lines...
79aceca5
FB		 2167 */
2168/* dcbf */
9a64fbe4 2169GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
79aceca5 2170{
a541f297
FB		 2171 if (rA(ctx->opcode) == 0) {
2172 gen_op_load_gpr_T0(rB(ctx->opcode));
2173 } else {
2174 gen_op_load_gpr_T0(rA(ctx->opcode));
2175 gen_op_load_gpr_T1(rB(ctx->opcode));
2176 gen_op_add();
2177 }
2178 op_ldst(lbz);
79aceca5
FB		 2179}
2180
2181/* dcbi (Supervisor only) */
9a64fbe4 2182GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 2183{
a541f297
FB		 2184#if defined(CONFIG_USER_ONLY)
2185 RET_PRIVOPC();
2186#else
2187 if (!ctx->supervisor) {
9a64fbe4
FB		 2188 RET_PRIVOPC();
2189 }
a541f297
FB		 2190 if (rA(ctx->opcode) == 0) {
2191 gen_op_load_gpr_T0(rB(ctx->opcode));
2192 } else {
2193 gen_op_load_gpr_T0(rA(ctx->opcode));
2194 gen_op_load_gpr_T1(rB(ctx->opcode));
2195 gen_op_add();
2196 }
2197 op_ldst(lbz);
2198 op_ldst(stb);
2199#endif
79aceca5
FB		 2200}
2201
2202/* dcdst */
9a64fbe4 2203GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 2204{
a541f297
FB		 2205 if (rA(ctx->opcode) == 0) {
2206 gen_op_load_gpr_T0(rB(ctx->opcode));
2207 } else {
2208 gen_op_load_gpr_T0(rA(ctx->opcode));
2209 gen_op_load_gpr_T1(rB(ctx->opcode));
2210 gen_op_add();
2211 }
2212 op_ldst(lbz);
79aceca5
FB		 2213}
2214
2215/* dcbt */
9a64fbe4 2216GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
79aceca5 2217{
79aceca5
FB		 2218}
2219
2220/* dcbtst */
9a64fbe4 2221GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
79aceca5 2222{
79aceca5
FB		 2223}
2224
2225/* dcbz */
9a64fbe4
FB		 2226#if defined(CONFIG_USER_ONLY)
2227#define op_dcbz() gen_op_dcbz_raw()
2228#else
2229#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2230static GenOpFunc *gen_op_dcbz[] = {
2231 &gen_op_dcbz_user,
2232 &gen_op_dcbz_kernel,
2233};
2234#endif
2235
2236GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
79aceca5 2237{
fb0eaffc
FB		 2238 if (rA(ctx->opcode) == 0) {
2239 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2240 } else {
2241 gen_op_load_gpr_T0(rA(ctx->opcode));
2242 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2243 gen_op_add();
fb0eaffc 2244 }
9a64fbe4 2245 op_dcbz();
79aceca5
FB		 2246}
2247
2248/* icbi */
9a64fbe4 2249GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
79aceca5 2250{
fb0eaffc
FB		 2251 if (rA(ctx->opcode) == 0) {
2252 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2253 } else {
2254 gen_op_load_gpr_T0(rA(ctx->opcode));
2255 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2256 gen_op_add();
fb0eaffc 2257 }
9a64fbe4 2258 gen_op_icbi();
79aceca5
FB		 2259}
2260
2261/* Optional: */
2262/* dcba */
9a64fbe4 2263GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
79aceca5 2264{
79aceca5
FB		 2265}
2266
2267/*** Segment register manipulation ***/
2268/* Supervisor only: */
2269/* mfsr */
2270GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2271{
9a64fbe4
FB		 2272#if defined(CONFIG_USER_ONLY)
2273 RET_PRIVREG();
2274#else
2275 if (!ctx->supervisor) {
2276 RET_PRIVREG();
2277 }
2278 gen_op_load_sr(SR(ctx->opcode));
2279 gen_op_store_T0_gpr(rD(ctx->opcode));
2280#endif
79aceca5
FB		 2281}
2282
2283/* mfsrin */
9a64fbe4 2284GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 2285{
9a64fbe4
FB		 2286#if defined(CONFIG_USER_ONLY)
2287 RET_PRIVREG();
2288#else
2289 if (!ctx->supervisor) {
2290 RET_PRIVREG();
2291 }
2292 gen_op_load_gpr_T1(rB(ctx->opcode));
2293 gen_op_load_srin();
2294 gen_op_store_T0_gpr(rD(ctx->opcode));
2295#endif
79aceca5
FB		 2296}
2297
2298/* mtsr */
2299GEN_HANDLER(mtsr, 0x1F, 0x12, 0x02, 0x0010F801, PPC_SEGMENT)
2300{
9a64fbe4
FB		 2301#if defined(CONFIG_USER_ONLY)
2302 RET_PRIVREG();
2303#else
2304 if (!ctx->supervisor) {
2305 RET_PRIVREG();
2306 }
2307 gen_op_load_gpr_T0(rS(ctx->opcode));
2308 gen_op_store_sr(SR(ctx->opcode));
2309 gen_op_tlbia();
2310#endif
79aceca5
FB		 2311}
2312
2313/* mtsrin */
9a64fbe4 2314GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 2315{
9a64fbe4
FB		 2316#if defined(CONFIG_USER_ONLY)
2317 RET_PRIVREG();
2318#else
2319 if (!ctx->supervisor) {
2320 RET_PRIVREG();
2321 }
2322 gen_op_load_gpr_T0(rS(ctx->opcode));
2323 gen_op_load_gpr_T1(rB(ctx->opcode));
2324 gen_op_store_srin();
2325 gen_op_tlbia();
2326#endif
79aceca5
FB		 2327}
2328
2329/*** Lookaside buffer management ***/
2330/* Optional & supervisor only: */
2331/* tlbia */
9a64fbe4 2332GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
79aceca5 2333{
9a64fbe4
FB		 2334#if defined(CONFIG_USER_ONLY)
2335 RET_PRIVOPC();
2336#else
2337 if (!ctx->supervisor) {
2338 RET_PRIVOPC();
2339 }
2340 gen_op_tlbia();
2341#endif
79aceca5
FB		 2342}
2343
2344/* tlbie */
9a64fbe4 2345GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
79aceca5 2346{
9a64fbe4
FB		 2347#if defined(CONFIG_USER_ONLY)
2348 RET_PRIVOPC();
2349#else
2350 if (!ctx->supervisor) {
2351 RET_PRIVOPC();
2352 }
2353 gen_op_load_gpr_T0(rB(ctx->opcode));
2354 gen_op_tlbie();
2355#endif
79aceca5
FB		 2356}
2357
2358/* tlbsync */
2359GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFFC01, PPC_MEM)
2360{
9a64fbe4
FB		 2361#if defined(CONFIG_USER_ONLY)
2362 RET_PRIVOPC();
2363#else
2364 if (!ctx->supervisor) {
2365 RET_PRIVOPC();
2366 }
2367 /* This has no effect: it should ensure that all previous
2368 * tlbie have completed
2369 */
2370#endif
79aceca5
FB		 2371}
2372
2373/*** External control ***/
2374/* Optional: */
2375/* eciwx */
9a64fbe4
FB		 2376#if defined(CONFIG_USER_ONLY)
2377#define op_eciwx() gen_op_eciwx_raw()
2378#define op_ecowx() gen_op_ecowx_raw()
2379#else
2380#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2381#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2382static GenOpFunc *gen_op_eciwx[] = {
2383 &gen_op_eciwx_user,
2384 &gen_op_eciwx_kernel,
2385};
2386static GenOpFunc *gen_op_ecowx[] = {
2387 &gen_op_ecowx_user,
2388 &gen_op_ecowx_kernel,
2389};
2390#endif
2391
79aceca5
FB		 2392GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2393{
9a64fbe4
FB		 2394 /* Should check EAR[E] & alignment ! */
2395 if (rA(ctx->opcode) == 0) {
2396 gen_op_load_gpr_T0(rB(ctx->opcode));
2397 } else {
2398 gen_op_load_gpr_T0(rA(ctx->opcode));
2399 gen_op_load_gpr_T1(rB(ctx->opcode));
2400 gen_op_add();
2401 }
2402 op_eciwx();
2403 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2404}
2405
2406/* ecowx */
2407GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2408{
9a64fbe4
FB		 2409 /* Should check EAR[E] & alignment ! */
2410 if (rA(ctx->opcode) == 0) {
2411 gen_op_load_gpr_T0(rB(ctx->opcode));
2412 } else {
2413 gen_op_load_gpr_T0(rA(ctx->opcode));
2414 gen_op_load_gpr_T1(rB(ctx->opcode));
2415 gen_op_add();
2416 }
2417 gen_op_load_gpr_T2(rS(ctx->opcode));
2418 op_ecowx();
79aceca5
FB		 2419}
2420
2421/* End opcode list */
2422GEN_OPCODE_MARK(end);
2423
2424/*****************************************************************************/
9a64fbe4 2425#include <stdlib.h>
79aceca5 2426#include <string.h>
9a64fbe4
FB		 2427
2428int fflush (FILE *stream);
79aceca5
FB		 2429
2430/* Main ppc opcodes table:
2431 * at init, all opcodes are invalids
2432 */
2433static opc_handler_t *ppc_opcodes[0x40];
2434
2435/* Opcode types */
2436enum {
2437 PPC_DIRECT = 0, /* Opcode routine */
2438 PPC_INDIRECT = 1, /* Indirect opcode table */
2439};
2440
2441static inline int is_indirect_opcode (void *handler)
2442{
2443 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2444}
2445
2446static inline opc_handler_t **ind_table(void *handler)
2447{
2448 return (opc_handler_t **)((unsigned long)handler & ~3);
2449}
2450
9a64fbe4 2451/* Instruction table creation */
79aceca5
FB		 2452/* Opcodes tables creation */
2453static void fill_new_table (opc_handler_t **table, int len)
2454{
2455 int i;
2456
2457 for (i = 0; i < len; i++)
2458 table[i] = &invalid_handler;
2459}
2460
2461static int create_new_table (opc_handler_t **table, unsigned char idx)
2462{
2463 opc_handler_t **tmp;
2464
2465 tmp = malloc(0x20 * sizeof(opc_handler_t));
2466 if (tmp == NULL)
2467 return -1;
2468 fill_new_table(tmp, 0x20);
2469 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2470
2471 return 0;
2472}
2473
2474static int insert_in_table (opc_handler_t **table, unsigned char idx,
2475 opc_handler_t *handler)
2476{
2477 if (table[idx] != &invalid_handler)
2478 return -1;
2479 table[idx] = handler;
2480
2481 return 0;
2482}
2483
9a64fbe4
FB		 2484static int register_direct_insn (opc_handler_t **ppc_opcodes,
2485 unsigned char idx, opc_handler_t *handler)
79aceca5
FB		 2486{
2487 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9a64fbe4 2488 printf("*** ERROR: opcode %02x already assigned in main "
79aceca5
FB		 2489 "opcode table\n", idx);
2490 return -1;
2491 }
2492
2493 return 0;
2494}
2495
2496static int register_ind_in_table (opc_handler_t **table,
2497 unsigned char idx1, unsigned char idx2,
2498 opc_handler_t *handler)
2499{
2500 if (table[idx1] == &invalid_handler) {
2501 if (create_new_table(table, idx1) < 0) {
9a64fbe4 2502 printf("*** ERROR: unable to create indirect table "
79aceca5
FB		 2503 "idx=%02x\n", idx1);
2504 return -1;
2505 }
2506 } else {
2507 if (!is_indirect_opcode(table[idx1])) {
9a64fbe4 2508 printf("*** ERROR: idx %02x already assigned to a direct "
79aceca5
FB		 2509 "opcode\n", idx1);
2510 return -1;
2511 }
2512 }
2513 if (handler != NULL &&
2514 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9a64fbe4 2515 printf("*** ERROR: opcode %02x already assigned in "
79aceca5
FB		 2516 "opcode table %02x\n", idx2, idx1);
2517 return -1;
2518 }
2519
2520 return 0;
2521}
2522
9a64fbe4
FB		 2523static int register_ind_insn (opc_handler_t **ppc_opcodes,
2524 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2525 opc_handler_t *handler)
2526{
2527 int ret;
2528
2529 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2530
2531 return ret;
2532}
2533
9a64fbe4
FB		 2534static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2535 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2536 unsigned char idx3, opc_handler_t *handler)
2537{
2538 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9a64fbe4 2539 printf("*** ERROR: unable to join indirect table idx "
79aceca5
FB		 2540 "[%02x-%02x]\n", idx1, idx2);
2541 return -1;
2542 }
2543 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2544 handler) < 0) {
9a64fbe4 2545 printf("*** ERROR: unable to insert opcode "
79aceca5
FB		 2546 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2547 return -1;
2548 }
2549
2550 return 0;
2551}
2552
9a64fbe4 2553static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
79aceca5
FB		 2554{
2555 if (insn->opc2 != 0xFF) {
2556 if (insn->opc3 != 0xFF) {
9a64fbe4
FB		 2557 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2558 insn->opc3, &insn->handler) < 0)
79aceca5
FB		 2559 return -1;
2560 } else {
9a64fbe4
FB		 2561 if (register_ind_insn(ppc_opcodes, insn->opc1,
2562 insn->opc2, &insn->handler) < 0)
79aceca5
FB		 2563 return -1;
2564 }
2565 } else {
9a64fbe4 2566 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
79aceca5
FB		 2567 return -1;
2568 }
2569
2570 return 0;
2571}
2572
2573static int test_opcode_table (opc_handler_t **table, int len)
2574{
2575 int i, count, tmp;
2576
2577 for (i = 0, count = 0; i < len; i++) {
2578 /* Consistency fixup */
2579 if (table[i] == NULL)
2580 table[i] = &invalid_handler;
2581 if (table[i] != &invalid_handler) {
2582 if (is_indirect_opcode(table[i])) {
2583 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2584 if (tmp == 0) {
2585 free(table[i]);
2586 table[i] = &invalid_handler;
2587 } else {
2588 count++;
2589 }
2590 } else {
2591 count++;
2592 }
2593 }
2594 }
2595
2596 return count;
2597}
2598
9a64fbe4 2599static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
79aceca5
FB		 2600{
2601 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9a64fbe4 2602 printf("*** WARNING: no opcode defined !\n");
79aceca5
FB		 2603}
2604
9a64fbe4 2605#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
79aceca5
FB		 2606#define SPR_UR SPR_RIGHTS(0, 0)
2607#define SPR_UW SPR_RIGHTS(1, 0)
2608#define SPR_SR SPR_RIGHTS(0, 1)
2609#define SPR_SW SPR_RIGHTS(1, 1)
2610
2611#define spr_set_rights(spr, rights) \
2612do { \
2613 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2614} while (0)
2615
9a64fbe4 2616static void init_spr_rights (uint32_t pvr)
79aceca5
FB		 2617{
2618 /* XER (SPR 1) */
9a64fbe4 2619 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2620 /* LR (SPR 8) */
9a64fbe4 2621 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2622 /* CTR (SPR 9) */
9a64fbe4 2623 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2624 /* TBL (SPR 268) */
9a64fbe4 2625 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
79aceca5 2626 /* TBU (SPR 269) */
9a64fbe4 2627 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
79aceca5 2628 /* DSISR (SPR 18) */
9a64fbe4 2629 spr_set_rights(DSISR, SPR_SR | SPR_SW);
79aceca5 2630 /* DAR (SPR 19) */
9a64fbe4 2631 spr_set_rights(DAR, SPR_SR | SPR_SW);
79aceca5 2632 /* DEC (SPR 22) */
9a64fbe4 2633 spr_set_rights(DECR, SPR_SR | SPR_SW);
79aceca5 2634 /* SDR1 (SPR 25) */
9a64fbe4
FB		 2635 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2636 /* SRR0 (SPR 26) */
2637 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2638 /* SRR1 (SPR 27) */
2639 spr_set_rights(SRR1, SPR_SR | SPR_SW);
79aceca5 2640 /* SPRG0 (SPR 272) */
9a64fbe4 2641 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
79aceca5 2642 /* SPRG1 (SPR 273) */
9a64fbe4 2643 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
79aceca5 2644 /* SPRG2 (SPR 274) */
9a64fbe4 2645 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
79aceca5 2646 /* SPRG3 (SPR 275) */
9a64fbe4 2647 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
79aceca5 2648 /* ASR (SPR 280) */
9a64fbe4 2649 spr_set_rights(ASR, SPR_SR | SPR_SW);
79aceca5 2650 /* EAR (SPR 282) */
9a64fbe4
FB		 2651 spr_set_rights(EAR, SPR_SR | SPR_SW);
2652 /* TBL (SPR 284) */
2653 spr_set_rights(O_TBL, SPR_SW);
2654 /* TBU (SPR 285) */
2655 spr_set_rights(O_TBU, SPR_SW);
2656 /* PVR (SPR 287) */
2657 spr_set_rights(PVR, SPR_SR);
79aceca5 2658 /* IBAT0U (SPR 528) */
9a64fbe4 2659 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
79aceca5 2660 /* IBAT0L (SPR 529) */
9a64fbe4 2661 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
79aceca5 2662 /* IBAT1U (SPR 530) */
9a64fbe4 2663 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
79aceca5 2664 /* IBAT1L (SPR 531) */
9a64fbe4 2665 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
79aceca5 2666 /* IBAT2U (SPR 532) */
9a64fbe4 2667 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
79aceca5 2668 /* IBAT2L (SPR 533) */
9a64fbe4 2669 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
79aceca5 2670 /* IBAT3U (SPR 534) */
9a64fbe4 2671 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
79aceca5 2672 /* IBAT3L (SPR 535) */
9a64fbe4 2673 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
79aceca5 2674 /* DBAT0U (SPR 536) */
9a64fbe4 2675 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
79aceca5 2676 /* DBAT0L (SPR 537) */
9a64fbe4 2677 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
79aceca5 2678 /* DBAT1U (SPR 538) */
9a64fbe4 2679 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
79aceca5 2680 /* DBAT1L (SPR 539) */
9a64fbe4 2681 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
79aceca5 2682 /* DBAT2U (SPR 540) */
9a64fbe4 2683 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
79aceca5 2684 /* DBAT2L (SPR 541) */
9a64fbe4 2685 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
79aceca5 2686 /* DBAT3U (SPR 542) */
9a64fbe4 2687 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
79aceca5 2688 /* DBAT3L (SPR 543) */
9a64fbe4 2689 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
79aceca5 2690 /* DABR (SPR 1013) */
9a64fbe4 2691 spr_set_rights(DABR, SPR_SR | SPR_SW);
79aceca5 2692 /* FPECR (SPR 1022) */
9a64fbe4 2693 spr_set_rights(FPECR, SPR_SR | SPR_SW);
79aceca5 2694 /* PIR (SPR 1023) */
9a64fbe4
FB		 2695 spr_set_rights(PIR, SPR_SR | SPR_SW);
2696 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2697 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2698 (pvr & 0xFFFF0000) == 0x70000000) {
2699 /* HID0 */
2700 spr_set_rights(SPR_ENCODE(1008), SPR_SR | SPR_SW);
2701 /* HID1 */
2702 spr_set_rights(SPR_ENCODE(1009), SPR_SR | SPR_SW);
2703 /* IABR */
2704 spr_set_rights(SPR_ENCODE(1010), SPR_SR | SPR_SW);
2705 /* ICTC */
2706 spr_set_rights(SPR_ENCODE(1019), SPR_SR | SPR_SW);
2707 /* L2CR */
2708 spr_set_rights(SPR_ENCODE(1017), SPR_SR | SPR_SW);
2709 /* MMCR0 */
2710 spr_set_rights(SPR_ENCODE(952), SPR_SR | SPR_SW);
2711 /* MMCR1 */
2712 spr_set_rights(SPR_ENCODE(956), SPR_SR | SPR_SW);
2713 /* PMC1 */
2714 spr_set_rights(SPR_ENCODE(953), SPR_SR | SPR_SW);
2715 /* PMC2 */
2716 spr_set_rights(SPR_ENCODE(954), SPR_SR | SPR_SW);
2717 /* PMC3 */
2718 spr_set_rights(SPR_ENCODE(957), SPR_SR | SPR_SW);
2719 /* PMC4 */
2720 spr_set_rights(SPR_ENCODE(958), SPR_SR | SPR_SW);
2721 /* SIA */
2722 spr_set_rights(SPR_ENCODE(955), SPR_SR | SPR_SW);
2723 /* THRM1 */
2724 spr_set_rights(SPR_ENCODE(1020), SPR_SR | SPR_SW);
2725 /* THRM2 */
2726 spr_set_rights(SPR_ENCODE(1021), SPR_SR | SPR_SW);
2727 /* THRM3 */
2728 spr_set_rights(SPR_ENCODE(1022), SPR_SR | SPR_SW);
2729 /* UMMCR0 */
2730 spr_set_rights(SPR_ENCODE(936), SPR_UR | SPR_UW);
2731 /* UMMCR1 */
2732 spr_set_rights(SPR_ENCODE(940), SPR_UR | SPR_UW);
2733 /* UPMC1 */
2734 spr_set_rights(SPR_ENCODE(937), SPR_UR | SPR_UW);
2735 /* UPMC2 */
2736 spr_set_rights(SPR_ENCODE(938), SPR_UR | SPR_UW);
2737 /* UPMC3 */
2738 spr_set_rights(SPR_ENCODE(941), SPR_UR | SPR_UW);
2739 /* UPMC4 */
2740 spr_set_rights(SPR_ENCODE(942), SPR_UR | SPR_UW);
2741 /* USIA */
2742 spr_set_rights(SPR_ENCODE(939), SPR_UR | SPR_UW);
2743 }
2744 /* MPC755 has special registers */
2745 if (pvr == 0x00083100) {
2746 /* SPRG4 */
2747 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2748 /* SPRG5 */
2749 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2750 /* SPRG6 */
2751 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2752 /* SPRG7 */
2753 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2754 /* IBAT4U */
2755 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2756 /* IBAT4L */
2757 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2758 /* IBAT5U */
2759 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2760 /* IBAT5L */
2761 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2762 /* IBAT6U */
2763 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2764 /* IBAT6L */
2765 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2766 /* IBAT7U */
2767 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2768 /* IBAT7L */
2769 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2770 /* DBAT4U */
2771 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2772 /* DBAT4L */
2773 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2774 /* DBAT5U */
2775 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2776 /* DBAT5L */
2777 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2778 /* DBAT6U */
2779 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2780 /* DBAT6L */
2781 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2782 /* DBAT7U */
2783 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2784 /* DBAT7L */
2785 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2786 /* DMISS */
2787 spr_set_rights(SPR_ENCODE(976), SPR_SR | SPR_SW);
2788 /* DCMP */
2789 spr_set_rights(SPR_ENCODE(977), SPR_SR | SPR_SW);
2790 /* DHASH1 */
2791 spr_set_rights(SPR_ENCODE(978), SPR_SR | SPR_SW);
2792 /* DHASH2 */
2793 spr_set_rights(SPR_ENCODE(979), SPR_SR | SPR_SW);
2794 /* IMISS */
2795 spr_set_rights(SPR_ENCODE(980), SPR_SR | SPR_SW);
2796 /* ICMP */
2797 spr_set_rights(SPR_ENCODE(981), SPR_SR | SPR_SW);
2798 /* RPA */
2799 spr_set_rights(SPR_ENCODE(982), SPR_SR | SPR_SW);
2800 /* HID2 */
2801 spr_set_rights(SPR_ENCODE(1011), SPR_SR | SPR_SW);
2802 /* L2PM */
2803 spr_set_rights(SPR_ENCODE(1016), SPR_SR | SPR_SW);
2804 }
79aceca5
FB		 2805}
2806
9a64fbe4
FB		 2807/*****************************************************************************/
2808/* PPC "main stream" common instructions (no optional ones) */
79aceca5
FB		 2809
2810typedef struct ppc_proc_t {
2811 int flags;
2812 void *specific;
2813} ppc_proc_t;
2814
2815typedef struct ppc_def_t {
2816 unsigned long pvr;
2817 unsigned long pvr_mask;
2818 ppc_proc_t *proc;
2819} ppc_def_t;
2820
2821static ppc_proc_t ppc_proc_common = {
2822 .flags = PPC_COMMON,
2823 .specific = NULL,
2824};
2825
9a64fbe4
FB		 2826static ppc_proc_t ppc_proc_G3 = {
2827 .flags = PPC_750,
2828 .specific = NULL,
2829};
2830
79aceca5
FB		 2831static ppc_def_t ppc_defs[] =
2832{
9a64fbe4
FB		 2833 /* MPC740/745/750/755 (G3) */
2834 {
2835 .pvr = 0x00080000,
2836 .pvr_mask = 0xFFFF0000,
2837 .proc = &ppc_proc_G3,
2838 },
2839 /* IBM 750FX (G3 embedded) */
2840 {
2841 .pvr = 0x70000000,
2842 .pvr_mask = 0xFFFF0000,
2843 .proc = &ppc_proc_G3,
2844 },
2845 /* Fallback (generic PPC) */
79aceca5
FB		 2846 {
2847 .pvr = 0x00000000,
2848 .pvr_mask = 0x00000000,
2849 .proc = &ppc_proc_common,
2850 },
2851};
2852
9a64fbe4 2853static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
79aceca5
FB		 2854{
2855 opcode_t *opc;
2856 int i, flags;
2857
2858 fill_new_table(ppc_opcodes, 0x40);
2859 for (i = 0; ; i++) {
2860 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2861 (pvr & ppc_defs[i].pvr_mask)) {
2862 flags = ppc_defs[i].proc->flags;
2863 break;
2864 }
2865 }
2866
2867 for (opc = &opc_start + 1; opc != &opc_end; opc++) {
9a64fbe4
FB		 2868 if ((opc->handler.type & flags) != 0)
2869 if (register_insn(ppc_opcodes, opc) < 0) {
2870 printf("*** ERROR initializing PPC instruction "
79aceca5
FB		 2871 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2872 opc->opc3);
2873 return -1;
2874 }
2875 }
9a64fbe4 2876 fix_opcode_tables(ppc_opcodes);
79aceca5
FB		 2877
2878 return 0;
2879}
2880
9a64fbe4 2881
79aceca5 2882/*****************************************************************************/
9a64fbe4
FB		 2883/* Misc PPC helpers */
2884FILE *stdout;
79aceca5
FB		 2885
2886void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags)
2887{
2888 int i;
2889
9a64fbe4
FB		 2890 fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
2891 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
a541f297 2892 _load_xer(env), _load_msr(env));
79aceca5
FB		 2893 for (i = 0; i < 32; i++) {
2894 if ((i & 7) == 0)
9a64fbe4
FB		 2895 fprintf(f, "GPR%02d:", i);
2896 fprintf(f, " %08x", env->gpr[i]);
79aceca5 2897 if ((i & 7) == 7)
9a64fbe4 2898 fprintf(f, "\n");
79aceca5 2899 }
9a64fbe4 2900 fprintf(f, "CR: 0x");
79aceca5 2901 for (i = 0; i < 8; i++)
9a64fbe4
FB		 2902 fprintf(f, "%01x", env->crf[i]);
2903 fprintf(f, " [");
79aceca5
FB		 2904 for (i = 0; i < 8; i++) {
2905 char a = '-';
79aceca5
FB		 2906 if (env->crf[i] & 0x08)
2907 a = 'L';
2908 else if (env->crf[i] & 0x04)
2909 a = 'G';
2910 else if (env->crf[i] & 0x02)
2911 a = 'E';
9a64fbe4 2912 fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
79aceca5 2913 }
9a64fbe4
FB		 2914 fprintf(f, " ] ");
2915 fprintf(f, "TB: 0x%08x %08x\n", env->tb[1], env->tb[0]);
79aceca5
FB		 2916 for (i = 0; i < 16; i++) {
2917 if ((i & 3) == 0)
9a64fbe4
FB		 2918 fprintf(f, "FPR%02d:", i);
2919 fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
79aceca5 2920 if ((i & 3) == 3)
9a64fbe4 2921 fprintf(f, "\n");
79aceca5 2922 }
a541f297
FB		 2923 fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x excp:0x%08x\n",
2924 env->spr[SRR0], env->spr[SRR1], env->decr, env->exceptions);
9a64fbe4
FB		 2925 fprintf(f, "reservation 0x%08x\n", env->reserve);
2926 fflush(f);
79aceca5
FB		 2927}
2928
9a64fbe4
FB		 2929#if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
2930int setup_machine (CPUPPCState *env, uint32_t mid);
2931#endif
2932
79aceca5
FB		 2933CPUPPCState *cpu_ppc_init(void)
2934{
2935 CPUPPCState *env;
2936
2937 cpu_exec_init();
2938
2939 env = malloc(sizeof(CPUPPCState));
2940 if (!env)
2941 return NULL;
2942 memset(env, 0, sizeof(CPUPPCState));
9a64fbe4
FB		 2943#if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
2944 setup_machine(env, 0);
2945#else
2946// env->spr[PVR] = 0; /* Basic PPC */
2947 env->spr[PVR] = 0x00080100; /* G3 CPU */
2948// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
2949// env->spr[PVR] = 0x00070100; /* IBM 750FX */
2950#endif
2951 env->decr = 0xFFFFFFFF;
2952 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
79aceca5 2953 return NULL;
9a64fbe4 2954 init_spr_rights(env->spr[PVR]);
ad081323 2955 tlb_flush(env, 1);
9a64fbe4
FB		 2956#if defined (DO_SINGLE_STEP)
2957 /* Single step trace mode */
2958 msr_se = 1;
2959#endif
2960#if defined(CONFIG_USER_ONLY)
2961 msr_pr = 1;
2962#endif
a541f297 2963 env->access_type = ACCESS_INT;
79aceca5
FB		 2964
2965 return env;
2966}
2967
2968void cpu_ppc_close(CPUPPCState *env)
2969{
2970 /* Should also remove all opcode tables... */
2971 free(env);
2972}
2973
9a64fbe4
FB		 2974/*****************************************************************************/
2975void raise_exception_err (int exception_index, int error_code);
2976int print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr,
2977 int dialect);
2978
79aceca5
FB		 2979int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
2980 int search_pc)
2981{
2982 DisasContext ctx;
2983 opc_handler_t **table, *handler;
2984 uint32_t pc_start;
2985 uint16_t *gen_opc_end;
2986 int j, lj = -1;
79aceca5
FB		 2987
2988 pc_start = tb->pc;
2989 gen_opc_ptr = gen_opc_buf;
2990 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2991 gen_opparam_ptr = gen_opparam_buf;
2992 ctx.nip = (uint32_t *)pc_start;
2993 ctx.tb_offset = 0;
9a64fbe4 2994 ctx.decr_offset = 0;
79aceca5 2995 ctx.tb = tb;
9a64fbe4
FB		 2996 ctx.exception = EXCP_NONE;
2997#if defined(CONFIG_USER_ONLY)
2998 ctx.mem_idx = 0;
2999#else
3000 ctx.supervisor = 1 - msr_pr;
3001 ctx.mem_idx = (1 - msr_pr);
3002#endif
3003#if defined (DO_SINGLE_STEP)
3004 /* Single step trace mode */
3005 msr_se = 1;
3006#endif
a541f297 3007 env->access_type = ACCESS_CODE;
9a64fbe4
FB		 3008 /* Set env in case of segfault during code fetch */
3009 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
79aceca5
FB		 3010 if (search_pc) {
3011 if (loglevel > 0)
3012 fprintf(logfile, "Search PC...\n");
3013 j = gen_opc_ptr - gen_opc_buf;
3014 if (lj < j) {
3015 lj++;
3016 while (lj < j)
3017 gen_opc_instr_start[lj++] = 0;
3018 gen_opc_pc[lj] = (uint32_t)ctx.nip;
3019 gen_opc_instr_start[lj] = 1;
3020 }
3021 }
9a64fbe4 3022#if defined DEBUG_DISAS
79aceca5
FB		 3023 if (loglevel > 0) {
3024 fprintf(logfile, "----------------\n");
9a64fbe4
FB		 3025 fprintf(logfile, "nip=%p super=%d ir=%d\n",
3026 ctx.nip, 1 - msr_pr, msr_ir);
3027 }
3028#endif
3029 ctx.opcode = ldl_code(ctx.nip);
3030#if defined DEBUG_DISAS
3031 if (loglevel > 0) {
3032 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3033 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3034 opc3(ctx.opcode));
79aceca5
FB		 3035 }
3036#endif
3037 ctx.nip++;
9a64fbe4
FB		 3038 ctx.tb_offset++;
3039 /* Check decrementer exception */
3040 if (++ctx.decr_offset == env->decr + 1)
3041 ctx.exception = EXCP_DECR;
79aceca5
FB		 3042 table = ppc_opcodes;
3043 handler = table[opc1(ctx.opcode)];
3044 if (is_indirect_opcode(handler)) {
3045 table = ind_table(handler);
3046 handler = table[opc2(ctx.opcode)];
3047 if (is_indirect_opcode(handler)) {
3048 table = ind_table(handler);
3049 handler = table[opc3(ctx.opcode)];
3050 }
3051 }
3052 /* Is opcode *REALLY* valid ? */
3053 if ((ctx.opcode & handler->inval) != 0) {
3054 if (loglevel > 0) {
3055 if (handler->handler == &gen_invalid) {
3056 fprintf(logfile, "invalid/unsupported opcode: "
9a64fbe4
FB		 3057 "%02x -%02x - %02x (%08x) %p\n",
3058 opc1(ctx.opcode), opc2(ctx.opcode),
3059 opc3(ctx.opcode), ctx.opcode, ctx.nip - 1);
79aceca5
FB		 3060 } else {
3061 fprintf(logfile, "invalid bits: %08x for opcode: "
9a64fbe4 3062 "%02x -%02x - %02x (0x%08x) (%p)\n",
79aceca5
FB		 3063 ctx.opcode & handler->inval, opc1(ctx.opcode),
3064 opc2(ctx.opcode), opc3(ctx.opcode),
9a64fbe4 3065 ctx.opcode, ctx.nip - 1);
79aceca5 3066 }
9a64fbe4
FB		 3067 } else {
3068 if (handler->handler == &gen_invalid) {
3069 printf("invalid/unsupported opcode: "
3070 "%02x -%02x - %02x (%08x) %p\n",
3071 opc1(ctx.opcode), opc2(ctx.opcode),
3072 opc3(ctx.opcode), ctx.opcode, ctx.nip - 1);
3073 } else {
3074 printf("invalid bits: %08x for opcode: "
3075 "%02x -%02x - %02x (0x%08x) (%p)\n",
3076 ctx.opcode & handler->inval, opc1(ctx.opcode),
3077 opc2(ctx.opcode), opc3(ctx.opcode),
3078 ctx.opcode, ctx.nip - 1);
3079 }
79aceca5 3080 }
9a64fbe4 3081 (*gen_invalid)(&ctx);
79aceca5 3082 } else {
9a64fbe4 3083 (*(handler->handler))(&ctx);
79aceca5 3084 }
9a64fbe4
FB		 3085 /* Check trace mode exceptions */
3086 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3087 /* Check in single step trace mode
3088 * we need to stop except if:
3089 * - rfi, trap or syscall
3090 * - first instruction of an exception handler
3091 */
3092 (msr_se && ((uint32_t)ctx.nip < 0x100 ||
3093 (uint32_t)ctx.nip > 0xF00 ||
3094 ((uint32_t)ctx.nip & 0xFC) != 0x04) &&
3095 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3096 ctx.exception != EXCP_TRAP)) {
3097#if !defined(CONFIG_USER_ONLY)
3098 gen_op_queue_exception(EXCP_TRACE);
79aceca5 3099#endif
9a64fbe4
FB		 3100 if (ctx.exception == EXCP_NONE) {
3101 ctx.exception = EXCP_TRACE;
79aceca5 3102 }
9a64fbe4 3103 }
a541f297
FB		 3104 /* if we reach a page boundary, stop generation */
3105 if (((uint32_t)ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
9a64fbe4 3106 if (ctx.exception == EXCP_NONE) {
e98a6e40 3107 gen_op_b((long)ctx.tb, (uint32_t)ctx.nip);
9a64fbe4 3108 ctx.exception = EXCP_BRANCH;
79aceca5 3109 }
79aceca5 3110 }
9a64fbe4
FB		 3111 }
3112 /* In case of branch, this has already been done *BEFORE* the branch */
3113 if (ctx.exception != EXCP_BRANCH && ctx.exception != EXCP_RFI) {
3114 gen_op_update_tb(ctx.tb_offset);
3115 gen_op_update_decr(ctx.decr_offset);
3116 gen_op_process_exceptions((uint32_t)ctx.nip);
3117 }
3118#if 1
79aceca5
FB		 3119 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3120 * do bad business and then qemu crashes !
3121 */
3122 gen_op_set_T0(0);
9a64fbe4 3123#endif
79aceca5
FB		 3124 /* Generate the return instruction */
3125 gen_op_exit_tb();
3126 *gen_opc_ptr = INDEX_op_end;
9a64fbe4
FB		 3127 if (search_pc) {
3128 j = gen_opc_ptr - gen_opc_buf;
3129 lj++;
3130 while (lj <= j)
3131 gen_opc_instr_start[lj++] = 0;
79aceca5 3132 tb->size = 0;
985a19d6 3133#if 0
9a64fbe4
FB		 3134 if (loglevel > 0) {
3135 page_dump(logfile);
3136 }
985a19d6 3137#endif
9a64fbe4
FB		 3138 } else {
3139 tb->size = (uint32_t)ctx.nip - pc_start;
3140 }
a541f297 3141 env->access_type = ACCESS_INT;
79aceca5
FB		 3142#ifdef DEBUG_DISAS
3143 if (loglevel > 0) {
9a64fbe4
FB		 3144 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
3145 cpu_ppc_dump_state(env, logfile, 0);
79aceca5
FB		 3146 fprintf(logfile, "IN: %s\n", lookup_symbol((void *)pc_start));
3147 disas(logfile, (void *)pc_start, (uint32_t)ctx.nip - pc_start, 0, 0);
3148 fprintf(logfile, "\n");
3149
3150 fprintf(logfile, "OP:\n");
3151 dump_ops(gen_opc_buf, gen_opparam_buf);
3152 fprintf(logfile, "\n");
3153 }
3154#endif
3155
3156 return 0;
3157}
3158
9a64fbe4 3159int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3160{
3161 return gen_intermediate_code_internal(env, tb, 0);
3162}
3163
9a64fbe4 3164int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3165{
3166 return gen_intermediate_code_internal(env, tb, 1);
3167}
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