]>
Commit | Line | Data |
---|---|---|
79aceca5 | 1 | /* |
3fc6c082 | 2 | * PowerPC emulation for qemu: main translation routines. |
5fafdf24 | 3 | * |
76a66253 | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
90dc8812 | 5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
79aceca5 FB |
6 | * |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
79aceca5 | 19 | */ |
c6a1c22b | 20 | |
0d75590d | 21 | #include "qemu/osdep.h" |
79aceca5 | 22 | #include "cpu.h" |
76cad711 | 23 | #include "disas/disas.h" |
63c91552 | 24 | #include "exec/exec-all.h" |
57fec1fe | 25 | #include "tcg-op.h" |
1de7afc9 | 26 | #include "qemu/host-utils.h" |
f08b6170 | 27 | #include "exec/cpu_ldst.h" |
79aceca5 | 28 | |
2ef6175a RH |
29 | #include "exec/helper-proto.h" |
30 | #include "exec/helper-gen.h" | |
a7812ae4 | 31 | |
a7e30d84 | 32 | #include "trace-tcg.h" |
508127e2 | 33 | #include "exec/log.h" |
a7e30d84 LV |
34 | |
35 | ||
8cbcb4fa AJ |
36 | #define CPU_SINGLE_STEP 0x1 |
37 | #define CPU_BRANCH_STEP 0x2 | |
38 | #define GDBSTUB_SINGLE_STEP 0x4 | |
39 | ||
a750fc0b | 40 | /* Include definitions for instructions classes and implementations flags */ |
9fddaa0c | 41 | //#define PPC_DEBUG_DISAS |
76a66253 | 42 | //#define DO_PPC_STATISTICS |
79aceca5 | 43 | |
d12d51d5 | 44 | #ifdef PPC_DEBUG_DISAS |
93fcfe39 | 45 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
d12d51d5 AL |
46 | #else |
47 | # define LOG_DISAS(...) do { } while (0) | |
48 | #endif | |
a750fc0b JM |
49 | /*****************************************************************************/ |
50 | /* Code translation helpers */ | |
c53be334 | 51 | |
f78fb44e | 52 | /* global register indexes */ |
1bcea73e | 53 | static TCGv_env cpu_env; |
1d542695 | 54 | static char cpu_reg_names[10*3 + 22*4 /* GPR */ |
1d542695 | 55 | + 10*4 + 22*5 /* SPE GPRh */ |
a5e26afa | 56 | + 10*4 + 22*5 /* FPR */ |
47e4661c | 57 | + 2*(10*6 + 22*7) /* AVRh, AVRl */ |
472b24ce | 58 | + 10*5 + 22*6 /* VSR */ |
47e4661c | 59 | + 8*5 /* CRF */]; |
f78fb44e | 60 | static TCGv cpu_gpr[32]; |
f78fb44e | 61 | static TCGv cpu_gprh[32]; |
a7812ae4 PB |
62 | static TCGv_i64 cpu_fpr[32]; |
63 | static TCGv_i64 cpu_avrh[32], cpu_avrl[32]; | |
472b24ce | 64 | static TCGv_i64 cpu_vsr[32]; |
a7812ae4 | 65 | static TCGv_i32 cpu_crf[8]; |
bd568f18 | 66 | static TCGv cpu_nip; |
6527f6ea | 67 | static TCGv cpu_msr; |
cfdcd37a AJ |
68 | static TCGv cpu_ctr; |
69 | static TCGv cpu_lr; | |
697ab892 DG |
70 | #if defined(TARGET_PPC64) |
71 | static TCGv cpu_cfar; | |
72 | #endif | |
da91a00f | 73 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; |
cf360a32 | 74 | static TCGv cpu_reserve; |
30304420 | 75 | static TCGv cpu_fpscr; |
a7859e89 | 76 | static TCGv_i32 cpu_access_type; |
f78fb44e | 77 | |
022c62cb | 78 | #include "exec/gen-icount.h" |
2e70f6ef PB |
79 | |
80 | void ppc_translate_init(void) | |
81 | { | |
f78fb44e AJ |
82 | int i; |
83 | char* p; | |
2dc766da | 84 | size_t cpu_reg_names_size; |
b2437bf2 | 85 | static int done_init = 0; |
f78fb44e | 86 | |
2e70f6ef PB |
87 | if (done_init) |
88 | return; | |
f78fb44e | 89 | |
a7812ae4 | 90 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
7c255043 | 91 | tcg_ctx.tcg_env = cpu_env; |
a7812ae4 | 92 | |
f78fb44e | 93 | p = cpu_reg_names; |
2dc766da | 94 | cpu_reg_names_size = sizeof(cpu_reg_names); |
47e4661c AJ |
95 | |
96 | for (i = 0; i < 8; i++) { | |
2dc766da | 97 | snprintf(p, cpu_reg_names_size, "crf%d", i); |
e1ccc054 | 98 | cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 99 | offsetof(CPUPPCState, crf[i]), p); |
47e4661c | 100 | p += 5; |
2dc766da | 101 | cpu_reg_names_size -= 5; |
47e4661c AJ |
102 | } |
103 | ||
f78fb44e | 104 | for (i = 0; i < 32; i++) { |
2dc766da | 105 | snprintf(p, cpu_reg_names_size, "r%d", i); |
e1ccc054 | 106 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, |
1328c2bf | 107 | offsetof(CPUPPCState, gpr[i]), p); |
f78fb44e | 108 | p += (i < 10) ? 3 : 4; |
2dc766da | 109 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
2dc766da | 110 | snprintf(p, cpu_reg_names_size, "r%dH", i); |
e1ccc054 | 111 | cpu_gprh[i] = tcg_global_mem_new(cpu_env, |
13b6a455 | 112 | offsetof(CPUPPCState, gprh[i]), p); |
f78fb44e | 113 | p += (i < 10) ? 4 : 5; |
2dc766da | 114 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
1d542695 | 115 | |
2dc766da | 116 | snprintf(p, cpu_reg_names_size, "fp%d", i); |
e1ccc054 | 117 | cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 118 | offsetof(CPUPPCState, fpr[i]), p); |
ec1ac72d | 119 | p += (i < 10) ? 4 : 5; |
2dc766da | 120 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
a5e26afa | 121 | |
2dc766da | 122 | snprintf(p, cpu_reg_names_size, "avr%dH", i); |
e2542fe2 | 123 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 124 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 125 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 126 | #else |
e1ccc054 | 127 | cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 128 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 129 | #endif |
1d542695 | 130 | p += (i < 10) ? 6 : 7; |
2dc766da | 131 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
ec1ac72d | 132 | |
2dc766da | 133 | snprintf(p, cpu_reg_names_size, "avr%dL", i); |
e2542fe2 | 134 | #ifdef HOST_WORDS_BIGENDIAN |
e1ccc054 | 135 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 136 | offsetof(CPUPPCState, avr[i].u64[1]), p); |
fe1e5c53 | 137 | #else |
e1ccc054 | 138 | cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env, |
1328c2bf | 139 | offsetof(CPUPPCState, avr[i].u64[0]), p); |
fe1e5c53 | 140 | #endif |
1d542695 | 141 | p += (i < 10) ? 6 : 7; |
2dc766da | 142 | cpu_reg_names_size -= (i < 10) ? 6 : 7; |
472b24ce | 143 | snprintf(p, cpu_reg_names_size, "vsr%d", i); |
e1ccc054 RH |
144 | cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env, |
145 | offsetof(CPUPPCState, vsr[i]), p); | |
472b24ce TM |
146 | p += (i < 10) ? 5 : 6; |
147 | cpu_reg_names_size -= (i < 10) ? 5 : 6; | |
f78fb44e | 148 | } |
f10dc08e | 149 | |
e1ccc054 | 150 | cpu_nip = tcg_global_mem_new(cpu_env, |
1328c2bf | 151 | offsetof(CPUPPCState, nip), "nip"); |
bd568f18 | 152 | |
e1ccc054 | 153 | cpu_msr = tcg_global_mem_new(cpu_env, |
1328c2bf | 154 | offsetof(CPUPPCState, msr), "msr"); |
6527f6ea | 155 | |
e1ccc054 | 156 | cpu_ctr = tcg_global_mem_new(cpu_env, |
1328c2bf | 157 | offsetof(CPUPPCState, ctr), "ctr"); |
cfdcd37a | 158 | |
e1ccc054 | 159 | cpu_lr = tcg_global_mem_new(cpu_env, |
1328c2bf | 160 | offsetof(CPUPPCState, lr), "lr"); |
cfdcd37a | 161 | |
697ab892 | 162 | #if defined(TARGET_PPC64) |
e1ccc054 | 163 | cpu_cfar = tcg_global_mem_new(cpu_env, |
1328c2bf | 164 | offsetof(CPUPPCState, cfar), "cfar"); |
697ab892 DG |
165 | #endif |
166 | ||
e1ccc054 | 167 | cpu_xer = tcg_global_mem_new(cpu_env, |
1328c2bf | 168 | offsetof(CPUPPCState, xer), "xer"); |
e1ccc054 | 169 | cpu_so = tcg_global_mem_new(cpu_env, |
da91a00f | 170 | offsetof(CPUPPCState, so), "SO"); |
e1ccc054 | 171 | cpu_ov = tcg_global_mem_new(cpu_env, |
da91a00f | 172 | offsetof(CPUPPCState, ov), "OV"); |
e1ccc054 | 173 | cpu_ca = tcg_global_mem_new(cpu_env, |
da91a00f | 174 | offsetof(CPUPPCState, ca), "CA"); |
3d7b417e | 175 | |
e1ccc054 | 176 | cpu_reserve = tcg_global_mem_new(cpu_env, |
1328c2bf | 177 | offsetof(CPUPPCState, reserve_addr), |
18b21a2f | 178 | "reserve_addr"); |
cf360a32 | 179 | |
e1ccc054 | 180 | cpu_fpscr = tcg_global_mem_new(cpu_env, |
30304420 | 181 | offsetof(CPUPPCState, fpscr), "fpscr"); |
e1571908 | 182 | |
e1ccc054 | 183 | cpu_access_type = tcg_global_mem_new_i32(cpu_env, |
1328c2bf | 184 | offsetof(CPUPPCState, access_type), "access_type"); |
a7859e89 | 185 | |
2e70f6ef PB |
186 | done_init = 1; |
187 | } | |
188 | ||
79aceca5 | 189 | /* internal defines */ |
69b058c8 | 190 | struct DisasContext { |
79aceca5 | 191 | struct TranslationBlock *tb; |
0fa85d43 | 192 | target_ulong nip; |
79aceca5 | 193 | uint32_t opcode; |
9a64fbe4 | 194 | uint32_t exception; |
3cc62370 | 195 | /* Routine used to access memory */ |
5c3ae929 | 196 | bool pr, hv, dr, le_mode; |
c5a8d8f3 | 197 | bool lazy_tlb_flush; |
5f2a6254 | 198 | bool need_access_type; |
3cc62370 | 199 | int mem_idx; |
76db3ba4 | 200 | int access_type; |
3cc62370 | 201 | /* Translation flags */ |
e22c357b | 202 | TCGMemOp default_tcg_memop_mask; |
d9bce9d9 | 203 | #if defined(TARGET_PPC64) |
5c3ae929 BH |
204 | bool sf_mode; |
205 | bool has_cfar; | |
9a64fbe4 | 206 | #endif |
5c3ae929 BH |
207 | bool fpu_enabled; |
208 | bool altivec_enabled; | |
209 | bool vsx_enabled; | |
210 | bool spe_enabled; | |
211 | bool tm_enabled; | |
c227f099 | 212 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
ea4e754f | 213 | int singlestep_enabled; |
7d08d856 AJ |
214 | uint64_t insns_flags; |
215 | uint64_t insns_flags2; | |
69b058c8 | 216 | }; |
79aceca5 | 217 | |
e22c357b DK |
218 | /* Return true iff byteswap is needed in a scalar memop */ |
219 | static inline bool need_byteswap(const DisasContext *ctx) | |
220 | { | |
221 | #if defined(TARGET_WORDS_BIGENDIAN) | |
222 | return ctx->le_mode; | |
223 | #else | |
224 | return !ctx->le_mode; | |
225 | #endif | |
226 | } | |
227 | ||
79482e5a RH |
228 | /* True when active word size < size of target_long. */ |
229 | #ifdef TARGET_PPC64 | |
230 | # define NARROW_MODE(C) (!(C)->sf_mode) | |
231 | #else | |
232 | # define NARROW_MODE(C) 0 | |
233 | #endif | |
234 | ||
c227f099 | 235 | struct opc_handler_t { |
70560da7 FC |
236 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
237 | uint32_t inval1; | |
238 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ | |
239 | uint32_t inval2; | |
9a64fbe4 | 240 | /* instruction type */ |
0487d6a8 | 241 | uint64_t type; |
a5858d7a AG |
242 | /* extended instruction type */ |
243 | uint64_t type2; | |
79aceca5 FB |
244 | /* handler */ |
245 | void (*handler)(DisasContext *ctx); | |
a750fc0b | 246 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
b55266b5 | 247 | const char *oname; |
a750fc0b JM |
248 | #endif |
249 | #if defined(DO_PPC_STATISTICS) | |
76a66253 JM |
250 | uint64_t count; |
251 | #endif | |
3fc6c082 | 252 | }; |
79aceca5 | 253 | |
636aa200 | 254 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
a7859e89 | 255 | { |
5f2a6254 | 256 | if (ctx->need_access_type && ctx->access_type != access_type) { |
76db3ba4 AJ |
257 | tcg_gen_movi_i32(cpu_access_type, access_type); |
258 | ctx->access_type = access_type; | |
259 | } | |
a7859e89 AJ |
260 | } |
261 | ||
636aa200 | 262 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
d9bce9d9 | 263 | { |
e0c8f9ce RH |
264 | if (NARROW_MODE(ctx)) { |
265 | nip = (uint32_t)nip; | |
266 | } | |
267 | tcg_gen_movi_tl(cpu_nip, nip); | |
d9bce9d9 JM |
268 | } |
269 | ||
b9971cc5 | 270 | static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
e06fcd75 AJ |
271 | { |
272 | TCGv_i32 t0, t1; | |
bd6fefe7 BH |
273 | |
274 | /* These are all synchronous exceptions, we set the PC back to | |
275 | * the faulting instruction | |
276 | */ | |
e06fcd75 | 277 | if (ctx->exception == POWERPC_EXCP_NONE) { |
bd6fefe7 | 278 | gen_update_nip(ctx, ctx->nip - 4); |
e06fcd75 AJ |
279 | } |
280 | t0 = tcg_const_i32(excp); | |
281 | t1 = tcg_const_i32(error); | |
e5f17ac6 | 282 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
e06fcd75 AJ |
283 | tcg_temp_free_i32(t0); |
284 | tcg_temp_free_i32(t1); | |
285 | ctx->exception = (excp); | |
286 | } | |
e1833e1f | 287 | |
b9971cc5 | 288 | static void gen_exception(DisasContext *ctx, uint32_t excp) |
e06fcd75 AJ |
289 | { |
290 | TCGv_i32 t0; | |
bd6fefe7 BH |
291 | |
292 | /* These are all synchronous exceptions, we set the PC back to | |
293 | * the faulting instruction | |
294 | */ | |
e06fcd75 | 295 | if (ctx->exception == POWERPC_EXCP_NONE) { |
bd6fefe7 | 296 | gen_update_nip(ctx, ctx->nip - 4); |
e06fcd75 AJ |
297 | } |
298 | t0 = tcg_const_i32(excp); | |
e5f17ac6 | 299 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
300 | tcg_temp_free_i32(t0); |
301 | ctx->exception = (excp); | |
302 | } | |
e1833e1f | 303 | |
bd6fefe7 BH |
304 | static void gen_exception_nip(DisasContext *ctx, uint32_t excp, |
305 | target_ulong nip) | |
306 | { | |
307 | TCGv_i32 t0; | |
308 | ||
309 | gen_update_nip(ctx, nip); | |
310 | t0 = tcg_const_i32(excp); | |
311 | gen_helper_raise_exception(cpu_env, t0); | |
312 | tcg_temp_free_i32(t0); | |
313 | ctx->exception = (excp); | |
314 | } | |
315 | ||
b9971cc5 | 316 | static void gen_debug_exception(DisasContext *ctx) |
e06fcd75 AJ |
317 | { |
318 | TCGv_i32 t0; | |
5518f3a6 | 319 | |
bd6fefe7 BH |
320 | /* These are all synchronous exceptions, we set the PC back to |
321 | * the faulting instruction | |
322 | */ | |
ee2b3994 SB |
323 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
324 | (ctx->exception != POWERPC_EXCP_SYNC)) { | |
bd6fefe7 | 325 | gen_update_nip(ctx, ctx->nip - 4); |
ee2b3994 | 326 | } |
e06fcd75 | 327 | t0 = tcg_const_i32(EXCP_DEBUG); |
e5f17ac6 | 328 | gen_helper_raise_exception(cpu_env, t0); |
e06fcd75 AJ |
329 | tcg_temp_free_i32(t0); |
330 | } | |
9a64fbe4 | 331 | |
636aa200 | 332 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
e06fcd75 | 333 | { |
9b2fadda BH |
334 | /* Will be converted to program check if needed */ |
335 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); | |
336 | } | |
337 | ||
338 | static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) | |
339 | { | |
340 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); | |
341 | } | |
342 | ||
343 | static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) | |
344 | { | |
345 | /* Will be converted to program check if needed */ | |
346 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); | |
e06fcd75 | 347 | } |
a9d9eb8f | 348 | |
f24e5695 | 349 | /* Stop translation */ |
636aa200 | 350 | static inline void gen_stop_exception(DisasContext *ctx) |
3fc6c082 | 351 | { |
d9bce9d9 | 352 | gen_update_nip(ctx, ctx->nip); |
e1833e1f | 353 | ctx->exception = POWERPC_EXCP_STOP; |
3fc6c082 FB |
354 | } |
355 | ||
466976d9 | 356 | #ifndef CONFIG_USER_ONLY |
f24e5695 | 357 | /* No need to update nip here, as execution flow will change */ |
636aa200 | 358 | static inline void gen_sync_exception(DisasContext *ctx) |
2be0071f | 359 | { |
e1833e1f | 360 | ctx->exception = POWERPC_EXCP_SYNC; |
2be0071f | 361 | } |
466976d9 | 362 | #endif |
2be0071f | 363 | |
79aceca5 | 364 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
365 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
366 | ||
367 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ | |
368 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) | |
79aceca5 | 369 | |
c7697e1f | 370 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
a5858d7a AG |
371 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
372 | ||
373 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ | |
374 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) | |
c7697e1f | 375 | |
323ad19b ND |
376 | #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ |
377 | GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) | |
378 | ||
c227f099 | 379 | typedef struct opcode_t { |
323ad19b | 380 | unsigned char opc1, opc2, opc3, opc4; |
1235fc06 | 381 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
323ad19b | 382 | unsigned char pad[4]; |
18fba28c | 383 | #endif |
c227f099 | 384 | opc_handler_t handler; |
b55266b5 | 385 | const char *oname; |
c227f099 | 386 | } opcode_t; |
79aceca5 | 387 | |
9b2fadda BH |
388 | /* Helpers for priv. check */ |
389 | #define GEN_PRIV \ | |
390 | do { \ | |
391 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ | |
392 | } while (0) | |
393 | ||
394 | #if defined(CONFIG_USER_ONLY) | |
395 | #define CHK_HV GEN_PRIV | |
396 | #define CHK_SV GEN_PRIV | |
b7815375 | 397 | #define CHK_HVRM GEN_PRIV |
9b2fadda BH |
398 | #else |
399 | #define CHK_HV \ | |
400 | do { \ | |
401 | if (unlikely(ctx->pr || !ctx->hv)) { \ | |
402 | GEN_PRIV; \ | |
403 | } \ | |
404 | } while (0) | |
405 | #define CHK_SV \ | |
406 | do { \ | |
407 | if (unlikely(ctx->pr)) { \ | |
408 | GEN_PRIV; \ | |
409 | } \ | |
410 | } while (0) | |
b7815375 BH |
411 | #define CHK_HVRM \ |
412 | do { \ | |
413 | if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ | |
414 | GEN_PRIV; \ | |
415 | } \ | |
416 | } while (0) | |
9b2fadda BH |
417 | #endif |
418 | ||
419 | #define CHK_NONE | |
420 | ||
421 | ||
a750fc0b | 422 | /*****************************************************************************/ |
79aceca5 FB |
423 | /*** Instruction decoding ***/ |
424 | #define EXTRACT_HELPER(name, shift, nb) \ | |
636aa200 | 425 | static inline uint32_t name(uint32_t opcode) \ |
79aceca5 FB |
426 | { \ |
427 | return (opcode >> (shift)) & ((1 << (nb)) - 1); \ | |
428 | } | |
429 | ||
430 | #define EXTRACT_SHELPER(name, shift, nb) \ | |
636aa200 | 431 | static inline int32_t name(uint32_t opcode) \ |
79aceca5 | 432 | { \ |
18fba28c | 433 | return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \ |
79aceca5 FB |
434 | } |
435 | ||
f9fc6d81 TM |
436 | #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \ |
437 | static inline uint32_t name(uint32_t opcode) \ | |
438 | { \ | |
439 | return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \ | |
440 | ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \ | |
441 | } | |
c5b2b9ce ND |
442 | |
443 | #define EXTRACT_HELPER_DXFORM(name, \ | |
444 | d0_bits, shift_op_d0, shift_d0, \ | |
445 | d1_bits, shift_op_d1, shift_d1, \ | |
446 | d2_bits, shift_op_d2, shift_d2) \ | |
447 | static inline int16_t name(uint32_t opcode) \ | |
448 | { \ | |
449 | return \ | |
450 | (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \ | |
451 | (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \ | |
452 | (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \ | |
453 | } | |
454 | ||
455 | ||
79aceca5 FB |
456 | /* Opcode part 1 */ |
457 | EXTRACT_HELPER(opc1, 26, 6); | |
458 | /* Opcode part 2 */ | |
459 | EXTRACT_HELPER(opc2, 1, 5); | |
460 | /* Opcode part 3 */ | |
461 | EXTRACT_HELPER(opc3, 6, 5); | |
323ad19b ND |
462 | /* Opcode part 4 */ |
463 | EXTRACT_HELPER(opc4, 16, 5); | |
79aceca5 FB |
464 | /* Update Cr0 flags */ |
465 | EXTRACT_HELPER(Rc, 0, 1); | |
a737d3eb TM |
466 | /* Update Cr6 flags (Altivec) */ |
467 | EXTRACT_HELPER(Rc21, 10, 1); | |
79aceca5 FB |
468 | /* Destination */ |
469 | EXTRACT_HELPER(rD, 21, 5); | |
470 | /* Source */ | |
471 | EXTRACT_HELPER(rS, 21, 5); | |
472 | /* First operand */ | |
473 | EXTRACT_HELPER(rA, 16, 5); | |
474 | /* Second operand */ | |
475 | EXTRACT_HELPER(rB, 11, 5); | |
476 | /* Third operand */ | |
477 | EXTRACT_HELPER(rC, 6, 5); | |
478 | /*** Get CRn ***/ | |
479 | EXTRACT_HELPER(crfD, 23, 3); | |
480 | EXTRACT_HELPER(crfS, 18, 3); | |
481 | EXTRACT_HELPER(crbD, 21, 5); | |
482 | EXTRACT_HELPER(crbA, 16, 5); | |
483 | EXTRACT_HELPER(crbB, 11, 5); | |
484 | /* SPR / TBL */ | |
3fc6c082 | 485 | EXTRACT_HELPER(_SPR, 11, 10); |
636aa200 | 486 | static inline uint32_t SPR(uint32_t opcode) |
3fc6c082 FB |
487 | { |
488 | uint32_t sprn = _SPR(opcode); | |
489 | ||
490 | return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); | |
491 | } | |
79aceca5 | 492 | /*** Get constants ***/ |
79aceca5 FB |
493 | /* 16 bits signed immediate value */ |
494 | EXTRACT_SHELPER(SIMM, 0, 16); | |
495 | /* 16 bits unsigned immediate value */ | |
496 | EXTRACT_HELPER(UIMM, 0, 16); | |
21d21583 AJ |
497 | /* 5 bits signed immediate value */ |
498 | EXTRACT_HELPER(SIMM5, 16, 5); | |
27a4edb3 AJ |
499 | /* 5 bits signed immediate value */ |
500 | EXTRACT_HELPER(UIMM5, 16, 5); | |
e7b1e06f RS |
501 | /* 4 bits unsigned immediate value */ |
502 | EXTRACT_HELPER(UIMM4, 16, 4); | |
79aceca5 FB |
503 | /* Bit count */ |
504 | EXTRACT_HELPER(NB, 11, 5); | |
505 | /* Shift count */ | |
506 | EXTRACT_HELPER(SH, 11, 5); | |
cd633b10 AJ |
507 | /* Vector shift count */ |
508 | EXTRACT_HELPER(VSH, 6, 4); | |
79aceca5 FB |
509 | /* Mask start */ |
510 | EXTRACT_HELPER(MB, 6, 5); | |
511 | /* Mask end */ | |
512 | EXTRACT_HELPER(ME, 1, 5); | |
fb0eaffc FB |
513 | /* Trap operand */ |
514 | EXTRACT_HELPER(TO, 21, 5); | |
79aceca5 FB |
515 | |
516 | EXTRACT_HELPER(CRM, 12, 8); | |
466976d9 PM |
517 | |
518 | #ifndef CONFIG_USER_ONLY | |
79aceca5 | 519 | EXTRACT_HELPER(SR, 16, 4); |
466976d9 | 520 | #endif |
7d08d856 AJ |
521 | |
522 | /* mtfsf/mtfsfi */ | |
779f6590 | 523 | EXTRACT_HELPER(FPBF, 23, 3); |
e4bb997e | 524 | EXTRACT_HELPER(FPIMM, 12, 4); |
779f6590 | 525 | EXTRACT_HELPER(FPL, 25, 1); |
7d08d856 AJ |
526 | EXTRACT_HELPER(FPFLM, 17, 8); |
527 | EXTRACT_HELPER(FPW, 16, 1); | |
fb0eaffc | 528 | |
c5b2b9ce ND |
529 | /* addpcis */ |
530 | EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0) | |
531 | ||
79aceca5 | 532 | /*** Jump target decoding ***/ |
79aceca5 | 533 | /* Immediate address */ |
636aa200 | 534 | static inline target_ulong LI(uint32_t opcode) |
79aceca5 FB |
535 | { |
536 | return (opcode >> 0) & 0x03FFFFFC; | |
537 | } | |
538 | ||
636aa200 | 539 | static inline uint32_t BD(uint32_t opcode) |
79aceca5 FB |
540 | { |
541 | return (opcode >> 0) & 0xFFFC; | |
542 | } | |
543 | ||
544 | EXTRACT_HELPER(BO, 21, 5); | |
545 | EXTRACT_HELPER(BI, 16, 5); | |
546 | /* Absolute/relative address */ | |
547 | EXTRACT_HELPER(AA, 1, 1); | |
548 | /* Link */ | |
549 | EXTRACT_HELPER(LK, 0, 1); | |
550 | ||
f0b01f02 TM |
551 | /* DFP Z22-form */ |
552 | EXTRACT_HELPER(DCM, 10, 6) | |
553 | ||
554 | /* DFP Z23-form */ | |
555 | EXTRACT_HELPER(RMC, 9, 2) | |
556 | ||
79aceca5 | 557 | /* Create a mask between <start> and <end> bits */ |
636aa200 | 558 | static inline target_ulong MASK(uint32_t start, uint32_t end) |
79aceca5 | 559 | { |
76a66253 | 560 | target_ulong ret; |
79aceca5 | 561 | |
76a66253 JM |
562 | #if defined(TARGET_PPC64) |
563 | if (likely(start == 0)) { | |
6f2d8978 | 564 | ret = UINT64_MAX << (63 - end); |
76a66253 | 565 | } else if (likely(end == 63)) { |
6f2d8978 | 566 | ret = UINT64_MAX >> start; |
76a66253 JM |
567 | } |
568 | #else | |
569 | if (likely(start == 0)) { | |
6f2d8978 | 570 | ret = UINT32_MAX << (31 - end); |
76a66253 | 571 | } else if (likely(end == 31)) { |
6f2d8978 | 572 | ret = UINT32_MAX >> start; |
76a66253 JM |
573 | } |
574 | #endif | |
575 | else { | |
576 | ret = (((target_ulong)(-1ULL)) >> (start)) ^ | |
577 | (((target_ulong)(-1ULL) >> (end)) >> 1); | |
578 | if (unlikely(start > end)) | |
579 | return ~ret; | |
580 | } | |
79aceca5 FB |
581 | |
582 | return ret; | |
583 | } | |
584 | ||
f9fc6d81 TM |
585 | EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5); |
586 | EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5); | |
587 | EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5); | |
588 | EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5); | |
551e3ef7 | 589 | EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5); |
f9fc6d81 | 590 | EXTRACT_HELPER(DM, 8, 2); |
76c15fe0 | 591 | EXTRACT_HELPER(UIM, 16, 2); |
acc42968 | 592 | EXTRACT_HELPER(SHW, 8, 2); |
f0b01f02 | 593 | EXTRACT_HELPER(SP, 19, 2); |
f1132835 ND |
594 | EXTRACT_HELPER(IMM8, 11, 8); |
595 | ||
a750fc0b | 596 | /*****************************************************************************/ |
a750fc0b | 597 | /* PowerPC instructions table */ |
933dc6eb | 598 | |
76a66253 | 599 | #if defined(DO_PPC_STATISTICS) |
a5858d7a | 600 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 601 | { \ |
79aceca5 FB |
602 | .opc1 = op1, \ |
603 | .opc2 = op2, \ | |
604 | .opc3 = op3, \ | |
323ad19b | 605 | .opc4 = 0xff, \ |
79aceca5 | 606 | .handler = { \ |
70560da7 FC |
607 | .inval1 = invl, \ |
608 | .type = _typ, \ | |
609 | .type2 = _typ2, \ | |
610 | .handler = &gen_##name, \ | |
611 | .oname = stringify(name), \ | |
612 | }, \ | |
613 | .oname = stringify(name), \ | |
614 | } | |
615 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
616 | { \ | |
617 | .opc1 = op1, \ | |
618 | .opc2 = op2, \ | |
619 | .opc3 = op3, \ | |
323ad19b | 620 | .opc4 = 0xff, \ |
70560da7 FC |
621 | .handler = { \ |
622 | .inval1 = invl1, \ | |
623 | .inval2 = invl2, \ | |
9a64fbe4 | 624 | .type = _typ, \ |
a5858d7a | 625 | .type2 = _typ2, \ |
79aceca5 | 626 | .handler = &gen_##name, \ |
76a66253 | 627 | .oname = stringify(name), \ |
79aceca5 | 628 | }, \ |
3fc6c082 | 629 | .oname = stringify(name), \ |
79aceca5 | 630 | } |
a5858d7a | 631 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 632 | { \ |
c7697e1f JM |
633 | .opc1 = op1, \ |
634 | .opc2 = op2, \ | |
635 | .opc3 = op3, \ | |
323ad19b | 636 | .opc4 = 0xff, \ |
c7697e1f | 637 | .handler = { \ |
70560da7 | 638 | .inval1 = invl, \ |
c7697e1f | 639 | .type = _typ, \ |
a5858d7a | 640 | .type2 = _typ2, \ |
c7697e1f JM |
641 | .handler = &gen_##name, \ |
642 | .oname = onam, \ | |
643 | }, \ | |
644 | .oname = onam, \ | |
645 | } | |
323ad19b ND |
646 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
647 | { \ | |
648 | .opc1 = op1, \ | |
649 | .opc2 = op2, \ | |
650 | .opc3 = op3, \ | |
651 | .opc4 = op4, \ | |
652 | .handler = { \ | |
653 | .inval1 = invl, \ | |
654 | .type = _typ, \ | |
655 | .type2 = _typ2, \ | |
656 | .handler = &gen_##name, \ | |
657 | .oname = stringify(name), \ | |
658 | }, \ | |
659 | .oname = stringify(name), \ | |
660 | } | |
76a66253 | 661 | #else |
a5858d7a | 662 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 | 663 | { \ |
c7697e1f JM |
664 | .opc1 = op1, \ |
665 | .opc2 = op2, \ | |
666 | .opc3 = op3, \ | |
323ad19b | 667 | .opc4 = 0xff, \ |
c7697e1f | 668 | .handler = { \ |
70560da7 FC |
669 | .inval1 = invl, \ |
670 | .type = _typ, \ | |
671 | .type2 = _typ2, \ | |
672 | .handler = &gen_##name, \ | |
673 | }, \ | |
674 | .oname = stringify(name), \ | |
675 | } | |
676 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ | |
677 | { \ | |
678 | .opc1 = op1, \ | |
679 | .opc2 = op2, \ | |
680 | .opc3 = op3, \ | |
323ad19b | 681 | .opc4 = 0xff, \ |
70560da7 FC |
682 | .handler = { \ |
683 | .inval1 = invl1, \ | |
684 | .inval2 = invl2, \ | |
c7697e1f | 685 | .type = _typ, \ |
a5858d7a | 686 | .type2 = _typ2, \ |
c7697e1f | 687 | .handler = &gen_##name, \ |
5c55ff99 BS |
688 | }, \ |
689 | .oname = stringify(name), \ | |
690 | } | |
a5858d7a | 691 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
5c55ff99 BS |
692 | { \ |
693 | .opc1 = op1, \ | |
694 | .opc2 = op2, \ | |
695 | .opc3 = op3, \ | |
323ad19b | 696 | .opc4 = 0xff, \ |
5c55ff99 | 697 | .handler = { \ |
70560da7 | 698 | .inval1 = invl, \ |
5c55ff99 | 699 | .type = _typ, \ |
a5858d7a | 700 | .type2 = _typ2, \ |
5c55ff99 BS |
701 | .handler = &gen_##name, \ |
702 | }, \ | |
703 | .oname = onam, \ | |
704 | } | |
323ad19b ND |
705 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
706 | { \ | |
707 | .opc1 = op1, \ | |
708 | .opc2 = op2, \ | |
709 | .opc3 = op3, \ | |
710 | .opc4 = op4, \ | |
711 | .handler = { \ | |
712 | .inval1 = invl, \ | |
713 | .type = _typ, \ | |
714 | .type2 = _typ2, \ | |
715 | .handler = &gen_##name, \ | |
716 | }, \ | |
717 | .oname = stringify(name), \ | |
718 | } | |
5c55ff99 | 719 | #endif |
2e610050 | 720 | |
5c55ff99 | 721 | /* SPR load/store helpers */ |
636aa200 | 722 | static inline void gen_load_spr(TCGv t, int reg) |
5c55ff99 | 723 | { |
1328c2bf | 724 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 725 | } |
2e610050 | 726 | |
636aa200 | 727 | static inline void gen_store_spr(int reg, TCGv t) |
5c55ff99 | 728 | { |
1328c2bf | 729 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
5c55ff99 | 730 | } |
2e610050 | 731 | |
54623277 | 732 | /* Invalid instruction */ |
99e300ef | 733 | static void gen_invalid(DisasContext *ctx) |
9a64fbe4 | 734 | { |
e06fcd75 | 735 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
9a64fbe4 FB |
736 | } |
737 | ||
c227f099 | 738 | static opc_handler_t invalid_handler = { |
70560da7 FC |
739 | .inval1 = 0xFFFFFFFF, |
740 | .inval2 = 0xFFFFFFFF, | |
9a64fbe4 | 741 | .type = PPC_NONE, |
a5858d7a | 742 | .type2 = PPC_NONE, |
79aceca5 FB |
743 | .handler = gen_invalid, |
744 | }; | |
745 | ||
e1571908 AJ |
746 | /*** Integer comparison ***/ |
747 | ||
636aa200 | 748 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 749 | { |
2fdcb629 RH |
750 | TCGv t0 = tcg_temp_new(); |
751 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
e1571908 | 752 | |
da91a00f | 753 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
e1571908 | 754 | |
2fdcb629 RH |
755 | tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1); |
756 | tcg_gen_trunc_tl_i32(t1, t0); | |
757 | tcg_gen_shli_i32(t1, t1, CRF_LT); | |
758 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
759 | ||
760 | tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1); | |
761 | tcg_gen_trunc_tl_i32(t1, t0); | |
762 | tcg_gen_shli_i32(t1, t1, CRF_GT); | |
763 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
764 | ||
765 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1); | |
766 | tcg_gen_trunc_tl_i32(t1, t0); | |
767 | tcg_gen_shli_i32(t1, t1, CRF_EQ); | |
768 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1); | |
769 | ||
770 | tcg_temp_free(t0); | |
771 | tcg_temp_free_i32(t1); | |
e1571908 AJ |
772 | } |
773 | ||
636aa200 | 774 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 775 | { |
2fdcb629 | 776 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
777 | gen_op_cmp(arg0, t0, s, crf); |
778 | tcg_temp_free(t0); | |
e1571908 AJ |
779 | } |
780 | ||
636aa200 | 781 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
e1571908 | 782 | { |
ea363694 | 783 | TCGv t0, t1; |
2fdcb629 RH |
784 | t0 = tcg_temp_new(); |
785 | t1 = tcg_temp_new(); | |
e1571908 | 786 | if (s) { |
ea363694 AJ |
787 | tcg_gen_ext32s_tl(t0, arg0); |
788 | tcg_gen_ext32s_tl(t1, arg1); | |
e1571908 | 789 | } else { |
ea363694 AJ |
790 | tcg_gen_ext32u_tl(t0, arg0); |
791 | tcg_gen_ext32u_tl(t1, arg1); | |
e1571908 | 792 | } |
ea363694 AJ |
793 | gen_op_cmp(t0, t1, s, crf); |
794 | tcg_temp_free(t1); | |
795 | tcg_temp_free(t0); | |
e1571908 AJ |
796 | } |
797 | ||
636aa200 | 798 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
e1571908 | 799 | { |
2fdcb629 | 800 | TCGv t0 = tcg_const_tl(arg1); |
ea363694 AJ |
801 | gen_op_cmp32(arg0, t0, s, crf); |
802 | tcg_temp_free(t0); | |
e1571908 | 803 | } |
e1571908 | 804 | |
636aa200 | 805 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
e1571908 | 806 | { |
02765534 | 807 | if (NARROW_MODE(ctx)) { |
e1571908 | 808 | gen_op_cmpi32(reg, 0, 1, 0); |
02765534 | 809 | } else { |
e1571908 | 810 | gen_op_cmpi(reg, 0, 1, 0); |
02765534 | 811 | } |
e1571908 AJ |
812 | } |
813 | ||
814 | /* cmp */ | |
99e300ef | 815 | static void gen_cmp(DisasContext *ctx) |
e1571908 | 816 | { |
36f48d9c | 817 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
818 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
819 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
820 | } else { |
821 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
822 | 1, crfD(ctx->opcode)); | |
02765534 | 823 | } |
e1571908 AJ |
824 | } |
825 | ||
826 | /* cmpi */ | |
99e300ef | 827 | static void gen_cmpi(DisasContext *ctx) |
e1571908 | 828 | { |
36f48d9c | 829 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
830 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
831 | 1, crfD(ctx->opcode)); | |
36f48d9c AG |
832 | } else { |
833 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), | |
834 | 1, crfD(ctx->opcode)); | |
02765534 | 835 | } |
e1571908 AJ |
836 | } |
837 | ||
838 | /* cmpl */ | |
99e300ef | 839 | static void gen_cmpl(DisasContext *ctx) |
e1571908 | 840 | { |
36f48d9c | 841 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
842 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
843 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
844 | } else { |
845 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], | |
846 | 0, crfD(ctx->opcode)); | |
02765534 | 847 | } |
e1571908 AJ |
848 | } |
849 | ||
850 | /* cmpli */ | |
99e300ef | 851 | static void gen_cmpli(DisasContext *ctx) |
e1571908 | 852 | { |
36f48d9c | 853 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
e1571908 AJ |
854 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
855 | 0, crfD(ctx->opcode)); | |
36f48d9c AG |
856 | } else { |
857 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), | |
858 | 0, crfD(ctx->opcode)); | |
02765534 | 859 | } |
e1571908 AJ |
860 | } |
861 | ||
f2442ef9 ND |
862 | /* cmprb - range comparison: isupper, isaplha, islower*/ |
863 | static void gen_cmprb(DisasContext *ctx) | |
864 | { | |
865 | TCGv_i32 src1 = tcg_temp_new_i32(); | |
866 | TCGv_i32 src2 = tcg_temp_new_i32(); | |
867 | TCGv_i32 src2lo = tcg_temp_new_i32(); | |
868 | TCGv_i32 src2hi = tcg_temp_new_i32(); | |
869 | TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; | |
870 | ||
871 | tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); | |
872 | tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); | |
873 | ||
874 | tcg_gen_andi_i32(src1, src1, 0xFF); | |
875 | tcg_gen_ext8u_i32(src2lo, src2); | |
876 | tcg_gen_shri_i32(src2, src2, 8); | |
877 | tcg_gen_ext8u_i32(src2hi, src2); | |
878 | ||
879 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
880 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
881 | tcg_gen_and_i32(crf, src2lo, src2hi); | |
882 | ||
883 | if (ctx->opcode & 0x00200000) { | |
884 | tcg_gen_shri_i32(src2, src2, 8); | |
885 | tcg_gen_ext8u_i32(src2lo, src2); | |
886 | tcg_gen_shri_i32(src2, src2, 8); | |
887 | tcg_gen_ext8u_i32(src2hi, src2); | |
888 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); | |
889 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); | |
890 | tcg_gen_and_i32(src2lo, src2lo, src2hi); | |
891 | tcg_gen_or_i32(crf, crf, src2lo); | |
892 | } | |
893 | tcg_gen_shli_i32(crf, crf, CRF_GT); | |
894 | tcg_temp_free_i32(src1); | |
895 | tcg_temp_free_i32(src2); | |
896 | tcg_temp_free_i32(src2lo); | |
897 | tcg_temp_free_i32(src2hi); | |
898 | } | |
899 | ||
082ce330 ND |
900 | #if defined(TARGET_PPC64) |
901 | /* cmpeqb */ | |
902 | static void gen_cmpeqb(DisasContext *ctx) | |
903 | { | |
904 | gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
905 | cpu_gpr[rB(ctx->opcode)]); | |
906 | } | |
907 | #endif | |
908 | ||
e1571908 | 909 | /* isel (PowerPC 2.03 specification) */ |
99e300ef | 910 | static void gen_isel(DisasContext *ctx) |
e1571908 | 911 | { |
e1571908 | 912 | uint32_t bi = rC(ctx->opcode); |
24f9cd95 RH |
913 | uint32_t mask = 0x08 >> (bi & 0x03); |
914 | TCGv t0 = tcg_temp_new(); | |
915 | TCGv zr; | |
e1571908 | 916 | |
24f9cd95 RH |
917 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); |
918 | tcg_gen_andi_tl(t0, t0, mask); | |
919 | ||
920 | zr = tcg_const_tl(0); | |
921 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, | |
922 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, | |
923 | cpu_gpr[rB(ctx->opcode)]); | |
924 | tcg_temp_free(zr); | |
925 | tcg_temp_free(t0); | |
e1571908 AJ |
926 | } |
927 | ||
fcfda20f AJ |
928 | /* cmpb: PowerPC 2.05 specification */ |
929 | static void gen_cmpb(DisasContext *ctx) | |
930 | { | |
931 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], | |
932 | cpu_gpr[rB(ctx->opcode)]); | |
933 | } | |
934 | ||
79aceca5 | 935 | /*** Integer arithmetic ***/ |
79aceca5 | 936 | |
636aa200 BS |
937 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
938 | TCGv arg1, TCGv arg2, int sub) | |
74637406 | 939 | { |
ffe30937 | 940 | TCGv t0 = tcg_temp_new(); |
79aceca5 | 941 | |
8e7a6db9 | 942 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
74637406 | 943 | tcg_gen_xor_tl(t0, arg1, arg2); |
ffe30937 RH |
944 | if (sub) { |
945 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); | |
946 | } else { | |
947 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); | |
948 | } | |
949 | tcg_temp_free(t0); | |
02765534 | 950 | if (NARROW_MODE(ctx)) { |
ffe30937 RH |
951 | tcg_gen_ext32s_tl(cpu_ov, cpu_ov); |
952 | } | |
ffe30937 RH |
953 | tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1); |
954 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
79aceca5 FB |
955 | } |
956 | ||
74637406 | 957 | /* Common add function */ |
636aa200 | 958 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
959 | TCGv arg2, bool add_ca, bool compute_ca, |
960 | bool compute_ov, bool compute_rc0) | |
74637406 | 961 | { |
b5a73f8d | 962 | TCGv t0 = ret; |
d9bce9d9 | 963 | |
752d634e | 964 | if (compute_ca || compute_ov) { |
146de60d | 965 | t0 = tcg_temp_new(); |
74637406 | 966 | } |
79aceca5 | 967 | |
da91a00f | 968 | if (compute_ca) { |
79482e5a | 969 | if (NARROW_MODE(ctx)) { |
752d634e RH |
970 | /* Caution: a non-obvious corner case of the spec is that we |
971 | must produce the *entire* 64-bit addition, but produce the | |
972 | carry into bit 32. */ | |
79482e5a | 973 | TCGv t1 = tcg_temp_new(); |
752d634e RH |
974 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
975 | tcg_gen_add_tl(t0, arg1, arg2); | |
79482e5a RH |
976 | if (add_ca) { |
977 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
978 | } | |
752d634e RH |
979 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */ |
980 | tcg_temp_free(t1); | |
981 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
982 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
b5a73f8d | 983 | } else { |
79482e5a RH |
984 | TCGv zero = tcg_const_tl(0); |
985 | if (add_ca) { | |
986 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero); | |
987 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero); | |
988 | } else { | |
989 | tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero); | |
990 | } | |
991 | tcg_temp_free(zero); | |
b5a73f8d | 992 | } |
b5a73f8d RH |
993 | } else { |
994 | tcg_gen_add_tl(t0, arg1, arg2); | |
995 | if (add_ca) { | |
996 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
997 | } | |
da91a00f | 998 | } |
79aceca5 | 999 | |
74637406 AJ |
1000 | if (compute_ov) { |
1001 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); | |
1002 | } | |
b5a73f8d | 1003 | if (unlikely(compute_rc0)) { |
74637406 | 1004 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1005 | } |
74637406 | 1006 | |
a7812ae4 | 1007 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1008 | tcg_gen_mov_tl(ret, t0); |
1009 | tcg_temp_free(t0); | |
1010 | } | |
39dd32ee | 1011 | } |
74637406 AJ |
1012 | /* Add functions with two operands */ |
1013 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1014 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1015 | { \ |
1016 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1017 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1018 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1019 | } |
1020 | /* Add functions with one operand and one immediate */ | |
1021 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
1022 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1023 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1024 | { \ |
b5a73f8d | 1025 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1026 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1027 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1028 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1029 | tcg_temp_free(t0); \ |
1030 | } | |
1031 | ||
1032 | /* add add. addo addo. */ | |
1033 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
1034 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
1035 | /* addc addc. addco addco. */ | |
1036 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
1037 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
1038 | /* adde adde. addeo addeo. */ | |
1039 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
1040 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
1041 | /* addme addme. addmeo addmeo. */ | |
1042 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
1043 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
1044 | /* addze addze. addzeo addzeo.*/ | |
1045 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
1046 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
1047 | /* addi */ | |
99e300ef | 1048 | static void gen_addi(DisasContext *ctx) |
d9bce9d9 | 1049 | { |
74637406 AJ |
1050 | target_long simm = SIMM(ctx->opcode); |
1051 | ||
1052 | if (rA(ctx->opcode) == 0) { | |
1053 | /* li case */ | |
1054 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); | |
1055 | } else { | |
b5a73f8d RH |
1056 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
1057 | cpu_gpr[rA(ctx->opcode)], simm); | |
74637406 | 1058 | } |
d9bce9d9 | 1059 | } |
74637406 | 1060 | /* addic addic.*/ |
b5a73f8d | 1061 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
d9bce9d9 | 1062 | { |
b5a73f8d RH |
1063 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1064 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1065 | c, 0, 1, 0, compute_rc0); | |
1066 | tcg_temp_free(c); | |
d9bce9d9 | 1067 | } |
99e300ef BS |
1068 | |
1069 | static void gen_addic(DisasContext *ctx) | |
d9bce9d9 | 1070 | { |
b5a73f8d | 1071 | gen_op_addic(ctx, 0); |
d9bce9d9 | 1072 | } |
e8eaa2c0 BS |
1073 | |
1074 | static void gen_addic_(DisasContext *ctx) | |
d9bce9d9 | 1075 | { |
b5a73f8d | 1076 | gen_op_addic(ctx, 1); |
d9bce9d9 | 1077 | } |
99e300ef | 1078 | |
54623277 | 1079 | /* addis */ |
99e300ef | 1080 | static void gen_addis(DisasContext *ctx) |
d9bce9d9 | 1081 | { |
74637406 AJ |
1082 | target_long simm = SIMM(ctx->opcode); |
1083 | ||
1084 | if (rA(ctx->opcode) == 0) { | |
1085 | /* lis case */ | |
1086 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); | |
1087 | } else { | |
b5a73f8d RH |
1088 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
1089 | cpu_gpr[rA(ctx->opcode)], simm << 16); | |
74637406 | 1090 | } |
d9bce9d9 | 1091 | } |
74637406 | 1092 | |
c5b2b9ce ND |
1093 | /* addpcis */ |
1094 | static void gen_addpcis(DisasContext *ctx) | |
1095 | { | |
1096 | target_long d = DX(ctx->opcode); | |
1097 | ||
1098 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->nip + (d << 16)); | |
1099 | } | |
1100 | ||
636aa200 BS |
1101 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1102 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1103 | { |
b07c32dc ND |
1104 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1105 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1106 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1107 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
74637406 | 1108 | |
2ef1b120 AJ |
1109 | tcg_gen_trunc_tl_i32(t0, arg1); |
1110 | tcg_gen_trunc_tl_i32(t1, arg2); | |
74637406 | 1111 | if (sign) { |
b07c32dc ND |
1112 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); |
1113 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1114 | tcg_gen_and_i32(t2, t2, t3); | |
1115 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1116 | tcg_gen_or_i32(t2, t2, t3); | |
1117 | tcg_gen_movi_i32(t3, 0); | |
1118 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1119 | tcg_gen_div_i32(t3, t0, t1); | |
1120 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 | 1121 | } else { |
b07c32dc ND |
1122 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); |
1123 | tcg_gen_movi_i32(t3, 0); | |
1124 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1125 | tcg_gen_divu_i32(t3, t0, t1); | |
1126 | tcg_gen_extu_i32_tl(ret, t3); | |
74637406 AJ |
1127 | } |
1128 | if (compute_ov) { | |
b07c32dc ND |
1129 | tcg_gen_extu_i32_tl(cpu_ov, t2); |
1130 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
74637406 | 1131 | } |
a7812ae4 PB |
1132 | tcg_temp_free_i32(t0); |
1133 | tcg_temp_free_i32(t1); | |
b07c32dc ND |
1134 | tcg_temp_free_i32(t2); |
1135 | tcg_temp_free_i32(t3); | |
1136 | ||
74637406 AJ |
1137 | if (unlikely(Rc(ctx->opcode) != 0)) |
1138 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1139 | } |
74637406 AJ |
1140 | /* Div functions */ |
1141 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
99e300ef | 1142 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1143 | { \ |
1144 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1145 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1146 | sign, compute_ov); \ | |
1147 | } | |
1148 | /* divwu divwu. divwuo divwuo. */ | |
1149 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); | |
1150 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); | |
1151 | /* divw divw. divwo divwo. */ | |
1152 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); | |
1153 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); | |
98d1eb27 TM |
1154 | |
1155 | /* div[wd]eu[o][.] */ | |
1156 | #define GEN_DIVE(name, hlpr, compute_ov) \ | |
1157 | static void gen_##name(DisasContext *ctx) \ | |
1158 | { \ | |
1159 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ | |
1160 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ | |
1161 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ | |
1162 | tcg_temp_free_i32(t0); \ | |
1163 | if (unlikely(Rc(ctx->opcode) != 0)) { \ | |
1164 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ | |
1165 | } \ | |
1166 | } | |
1167 | ||
6a4fda33 TM |
1168 | GEN_DIVE(divweu, divweu, 0); |
1169 | GEN_DIVE(divweuo, divweu, 1); | |
a98eb9e9 TM |
1170 | GEN_DIVE(divwe, divwe, 0); |
1171 | GEN_DIVE(divweo, divwe, 1); | |
6a4fda33 | 1172 | |
d9bce9d9 | 1173 | #if defined(TARGET_PPC64) |
636aa200 BS |
1174 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1175 | TCGv arg2, int sign, int compute_ov) | |
d9bce9d9 | 1176 | { |
4110b586 ND |
1177 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1178 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1179 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1180 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
74637406 | 1181 | |
4110b586 ND |
1182 | tcg_gen_mov_i64(t0, arg1); |
1183 | tcg_gen_mov_i64(t1, arg2); | |
74637406 | 1184 | if (sign) { |
4110b586 ND |
1185 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); |
1186 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1187 | tcg_gen_and_i64(t2, t2, t3); | |
1188 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1189 | tcg_gen_or_i64(t2, t2, t3); | |
1190 | tcg_gen_movi_i64(t3, 0); | |
1191 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1192 | tcg_gen_div_i64(ret, t0, t1); | |
74637406 | 1193 | } else { |
4110b586 ND |
1194 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); |
1195 | tcg_gen_movi_i64(t3, 0); | |
1196 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1197 | tcg_gen_divu_i64(ret, t0, t1); | |
74637406 AJ |
1198 | } |
1199 | if (compute_ov) { | |
4110b586 ND |
1200 | tcg_gen_mov_tl(cpu_ov, t2); |
1201 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
74637406 | 1202 | } |
4110b586 ND |
1203 | tcg_temp_free_i64(t0); |
1204 | tcg_temp_free_i64(t1); | |
1205 | tcg_temp_free_i64(t2); | |
1206 | tcg_temp_free_i64(t3); | |
1207 | ||
74637406 AJ |
1208 | if (unlikely(Rc(ctx->opcode) != 0)) |
1209 | gen_set_Rc0(ctx, ret); | |
d9bce9d9 | 1210 | } |
4110b586 | 1211 | |
74637406 | 1212 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
99e300ef | 1213 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1214 | { \ |
2ef1b120 AJ |
1215 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1216 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1217 | sign, compute_ov); \ | |
74637406 AJ |
1218 | } |
1219 | /* divwu divwu. divwuo divwuo. */ | |
1220 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); | |
1221 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); | |
1222 | /* divw divw. divwo divwo. */ | |
1223 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); | |
1224 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); | |
98d1eb27 TM |
1225 | |
1226 | GEN_DIVE(divdeu, divdeu, 0); | |
1227 | GEN_DIVE(divdeuo, divdeu, 1); | |
e44259b6 TM |
1228 | GEN_DIVE(divde, divde, 0); |
1229 | GEN_DIVE(divdeo, divde, 1); | |
d9bce9d9 | 1230 | #endif |
74637406 | 1231 | |
af2c6620 ND |
1232 | static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1233 | TCGv arg2, int sign) | |
1234 | { | |
1235 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1236 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
1237 | ||
1238 | tcg_gen_trunc_tl_i32(t0, arg1); | |
1239 | tcg_gen_trunc_tl_i32(t1, arg2); | |
1240 | if (sign) { | |
1241 | TCGv_i32 t2 = tcg_temp_new_i32(); | |
1242 | TCGv_i32 t3 = tcg_temp_new_i32(); | |
1243 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); | |
1244 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); | |
1245 | tcg_gen_and_i32(t2, t2, t3); | |
1246 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); | |
1247 | tcg_gen_or_i32(t2, t2, t3); | |
1248 | tcg_gen_movi_i32(t3, 0); | |
1249 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1250 | tcg_gen_rem_i32(t3, t0, t1); | |
1251 | tcg_gen_ext_i32_tl(ret, t3); | |
1252 | tcg_temp_free_i32(t2); | |
1253 | tcg_temp_free_i32(t3); | |
1254 | } else { | |
1255 | TCGv_i32 t2 = tcg_const_i32(1); | |
1256 | TCGv_i32 t3 = tcg_const_i32(0); | |
1257 | tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1258 | tcg_gen_remu_i32(t3, t0, t1); | |
1259 | tcg_gen_extu_i32_tl(ret, t3); | |
1260 | tcg_temp_free_i32(t2); | |
1261 | tcg_temp_free_i32(t3); | |
1262 | } | |
1263 | tcg_temp_free_i32(t0); | |
1264 | tcg_temp_free_i32(t1); | |
1265 | } | |
1266 | ||
1267 | #define GEN_INT_ARITH_MODW(name, opc3, sign) \ | |
1268 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1269 | { \ | |
1270 | gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1271 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1272 | sign); \ | |
1273 | } | |
1274 | ||
1275 | GEN_INT_ARITH_MODW(moduw, 0x08, 0); | |
1276 | GEN_INT_ARITH_MODW(modsw, 0x18, 1); | |
1277 | ||
063cf14f ND |
1278 | #if defined(TARGET_PPC64) |
1279 | static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, | |
1280 | TCGv arg2, int sign) | |
1281 | { | |
1282 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
1283 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1284 | ||
1285 | tcg_gen_mov_i64(t0, arg1); | |
1286 | tcg_gen_mov_i64(t1, arg2); | |
1287 | if (sign) { | |
1288 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
1289 | TCGv_i64 t3 = tcg_temp_new_i64(); | |
1290 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); | |
1291 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); | |
1292 | tcg_gen_and_i64(t2, t2, t3); | |
1293 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); | |
1294 | tcg_gen_or_i64(t2, t2, t3); | |
1295 | tcg_gen_movi_i64(t3, 0); | |
1296 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); | |
1297 | tcg_gen_rem_i64(ret, t0, t1); | |
1298 | tcg_temp_free_i64(t2); | |
1299 | tcg_temp_free_i64(t3); | |
1300 | } else { | |
1301 | TCGv_i64 t2 = tcg_const_i64(1); | |
1302 | TCGv_i64 t3 = tcg_const_i64(0); | |
1303 | tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); | |
1304 | tcg_gen_remu_i64(ret, t0, t1); | |
1305 | tcg_temp_free_i64(t2); | |
1306 | tcg_temp_free_i64(t3); | |
1307 | } | |
1308 | tcg_temp_free_i64(t0); | |
1309 | tcg_temp_free_i64(t1); | |
1310 | } | |
1311 | ||
1312 | #define GEN_INT_ARITH_MODD(name, opc3, sign) \ | |
1313 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1314 | { \ | |
1315 | gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1316 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
1317 | sign); \ | |
1318 | } | |
1319 | ||
1320 | GEN_INT_ARITH_MODD(modud, 0x08, 0); | |
1321 | GEN_INT_ARITH_MODD(modsd, 0x18, 1); | |
1322 | #endif | |
1323 | ||
74637406 | 1324 | /* mulhw mulhw. */ |
99e300ef | 1325 | static void gen_mulhw(DisasContext *ctx) |
d9bce9d9 | 1326 | { |
23ad1d5d RH |
1327 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1328 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1329 | |
23ad1d5d RH |
1330 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1331 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1332 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
1333 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1334 | tcg_temp_free_i32(t0); | |
1335 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1336 | if (unlikely(Rc(ctx->opcode) != 0)) |
1337 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1338 | } |
99e300ef | 1339 | |
54623277 | 1340 | /* mulhwu mulhwu. */ |
99e300ef | 1341 | static void gen_mulhwu(DisasContext *ctx) |
d9bce9d9 | 1342 | { |
23ad1d5d RH |
1343 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1344 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1345 | |
23ad1d5d RH |
1346 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1347 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1348 | tcg_gen_mulu2_i32(t0, t1, t0, t1); | |
1349 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
1350 | tcg_temp_free_i32(t0); | |
1351 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1352 | if (unlikely(Rc(ctx->opcode) != 0)) |
1353 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1354 | } |
99e300ef | 1355 | |
54623277 | 1356 | /* mullw mullw. */ |
99e300ef | 1357 | static void gen_mullw(DisasContext *ctx) |
d9bce9d9 | 1358 | { |
1fa74845 TM |
1359 | #if defined(TARGET_PPC64) |
1360 | TCGv_i64 t0, t1; | |
1361 | t0 = tcg_temp_new_i64(); | |
1362 | t1 = tcg_temp_new_i64(); | |
1363 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); | |
1364 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); | |
1365 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); | |
1366 | tcg_temp_free(t0); | |
1367 | tcg_temp_free(t1); | |
1368 | #else | |
03039e5e TM |
1369 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1370 | cpu_gpr[rB(ctx->opcode)]); | |
1fa74845 | 1371 | #endif |
74637406 AJ |
1372 | if (unlikely(Rc(ctx->opcode) != 0)) |
1373 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1374 | } |
99e300ef | 1375 | |
54623277 | 1376 | /* mullwo mullwo. */ |
99e300ef | 1377 | static void gen_mullwo(DisasContext *ctx) |
d9bce9d9 | 1378 | { |
e4a2c846 RH |
1379 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1380 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
74637406 | 1381 | |
e4a2c846 RH |
1382 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1383 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); | |
1384 | tcg_gen_muls2_i32(t0, t1, t0, t1); | |
f11ebbf8 | 1385 | #if defined(TARGET_PPC64) |
26977876 TM |
1386 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1387 | #else | |
1388 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); | |
f11ebbf8 | 1389 | #endif |
e4a2c846 RH |
1390 | |
1391 | tcg_gen_sari_i32(t0, t0, 31); | |
1392 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); | |
1393 | tcg_gen_extu_i32_tl(cpu_ov, t0); | |
1394 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1395 | ||
1396 | tcg_temp_free_i32(t0); | |
1397 | tcg_temp_free_i32(t1); | |
74637406 AJ |
1398 | if (unlikely(Rc(ctx->opcode) != 0)) |
1399 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1400 | } |
99e300ef | 1401 | |
54623277 | 1402 | /* mulli */ |
99e300ef | 1403 | static void gen_mulli(DisasContext *ctx) |
d9bce9d9 | 1404 | { |
74637406 AJ |
1405 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1406 | SIMM(ctx->opcode)); | |
d9bce9d9 | 1407 | } |
23ad1d5d | 1408 | |
d9bce9d9 | 1409 | #if defined(TARGET_PPC64) |
74637406 | 1410 | /* mulhd mulhd. */ |
23ad1d5d RH |
1411 | static void gen_mulhd(DisasContext *ctx) |
1412 | { | |
1413 | TCGv lo = tcg_temp_new(); | |
1414 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1415 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1416 | tcg_temp_free(lo); | |
1417 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1418 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1419 | } | |
1420 | } | |
1421 | ||
74637406 | 1422 | /* mulhdu mulhdu. */ |
23ad1d5d RH |
1423 | static void gen_mulhdu(DisasContext *ctx) |
1424 | { | |
1425 | TCGv lo = tcg_temp_new(); | |
1426 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], | |
1427 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1428 | tcg_temp_free(lo); | |
1429 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1430 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1431 | } | |
1432 | } | |
99e300ef | 1433 | |
54623277 | 1434 | /* mulld mulld. */ |
99e300ef | 1435 | static void gen_mulld(DisasContext *ctx) |
d9bce9d9 | 1436 | { |
74637406 AJ |
1437 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1438 | cpu_gpr[rB(ctx->opcode)]); | |
1439 | if (unlikely(Rc(ctx->opcode) != 0)) | |
1440 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
d9bce9d9 | 1441 | } |
d15f74fb | 1442 | |
74637406 | 1443 | /* mulldo mulldo. */ |
d15f74fb BS |
1444 | static void gen_mulldo(DisasContext *ctx) |
1445 | { | |
22ffad31 TM |
1446 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1447 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
1448 | ||
1449 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], | |
1450 | cpu_gpr[rB(ctx->opcode)]); | |
1451 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); | |
1452 | ||
1453 | tcg_gen_sari_i64(t0, t0, 63); | |
1454 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); | |
1455 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); | |
1456 | ||
1457 | tcg_temp_free_i64(t0); | |
1458 | tcg_temp_free_i64(t1); | |
1459 | ||
d15f74fb BS |
1460 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1461 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
1462 | } | |
1463 | } | |
d9bce9d9 | 1464 | #endif |
74637406 | 1465 | |
74637406 | 1466 | /* Common subf function */ |
636aa200 | 1467 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
b5a73f8d RH |
1468 | TCGv arg2, bool add_ca, bool compute_ca, |
1469 | bool compute_ov, bool compute_rc0) | |
79aceca5 | 1470 | { |
b5a73f8d | 1471 | TCGv t0 = ret; |
79aceca5 | 1472 | |
752d634e | 1473 | if (compute_ca || compute_ov) { |
b5a73f8d | 1474 | t0 = tcg_temp_new(); |
da91a00f | 1475 | } |
74637406 | 1476 | |
79482e5a RH |
1477 | if (compute_ca) { |
1478 | /* dest = ~arg1 + arg2 [+ ca]. */ | |
1479 | if (NARROW_MODE(ctx)) { | |
752d634e RH |
1480 | /* Caution: a non-obvious corner case of the spec is that we |
1481 | must produce the *entire* 64-bit addition, but produce the | |
1482 | carry into bit 32. */ | |
79482e5a | 1483 | TCGv inv1 = tcg_temp_new(); |
752d634e | 1484 | TCGv t1 = tcg_temp_new(); |
79482e5a | 1485 | tcg_gen_not_tl(inv1, arg1); |
79482e5a | 1486 | if (add_ca) { |
752d634e | 1487 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
79482e5a | 1488 | } else { |
752d634e | 1489 | tcg_gen_addi_tl(t0, arg2, 1); |
79482e5a | 1490 | } |
752d634e | 1491 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
79482e5a | 1492 | tcg_gen_add_tl(t0, t0, inv1); |
c80d1df5 | 1493 | tcg_temp_free(inv1); |
752d634e RH |
1494 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1495 | tcg_temp_free(t1); | |
1496 | tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */ | |
1497 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
79482e5a | 1498 | } else if (add_ca) { |
08f4a0f7 RH |
1499 | TCGv zero, inv1 = tcg_temp_new(); |
1500 | tcg_gen_not_tl(inv1, arg1); | |
b5a73f8d RH |
1501 | zero = tcg_const_tl(0); |
1502 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); | |
08f4a0f7 | 1503 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
b5a73f8d | 1504 | tcg_temp_free(zero); |
08f4a0f7 | 1505 | tcg_temp_free(inv1); |
b5a73f8d | 1506 | } else { |
79482e5a | 1507 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
b5a73f8d | 1508 | tcg_gen_sub_tl(t0, arg2, arg1); |
b5a73f8d | 1509 | } |
79482e5a RH |
1510 | } else if (add_ca) { |
1511 | /* Since we're ignoring carry-out, we can simplify the | |
1512 | standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */ | |
1513 | tcg_gen_sub_tl(t0, arg2, arg1); | |
1514 | tcg_gen_add_tl(t0, t0, cpu_ca); | |
1515 | tcg_gen_subi_tl(t0, t0, 1); | |
79aceca5 | 1516 | } else { |
b5a73f8d | 1517 | tcg_gen_sub_tl(t0, arg2, arg1); |
74637406 | 1518 | } |
b5a73f8d | 1519 | |
74637406 AJ |
1520 | if (compute_ov) { |
1521 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); | |
1522 | } | |
b5a73f8d | 1523 | if (unlikely(compute_rc0)) { |
74637406 | 1524 | gen_set_Rc0(ctx, t0); |
b5a73f8d | 1525 | } |
74637406 | 1526 | |
a7812ae4 | 1527 | if (!TCGV_EQUAL(t0, ret)) { |
74637406 AJ |
1528 | tcg_gen_mov_tl(ret, t0); |
1529 | tcg_temp_free(t0); | |
79aceca5 | 1530 | } |
79aceca5 | 1531 | } |
74637406 AJ |
1532 | /* Sub functions with Two operands functions */ |
1533 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1534 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 AJ |
1535 | { \ |
1536 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ | |
1537 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ | |
b5a73f8d | 1538 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1539 | } |
1540 | /* Sub functions with one operand and one immediate */ | |
1541 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
1542 | add_ca, compute_ca, compute_ov) \ | |
b5a73f8d | 1543 | static void glue(gen_, name)(DisasContext *ctx) \ |
74637406 | 1544 | { \ |
b5a73f8d | 1545 | TCGv t0 = tcg_const_tl(const_val); \ |
74637406 AJ |
1546 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1547 | cpu_gpr[rA(ctx->opcode)], t0, \ | |
b5a73f8d | 1548 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
74637406 AJ |
1549 | tcg_temp_free(t0); \ |
1550 | } | |
1551 | /* subf subf. subfo subfo. */ | |
1552 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
1553 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
1554 | /* subfc subfc. subfco subfco. */ | |
1555 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
1556 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
1557 | /* subfe subfe. subfeo subfo. */ | |
1558 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
1559 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
1560 | /* subfme subfme. subfmeo subfmeo. */ | |
1561 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
1562 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
1563 | /* subfze subfze. subfzeo subfzeo.*/ | |
1564 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
1565 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
99e300ef | 1566 | |
54623277 | 1567 | /* subfic */ |
99e300ef | 1568 | static void gen_subfic(DisasContext *ctx) |
79aceca5 | 1569 | { |
b5a73f8d RH |
1570 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1571 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1572 | c, 0, 1, 0, 0); | |
1573 | tcg_temp_free(c); | |
79aceca5 FB |
1574 | } |
1575 | ||
fd3f0081 RH |
1576 | /* neg neg. nego nego. */ |
1577 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) | |
1578 | { | |
1579 | TCGv zero = tcg_const_tl(0); | |
1580 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], | |
1581 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); | |
1582 | tcg_temp_free(zero); | |
1583 | } | |
1584 | ||
1585 | static void gen_neg(DisasContext *ctx) | |
1586 | { | |
1587 | gen_op_arith_neg(ctx, 0); | |
1588 | } | |
1589 | ||
1590 | static void gen_nego(DisasContext *ctx) | |
1591 | { | |
1592 | gen_op_arith_neg(ctx, 1); | |
1593 | } | |
1594 | ||
79aceca5 | 1595 | /*** Integer logical ***/ |
26d67362 | 1596 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
99e300ef | 1597 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1598 | { \ |
26d67362 AJ |
1599 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1600 | cpu_gpr[rB(ctx->opcode)]); \ | |
76a66253 | 1601 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1602 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 | 1603 | } |
79aceca5 | 1604 | |
26d67362 | 1605 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
99e300ef | 1606 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 1607 | { \ |
26d67362 | 1608 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
76a66253 | 1609 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
26d67362 | 1610 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
79aceca5 FB |
1611 | } |
1612 | ||
1613 | /* and & and. */ | |
26d67362 | 1614 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
79aceca5 | 1615 | /* andc & andc. */ |
26d67362 | 1616 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
e8eaa2c0 | 1617 | |
54623277 | 1618 | /* andi. */ |
e8eaa2c0 | 1619 | static void gen_andi_(DisasContext *ctx) |
79aceca5 | 1620 | { |
26d67362 AJ |
1621 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode)); |
1622 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1623 | } |
e8eaa2c0 | 1624 | |
54623277 | 1625 | /* andis. */ |
e8eaa2c0 | 1626 | static void gen_andis_(DisasContext *ctx) |
79aceca5 | 1627 | { |
26d67362 AJ |
1628 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16); |
1629 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
79aceca5 | 1630 | } |
99e300ef | 1631 | |
54623277 | 1632 | /* cntlzw */ |
99e300ef | 1633 | static void gen_cntlzw(DisasContext *ctx) |
26d67362 | 1634 | { |
a7812ae4 | 1635 | gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 | 1636 | if (unlikely(Rc(ctx->opcode) != 0)) |
2e31f5d3 | 1637 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
26d67362 | 1638 | } |
b35344e4 ND |
1639 | |
1640 | /* cnttzw */ | |
1641 | static void gen_cnttzw(DisasContext *ctx) | |
1642 | { | |
1643 | gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1644 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1645 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1646 | } | |
1647 | } | |
1648 | ||
79aceca5 | 1649 | /* eqv & eqv. */ |
26d67362 | 1650 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
79aceca5 | 1651 | /* extsb & extsb. */ |
26d67362 | 1652 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
79aceca5 | 1653 | /* extsh & extsh. */ |
26d67362 | 1654 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
79aceca5 | 1655 | /* nand & nand. */ |
26d67362 | 1656 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
79aceca5 | 1657 | /* nor & nor. */ |
26d67362 | 1658 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
99e300ef | 1659 | |
7f2b1744 | 1660 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
b68e60e6 BH |
1661 | static void gen_pause(DisasContext *ctx) |
1662 | { | |
1663 | TCGv_i32 t0 = tcg_const_i32(0); | |
1664 | tcg_gen_st_i32(t0, cpu_env, | |
1665 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
1666 | tcg_temp_free_i32(t0); | |
1667 | ||
1668 | /* Stop translation, this gives other CPUs a chance to run */ | |
bd6fefe7 | 1669 | gen_exception_nip(ctx, EXCP_HLT, ctx->nip); |
b68e60e6 BH |
1670 | } |
1671 | #endif /* defined(TARGET_PPC64) */ | |
1672 | ||
54623277 | 1673 | /* or & or. */ |
99e300ef | 1674 | static void gen_or(DisasContext *ctx) |
9a64fbe4 | 1675 | { |
76a66253 JM |
1676 | int rs, ra, rb; |
1677 | ||
1678 | rs = rS(ctx->opcode); | |
1679 | ra = rA(ctx->opcode); | |
1680 | rb = rB(ctx->opcode); | |
1681 | /* Optimisation for mr. ri case */ | |
1682 | if (rs != ra || rs != rb) { | |
26d67362 AJ |
1683 | if (rs != rb) |
1684 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); | |
1685 | else | |
1686 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); | |
76a66253 | 1687 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1688 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
76a66253 | 1689 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
26d67362 | 1690 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
c80f84e3 | 1691 | #if defined(TARGET_PPC64) |
9e196938 | 1692 | } else if (rs != 0) { /* 0 is nop */ |
26d67362 AJ |
1693 | int prio = 0; |
1694 | ||
c80f84e3 JM |
1695 | switch (rs) { |
1696 | case 1: | |
1697 | /* Set process priority to low */ | |
26d67362 | 1698 | prio = 2; |
c80f84e3 JM |
1699 | break; |
1700 | case 6: | |
1701 | /* Set process priority to medium-low */ | |
26d67362 | 1702 | prio = 3; |
c80f84e3 JM |
1703 | break; |
1704 | case 2: | |
1705 | /* Set process priority to normal */ | |
26d67362 | 1706 | prio = 4; |
c80f84e3 | 1707 | break; |
be147d08 JM |
1708 | #if !defined(CONFIG_USER_ONLY) |
1709 | case 31: | |
c47493f2 | 1710 | if (!ctx->pr) { |
be147d08 | 1711 | /* Set process priority to very low */ |
26d67362 | 1712 | prio = 1; |
be147d08 JM |
1713 | } |
1714 | break; | |
1715 | case 5: | |
c47493f2 | 1716 | if (!ctx->pr) { |
be147d08 | 1717 | /* Set process priority to medium-hight */ |
26d67362 | 1718 | prio = 5; |
be147d08 JM |
1719 | } |
1720 | break; | |
1721 | case 3: | |
c47493f2 | 1722 | if (!ctx->pr) { |
be147d08 | 1723 | /* Set process priority to high */ |
26d67362 | 1724 | prio = 6; |
be147d08 JM |
1725 | } |
1726 | break; | |
be147d08 | 1727 | case 7: |
b68e60e6 | 1728 | if (ctx->hv && !ctx->pr) { |
be147d08 | 1729 | /* Set process priority to very high */ |
26d67362 | 1730 | prio = 7; |
be147d08 JM |
1731 | } |
1732 | break; | |
be147d08 | 1733 | #endif |
c80f84e3 | 1734 | default: |
c80f84e3 JM |
1735 | break; |
1736 | } | |
26d67362 | 1737 | if (prio) { |
a7812ae4 | 1738 | TCGv t0 = tcg_temp_new(); |
54cdcae6 | 1739 | gen_load_spr(t0, SPR_PPR); |
ea363694 AJ |
1740 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1741 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); | |
54cdcae6 | 1742 | gen_store_spr(SPR_PPR, t0); |
ea363694 | 1743 | tcg_temp_free(t0); |
9e196938 | 1744 | } |
7f2b1744 | 1745 | #if !defined(CONFIG_USER_ONLY) |
9e196938 AL |
1746 | /* Pause out of TCG otherwise spin loops with smt_low eat too much |
1747 | * CPU and the kernel hangs. This applies to all encodings other | |
1748 | * than no-op, e.g., miso(rs=26), yield(27), mdoio(29), mdoom(30), | |
1749 | * and all currently undefined. | |
1750 | */ | |
1751 | gen_pause(ctx); | |
7f2b1744 | 1752 | #endif |
c80f84e3 | 1753 | #endif |
9a64fbe4 | 1754 | } |
9a64fbe4 | 1755 | } |
79aceca5 | 1756 | /* orc & orc. */ |
26d67362 | 1757 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
99e300ef | 1758 | |
54623277 | 1759 | /* xor & xor. */ |
99e300ef | 1760 | static void gen_xor(DisasContext *ctx) |
9a64fbe4 | 1761 | { |
9a64fbe4 | 1762 | /* Optimisation for "set to zero" case */ |
26d67362 | 1763 | if (rS(ctx->opcode) != rB(ctx->opcode)) |
312179c4 | 1764 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
1765 | else |
1766 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
76a66253 | 1767 | if (unlikely(Rc(ctx->opcode) != 0)) |
26d67362 | 1768 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
9a64fbe4 | 1769 | } |
99e300ef | 1770 | |
54623277 | 1771 | /* ori */ |
99e300ef | 1772 | static void gen_ori(DisasContext *ctx) |
79aceca5 | 1773 | { |
76a66253 | 1774 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1775 | |
9a64fbe4 | 1776 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
9a64fbe4 | 1777 | return; |
76a66253 | 1778 | } |
26d67362 | 1779 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1780 | } |
99e300ef | 1781 | |
54623277 | 1782 | /* oris */ |
99e300ef | 1783 | static void gen_oris(DisasContext *ctx) |
79aceca5 | 1784 | { |
76a66253 | 1785 | target_ulong uimm = UIMM(ctx->opcode); |
79aceca5 | 1786 | |
9a64fbe4 FB |
1787 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1788 | /* NOP */ | |
1789 | return; | |
76a66253 | 1790 | } |
26d67362 | 1791 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1792 | } |
99e300ef | 1793 | |
54623277 | 1794 | /* xori */ |
99e300ef | 1795 | static void gen_xori(DisasContext *ctx) |
79aceca5 | 1796 | { |
76a66253 | 1797 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1798 | |
1799 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1800 | /* NOP */ | |
1801 | return; | |
1802 | } | |
26d67362 | 1803 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
79aceca5 | 1804 | } |
99e300ef | 1805 | |
54623277 | 1806 | /* xoris */ |
99e300ef | 1807 | static void gen_xoris(DisasContext *ctx) |
79aceca5 | 1808 | { |
76a66253 | 1809 | target_ulong uimm = UIMM(ctx->opcode); |
9a64fbe4 FB |
1810 | |
1811 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { | |
1812 | /* NOP */ | |
1813 | return; | |
1814 | } | |
26d67362 | 1815 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16); |
79aceca5 | 1816 | } |
99e300ef | 1817 | |
54623277 | 1818 | /* popcntb : PowerPC 2.03 specification */ |
99e300ef | 1819 | static void gen_popcntb(DisasContext *ctx) |
d9bce9d9 | 1820 | { |
eaabeef2 DG |
1821 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1822 | } | |
1823 | ||
1824 | static void gen_popcntw(DisasContext *ctx) | |
1825 | { | |
1826 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1827 | } | |
1828 | ||
d9bce9d9 | 1829 | #if defined(TARGET_PPC64) |
eaabeef2 DG |
1830 | /* popcntd: PowerPC 2.06 specification */ |
1831 | static void gen_popcntd(DisasContext *ctx) | |
1832 | { | |
1833 | gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 1834 | } |
eaabeef2 | 1835 | #endif |
d9bce9d9 | 1836 | |
725bcec2 AJ |
1837 | /* prtyw: PowerPC 2.05 specification */ |
1838 | static void gen_prtyw(DisasContext *ctx) | |
1839 | { | |
1840 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1841 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1842 | TCGv t0 = tcg_temp_new(); | |
1843 | tcg_gen_shri_tl(t0, rs, 16); | |
1844 | tcg_gen_xor_tl(ra, rs, t0); | |
1845 | tcg_gen_shri_tl(t0, ra, 8); | |
1846 | tcg_gen_xor_tl(ra, ra, t0); | |
1847 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); | |
1848 | tcg_temp_free(t0); | |
1849 | } | |
1850 | ||
1851 | #if defined(TARGET_PPC64) | |
1852 | /* prtyd: PowerPC 2.05 specification */ | |
1853 | static void gen_prtyd(DisasContext *ctx) | |
1854 | { | |
1855 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; | |
1856 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; | |
1857 | TCGv t0 = tcg_temp_new(); | |
1858 | tcg_gen_shri_tl(t0, rs, 32); | |
1859 | tcg_gen_xor_tl(ra, rs, t0); | |
1860 | tcg_gen_shri_tl(t0, ra, 16); | |
1861 | tcg_gen_xor_tl(ra, ra, t0); | |
1862 | tcg_gen_shri_tl(t0, ra, 8); | |
1863 | tcg_gen_xor_tl(ra, ra, t0); | |
1864 | tcg_gen_andi_tl(ra, ra, 1); | |
1865 | tcg_temp_free(t0); | |
1866 | } | |
1867 | #endif | |
1868 | ||
86ba37ed TM |
1869 | #if defined(TARGET_PPC64) |
1870 | /* bpermd */ | |
1871 | static void gen_bpermd(DisasContext *ctx) | |
1872 | { | |
1873 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], | |
1874 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
1875 | } | |
1876 | #endif | |
1877 | ||
d9bce9d9 JM |
1878 | #if defined(TARGET_PPC64) |
1879 | /* extsw & extsw. */ | |
26d67362 | 1880 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
99e300ef | 1881 | |
54623277 | 1882 | /* cntlzd */ |
99e300ef | 1883 | static void gen_cntlzd(DisasContext *ctx) |
26d67362 | 1884 | { |
a7812ae4 | 1885 | gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
26d67362 AJ |
1886 | if (unlikely(Rc(ctx->opcode) != 0)) |
1887 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1888 | } | |
e91d95b2 SD |
1889 | |
1890 | /* cnttzd */ | |
1891 | static void gen_cnttzd(DisasContext *ctx) | |
1892 | { | |
1893 | gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); | |
1894 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1895 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
1896 | } | |
1897 | } | |
d9bce9d9 JM |
1898 | #endif |
1899 | ||
79aceca5 | 1900 | /*** Integer rotate ***/ |
99e300ef | 1901 | |
54623277 | 1902 | /* rlwimi & rlwimi. */ |
99e300ef | 1903 | static void gen_rlwimi(DisasContext *ctx) |
79aceca5 | 1904 | { |
63ae0915 RH |
1905 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1906 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1907 | uint32_t sh = SH(ctx->opcode); | |
1908 | uint32_t mb = MB(ctx->opcode); | |
1909 | uint32_t me = ME(ctx->opcode); | |
1910 | ||
1911 | if (sh == (31-me) && mb <= me) { | |
1912 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 1913 | } else { |
d03ef511 | 1914 | target_ulong mask; |
a7812ae4 | 1915 | TCGv t1; |
63ae0915 | 1916 | |
76a66253 | 1917 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1918 | mb += 32; |
1919 | me += 32; | |
76a66253 | 1920 | #endif |
d03ef511 | 1921 | mask = MASK(mb, me); |
63ae0915 | 1922 | |
a7812ae4 | 1923 | t1 = tcg_temp_new(); |
2e11b15d RH |
1924 | if (mask <= 0xffffffffu) { |
1925 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
1926 | tcg_gen_trunc_tl_i32(t0, t_rs); | |
1927 | tcg_gen_rotli_i32(t0, t0, sh); | |
1928 | tcg_gen_extu_i32_tl(t1, t0); | |
1929 | tcg_temp_free_i32(t0); | |
1930 | } else { | |
1931 | #if defined(TARGET_PPC64) | |
1932 | tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); | |
1933 | tcg_gen_rotli_i64(t1, t1, sh); | |
1934 | #else | |
1935 | g_assert_not_reached(); | |
1936 | #endif | |
1937 | } | |
63ae0915 RH |
1938 | |
1939 | tcg_gen_andi_tl(t1, t1, mask); | |
1940 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
1941 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 AJ |
1942 | tcg_temp_free(t1); |
1943 | } | |
63ae0915 RH |
1944 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1945 | gen_set_Rc0(ctx, t_ra); | |
1946 | } | |
79aceca5 | 1947 | } |
99e300ef | 1948 | |
54623277 | 1949 | /* rlwinm & rlwinm. */ |
99e300ef | 1950 | static void gen_rlwinm(DisasContext *ctx) |
79aceca5 | 1951 | { |
63ae0915 RH |
1952 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1953 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1954 | uint32_t sh = SH(ctx->opcode); | |
1955 | uint32_t mb = MB(ctx->opcode); | |
1956 | uint32_t me = ME(ctx->opcode); | |
1957 | ||
1958 | if (mb == 0 && me == (31 - sh)) { | |
1959 | tcg_gen_shli_tl(t_ra, t_rs, sh); | |
1960 | tcg_gen_ext32u_tl(t_ra, t_ra); | |
1961 | } else if (sh != 0 && me == 31 && sh == (32 - mb)) { | |
1962 | tcg_gen_ext32u_tl(t_ra, t_rs); | |
1963 | tcg_gen_shri_tl(t_ra, t_ra, mb); | |
d03ef511 | 1964 | } else { |
2e11b15d | 1965 | target_ulong mask; |
76a66253 | 1966 | #if defined(TARGET_PPC64) |
d03ef511 AJ |
1967 | mb += 32; |
1968 | me += 32; | |
76a66253 | 1969 | #endif |
2e11b15d RH |
1970 | mask = MASK(mb, me); |
1971 | ||
820724d1 | 1972 | if (mask <= 0xffffffffu) { |
63ae0915 | 1973 | TCGv_i32 t0 = tcg_temp_new_i32(); |
63ae0915 RH |
1974 | tcg_gen_trunc_tl_i32(t0, t_rs); |
1975 | tcg_gen_rotli_i32(t0, t0, sh); | |
2e11b15d | 1976 | tcg_gen_andi_i32(t0, t0, mask); |
63ae0915 RH |
1977 | tcg_gen_extu_i32_tl(t_ra, t0); |
1978 | tcg_temp_free_i32(t0); | |
2e11b15d RH |
1979 | } else { |
1980 | #if defined(TARGET_PPC64) | |
1981 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
1982 | tcg_gen_rotli_i64(t_ra, t_ra, sh); | |
1983 | tcg_gen_andi_i64(t_ra, t_ra, mask); | |
1984 | #else | |
1985 | g_assert_not_reached(); | |
1986 | #endif | |
63ae0915 RH |
1987 | } |
1988 | } | |
1989 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
1990 | gen_set_Rc0(ctx, t_ra); | |
d03ef511 | 1991 | } |
79aceca5 | 1992 | } |
99e300ef | 1993 | |
54623277 | 1994 | /* rlwnm & rlwnm. */ |
99e300ef | 1995 | static void gen_rlwnm(DisasContext *ctx) |
79aceca5 | 1996 | { |
63ae0915 RH |
1997 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1998 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
1999 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
2000 | uint32_t mb = MB(ctx->opcode); | |
2001 | uint32_t me = ME(ctx->opcode); | |
2e11b15d | 2002 | target_ulong mask; |
57fca134 | 2003 | |
54843a58 | 2004 | #if defined(TARGET_PPC64) |
63ae0915 RH |
2005 | mb += 32; |
2006 | me += 32; | |
54843a58 | 2007 | #endif |
2e11b15d RH |
2008 | mask = MASK(mb, me); |
2009 | ||
2010 | if (mask <= 0xffffffffu) { | |
2011 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
2012 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
2013 | tcg_gen_trunc_tl_i32(t0, t_rb); | |
2014 | tcg_gen_trunc_tl_i32(t1, t_rs); | |
2015 | tcg_gen_andi_i32(t0, t0, 0x1f); | |
2016 | tcg_gen_rotl_i32(t1, t1, t0); | |
2017 | tcg_gen_extu_i32_tl(t_ra, t1); | |
2018 | tcg_temp_free_i32(t0); | |
2019 | tcg_temp_free_i32(t1); | |
2020 | } else { | |
2021 | #if defined(TARGET_PPC64) | |
2022 | TCGv_i64 t0 = tcg_temp_new_i64(); | |
2023 | tcg_gen_andi_i64(t0, t_rb, 0x1f); | |
2024 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); | |
2025 | tcg_gen_rotl_i64(t_ra, t_ra, t0); | |
2026 | tcg_temp_free_i64(t0); | |
2027 | #else | |
2028 | g_assert_not_reached(); | |
2029 | #endif | |
2030 | } | |
57fca134 | 2031 | |
2e11b15d | 2032 | tcg_gen_andi_tl(t_ra, t_ra, mask); |
63ae0915 RH |
2033 | |
2034 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2035 | gen_set_Rc0(ctx, t_ra); | |
79aceca5 | 2036 | } |
79aceca5 FB |
2037 | } |
2038 | ||
d9bce9d9 JM |
2039 | #if defined(TARGET_PPC64) |
2040 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
e8eaa2c0 | 2041 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2042 | { \ |
2043 | gen_##name(ctx, 0); \ | |
2044 | } \ | |
e8eaa2c0 BS |
2045 | \ |
2046 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2047 | { \ |
2048 | gen_##name(ctx, 1); \ | |
2049 | } | |
2050 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
e8eaa2c0 | 2051 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
d9bce9d9 JM |
2052 | { \ |
2053 | gen_##name(ctx, 0, 0); \ | |
2054 | } \ | |
e8eaa2c0 BS |
2055 | \ |
2056 | static void glue(gen_, name##1)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2057 | { \ |
2058 | gen_##name(ctx, 0, 1); \ | |
2059 | } \ | |
e8eaa2c0 BS |
2060 | \ |
2061 | static void glue(gen_, name##2)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2062 | { \ |
2063 | gen_##name(ctx, 1, 0); \ | |
2064 | } \ | |
e8eaa2c0 BS |
2065 | \ |
2066 | static void glue(gen_, name##3)(DisasContext *ctx) \ | |
d9bce9d9 JM |
2067 | { \ |
2068 | gen_##name(ctx, 1, 1); \ | |
2069 | } | |
51789c41 | 2070 | |
a7b2c8b9 | 2071 | static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) |
51789c41 | 2072 | { |
a7b2c8b9 RH |
2073 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2074 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2075 | ||
2076 | if (sh != 0 && mb == 0 && me == (63 - sh)) { | |
2077 | tcg_gen_shli_tl(t_ra, t_rs, sh); | |
2078 | } else if (sh != 0 && me == 63 && sh == (64 - mb)) { | |
2079 | tcg_gen_shri_tl(t_ra, t_rs, mb); | |
d03ef511 | 2080 | } else { |
a7b2c8b9 RH |
2081 | tcg_gen_rotli_tl(t_ra, t_rs, sh); |
2082 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2083 | } | |
2084 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2085 | gen_set_Rc0(ctx, t_ra); | |
51789c41 | 2086 | } |
51789c41 | 2087 | } |
a7b2c8b9 | 2088 | |
d9bce9d9 | 2089 | /* rldicl - rldicl. */ |
636aa200 | 2090 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2091 | { |
51789c41 | 2092 | uint32_t sh, mb; |
d9bce9d9 | 2093 | |
9d53c753 JM |
2094 | sh = SH(ctx->opcode) | (shn << 5); |
2095 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 | 2096 | gen_rldinm(ctx, mb, 63, sh); |
d9bce9d9 | 2097 | } |
51789c41 | 2098 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
a7b2c8b9 | 2099 | |
d9bce9d9 | 2100 | /* rldicr - rldicr. */ |
636aa200 | 2101 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
d9bce9d9 | 2102 | { |
51789c41 | 2103 | uint32_t sh, me; |
d9bce9d9 | 2104 | |
9d53c753 JM |
2105 | sh = SH(ctx->opcode) | (shn << 5); |
2106 | me = MB(ctx->opcode) | (men << 5); | |
51789c41 | 2107 | gen_rldinm(ctx, 0, me, sh); |
d9bce9d9 | 2108 | } |
51789c41 | 2109 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
a7b2c8b9 | 2110 | |
d9bce9d9 | 2111 | /* rldic - rldic. */ |
636aa200 | 2112 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2113 | { |
51789c41 | 2114 | uint32_t sh, mb; |
d9bce9d9 | 2115 | |
9d53c753 JM |
2116 | sh = SH(ctx->opcode) | (shn << 5); |
2117 | mb = MB(ctx->opcode) | (mbn << 5); | |
51789c41 JM |
2118 | gen_rldinm(ctx, mb, 63 - sh, sh); |
2119 | } | |
2120 | GEN_PPC64_R4(rldic, 0x1E, 0x04); | |
2121 | ||
a7b2c8b9 | 2122 | static void gen_rldnm(DisasContext *ctx, int mb, int me) |
51789c41 | 2123 | { |
a7b2c8b9 RH |
2124 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2125 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2126 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; | |
54843a58 | 2127 | TCGv t0; |
d03ef511 | 2128 | |
a7812ae4 | 2129 | t0 = tcg_temp_new(); |
a7b2c8b9 RH |
2130 | tcg_gen_andi_tl(t0, t_rb, 0x3f); |
2131 | tcg_gen_rotl_tl(t_ra, t_rs, t0); | |
54843a58 | 2132 | tcg_temp_free(t0); |
a7b2c8b9 RH |
2133 | |
2134 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); | |
2135 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2136 | gen_set_Rc0(ctx, t_ra); | |
2137 | } | |
d9bce9d9 | 2138 | } |
51789c41 | 2139 | |
d9bce9d9 | 2140 | /* rldcl - rldcl. */ |
636aa200 | 2141 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
d9bce9d9 | 2142 | { |
51789c41 | 2143 | uint32_t mb; |
d9bce9d9 | 2144 | |
9d53c753 | 2145 | mb = MB(ctx->opcode) | (mbn << 5); |
51789c41 | 2146 | gen_rldnm(ctx, mb, 63); |
d9bce9d9 | 2147 | } |
36081602 | 2148 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
a7b2c8b9 | 2149 | |
d9bce9d9 | 2150 | /* rldcr - rldcr. */ |
636aa200 | 2151 | static inline void gen_rldcr(DisasContext *ctx, int men) |
d9bce9d9 | 2152 | { |
51789c41 | 2153 | uint32_t me; |
d9bce9d9 | 2154 | |
9d53c753 | 2155 | me = MB(ctx->opcode) | (men << 5); |
51789c41 | 2156 | gen_rldnm(ctx, 0, me); |
d9bce9d9 | 2157 | } |
36081602 | 2158 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
a7b2c8b9 | 2159 | |
d9bce9d9 | 2160 | /* rldimi - rldimi. */ |
a7b2c8b9 | 2161 | static void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
d9bce9d9 | 2162 | { |
a7b2c8b9 RH |
2163 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2164 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; | |
2165 | uint32_t sh = SH(ctx->opcode) | (shn << 5); | |
2166 | uint32_t mb = MB(ctx->opcode) | (mbn << 5); | |
2167 | uint32_t me = 63 - sh; | |
d9bce9d9 | 2168 | |
a7b2c8b9 RH |
2169 | if (mb <= me) { |
2170 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); | |
d03ef511 | 2171 | } else { |
a7b2c8b9 RH |
2172 | target_ulong mask = MASK(mb, me); |
2173 | TCGv t1 = tcg_temp_new(); | |
d03ef511 | 2174 | |
a7b2c8b9 RH |
2175 | tcg_gen_rotli_tl(t1, t_rs, sh); |
2176 | tcg_gen_andi_tl(t1, t1, mask); | |
2177 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); | |
2178 | tcg_gen_or_tl(t_ra, t_ra, t1); | |
d03ef511 | 2179 | tcg_temp_free(t1); |
51789c41 | 2180 | } |
a7b2c8b9 RH |
2181 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2182 | gen_set_Rc0(ctx, t_ra); | |
2183 | } | |
d9bce9d9 | 2184 | } |
36081602 | 2185 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
d9bce9d9 JM |
2186 | #endif |
2187 | ||
79aceca5 | 2188 | /*** Integer shift ***/ |
99e300ef | 2189 | |
54623277 | 2190 | /* slw & slw. */ |
99e300ef | 2191 | static void gen_slw(DisasContext *ctx) |
26d67362 | 2192 | { |
7fd6bf7d | 2193 | TCGv t0, t1; |
26d67362 | 2194 | |
7fd6bf7d AJ |
2195 | t0 = tcg_temp_new(); |
2196 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2197 | #if defined(TARGET_PPC64) | |
2198 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2199 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2200 | #else | |
2201 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2202 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2203 | #endif | |
2204 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2205 | t1 = tcg_temp_new(); | |
2206 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); | |
2207 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2208 | tcg_temp_free(t1); | |
fea0c503 | 2209 | tcg_temp_free(t0); |
7fd6bf7d | 2210 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
26d67362 AJ |
2211 | if (unlikely(Rc(ctx->opcode) != 0)) |
2212 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2213 | } | |
99e300ef | 2214 | |
54623277 | 2215 | /* sraw & sraw. */ |
99e300ef | 2216 | static void gen_sraw(DisasContext *ctx) |
26d67362 | 2217 | { |
d15f74fb | 2218 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2219 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2220 | if (unlikely(Rc(ctx->opcode) != 0)) |
2221 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2222 | } | |
99e300ef | 2223 | |
54623277 | 2224 | /* srawi & srawi. */ |
99e300ef | 2225 | static void gen_srawi(DisasContext *ctx) |
79aceca5 | 2226 | { |
26d67362 | 2227 | int sh = SH(ctx->opcode); |
ba4af3e4 RH |
2228 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2229 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2230 | if (sh == 0) { | |
34a0fad1 | 2231 | tcg_gen_ext32s_tl(dst, src); |
da91a00f | 2232 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 2233 | } else { |
ba4af3e4 RH |
2234 | TCGv t0; |
2235 | tcg_gen_ext32s_tl(dst, src); | |
2236 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); | |
2237 | t0 = tcg_temp_new(); | |
2238 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); | |
2239 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2240 | tcg_temp_free(t0); | |
2241 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
2242 | tcg_gen_sari_tl(dst, dst, sh); | |
2243 | } | |
2244 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2245 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2246 | } |
79aceca5 | 2247 | } |
99e300ef | 2248 | |
54623277 | 2249 | /* srw & srw. */ |
99e300ef | 2250 | static void gen_srw(DisasContext *ctx) |
26d67362 | 2251 | { |
fea0c503 | 2252 | TCGv t0, t1; |
d9bce9d9 | 2253 | |
7fd6bf7d AJ |
2254 | t0 = tcg_temp_new(); |
2255 | /* AND rS with a mask that is 0 when rB >= 0x20 */ | |
2256 | #if defined(TARGET_PPC64) | |
2257 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); | |
2258 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2259 | #else | |
2260 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); | |
2261 | tcg_gen_sari_tl(t0, t0, 0x1f); | |
2262 | #endif | |
2263 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2264 | tcg_gen_ext32u_tl(t0, t0); | |
a7812ae4 | 2265 | t1 = tcg_temp_new(); |
7fd6bf7d AJ |
2266 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
2267 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
fea0c503 | 2268 | tcg_temp_free(t1); |
fea0c503 | 2269 | tcg_temp_free(t0); |
26d67362 AJ |
2270 | if (unlikely(Rc(ctx->opcode) != 0)) |
2271 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2272 | } | |
54623277 | 2273 | |
d9bce9d9 JM |
2274 | #if defined(TARGET_PPC64) |
2275 | /* sld & sld. */ | |
99e300ef | 2276 | static void gen_sld(DisasContext *ctx) |
26d67362 | 2277 | { |
7fd6bf7d | 2278 | TCGv t0, t1; |
26d67362 | 2279 | |
7fd6bf7d AJ |
2280 | t0 = tcg_temp_new(); |
2281 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2282 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2283 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2284 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2285 | t1 = tcg_temp_new(); | |
2286 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2287 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2288 | tcg_temp_free(t1); | |
fea0c503 | 2289 | tcg_temp_free(t0); |
26d67362 AJ |
2290 | if (unlikely(Rc(ctx->opcode) != 0)) |
2291 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2292 | } | |
99e300ef | 2293 | |
54623277 | 2294 | /* srad & srad. */ |
99e300ef | 2295 | static void gen_srad(DisasContext *ctx) |
26d67362 | 2296 | { |
d15f74fb | 2297 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
a7812ae4 | 2298 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
26d67362 AJ |
2299 | if (unlikely(Rc(ctx->opcode) != 0)) |
2300 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2301 | } | |
d9bce9d9 | 2302 | /* sradi & sradi. */ |
636aa200 | 2303 | static inline void gen_sradi(DisasContext *ctx, int n) |
d9bce9d9 | 2304 | { |
26d67362 | 2305 | int sh = SH(ctx->opcode) + (n << 5); |
ba4af3e4 RH |
2306 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2307 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2308 | if (sh == 0) { | |
2309 | tcg_gen_mov_tl(dst, src); | |
da91a00f | 2310 | tcg_gen_movi_tl(cpu_ca, 0); |
26d67362 | 2311 | } else { |
ba4af3e4 RH |
2312 | TCGv t0; |
2313 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); | |
2314 | t0 = tcg_temp_new(); | |
2315 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); | |
2316 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); | |
2317 | tcg_temp_free(t0); | |
2318 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); | |
2319 | tcg_gen_sari_tl(dst, src, sh); | |
2320 | } | |
2321 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2322 | gen_set_Rc0(ctx, dst); | |
d9bce9d9 | 2323 | } |
d9bce9d9 | 2324 | } |
e8eaa2c0 BS |
2325 | |
2326 | static void gen_sradi0(DisasContext *ctx) | |
d9bce9d9 JM |
2327 | { |
2328 | gen_sradi(ctx, 0); | |
2329 | } | |
e8eaa2c0 BS |
2330 | |
2331 | static void gen_sradi1(DisasContext *ctx) | |
d9bce9d9 JM |
2332 | { |
2333 | gen_sradi(ctx, 1); | |
2334 | } | |
99e300ef | 2335 | |
787bbe37 ND |
2336 | /* extswsli & extswsli. */ |
2337 | static inline void gen_extswsli(DisasContext *ctx, int n) | |
2338 | { | |
2339 | int sh = SH(ctx->opcode) + (n << 5); | |
2340 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; | |
2341 | TCGv src = cpu_gpr[rS(ctx->opcode)]; | |
2342 | ||
2343 | tcg_gen_ext32s_tl(dst, src); | |
2344 | tcg_gen_shli_tl(dst, dst, sh); | |
2345 | if (unlikely(Rc(ctx->opcode) != 0)) { | |
2346 | gen_set_Rc0(ctx, dst); | |
2347 | } | |
2348 | } | |
2349 | ||
2350 | static void gen_extswsli0(DisasContext *ctx) | |
2351 | { | |
2352 | gen_extswsli(ctx, 0); | |
2353 | } | |
2354 | ||
2355 | static void gen_extswsli1(DisasContext *ctx) | |
2356 | { | |
2357 | gen_extswsli(ctx, 1); | |
2358 | } | |
2359 | ||
54623277 | 2360 | /* srd & srd. */ |
99e300ef | 2361 | static void gen_srd(DisasContext *ctx) |
26d67362 | 2362 | { |
7fd6bf7d | 2363 | TCGv t0, t1; |
26d67362 | 2364 | |
7fd6bf7d AJ |
2365 | t0 = tcg_temp_new(); |
2366 | /* AND rS with a mask that is 0 when rB >= 0x40 */ | |
2367 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); | |
2368 | tcg_gen_sari_tl(t0, t0, 0x3f); | |
2369 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
2370 | t1 = tcg_temp_new(); | |
2371 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); | |
2372 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
2373 | tcg_temp_free(t1); | |
fea0c503 | 2374 | tcg_temp_free(t0); |
26d67362 AJ |
2375 | if (unlikely(Rc(ctx->opcode) != 0)) |
2376 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); | |
2377 | } | |
d9bce9d9 | 2378 | #endif |
79aceca5 | 2379 | |
76a66253 JM |
2380 | /*** Addressing modes ***/ |
2381 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ | |
636aa200 BS |
2382 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2383 | target_long maskl) | |
76a66253 JM |
2384 | { |
2385 | target_long simm = SIMM(ctx->opcode); | |
2386 | ||
be147d08 | 2387 | simm &= ~maskl; |
76db3ba4 | 2388 | if (rA(ctx->opcode) == 0) { |
c791fe84 RH |
2389 | if (NARROW_MODE(ctx)) { |
2390 | simm = (uint32_t)simm; | |
2391 | } | |
e2be8d8d | 2392 | tcg_gen_movi_tl(EA, simm); |
76db3ba4 | 2393 | } else if (likely(simm != 0)) { |
e2be8d8d | 2394 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
c791fe84 | 2395 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2396 | tcg_gen_ext32u_tl(EA, EA); |
2397 | } | |
76db3ba4 | 2398 | } else { |
c791fe84 | 2399 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2400 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
c791fe84 RH |
2401 | } else { |
2402 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
2403 | } | |
76db3ba4 | 2404 | } |
76a66253 JM |
2405 | } |
2406 | ||
636aa200 | 2407 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
76a66253 | 2408 | { |
76db3ba4 | 2409 | if (rA(ctx->opcode) == 0) { |
c791fe84 | 2410 | if (NARROW_MODE(ctx)) { |
76db3ba4 | 2411 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
c791fe84 RH |
2412 | } else { |
2413 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); | |
2414 | } | |
76db3ba4 | 2415 | } else { |
e2be8d8d | 2416 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
c791fe84 | 2417 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2418 | tcg_gen_ext32u_tl(EA, EA); |
2419 | } | |
76db3ba4 | 2420 | } |
76a66253 JM |
2421 | } |
2422 | ||
636aa200 | 2423 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
76a66253 | 2424 | { |
76db3ba4 | 2425 | if (rA(ctx->opcode) == 0) { |
e2be8d8d | 2426 | tcg_gen_movi_tl(EA, 0); |
c791fe84 RH |
2427 | } else if (NARROW_MODE(ctx)) { |
2428 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); | |
76db3ba4 | 2429 | } else { |
c791fe84 | 2430 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
76db3ba4 AJ |
2431 | } |
2432 | } | |
2433 | ||
636aa200 BS |
2434 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2435 | target_long val) | |
76db3ba4 AJ |
2436 | { |
2437 | tcg_gen_addi_tl(ret, arg1, val); | |
c791fe84 | 2438 | if (NARROW_MODE(ctx)) { |
76db3ba4 AJ |
2439 | tcg_gen_ext32u_tl(ret, ret); |
2440 | } | |
76a66253 JM |
2441 | } |
2442 | ||
636aa200 | 2443 | static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask) |
cf360a32 | 2444 | { |
42a268c2 | 2445 | TCGLabel *l1 = gen_new_label(); |
cf360a32 AJ |
2446 | TCGv t0 = tcg_temp_new(); |
2447 | TCGv_i32 t1, t2; | |
cf360a32 AJ |
2448 | tcg_gen_andi_tl(t0, EA, mask); |
2449 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
2450 | t1 = tcg_const_i32(POWERPC_EXCP_ALIGN); | |
3433b732 | 2451 | t2 = tcg_const_i32(ctx->opcode & 0x03FF0000); |
573708e3 | 2452 | gen_update_nip(ctx, ctx->nip - 4); |
e5f17ac6 | 2453 | gen_helper_raise_exception_err(cpu_env, t1, t2); |
cf360a32 AJ |
2454 | tcg_temp_free_i32(t1); |
2455 | tcg_temp_free_i32(t2); | |
2456 | gen_set_label(l1); | |
2457 | tcg_temp_free(t0); | |
2458 | } | |
2459 | ||
65f2475f BH |
2460 | static inline void gen_align_no_le(DisasContext *ctx) |
2461 | { | |
2462 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, | |
2463 | (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); | |
2464 | } | |
2465 | ||
7863667f | 2466 | /*** Integer load ***/ |
09bfe50d | 2467 | #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) |
ff5f3981 | 2468 | #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) |
b61f2753 | 2469 | |
09bfe50d ND |
2470 | #define GEN_QEMU_LOAD_TL(ldop, op) \ |
2471 | static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ | |
2472 | TCGv val, \ | |
2473 | TCGv addr) \ | |
2474 | { \ | |
2475 | tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2476 | } |
2477 | ||
09bfe50d ND |
2478 | GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) |
2479 | GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) | |
2480 | GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) | |
2481 | GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) | |
2482 | GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) | |
f976b09e | 2483 | |
ff5f3981 ND |
2484 | GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) |
2485 | GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) | |
2486 | ||
09bfe50d ND |
2487 | #define GEN_QEMU_LOAD_64(ldop, op) \ |
2488 | static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ | |
2489 | TCGv_i64 val, \ | |
2490 | TCGv addr) \ | |
2491 | { \ | |
2492 | tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2493 | } |
2494 | ||
740ae9a2 ND |
2495 | GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) |
2496 | GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) | |
09bfe50d ND |
2497 | GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) |
2498 | GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) | |
4f364fe7 | 2499 | GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2500 | |
ff5f3981 ND |
2501 | #if defined(TARGET_PPC64) |
2502 | GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) | |
2503 | #endif | |
2504 | ||
761a89c6 ND |
2505 | #define GEN_QEMU_STORE_TL(stop, op) \ |
2506 | static void glue(gen_qemu_, stop)(DisasContext *ctx, \ | |
2507 | TCGv val, \ | |
2508 | TCGv addr) \ | |
2509 | { \ | |
2510 | tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2511 | } |
2512 | ||
761a89c6 ND |
2513 | GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) |
2514 | GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) | |
2515 | GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) | |
b61f2753 | 2516 | |
804108aa ND |
2517 | GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) |
2518 | GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) | |
2519 | ||
761a89c6 ND |
2520 | #define GEN_QEMU_STORE_64(stop, op) \ |
2521 | static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ | |
2522 | TCGv_i64 val, \ | |
2523 | TCGv addr) \ | |
2524 | { \ | |
2525 | tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ | |
b61f2753 AJ |
2526 | } |
2527 | ||
ddb9ac50 ND |
2528 | GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) |
2529 | GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) | |
761a89c6 | 2530 | GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) |
2468f23d | 2531 | GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) |
b61f2753 | 2532 | |
804108aa ND |
2533 | #if defined(TARGET_PPC64) |
2534 | GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) | |
2535 | #endif | |
2536 | ||
0c8aacd4 | 2537 | #define GEN_LD(name, ldop, opc, type) \ |
99e300ef | 2538 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2539 | { \ |
76db3ba4 AJ |
2540 | TCGv EA; \ |
2541 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2542 | EA = tcg_temp_new(); \ | |
2543 | gen_addr_imm_index(ctx, EA, 0); \ | |
2544 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2545 | tcg_temp_free(EA); \ |
79aceca5 FB |
2546 | } |
2547 | ||
0c8aacd4 | 2548 | #define GEN_LDU(name, ldop, opc, type) \ |
99e300ef | 2549 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
79aceca5 | 2550 | { \ |
b61f2753 | 2551 | TCGv EA; \ |
76a66253 JM |
2552 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2553 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2554 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2555 | return; \ |
9a64fbe4 | 2556 | } \ |
76db3ba4 | 2557 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2558 | EA = tcg_temp_new(); \ |
9d53c753 | 2559 | if (type == PPC_64B) \ |
76db3ba4 | 2560 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2561 | else \ |
76db3ba4 AJ |
2562 | gen_addr_imm_index(ctx, EA, 0); \ |
2563 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2564 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2565 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2566 | } |
2567 | ||
0c8aacd4 | 2568 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
99e300ef | 2569 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2570 | { \ |
b61f2753 | 2571 | TCGv EA; \ |
76a66253 JM |
2572 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2573 | rA(ctx->opcode) == rD(ctx->opcode))) { \ | |
e06fcd75 | 2574 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2575 | return; \ |
9a64fbe4 | 2576 | } \ |
76db3ba4 | 2577 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2578 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2579 | gen_addr_reg_index(ctx, EA); \ |
2580 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2581 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2582 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2583 | } |
2584 | ||
b7815375 | 2585 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
99e300ef | 2586 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2587 | { \ |
76db3ba4 | 2588 | TCGv EA; \ |
b7815375 | 2589 | chk; \ |
76db3ba4 AJ |
2590 | gen_set_access_type(ctx, ACCESS_INT); \ |
2591 | EA = tcg_temp_new(); \ | |
2592 | gen_addr_reg_index(ctx, EA); \ | |
2593 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ | |
b61f2753 | 2594 | tcg_temp_free(EA); \ |
79aceca5 | 2595 | } |
b7815375 | 2596 | |
cd6e9320 | 2597 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
b7815375 BH |
2598 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2599 | ||
2600 | #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ | |
2601 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2602 | |
0c8aacd4 AJ |
2603 | #define GEN_LDS(name, ldop, op, type) \ |
2604 | GEN_LD(name, ldop, op | 0x20, type); \ | |
2605 | GEN_LDU(name, ldop, op | 0x21, type); \ | |
2606 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ | |
2607 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2608 | |
2609 | /* lbz lbzu lbzux lbzx */ | |
0c8aacd4 | 2610 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
79aceca5 | 2611 | /* lha lhau lhaux lhax */ |
0c8aacd4 | 2612 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
79aceca5 | 2613 | /* lhz lhzu lhzux lhzx */ |
0c8aacd4 | 2614 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
79aceca5 | 2615 | /* lwz lwzu lwzux lwzx */ |
0c8aacd4 | 2616 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
d9bce9d9 | 2617 | #if defined(TARGET_PPC64) |
d9bce9d9 | 2618 | /* lwaux */ |
0c8aacd4 | 2619 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
d9bce9d9 | 2620 | /* lwax */ |
0c8aacd4 | 2621 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
d9bce9d9 | 2622 | /* ldux */ |
4f364fe7 | 2623 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); |
d9bce9d9 | 2624 | /* ldx */ |
4f364fe7 | 2625 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); |
99e300ef | 2626 | |
b7815375 | 2627 | /* CI load/store variants */ |
4f364fe7 | 2628 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
2629 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) |
2630 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
2631 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
2632 | ||
99e300ef | 2633 | static void gen_ld(DisasContext *ctx) |
d9bce9d9 | 2634 | { |
b61f2753 | 2635 | TCGv EA; |
d9bce9d9 JM |
2636 | if (Rc(ctx->opcode)) { |
2637 | if (unlikely(rA(ctx->opcode) == 0 || | |
2638 | rA(ctx->opcode) == rD(ctx->opcode))) { | |
e06fcd75 | 2639 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
d9bce9d9 JM |
2640 | return; |
2641 | } | |
2642 | } | |
76db3ba4 | 2643 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2644 | EA = tcg_temp_new(); |
76db3ba4 | 2645 | gen_addr_imm_index(ctx, EA, 0x03); |
d9bce9d9 JM |
2646 | if (ctx->opcode & 0x02) { |
2647 | /* lwa (lwau is undefined) */ | |
76db3ba4 | 2648 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 JM |
2649 | } else { |
2650 | /* ld - ldu */ | |
4f364fe7 | 2651 | gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
d9bce9d9 | 2652 | } |
d9bce9d9 | 2653 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2654 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2655 | tcg_temp_free(EA); | |
d9bce9d9 | 2656 | } |
99e300ef | 2657 | |
54623277 | 2658 | /* lq */ |
99e300ef | 2659 | static void gen_lq(DisasContext *ctx) |
be147d08 | 2660 | { |
be147d08 | 2661 | int ra, rd; |
b61f2753 | 2662 | TCGv EA; |
be147d08 | 2663 | |
e0498daa TM |
2664 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2665 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2666 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2667 | ||
c47493f2 | 2668 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2669 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2670 | return; |
2671 | } | |
e0498daa TM |
2672 | |
2673 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2674 | gen_align_no_le(ctx); |
e0498daa TM |
2675 | return; |
2676 | } | |
be147d08 JM |
2677 | ra = rA(ctx->opcode); |
2678 | rd = rD(ctx->opcode); | |
2679 | if (unlikely((rd & 1) || rd == ra)) { | |
e06fcd75 | 2680 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2681 | return; |
2682 | } | |
e0498daa | 2683 | |
76db3ba4 | 2684 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2685 | EA = tcg_temp_new(); |
76db3ba4 | 2686 | gen_addr_imm_index(ctx, EA, 0x0F); |
e0498daa | 2687 | |
4f364fe7 ND |
2688 | /* We only need to swap high and low halves. gen_qemu_ld64_i64 does |
2689 | necessary 64-bit byteswap already. */ | |
e0498daa | 2690 | if (unlikely(ctx->le_mode)) { |
4f364fe7 | 2691 | gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); |
e0498daa | 2692 | gen_addr_add(ctx, EA, EA, 8); |
4f364fe7 | 2693 | gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); |
e0498daa | 2694 | } else { |
4f364fe7 | 2695 | gen_qemu_ld64_i64(ctx, cpu_gpr[rd], EA); |
e0498daa | 2696 | gen_addr_add(ctx, EA, EA, 8); |
4f364fe7 | 2697 | gen_qemu_ld64_i64(ctx, cpu_gpr[rd + 1], EA); |
e0498daa | 2698 | } |
b61f2753 | 2699 | tcg_temp_free(EA); |
be147d08 | 2700 | } |
d9bce9d9 | 2701 | #endif |
79aceca5 FB |
2702 | |
2703 | /*** Integer store ***/ | |
0c8aacd4 | 2704 | #define GEN_ST(name, stop, opc, type) \ |
99e300ef | 2705 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 2706 | { \ |
76db3ba4 AJ |
2707 | TCGv EA; \ |
2708 | gen_set_access_type(ctx, ACCESS_INT); \ | |
2709 | EA = tcg_temp_new(); \ | |
2710 | gen_addr_imm_index(ctx, EA, 0); \ | |
2711 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2712 | tcg_temp_free(EA); \ |
79aceca5 FB |
2713 | } |
2714 | ||
0c8aacd4 | 2715 | #define GEN_STU(name, stop, opc, type) \ |
99e300ef | 2716 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
79aceca5 | 2717 | { \ |
b61f2753 | 2718 | TCGv EA; \ |
76a66253 | 2719 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2720 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2721 | return; \ |
9a64fbe4 | 2722 | } \ |
76db3ba4 | 2723 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2724 | EA = tcg_temp_new(); \ |
9d53c753 | 2725 | if (type == PPC_64B) \ |
76db3ba4 | 2726 | gen_addr_imm_index(ctx, EA, 0x03); \ |
9d53c753 | 2727 | else \ |
76db3ba4 AJ |
2728 | gen_addr_imm_index(ctx, EA, 0); \ |
2729 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2730 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2731 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2732 | } |
2733 | ||
0c8aacd4 | 2734 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
99e300ef | 2735 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
79aceca5 | 2736 | { \ |
b61f2753 | 2737 | TCGv EA; \ |
76a66253 | 2738 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
e06fcd75 | 2739 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
9fddaa0c | 2740 | return; \ |
9a64fbe4 | 2741 | } \ |
76db3ba4 | 2742 | gen_set_access_type(ctx, ACCESS_INT); \ |
0c8aacd4 | 2743 | EA = tcg_temp_new(); \ |
76db3ba4 AJ |
2744 | gen_addr_reg_index(ctx, EA); \ |
2745 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 AJ |
2746 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2747 | tcg_temp_free(EA); \ | |
79aceca5 FB |
2748 | } |
2749 | ||
b7815375 | 2750 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 2751 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
79aceca5 | 2752 | { \ |
76db3ba4 | 2753 | TCGv EA; \ |
b7815375 | 2754 | chk; \ |
76db3ba4 AJ |
2755 | gen_set_access_type(ctx, ACCESS_INT); \ |
2756 | EA = tcg_temp_new(); \ | |
2757 | gen_addr_reg_index(ctx, EA); \ | |
2758 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ | |
b61f2753 | 2759 | tcg_temp_free(EA); \ |
79aceca5 | 2760 | } |
cd6e9320 | 2761 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
b7815375 BH |
2762 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2763 | ||
2764 | #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ | |
2765 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) | |
79aceca5 | 2766 | |
0c8aacd4 AJ |
2767 | #define GEN_STS(name, stop, op, type) \ |
2768 | GEN_ST(name, stop, op | 0x20, type); \ | |
2769 | GEN_STU(name, stop, op | 0x21, type); \ | |
2770 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ | |
2771 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
79aceca5 FB |
2772 | |
2773 | /* stb stbu stbux stbx */ | |
0c8aacd4 | 2774 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
79aceca5 | 2775 | /* sth sthu sthux sthx */ |
0c8aacd4 | 2776 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
79aceca5 | 2777 | /* stw stwu stwux stwx */ |
0c8aacd4 | 2778 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
d9bce9d9 | 2779 | #if defined(TARGET_PPC64) |
2468f23d ND |
2780 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); |
2781 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); | |
2782 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) | |
b7815375 BH |
2783 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
2784 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
2785 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
99e300ef BS |
2786 | |
2787 | static void gen_std(DisasContext *ctx) | |
d9bce9d9 | 2788 | { |
be147d08 | 2789 | int rs; |
b61f2753 | 2790 | TCGv EA; |
be147d08 JM |
2791 | |
2792 | rs = rS(ctx->opcode); | |
84cab1e2 | 2793 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
84cab1e2 TM |
2794 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2795 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; | |
2796 | ||
dfdd3e43 BH |
2797 | if (!(ctx->insns_flags & PPC_64BX)) { |
2798 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
2799 | } | |
2800 | ||
c47493f2 | 2801 | if (!legal_in_user_mode && ctx->pr) { |
9b2fadda | 2802 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
be147d08 JM |
2803 | return; |
2804 | } | |
84cab1e2 TM |
2805 | |
2806 | if (!le_is_supported && ctx->le_mode) { | |
65f2475f | 2807 | gen_align_no_le(ctx); |
d9bce9d9 JM |
2808 | return; |
2809 | } | |
84cab1e2 TM |
2810 | |
2811 | if (unlikely(rs & 1)) { | |
2812 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
be147d08 JM |
2813 | return; |
2814 | } | |
76db3ba4 | 2815 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2816 | EA = tcg_temp_new(); |
76db3ba4 | 2817 | gen_addr_imm_index(ctx, EA, 0x03); |
84cab1e2 | 2818 | |
2468f23d | 2819 | /* We only need to swap high and low halves. gen_qemu_st64_i64 does |
e22c357b | 2820 | necessary 64-bit byteswap already. */ |
84cab1e2 | 2821 | if (unlikely(ctx->le_mode)) { |
2468f23d | 2822 | gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); |
84cab1e2 | 2823 | gen_addr_add(ctx, EA, EA, 8); |
2468f23d | 2824 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
84cab1e2 | 2825 | } else { |
2468f23d | 2826 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
84cab1e2 | 2827 | gen_addr_add(ctx, EA, EA, 8); |
2468f23d | 2828 | gen_qemu_st64_i64(ctx, cpu_gpr[rs + 1], EA); |
84cab1e2 | 2829 | } |
b61f2753 | 2830 | tcg_temp_free(EA); |
be147d08 | 2831 | } else { |
84cab1e2 | 2832 | /* std / stdu*/ |
be147d08 JM |
2833 | if (Rc(ctx->opcode)) { |
2834 | if (unlikely(rA(ctx->opcode) == 0)) { | |
e06fcd75 | 2835 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
be147d08 JM |
2836 | return; |
2837 | } | |
2838 | } | |
76db3ba4 | 2839 | gen_set_access_type(ctx, ACCESS_INT); |
a7812ae4 | 2840 | EA = tcg_temp_new(); |
76db3ba4 | 2841 | gen_addr_imm_index(ctx, EA, 0x03); |
2468f23d | 2842 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
be147d08 | 2843 | if (Rc(ctx->opcode)) |
b61f2753 AJ |
2844 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2845 | tcg_temp_free(EA); | |
d9bce9d9 | 2846 | } |
d9bce9d9 JM |
2847 | } |
2848 | #endif | |
79aceca5 | 2849 | /*** Integer load and store with byte reverse ***/ |
e22c357b | 2850 | |
79aceca5 | 2851 | /* lhbrx */ |
0c8aacd4 | 2852 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
b61f2753 | 2853 | |
79aceca5 | 2854 | /* lwbrx */ |
0c8aacd4 | 2855 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
b61f2753 | 2856 | |
cd6e9320 TH |
2857 | #if defined(TARGET_PPC64) |
2858 | /* ldbrx */ | |
ff5f3981 | 2859 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); |
804108aa ND |
2860 | /* stdbrx */ |
2861 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); | |
cd6e9320 TH |
2862 | #endif /* TARGET_PPC64 */ |
2863 | ||
79aceca5 | 2864 | /* sthbrx */ |
0c8aacd4 | 2865 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
79aceca5 | 2866 | /* stwbrx */ |
0c8aacd4 | 2867 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
79aceca5 FB |
2868 | |
2869 | /*** Integer load and store multiple ***/ | |
99e300ef | 2870 | |
54623277 | 2871 | /* lmw */ |
99e300ef | 2872 | static void gen_lmw(DisasContext *ctx) |
79aceca5 | 2873 | { |
76db3ba4 AJ |
2874 | TCGv t0; |
2875 | TCGv_i32 t1; | |
5817355e BH |
2876 | |
2877 | if (ctx->le_mode) { | |
2878 | gen_align_no_le(ctx); | |
2879 | return; | |
2880 | } | |
76db3ba4 | 2881 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2882 | t0 = tcg_temp_new(); |
2883 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2884 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2885 | gen_helper_lmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2886 | tcg_temp_free(t0); |
2887 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2888 | } |
2889 | ||
2890 | /* stmw */ | |
99e300ef | 2891 | static void gen_stmw(DisasContext *ctx) |
79aceca5 | 2892 | { |
76db3ba4 AJ |
2893 | TCGv t0; |
2894 | TCGv_i32 t1; | |
5817355e BH |
2895 | |
2896 | if (ctx->le_mode) { | |
2897 | gen_align_no_le(ctx); | |
2898 | return; | |
2899 | } | |
76db3ba4 | 2900 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2901 | t0 = tcg_temp_new(); |
2902 | t1 = tcg_const_i32(rS(ctx->opcode)); | |
2903 | gen_addr_imm_index(ctx, t0, 0); | |
2f5a189c | 2904 | gen_helper_stmw(cpu_env, t0, t1); |
ff4a62cd AJ |
2905 | tcg_temp_free(t0); |
2906 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
2907 | } |
2908 | ||
2909 | /*** Integer load and store strings ***/ | |
54623277 | 2910 | |
79aceca5 | 2911 | /* lswi */ |
3fc6c082 | 2912 | /* PowerPC32 specification says we must generate an exception if |
9a64fbe4 FB |
2913 | * rA is in the range of registers to be loaded. |
2914 | * In an other hand, IBM says this is valid, but rA won't be loaded. | |
2915 | * For now, I'll follow the spec... | |
2916 | */ | |
99e300ef | 2917 | static void gen_lswi(DisasContext *ctx) |
79aceca5 | 2918 | { |
dfbc799d AJ |
2919 | TCGv t0; |
2920 | TCGv_i32 t1, t2; | |
79aceca5 FB |
2921 | int nb = NB(ctx->opcode); |
2922 | int start = rD(ctx->opcode); | |
9a64fbe4 | 2923 | int ra = rA(ctx->opcode); |
79aceca5 FB |
2924 | int nr; |
2925 | ||
5817355e BH |
2926 | if (ctx->le_mode) { |
2927 | gen_align_no_le(ctx); | |
2928 | return; | |
2929 | } | |
79aceca5 FB |
2930 | if (nb == 0) |
2931 | nb = 32; | |
afbee712 TH |
2932 | nr = (nb + 3) / 4; |
2933 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { | |
e06fcd75 | 2934 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
9fddaa0c | 2935 | return; |
297d8e62 | 2936 | } |
76db3ba4 | 2937 | gen_set_access_type(ctx, ACCESS_INT); |
dfbc799d | 2938 | t0 = tcg_temp_new(); |
76db3ba4 | 2939 | gen_addr_register(ctx, t0); |
dfbc799d AJ |
2940 | t1 = tcg_const_i32(nb); |
2941 | t2 = tcg_const_i32(start); | |
2f5a189c | 2942 | gen_helper_lsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2943 | tcg_temp_free(t0); |
2944 | tcg_temp_free_i32(t1); | |
2945 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2946 | } |
2947 | ||
2948 | /* lswx */ | |
99e300ef | 2949 | static void gen_lswx(DisasContext *ctx) |
79aceca5 | 2950 | { |
76db3ba4 AJ |
2951 | TCGv t0; |
2952 | TCGv_i32 t1, t2, t3; | |
5817355e BH |
2953 | |
2954 | if (ctx->le_mode) { | |
2955 | gen_align_no_le(ctx); | |
2956 | return; | |
2957 | } | |
76db3ba4 | 2958 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2959 | t0 = tcg_temp_new(); |
2960 | gen_addr_reg_index(ctx, t0); | |
2961 | t1 = tcg_const_i32(rD(ctx->opcode)); | |
2962 | t2 = tcg_const_i32(rA(ctx->opcode)); | |
2963 | t3 = tcg_const_i32(rB(ctx->opcode)); | |
2f5a189c | 2964 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
dfbc799d AJ |
2965 | tcg_temp_free(t0); |
2966 | tcg_temp_free_i32(t1); | |
2967 | tcg_temp_free_i32(t2); | |
2968 | tcg_temp_free_i32(t3); | |
79aceca5 FB |
2969 | } |
2970 | ||
2971 | /* stswi */ | |
99e300ef | 2972 | static void gen_stswi(DisasContext *ctx) |
79aceca5 | 2973 | { |
76db3ba4 AJ |
2974 | TCGv t0; |
2975 | TCGv_i32 t1, t2; | |
4b3686fa | 2976 | int nb = NB(ctx->opcode); |
5817355e BH |
2977 | |
2978 | if (ctx->le_mode) { | |
2979 | gen_align_no_le(ctx); | |
2980 | return; | |
2981 | } | |
76db3ba4 | 2982 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
2983 | t0 = tcg_temp_new(); |
2984 | gen_addr_register(ctx, t0); | |
4b3686fa FB |
2985 | if (nb == 0) |
2986 | nb = 32; | |
dfbc799d | 2987 | t1 = tcg_const_i32(nb); |
76db3ba4 | 2988 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 2989 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
2990 | tcg_temp_free(t0); |
2991 | tcg_temp_free_i32(t1); | |
2992 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
2993 | } |
2994 | ||
2995 | /* stswx */ | |
99e300ef | 2996 | static void gen_stswx(DisasContext *ctx) |
79aceca5 | 2997 | { |
76db3ba4 AJ |
2998 | TCGv t0; |
2999 | TCGv_i32 t1, t2; | |
5817355e BH |
3000 | |
3001 | if (ctx->le_mode) { | |
3002 | gen_align_no_le(ctx); | |
3003 | return; | |
3004 | } | |
76db3ba4 | 3005 | gen_set_access_type(ctx, ACCESS_INT); |
76db3ba4 AJ |
3006 | t0 = tcg_temp_new(); |
3007 | gen_addr_reg_index(ctx, t0); | |
3008 | t1 = tcg_temp_new_i32(); | |
dfbc799d AJ |
3009 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3010 | tcg_gen_andi_i32(t1, t1, 0x7F); | |
76db3ba4 | 3011 | t2 = tcg_const_i32(rS(ctx->opcode)); |
2f5a189c | 3012 | gen_helper_stsw(cpu_env, t0, t1, t2); |
dfbc799d AJ |
3013 | tcg_temp_free(t0); |
3014 | tcg_temp_free_i32(t1); | |
3015 | tcg_temp_free_i32(t2); | |
79aceca5 FB |
3016 | } |
3017 | ||
3018 | /*** Memory synchronisation ***/ | |
3019 | /* eieio */ | |
99e300ef | 3020 | static void gen_eieio(DisasContext *ctx) |
79aceca5 | 3021 | { |
79aceca5 FB |
3022 | } |
3023 | ||
c5a8d8f3 | 3024 | #if !defined(CONFIG_USER_ONLY) |
cd0c6f47 BH |
3025 | static inline void gen_check_tlb_flush(DisasContext *ctx) |
3026 | { | |
c5a8d8f3 BH |
3027 | TCGv_i32 t; |
3028 | TCGLabel *l; | |
cd0c6f47 | 3029 | |
c5a8d8f3 BH |
3030 | if (!ctx->lazy_tlb_flush) { |
3031 | return; | |
3032 | } | |
3033 | l = gen_new_label(); | |
3034 | t = tcg_temp_new_i32(); | |
cd0c6f47 BH |
3035 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
3036 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); | |
3037 | gen_helper_check_tlb_flush(cpu_env); | |
3038 | gen_set_label(l); | |
3039 | tcg_temp_free_i32(t); | |
3040 | } | |
3041 | #else | |
3042 | static inline void gen_check_tlb_flush(DisasContext *ctx) { } | |
3043 | #endif | |
3044 | ||
79aceca5 | 3045 | /* isync */ |
99e300ef | 3046 | static void gen_isync(DisasContext *ctx) |
79aceca5 | 3047 | { |
cd0c6f47 BH |
3048 | /* |
3049 | * We need to check for a pending TLB flush. This can only happen in | |
3050 | * kernel mode however so check MSR_PR | |
3051 | */ | |
3052 | if (!ctx->pr) { | |
3053 | gen_check_tlb_flush(ctx); | |
3054 | } | |
e06fcd75 | 3055 | gen_stop_exception(ctx); |
79aceca5 FB |
3056 | } |
3057 | ||
48793c95 ND |
3058 | #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) |
3059 | ||
3060 | #define LARX(name, memop) \ | |
5c77a786 TM |
3061 | static void gen_##name(DisasContext *ctx) \ |
3062 | { \ | |
3063 | TCGv t0; \ | |
3064 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \ | |
48793c95 | 3065 | int len = MEMOP_GET_SIZE(memop); \ |
5c77a786 TM |
3066 | gen_set_access_type(ctx, ACCESS_RES); \ |
3067 | t0 = tcg_temp_local_new(); \ | |
3068 | gen_addr_reg_index(ctx, t0); \ | |
3069 | if ((len) > 1) { \ | |
3070 | gen_check_align(ctx, t0, (len)-1); \ | |
3071 | } \ | |
48793c95 | 3072 | tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \ |
5c77a786 TM |
3073 | tcg_gen_mov_tl(cpu_reserve, t0); \ |
3074 | tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \ | |
3075 | tcg_temp_free(t0); \ | |
79aceca5 FB |
3076 | } |
3077 | ||
5c77a786 | 3078 | /* lwarx */ |
48793c95 ND |
3079 | LARX(lbarx, DEF_MEMOP(MO_UB)) |
3080 | LARX(lharx, DEF_MEMOP(MO_UW)) | |
3081 | LARX(lwarx, DEF_MEMOP(MO_UL)) | |
5c77a786 | 3082 | |
4425265b | 3083 | #if defined(CONFIG_USER_ONLY) |
587c51f7 | 3084 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
2391b357 | 3085 | int reg, int memop) |
4425265b NF |
3086 | { |
3087 | TCGv t0 = tcg_temp_new(); | |
4425265b | 3088 | |
1328c2bf | 3089 | tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea)); |
2391b357 | 3090 | tcg_gen_movi_tl(t0, (MEMOP_GET_SIZE(memop) << 5) | reg); |
1328c2bf | 3091 | tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info)); |
4425265b | 3092 | tcg_temp_free(t0); |
bd6fefe7 | 3093 | gen_exception_err(ctx, POWERPC_EXCP_STCX, 0); |
4425265b | 3094 | } |
4425265b | 3095 | #else |
587c51f7 | 3096 | static void gen_conditional_store(DisasContext *ctx, TCGv EA, |
2391b357 | 3097 | int reg, int memop) |
587c51f7 | 3098 | { |
42a268c2 | 3099 | TCGLabel *l1; |
4425265b | 3100 | |
587c51f7 TM |
3101 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3102 | l1 = gen_new_label(); | |
3103 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); | |
3104 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
2391b357 | 3105 | tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop); |
587c51f7 TM |
3106 | gen_set_label(l1); |
3107 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3108 | } | |
4425265b | 3109 | #endif |
587c51f7 | 3110 | |
2391b357 ND |
3111 | #define STCX(name, memop) \ |
3112 | static void gen_##name(DisasContext *ctx) \ | |
3113 | { \ | |
3114 | TCGv t0; \ | |
3115 | int len = MEMOP_GET_SIZE(memop); \ | |
3116 | gen_set_access_type(ctx, ACCESS_RES); \ | |
3117 | t0 = tcg_temp_local_new(); \ | |
3118 | gen_addr_reg_index(ctx, t0); \ | |
3119 | if (len > 1) { \ | |
3120 | gen_check_align(ctx, t0, (len) - 1); \ | |
3121 | } \ | |
3122 | gen_conditional_store(ctx, t0, rS(ctx->opcode), memop); \ | |
3123 | tcg_temp_free(t0); \ | |
3124 | } | |
3125 | ||
3126 | STCX(stbcx_, DEF_MEMOP(MO_UB)) | |
3127 | STCX(sthcx_, DEF_MEMOP(MO_UW)) | |
3128 | STCX(stwcx_, DEF_MEMOP(MO_UL)) | |
587c51f7 | 3129 | |
426613db | 3130 | #if defined(TARGET_PPC64) |
426613db | 3131 | /* ldarx */ |
48793c95 | 3132 | LARX(ldarx, DEF_MEMOP(MO_Q)) |
2391b357 ND |
3133 | /* stdcx. */ |
3134 | STCX(stdcx_, DEF_MEMOP(MO_Q)) | |
426613db | 3135 | |
9c294d5a TM |
3136 | /* lqarx */ |
3137 | static void gen_lqarx(DisasContext *ctx) | |
3138 | { | |
3139 | TCGv EA; | |
3140 | int rd = rD(ctx->opcode); | |
3141 | TCGv gpr1, gpr2; | |
3142 | ||
3143 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || | |
3144 | (rd == rB(ctx->opcode)))) { | |
3145 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3146 | return; | |
3147 | } | |
3148 | ||
3149 | gen_set_access_type(ctx, ACCESS_RES); | |
3150 | EA = tcg_temp_local_new(); | |
3151 | gen_addr_reg_index(ctx, EA); | |
3152 | gen_check_align(ctx, EA, 15); | |
3153 | if (unlikely(ctx->le_mode)) { | |
3154 | gpr1 = cpu_gpr[rd+1]; | |
3155 | gpr2 = cpu_gpr[rd]; | |
3156 | } else { | |
3157 | gpr1 = cpu_gpr[rd]; | |
3158 | gpr2 = cpu_gpr[rd+1]; | |
3159 | } | |
48793c95 | 3160 | tcg_gen_qemu_ld_i64(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); |
9c294d5a | 3161 | tcg_gen_mov_tl(cpu_reserve, EA); |
9c294d5a | 3162 | gen_addr_add(ctx, EA, EA, 8); |
48793c95 | 3163 | tcg_gen_qemu_ld_i64(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); |
9c294d5a TM |
3164 | |
3165 | tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val)); | |
3166 | tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2)); | |
9c294d5a TM |
3167 | tcg_temp_free(EA); |
3168 | } | |
3169 | ||
aa2008af ND |
3170 | /* stqcx. */ |
3171 | static void gen_stqcx_(DisasContext *ctx) | |
3172 | { | |
3173 | TCGv EA; | |
3174 | int reg = rS(ctx->opcode); | |
3175 | int len = 16; | |
3176 | #if !defined(CONFIG_USER_ONLY) | |
3177 | TCGLabel *l1; | |
3178 | TCGv gpr1, gpr2; | |
3179 | #endif | |
3180 | ||
3181 | if (unlikely((rD(ctx->opcode) & 1))) { | |
3182 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3183 | return; | |
3184 | } | |
3185 | gen_set_access_type(ctx, ACCESS_RES); | |
3186 | EA = tcg_temp_local_new(); | |
3187 | gen_addr_reg_index(ctx, EA); | |
3188 | if (len > 1) { | |
3189 | gen_check_align(ctx, EA, (len) - 1); | |
3190 | } | |
3191 | ||
3192 | #if defined(CONFIG_USER_ONLY) | |
3193 | gen_conditional_store(ctx, EA, reg, 16); | |
3194 | #else | |
3195 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
3196 | l1 = gen_new_label(); | |
3197 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1); | |
3198 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
3199 | ||
3200 | if (unlikely(ctx->le_mode)) { | |
3201 | gpr1 = cpu_gpr[reg + 1]; | |
3202 | gpr2 = cpu_gpr[reg]; | |
3203 | } else { | |
3204 | gpr1 = cpu_gpr[reg]; | |
3205 | gpr2 = cpu_gpr[reg + 1]; | |
3206 | } | |
3207 | tcg_gen_qemu_st_tl(gpr1, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); | |
3208 | gen_addr_add(ctx, EA, EA, 8); | |
3209 | tcg_gen_qemu_st_tl(gpr2, EA, ctx->mem_idx, DEF_MEMOP(MO_Q)); | |
3210 | ||
3211 | gen_set_label(l1); | |
3212 | tcg_gen_movi_tl(cpu_reserve, -1); | |
3213 | #endif | |
3214 | tcg_temp_free(EA); | |
3215 | } | |
3216 | ||
426613db JM |
3217 | #endif /* defined(TARGET_PPC64) */ |
3218 | ||
79aceca5 | 3219 | /* sync */ |
99e300ef | 3220 | static void gen_sync(DisasContext *ctx) |
79aceca5 | 3221 | { |
cd0c6f47 BH |
3222 | uint32_t l = (ctx->opcode >> 21) & 3; |
3223 | ||
3224 | /* | |
c5a8d8f3 BH |
3225 | * We may need to check for a pending TLB flush. |
3226 | * | |
3227 | * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. | |
3228 | * | |
3229 | * Additionally, this can only happen in kernel mode however so | |
3230 | * check MSR_PR as well. | |
cd0c6f47 | 3231 | */ |
c5a8d8f3 | 3232 | if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { |
cd0c6f47 BH |
3233 | gen_check_tlb_flush(ctx); |
3234 | } | |
79aceca5 FB |
3235 | } |
3236 | ||
0db1b20e | 3237 | /* wait */ |
99e300ef | 3238 | static void gen_wait(DisasContext *ctx) |
0db1b20e | 3239 | { |
35b5066e | 3240 | TCGv_i32 t0 = tcg_const_i32(1); |
259186a7 AF |
3241 | tcg_gen_st_i32(t0, cpu_env, |
3242 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); | |
931ff272 | 3243 | tcg_temp_free_i32(t0); |
0db1b20e | 3244 | /* Stop translation, as the CPU is supposed to sleep from now */ |
bd6fefe7 | 3245 | gen_exception_nip(ctx, EXCP_HLT, ctx->nip); |
0db1b20e JM |
3246 | } |
3247 | ||
7778a575 BH |
3248 | #if defined(TARGET_PPC64) |
3249 | static void gen_doze(DisasContext *ctx) | |
3250 | { | |
3251 | #if defined(CONFIG_USER_ONLY) | |
3252 | GEN_PRIV; | |
3253 | #else | |
3254 | TCGv_i32 t; | |
3255 | ||
3256 | CHK_HV; | |
3257 | t = tcg_const_i32(PPC_PM_DOZE); | |
3258 | gen_helper_pminsn(cpu_env, t); | |
3259 | tcg_temp_free_i32(t); | |
3260 | gen_stop_exception(ctx); | |
3261 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3262 | } | |
3263 | ||
3264 | static void gen_nap(DisasContext *ctx) | |
3265 | { | |
3266 | #if defined(CONFIG_USER_ONLY) | |
3267 | GEN_PRIV; | |
3268 | #else | |
3269 | TCGv_i32 t; | |
3270 | ||
3271 | CHK_HV; | |
3272 | t = tcg_const_i32(PPC_PM_NAP); | |
3273 | gen_helper_pminsn(cpu_env, t); | |
3274 | tcg_temp_free_i32(t); | |
3275 | gen_stop_exception(ctx); | |
3276 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3277 | } | |
3278 | ||
3279 | static void gen_sleep(DisasContext *ctx) | |
3280 | { | |
3281 | #if defined(CONFIG_USER_ONLY) | |
3282 | GEN_PRIV; | |
3283 | #else | |
3284 | TCGv_i32 t; | |
3285 | ||
3286 | CHK_HV; | |
3287 | t = tcg_const_i32(PPC_PM_SLEEP); | |
3288 | gen_helper_pminsn(cpu_env, t); | |
3289 | tcg_temp_free_i32(t); | |
3290 | gen_stop_exception(ctx); | |
3291 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3292 | } | |
3293 | ||
3294 | static void gen_rvwinkle(DisasContext *ctx) | |
3295 | { | |
3296 | #if defined(CONFIG_USER_ONLY) | |
3297 | GEN_PRIV; | |
3298 | #else | |
3299 | TCGv_i32 t; | |
3300 | ||
3301 | CHK_HV; | |
3302 | t = tcg_const_i32(PPC_PM_RVWINKLE); | |
3303 | gen_helper_pminsn(cpu_env, t); | |
3304 | tcg_temp_free_i32(t); | |
3305 | gen_stop_exception(ctx); | |
3306 | #endif /* defined(CONFIG_USER_ONLY) */ | |
3307 | } | |
3308 | #endif /* #if defined(TARGET_PPC64) */ | |
3309 | ||
697ab892 DG |
3310 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3311 | { | |
3312 | #if defined(TARGET_PPC64) | |
3313 | if (ctx->has_cfar) | |
3314 | tcg_gen_movi_tl(cpu_cfar, nip); | |
3315 | #endif | |
3316 | } | |
3317 | ||
90aa39a1 SF |
3318 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
3319 | { | |
3320 | if (unlikely(ctx->singlestep_enabled)) { | |
3321 | return false; | |
3322 | } | |
3323 | ||
3324 | #ifndef CONFIG_USER_ONLY | |
3325 | return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
3326 | #else | |
3327 | return true; | |
3328 | #endif | |
3329 | } | |
3330 | ||
79aceca5 | 3331 | /*** Branch ***/ |
636aa200 | 3332 | static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
c1942362 | 3333 | { |
e0c8f9ce | 3334 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3335 | dest = (uint32_t) dest; |
e0c8f9ce | 3336 | } |
90aa39a1 | 3337 | if (use_goto_tb(ctx, dest)) { |
57fec1fe | 3338 | tcg_gen_goto_tb(n); |
a2ffb812 | 3339 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
90aa39a1 | 3340 | tcg_gen_exit_tb((uintptr_t)ctx->tb + n); |
c1942362 | 3341 | } else { |
a2ffb812 | 3342 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
8cbcb4fa AJ |
3343 | if (unlikely(ctx->singlestep_enabled)) { |
3344 | if ((ctx->singlestep_enabled & | |
bdc4e053 | 3345 | (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && |
f0cc4aa8 JG |
3346 | (ctx->exception == POWERPC_EXCP_BRANCH || |
3347 | ctx->exception == POWERPC_EXCP_TRACE)) { | |
bd6fefe7 | 3348 | gen_exception_nip(ctx, POWERPC_EXCP_TRACE, dest); |
8cbcb4fa AJ |
3349 | } |
3350 | if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) { | |
e06fcd75 | 3351 | gen_debug_exception(ctx); |
8cbcb4fa AJ |
3352 | } |
3353 | } | |
57fec1fe | 3354 | tcg_gen_exit_tb(0); |
c1942362 | 3355 | } |
c53be334 FB |
3356 | } |
3357 | ||
636aa200 | 3358 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
e1833e1f | 3359 | { |
e0c8f9ce RH |
3360 | if (NARROW_MODE(ctx)) { |
3361 | nip = (uint32_t)nip; | |
3362 | } | |
3363 | tcg_gen_movi_tl(cpu_lr, nip); | |
e1833e1f JM |
3364 | } |
3365 | ||
79aceca5 | 3366 | /* b ba bl bla */ |
99e300ef | 3367 | static void gen_b(DisasContext *ctx) |
79aceca5 | 3368 | { |
76a66253 | 3369 | target_ulong li, target; |
38a64f9d | 3370 | |
8cbcb4fa | 3371 | ctx->exception = POWERPC_EXCP_BRANCH; |
38a64f9d | 3372 | /* sign extend LI */ |
e0c8f9ce RH |
3373 | li = LI(ctx->opcode); |
3374 | li = (li ^ 0x02000000) - 0x02000000; | |
3375 | if (likely(AA(ctx->opcode) == 0)) { | |
046d6672 | 3376 | target = ctx->nip + li - 4; |
e0c8f9ce | 3377 | } else { |
9a64fbe4 | 3378 | target = li; |
e0c8f9ce RH |
3379 | } |
3380 | if (LK(ctx->opcode)) { | |
e1833e1f | 3381 | gen_setlr(ctx, ctx->nip); |
e0c8f9ce | 3382 | } |
fbc3b39b | 3383 | gen_update_cfar(ctx, ctx->nip - 4); |
c1942362 | 3384 | gen_goto_tb(ctx, 0, target); |
79aceca5 FB |
3385 | } |
3386 | ||
e98a6e40 FB |
3387 | #define BCOND_IM 0 |
3388 | #define BCOND_LR 1 | |
3389 | #define BCOND_CTR 2 | |
52a4984d | 3390 | #define BCOND_TAR 3 |
e98a6e40 | 3391 | |
636aa200 | 3392 | static inline void gen_bcond(DisasContext *ctx, int type) |
d9bce9d9 | 3393 | { |
d9bce9d9 | 3394 | uint32_t bo = BO(ctx->opcode); |
42a268c2 | 3395 | TCGLabel *l1; |
a2ffb812 | 3396 | TCGv target; |
e98a6e40 | 3397 | |
8cbcb4fa | 3398 | ctx->exception = POWERPC_EXCP_BRANCH; |
52a4984d | 3399 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
a7812ae4 | 3400 | target = tcg_temp_local_new(); |
a2ffb812 AJ |
3401 | if (type == BCOND_CTR) |
3402 | tcg_gen_mov_tl(target, cpu_ctr); | |
52a4984d TM |
3403 | else if (type == BCOND_TAR) |
3404 | gen_load_spr(target, SPR_TAR); | |
a2ffb812 AJ |
3405 | else |
3406 | tcg_gen_mov_tl(target, cpu_lr); | |
d2e9fd8f | 3407 | } else { |
3408 | TCGV_UNUSED(target); | |
e98a6e40 | 3409 | } |
e1833e1f JM |
3410 | if (LK(ctx->opcode)) |
3411 | gen_setlr(ctx, ctx->nip); | |
a2ffb812 AJ |
3412 | l1 = gen_new_label(); |
3413 | if ((bo & 0x4) == 0) { | |
3414 | /* Decrement and test CTR */ | |
a7812ae4 | 3415 | TCGv temp = tcg_temp_new(); |
a2ffb812 | 3416 | if (unlikely(type == BCOND_CTR)) { |
e06fcd75 | 3417 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
a2ffb812 AJ |
3418 | return; |
3419 | } | |
3420 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); | |
e0c8f9ce | 3421 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3422 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
e0c8f9ce | 3423 | } else { |
a2ffb812 | 3424 | tcg_gen_mov_tl(temp, cpu_ctr); |
e0c8f9ce | 3425 | } |
a2ffb812 AJ |
3426 | if (bo & 0x2) { |
3427 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); | |
3428 | } else { | |
3429 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); | |
e98a6e40 | 3430 | } |
a7812ae4 | 3431 | tcg_temp_free(temp); |
a2ffb812 AJ |
3432 | } |
3433 | if ((bo & 0x10) == 0) { | |
3434 | /* Test CR */ | |
3435 | uint32_t bi = BI(ctx->opcode); | |
8f9fb7ac | 3436 | uint32_t mask = 0x08 >> (bi & 0x03); |
a7812ae4 | 3437 | TCGv_i32 temp = tcg_temp_new_i32(); |
a2ffb812 | 3438 | |
d9bce9d9 | 3439 | if (bo & 0x8) { |
a2ffb812 AJ |
3440 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3441 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); | |
d9bce9d9 | 3442 | } else { |
a2ffb812 AJ |
3443 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3444 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); | |
d9bce9d9 | 3445 | } |
a7812ae4 | 3446 | tcg_temp_free_i32(temp); |
d9bce9d9 | 3447 | } |
fbc3b39b | 3448 | gen_update_cfar(ctx, ctx->nip - 4); |
e98a6e40 | 3449 | if (type == BCOND_IM) { |
a2ffb812 AJ |
3450 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3451 | if (likely(AA(ctx->opcode) == 0)) { | |
3452 | gen_goto_tb(ctx, 0, ctx->nip + li - 4); | |
3453 | } else { | |
3454 | gen_goto_tb(ctx, 0, li); | |
3455 | } | |
accc60c4 BH |
3456 | if ((bo & 0x14) != 0x14) { |
3457 | gen_set_label(l1); | |
3458 | gen_goto_tb(ctx, 1, ctx->nip); | |
3459 | } | |
e98a6e40 | 3460 | } else { |
e0c8f9ce | 3461 | if (NARROW_MODE(ctx)) { |
a2ffb812 | 3462 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
e0c8f9ce | 3463 | } else { |
a2ffb812 | 3464 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
e0c8f9ce | 3465 | } |
a2ffb812 | 3466 | tcg_gen_exit_tb(0); |
accc60c4 BH |
3467 | if ((bo & 0x14) != 0x14) { |
3468 | gen_set_label(l1); | |
3469 | gen_update_nip(ctx, ctx->nip); | |
3470 | tcg_gen_exit_tb(0); | |
3471 | } | |
08e46e54 | 3472 | } |
a9e8f4e7 | 3473 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
c80d1df5 AG |
3474 | tcg_temp_free(target); |
3475 | } | |
e98a6e40 FB |
3476 | } |
3477 | ||
99e300ef | 3478 | static void gen_bc(DisasContext *ctx) |
3b46e624 | 3479 | { |
e98a6e40 FB |
3480 | gen_bcond(ctx, BCOND_IM); |
3481 | } | |
3482 | ||
99e300ef | 3483 | static void gen_bcctr(DisasContext *ctx) |
3b46e624 | 3484 | { |
e98a6e40 FB |
3485 | gen_bcond(ctx, BCOND_CTR); |
3486 | } | |
3487 | ||
99e300ef | 3488 | static void gen_bclr(DisasContext *ctx) |
3b46e624 | 3489 | { |
e98a6e40 FB |
3490 | gen_bcond(ctx, BCOND_LR); |
3491 | } | |
79aceca5 | 3492 | |
52a4984d TM |
3493 | static void gen_bctar(DisasContext *ctx) |
3494 | { | |
3495 | gen_bcond(ctx, BCOND_TAR); | |
3496 | } | |
3497 | ||
79aceca5 | 3498 | /*** Condition register logical ***/ |
e1571908 | 3499 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
99e300ef | 3500 | static void glue(gen_, name)(DisasContext *ctx) \ |
79aceca5 | 3501 | { \ |
fc0d441e JM |
3502 | uint8_t bitmask; \ |
3503 | int sh; \ | |
a7812ae4 | 3504 | TCGv_i32 t0, t1; \ |
fc0d441e | 3505 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
a7812ae4 | 3506 | t0 = tcg_temp_new_i32(); \ |
fc0d441e | 3507 | if (sh > 0) \ |
fea0c503 | 3508 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3509 | else if (sh < 0) \ |
fea0c503 | 3510 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3511 | else \ |
fea0c503 | 3512 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
a7812ae4 | 3513 | t1 = tcg_temp_new_i32(); \ |
fc0d441e JM |
3514 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3515 | if (sh > 0) \ | |
fea0c503 | 3516 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
fc0d441e | 3517 | else if (sh < 0) \ |
fea0c503 | 3518 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
e1571908 | 3519 | else \ |
fea0c503 AJ |
3520 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3521 | tcg_op(t0, t0, t1); \ | |
8f9fb7ac | 3522 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ |
fea0c503 AJ |
3523 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3524 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ | |
3525 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ | |
a7812ae4 PB |
3526 | tcg_temp_free_i32(t0); \ |
3527 | tcg_temp_free_i32(t1); \ | |
79aceca5 FB |
3528 | } |
3529 | ||
3530 | /* crand */ | |
e1571908 | 3531 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
79aceca5 | 3532 | /* crandc */ |
e1571908 | 3533 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
79aceca5 | 3534 | /* creqv */ |
e1571908 | 3535 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
79aceca5 | 3536 | /* crnand */ |
e1571908 | 3537 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
79aceca5 | 3538 | /* crnor */ |
e1571908 | 3539 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
79aceca5 | 3540 | /* cror */ |
e1571908 | 3541 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
79aceca5 | 3542 | /* crorc */ |
e1571908 | 3543 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
79aceca5 | 3544 | /* crxor */ |
e1571908 | 3545 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
99e300ef | 3546 | |
54623277 | 3547 | /* mcrf */ |
99e300ef | 3548 | static void gen_mcrf(DisasContext *ctx) |
79aceca5 | 3549 | { |
47e4661c | 3550 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
79aceca5 FB |
3551 | } |
3552 | ||
3553 | /*** System linkage ***/ | |
99e300ef | 3554 | |
c47493f2 | 3555 | /* rfi (supervisor only) */ |
99e300ef | 3556 | static void gen_rfi(DisasContext *ctx) |
79aceca5 | 3557 | { |
9a64fbe4 | 3558 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 3559 | GEN_PRIV; |
9a64fbe4 | 3560 | #else |
6ca038c2 BH |
3561 | /* This instruction doesn't exist anymore on 64-bit server |
3562 | * processors compliant with arch 2.x | |
a2e71b28 | 3563 | */ |
6ca038c2 BH |
3564 | if (ctx->insns_flags & PPC_SEGMENT_64B) { |
3565 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
3566 | return; | |
3567 | } | |
9a64fbe4 | 3568 | /* Restore CPU state */ |
9b2fadda | 3569 | CHK_SV; |
fbc3b39b | 3570 | gen_update_cfar(ctx, ctx->nip - 4); |
e5f17ac6 | 3571 | gen_helper_rfi(cpu_env); |
e06fcd75 | 3572 | gen_sync_exception(ctx); |
9a64fbe4 | 3573 | #endif |
79aceca5 FB |
3574 | } |
3575 | ||
426613db | 3576 | #if defined(TARGET_PPC64) |
99e300ef | 3577 | static void gen_rfid(DisasContext *ctx) |
426613db JM |
3578 | { |
3579 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 3580 | GEN_PRIV; |
426613db JM |
3581 | #else |
3582 | /* Restore CPU state */ | |
9b2fadda | 3583 | CHK_SV; |
fbc3b39b | 3584 | gen_update_cfar(ctx, ctx->nip - 4); |
e5f17ac6 | 3585 | gen_helper_rfid(cpu_env); |
e06fcd75 | 3586 | gen_sync_exception(ctx); |
426613db JM |
3587 | #endif |
3588 | } | |
426613db | 3589 | |
99e300ef | 3590 | static void gen_hrfid(DisasContext *ctx) |
be147d08 JM |
3591 | { |
3592 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 3593 | GEN_PRIV; |
be147d08 JM |
3594 | #else |
3595 | /* Restore CPU state */ | |
9b2fadda | 3596 | CHK_HV; |
e5f17ac6 | 3597 | gen_helper_hrfid(cpu_env); |
e06fcd75 | 3598 | gen_sync_exception(ctx); |
be147d08 JM |
3599 | #endif |
3600 | } | |
3601 | #endif | |
3602 | ||
79aceca5 | 3603 | /* sc */ |
417bf010 JM |
3604 | #if defined(CONFIG_USER_ONLY) |
3605 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER | |
3606 | #else | |
3607 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL | |
3608 | #endif | |
99e300ef | 3609 | static void gen_sc(DisasContext *ctx) |
79aceca5 | 3610 | { |
e1833e1f JM |
3611 | uint32_t lev; |
3612 | ||
3613 | lev = (ctx->opcode >> 5) & 0x7F; | |
e06fcd75 | 3614 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
79aceca5 FB |
3615 | } |
3616 | ||
3617 | /*** Trap ***/ | |
99e300ef | 3618 | |
22b56ee5 BH |
3619 | /* Check for unconditional traps (always or never) */ |
3620 | static bool check_unconditional_trap(DisasContext *ctx) | |
3621 | { | |
3622 | /* Trap never */ | |
3623 | if (TO(ctx->opcode) == 0) { | |
3624 | return true; | |
3625 | } | |
3626 | /* Trap always */ | |
3627 | if (TO(ctx->opcode) == 31) { | |
3628 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); | |
3629 | return true; | |
3630 | } | |
3631 | return false; | |
3632 | } | |
3633 | ||
54623277 | 3634 | /* tw */ |
99e300ef | 3635 | static void gen_tw(DisasContext *ctx) |
79aceca5 | 3636 | { |
22b56ee5 BH |
3637 | TCGv_i32 t0; |
3638 | ||
3639 | if (check_unconditional_trap(ctx)) { | |
3640 | return; | |
3641 | } | |
3642 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
3643 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3644 | t0); | |
cab3bee2 | 3645 | tcg_temp_free_i32(t0); |
79aceca5 FB |
3646 | } |
3647 | ||
3648 | /* twi */ | |
99e300ef | 3649 | static void gen_twi(DisasContext *ctx) |
79aceca5 | 3650 | { |
22b56ee5 BH |
3651 | TCGv t0; |
3652 | TCGv_i32 t1; | |
3653 | ||
3654 | if (check_unconditional_trap(ctx)) { | |
3655 | return; | |
3656 | } | |
3657 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3658 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 3659 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3660 | tcg_temp_free(t0); |
3661 | tcg_temp_free_i32(t1); | |
79aceca5 FB |
3662 | } |
3663 | ||
d9bce9d9 JM |
3664 | #if defined(TARGET_PPC64) |
3665 | /* td */ | |
99e300ef | 3666 | static void gen_td(DisasContext *ctx) |
d9bce9d9 | 3667 | { |
22b56ee5 BH |
3668 | TCGv_i32 t0; |
3669 | ||
3670 | if (check_unconditional_trap(ctx)) { | |
3671 | return; | |
3672 | } | |
3673 | t0 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 BS |
3674 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
3675 | t0); | |
cab3bee2 | 3676 | tcg_temp_free_i32(t0); |
d9bce9d9 JM |
3677 | } |
3678 | ||
3679 | /* tdi */ | |
99e300ef | 3680 | static void gen_tdi(DisasContext *ctx) |
d9bce9d9 | 3681 | { |
22b56ee5 BH |
3682 | TCGv t0; |
3683 | TCGv_i32 t1; | |
3684 | ||
3685 | if (check_unconditional_trap(ctx)) { | |
3686 | return; | |
3687 | } | |
3688 | t0 = tcg_const_tl(SIMM(ctx->opcode)); | |
3689 | t1 = tcg_const_i32(TO(ctx->opcode)); | |
e5f17ac6 | 3690 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
cab3bee2 AJ |
3691 | tcg_temp_free(t0); |
3692 | tcg_temp_free_i32(t1); | |
d9bce9d9 JM |
3693 | } |
3694 | #endif | |
3695 | ||
79aceca5 | 3696 | /*** Processor control ***/ |
99e300ef | 3697 | |
da91a00f RH |
3698 | static void gen_read_xer(TCGv dst) |
3699 | { | |
3700 | TCGv t0 = tcg_temp_new(); | |
3701 | TCGv t1 = tcg_temp_new(); | |
3702 | TCGv t2 = tcg_temp_new(); | |
3703 | tcg_gen_mov_tl(dst, cpu_xer); | |
3704 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); | |
3705 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); | |
3706 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); | |
3707 | tcg_gen_or_tl(t0, t0, t1); | |
3708 | tcg_gen_or_tl(dst, dst, t2); | |
3709 | tcg_gen_or_tl(dst, dst, t0); | |
3710 | tcg_temp_free(t0); | |
3711 | tcg_temp_free(t1); | |
3712 | tcg_temp_free(t2); | |
3713 | } | |
3714 | ||
3715 | static void gen_write_xer(TCGv src) | |
3716 | { | |
3717 | tcg_gen_andi_tl(cpu_xer, src, | |
3718 | ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA))); | |
3719 | tcg_gen_shri_tl(cpu_so, src, XER_SO); | |
3720 | tcg_gen_shri_tl(cpu_ov, src, XER_OV); | |
3721 | tcg_gen_shri_tl(cpu_ca, src, XER_CA); | |
3722 | tcg_gen_andi_tl(cpu_so, cpu_so, 1); | |
3723 | tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); | |
3724 | tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); | |
3725 | } | |
3726 | ||
54623277 | 3727 | /* mcrxr */ |
99e300ef | 3728 | static void gen_mcrxr(DisasContext *ctx) |
79aceca5 | 3729 | { |
da91a00f RH |
3730 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3731 | TCGv_i32 t1 = tcg_temp_new_i32(); | |
3732 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; | |
3733 | ||
3734 | tcg_gen_trunc_tl_i32(t0, cpu_so); | |
3735 | tcg_gen_trunc_tl_i32(t1, cpu_ov); | |
3736 | tcg_gen_trunc_tl_i32(dst, cpu_ca); | |
294d1292 SB |
3737 | tcg_gen_shli_i32(t0, t0, 3); |
3738 | tcg_gen_shli_i32(t1, t1, 2); | |
3739 | tcg_gen_shli_i32(dst, dst, 1); | |
da91a00f RH |
3740 | tcg_gen_or_i32(dst, dst, t0); |
3741 | tcg_gen_or_i32(dst, dst, t1); | |
3742 | tcg_temp_free_i32(t0); | |
3743 | tcg_temp_free_i32(t1); | |
3744 | ||
3745 | tcg_gen_movi_tl(cpu_so, 0); | |
3746 | tcg_gen_movi_tl(cpu_ov, 0); | |
3747 | tcg_gen_movi_tl(cpu_ca, 0); | |
79aceca5 FB |
3748 | } |
3749 | ||
0cfe11ea | 3750 | /* mfcr mfocrf */ |
99e300ef | 3751 | static void gen_mfcr(DisasContext *ctx) |
79aceca5 | 3752 | { |
76a66253 | 3753 | uint32_t crm, crn; |
3b46e624 | 3754 | |
76a66253 JM |
3755 | if (likely(ctx->opcode & 0x00100000)) { |
3756 | crm = CRM(ctx->opcode); | |
8dd640e4 | 3757 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
0cfe11ea | 3758 | crn = ctz32 (crm); |
e1571908 | 3759 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
0497d2f4 AJ |
3760 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
3761 | cpu_gpr[rD(ctx->opcode)], crn * 4); | |
76a66253 | 3762 | } |
d9bce9d9 | 3763 | } else { |
651721b2 AJ |
3764 | TCGv_i32 t0 = tcg_temp_new_i32(); |
3765 | tcg_gen_mov_i32(t0, cpu_crf[0]); | |
3766 | tcg_gen_shli_i32(t0, t0, 4); | |
3767 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); | |
3768 | tcg_gen_shli_i32(t0, t0, 4); | |
3769 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); | |
3770 | tcg_gen_shli_i32(t0, t0, 4); | |
3771 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); | |
3772 | tcg_gen_shli_i32(t0, t0, 4); | |
3773 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); | |
3774 | tcg_gen_shli_i32(t0, t0, 4); | |
3775 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); | |
3776 | tcg_gen_shli_i32(t0, t0, 4); | |
3777 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); | |
3778 | tcg_gen_shli_i32(t0, t0, 4); | |
3779 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); | |
3780 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
3781 | tcg_temp_free_i32(t0); | |
d9bce9d9 | 3782 | } |
79aceca5 FB |
3783 | } |
3784 | ||
3785 | /* mfmsr */ | |
99e300ef | 3786 | static void gen_mfmsr(DisasContext *ctx) |
79aceca5 | 3787 | { |
9b2fadda | 3788 | CHK_SV; |
6527f6ea | 3789 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
79aceca5 FB |
3790 | } |
3791 | ||
69b058c8 | 3792 | static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) |
3fc6c082 | 3793 | { |
7b13448f | 3794 | #if 0 |
3fc6c082 FB |
3795 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
3796 | printf("ERROR: try to access SPR %d !\n", sprn); | |
7b13448f | 3797 | #endif |
3fc6c082 FB |
3798 | } |
3799 | #define SPR_NOACCESS (&spr_noaccess) | |
3fc6c082 | 3800 | |
79aceca5 | 3801 | /* mfspr */ |
636aa200 | 3802 | static inline void gen_op_mfspr(DisasContext *ctx) |
79aceca5 | 3803 | { |
69b058c8 | 3804 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); |
79aceca5 FB |
3805 | uint32_t sprn = SPR(ctx->opcode); |
3806 | ||
eb94268e BH |
3807 | #if defined(CONFIG_USER_ONLY) |
3808 | read_cb = ctx->spr_cb[sprn].uea_read; | |
3809 | #else | |
3810 | if (ctx->pr) { | |
3811 | read_cb = ctx->spr_cb[sprn].uea_read; | |
3812 | } else if (ctx->hv) { | |
be147d08 | 3813 | read_cb = ctx->spr_cb[sprn].hea_read; |
eb94268e | 3814 | } else { |
3fc6c082 | 3815 | read_cb = ctx->spr_cb[sprn].oea_read; |
eb94268e | 3816 | } |
9a64fbe4 | 3817 | #endif |
76a66253 JM |
3818 | if (likely(read_cb != NULL)) { |
3819 | if (likely(read_cb != SPR_NOACCESS)) { | |
45d827d2 | 3820 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
3fc6c082 FB |
3821 | } else { |
3822 | /* Privilege exception */ | |
9fceefa7 JM |
3823 | /* This is a hack to avoid warnings when running Linux: |
3824 | * this OS breaks the PowerPC virtualisation model, | |
3825 | * allowing userland application to read the PVR | |
3826 | */ | |
3827 | if (sprn != SPR_PVR) { | |
013a2942 PB |
3828 | fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at " |
3829 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3830 | if (qemu_log_separate()) { | |
3831 | qemu_log("Trying to read privileged spr %d (0x%03x) at " | |
3832 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3833 | } | |
f24e5695 | 3834 | } |
9b2fadda | 3835 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
79aceca5 | 3836 | } |
3fc6c082 | 3837 | } else { |
9b2fadda BH |
3838 | /* ISA 2.07 defines these as no-ops */ |
3839 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
3840 | (sprn >= 808 && sprn <= 811)) { | |
3841 | /* This is a nop */ | |
3842 | return; | |
3843 | } | |
3fc6c082 | 3844 | /* Not defined */ |
013a2942 PB |
3845 | fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at " |
3846 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3847 | if (qemu_log_separate()) { | |
3848 | qemu_log("Trying to read invalid spr %d (0x%03x) at " | |
3849 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3850 | } | |
9b2fadda BH |
3851 | |
3852 | /* The behaviour depends on MSR:PR and SPR# bit 0x10, | |
3853 | * it can generate a priv, a hv emu or a no-op | |
3854 | */ | |
3855 | if (sprn & 0x10) { | |
3856 | if (ctx->pr) { | |
3857 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
3858 | } | |
3859 | } else { | |
3860 | if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { | |
3861 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
3862 | } | |
4d6a0680 | 3863 | } |
79aceca5 | 3864 | } |
79aceca5 FB |
3865 | } |
3866 | ||
99e300ef | 3867 | static void gen_mfspr(DisasContext *ctx) |
79aceca5 | 3868 | { |
3fc6c082 | 3869 | gen_op_mfspr(ctx); |
76a66253 | 3870 | } |
3fc6c082 FB |
3871 | |
3872 | /* mftb */ | |
99e300ef | 3873 | static void gen_mftb(DisasContext *ctx) |
3fc6c082 FB |
3874 | { |
3875 | gen_op_mfspr(ctx); | |
79aceca5 FB |
3876 | } |
3877 | ||
0cfe11ea | 3878 | /* mtcrf mtocrf*/ |
99e300ef | 3879 | static void gen_mtcrf(DisasContext *ctx) |
79aceca5 | 3880 | { |
76a66253 | 3881 | uint32_t crm, crn; |
3b46e624 | 3882 | |
76a66253 | 3883 | crm = CRM(ctx->opcode); |
8dd640e4 | 3884 | if (likely((ctx->opcode & 0x00100000))) { |
3885 | if (crm && ((crm & (crm - 1)) == 0)) { | |
3886 | TCGv_i32 temp = tcg_temp_new_i32(); | |
0cfe11ea | 3887 | crn = ctz32 (crm); |
8dd640e4 | 3888 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
0cfe11ea AJ |
3889 | tcg_gen_shri_i32(temp, temp, crn * 4); |
3890 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); | |
8dd640e4 | 3891 | tcg_temp_free_i32(temp); |
3892 | } | |
76a66253 | 3893 | } else { |
651721b2 AJ |
3894 | TCGv_i32 temp = tcg_temp_new_i32(); |
3895 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); | |
3896 | for (crn = 0 ; crn < 8 ; crn++) { | |
3897 | if (crm & (1 << crn)) { | |
3898 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); | |
3899 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); | |
3900 | } | |
3901 | } | |
a7812ae4 | 3902 | tcg_temp_free_i32(temp); |
76a66253 | 3903 | } |
79aceca5 FB |
3904 | } |
3905 | ||
3906 | /* mtmsr */ | |
426613db | 3907 | #if defined(TARGET_PPC64) |
99e300ef | 3908 | static void gen_mtmsrd(DisasContext *ctx) |
426613db | 3909 | { |
9b2fadda BH |
3910 | CHK_SV; |
3911 | ||
3912 | #if !defined(CONFIG_USER_ONLY) | |
be147d08 JM |
3913 | if (ctx->opcode & 0x00010000) { |
3914 | /* Special form that does not need any synchronisation */ | |
6527f6ea AJ |
3915 | TCGv t0 = tcg_temp_new(); |
3916 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
c409bc5d | 3917 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
6527f6ea AJ |
3918 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3919 | tcg_temp_free(t0); | |
be147d08 | 3920 | } else { |
056b05f8 JM |
3921 | /* XXX: we need to update nip before the store |
3922 | * if we enter power saving mode, we will exit the loop | |
3923 | * directly from ppc_store_msr | |
3924 | */ | |
be147d08 | 3925 | gen_update_nip(ctx, ctx->nip); |
e5f17ac6 | 3926 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
be147d08 JM |
3927 | /* Must stop the translation as machine state (may have) changed */ |
3928 | /* Note that mtmsr is not always defined as context-synchronizing */ | |
e06fcd75 | 3929 | gen_stop_exception(ctx); |
be147d08 | 3930 | } |
9b2fadda | 3931 | #endif /* !defined(CONFIG_USER_ONLY) */ |
426613db | 3932 | } |
9b2fadda | 3933 | #endif /* defined(TARGET_PPC64) */ |
426613db | 3934 | |
99e300ef | 3935 | static void gen_mtmsr(DisasContext *ctx) |
79aceca5 | 3936 | { |
9b2fadda BH |
3937 | CHK_SV; |
3938 | ||
3939 | #if !defined(CONFIG_USER_ONLY) | |
3940 | if (ctx->opcode & 0x00010000) { | |
be147d08 | 3941 | /* Special form that does not need any synchronisation */ |
6527f6ea AJ |
3942 | TCGv t0 = tcg_temp_new(); |
3943 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE)); | |
c409bc5d | 3944 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
6527f6ea AJ |
3945 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
3946 | tcg_temp_free(t0); | |
be147d08 | 3947 | } else { |
8018dc63 AG |
3948 | TCGv msr = tcg_temp_new(); |
3949 | ||
056b05f8 JM |
3950 | /* XXX: we need to update nip before the store |
3951 | * if we enter power saving mode, we will exit the loop | |
3952 | * directly from ppc_store_msr | |
3953 | */ | |
be147d08 | 3954 | gen_update_nip(ctx, ctx->nip); |
d9bce9d9 | 3955 | #if defined(TARGET_PPC64) |
8018dc63 AG |
3956 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
3957 | #else | |
3958 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); | |
d9bce9d9 | 3959 | #endif |
e5f17ac6 | 3960 | gen_helper_store_msr(cpu_env, msr); |
c80d1df5 | 3961 | tcg_temp_free(msr); |
be147d08 | 3962 | /* Must stop the translation as machine state (may have) changed */ |
6527f6ea | 3963 | /* Note that mtmsr is not always defined as context-synchronizing */ |
e06fcd75 | 3964 | gen_stop_exception(ctx); |
be147d08 | 3965 | } |
9a64fbe4 | 3966 | #endif |
79aceca5 FB |
3967 | } |
3968 | ||
3969 | /* mtspr */ | |
99e300ef | 3970 | static void gen_mtspr(DisasContext *ctx) |
79aceca5 | 3971 | { |
69b058c8 | 3972 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); |
79aceca5 FB |
3973 | uint32_t sprn = SPR(ctx->opcode); |
3974 | ||
eb94268e BH |
3975 | #if defined(CONFIG_USER_ONLY) |
3976 | write_cb = ctx->spr_cb[sprn].uea_write; | |
3977 | #else | |
3978 | if (ctx->pr) { | |
3979 | write_cb = ctx->spr_cb[sprn].uea_write; | |
3980 | } else if (ctx->hv) { | |
be147d08 | 3981 | write_cb = ctx->spr_cb[sprn].hea_write; |
eb94268e | 3982 | } else { |
3fc6c082 | 3983 | write_cb = ctx->spr_cb[sprn].oea_write; |
eb94268e | 3984 | } |
9a64fbe4 | 3985 | #endif |
76a66253 JM |
3986 | if (likely(write_cb != NULL)) { |
3987 | if (likely(write_cb != SPR_NOACCESS)) { | |
45d827d2 | 3988 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
3fc6c082 FB |
3989 | } else { |
3990 | /* Privilege exception */ | |
013a2942 PB |
3991 | fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at " |
3992 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3993 | if (qemu_log_separate()) { | |
3994 | qemu_log("Trying to write privileged spr %d (0x%03x) at " | |
3995 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
3996 | } | |
9b2fadda | 3997 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
76a66253 | 3998 | } |
3fc6c082 | 3999 | } else { |
9b2fadda BH |
4000 | /* ISA 2.07 defines these as no-ops */ |
4001 | if ((ctx->insns_flags2 & PPC2_ISA207S) && | |
4002 | (sprn >= 808 && sprn <= 811)) { | |
4003 | /* This is a nop */ | |
4004 | return; | |
4005 | } | |
4006 | ||
3fc6c082 | 4007 | /* Not defined */ |
013a2942 PB |
4008 | if (qemu_log_separate()) { |
4009 | qemu_log("Trying to write invalid spr %d (0x%03x) at " | |
4010 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4011 | } | |
4012 | fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at " | |
4013 | TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); | |
4d6a0680 | 4014 | |
9b2fadda BH |
4015 | |
4016 | /* The behaviour depends on MSR:PR and SPR# bit 0x10, | |
4017 | * it can generate a priv, a hv emu or a no-op | |
4018 | */ | |
4019 | if (sprn & 0x10) { | |
4020 | if (ctx->pr) { | |
4021 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4022 | } | |
4023 | } else { | |
4024 | if (ctx->pr || sprn == 0) { | |
4025 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); | |
4026 | } | |
4d6a0680 | 4027 | } |
79aceca5 | 4028 | } |
79aceca5 FB |
4029 | } |
4030 | ||
dc2ee038 VAS |
4031 | #if defined(TARGET_PPC64) |
4032 | /* setb */ | |
4033 | static void gen_setb(DisasContext *ctx) | |
4034 | { | |
4035 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
4036 | TCGv_i32 t8 = tcg_temp_new_i32(); | |
4037 | TCGv_i32 tm1 = tcg_temp_new_i32(); | |
4038 | int crf = crfS(ctx->opcode); | |
4039 | ||
4040 | tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); | |
4041 | tcg_gen_movi_i32(t8, 8); | |
4042 | tcg_gen_movi_i32(tm1, -1); | |
4043 | tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); | |
4044 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4045 | ||
4046 | tcg_temp_free_i32(t0); | |
4047 | tcg_temp_free_i32(t8); | |
4048 | tcg_temp_free_i32(tm1); | |
4049 | } | |
4050 | #endif | |
4051 | ||
79aceca5 | 4052 | /*** Cache management ***/ |
99e300ef | 4053 | |
54623277 | 4054 | /* dcbf */ |
99e300ef | 4055 | static void gen_dcbf(DisasContext *ctx) |
79aceca5 | 4056 | { |
dac454af | 4057 | /* XXX: specification says this is treated as a load by the MMU */ |
76db3ba4 AJ |
4058 | TCGv t0; |
4059 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4060 | t0 = tcg_temp_new(); | |
4061 | gen_addr_reg_index(ctx, t0); | |
4062 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4063 | tcg_temp_free(t0); |
79aceca5 FB |
4064 | } |
4065 | ||
4066 | /* dcbi (Supervisor only) */ | |
99e300ef | 4067 | static void gen_dcbi(DisasContext *ctx) |
79aceca5 | 4068 | { |
a541f297 | 4069 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4070 | GEN_PRIV; |
a541f297 | 4071 | #else |
b61f2753 | 4072 | TCGv EA, val; |
9b2fadda BH |
4073 | |
4074 | CHK_SV; | |
a7812ae4 | 4075 | EA = tcg_temp_new(); |
76db3ba4 AJ |
4076 | gen_set_access_type(ctx, ACCESS_CACHE); |
4077 | gen_addr_reg_index(ctx, EA); | |
a7812ae4 | 4078 | val = tcg_temp_new(); |
76a66253 | 4079 | /* XXX: specification says this should be treated as a store by the MMU */ |
76db3ba4 AJ |
4080 | gen_qemu_ld8u(ctx, val, EA); |
4081 | gen_qemu_st8(ctx, val, EA); | |
b61f2753 AJ |
4082 | tcg_temp_free(val); |
4083 | tcg_temp_free(EA); | |
9b2fadda | 4084 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4085 | } |
4086 | ||
4087 | /* dcdst */ | |
99e300ef | 4088 | static void gen_dcbst(DisasContext *ctx) |
79aceca5 | 4089 | { |
76a66253 | 4090 | /* XXX: specification say this is treated as a load by the MMU */ |
76db3ba4 AJ |
4091 | TCGv t0; |
4092 | gen_set_access_type(ctx, ACCESS_CACHE); | |
4093 | t0 = tcg_temp_new(); | |
4094 | gen_addr_reg_index(ctx, t0); | |
4095 | gen_qemu_ld8u(ctx, t0, t0); | |
fea0c503 | 4096 | tcg_temp_free(t0); |
79aceca5 FB |
4097 | } |
4098 | ||
4099 | /* dcbt */ | |
99e300ef | 4100 | static void gen_dcbt(DisasContext *ctx) |
79aceca5 | 4101 | { |
0db1b20e | 4102 | /* interpreted as no-op */ |
76a66253 JM |
4103 | /* XXX: specification say this is treated as a load by the MMU |
4104 | * but does not generate any exception | |
4105 | */ | |
79aceca5 FB |
4106 | } |
4107 | ||
4108 | /* dcbtst */ | |
99e300ef | 4109 | static void gen_dcbtst(DisasContext *ctx) |
79aceca5 | 4110 | { |
0db1b20e | 4111 | /* interpreted as no-op */ |
76a66253 JM |
4112 | /* XXX: specification say this is treated as a load by the MMU |
4113 | * but does not generate any exception | |
4114 | */ | |
79aceca5 FB |
4115 | } |
4116 | ||
4d09d529 AG |
4117 | /* dcbtls */ |
4118 | static void gen_dcbtls(DisasContext *ctx) | |
4119 | { | |
4120 | /* Always fails locking the cache */ | |
4121 | TCGv t0 = tcg_temp_new(); | |
4122 | gen_load_spr(t0, SPR_Exxx_L1CSR0); | |
4123 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); | |
4124 | gen_store_spr(SPR_Exxx_L1CSR0, t0); | |
4125 | tcg_temp_free(t0); | |
4126 | } | |
4127 | ||
79aceca5 | 4128 | /* dcbz */ |
99e300ef | 4129 | static void gen_dcbz(DisasContext *ctx) |
79aceca5 | 4130 | { |
8e33944f | 4131 | TCGv tcgv_addr; |
c9f82d01 | 4132 | TCGv_i32 tcgv_op; |
d63001d1 | 4133 | |
76db3ba4 | 4134 | gen_set_access_type(ctx, ACCESS_CACHE); |
8e33944f | 4135 | tcgv_addr = tcg_temp_new(); |
c9f82d01 | 4136 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); |
8e33944f | 4137 | gen_addr_reg_index(ctx, tcgv_addr); |
c9f82d01 | 4138 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); |
8e33944f | 4139 | tcg_temp_free(tcgv_addr); |
c9f82d01 | 4140 | tcg_temp_free_i32(tcgv_op); |
79aceca5 FB |
4141 | } |
4142 | ||
ae1c1a3d | 4143 | /* dst / dstt */ |
99e300ef | 4144 | static void gen_dst(DisasContext *ctx) |
ae1c1a3d AJ |
4145 | { |
4146 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4147 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4148 | } else { |
4149 | /* interpreted as no-op */ | |
4150 | } | |
4151 | } | |
4152 | ||
4153 | /* dstst /dststt */ | |
99e300ef | 4154 | static void gen_dstst(DisasContext *ctx) |
ae1c1a3d AJ |
4155 | { |
4156 | if (rA(ctx->opcode) == 0) { | |
e41029b3 | 4157 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
ae1c1a3d AJ |
4158 | } else { |
4159 | /* interpreted as no-op */ | |
4160 | } | |
4161 | ||
4162 | } | |
4163 | ||
4164 | /* dss / dssall */ | |
99e300ef | 4165 | static void gen_dss(DisasContext *ctx) |
ae1c1a3d AJ |
4166 | { |
4167 | /* interpreted as no-op */ | |
4168 | } | |
4169 | ||
79aceca5 | 4170 | /* icbi */ |
99e300ef | 4171 | static void gen_icbi(DisasContext *ctx) |
79aceca5 | 4172 | { |
76db3ba4 AJ |
4173 | TCGv t0; |
4174 | gen_set_access_type(ctx, ACCESS_CACHE); | |
76db3ba4 AJ |
4175 | t0 = tcg_temp_new(); |
4176 | gen_addr_reg_index(ctx, t0); | |
2f5a189c | 4177 | gen_helper_icbi(cpu_env, t0); |
37d269df | 4178 | tcg_temp_free(t0); |
79aceca5 FB |
4179 | } |
4180 | ||
4181 | /* Optional: */ | |
4182 | /* dcba */ | |
99e300ef | 4183 | static void gen_dcba(DisasContext *ctx) |
79aceca5 | 4184 | { |
0db1b20e JM |
4185 | /* interpreted as no-op */ |
4186 | /* XXX: specification say this is treated as a store by the MMU | |
4187 | * but does not generate any exception | |
4188 | */ | |
79aceca5 FB |
4189 | } |
4190 | ||
4191 | /*** Segment register manipulation ***/ | |
4192 | /* Supervisor only: */ | |
99e300ef | 4193 | |
54623277 | 4194 | /* mfsr */ |
99e300ef | 4195 | static void gen_mfsr(DisasContext *ctx) |
79aceca5 | 4196 | { |
9a64fbe4 | 4197 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4198 | GEN_PRIV; |
9a64fbe4 | 4199 | #else |
74d37793 | 4200 | TCGv t0; |
9b2fadda BH |
4201 | |
4202 | CHK_SV; | |
74d37793 | 4203 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4204 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4205 | tcg_temp_free(t0); |
9b2fadda | 4206 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4207 | } |
4208 | ||
4209 | /* mfsrin */ | |
99e300ef | 4210 | static void gen_mfsrin(DisasContext *ctx) |
79aceca5 | 4211 | { |
9a64fbe4 | 4212 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4213 | GEN_PRIV; |
9a64fbe4 | 4214 | #else |
74d37793 | 4215 | TCGv t0; |
9b2fadda BH |
4216 | |
4217 | CHK_SV; | |
74d37793 AJ |
4218 | t0 = tcg_temp_new(); |
4219 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4220 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4221 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4222 | tcg_temp_free(t0); |
9b2fadda | 4223 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4224 | } |
4225 | ||
4226 | /* mtsr */ | |
99e300ef | 4227 | static void gen_mtsr(DisasContext *ctx) |
79aceca5 | 4228 | { |
9a64fbe4 | 4229 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4230 | GEN_PRIV; |
9a64fbe4 | 4231 | #else |
74d37793 | 4232 | TCGv t0; |
9b2fadda BH |
4233 | |
4234 | CHK_SV; | |
74d37793 | 4235 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4236 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4237 | tcg_temp_free(t0); |
9b2fadda | 4238 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4239 | } |
4240 | ||
4241 | /* mtsrin */ | |
99e300ef | 4242 | static void gen_mtsrin(DisasContext *ctx) |
79aceca5 | 4243 | { |
9a64fbe4 | 4244 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4245 | GEN_PRIV; |
9a64fbe4 | 4246 | #else |
74d37793 | 4247 | TCGv t0; |
9b2fadda BH |
4248 | CHK_SV; |
4249 | ||
74d37793 AJ |
4250 | t0 = tcg_temp_new(); |
4251 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4252 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4253 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
74d37793 | 4254 | tcg_temp_free(t0); |
9b2fadda | 4255 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4256 | } |
4257 | ||
12de9a39 JM |
4258 | #if defined(TARGET_PPC64) |
4259 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ | |
e8eaa2c0 | 4260 | |
54623277 | 4261 | /* mfsr */ |
e8eaa2c0 | 4262 | static void gen_mfsr_64b(DisasContext *ctx) |
12de9a39 JM |
4263 | { |
4264 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4265 | GEN_PRIV; |
12de9a39 | 4266 | #else |
74d37793 | 4267 | TCGv t0; |
9b2fadda BH |
4268 | |
4269 | CHK_SV; | |
74d37793 | 4270 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4271 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4272 | tcg_temp_free(t0); |
9b2fadda | 4273 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4274 | } |
4275 | ||
4276 | /* mfsrin */ | |
e8eaa2c0 | 4277 | static void gen_mfsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4278 | { |
4279 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4280 | GEN_PRIV; |
12de9a39 | 4281 | #else |
74d37793 | 4282 | TCGv t0; |
9b2fadda BH |
4283 | |
4284 | CHK_SV; | |
74d37793 AJ |
4285 | t0 = tcg_temp_new(); |
4286 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4287 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4288 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 | 4289 | tcg_temp_free(t0); |
9b2fadda | 4290 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4291 | } |
4292 | ||
4293 | /* mtsr */ | |
e8eaa2c0 | 4294 | static void gen_mtsr_64b(DisasContext *ctx) |
12de9a39 JM |
4295 | { |
4296 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4297 | GEN_PRIV; |
12de9a39 | 4298 | #else |
74d37793 | 4299 | TCGv t0; |
9b2fadda BH |
4300 | |
4301 | CHK_SV; | |
74d37793 | 4302 | t0 = tcg_const_tl(SR(ctx->opcode)); |
c6c7cf05 | 4303 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4304 | tcg_temp_free(t0); |
9b2fadda | 4305 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 JM |
4306 | } |
4307 | ||
4308 | /* mtsrin */ | |
e8eaa2c0 | 4309 | static void gen_mtsrin_64b(DisasContext *ctx) |
12de9a39 JM |
4310 | { |
4311 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4312 | GEN_PRIV; |
12de9a39 | 4313 | #else |
74d37793 | 4314 | TCGv t0; |
9b2fadda BH |
4315 | |
4316 | CHK_SV; | |
74d37793 AJ |
4317 | t0 = tcg_temp_new(); |
4318 | tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); | |
4319 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 4320 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
74d37793 | 4321 | tcg_temp_free(t0); |
9b2fadda | 4322 | #endif /* defined(CONFIG_USER_ONLY) */ |
12de9a39 | 4323 | } |
f6b868fc BS |
4324 | |
4325 | /* slbmte */ | |
e8eaa2c0 | 4326 | static void gen_slbmte(DisasContext *ctx) |
f6b868fc BS |
4327 | { |
4328 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4329 | GEN_PRIV; |
f6b868fc | 4330 | #else |
9b2fadda BH |
4331 | CHK_SV; |
4332 | ||
c6c7cf05 BS |
4333 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4334 | cpu_gpr[rS(ctx->opcode)]); | |
9b2fadda | 4335 | #endif /* defined(CONFIG_USER_ONLY) */ |
f6b868fc BS |
4336 | } |
4337 | ||
efdef95f DG |
4338 | static void gen_slbmfee(DisasContext *ctx) |
4339 | { | |
4340 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4341 | GEN_PRIV; |
efdef95f | 4342 | #else |
9b2fadda BH |
4343 | CHK_SV; |
4344 | ||
c6c7cf05 | 4345 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4346 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4347 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f DG |
4348 | } |
4349 | ||
4350 | static void gen_slbmfev(DisasContext *ctx) | |
4351 | { | |
4352 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4353 | GEN_PRIV; |
efdef95f | 4354 | #else |
9b2fadda BH |
4355 | CHK_SV; |
4356 | ||
c6c7cf05 | 4357 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
efdef95f | 4358 | cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4359 | #endif /* defined(CONFIG_USER_ONLY) */ |
efdef95f | 4360 | } |
c76c22d5 BH |
4361 | |
4362 | static void gen_slbfee_(DisasContext *ctx) | |
4363 | { | |
4364 | #if defined(CONFIG_USER_ONLY) | |
4365 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4366 | #else | |
4367 | TCGLabel *l1, *l2; | |
4368 | ||
4369 | if (unlikely(ctx->pr)) { | |
4370 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); | |
4371 | return; | |
4372 | } | |
4373 | gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, | |
4374 | cpu_gpr[rB(ctx->opcode)]); | |
4375 | l1 = gen_new_label(); | |
4376 | l2 = gen_new_label(); | |
4377 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); | |
4378 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); | |
4379 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ); | |
4380 | tcg_gen_br(l2); | |
4381 | gen_set_label(l1); | |
4382 | tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); | |
4383 | gen_set_label(l2); | |
4384 | #endif | |
4385 | } | |
12de9a39 JM |
4386 | #endif /* defined(TARGET_PPC64) */ |
4387 | ||
79aceca5 | 4388 | /*** Lookaside buffer management ***/ |
c47493f2 | 4389 | /* Optional & supervisor only: */ |
99e300ef | 4390 | |
54623277 | 4391 | /* tlbia */ |
99e300ef | 4392 | static void gen_tlbia(DisasContext *ctx) |
79aceca5 | 4393 | { |
9a64fbe4 | 4394 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4395 | GEN_PRIV; |
9a64fbe4 | 4396 | #else |
9b2fadda BH |
4397 | CHK_HV; |
4398 | ||
c6c7cf05 | 4399 | gen_helper_tlbia(cpu_env); |
9b2fadda | 4400 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4401 | } |
4402 | ||
bf14b1ce | 4403 | /* tlbiel */ |
99e300ef | 4404 | static void gen_tlbiel(DisasContext *ctx) |
bf14b1ce BS |
4405 | { |
4406 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4407 | GEN_PRIV; |
bf14b1ce | 4408 | #else |
9b2fadda BH |
4409 | CHK_SV; |
4410 | ||
c6c7cf05 | 4411 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4412 | #endif /* defined(CONFIG_USER_ONLY) */ |
bf14b1ce BS |
4413 | } |
4414 | ||
79aceca5 | 4415 | /* tlbie */ |
99e300ef | 4416 | static void gen_tlbie(DisasContext *ctx) |
79aceca5 | 4417 | { |
9a64fbe4 | 4418 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4419 | GEN_PRIV; |
9a64fbe4 | 4420 | #else |
9b2fadda BH |
4421 | CHK_HV; |
4422 | ||
9ca3f7f3 | 4423 | if (NARROW_MODE(ctx)) { |
74d37793 AJ |
4424 | TCGv t0 = tcg_temp_new(); |
4425 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 4426 | gen_helper_tlbie(cpu_env, t0); |
74d37793 | 4427 | tcg_temp_free(t0); |
9ca3f7f3 | 4428 | } else { |
c6c7cf05 | 4429 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9ca3f7f3 | 4430 | } |
9b2fadda | 4431 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4432 | } |
4433 | ||
4434 | /* tlbsync */ | |
99e300ef | 4435 | static void gen_tlbsync(DisasContext *ctx) |
79aceca5 | 4436 | { |
9a64fbe4 | 4437 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 4438 | GEN_PRIV; |
9a64fbe4 | 4439 | #else |
9b2fadda BH |
4440 | CHK_HV; |
4441 | ||
cd0c6f47 BH |
4442 | /* tlbsync is a nop for server, ptesync handles delayed tlb flush, |
4443 | * embedded however needs to deal with tlbsync. We don't try to be | |
4444 | * fancy and swallow the overhead of checking for both. | |
9a64fbe4 | 4445 | */ |
cd0c6f47 | 4446 | gen_check_tlb_flush(ctx); |
9b2fadda | 4447 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
4448 | } |
4449 | ||
426613db JM |
4450 | #if defined(TARGET_PPC64) |
4451 | /* slbia */ | |
99e300ef | 4452 | static void gen_slbia(DisasContext *ctx) |
426613db JM |
4453 | { |
4454 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4455 | GEN_PRIV; |
426613db | 4456 | #else |
9b2fadda BH |
4457 | CHK_SV; |
4458 | ||
c6c7cf05 | 4459 | gen_helper_slbia(cpu_env); |
9b2fadda | 4460 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db JM |
4461 | } |
4462 | ||
4463 | /* slbie */ | |
99e300ef | 4464 | static void gen_slbie(DisasContext *ctx) |
426613db JM |
4465 | { |
4466 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 4467 | GEN_PRIV; |
426613db | 4468 | #else |
9b2fadda BH |
4469 | CHK_SV; |
4470 | ||
c6c7cf05 | 4471 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 4472 | #endif /* defined(CONFIG_USER_ONLY) */ |
426613db | 4473 | } |
9b2fadda | 4474 | #endif /* defined(TARGET_PPC64) */ |
426613db | 4475 | |
79aceca5 FB |
4476 | /*** External control ***/ |
4477 | /* Optional: */ | |
99e300ef | 4478 | |
54623277 | 4479 | /* eciwx */ |
99e300ef | 4480 | static void gen_eciwx(DisasContext *ctx) |
79aceca5 | 4481 | { |
76db3ba4 | 4482 | TCGv t0; |
fa407c03 | 4483 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4484 | gen_set_access_type(ctx, ACCESS_EXT); |
4485 | t0 = tcg_temp_new(); | |
4486 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4487 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4488 | gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4489 | tcg_temp_free(t0); |
76a66253 JM |
4490 | } |
4491 | ||
4492 | /* ecowx */ | |
99e300ef | 4493 | static void gen_ecowx(DisasContext *ctx) |
76a66253 | 4494 | { |
76db3ba4 | 4495 | TCGv t0; |
fa407c03 | 4496 | /* Should check EAR[E] ! */ |
76db3ba4 AJ |
4497 | gen_set_access_type(ctx, ACCESS_EXT); |
4498 | t0 = tcg_temp_new(); | |
4499 | gen_addr_reg_index(ctx, t0); | |
fa407c03 | 4500 | gen_check_align(ctx, t0, 0x03); |
76db3ba4 | 4501 | gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0); |
fa407c03 | 4502 | tcg_temp_free(t0); |
76a66253 JM |
4503 | } |
4504 | ||
4505 | /* PowerPC 601 specific instructions */ | |
99e300ef | 4506 | |
54623277 | 4507 | /* abs - abs. */ |
99e300ef | 4508 | static void gen_abs(DisasContext *ctx) |
76a66253 | 4509 | { |
42a268c2 RH |
4510 | TCGLabel *l1 = gen_new_label(); |
4511 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4512 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4513 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4514 | tcg_gen_br(l2); | |
4515 | gen_set_label(l1); | |
4516 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4517 | gen_set_label(l2); | |
76a66253 | 4518 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4519 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4520 | } |
4521 | ||
4522 | /* abso - abso. */ | |
99e300ef | 4523 | static void gen_abso(DisasContext *ctx) |
76a66253 | 4524 | { |
42a268c2 RH |
4525 | TCGLabel *l1 = gen_new_label(); |
4526 | TCGLabel *l2 = gen_new_label(); | |
4527 | TCGLabel *l3 = gen_new_label(); | |
22e0e173 | 4528 | /* Start with XER OV disabled, the most likely case */ |
da91a00f | 4529 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4530 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2); |
4531 | tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1); | |
da91a00f RH |
4532 | tcg_gen_movi_tl(cpu_ov, 1); |
4533 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4534 | tcg_gen_br(l2); |
4535 | gen_set_label(l1); | |
4536 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4537 | tcg_gen_br(l3); | |
4538 | gen_set_label(l2); | |
4539 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4540 | gen_set_label(l3); | |
76a66253 | 4541 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4542 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4543 | } |
4544 | ||
4545 | /* clcs */ | |
99e300ef | 4546 | static void gen_clcs(DisasContext *ctx) |
76a66253 | 4547 | { |
22e0e173 | 4548 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
d523dd00 | 4549 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 4550 | tcg_temp_free_i32(t0); |
c7697e1f | 4551 | /* Rc=1 sets CR0 to an undefined state */ |
76a66253 JM |
4552 | } |
4553 | ||
4554 | /* div - div. */ | |
99e300ef | 4555 | static void gen_div(DisasContext *ctx) |
76a66253 | 4556 | { |
d15f74fb BS |
4557 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4558 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4559 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4560 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4561 | } |
4562 | ||
4563 | /* divo - divo. */ | |
99e300ef | 4564 | static void gen_divo(DisasContext *ctx) |
76a66253 | 4565 | { |
d15f74fb BS |
4566 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4567 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4568 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4569 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4570 | } |
4571 | ||
4572 | /* divs - divs. */ | |
99e300ef | 4573 | static void gen_divs(DisasContext *ctx) |
76a66253 | 4574 | { |
d15f74fb BS |
4575 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
4576 | cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4577 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4578 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4579 | } |
4580 | ||
4581 | /* divso - divso. */ | |
99e300ef | 4582 | static void gen_divso(DisasContext *ctx) |
76a66253 | 4583 | { |
d15f74fb BS |
4584 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
4585 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
76a66253 | 4586 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4587 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4588 | } |
4589 | ||
4590 | /* doz - doz. */ | |
99e300ef | 4591 | static void gen_doz(DisasContext *ctx) |
76a66253 | 4592 | { |
42a268c2 RH |
4593 | TCGLabel *l1 = gen_new_label(); |
4594 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4595 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4596 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4597 | tcg_gen_br(l2); | |
4598 | gen_set_label(l1); | |
4599 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4600 | gen_set_label(l2); | |
76a66253 | 4601 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4602 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4603 | } |
4604 | ||
4605 | /* dozo - dozo. */ | |
99e300ef | 4606 | static void gen_dozo(DisasContext *ctx) |
76a66253 | 4607 | { |
42a268c2 RH |
4608 | TCGLabel *l1 = gen_new_label(); |
4609 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4610 | TCGv t0 = tcg_temp_new(); |
4611 | TCGv t1 = tcg_temp_new(); | |
4612 | TCGv t2 = tcg_temp_new(); | |
4613 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4614 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4615 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1); |
4616 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4617 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4618 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); | |
4619 | tcg_gen_andc_tl(t1, t1, t2); | |
4620 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); | |
4621 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); | |
da91a00f RH |
4622 | tcg_gen_movi_tl(cpu_ov, 1); |
4623 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4624 | tcg_gen_br(l2); |
4625 | gen_set_label(l1); | |
4626 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4627 | gen_set_label(l2); | |
4628 | tcg_temp_free(t0); | |
4629 | tcg_temp_free(t1); | |
4630 | tcg_temp_free(t2); | |
76a66253 | 4631 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4632 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4633 | } |
4634 | ||
4635 | /* dozi */ | |
99e300ef | 4636 | static void gen_dozi(DisasContext *ctx) |
76a66253 | 4637 | { |
22e0e173 | 4638 | target_long simm = SIMM(ctx->opcode); |
42a268c2 RH |
4639 | TCGLabel *l1 = gen_new_label(); |
4640 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4641 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
4642 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); | |
4643 | tcg_gen_br(l2); | |
4644 | gen_set_label(l1); | |
4645 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); | |
4646 | gen_set_label(l2); | |
4647 | if (unlikely(Rc(ctx->opcode) != 0)) | |
4648 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); | |
76a66253 JM |
4649 | } |
4650 | ||
76a66253 | 4651 | /* lscbx - lscbx. */ |
99e300ef | 4652 | static void gen_lscbx(DisasContext *ctx) |
76a66253 | 4653 | { |
bdb4b689 AJ |
4654 | TCGv t0 = tcg_temp_new(); |
4655 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); | |
4656 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); | |
4657 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); | |
76a66253 | 4658 | |
76db3ba4 | 4659 | gen_addr_reg_index(ctx, t0); |
2f5a189c | 4660 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
bdb4b689 AJ |
4661 | tcg_temp_free_i32(t1); |
4662 | tcg_temp_free_i32(t2); | |
4663 | tcg_temp_free_i32(t3); | |
3d7b417e | 4664 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
bdb4b689 | 4665 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
76a66253 | 4666 | if (unlikely(Rc(ctx->opcode) != 0)) |
bdb4b689 AJ |
4667 | gen_set_Rc0(ctx, t0); |
4668 | tcg_temp_free(t0); | |
76a66253 JM |
4669 | } |
4670 | ||
4671 | /* maskg - maskg. */ | |
99e300ef | 4672 | static void gen_maskg(DisasContext *ctx) |
76a66253 | 4673 | { |
42a268c2 | 4674 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
4675 | TCGv t0 = tcg_temp_new(); |
4676 | TCGv t1 = tcg_temp_new(); | |
4677 | TCGv t2 = tcg_temp_new(); | |
4678 | TCGv t3 = tcg_temp_new(); | |
4679 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); | |
4680 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4681 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); | |
4682 | tcg_gen_addi_tl(t2, t0, 1); | |
4683 | tcg_gen_shr_tl(t2, t3, t2); | |
4684 | tcg_gen_shr_tl(t3, t3, t1); | |
4685 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); | |
4686 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); | |
4687 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4688 | gen_set_label(l1); | |
4689 | tcg_temp_free(t0); | |
4690 | tcg_temp_free(t1); | |
4691 | tcg_temp_free(t2); | |
4692 | tcg_temp_free(t3); | |
76a66253 | 4693 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4694 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4695 | } |
4696 | ||
4697 | /* maskir - maskir. */ | |
99e300ef | 4698 | static void gen_maskir(DisasContext *ctx) |
76a66253 | 4699 | { |
22e0e173 AJ |
4700 | TCGv t0 = tcg_temp_new(); |
4701 | TCGv t1 = tcg_temp_new(); | |
4702 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4703 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
4704 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4705 | tcg_temp_free(t0); | |
4706 | tcg_temp_free(t1); | |
76a66253 | 4707 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4708 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4709 | } |
4710 | ||
4711 | /* mul - mul. */ | |
99e300ef | 4712 | static void gen_mul(DisasContext *ctx) |
76a66253 | 4713 | { |
22e0e173 AJ |
4714 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4715 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4716 | TCGv t2 = tcg_temp_new(); | |
4717 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); | |
4718 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4719 | tcg_gen_mul_i64(t0, t0, t1); | |
4720 | tcg_gen_trunc_i64_tl(t2, t0); | |
4721 | gen_store_spr(SPR_MQ, t2); | |
4722 | tcg_gen_shri_i64(t1, t0, 32); | |
4723 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4724 | tcg_temp_free_i64(t0); | |
4725 | tcg_temp_free_i64(t1); | |
4726 | tcg_temp_free(t2); | |
76a66253 | 4727 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4728 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4729 | } |
4730 | ||
4731 | /* mulo - mulo. */ | |
99e300ef | 4732 | static void gen_mulo(DisasContext *ctx) |
76a66253 | 4733 | { |
42a268c2 | 4734 | TCGLabel *l1 = gen_new_label(); |
22e0e173 AJ |
4735 | TCGv_i64 t0 = tcg_temp_new_i64(); |
4736 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
4737 | TCGv t2 = tcg_temp_new(); | |
4738 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 4739 | tcg_gen_movi_tl(cpu_ov, 0); |
22e0e173 AJ |
4740 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
4741 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); | |
4742 | tcg_gen_mul_i64(t0, t0, t1); | |
4743 | tcg_gen_trunc_i64_tl(t2, t0); | |
4744 | gen_store_spr(SPR_MQ, t2); | |
4745 | tcg_gen_shri_i64(t1, t0, 32); | |
4746 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); | |
4747 | tcg_gen_ext32s_i64(t1, t0); | |
4748 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); | |
da91a00f RH |
4749 | tcg_gen_movi_tl(cpu_ov, 1); |
4750 | tcg_gen_movi_tl(cpu_so, 1); | |
22e0e173 AJ |
4751 | gen_set_label(l1); |
4752 | tcg_temp_free_i64(t0); | |
4753 | tcg_temp_free_i64(t1); | |
4754 | tcg_temp_free(t2); | |
76a66253 | 4755 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4756 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4757 | } |
4758 | ||
4759 | /* nabs - nabs. */ | |
99e300ef | 4760 | static void gen_nabs(DisasContext *ctx) |
76a66253 | 4761 | { |
42a268c2 RH |
4762 | TCGLabel *l1 = gen_new_label(); |
4763 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4764 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4765 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4766 | tcg_gen_br(l2); | |
4767 | gen_set_label(l1); | |
4768 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4769 | gen_set_label(l2); | |
76a66253 | 4770 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4771 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4772 | } |
4773 | ||
4774 | /* nabso - nabso. */ | |
99e300ef | 4775 | static void gen_nabso(DisasContext *ctx) |
76a66253 | 4776 | { |
42a268c2 RH |
4777 | TCGLabel *l1 = gen_new_label(); |
4778 | TCGLabel *l2 = gen_new_label(); | |
22e0e173 AJ |
4779 | tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1); |
4780 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4781 | tcg_gen_br(l2); | |
4782 | gen_set_label(l1); | |
4783 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); | |
4784 | gen_set_label(l2); | |
4785 | /* nabs never overflows */ | |
da91a00f | 4786 | tcg_gen_movi_tl(cpu_ov, 0); |
76a66253 | 4787 | if (unlikely(Rc(ctx->opcode) != 0)) |
22e0e173 | 4788 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
76a66253 JM |
4789 | } |
4790 | ||
4791 | /* rlmi - rlmi. */ | |
99e300ef | 4792 | static void gen_rlmi(DisasContext *ctx) |
76a66253 | 4793 | { |
7487953d AJ |
4794 | uint32_t mb = MB(ctx->opcode); |
4795 | uint32_t me = ME(ctx->opcode); | |
4796 | TCGv t0 = tcg_temp_new(); | |
4797 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4798 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4799 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); | |
4800 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me)); | |
4801 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); | |
4802 | tcg_temp_free(t0); | |
76a66253 | 4803 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4804 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4805 | } |
4806 | ||
4807 | /* rrib - rrib. */ | |
99e300ef | 4808 | static void gen_rrib(DisasContext *ctx) |
76a66253 | 4809 | { |
7487953d AJ |
4810 | TCGv t0 = tcg_temp_new(); |
4811 | TCGv t1 = tcg_temp_new(); | |
4812 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4813 | tcg_gen_movi_tl(t1, 0x80000000); | |
4814 | tcg_gen_shr_tl(t1, t1, t0); | |
4815 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4816 | tcg_gen_and_tl(t0, t0, t1); | |
4817 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); | |
4818 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4819 | tcg_temp_free(t0); | |
4820 | tcg_temp_free(t1); | |
76a66253 | 4821 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4822 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4823 | } |
4824 | ||
4825 | /* sle - sle. */ | |
99e300ef | 4826 | static void gen_sle(DisasContext *ctx) |
76a66253 | 4827 | { |
7487953d AJ |
4828 | TCGv t0 = tcg_temp_new(); |
4829 | TCGv t1 = tcg_temp_new(); | |
4830 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4831 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4832 | tcg_gen_subfi_tl(t1, 32, t1); | |
4833 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4834 | tcg_gen_or_tl(t1, t0, t1); | |
4835 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4836 | gen_store_spr(SPR_MQ, t1); | |
4837 | tcg_temp_free(t0); | |
4838 | tcg_temp_free(t1); | |
76a66253 | 4839 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4840 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4841 | } |
4842 | ||
4843 | /* sleq - sleq. */ | |
99e300ef | 4844 | static void gen_sleq(DisasContext *ctx) |
76a66253 | 4845 | { |
7487953d AJ |
4846 | TCGv t0 = tcg_temp_new(); |
4847 | TCGv t1 = tcg_temp_new(); | |
4848 | TCGv t2 = tcg_temp_new(); | |
4849 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4850 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); | |
4851 | tcg_gen_shl_tl(t2, t2, t0); | |
4852 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
4853 | gen_load_spr(t1, SPR_MQ); | |
4854 | gen_store_spr(SPR_MQ, t0); | |
4855 | tcg_gen_and_tl(t0, t0, t2); | |
4856 | tcg_gen_andc_tl(t1, t1, t2); | |
4857 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4858 | tcg_temp_free(t0); | |
4859 | tcg_temp_free(t1); | |
4860 | tcg_temp_free(t2); | |
76a66253 | 4861 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4862 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4863 | } |
4864 | ||
4865 | /* sliq - sliq. */ | |
99e300ef | 4866 | static void gen_sliq(DisasContext *ctx) |
76a66253 | 4867 | { |
7487953d AJ |
4868 | int sh = SH(ctx->opcode); |
4869 | TCGv t0 = tcg_temp_new(); | |
4870 | TCGv t1 = tcg_temp_new(); | |
4871 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4872 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4873 | tcg_gen_or_tl(t1, t0, t1); | |
4874 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4875 | gen_store_spr(SPR_MQ, t1); | |
4876 | tcg_temp_free(t0); | |
4877 | tcg_temp_free(t1); | |
76a66253 | 4878 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4879 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4880 | } |
4881 | ||
4882 | /* slliq - slliq. */ | |
99e300ef | 4883 | static void gen_slliq(DisasContext *ctx) |
76a66253 | 4884 | { |
7487953d AJ |
4885 | int sh = SH(ctx->opcode); |
4886 | TCGv t0 = tcg_temp_new(); | |
4887 | TCGv t1 = tcg_temp_new(); | |
4888 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4889 | gen_load_spr(t1, SPR_MQ); | |
4890 | gen_store_spr(SPR_MQ, t0); | |
4891 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); | |
4892 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); | |
4893 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4894 | tcg_temp_free(t0); | |
4895 | tcg_temp_free(t1); | |
76a66253 | 4896 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4897 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4898 | } |
4899 | ||
4900 | /* sllq - sllq. */ | |
99e300ef | 4901 | static void gen_sllq(DisasContext *ctx) |
76a66253 | 4902 | { |
42a268c2 RH |
4903 | TCGLabel *l1 = gen_new_label(); |
4904 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
4905 | TCGv t0 = tcg_temp_local_new(); |
4906 | TCGv t1 = tcg_temp_local_new(); | |
4907 | TCGv t2 = tcg_temp_local_new(); | |
4908 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4909 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
4910 | tcg_gen_shl_tl(t1, t1, t2); | |
4911 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4912 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
4913 | gen_load_spr(t0, SPR_MQ); | |
4914 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4915 | tcg_gen_br(l2); | |
4916 | gen_set_label(l1); | |
4917 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4918 | gen_load_spr(t2, SPR_MQ); | |
4919 | tcg_gen_andc_tl(t1, t2, t1); | |
4920 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
4921 | gen_set_label(l2); | |
4922 | tcg_temp_free(t0); | |
4923 | tcg_temp_free(t1); | |
4924 | tcg_temp_free(t2); | |
76a66253 | 4925 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4926 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4927 | } |
4928 | ||
4929 | /* slq - slq. */ | |
99e300ef | 4930 | static void gen_slq(DisasContext *ctx) |
76a66253 | 4931 | { |
42a268c2 | 4932 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
4933 | TCGv t0 = tcg_temp_new(); |
4934 | TCGv t1 = tcg_temp_new(); | |
4935 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4936 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
4937 | tcg_gen_subfi_tl(t1, 32, t1); | |
4938 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
4939 | tcg_gen_or_tl(t1, t0, t1); | |
4940 | gen_store_spr(SPR_MQ, t1); | |
4941 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4942 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
4943 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); | |
4944 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
4945 | gen_set_label(l1); | |
4946 | tcg_temp_free(t0); | |
4947 | tcg_temp_free(t1); | |
76a66253 | 4948 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4949 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4950 | } |
4951 | ||
d9bce9d9 | 4952 | /* sraiq - sraiq. */ |
99e300ef | 4953 | static void gen_sraiq(DisasContext *ctx) |
76a66253 | 4954 | { |
7487953d | 4955 | int sh = SH(ctx->opcode); |
42a268c2 | 4956 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
4957 | TCGv t0 = tcg_temp_new(); |
4958 | TCGv t1 = tcg_temp_new(); | |
4959 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
4960 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
4961 | tcg_gen_or_tl(t0, t0, t1); | |
4962 | gen_store_spr(SPR_MQ, t0); | |
da91a00f | 4963 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
4964 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
4965 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); | |
da91a00f | 4966 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
4967 | gen_set_label(l1); |
4968 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); | |
4969 | tcg_temp_free(t0); | |
4970 | tcg_temp_free(t1); | |
76a66253 | 4971 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 4972 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
4973 | } |
4974 | ||
4975 | /* sraq - sraq. */ | |
99e300ef | 4976 | static void gen_sraq(DisasContext *ctx) |
76a66253 | 4977 | { |
42a268c2 RH |
4978 | TCGLabel *l1 = gen_new_label(); |
4979 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
4980 | TCGv t0 = tcg_temp_new(); |
4981 | TCGv t1 = tcg_temp_local_new(); | |
4982 | TCGv t2 = tcg_temp_local_new(); | |
4983 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
4984 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
4985 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); | |
4986 | tcg_gen_subfi_tl(t2, 32, t2); | |
4987 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); | |
4988 | tcg_gen_or_tl(t0, t0, t2); | |
4989 | gen_store_spr(SPR_MQ, t0); | |
4990 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
4991 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); | |
4992 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); | |
4993 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); | |
4994 | gen_set_label(l1); | |
4995 | tcg_temp_free(t0); | |
4996 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); | |
da91a00f | 4997 | tcg_gen_movi_tl(cpu_ca, 0); |
7487953d AJ |
4998 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
4999 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); | |
da91a00f | 5000 | tcg_gen_movi_tl(cpu_ca, 1); |
7487953d AJ |
5001 | gen_set_label(l2); |
5002 | tcg_temp_free(t1); | |
5003 | tcg_temp_free(t2); | |
76a66253 | 5004 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5005 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5006 | } |
5007 | ||
5008 | /* sre - sre. */ | |
99e300ef | 5009 | static void gen_sre(DisasContext *ctx) |
76a66253 | 5010 | { |
7487953d AJ |
5011 | TCGv t0 = tcg_temp_new(); |
5012 | TCGv t1 = tcg_temp_new(); | |
5013 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5014 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5015 | tcg_gen_subfi_tl(t1, 32, t1); | |
5016 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5017 | tcg_gen_or_tl(t1, t0, t1); | |
5018 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5019 | gen_store_spr(SPR_MQ, t1); | |
5020 | tcg_temp_free(t0); | |
5021 | tcg_temp_free(t1); | |
76a66253 | 5022 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5023 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5024 | } |
5025 | ||
5026 | /* srea - srea. */ | |
99e300ef | 5027 | static void gen_srea(DisasContext *ctx) |
76a66253 | 5028 | { |
7487953d AJ |
5029 | TCGv t0 = tcg_temp_new(); |
5030 | TCGv t1 = tcg_temp_new(); | |
5031 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5032 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5033 | gen_store_spr(SPR_MQ, t0); | |
5034 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); | |
5035 | tcg_temp_free(t0); | |
5036 | tcg_temp_free(t1); | |
76a66253 | 5037 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5038 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5039 | } |
5040 | ||
5041 | /* sreq */ | |
99e300ef | 5042 | static void gen_sreq(DisasContext *ctx) |
76a66253 | 5043 | { |
7487953d AJ |
5044 | TCGv t0 = tcg_temp_new(); |
5045 | TCGv t1 = tcg_temp_new(); | |
5046 | TCGv t2 = tcg_temp_new(); | |
5047 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5048 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5049 | tcg_gen_shr_tl(t1, t1, t0); | |
5050 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); | |
5051 | gen_load_spr(t2, SPR_MQ); | |
5052 | gen_store_spr(SPR_MQ, t0); | |
5053 | tcg_gen_and_tl(t0, t0, t1); | |
5054 | tcg_gen_andc_tl(t2, t2, t1); | |
5055 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5056 | tcg_temp_free(t0); | |
5057 | tcg_temp_free(t1); | |
5058 | tcg_temp_free(t2); | |
76a66253 | 5059 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5060 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5061 | } |
5062 | ||
5063 | /* sriq */ | |
99e300ef | 5064 | static void gen_sriq(DisasContext *ctx) |
76a66253 | 5065 | { |
7487953d AJ |
5066 | int sh = SH(ctx->opcode); |
5067 | TCGv t0 = tcg_temp_new(); | |
5068 | TCGv t1 = tcg_temp_new(); | |
5069 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5070 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); | |
5071 | tcg_gen_or_tl(t1, t0, t1); | |
5072 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5073 | gen_store_spr(SPR_MQ, t1); | |
5074 | tcg_temp_free(t0); | |
5075 | tcg_temp_free(t1); | |
76a66253 | 5076 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5077 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5078 | } |
5079 | ||
5080 | /* srliq */ | |
99e300ef | 5081 | static void gen_srliq(DisasContext *ctx) |
76a66253 | 5082 | { |
7487953d AJ |
5083 | int sh = SH(ctx->opcode); |
5084 | TCGv t0 = tcg_temp_new(); | |
5085 | TCGv t1 = tcg_temp_new(); | |
5086 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); | |
5087 | gen_load_spr(t1, SPR_MQ); | |
5088 | gen_store_spr(SPR_MQ, t0); | |
5089 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); | |
5090 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); | |
5091 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5092 | tcg_temp_free(t0); | |
5093 | tcg_temp_free(t1); | |
76a66253 | 5094 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5095 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5096 | } |
5097 | ||
5098 | /* srlq */ | |
99e300ef | 5099 | static void gen_srlq(DisasContext *ctx) |
76a66253 | 5100 | { |
42a268c2 RH |
5101 | TCGLabel *l1 = gen_new_label(); |
5102 | TCGLabel *l2 = gen_new_label(); | |
7487953d AJ |
5103 | TCGv t0 = tcg_temp_local_new(); |
5104 | TCGv t1 = tcg_temp_local_new(); | |
5105 | TCGv t2 = tcg_temp_local_new(); | |
5106 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5107 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); | |
5108 | tcg_gen_shr_tl(t2, t1, t2); | |
5109 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5110 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5111 | gen_load_spr(t0, SPR_MQ); | |
5112 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); | |
5113 | tcg_gen_br(l2); | |
5114 | gen_set_label(l1); | |
5115 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); | |
5116 | tcg_gen_and_tl(t0, t0, t2); | |
5117 | gen_load_spr(t1, SPR_MQ); | |
5118 | tcg_gen_andc_tl(t1, t1, t2); | |
5119 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); | |
5120 | gen_set_label(l2); | |
5121 | tcg_temp_free(t0); | |
5122 | tcg_temp_free(t1); | |
5123 | tcg_temp_free(t2); | |
76a66253 | 5124 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5125 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5126 | } |
5127 | ||
5128 | /* srq */ | |
99e300ef | 5129 | static void gen_srq(DisasContext *ctx) |
76a66253 | 5130 | { |
42a268c2 | 5131 | TCGLabel *l1 = gen_new_label(); |
7487953d AJ |
5132 | TCGv t0 = tcg_temp_new(); |
5133 | TCGv t1 = tcg_temp_new(); | |
5134 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); | |
5135 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); | |
5136 | tcg_gen_subfi_tl(t1, 32, t1); | |
5137 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); | |
5138 | tcg_gen_or_tl(t1, t0, t1); | |
5139 | gen_store_spr(SPR_MQ, t1); | |
5140 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); | |
5141 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); | |
5142 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); | |
5143 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); | |
5144 | gen_set_label(l1); | |
5145 | tcg_temp_free(t0); | |
5146 | tcg_temp_free(t1); | |
76a66253 | 5147 | if (unlikely(Rc(ctx->opcode) != 0)) |
7487953d | 5148 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
76a66253 JM |
5149 | } |
5150 | ||
5151 | /* PowerPC 602 specific instructions */ | |
99e300ef | 5152 | |
54623277 | 5153 | /* dsa */ |
99e300ef | 5154 | static void gen_dsa(DisasContext *ctx) |
76a66253 JM |
5155 | { |
5156 | /* XXX: TODO */ | |
e06fcd75 | 5157 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5158 | } |
5159 | ||
5160 | /* esa */ | |
99e300ef | 5161 | static void gen_esa(DisasContext *ctx) |
76a66253 JM |
5162 | { |
5163 | /* XXX: TODO */ | |
e06fcd75 | 5164 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5165 | } |
5166 | ||
5167 | /* mfrom */ | |
99e300ef | 5168 | static void gen_mfrom(DisasContext *ctx) |
76a66253 JM |
5169 | { |
5170 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5171 | GEN_PRIV; |
76a66253 | 5172 | #else |
9b2fadda | 5173 | CHK_SV; |
cf02a65c | 5174 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
9b2fadda | 5175 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5176 | } |
5177 | ||
5178 | /* 602 - 603 - G2 TLB management */ | |
e8eaa2c0 | 5179 | |
54623277 | 5180 | /* tlbld */ |
e8eaa2c0 | 5181 | static void gen_tlbld_6xx(DisasContext *ctx) |
76a66253 JM |
5182 | { |
5183 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5184 | GEN_PRIV; |
76a66253 | 5185 | #else |
9b2fadda | 5186 | CHK_SV; |
c6c7cf05 | 5187 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5188 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5189 | } |
5190 | ||
5191 | /* tlbli */ | |
e8eaa2c0 | 5192 | static void gen_tlbli_6xx(DisasContext *ctx) |
76a66253 JM |
5193 | { |
5194 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5195 | GEN_PRIV; |
76a66253 | 5196 | #else |
9b2fadda | 5197 | CHK_SV; |
c6c7cf05 | 5198 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5199 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5200 | } |
5201 | ||
7dbe11ac | 5202 | /* 74xx TLB management */ |
e8eaa2c0 | 5203 | |
54623277 | 5204 | /* tlbld */ |
e8eaa2c0 | 5205 | static void gen_tlbld_74xx(DisasContext *ctx) |
7dbe11ac JM |
5206 | { |
5207 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5208 | GEN_PRIV; |
7dbe11ac | 5209 | #else |
9b2fadda | 5210 | CHK_SV; |
c6c7cf05 | 5211 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5212 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5213 | } |
5214 | ||
5215 | /* tlbli */ | |
e8eaa2c0 | 5216 | static void gen_tlbli_74xx(DisasContext *ctx) |
7dbe11ac JM |
5217 | { |
5218 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5219 | GEN_PRIV; |
7dbe11ac | 5220 | #else |
9b2fadda | 5221 | CHK_SV; |
c6c7cf05 | 5222 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 5223 | #endif /* defined(CONFIG_USER_ONLY) */ |
7dbe11ac JM |
5224 | } |
5225 | ||
76a66253 | 5226 | /* POWER instructions not in PowerPC 601 */ |
99e300ef | 5227 | |
54623277 | 5228 | /* clf */ |
99e300ef | 5229 | static void gen_clf(DisasContext *ctx) |
76a66253 JM |
5230 | { |
5231 | /* Cache line flush: implemented as no-op */ | |
5232 | } | |
5233 | ||
5234 | /* cli */ | |
99e300ef | 5235 | static void gen_cli(DisasContext *ctx) |
76a66253 | 5236 | { |
76a66253 | 5237 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5238 | GEN_PRIV; |
76a66253 | 5239 | #else |
9b2fadda BH |
5240 | /* Cache line invalidate: privileged and treated as no-op */ |
5241 | CHK_SV; | |
5242 | #endif /* defined(CONFIG_USER_ONLY) */ | |
76a66253 JM |
5243 | } |
5244 | ||
5245 | /* dclst */ | |
99e300ef | 5246 | static void gen_dclst(DisasContext *ctx) |
76a66253 JM |
5247 | { |
5248 | /* Data cache line store: treated as no-op */ | |
5249 | } | |
5250 | ||
99e300ef | 5251 | static void gen_mfsri(DisasContext *ctx) |
76a66253 JM |
5252 | { |
5253 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5254 | GEN_PRIV; |
76a66253 | 5255 | #else |
74d37793 AJ |
5256 | int ra = rA(ctx->opcode); |
5257 | int rd = rD(ctx->opcode); | |
5258 | TCGv t0; | |
9b2fadda BH |
5259 | |
5260 | CHK_SV; | |
74d37793 | 5261 | t0 = tcg_temp_new(); |
76db3ba4 | 5262 | gen_addr_reg_index(ctx, t0); |
74d37793 AJ |
5263 | tcg_gen_shri_tl(t0, t0, 28); |
5264 | tcg_gen_andi_tl(t0, t0, 0xF); | |
c6c7cf05 | 5265 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
74d37793 | 5266 | tcg_temp_free(t0); |
76a66253 | 5267 | if (ra != 0 && ra != rd) |
74d37793 | 5268 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
9b2fadda | 5269 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5270 | } |
5271 | ||
99e300ef | 5272 | static void gen_rac(DisasContext *ctx) |
76a66253 JM |
5273 | { |
5274 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5275 | GEN_PRIV; |
76a66253 | 5276 | #else |
22e0e173 | 5277 | TCGv t0; |
9b2fadda BH |
5278 | |
5279 | CHK_SV; | |
22e0e173 | 5280 | t0 = tcg_temp_new(); |
76db3ba4 | 5281 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5282 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
22e0e173 | 5283 | tcg_temp_free(t0); |
9b2fadda | 5284 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5285 | } |
5286 | ||
99e300ef | 5287 | static void gen_rfsvc(DisasContext *ctx) |
76a66253 JM |
5288 | { |
5289 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5290 | GEN_PRIV; |
76a66253 | 5291 | #else |
9b2fadda BH |
5292 | CHK_SV; |
5293 | ||
e5f17ac6 | 5294 | gen_helper_rfsvc(cpu_env); |
e06fcd75 | 5295 | gen_sync_exception(ctx); |
9b2fadda | 5296 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5297 | } |
5298 | ||
f9651121 | 5299 | /* svc is not implemented for now */ |
76a66253 JM |
5300 | |
5301 | /* BookE specific instructions */ | |
99e300ef | 5302 | |
54623277 | 5303 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5304 | static void gen_mfapidi(DisasContext *ctx) |
76a66253 JM |
5305 | { |
5306 | /* XXX: TODO */ | |
e06fcd75 | 5307 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 JM |
5308 | } |
5309 | ||
2662a059 | 5310 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5311 | static void gen_tlbiva(DisasContext *ctx) |
76a66253 JM |
5312 | { |
5313 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5314 | GEN_PRIV; |
76a66253 | 5315 | #else |
74d37793 | 5316 | TCGv t0; |
9b2fadda BH |
5317 | |
5318 | CHK_SV; | |
ec72e276 | 5319 | t0 = tcg_temp_new(); |
76db3ba4 | 5320 | gen_addr_reg_index(ctx, t0); |
4693364f | 5321 | gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
74d37793 | 5322 | tcg_temp_free(t0); |
9b2fadda | 5323 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5324 | } |
5325 | ||
5326 | /* All 405 MAC instructions are translated here */ | |
636aa200 BS |
5327 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5328 | int ra, int rb, int rt, int Rc) | |
76a66253 | 5329 | { |
182608d4 AJ |
5330 | TCGv t0, t1; |
5331 | ||
a7812ae4 PB |
5332 | t0 = tcg_temp_local_new(); |
5333 | t1 = tcg_temp_local_new(); | |
182608d4 | 5334 | |
76a66253 JM |
5335 | switch (opc3 & 0x0D) { |
5336 | case 0x05: | |
5337 | /* macchw - macchw. - macchwo - macchwo. */ | |
5338 | /* macchws - macchws. - macchwso - macchwso. */ | |
5339 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ | |
5340 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ | |
5341 | /* mulchw - mulchw. */ | |
182608d4 AJ |
5342 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5343 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5344 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5345 | break; |
5346 | case 0x04: | |
5347 | /* macchwu - macchwu. - macchwuo - macchwuo. */ | |
5348 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ | |
5349 | /* mulchwu - mulchwu. */ | |
182608d4 AJ |
5350 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5351 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5352 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5353 | break; |
5354 | case 0x01: | |
5355 | /* machhw - machhw. - machhwo - machhwo. */ | |
5356 | /* machhws - machhws. - machhwso - machhwso. */ | |
5357 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ | |
5358 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ | |
5359 | /* mulhhw - mulhhw. */ | |
182608d4 AJ |
5360 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5361 | tcg_gen_ext16s_tl(t0, t0); | |
5362 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); | |
5363 | tcg_gen_ext16s_tl(t1, t1); | |
76a66253 JM |
5364 | break; |
5365 | case 0x00: | |
5366 | /* machhwu - machhwu. - machhwuo - machhwuo. */ | |
5367 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ | |
5368 | /* mulhhwu - mulhhwu. */ | |
182608d4 AJ |
5369 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5370 | tcg_gen_ext16u_tl(t0, t0); | |
5371 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); | |
5372 | tcg_gen_ext16u_tl(t1, t1); | |
76a66253 JM |
5373 | break; |
5374 | case 0x0D: | |
5375 | /* maclhw - maclhw. - maclhwo - maclhwo. */ | |
5376 | /* maclhws - maclhws. - maclhwso - maclhwso. */ | |
5377 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ | |
5378 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ | |
5379 | /* mullhw - mullhw. */ | |
182608d4 AJ |
5380 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5381 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5382 | break; |
5383 | case 0x0C: | |
5384 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ | |
5385 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ | |
5386 | /* mullhwu - mullhwu. */ | |
182608d4 AJ |
5387 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5388 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); | |
76a66253 JM |
5389 | break; |
5390 | } | |
76a66253 | 5391 | if (opc2 & 0x04) { |
182608d4 AJ |
5392 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5393 | tcg_gen_mul_tl(t1, t0, t1); | |
5394 | if (opc2 & 0x02) { | |
5395 | /* nmultiply-and-accumulate (0x0E) */ | |
5396 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); | |
5397 | } else { | |
5398 | /* multiply-and-accumulate (0x0C) */ | |
5399 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); | |
5400 | } | |
5401 | ||
5402 | if (opc3 & 0x12) { | |
5403 | /* Check overflow and/or saturate */ | |
42a268c2 | 5404 | TCGLabel *l1 = gen_new_label(); |
182608d4 AJ |
5405 | |
5406 | if (opc3 & 0x10) { | |
5407 | /* Start with XER OV disabled, the most likely case */ | |
da91a00f | 5408 | tcg_gen_movi_tl(cpu_ov, 0); |
182608d4 AJ |
5409 | } |
5410 | if (opc3 & 0x01) { | |
5411 | /* Signed */ | |
5412 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); | |
5413 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); | |
5414 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); | |
5415 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); | |
bdc4e053 | 5416 | if (opc3 & 0x02) { |
182608d4 AJ |
5417 | /* Saturate */ |
5418 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); | |
5419 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); | |
5420 | } | |
5421 | } else { | |
5422 | /* Unsigned */ | |
5423 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); | |
bdc4e053 | 5424 | if (opc3 & 0x02) { |
182608d4 AJ |
5425 | /* Saturate */ |
5426 | tcg_gen_movi_tl(t0, UINT32_MAX); | |
5427 | } | |
5428 | } | |
5429 | if (opc3 & 0x10) { | |
5430 | /* Check overflow */ | |
da91a00f RH |
5431 | tcg_gen_movi_tl(cpu_ov, 1); |
5432 | tcg_gen_movi_tl(cpu_so, 1); | |
182608d4 AJ |
5433 | } |
5434 | gen_set_label(l1); | |
5435 | tcg_gen_mov_tl(cpu_gpr[rt], t0); | |
5436 | } | |
5437 | } else { | |
5438 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); | |
76a66253 | 5439 | } |
182608d4 AJ |
5440 | tcg_temp_free(t0); |
5441 | tcg_temp_free(t1); | |
76a66253 JM |
5442 | if (unlikely(Rc) != 0) { |
5443 | /* Update Rc0 */ | |
182608d4 | 5444 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
76a66253 JM |
5445 | } |
5446 | } | |
5447 | ||
a750fc0b | 5448 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
99e300ef | 5449 | static void glue(gen_, name)(DisasContext *ctx) \ |
76a66253 JM |
5450 | { \ |
5451 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ | |
5452 | rD(ctx->opcode), Rc(ctx->opcode)); \ | |
5453 | } | |
5454 | ||
5455 | /* macchw - macchw. */ | |
a750fc0b | 5456 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
76a66253 | 5457 | /* macchwo - macchwo. */ |
a750fc0b | 5458 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
76a66253 | 5459 | /* macchws - macchws. */ |
a750fc0b | 5460 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
76a66253 | 5461 | /* macchwso - macchwso. */ |
a750fc0b | 5462 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
76a66253 | 5463 | /* macchwsu - macchwsu. */ |
a750fc0b | 5464 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
76a66253 | 5465 | /* macchwsuo - macchwsuo. */ |
a750fc0b | 5466 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
76a66253 | 5467 | /* macchwu - macchwu. */ |
a750fc0b | 5468 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
76a66253 | 5469 | /* macchwuo - macchwuo. */ |
a750fc0b | 5470 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
76a66253 | 5471 | /* machhw - machhw. */ |
a750fc0b | 5472 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
76a66253 | 5473 | /* machhwo - machhwo. */ |
a750fc0b | 5474 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
76a66253 | 5475 | /* machhws - machhws. */ |
a750fc0b | 5476 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
76a66253 | 5477 | /* machhwso - machhwso. */ |
a750fc0b | 5478 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
76a66253 | 5479 | /* machhwsu - machhwsu. */ |
a750fc0b | 5480 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
76a66253 | 5481 | /* machhwsuo - machhwsuo. */ |
a750fc0b | 5482 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
76a66253 | 5483 | /* machhwu - machhwu. */ |
a750fc0b | 5484 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
76a66253 | 5485 | /* machhwuo - machhwuo. */ |
a750fc0b | 5486 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
76a66253 | 5487 | /* maclhw - maclhw. */ |
a750fc0b | 5488 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
76a66253 | 5489 | /* maclhwo - maclhwo. */ |
a750fc0b | 5490 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
76a66253 | 5491 | /* maclhws - maclhws. */ |
a750fc0b | 5492 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
76a66253 | 5493 | /* maclhwso - maclhwso. */ |
a750fc0b | 5494 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
76a66253 | 5495 | /* maclhwu - maclhwu. */ |
a750fc0b | 5496 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
76a66253 | 5497 | /* maclhwuo - maclhwuo. */ |
a750fc0b | 5498 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
76a66253 | 5499 | /* maclhwsu - maclhwsu. */ |
a750fc0b | 5500 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
76a66253 | 5501 | /* maclhwsuo - maclhwsuo. */ |
a750fc0b | 5502 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
76a66253 | 5503 | /* nmacchw - nmacchw. */ |
a750fc0b | 5504 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
76a66253 | 5505 | /* nmacchwo - nmacchwo. */ |
a750fc0b | 5506 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
76a66253 | 5507 | /* nmacchws - nmacchws. */ |
a750fc0b | 5508 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
76a66253 | 5509 | /* nmacchwso - nmacchwso. */ |
a750fc0b | 5510 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
76a66253 | 5511 | /* nmachhw - nmachhw. */ |
a750fc0b | 5512 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
76a66253 | 5513 | /* nmachhwo - nmachhwo. */ |
a750fc0b | 5514 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
76a66253 | 5515 | /* nmachhws - nmachhws. */ |
a750fc0b | 5516 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
76a66253 | 5517 | /* nmachhwso - nmachhwso. */ |
a750fc0b | 5518 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
76a66253 | 5519 | /* nmaclhw - nmaclhw. */ |
a750fc0b | 5520 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
76a66253 | 5521 | /* nmaclhwo - nmaclhwo. */ |
a750fc0b | 5522 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
76a66253 | 5523 | /* nmaclhws - nmaclhws. */ |
a750fc0b | 5524 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
76a66253 | 5525 | /* nmaclhwso - nmaclhwso. */ |
a750fc0b | 5526 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
76a66253 JM |
5527 | |
5528 | /* mulchw - mulchw. */ | |
a750fc0b | 5529 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
76a66253 | 5530 | /* mulchwu - mulchwu. */ |
a750fc0b | 5531 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
76a66253 | 5532 | /* mulhhw - mulhhw. */ |
a750fc0b | 5533 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
76a66253 | 5534 | /* mulhhwu - mulhhwu. */ |
a750fc0b | 5535 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
76a66253 | 5536 | /* mullhw - mullhw. */ |
a750fc0b | 5537 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
76a66253 | 5538 | /* mullhwu - mullhwu. */ |
a750fc0b | 5539 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
76a66253 JM |
5540 | |
5541 | /* mfdcr */ | |
99e300ef | 5542 | static void gen_mfdcr(DisasContext *ctx) |
76a66253 JM |
5543 | { |
5544 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5545 | GEN_PRIV; |
76a66253 | 5546 | #else |
06dca6a7 | 5547 | TCGv dcrn; |
9b2fadda BH |
5548 | |
5549 | CHK_SV; | |
06dca6a7 | 5550 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 5551 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
06dca6a7 | 5552 | tcg_temp_free(dcrn); |
9b2fadda | 5553 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5554 | } |
5555 | ||
5556 | /* mtdcr */ | |
99e300ef | 5557 | static void gen_mtdcr(DisasContext *ctx) |
76a66253 JM |
5558 | { |
5559 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5560 | GEN_PRIV; |
76a66253 | 5561 | #else |
06dca6a7 | 5562 | TCGv dcrn; |
9b2fadda BH |
5563 | |
5564 | CHK_SV; | |
06dca6a7 | 5565 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
d0f1562d | 5566 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
06dca6a7 | 5567 | tcg_temp_free(dcrn); |
9b2fadda | 5568 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5569 | } |
5570 | ||
5571 | /* mfdcrx */ | |
2662a059 | 5572 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5573 | static void gen_mfdcrx(DisasContext *ctx) |
a42bd6cc JM |
5574 | { |
5575 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5576 | GEN_PRIV; |
a42bd6cc | 5577 | #else |
9b2fadda | 5578 | CHK_SV; |
d0f1562d BS |
5579 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5580 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b | 5581 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5582 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5583 | } |
5584 | ||
5585 | /* mtdcrx */ | |
2662a059 | 5586 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5587 | static void gen_mtdcrx(DisasContext *ctx) |
a42bd6cc JM |
5588 | { |
5589 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5590 | GEN_PRIV; |
a42bd6cc | 5591 | #else |
9b2fadda | 5592 | CHK_SV; |
d0f1562d BS |
5593 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5594 | cpu_gpr[rS(ctx->opcode)]); | |
a750fc0b | 5595 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
9b2fadda | 5596 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5597 | } |
5598 | ||
a750fc0b | 5599 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
99e300ef | 5600 | static void gen_mfdcrux(DisasContext *ctx) |
a750fc0b | 5601 | { |
d0f1562d BS |
5602 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5603 | cpu_gpr[rA(ctx->opcode)]); | |
a750fc0b JM |
5604 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5605 | } | |
5606 | ||
5607 | /* mtdcrux (PPC 460) : user-mode access to DCR */ | |
99e300ef | 5608 | static void gen_mtdcrux(DisasContext *ctx) |
a750fc0b | 5609 | { |
975e5463 | 5610 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
d0f1562d | 5611 | cpu_gpr[rS(ctx->opcode)]); |
a750fc0b JM |
5612 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
5613 | } | |
5614 | ||
76a66253 | 5615 | /* dccci */ |
99e300ef | 5616 | static void gen_dccci(DisasContext *ctx) |
76a66253 | 5617 | { |
9b2fadda | 5618 | CHK_SV; |
76a66253 | 5619 | /* interpreted as no-op */ |
76a66253 JM |
5620 | } |
5621 | ||
5622 | /* dcread */ | |
99e300ef | 5623 | static void gen_dcread(DisasContext *ctx) |
76a66253 JM |
5624 | { |
5625 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5626 | GEN_PRIV; |
76a66253 | 5627 | #else |
b61f2753 | 5628 | TCGv EA, val; |
9b2fadda BH |
5629 | |
5630 | CHK_SV; | |
76db3ba4 | 5631 | gen_set_access_type(ctx, ACCESS_CACHE); |
a7812ae4 | 5632 | EA = tcg_temp_new(); |
76db3ba4 | 5633 | gen_addr_reg_index(ctx, EA); |
a7812ae4 | 5634 | val = tcg_temp_new(); |
76db3ba4 | 5635 | gen_qemu_ld32u(ctx, val, EA); |
b61f2753 AJ |
5636 | tcg_temp_free(val); |
5637 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); | |
5638 | tcg_temp_free(EA); | |
9b2fadda | 5639 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5640 | } |
5641 | ||
5642 | /* icbt */ | |
e8eaa2c0 | 5643 | static void gen_icbt_40x(DisasContext *ctx) |
76a66253 JM |
5644 | { |
5645 | /* interpreted as no-op */ | |
5646 | /* XXX: specification say this is treated as a load by the MMU | |
5647 | * but does not generate any exception | |
5648 | */ | |
5649 | } | |
5650 | ||
5651 | /* iccci */ | |
99e300ef | 5652 | static void gen_iccci(DisasContext *ctx) |
76a66253 | 5653 | { |
9b2fadda | 5654 | CHK_SV; |
76a66253 | 5655 | /* interpreted as no-op */ |
76a66253 JM |
5656 | } |
5657 | ||
5658 | /* icread */ | |
99e300ef | 5659 | static void gen_icread(DisasContext *ctx) |
76a66253 | 5660 | { |
9b2fadda | 5661 | CHK_SV; |
76a66253 | 5662 | /* interpreted as no-op */ |
76a66253 JM |
5663 | } |
5664 | ||
c47493f2 | 5665 | /* rfci (supervisor only) */ |
e8eaa2c0 | 5666 | static void gen_rfci_40x(DisasContext *ctx) |
a42bd6cc JM |
5667 | { |
5668 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5669 | GEN_PRIV; |
a42bd6cc | 5670 | #else |
9b2fadda | 5671 | CHK_SV; |
a42bd6cc | 5672 | /* Restore CPU state */ |
e5f17ac6 | 5673 | gen_helper_40x_rfci(cpu_env); |
e06fcd75 | 5674 | gen_sync_exception(ctx); |
9b2fadda | 5675 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5676 | } |
5677 | ||
99e300ef | 5678 | static void gen_rfci(DisasContext *ctx) |
a42bd6cc JM |
5679 | { |
5680 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5681 | GEN_PRIV; |
a42bd6cc | 5682 | #else |
9b2fadda | 5683 | CHK_SV; |
a42bd6cc | 5684 | /* Restore CPU state */ |
e5f17ac6 | 5685 | gen_helper_rfci(cpu_env); |
e06fcd75 | 5686 | gen_sync_exception(ctx); |
9b2fadda | 5687 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc JM |
5688 | } |
5689 | ||
5690 | /* BookE specific */ | |
99e300ef | 5691 | |
54623277 | 5692 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5693 | static void gen_rfdi(DisasContext *ctx) |
76a66253 JM |
5694 | { |
5695 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5696 | GEN_PRIV; |
76a66253 | 5697 | #else |
9b2fadda | 5698 | CHK_SV; |
76a66253 | 5699 | /* Restore CPU state */ |
e5f17ac6 | 5700 | gen_helper_rfdi(cpu_env); |
e06fcd75 | 5701 | gen_sync_exception(ctx); |
9b2fadda | 5702 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5703 | } |
5704 | ||
2662a059 | 5705 | /* XXX: not implemented on 440 ? */ |
99e300ef | 5706 | static void gen_rfmci(DisasContext *ctx) |
a42bd6cc JM |
5707 | { |
5708 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5709 | GEN_PRIV; |
a42bd6cc | 5710 | #else |
9b2fadda | 5711 | CHK_SV; |
a42bd6cc | 5712 | /* Restore CPU state */ |
e5f17ac6 | 5713 | gen_helper_rfmci(cpu_env); |
e06fcd75 | 5714 | gen_sync_exception(ctx); |
9b2fadda | 5715 | #endif /* defined(CONFIG_USER_ONLY) */ |
a42bd6cc | 5716 | } |
5eb7995e | 5717 | |
d9bce9d9 | 5718 | /* TLB management - PowerPC 405 implementation */ |
e8eaa2c0 | 5719 | |
54623277 | 5720 | /* tlbre */ |
e8eaa2c0 | 5721 | static void gen_tlbre_40x(DisasContext *ctx) |
76a66253 JM |
5722 | { |
5723 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5724 | GEN_PRIV; |
76a66253 | 5725 | #else |
9b2fadda | 5726 | CHK_SV; |
76a66253 JM |
5727 | switch (rB(ctx->opcode)) { |
5728 | case 0: | |
c6c7cf05 BS |
5729 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5730 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5731 | break; |
5732 | case 1: | |
c6c7cf05 BS |
5733 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5734 | cpu_gpr[rA(ctx->opcode)]); | |
76a66253 JM |
5735 | break; |
5736 | default: | |
e06fcd75 | 5737 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5738 | break; |
9a64fbe4 | 5739 | } |
9b2fadda | 5740 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5741 | } |
5742 | ||
d9bce9d9 | 5743 | /* tlbsx - tlbsx. */ |
e8eaa2c0 | 5744 | static void gen_tlbsx_40x(DisasContext *ctx) |
76a66253 JM |
5745 | { |
5746 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5747 | GEN_PRIV; |
76a66253 | 5748 | #else |
74d37793 | 5749 | TCGv t0; |
9b2fadda BH |
5750 | |
5751 | CHK_SV; | |
74d37793 | 5752 | t0 = tcg_temp_new(); |
76db3ba4 | 5753 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5754 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
5755 | tcg_temp_free(t0); |
5756 | if (Rc(ctx->opcode)) { | |
42a268c2 | 5757 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 5758 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5759 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5760 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5761 | gen_set_label(l1); | |
5762 | } | |
9b2fadda | 5763 | #endif /* defined(CONFIG_USER_ONLY) */ |
79aceca5 FB |
5764 | } |
5765 | ||
76a66253 | 5766 | /* tlbwe */ |
e8eaa2c0 | 5767 | static void gen_tlbwe_40x(DisasContext *ctx) |
79aceca5 | 5768 | { |
76a66253 | 5769 | #if defined(CONFIG_USER_ONLY) |
9b2fadda | 5770 | GEN_PRIV; |
76a66253 | 5771 | #else |
9b2fadda BH |
5772 | CHK_SV; |
5773 | ||
76a66253 JM |
5774 | switch (rB(ctx->opcode)) { |
5775 | case 0: | |
c6c7cf05 BS |
5776 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5777 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5778 | break; |
5779 | case 1: | |
c6c7cf05 BS |
5780 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
5781 | cpu_gpr[rS(ctx->opcode)]); | |
76a66253 JM |
5782 | break; |
5783 | default: | |
e06fcd75 | 5784 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
76a66253 | 5785 | break; |
9a64fbe4 | 5786 | } |
9b2fadda | 5787 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5788 | } |
5789 | ||
a4bb6c3e | 5790 | /* TLB management - PowerPC 440 implementation */ |
e8eaa2c0 | 5791 | |
54623277 | 5792 | /* tlbre */ |
e8eaa2c0 | 5793 | static void gen_tlbre_440(DisasContext *ctx) |
5eb7995e JM |
5794 | { |
5795 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5796 | GEN_PRIV; |
5eb7995e | 5797 | #else |
9b2fadda BH |
5798 | CHK_SV; |
5799 | ||
5eb7995e JM |
5800 | switch (rB(ctx->opcode)) { |
5801 | case 0: | |
5eb7995e | 5802 | case 1: |
5eb7995e | 5803 | case 2: |
74d37793 AJ |
5804 | { |
5805 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
5806 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5807 | t0, cpu_gpr[rA(ctx->opcode)]); | |
74d37793 AJ |
5808 | tcg_temp_free_i32(t0); |
5809 | } | |
5eb7995e JM |
5810 | break; |
5811 | default: | |
e06fcd75 | 5812 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5813 | break; |
5814 | } | |
9b2fadda | 5815 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
5816 | } |
5817 | ||
5818 | /* tlbsx - tlbsx. */ | |
e8eaa2c0 | 5819 | static void gen_tlbsx_440(DisasContext *ctx) |
5eb7995e JM |
5820 | { |
5821 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5822 | GEN_PRIV; |
5eb7995e | 5823 | #else |
74d37793 | 5824 | TCGv t0; |
9b2fadda BH |
5825 | |
5826 | CHK_SV; | |
74d37793 | 5827 | t0 = tcg_temp_new(); |
76db3ba4 | 5828 | gen_addr_reg_index(ctx, t0); |
c6c7cf05 | 5829 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
74d37793 AJ |
5830 | tcg_temp_free(t0); |
5831 | if (Rc(ctx->opcode)) { | |
42a268c2 | 5832 | TCGLabel *l1 = gen_new_label(); |
da91a00f | 5833 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
74d37793 AJ |
5834 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
5835 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); | |
5836 | gen_set_label(l1); | |
5837 | } | |
9b2fadda | 5838 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
5839 | } |
5840 | ||
5841 | /* tlbwe */ | |
e8eaa2c0 | 5842 | static void gen_tlbwe_440(DisasContext *ctx) |
5eb7995e JM |
5843 | { |
5844 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5845 | GEN_PRIV; |
5eb7995e | 5846 | #else |
9b2fadda | 5847 | CHK_SV; |
5eb7995e JM |
5848 | switch (rB(ctx->opcode)) { |
5849 | case 0: | |
5eb7995e | 5850 | case 1: |
5eb7995e | 5851 | case 2: |
74d37793 AJ |
5852 | { |
5853 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); | |
c6c7cf05 BS |
5854 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
5855 | cpu_gpr[rS(ctx->opcode)]); | |
74d37793 AJ |
5856 | tcg_temp_free_i32(t0); |
5857 | } | |
5eb7995e JM |
5858 | break; |
5859 | default: | |
e06fcd75 | 5860 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5eb7995e JM |
5861 | break; |
5862 | } | |
9b2fadda | 5863 | #endif /* defined(CONFIG_USER_ONLY) */ |
5eb7995e JM |
5864 | } |
5865 | ||
01662f3e AG |
5866 | /* TLB management - PowerPC BookE 2.06 implementation */ |
5867 | ||
5868 | /* tlbre */ | |
5869 | static void gen_tlbre_booke206(DisasContext *ctx) | |
5870 | { | |
9b2fadda BH |
5871 | #if defined(CONFIG_USER_ONLY) |
5872 | GEN_PRIV; | |
01662f3e | 5873 | #else |
9b2fadda | 5874 | CHK_SV; |
c6c7cf05 | 5875 | gen_helper_booke206_tlbre(cpu_env); |
9b2fadda | 5876 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5877 | } |
5878 | ||
5879 | /* tlbsx - tlbsx. */ | |
5880 | static void gen_tlbsx_booke206(DisasContext *ctx) | |
5881 | { | |
5882 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5883 | GEN_PRIV; |
01662f3e AG |
5884 | #else |
5885 | TCGv t0; | |
01662f3e | 5886 | |
9b2fadda | 5887 | CHK_SV; |
01662f3e AG |
5888 | if (rA(ctx->opcode)) { |
5889 | t0 = tcg_temp_new(); | |
5890 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); | |
5891 | } else { | |
5892 | t0 = tcg_const_tl(0); | |
5893 | } | |
5894 | ||
5895 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); | |
c6c7cf05 | 5896 | gen_helper_booke206_tlbsx(cpu_env, t0); |
c80d1df5 | 5897 | tcg_temp_free(t0); |
9b2fadda | 5898 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5899 | } |
5900 | ||
5901 | /* tlbwe */ | |
5902 | static void gen_tlbwe_booke206(DisasContext *ctx) | |
5903 | { | |
5904 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5905 | GEN_PRIV; |
01662f3e | 5906 | #else |
9b2fadda | 5907 | CHK_SV; |
c6c7cf05 | 5908 | gen_helper_booke206_tlbwe(cpu_env); |
9b2fadda | 5909 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5910 | } |
5911 | ||
5912 | static void gen_tlbivax_booke206(DisasContext *ctx) | |
5913 | { | |
5914 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5915 | GEN_PRIV; |
01662f3e AG |
5916 | #else |
5917 | TCGv t0; | |
01662f3e | 5918 | |
9b2fadda | 5919 | CHK_SV; |
01662f3e AG |
5920 | t0 = tcg_temp_new(); |
5921 | gen_addr_reg_index(ctx, t0); | |
c6c7cf05 | 5922 | gen_helper_booke206_tlbivax(cpu_env, t0); |
c80d1df5 | 5923 | tcg_temp_free(t0); |
9b2fadda | 5924 | #endif /* defined(CONFIG_USER_ONLY) */ |
01662f3e AG |
5925 | } |
5926 | ||
6d3db821 AG |
5927 | static void gen_tlbilx_booke206(DisasContext *ctx) |
5928 | { | |
5929 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5930 | GEN_PRIV; |
6d3db821 AG |
5931 | #else |
5932 | TCGv t0; | |
6d3db821 | 5933 | |
9b2fadda | 5934 | CHK_SV; |
6d3db821 AG |
5935 | t0 = tcg_temp_new(); |
5936 | gen_addr_reg_index(ctx, t0); | |
5937 | ||
5938 | switch((ctx->opcode >> 21) & 0x3) { | |
5939 | case 0: | |
c6c7cf05 | 5940 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6d3db821 AG |
5941 | break; |
5942 | case 1: | |
c6c7cf05 | 5943 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6d3db821 AG |
5944 | break; |
5945 | case 3: | |
c6c7cf05 | 5946 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6d3db821 AG |
5947 | break; |
5948 | default: | |
5949 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); | |
5950 | break; | |
5951 | } | |
5952 | ||
5953 | tcg_temp_free(t0); | |
9b2fadda | 5954 | #endif /* defined(CONFIG_USER_ONLY) */ |
6d3db821 AG |
5955 | } |
5956 | ||
01662f3e | 5957 | |
76a66253 | 5958 | /* wrtee */ |
99e300ef | 5959 | static void gen_wrtee(DisasContext *ctx) |
76a66253 JM |
5960 | { |
5961 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5962 | GEN_PRIV; |
76a66253 | 5963 | #else |
6527f6ea | 5964 | TCGv t0; |
9b2fadda BH |
5965 | |
5966 | CHK_SV; | |
6527f6ea AJ |
5967 | t0 = tcg_temp_new(); |
5968 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); | |
5969 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); | |
5970 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); | |
5971 | tcg_temp_free(t0); | |
dee96f6c JM |
5972 | /* Stop translation to have a chance to raise an exception |
5973 | * if we just set msr_ee to 1 | |
5974 | */ | |
e06fcd75 | 5975 | gen_stop_exception(ctx); |
9b2fadda | 5976 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5977 | } |
5978 | ||
5979 | /* wrteei */ | |
99e300ef | 5980 | static void gen_wrteei(DisasContext *ctx) |
76a66253 JM |
5981 | { |
5982 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 5983 | GEN_PRIV; |
76a66253 | 5984 | #else |
9b2fadda | 5985 | CHK_SV; |
fbe73008 | 5986 | if (ctx->opcode & 0x00008000) { |
6527f6ea AJ |
5987 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
5988 | /* Stop translation to have a chance to raise an exception */ | |
e06fcd75 | 5989 | gen_stop_exception(ctx); |
6527f6ea | 5990 | } else { |
1b6e5f99 | 5991 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6527f6ea | 5992 | } |
9b2fadda | 5993 | #endif /* defined(CONFIG_USER_ONLY) */ |
76a66253 JM |
5994 | } |
5995 | ||
08e46e54 | 5996 | /* PowerPC 440 specific instructions */ |
99e300ef | 5997 | |
54623277 | 5998 | /* dlmzb */ |
99e300ef | 5999 | static void gen_dlmzb(DisasContext *ctx) |
76a66253 | 6000 | { |
ef0d51af | 6001 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
d15f74fb BS |
6002 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6003 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); | |
ef0d51af | 6004 | tcg_temp_free_i32(t0); |
76a66253 JM |
6005 | } |
6006 | ||
6007 | /* mbar replaces eieio on 440 */ | |
99e300ef | 6008 | static void gen_mbar(DisasContext *ctx) |
76a66253 JM |
6009 | { |
6010 | /* interpreted as no-op */ | |
6011 | } | |
6012 | ||
6013 | /* msync replaces sync on 440 */ | |
dcb2b9e1 | 6014 | static void gen_msync_4xx(DisasContext *ctx) |
76a66253 JM |
6015 | { |
6016 | /* interpreted as no-op */ | |
6017 | } | |
6018 | ||
6019 | /* icbt */ | |
e8eaa2c0 | 6020 | static void gen_icbt_440(DisasContext *ctx) |
76a66253 JM |
6021 | { |
6022 | /* interpreted as no-op */ | |
6023 | /* XXX: specification say this is treated as a load by the MMU | |
6024 | * but does not generate any exception | |
6025 | */ | |
79aceca5 FB |
6026 | } |
6027 | ||
9e0b5cb1 AG |
6028 | /* Embedded.Processor Control */ |
6029 | ||
6030 | static void gen_msgclr(DisasContext *ctx) | |
6031 | { | |
6032 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6033 | GEN_PRIV; |
9e0b5cb1 | 6034 | #else |
9b2fadda | 6035 | CHK_SV; |
e5f17ac6 | 6036 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 6037 | #endif /* defined(CONFIG_USER_ONLY) */ |
9e0b5cb1 AG |
6038 | } |
6039 | ||
d5d11a39 AG |
6040 | static void gen_msgsnd(DisasContext *ctx) |
6041 | { | |
6042 | #if defined(CONFIG_USER_ONLY) | |
9b2fadda | 6043 | GEN_PRIV; |
d5d11a39 | 6044 | #else |
9b2fadda | 6045 | CHK_SV; |
d5d11a39 | 6046 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); |
9b2fadda | 6047 | #endif /* defined(CONFIG_USER_ONLY) */ |
d5d11a39 AG |
6048 | } |
6049 | ||
b04ae981 | 6050 | |
aeeb044c ND |
6051 | #if defined(TARGET_PPC64) |
6052 | static void gen_maddld(DisasContext *ctx) | |
6053 | { | |
6054 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6055 | ||
6056 | tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); | |
6057 | tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); | |
6058 | tcg_temp_free_i64(t1); | |
6059 | } | |
5f29cc82 ND |
6060 | |
6061 | /* maddhd maddhdu */ | |
6062 | static void gen_maddhd_maddhdu(DisasContext *ctx) | |
6063 | { | |
6064 | TCGv_i64 lo = tcg_temp_new_i64(); | |
6065 | TCGv_i64 hi = tcg_temp_new_i64(); | |
6066 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
6067 | ||
6068 | if (Rc(ctx->opcode)) { | |
6069 | tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6070 | cpu_gpr[rB(ctx->opcode)]); | |
6071 | tcg_gen_movi_i64(t1, 0); | |
6072 | } else { | |
6073 | tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], | |
6074 | cpu_gpr[rB(ctx->opcode)]); | |
6075 | tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); | |
6076 | } | |
6077 | tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, | |
6078 | cpu_gpr[rC(ctx->opcode)], t1); | |
6079 | tcg_temp_free_i64(lo); | |
6080 | tcg_temp_free_i64(hi); | |
6081 | tcg_temp_free_i64(t1); | |
6082 | } | |
aeeb044c ND |
6083 | #endif /* defined(TARGET_PPC64) */ |
6084 | ||
0ff93d11 TM |
6085 | static void gen_tbegin(DisasContext *ctx) |
6086 | { | |
6087 | if (unlikely(!ctx->tm_enabled)) { | |
6088 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6089 | return; | |
6090 | } | |
6091 | gen_helper_tbegin(cpu_env); | |
6092 | } | |
6093 | ||
56a84615 TM |
6094 | #define GEN_TM_NOOP(name) \ |
6095 | static inline void gen_##name(DisasContext *ctx) \ | |
6096 | { \ | |
6097 | if (unlikely(!ctx->tm_enabled)) { \ | |
6098 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6099 | return; \ | |
6100 | } \ | |
6101 | /* Because tbegin always fails in QEMU, these user \ | |
6102 | * space instructions all have a simple implementation: \ | |
6103 | * \ | |
6104 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6105 | * = 0b0 || 0b00 || 0b0 \ | |
6106 | */ \ | |
6107 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6108 | } | |
6109 | ||
6110 | GEN_TM_NOOP(tend); | |
6111 | GEN_TM_NOOP(tabort); | |
6112 | GEN_TM_NOOP(tabortwc); | |
6113 | GEN_TM_NOOP(tabortwci); | |
6114 | GEN_TM_NOOP(tabortdc); | |
6115 | GEN_TM_NOOP(tabortdci); | |
6116 | GEN_TM_NOOP(tsr); | |
6117 | ||
aeedd582 TM |
6118 | static void gen_tcheck(DisasContext *ctx) |
6119 | { | |
6120 | if (unlikely(!ctx->tm_enabled)) { | |
6121 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); | |
6122 | return; | |
6123 | } | |
6124 | /* Because tbegin always fails, the tcheck implementation | |
6125 | * is simple: | |
6126 | * | |
6127 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 | |
6128 | * = 0b1 || 0b00 || 0b0 | |
6129 | */ | |
6130 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); | |
6131 | } | |
6132 | ||
f83c2378 TM |
6133 | #if defined(CONFIG_USER_ONLY) |
6134 | #define GEN_TM_PRIV_NOOP(name) \ | |
6135 | static inline void gen_##name(DisasContext *ctx) \ | |
6136 | { \ | |
9b2fadda | 6137 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ |
f83c2378 TM |
6138 | } |
6139 | ||
6140 | #else | |
6141 | ||
6142 | #define GEN_TM_PRIV_NOOP(name) \ | |
6143 | static inline void gen_##name(DisasContext *ctx) \ | |
6144 | { \ | |
9b2fadda | 6145 | CHK_SV; \ |
f83c2378 TM |
6146 | if (unlikely(!ctx->tm_enabled)) { \ |
6147 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ | |
6148 | return; \ | |
6149 | } \ | |
6150 | /* Because tbegin always fails, the implementation is \ | |
6151 | * simple: \ | |
6152 | * \ | |
6153 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ | |
6154 | * = 0b0 || 0b00 | 0b0 \ | |
6155 | */ \ | |
6156 | tcg_gen_movi_i32(cpu_crf[0], 0); \ | |
6157 | } | |
6158 | ||
6159 | #endif | |
6160 | ||
6161 | GEN_TM_PRIV_NOOP(treclaim); | |
6162 | GEN_TM_PRIV_NOOP(trechkpt); | |
6163 | ||
15848410 BH |
6164 | #include "translate/fp-impl.inc.c" |
6165 | ||
6166 | #include "translate/vmx-impl.inc.c" | |
6167 | ||
6168 | #include "translate/vsx-impl.inc.c" | |
6169 | ||
6170 | #include "translate/dfp-impl.inc.c" | |
6171 | ||
6172 | #include "translate/spe-impl.inc.c" | |
6173 | ||
c227f099 | 6174 | static opcode_t opcodes[] = { |
5c55ff99 BS |
6175 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
6176 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), | |
6177 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
6178 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER), | |
6179 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), | |
082ce330 ND |
6180 | #if defined(TARGET_PPC64) |
6181 | GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), | |
6182 | #endif | |
fcfda20f | 6183 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
f2442ef9 | 6184 | GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6185 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
6186 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6187 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6188 | GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6189 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
c5b2b9ce | 6190 | GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6191 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
6192 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), | |
6193 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), | |
6194 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), | |
6195 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6196 | #if defined(TARGET_PPC64) | |
6197 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), | |
6198 | #endif | |
6199 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), | |
6200 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), | |
6201 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6202 | GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6203 | GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6204 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), | |
b35344e4 | 6205 | GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), |
5c55ff99 BS |
6206 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
6207 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), | |
6208 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6209 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6210 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6211 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6ab39b1b | 6212 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
eaabeef2 | 6213 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
725bcec2 | 6214 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
5c55ff99 | 6215 | #if defined(TARGET_PPC64) |
eaabeef2 | 6216 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
5c55ff99 | 6217 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
e91d95b2 | 6218 | GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), |
725bcec2 | 6219 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
86ba37ed | 6220 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
5c55ff99 BS |
6221 | #endif |
6222 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6223 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6224 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6225 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), | |
6226 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), | |
6227 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), | |
6228 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), | |
6229 | #if defined(TARGET_PPC64) | |
6230 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), | |
6231 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), | |
6232 | GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), | |
6233 | GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), | |
6234 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), | |
787bbe37 ND |
6235 | GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000, |
6236 | PPC_NONE, PPC2_ISA300), | |
6237 | GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, | |
6238 | PPC_NONE, PPC2_ISA300), | |
5c55ff99 | 6239 | #endif |
5c55ff99 BS |
6240 | #if defined(TARGET_PPC64) |
6241 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6242 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), | |
6243 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6244 | #endif | |
6245 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6246 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), | |
6247 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), | |
6248 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), | |
6249 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), | |
6250 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), | |
6251 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO), | |
6252 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), | |
5c77a786 TM |
6253 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6254 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
f844c817 | 6255 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
587c51f7 TM |
6256 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6257 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), | |
5c55ff99 BS |
6258 | GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
6259 | #if defined(TARGET_PPC64) | |
f844c817 | 6260 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
9c294d5a | 6261 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 | 6262 | GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
27b95bfe | 6263 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
5c55ff99 BS |
6264 | #endif |
6265 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), | |
6266 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), | |
6267 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6268 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6269 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), | |
6270 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), | |
52a4984d | 6271 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207), |
5c55ff99 BS |
6272 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
6273 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), | |
6274 | #if defined(TARGET_PPC64) | |
6275 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), | |
7778a575 BH |
6276 | GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
6277 | GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6278 | GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
6279 | GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), | |
5c55ff99 BS |
6280 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
6281 | #endif | |
6282 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), | |
6283 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), | |
6284 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), | |
6285 | #if defined(TARGET_PPC64) | |
6286 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), | |
6287 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), | |
6288 | #endif | |
6289 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), | |
6290 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), | |
6291 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), | |
6292 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), | |
6293 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), | |
6294 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), | |
6295 | #if defined(TARGET_PPC64) | |
6296 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), | |
dc2ee038 | 6297 | GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), |
5c55ff99 | 6298 | #endif |
5e31867f | 6299 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), |
4248b336 | 6300 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |
5c55ff99 BS |
6301 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
6302 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), | |
6303 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), | |
3f34cf91 CLG |
6304 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
6305 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), | |
4d09d529 | 6306 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
8e33944f | 6307 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
5c55ff99 BS |
6308 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
6309 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), | |
6310 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), | |
6311 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), | |
6312 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), | |
6313 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), | |
6314 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), | |
6315 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), | |
6316 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), | |
6317 | #if defined(TARGET_PPC64) | |
6318 | GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), | |
6319 | GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001, | |
6320 | PPC_SEGMENT_64B), | |
6321 | GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), | |
6322 | GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001, | |
6323 | PPC_SEGMENT_64B), | |
efdef95f DG |
6324 | GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
6325 | GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), | |
6326 | GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), | |
c76c22d5 | 6327 | GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), |
5c55ff99 BS |
6328 | #endif |
6329 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), | |
f9ef0527 BH |
6330 | /* XXX Those instructions will need to be handled differently for |
6331 | * different ISA versions */ | |
6332 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), | |
6333 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), | |
5c55ff99 BS |
6334 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
6335 | #if defined(TARGET_PPC64) | |
2f9254d9 | 6336 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), |
5c55ff99 BS |
6337 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
6338 | #endif | |
6339 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), | |
6340 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), | |
6341 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), | |
6342 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), | |
6343 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), | |
6344 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), | |
6345 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), | |
6346 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), | |
6347 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), | |
6348 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), | |
6349 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), | |
6350 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
6351 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), | |
6352 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), | |
6353 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), | |
6354 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), | |
6355 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), | |
6356 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), | |
6357 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), | |
6358 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), | |
6359 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), | |
6360 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), | |
6361 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), | |
6362 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), | |
6363 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), | |
6364 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), | |
6365 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), | |
6366 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), | |
6367 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), | |
6368 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), | |
6369 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), | |
6370 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), | |
6371 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), | |
6372 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), | |
6373 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), | |
6374 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), | |
6375 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), | |
6376 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), | |
6377 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), | |
6378 | GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), | |
6379 | GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), | |
6380 | GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), | |
6381 | GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), | |
6382 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), | |
6383 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), | |
6384 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), | |
6385 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), | |
6386 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), | |
6387 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), | |
6388 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6389 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6390 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), | |
6391 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), | |
6392 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6393 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), | |
6394 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), | |
6395 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), | |
6396 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), | |
6397 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), | |
6398 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), | |
6399 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), | |
6400 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), | |
6401 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), | |
6402 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), | |
6403 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), | |
6404 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), | |
6405 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), | |
6406 | GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), | |
6407 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), | |
6408 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), | |
6409 | GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), | |
01662f3e | 6410 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
5c55ff99 BS |
6411 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
6412 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), | |
6413 | GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), | |
6414 | GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), | |
6415 | GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), | |
6416 | GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), | |
6417 | GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), | |
6418 | GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), | |
01662f3e AG |
6419 | GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, |
6420 | PPC_NONE, PPC2_BOOKE206), | |
6421 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, | |
6422 | PPC_NONE, PPC2_BOOKE206), | |
6423 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, | |
6424 | PPC_NONE, PPC2_BOOKE206), | |
6425 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001, | |
6426 | PPC_NONE, PPC2_BOOKE206), | |
6d3db821 AG |
6427 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001, |
6428 | PPC_NONE, PPC2_BOOKE206), | |
d5d11a39 AG |
6429 | GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001, |
6430 | PPC_NONE, PPC2_PRCNTL), | |
9e0b5cb1 AG |
6431 | GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001, |
6432 | PPC_NONE, PPC2_PRCNTL), | |
5c55ff99 | 6433 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
fbe73008 | 6434 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
5c55ff99 | 6435 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
01662f3e AG |
6436 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
6437 | PPC_BOOKE, PPC2_BOOKE206), | |
dcb2b9e1 | 6438 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), |
01662f3e AG |
6439 | GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, |
6440 | PPC_BOOKE, PPC2_BOOKE206), | |
5c55ff99 BS |
6441 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
6442 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), | |
6443 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), | |
6444 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), | |
5c55ff99 | 6445 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
aeeb044c | 6446 | #if defined(TARGET_PPC64) |
5f29cc82 ND |
6447 | GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, |
6448 | PPC2_ISA300), | |
aeeb044c ND |
6449 | GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
6450 | #endif | |
5c55ff99 BS |
6451 | |
6452 | #undef GEN_INT_ARITH_ADD | |
6453 | #undef GEN_INT_ARITH_ADD_CONST | |
6454 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6455 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), | |
6456 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ | |
6457 | add_ca, compute_ca, compute_ov) \ | |
6458 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), | |
6459 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) | |
6460 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) | |
6461 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) | |
6462 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) | |
6463 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) | |
6464 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) | |
6465 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) | |
6466 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) | |
6467 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) | |
6468 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) | |
6469 | ||
6470 | #undef GEN_INT_ARITH_DIVW | |
6471 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ | |
6472 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) | |
6473 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), | |
6474 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), | |
6475 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), | |
6476 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), | |
a98eb9e9 TM |
6477 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6478 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
6a4fda33 TM |
6479 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6480 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
af2c6620 ND |
6481 | GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6482 | GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
5c55ff99 BS |
6483 | |
6484 | #if defined(TARGET_PPC64) | |
6485 | #undef GEN_INT_ARITH_DIVD | |
6486 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ | |
6487 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6488 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), | |
6489 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), | |
6490 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), | |
6491 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), | |
6492 | ||
98d1eb27 TM |
6493 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6494 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
e44259b6 TM |
6495 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
6496 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), | |
063cf14f ND |
6497 | GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
6498 | GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), | |
98d1eb27 | 6499 | |
5c55ff99 BS |
6500 | #undef GEN_INT_ARITH_MUL_HELPER |
6501 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ | |
6502 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) | |
6503 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), | |
6504 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), | |
6505 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), | |
6506 | #endif | |
6507 | ||
6508 | #undef GEN_INT_ARITH_SUBF | |
6509 | #undef GEN_INT_ARITH_SUBF_CONST | |
6510 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ | |
6511 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), | |
6512 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ | |
6513 | add_ca, compute_ca, compute_ov) \ | |
6514 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), | |
6515 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) | |
6516 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) | |
6517 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) | |
6518 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) | |
6519 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) | |
6520 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) | |
6521 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) | |
6522 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) | |
6523 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) | |
6524 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) | |
6525 | ||
6526 | #undef GEN_LOGICAL1 | |
6527 | #undef GEN_LOGICAL2 | |
6528 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ | |
6529 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) | |
6530 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ | |
6531 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) | |
6532 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), | |
6533 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), | |
6534 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), | |
6535 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), | |
6536 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), | |
6537 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), | |
6538 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), | |
6539 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), | |
6540 | #if defined(TARGET_PPC64) | |
6541 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), | |
6542 | #endif | |
6543 | ||
6544 | #if defined(TARGET_PPC64) | |
6545 | #undef GEN_PPC64_R2 | |
6546 | #undef GEN_PPC64_R4 | |
6547 | #define GEN_PPC64_R2(name, opc1, opc2) \ | |
6548 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6549 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6550 | PPC_64B) | |
6551 | #define GEN_PPC64_R4(name, opc1, opc2) \ | |
6552 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ | |
6553 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ | |
6554 | PPC_64B), \ | |
6555 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ | |
6556 | PPC_64B), \ | |
6557 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ | |
6558 | PPC_64B) | |
6559 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), | |
6560 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), | |
6561 | GEN_PPC64_R4(rldic, 0x1E, 0x04), | |
6562 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), | |
6563 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), | |
6564 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), | |
6565 | #endif | |
6566 | ||
5c55ff99 BS |
6567 | #undef GEN_LD |
6568 | #undef GEN_LDU | |
6569 | #undef GEN_LDUX | |
cd6e9320 | 6570 | #undef GEN_LDX_E |
5c55ff99 BS |
6571 | #undef GEN_LDS |
6572 | #define GEN_LD(name, ldop, opc, type) \ | |
6573 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
6574 | #define GEN_LDU(name, ldop, opc, type) \ | |
6575 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
6576 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ | |
6577 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 6578 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 6579 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
6580 | #define GEN_LDS(name, ldop, op, type) \ |
6581 | GEN_LD(name, ldop, op | 0x20, type) \ | |
6582 | GEN_LDU(name, ldop, op | 0x21, type) \ | |
6583 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ | |
6584 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) | |
6585 | ||
6586 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) | |
6587 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) | |
6588 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) | |
6589 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) | |
6590 | #if defined(TARGET_PPC64) | |
6591 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) | |
6592 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) | |
4f364fe7 ND |
6593 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) |
6594 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) | |
ff5f3981 | 6595 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) |
b7815375 BH |
6596 | |
6597 | /* HV/P7 and later only */ | |
4f364fe7 | 6598 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
b7815375 BH |
6599 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) |
6600 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) | |
6601 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) | |
5c55ff99 BS |
6602 | #endif |
6603 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) | |
6604 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) | |
6605 | ||
6606 | #undef GEN_ST | |
6607 | #undef GEN_STU | |
6608 | #undef GEN_STUX | |
cd6e9320 | 6609 | #undef GEN_STX_E |
5c55ff99 BS |
6610 | #undef GEN_STS |
6611 | #define GEN_ST(name, stop, opc, type) \ | |
6612 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), | |
6613 | #define GEN_STU(name, stop, opc, type) \ | |
6614 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), | |
6615 | #define GEN_STUX(name, stop, opc2, opc3, type) \ | |
6616 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), | |
b7815375 | 6617 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
cd6e9320 | 6618 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
5c55ff99 BS |
6619 | #define GEN_STS(name, stop, op, type) \ |
6620 | GEN_ST(name, stop, op | 0x20, type) \ | |
6621 | GEN_STU(name, stop, op | 0x21, type) \ | |
6622 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ | |
6623 | GEN_STX(name, stop, 0x17, op | 0x00, type) | |
6624 | ||
6625 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) | |
6626 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) | |
6627 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) | |
6628 | #if defined(TARGET_PPC64) | |
2468f23d ND |
6629 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) |
6630 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) | |
804108aa | 6631 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) |
2468f23d | 6632 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
b7815375 BH |
6633 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
6634 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) | |
6635 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) | |
5c55ff99 BS |
6636 | #endif |
6637 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) | |
6638 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) | |
6639 | ||
5c55ff99 BS |
6640 | #undef GEN_CRLOGIC |
6641 | #define GEN_CRLOGIC(name, tcg_op, opc) \ | |
6642 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) | |
6643 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), | |
6644 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), | |
6645 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), | |
6646 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), | |
6647 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), | |
6648 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), | |
6649 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), | |
6650 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), | |
6651 | ||
6652 | #undef GEN_MAC_HANDLER | |
6653 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ | |
6654 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) | |
6655 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), | |
6656 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), | |
6657 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), | |
6658 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), | |
6659 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), | |
6660 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), | |
6661 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), | |
6662 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), | |
6663 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), | |
6664 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), | |
6665 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), | |
6666 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), | |
6667 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), | |
6668 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), | |
6669 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), | |
6670 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), | |
6671 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), | |
6672 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), | |
6673 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), | |
6674 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), | |
6675 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), | |
6676 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), | |
6677 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), | |
6678 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), | |
6679 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), | |
6680 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), | |
6681 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), | |
6682 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), | |
6683 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), | |
6684 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), | |
6685 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), | |
6686 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), | |
6687 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), | |
6688 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), | |
6689 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), | |
6690 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), | |
6691 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), | |
6692 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), | |
6693 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), | |
6694 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), | |
6695 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), | |
6696 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), | |
6697 | ||
0ff93d11 TM |
6698 | GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \ |
6699 | PPC_NONE, PPC2_TM), | |
56a84615 TM |
6700 | GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \ |
6701 | PPC_NONE, PPC2_TM), | |
6702 | GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \ | |
6703 | PPC_NONE, PPC2_TM), | |
6704 | GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \ | |
6705 | PPC_NONE, PPC2_TM), | |
6706 | GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \ | |
6707 | PPC_NONE, PPC2_TM), | |
6708 | GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \ | |
6709 | PPC_NONE, PPC2_TM), | |
6710 | GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \ | |
6711 | PPC_NONE, PPC2_TM), | |
6712 | GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \ | |
6713 | PPC_NONE, PPC2_TM), | |
aeedd582 TM |
6714 | GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \ |
6715 | PPC_NONE, PPC2_TM), | |
f83c2378 TM |
6716 | GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \ |
6717 | PPC_NONE, PPC2_TM), | |
6718 | GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \ | |
6719 | PPC_NONE, PPC2_TM), | |
15848410 BH |
6720 | |
6721 | #include "translate/fp-ops.inc.c" | |
6722 | ||
6723 | #include "translate/vmx-ops.inc.c" | |
6724 | ||
6725 | #include "translate/vsx-ops.inc.c" | |
6726 | ||
6727 | #include "translate/dfp-ops.inc.c" | |
6728 | ||
6729 | #include "translate/spe-ops.inc.c" | |
5c55ff99 BS |
6730 | }; |
6731 | ||
0411a972 | 6732 | #include "helper_regs.h" |
a1389542 | 6733 | #include "translate_init.c" |
79aceca5 | 6734 | |
9a64fbe4 | 6735 | /*****************************************************************************/ |
3fc6c082 | 6736 | /* Misc PowerPC helpers */ |
878096ee AF |
6737 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, |
6738 | int flags) | |
79aceca5 | 6739 | { |
3fc6c082 FB |
6740 | #define RGPL 4 |
6741 | #define RFPL 4 | |
3fc6c082 | 6742 | |
878096ee AF |
6743 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
6744 | CPUPPCState *env = &cpu->env; | |
79aceca5 FB |
6745 | int i; |
6746 | ||
90e189ec | 6747 | cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
21e5d28a TG |
6748 | TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", |
6749 | env->nip, env->lr, env->ctr, cpu_read_xer(env), | |
6750 | cs->cpu_index); | |
90e189ec | 6751 | cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
9fb04491 BH |
6752 | TARGET_FMT_lx " iidx %d didx %d\n", |
6753 | env->msr, env->spr[SPR_HID0], | |
6754 | env->hflags, env->immu_idx, env->dmmu_idx); | |
d9bce9d9 | 6755 | #if !defined(NO_TIMER_DUMP) |
9a78eead | 6756 | cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
76a66253 | 6757 | #if !defined(CONFIG_USER_ONLY) |
9a78eead | 6758 | " DECR %08" PRIu32 |
76a66253 JM |
6759 | #endif |
6760 | "\n", | |
077fc206 | 6761 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
76a66253 JM |
6762 | #if !defined(CONFIG_USER_ONLY) |
6763 | , cpu_ppc_load_decr(env) | |
6764 | #endif | |
6765 | ); | |
077fc206 | 6766 | #endif |
76a66253 | 6767 | for (i = 0; i < 32; i++) { |
3fc6c082 FB |
6768 | if ((i & (RGPL - 1)) == 0) |
6769 | cpu_fprintf(f, "GPR%02d", i); | |
b11ebf64 | 6770 | cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
3fc6c082 | 6771 | if ((i & (RGPL - 1)) == (RGPL - 1)) |
7fe48483 | 6772 | cpu_fprintf(f, "\n"); |
76a66253 | 6773 | } |
3fc6c082 | 6774 | cpu_fprintf(f, "CR "); |
76a66253 | 6775 | for (i = 0; i < 8; i++) |
7fe48483 FB |
6776 | cpu_fprintf(f, "%01x", env->crf[i]); |
6777 | cpu_fprintf(f, " ["); | |
76a66253 JM |
6778 | for (i = 0; i < 8; i++) { |
6779 | char a = '-'; | |
6780 | if (env->crf[i] & 0x08) | |
6781 | a = 'L'; | |
6782 | else if (env->crf[i] & 0x04) | |
6783 | a = 'G'; | |
6784 | else if (env->crf[i] & 0x02) | |
6785 | a = 'E'; | |
7fe48483 | 6786 | cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); |
76a66253 | 6787 | } |
90e189ec BS |
6788 | cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", |
6789 | env->reserve_addr); | |
3fc6c082 FB |
6790 | for (i = 0; i < 32; i++) { |
6791 | if ((i & (RFPL - 1)) == 0) | |
6792 | cpu_fprintf(f, "FPR%02d", i); | |
26a76461 | 6793 | cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); |
3fc6c082 | 6794 | if ((i & (RFPL - 1)) == (RFPL - 1)) |
7fe48483 | 6795 | cpu_fprintf(f, "\n"); |
79aceca5 | 6796 | } |
30304420 | 6797 | cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); |
f2e63a42 | 6798 | #if !defined(CONFIG_USER_ONLY) |
90dc8812 SW |
6799 | cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
6800 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", | |
6801 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], | |
6802 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); | |
6803 | ||
6804 | cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx | |
6805 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", | |
6806 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], | |
6807 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); | |
6808 | ||
6809 | cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx | |
6810 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", | |
6811 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], | |
6812 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); | |
6813 | ||
f2b70fde BH |
6814 | #if defined(TARGET_PPC64) |
6815 | if (env->excp_model == POWERPC_EXCP_POWER7 || | |
6816 | env->excp_model == POWERPC_EXCP_POWER8) { | |
6817 | cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", | |
6818 | env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); | |
6819 | } | |
6820 | #endif | |
90dc8812 SW |
6821 | if (env->excp_model == POWERPC_EXCP_BOOKE) { |
6822 | cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx | |
6823 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", | |
6824 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], | |
6825 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); | |
6826 | ||
6827 | cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx | |
6828 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", | |
6829 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], | |
6830 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); | |
6831 | ||
6832 | cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx | |
6833 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", | |
6834 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], | |
6835 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); | |
6836 | ||
6837 | cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx | |
6838 | " EPR " TARGET_FMT_lx "\n", | |
6839 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], | |
6840 | env->spr[SPR_BOOKE_EPR]); | |
6841 | ||
6842 | /* FSL-specific */ | |
6843 | cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx | |
6844 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", | |
6845 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], | |
6846 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); | |
6847 | ||
6848 | /* | |
6849 | * IVORs are left out as they are large and do not change often -- | |
6850 | * they can be read with "p $ivor0", "p $ivor1", etc. | |
6851 | */ | |
6852 | } | |
6853 | ||
697ab892 DG |
6854 | #if defined(TARGET_PPC64) |
6855 | if (env->flags & POWERPC_FLAG_CFAR) { | |
6856 | cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); | |
6857 | } | |
6858 | #endif | |
6859 | ||
90dc8812 SW |
6860 | switch (env->mmu_model) { |
6861 | case POWERPC_MMU_32B: | |
6862 | case POWERPC_MMU_601: | |
6863 | case POWERPC_MMU_SOFT_6xx: | |
6864 | case POWERPC_MMU_SOFT_74xx: | |
6865 | #if defined(TARGET_PPC64) | |
90dc8812 | 6866 | case POWERPC_MMU_64B: |
aa4bb587 | 6867 | case POWERPC_MMU_2_03: |
ca480de6 | 6868 | case POWERPC_MMU_2_06: |
808bc3b0 | 6869 | case POWERPC_MMU_2_06a: |
aa4bb587 | 6870 | case POWERPC_MMU_2_07: |
808bc3b0 | 6871 | case POWERPC_MMU_2_07a: |
90dc8812 | 6872 | #endif |
ca480de6 AB |
6873 | cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx |
6874 | " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1], | |
6875 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); | |
90dc8812 | 6876 | break; |
01662f3e | 6877 | case POWERPC_MMU_BOOKE206: |
90dc8812 SW |
6878 | cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
6879 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", | |
6880 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], | |
6881 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); | |
6882 | ||
6883 | cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx | |
6884 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", | |
6885 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], | |
6886 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); | |
6887 | ||
6888 | cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx | |
6889 | " TLB1CFG " TARGET_FMT_lx "\n", | |
6890 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], | |
6891 | env->spr[SPR_BOOKE_TLB1CFG]); | |
6892 | break; | |
6893 | default: | |
6894 | break; | |
6895 | } | |
f2e63a42 | 6896 | #endif |
79aceca5 | 6897 | |
3fc6c082 FB |
6898 | #undef RGPL |
6899 | #undef RFPL | |
79aceca5 FB |
6900 | } |
6901 | ||
878096ee AF |
6902 | void ppc_cpu_dump_statistics(CPUState *cs, FILE*f, |
6903 | fprintf_function cpu_fprintf, int flags) | |
76a66253 JM |
6904 | { |
6905 | #if defined(DO_PPC_STATISTICS) | |
878096ee | 6906 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
c227f099 | 6907 | opc_handler_t **t1, **t2, **t3, *handler; |
76a66253 JM |
6908 | int op1, op2, op3; |
6909 | ||
878096ee | 6910 | t1 = cpu->env.opcodes; |
76a66253 JM |
6911 | for (op1 = 0; op1 < 64; op1++) { |
6912 | handler = t1[op1]; | |
6913 | if (is_indirect_opcode(handler)) { | |
6914 | t2 = ind_table(handler); | |
6915 | for (op2 = 0; op2 < 32; op2++) { | |
6916 | handler = t2[op2]; | |
6917 | if (is_indirect_opcode(handler)) { | |
6918 | t3 = ind_table(handler); | |
6919 | for (op3 = 0; op3 < 32; op3++) { | |
6920 | handler = t3[op3]; | |
6921 | if (handler->count == 0) | |
6922 | continue; | |
6923 | cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 6924 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
6925 | op1, op2, op3, op1, (op3 << 5) | op2, |
6926 | handler->oname, | |
6927 | handler->count, handler->count); | |
6928 | } | |
6929 | } else { | |
6930 | if (handler->count == 0) | |
6931 | continue; | |
6932 | cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: " | |
0bfcd599 | 6933 | "%016" PRIx64 " %" PRId64 "\n", |
76a66253 JM |
6934 | op1, op2, op1, op2, handler->oname, |
6935 | handler->count, handler->count); | |
6936 | } | |
6937 | } | |
6938 | } else { | |
6939 | if (handler->count == 0) | |
6940 | continue; | |
0bfcd599 BS |
6941 | cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64 |
6942 | " %" PRId64 "\n", | |
76a66253 JM |
6943 | op1, op1, handler->oname, |
6944 | handler->count, handler->count); | |
6945 | } | |
6946 | } | |
6947 | #endif | |
6948 | } | |
6949 | ||
9a64fbe4 | 6950 | /*****************************************************************************/ |
4e5e1215 | 6951 | void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb) |
79aceca5 | 6952 | { |
4e5e1215 | 6953 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
ed2803da | 6954 | CPUState *cs = CPU(cpu); |
9fddaa0c | 6955 | DisasContext ctx, *ctxp = &ctx; |
c227f099 | 6956 | opc_handler_t **table, *handler; |
0fa85d43 | 6957 | target_ulong pc_start; |
2e70f6ef PB |
6958 | int num_insns; |
6959 | int max_insns; | |
79aceca5 FB |
6960 | |
6961 | pc_start = tb->pc; | |
046d6672 | 6962 | ctx.nip = pc_start; |
79aceca5 | 6963 | ctx.tb = tb; |
e1833e1f | 6964 | ctx.exception = POWERPC_EXCP_NONE; |
3fc6c082 | 6965 | ctx.spr_cb = env->spr_cb; |
c47493f2 | 6966 | ctx.pr = msr_pr; |
9fb04491 | 6967 | ctx.mem_idx = env->dmmu_idx; |
b7815375 | 6968 | ctx.dr = msr_dr; |
932ccbdd BH |
6969 | #if !defined(CONFIG_USER_ONLY) |
6970 | ctx.hv = msr_hv || !env->has_hv_mode; | |
6971 | #endif | |
7d08d856 AJ |
6972 | ctx.insns_flags = env->insns_flags; |
6973 | ctx.insns_flags2 = env->insns_flags2; | |
76db3ba4 | 6974 | ctx.access_type = -1; |
5f2a6254 | 6975 | ctx.need_access_type = !(env->mmu_model & POWERPC_MMU_64B); |
5c3ae929 | 6976 | ctx.le_mode = !!(env->hflags & (1 << MSR_LE)); |
e22c357b | 6977 | ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE; |
d9bce9d9 | 6978 | #if defined(TARGET_PPC64) |
e42a61f1 | 6979 | ctx.sf_mode = msr_is_64bit(env, env->msr); |
697ab892 | 6980 | ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
9a64fbe4 | 6981 | #endif |
c5a8d8f3 BH |
6982 | if (env->mmu_model == POWERPC_MMU_32B || |
6983 | env->mmu_model == POWERPC_MMU_601 || | |
6984 | (env->mmu_model & POWERPC_MMU_64B)) | |
6985 | ctx.lazy_tlb_flush = true; | |
6986 | ||
5c3ae929 | 6987 | ctx.fpu_enabled = !!msr_fp; |
a9d9eb8f | 6988 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) |
5c3ae929 | 6989 | ctx.spe_enabled = !!msr_spe; |
d26bfc9a | 6990 | else |
5c3ae929 | 6991 | ctx.spe_enabled = false; |
a9d9eb8f | 6992 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) |
5c3ae929 | 6993 | ctx.altivec_enabled = !!msr_vr; |
a9d9eb8f | 6994 | else |
5c3ae929 | 6995 | ctx.altivec_enabled = false; |
1f29871c | 6996 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
5c3ae929 | 6997 | ctx.vsx_enabled = !!msr_vsx; |
1f29871c | 6998 | } else { |
5c3ae929 | 6999 | ctx.vsx_enabled = false; |
1f29871c | 7000 | } |
69d1a937 TM |
7001 | #if defined(TARGET_PPC64) |
7002 | if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { | |
5c3ae929 | 7003 | ctx.tm_enabled = !!msr_tm; |
69d1a937 | 7004 | } else { |
5c3ae929 | 7005 | ctx.tm_enabled = false; |
69d1a937 TM |
7006 | } |
7007 | #endif | |
d26bfc9a | 7008 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) |
8cbcb4fa | 7009 | ctx.singlestep_enabled = CPU_SINGLE_STEP; |
d26bfc9a | 7010 | else |
8cbcb4fa | 7011 | ctx.singlestep_enabled = 0; |
d26bfc9a | 7012 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) |
8cbcb4fa | 7013 | ctx.singlestep_enabled |= CPU_BRANCH_STEP; |
ed2803da | 7014 | if (unlikely(cs->singlestep_enabled)) { |
8cbcb4fa | 7015 | ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
ed2803da | 7016 | } |
3fc6c082 | 7017 | #if defined (DO_SINGLE_STEP) && 0 |
9a64fbe4 FB |
7018 | /* Single step trace mode */ |
7019 | msr_se = 1; | |
7020 | #endif | |
2e70f6ef PB |
7021 | num_insns = 0; |
7022 | max_insns = tb->cflags & CF_COUNT_MASK; | |
190ce7fb | 7023 | if (max_insns == 0) { |
2e70f6ef | 7024 | max_insns = CF_COUNT_MASK; |
190ce7fb RH |
7025 | } |
7026 | if (max_insns > TCG_MAX_INSNS) { | |
7027 | max_insns = TCG_MAX_INSNS; | |
7028 | } | |
2e70f6ef | 7029 | |
cd42d5b2 | 7030 | gen_tb_start(tb); |
3de31797 | 7031 | tcg_clear_temp_count(); |
9a64fbe4 | 7032 | /* Set env in case of segfault during code fetch */ |
fe700adb | 7033 | while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) { |
667b8e29 | 7034 | tcg_gen_insn_start(ctx.nip); |
959082fc | 7035 | num_insns++; |
667b8e29 | 7036 | |
b933066a RH |
7037 | if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) { |
7038 | gen_debug_exception(ctxp); | |
522a0d4e RH |
7039 | /* The address covered by the breakpoint must be included in |
7040 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
7041 | properly cleared -- thus we increment the PC here so that | |
7042 | the logic setting tb->size below does the right thing. */ | |
7043 | ctx.nip += 4; | |
b933066a RH |
7044 | break; |
7045 | } | |
7046 | ||
d12d51d5 | 7047 | LOG_DISAS("----------------\n"); |
90e189ec | 7048 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", |
d12d51d5 | 7049 | ctx.nip, ctx.mem_idx, (int)msr_ir); |
959082fc | 7050 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) |
2e70f6ef | 7051 | gen_io_start(); |
e22c357b | 7052 | if (unlikely(need_byteswap(&ctx))) { |
2f5a189c | 7053 | ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip)); |
056401ea | 7054 | } else { |
2f5a189c | 7055 | ctx.opcode = cpu_ldl_code(env, ctx.nip); |
111bfab3 | 7056 | } |
323ad19b ND |
7057 | LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n", |
7058 | ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), | |
7059 | opc3(ctx.opcode), opc4(ctx.opcode), | |
7060 | ctx.le_mode ? "little" : "big"); | |
046d6672 | 7061 | ctx.nip += 4; |
3fc6c082 | 7062 | table = env->opcodes; |
79aceca5 FB |
7063 | handler = table[opc1(ctx.opcode)]; |
7064 | if (is_indirect_opcode(handler)) { | |
7065 | table = ind_table(handler); | |
7066 | handler = table[opc2(ctx.opcode)]; | |
7067 | if (is_indirect_opcode(handler)) { | |
7068 | table = ind_table(handler); | |
7069 | handler = table[opc3(ctx.opcode)]; | |
323ad19b ND |
7070 | if (is_indirect_opcode(handler)) { |
7071 | table = ind_table(handler); | |
7072 | handler = table[opc4(ctx.opcode)]; | |
7073 | } | |
79aceca5 FB |
7074 | } |
7075 | } | |
7076 | /* Is opcode *REALLY* valid ? */ | |
76a66253 | 7077 | if (unlikely(handler->handler == &gen_invalid)) { |
48880da6 | 7078 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " |
323ad19b ND |
7079 | "%02x - %02x - %02x - %02x (%08x) " |
7080 | TARGET_FMT_lx " %d\n", | |
48880da6 | 7081 | opc1(ctx.opcode), opc2(ctx.opcode), |
323ad19b ND |
7082 | opc3(ctx.opcode), opc4(ctx.opcode), |
7083 | ctx.opcode, ctx.nip - 4, (int)msr_ir); | |
76a66253 | 7084 | } else { |
70560da7 FC |
7085 | uint32_t inval; |
7086 | ||
7087 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) { | |
7088 | inval = handler->inval2; | |
7089 | } else { | |
7090 | inval = handler->inval1; | |
7091 | } | |
7092 | ||
7093 | if (unlikely((ctx.opcode & inval) != 0)) { | |
48880da6 | 7094 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " |
323ad19b ND |
7095 | "%02x - %02x - %02x - %02x (%08x) " |
7096 | TARGET_FMT_lx "\n", ctx.opcode & inval, | |
7097 | opc1(ctx.opcode), opc2(ctx.opcode), | |
7098 | opc3(ctx.opcode), opc4(ctx.opcode), | |
48880da6 | 7099 | ctx.opcode, ctx.nip - 4); |
e06fcd75 | 7100 | gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL); |
4b3686fa | 7101 | break; |
79aceca5 | 7102 | } |
79aceca5 | 7103 | } |
4b3686fa | 7104 | (*(handler->handler))(&ctx); |
76a66253 JM |
7105 | #if defined(DO_PPC_STATISTICS) |
7106 | handler->count++; | |
7107 | #endif | |
9a64fbe4 | 7108 | /* Check trace mode exceptions */ |
8cbcb4fa AJ |
7109 | if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP && |
7110 | (ctx.nip <= 0x100 || ctx.nip > 0xF00) && | |
7111 | ctx.exception != POWERPC_SYSCALL && | |
7112 | ctx.exception != POWERPC_EXCP_TRAP && | |
7113 | ctx.exception != POWERPC_EXCP_BRANCH)) { | |
bd6fefe7 | 7114 | gen_exception_nip(ctxp, POWERPC_EXCP_TRACE, ctx.nip); |
d26bfc9a | 7115 | } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) || |
ed2803da | 7116 | (cs->singlestep_enabled) || |
1b530a6d | 7117 | singlestep || |
2e70f6ef | 7118 | num_insns >= max_insns)) { |
d26bfc9a JM |
7119 | /* if we reach a page boundary or are single stepping, stop |
7120 | * generation | |
7121 | */ | |
8dd4983c | 7122 | break; |
76a66253 | 7123 | } |
3de31797 | 7124 | if (tcg_check_temp_count()) { |
323ad19b ND |
7125 | fprintf(stderr, "Opcode %02x %02x %02x %02x (%08x) leaked " |
7126 | "temporaries\n", opc1(ctx.opcode), opc2(ctx.opcode), | |
7127 | opc3(ctx.opcode), opc4(ctx.opcode), ctx.opcode); | |
3de31797 AG |
7128 | exit(1); |
7129 | } | |
3fc6c082 | 7130 | } |
2e70f6ef PB |
7131 | if (tb->cflags & CF_LAST_IO) |
7132 | gen_io_end(); | |
e1833e1f | 7133 | if (ctx.exception == POWERPC_EXCP_NONE) { |
c1942362 | 7134 | gen_goto_tb(&ctx, 0, ctx.nip); |
e1833e1f | 7135 | } else if (ctx.exception != POWERPC_EXCP_BRANCH) { |
ed2803da | 7136 | if (unlikely(cs->singlestep_enabled)) { |
e06fcd75 | 7137 | gen_debug_exception(ctxp); |
8cbcb4fa | 7138 | } |
76a66253 | 7139 | /* Generate the return instruction */ |
57fec1fe | 7140 | tcg_gen_exit_tb(0); |
9a64fbe4 | 7141 | } |
806f352d | 7142 | gen_tb_end(tb, num_insns); |
0a7df5da | 7143 | |
4e5e1215 RH |
7144 | tb->size = ctx.nip - pc_start; |
7145 | tb->icount = num_insns; | |
7146 | ||
d9bce9d9 | 7147 | #if defined(DEBUG_DISAS) |
4910e6e4 RH |
7148 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
7149 | && qemu_log_in_addr_range(pc_start)) { | |
76a66253 | 7150 | int flags; |
237c0af0 | 7151 | flags = env->bfd_mach; |
76db3ba4 | 7152 | flags |= ctx.le_mode << 16; |
93fcfe39 | 7153 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
d49190c4 | 7154 | log_target_disas(cs, pc_start, ctx.nip - pc_start, flags); |
93fcfe39 | 7155 | qemu_log("\n"); |
9fddaa0c | 7156 | } |
79aceca5 | 7157 | #endif |
79aceca5 FB |
7158 | } |
7159 | ||
bad729e2 RH |
7160 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, |
7161 | target_ulong *data) | |
d2856f1a | 7162 | { |
bad729e2 | 7163 | env->nip = data[0]; |
d2856f1a | 7164 | } |