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target-ppc: convert crf related instructions to TCG
[mirror_qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
f10dc08e 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
79aceca5 32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
79aceca5 38//#define DO_SINGLE_STEP
9fddaa0c 39//#define PPC_DEBUG_DISAS
76a66253 40//#define DO_PPC_STATISTICS
7c58044c 41//#define OPTIMIZE_FPRF_UPDATE
79aceca5 42
a750fc0b
JM		 43/*****************************************************************************/
44/* Code translation helpers */
c53be334 45
f78fb44e
AJ		 46/* global register indexes */
47static TCGv cpu_env;
1d542695 48static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 49#if !defined(TARGET_PPC64)
1d542695 50 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 51#endif
a5e26afa 52 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
f78fb44e
AJ		 55static TCGv cpu_gpr[32];
56#if !defined(TARGET_PPC64)
57static TCGv cpu_gprh[32];
58#endif
a5e26afa 59static TCGv cpu_fpr[32];
1d542695 60static TCGv cpu_avrh[32], cpu_avrl[32];
47e4661c 61static TCGv cpu_crf[8];
bd568f18 62static TCGv cpu_nip;
cfdcd37a
AJ		 63static TCGv cpu_ctr;
64static TCGv cpu_lr;
3d7b417e 65static TCGv cpu_xer;
e1571908 66static TCGv cpu_fpscr;
f78fb44e
AJ		 67
68/* dyngen register indexes */
69static TCGv cpu_T[3];
70#if defined(TARGET_PPC64)
71#define cpu_T64 cpu_T
72#else
73static TCGv cpu_T64[3];
74#endif
a5e26afa 75static TCGv cpu_FT[3];
1d542695 76static TCGv cpu_AVRh[3], cpu_AVRl[3];
2e70f6ef
PB		 77
78#include "gen-icount.h"
79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
b2437bf2 84 static int done_init = 0;
f78fb44e 85
2e70f6ef
PB		 86 if (done_init)
87 return;
f78fb44e 88
2e70f6ef 89 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
1c73fe5b
AJ		 90#if TARGET_LONG_BITS > HOST_LONG_BITS
91 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
92 TCG_AREG0, offsetof(CPUState, t0), "T0");
93 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
94 TCG_AREG0, offsetof(CPUState, t1), "T1");
95 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
96 TCG_AREG0, offsetof(CPUState, t2), "T2");
97#else
98 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
99 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
100 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
101#endif
f78fb44e
AJ		 102#if !defined(TARGET_PPC64)
103 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 104 TCG_AREG0, offsetof(CPUState, t0_64),
f78fb44e
AJ		 105 "T0_64");
106 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 107 TCG_AREG0, offsetof(CPUState, t1_64),
f78fb44e
AJ		 108 "T1_64");
109 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 110 TCG_AREG0, offsetof(CPUState, t2_64),
f78fb44e
AJ		 111 "T2_64");
112#endif
a5e26afa
AJ		 113
114 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
115 offsetof(CPUState, ft0), "FT0");
116 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
117 offsetof(CPUState, ft1), "FT1");
118 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
119 offsetof(CPUState, ft2), "FT2");
120
1d542695
AJ		 121 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
122 offsetof(CPUState, avr0.u64[0]), "AVR0H");
123 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124 offsetof(CPUState, avr0.u64[1]), "AVR0L");
125 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126 offsetof(CPUState, avr1.u64[0]), "AVR1H");
127 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128 offsetof(CPUState, avr1.u64[1]), "AVR1L");
129 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
130 offsetof(CPUState, avr2.u64[0]), "AVR2H");
131 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
132 offsetof(CPUState, avr2.u64[1]), "AVR2L");
133
f78fb44e 134 p = cpu_reg_names;
47e4661c
AJ		 135
136 for (i = 0; i < 8; i++) {
137 sprintf(p, "crf%d", i);
138 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
139 offsetof(CPUState, crf[i]), p);
140 p += 5;
141 }
142
f78fb44e
AJ		 143 for (i = 0; i < 32; i++) {
144 sprintf(p, "r%d", i);
145 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
146 offsetof(CPUState, gpr[i]), p);
147 p += (i < 10) ? 3 : 4;
148#if !defined(TARGET_PPC64)
149 sprintf(p, "r%dH", i);
150 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
151 offsetof(CPUState, gprh[i]), p);
152 p += (i < 10) ? 4 : 5;
153#endif
1d542695 154
a5e26afa
AJ		 155 sprintf(p, "fp%d", i);
156 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
157 offsetof(CPUState, fpr[i]), p);
ec1ac72d 158 p += (i < 10) ? 4 : 5;
a5e26afa 159
1d542695
AJ		 160 sprintf(p, "avr%dH", i);
161 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
162 offsetof(CPUState, avr[i].u64[0]), p);
163 p += (i < 10) ? 6 : 7;
ec1ac72d 164
1d542695
AJ		 165 sprintf(p, "avr%dL", i);
166 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
167 offsetof(CPUState, avr[i].u64[1]), p);
168 p += (i < 10) ? 6 : 7;
f78fb44e 169 }
f10dc08e 170
bd568f18
AJ		 171 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
172 offsetof(CPUState, nip), "nip");
173
cfdcd37a
AJ		 174 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
175 offsetof(CPUState, ctr), "ctr");
176
177 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
178 offsetof(CPUState, lr), "lr");
179
3d7b417e
AJ		 180 cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
181 offsetof(CPUState, xer), "xer");
182
e1571908
AJ		 183 cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
184 offsetof(CPUState, fpscr), "fpscr");
185
f10dc08e
AJ		 186 /* register helpers */
187#undef DEF_HELPER
188#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
189#include "helper.h"
190
2e70f6ef
PB		 191 done_init = 1;
192}
193
7c58044c
JM		 194#if defined(OPTIMIZE_FPRF_UPDATE)
195static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
196static uint16_t **gen_fprf_ptr;
197#endif
79aceca5 198
79aceca5
FB		 199/* internal defines */
200typedef struct DisasContext {
201 struct TranslationBlock *tb;
0fa85d43 202 target_ulong nip;
79aceca5 203 uint32_t opcode;
9a64fbe4 204 uint32_t exception;
3cc62370
FB		 205 /* Routine used to access memory */
206 int mem_idx;
207 /* Translation flags */
9a64fbe4 208#if !defined(CONFIG_USER_ONLY)
79aceca5 209 int supervisor;
d9bce9d9
JM		 210#endif
211#if defined(TARGET_PPC64)
212 int sf_mode;
9a64fbe4 213#endif
3cc62370 214 int fpu_enabled;
a9d9eb8f 215 int altivec_enabled;
0487d6a8 216 int spe_enabled;
3fc6c082 217 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 218 int singlestep_enabled;
d63001d1 219 int dcache_line_size;
79aceca5
FB		 220} DisasContext;
221
3fc6c082 222struct opc_handler_t {
79aceca5
FB		 223 /* invalid bits */
224 uint32_t inval;
9a64fbe4 225 /* instruction type */
0487d6a8 226 uint64_t type;
79aceca5
FB		 227 /* handler */
228 void (*handler)(DisasContext *ctx);
a750fc0b 229#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 230 const char *oname;
a750fc0b
JM		 231#endif
232#if defined(DO_PPC_STATISTICS)
76a66253
JM		 233 uint64_t count;
234#endif
3fc6c082 235};
79aceca5 236
7c58044c
JM		 237static always_inline void gen_reset_fpstatus (void)
238{
239#ifdef CONFIG_SOFTFLOAT
240 gen_op_reset_fpstatus();
241#endif
242}
243
244static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
245{
246 if (set_fprf != 0) {
247 /* This case might be optimized later */
248#if defined(OPTIMIZE_FPRF_UPDATE)
249 *gen_fprf_ptr++ = gen_opc_ptr;
250#endif
251 gen_op_compute_fprf(1);
252 if (unlikely(set_rc))
47e4661c 253 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 254 gen_op_float_check_status();
255 } else if (unlikely(set_rc)) {
256 /* We always need to compute fpcc */
257 gen_op_compute_fprf(0);
47e4661c 258 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 259 if (set_fprf)
260 gen_op_float_check_status();
261 }
262}
263
264static always_inline void gen_optimize_fprf (void)
265{
266#if defined(OPTIMIZE_FPRF_UPDATE)
267 uint16_t **ptr;
268
269 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
270 *ptr = INDEX_op_nop1;
271 gen_fprf_ptr = gen_fprf_buf;
272#endif
273}
274
b068d6a7 275static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 276{
277#if defined(TARGET_PPC64)
278 if (ctx->sf_mode)
bd568f18 279 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 280 else
281#endif
bd568f18 282 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 283}
284
e1833e1f 285#define GEN_EXCP(ctx, excp, error) \
79aceca5 286do { \
e1833e1f 287 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 288 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 289 } \
290 gen_op_raise_exception_err((excp), (error)); \
291 ctx->exception = (excp); \
79aceca5
FB		 292} while (0)
293
e1833e1f
JM		 294#define GEN_EXCP_INVAL(ctx) \
295GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
296 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 297
e1833e1f
JM		 298#define GEN_EXCP_PRIVOPC(ctx) \
299GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
300 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 301
e1833e1f
JM		 302#define GEN_EXCP_PRIVREG(ctx) \
303GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
304 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
305
306#define GEN_EXCP_NO_FP(ctx) \
307GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
308
309#define GEN_EXCP_NO_AP(ctx) \
310GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 311
a9d9eb8f
JM		 312#define GEN_EXCP_NO_VR(ctx) \
313GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
314
f24e5695 315/* Stop translation */
b068d6a7 316static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 317{
d9bce9d9 318 gen_update_nip(ctx, ctx->nip);
e1833e1f 319 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 320}
321
f24e5695 322/* No need to update nip here, as execution flow will change */
b068d6a7 323static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 324{
e1833e1f 325 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 326}
327
79aceca5
FB		 328#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329static void gen_##name (DisasContext *ctx); \
330GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
331static void gen_##name (DisasContext *ctx)
332
c7697e1f
JM		 333#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
334static void gen_##name (DisasContext *ctx); \
335GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
336static void gen_##name (DisasContext *ctx)
337
79aceca5
FB		 338typedef struct opcode_t {
339 unsigned char opc1, opc2, opc3;
1235fc06 340#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 341 unsigned char pad[5];
342#else
343 unsigned char pad[1];
344#endif
79aceca5 345 opc_handler_t handler;
b55266b5 346 const char *oname;
79aceca5
FB		 347} opcode_t;
348
a750fc0b 349/*****************************************************************************/
79aceca5
FB		 350/*** Instruction decoding ***/
351#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 352static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 353{ \
354 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
355}
356
357#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 358static always_inline int32_t name (uint32_t opcode) \
79aceca5 359{ \
18fba28c 360 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 361}
362
363/* Opcode part 1 */
364EXTRACT_HELPER(opc1, 26, 6);
365/* Opcode part 2 */
366EXTRACT_HELPER(opc2, 1, 5);
367/* Opcode part 3 */
368EXTRACT_HELPER(opc3, 6, 5);
369/* Update Cr0 flags */
370EXTRACT_HELPER(Rc, 0, 1);
371/* Destination */
372EXTRACT_HELPER(rD, 21, 5);
373/* Source */
374EXTRACT_HELPER(rS, 21, 5);
375/* First operand */
376EXTRACT_HELPER(rA, 16, 5);
377/* Second operand */
378EXTRACT_HELPER(rB, 11, 5);
379/* Third operand */
380EXTRACT_HELPER(rC, 6, 5);
381/*** Get CRn ***/
382EXTRACT_HELPER(crfD, 23, 3);
383EXTRACT_HELPER(crfS, 18, 3);
384EXTRACT_HELPER(crbD, 21, 5);
385EXTRACT_HELPER(crbA, 16, 5);
386EXTRACT_HELPER(crbB, 11, 5);
387/* SPR / TBL */
3fc6c082 388EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 389static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 390{
391 uint32_t sprn = _SPR(opcode);
392
393 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
394}
79aceca5
FB		 395/*** Get constants ***/
396EXTRACT_HELPER(IMM, 12, 8);
397/* 16 bits signed immediate value */
398EXTRACT_SHELPER(SIMM, 0, 16);
399/* 16 bits unsigned immediate value */
400EXTRACT_HELPER(UIMM, 0, 16);
401/* Bit count */
402EXTRACT_HELPER(NB, 11, 5);
403/* Shift count */
404EXTRACT_HELPER(SH, 11, 5);
405/* Mask start */
406EXTRACT_HELPER(MB, 6, 5);
407/* Mask end */
408EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 409/* Trap operand */
410EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 411
412EXTRACT_HELPER(CRM, 12, 8);
413EXTRACT_HELPER(FM, 17, 8);
414EXTRACT_HELPER(SR, 16, 4);
e4bb997e 415EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 416
79aceca5
FB		 417/*** Jump target decoding ***/
418/* Displacement */
419EXTRACT_SHELPER(d, 0, 16);
420/* Immediate address */
b068d6a7 421static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 422{
423 return (opcode >> 0) & 0x03FFFFFC;
424}
425
b068d6a7 426static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 427{
428 return (opcode >> 0) & 0xFFFC;
429}
430
431EXTRACT_HELPER(BO, 21, 5);
432EXTRACT_HELPER(BI, 16, 5);
433/* Absolute/relative address */
434EXTRACT_HELPER(AA, 1, 1);
435/* Link */
436EXTRACT_HELPER(LK, 0, 1);
437
438/* Create a mask between <start> and <end> bits */
b068d6a7 439static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 440{
76a66253 441 target_ulong ret;
79aceca5 442
76a66253
JM		 443#if defined(TARGET_PPC64)
444 if (likely(start == 0)) {
6f2d8978 445 ret = UINT64_MAX << (63 - end);
76a66253 446 } else if (likely(end == 63)) {
6f2d8978 447 ret = UINT64_MAX >> start;
76a66253
JM		 448 }
449#else
450 if (likely(start == 0)) {
6f2d8978 451 ret = UINT32_MAX << (31 - end);
76a66253 452 } else if (likely(end == 31)) {
6f2d8978 453 ret = UINT32_MAX >> start;
76a66253
JM		 454 }
455#endif
456 else {
457 ret = (((target_ulong)(-1ULL)) >> (start)) ^
458 (((target_ulong)(-1ULL) >> (end)) >> 1);
459 if (unlikely(start > end))
460 return ~ret;
461 }
79aceca5
FB		 462
463 return ret;
464}
465
a750fc0b
JM		 466/*****************************************************************************/
467/* PowerPC Instructions types definitions */
468enum {
1b413d55 469 PPC_NONE = 0x0000000000000000ULL,
12de9a39 470 /* PowerPC base instructions set */
1b413d55
JM		 471 PPC_INSNS_BASE = 0x0000000000000001ULL,
472 /* integer operations instructions */
a750fc0b 473#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 474 /* flow control instructions */
a750fc0b 475#define PPC_FLOW PPC_INSNS_BASE
1b413d55 476 /* virtual memory instructions */
a750fc0b 477#define PPC_MEM PPC_INSNS_BASE
1b413d55 478 /* ld/st with reservation instructions */
a750fc0b 479#define PPC_RES PPC_INSNS_BASE
1b413d55 480 /* spr/msr access instructions */
a750fc0b 481#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 482 /* Deprecated instruction sets */
483 /* Original POWER instruction set */
f610349f 484 PPC_POWER = 0x0000000000000002ULL,
1b413d55 485 /* POWER2 instruction set extension */
f610349f 486 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 487 /* Power RTC support */
f610349f 488 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 489 /* Power-to-PowerPC bridge (601) */
f610349f 490 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 491 /* 64 bits PowerPC instruction set */
f610349f 492 PPC_64B = 0x0000000000000020ULL,
1b413d55 493 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 494 PPC_64BX = 0x0000000000000040ULL,
1b413d55 495 /* 64 bits hypervisor extensions */
f610349f 496 PPC_64H = 0x0000000000000080ULL,
1b413d55 497 /* New wait instruction (PowerPC 2.0x) */
f610349f 498 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 499 /* Time base mftb instruction */
f610349f 500 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 501
502 /* Fixed-point unit extensions */
503 /* PowerPC 602 specific */
f610349f 504 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 505 /* isel instruction */
506 PPC_ISEL = 0x0000000000000800ULL,
507 /* popcntb instruction */
508 PPC_POPCNTB = 0x0000000000001000ULL,
509 /* string load / store */
510 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 511
512 /* Floating-point unit extensions */
513 /* Optional floating point instructions */
514 PPC_FLOAT = 0x0000000000010000ULL,
515 /* New floating-point extensions (PowerPC 2.0x) */
516 PPC_FLOAT_EXT = 0x0000000000020000ULL,
517 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
518 PPC_FLOAT_FRES = 0x0000000000080000ULL,
519 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
520 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
521 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
522 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
523
524 /* Vector/SIMD extensions */
525 /* Altivec support */
526 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 527 /* PowerPC 2.03 SPE extension */
05332d70 528 PPC_SPE = 0x0000000002000000ULL,
1b413d55 529 /* PowerPC 2.03 SPE floating-point extension */
05332d70 530 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 531
12de9a39 532 /* Optional memory control instructions */
1b413d55
JM		 533 PPC_MEM_TLBIA = 0x0000000010000000ULL,
534 PPC_MEM_TLBIE = 0x0000000020000000ULL,
535 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
536 /* sync instruction */
537 PPC_MEM_SYNC = 0x0000000080000000ULL,
538 /* eieio instruction */
539 PPC_MEM_EIEIO = 0x0000000100000000ULL,
540
541 /* Cache control instructions */
c8623f2e 542 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 543 /* icbi instruction */
05332d70 544 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 545 /* dcbz instruction with fixed cache line size */
05332d70 546 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 547 /* dcbz instruction with tunable cache line size */
05332d70 548 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 549 /* dcba instruction */
05332d70
JM		 550 PPC_CACHE_DCBA = 0x0000002000000000ULL,
551 /* Freescale cache locking instructions */
552 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 553
554 /* MMU related extensions */
555 /* external control instructions */
05332d70 556 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 557 /* segment register access instructions */
05332d70 558 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 559 /* PowerPC 6xx TLB management instructions */
05332d70 560 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 561 /* PowerPC 74xx TLB management instructions */
05332d70 562 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 563 /* PowerPC 40x TLB management instructions */
05332d70 564 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 565 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 566 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 567 /* SLB management */
05332d70 568 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 569
12de9a39 570 /* Embedded PowerPC dedicated instructions */
05332d70 571 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 572 /* PowerPC 40x exception model */
05332d70 573 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 574 /* PowerPC 405 Mac instructions */
05332d70 575 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 576 /* PowerPC 440 specific instructions */
05332d70 577 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 578 /* BookE (embedded) PowerPC specification */
05332d70
JM		 579 PPC_BOOKE = 0x0010000000000000ULL,
580 /* mfapidi instruction */
581 PPC_MFAPIDI = 0x0020000000000000ULL,
582 /* tlbiva instruction */
583 PPC_TLBIVA = 0x0040000000000000ULL,
584 /* tlbivax instruction */
585 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 586 /* PowerPC 4xx dedicated instructions */
05332d70 587 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 588 /* PowerPC 40x ibct instructions */
05332d70 589 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 590 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 591 PPC_RFMCI = 0x0400000000000000ULL,
592 /* rfdi instruction */
593 PPC_RFDI = 0x0800000000000000ULL,
594 /* DCR accesses */
595 PPC_DCR = 0x1000000000000000ULL,
596 /* DCR extended accesse */
597 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 598 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 599 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 600};
601
602/*****************************************************************************/
603/* PowerPC instructions table */
3fc6c082
FB		 604#if HOST_LONG_BITS == 64
605#define OPC_ALIGN 8
606#else
607#define OPC_ALIGN 4
608#endif
1b039c09 609#if defined(__APPLE__)
d9bce9d9 610#define OPCODES_SECTION \
3fc6c082 611 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 612#else
d9bce9d9 613#define OPCODES_SECTION \
3fc6c082 614 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 615#endif
616
76a66253 617#if defined(DO_PPC_STATISTICS)
79aceca5 618#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 619OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
18fba28c 623 .pad = { 0, }, \
79aceca5
FB		 624 .handler = { \
625 .inval = invl, \
9a64fbe4 626 .type = _typ, \
79aceca5 627 .handler = &gen_##name, \
76a66253 628 .oname = stringify(name), \
79aceca5 629 }, \
3fc6c082 630 .oname = stringify(name), \
79aceca5 631}
c7697e1f
JM		 632#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
633OPCODES_SECTION opcode_t opc_##name = { \
634 .opc1 = op1, \
635 .opc2 = op2, \
636 .opc3 = op3, \
637 .pad = { 0, }, \
638 .handler = { \
639 .inval = invl, \
640 .type = _typ, \
641 .handler = &gen_##name, \
642 .oname = onam, \
643 }, \
644 .oname = onam, \
645}
76a66253
JM		 646#else
647#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
648OPCODES_SECTION opcode_t opc_##name = { \
649 .opc1 = op1, \
650 .opc2 = op2, \
651 .opc3 = op3, \
652 .pad = { 0, }, \
653 .handler = { \
654 .inval = invl, \
655 .type = _typ, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = stringify(name), \
659}
c7697e1f
JM		 660#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
661OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = op1, \
663 .opc2 = op2, \
664 .opc3 = op3, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = invl, \
668 .type = _typ, \
669 .handler = &gen_##name, \
670 }, \
671 .oname = onam, \
672}
76a66253 673#endif
79aceca5
FB		 674
675#define GEN_OPCODE_MARK(name) \
18fba28c 676OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 677 .opc1 = 0xFF, \
678 .opc2 = 0xFF, \
679 .opc3 = 0xFF, \
18fba28c 680 .pad = { 0, }, \
79aceca5
FB		 681 .handler = { \
682 .inval = 0x00000000, \
9a64fbe4 683 .type = 0x00, \
79aceca5
FB		 684 .handler = NULL, \
685 }, \
3fc6c082 686 .oname = stringify(name), \
79aceca5
FB		 687}
688
689/* Start opcode list */
690GEN_OPCODE_MARK(start);
691
692/* Invalid instruction */
9a64fbe4
FB		 693GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
694{
e1833e1f 695 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 696}
697
79aceca5
FB		 698static opc_handler_t invalid_handler = {
699 .inval = 0xFFFFFFFF,
9a64fbe4 700 .type = PPC_NONE,
79aceca5
FB		 701 .handler = gen_invalid,
702};
703
e1571908
AJ		 704/*** Integer comparison ***/
705
706static always_inline void gen_op_cmp(TCGv t0, TCGv t1, int s, int crf)
707{
708 int l1, l2, l3;
709
710 tcg_gen_shri_i32(cpu_crf[crf], cpu_xer, XER_SO);
711 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
712
713 l1 = gen_new_label();
714 l2 = gen_new_label();
715 l3 = gen_new_label();
716 if (s) {
717 tcg_gen_brcond_tl(TCG_COND_LT, t0, t1, l1);
718 tcg_gen_brcond_tl(TCG_COND_GT, t0, t1, l2);
719 } else {
720 tcg_gen_brcond_tl(TCG_COND_LTU, t0, t1, l1);
721 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l2);
722 }
723 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
724 tcg_gen_br(l3);
725 gen_set_label(l1);
726 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
727 tcg_gen_br(l3);
728 gen_set_label(l2);
729 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
730 gen_set_label(l3);
731}
732
733static always_inline void gen_op_cmpi(TCGv t0, target_ulong t1, int s, int crf)
734{
735 TCGv temp = tcg_const_local_tl(t1);
736 gen_op_cmp(t0, temp, s, crf);
737 tcg_temp_free(temp);
738}
739
740#if defined(TARGET_PPC64)
741static always_inline void gen_op_cmp32(TCGv t0, TCGv t1, int s, int crf)
742{
743 TCGv t0_32, t1_32;
744 t0_32 = tcg_temp_local_new(TCG_TYPE_TL);
745 t1_32 = tcg_temp_local_new(TCG_TYPE_TL);
746 if (s) {
747 tcg_gen_ext32s_tl(t0_32, t0);
748 tcg_gen_ext32s_tl(t1_32, t1);
749 } else {
750 tcg_gen_ext32u_tl(t0_32, t0);
751 tcg_gen_ext32u_tl(t1_32, t1);
752 }
753 gen_op_cmp(t0_32, t1_32, s, crf);
754 tcg_temp_free(t1_32);
755 tcg_temp_free(t0_32);
756}
757
758static always_inline void gen_op_cmpi32(TCGv t0, target_ulong t1, int s, int crf)
759{
760 TCGv temp = tcg_const_local_tl(t1);
761 gen_op_cmp32(t0, temp, s, crf);
762 tcg_temp_free(temp);
763}
764#endif
765
766static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
767{
768#if defined(TARGET_PPC64)
769 if (!(ctx->sf_mode))
770 gen_op_cmpi32(reg, 0, 1, 0);
771 else
772#endif
773 gen_op_cmpi(reg, 0, 1, 0);
774}
775
776/* cmp */
777GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
778{
779#if defined(TARGET_PPC64)
780 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
781 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
782 1, crfD(ctx->opcode));
783 else
784#endif
785 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
786 1, crfD(ctx->opcode));
787}
788
789/* cmpi */
790GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
791{
792#if defined(TARGET_PPC64)
793 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
794 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
795 1, crfD(ctx->opcode));
796 else
797#endif
798 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
799 1, crfD(ctx->opcode));
800}
801
802/* cmpl */
803GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
804{
805#if defined(TARGET_PPC64)
806 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
807 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
808 0, crfD(ctx->opcode));
809 else
810#endif
811 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
812 0, crfD(ctx->opcode));
813}
814
815/* cmpli */
816GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
817{
818#if defined(TARGET_PPC64)
819 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
820 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
821 0, crfD(ctx->opcode));
822 else
823#endif
824 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
825 0, crfD(ctx->opcode));
826}
827
828/* isel (PowerPC 2.03 specification) */
829GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
830{
831 int l1, l2;
832 uint32_t bi = rC(ctx->opcode);
833 uint32_t mask;
834 TCGv temp;
835
836 l1 = gen_new_label();
837 l2 = gen_new_label();
838
839 mask = 1 << (3 - (bi & 0x03));
840 temp = tcg_temp_new(TCG_TYPE_I32);
841 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
842 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
843 if (rA(ctx->opcode) == 0)
844 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
845 else
846 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
847 tcg_gen_br(l2);
848 gen_set_label(l1);
849 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
850 gen_set_label(l2);
851}
852
79aceca5 853/*** Integer arithmetic ***/
d9bce9d9
JM		 854#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type) \
855GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 856{ \
f78fb44e
AJ		 857 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
858 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 859 gen_op_##name(); \
f78fb44e 860 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 861 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 862 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 863}
864
d9bce9d9
JM		 865#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type) \
866GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
79aceca5 867{ \
f78fb44e
AJ		 868 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
869 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 870 gen_op_##name(); \
f78fb44e 871 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 872 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 873 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 874}
875
d9bce9d9
JM		 876#define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
877GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 878{ \
f78fb44e 879 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 880 gen_op_##name(); \
f78fb44e 881 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 882 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 883 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5 884}
d9bce9d9
JM		 885#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type) \
886GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
79aceca5 887{ \
f78fb44e 888 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
79aceca5 889 gen_op_##name(); \
f78fb44e 890 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
76a66253 891 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 892 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 893}
894
895/* Two operands arithmetic functions */
d9bce9d9
JM		 896#define GEN_INT_ARITH2(name, opc1, opc2, opc3, type) \
897__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000, type) \
898__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
899
900/* Two operands arithmetic functions with no overflow allowed */
901#define GEN_INT_ARITHN(name, opc1, opc2, opc3, type) \
902__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400, type)
903
904/* One operand arithmetic functions */
905#define GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
906__GEN_INT_ARITH1(name, opc1, opc2, opc3, type) \
907__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
908
909#if defined(TARGET_PPC64)
910#define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type) \
911GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
912{ \
f78fb44e
AJ		 913 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
914 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 915 if (ctx->sf_mode) \
916 gen_op_##name##_64(); \
917 else \
918 gen_op_##name(); \
f78fb44e 919 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 920 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 921 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 922}
923
924#define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type) \
925GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
926{ \
f78fb44e
AJ		 927 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
928 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
d9bce9d9
JM		 929 if (ctx->sf_mode) \
930 gen_op_##name##_64(); \
931 else \
932 gen_op_##name(); \
f78fb44e 933 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 934 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 935 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 936}
937
938#define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
939GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
940{ \
f78fb44e 941 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 942 if (ctx->sf_mode) \
943 gen_op_##name##_64(); \
944 else \
945 gen_op_##name(); \
f78fb44e 946 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 947 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 948 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 949}
950#define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type) \
951GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type) \
952{ \
f78fb44e 953 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); \
d9bce9d9
JM		 954 if (ctx->sf_mode) \
955 gen_op_##name##_64(); \
956 else \
957 gen_op_##name(); \
f78fb44e 958 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]); \
d9bce9d9 959 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 960 gen_set_Rc0(ctx, cpu_T[0]); \
d9bce9d9
JM		 961}
962
963/* Two operands arithmetic functions */
964#define GEN_INT_ARITH2_64(name, opc1, opc2, opc3, type) \
965__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000000, type) \
966__GEN_INT_ARITH2_O_64(name##o, opc1, opc2, opc3 | 0x10, 0x00000000, type)
79aceca5
FB		 967
968/* Two operands arithmetic functions with no overflow allowed */
d9bce9d9
JM		 969#define GEN_INT_ARITHN_64(name, opc1, opc2, opc3, type) \
970__GEN_INT_ARITH2_64(name, opc1, opc2, opc3, 0x00000400, type)
79aceca5
FB		 971
972/* One operand arithmetic functions */
d9bce9d9
JM		 973#define GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
974__GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type) \
975__GEN_INT_ARITH1_O_64(name##o, opc1, opc2, opc3 | 0x10, type)
976#else
977#define GEN_INT_ARITH2_64 GEN_INT_ARITH2
978#define GEN_INT_ARITHN_64 GEN_INT_ARITHN
979#define GEN_INT_ARITH1_64 GEN_INT_ARITH1
980#endif
79aceca5
FB		 981
982/* add add. addo addo. */
39dd32ee
AJ		 983static always_inline void gen_op_add (void)
984{
985 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
986}
b068d6a7 987static always_inline void gen_op_addo (void)
d9bce9d9 988{
e55fd934 989 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 990 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 991 gen_op_check_addo();
992}
993#if defined(TARGET_PPC64)
994#define gen_op_add_64 gen_op_add
b068d6a7 995static always_inline void gen_op_addo_64 (void)
d9bce9d9 996{
e55fd934 997 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 998 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 999 gen_op_check_addo_64();
1000}
1001#endif
1002GEN_INT_ARITH2_64 (add, 0x1F, 0x0A, 0x08, PPC_INTEGER);
79aceca5 1003/* addc addc. addco addco. */
b068d6a7 1004static always_inline void gen_op_addc (void)
d9bce9d9 1005{
e55fd934 1006 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1007 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1008 gen_op_check_addc();
1009}
b068d6a7 1010static always_inline void gen_op_addco (void)
d9bce9d9 1011{
e55fd934 1012 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1013 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1014 gen_op_check_addc();
1015 gen_op_check_addo();
1016}
1017#if defined(TARGET_PPC64)
b068d6a7 1018static always_inline void gen_op_addc_64 (void)
d9bce9d9 1019{
e55fd934 1020 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1021 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1022 gen_op_check_addc_64();
1023}
b068d6a7 1024static always_inline void gen_op_addco_64 (void)
d9bce9d9 1025{
e55fd934 1026 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1027 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
d9bce9d9
JM		 1028 gen_op_check_addc_64();
1029 gen_op_check_addo_64();
1030}
1031#endif
1032GEN_INT_ARITH2_64 (addc, 0x1F, 0x0A, 0x00, PPC_INTEGER);
79aceca5 1033/* adde adde. addeo addeo. */
b068d6a7 1034static always_inline void gen_op_addeo (void)
d9bce9d9 1035{
e55fd934 1036 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1037 gen_op_adde();
1038 gen_op_check_addo();
1039}
1040#if defined(TARGET_PPC64)
b068d6a7 1041static always_inline void gen_op_addeo_64 (void)
d9bce9d9 1042{
e55fd934 1043 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1044 gen_op_adde_64();
1045 gen_op_check_addo_64();
1046}
1047#endif
1048GEN_INT_ARITH2_64 (adde, 0x1F, 0x0A, 0x04, PPC_INTEGER);
79aceca5 1049/* addme addme. addmeo addmeo. */
b068d6a7 1050static always_inline void gen_op_addme (void)
d9bce9d9 1051{
e55fd934 1052 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1053 gen_op_add_me();
1054}
1055#if defined(TARGET_PPC64)
b068d6a7 1056static always_inline void gen_op_addme_64 (void)
d9bce9d9 1057{
e55fd934 1058 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1059 gen_op_add_me_64();
1060}
1061#endif
1062GEN_INT_ARITH1_64 (addme, 0x1F, 0x0A, 0x07, PPC_INTEGER);
79aceca5 1063/* addze addze. addzeo addzeo. */
b068d6a7 1064static always_inline void gen_op_addze (void)
d9bce9d9 1065{
e55fd934 1066 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1067 gen_op_add_ze();
1068 gen_op_check_addc();
1069}
b068d6a7 1070static always_inline void gen_op_addzeo (void)
d9bce9d9 1071{
e55fd934 1072 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1073 gen_op_add_ze();
1074 gen_op_check_addc();
1075 gen_op_check_addo();
1076}
1077#if defined(TARGET_PPC64)
b068d6a7 1078static always_inline void gen_op_addze_64 (void)
d9bce9d9 1079{
e55fd934 1080 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1081 gen_op_add_ze();
1082 gen_op_check_addc_64();
1083}
b068d6a7 1084static always_inline void gen_op_addzeo_64 (void)
d9bce9d9 1085{
e55fd934 1086 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
d9bce9d9
JM		 1087 gen_op_add_ze();
1088 gen_op_check_addc_64();
1089 gen_op_check_addo_64();
1090}
1091#endif
1092GEN_INT_ARITH1_64 (addze, 0x1F, 0x0A, 0x06, PPC_INTEGER);
79aceca5 1093/* divw divw. divwo divwo. */
d9bce9d9 1094GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F, PPC_INTEGER);
79aceca5 1095/* divwu divwu. divwuo divwuo. */
d9bce9d9 1096GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E, PPC_INTEGER);
79aceca5 1097/* mulhw mulhw. */
d9bce9d9 1098GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02, PPC_INTEGER);
79aceca5 1099/* mulhwu mulhwu. */
d9bce9d9 1100GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00, PPC_INTEGER);
79aceca5 1101/* mullw mullw. mullwo mullwo. */
d9bce9d9 1102GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07, PPC_INTEGER);
79aceca5 1103/* neg neg. nego nego. */
d9bce9d9 1104GEN_INT_ARITH1_64 (neg, 0x1F, 0x08, 0x03, PPC_INTEGER);
79aceca5 1105/* subf subf. subfo subfo. */
7c417963
AJ		 1106static always_inline void gen_op_subf (void)
1107{
1108 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1109}
b068d6a7 1110static always_inline void gen_op_subfo (void)
d9bce9d9 1111{
f0413473 1112 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 1113 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 1114 gen_op_check_addo();
d9bce9d9
JM		 1115}
1116#if defined(TARGET_PPC64)
1117#define gen_op_subf_64 gen_op_subf
b068d6a7 1118static always_inline void gen_op_subfo_64 (void)
d9bce9d9 1119{
f0413473 1120 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 1121 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
c3e10c7b 1122 gen_op_check_addo_64();
d9bce9d9
JM		 1123}
1124#endif
1125GEN_INT_ARITH2_64 (subf, 0x1F, 0x08, 0x01, PPC_INTEGER);
79aceca5 1126/* subfc subfc. subfco subfco. */
b068d6a7 1127static always_inline void gen_op_subfc (void)
d9bce9d9 1128{
7c417963 1129 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1130 gen_op_check_subfc();
1131}
b068d6a7 1132static always_inline void gen_op_subfco (void)
d9bce9d9 1133{
f0413473 1134 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
7c417963 1135 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 1136 gen_op_check_subfc();
c3e10c7b 1137 gen_op_check_addo();
d9bce9d9
JM		 1138}
1139#if defined(TARGET_PPC64)
b068d6a7 1140static always_inline void gen_op_subfc_64 (void)
d9bce9d9 1141{
7c417963 1142 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1143 gen_op_check_subfc_64();
1144}
b068d6a7 1145static always_inline void gen_op_subfco_64 (void)
d9bce9d9 1146{
f0413473 1147 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
7c417963 1148 tcg_gen_sub_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
d9bce9d9 1149 gen_op_check_subfc_64();
c3e10c7b 1150 gen_op_check_addo_64();
d9bce9d9
JM		 1151}
1152#endif
1153GEN_INT_ARITH2_64 (subfc, 0x1F, 0x08, 0x00, PPC_INTEGER);
79aceca5 1154/* subfe subfe. subfeo subfeo. */
b068d6a7 1155static always_inline void gen_op_subfeo (void)
d9bce9d9 1156{
f0413473 1157 tcg_gen_not_tl(cpu_T[2], cpu_T[0]);
d9bce9d9 1158 gen_op_subfe();
c3e10c7b 1159 gen_op_check_addo();
d9bce9d9
JM		 1160}
1161#if defined(TARGET_PPC64)
1162#define gen_op_subfe_64 gen_op_subfe
b068d6a7 1163static always_inline void gen_op_subfeo_64 (void)
d9bce9d9 1164{
f0413473 1165 tcg_gen_not_i64(cpu_T[2], cpu_T[0]);
d9bce9d9 1166 gen_op_subfe_64();
c3e10c7b 1167 gen_op_check_addo_64();
d9bce9d9
JM		 1168}
1169#endif
1170GEN_INT_ARITH2_64 (subfe, 0x1F, 0x08, 0x04, PPC_INTEGER);
79aceca5 1171/* subfme subfme. subfmeo subfmeo. */
d9bce9d9 1172GEN_INT_ARITH1_64 (subfme, 0x1F, 0x08, 0x07, PPC_INTEGER);
79aceca5 1173/* subfze subfze. subfzeo subfzeo. */
d9bce9d9 1174GEN_INT_ARITH1_64 (subfze, 0x1F, 0x08, 0x06, PPC_INTEGER);
79aceca5
FB		 1175/* addi */
1176GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1177{
76a66253 1178 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1179
1180 if (rA(ctx->opcode) == 0) {
76a66253 1181 /* li case */
02f4f6c2 1182 tcg_gen_movi_tl(cpu_T[0], simm);
79aceca5 1183 } else {
f78fb44e 1184 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1185 if (likely(simm != 0))
39dd32ee 1186 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
79aceca5 1187 }
f78fb44e 1188 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1189}
1190/* addic */
1191GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1192{
76a66253
JM		 1193 target_long simm = SIMM(ctx->opcode);
1194
f78fb44e 1195 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1196 if (likely(simm != 0)) {
e55fd934 1197 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1198 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1199#if defined(TARGET_PPC64)
1200 if (ctx->sf_mode)
1201 gen_op_check_addc_64();
1202 else
1203#endif
1204 gen_op_check_addc();
e864cabd 1205 } else {
3d7b417e 1206 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1207 }
f78fb44e 1208 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1209}
1210/* addic. */
c7697e1f 1211GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1212{
76a66253
JM		 1213 target_long simm = SIMM(ctx->opcode);
1214
f78fb44e 1215 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1216 if (likely(simm != 0)) {
e55fd934 1217 tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
39dd32ee 1218 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm);
d9bce9d9
JM		 1219#if defined(TARGET_PPC64)
1220 if (ctx->sf_mode)
1221 gen_op_check_addc_64();
1222 else
1223#endif
1224 gen_op_check_addc();
966439a6 1225 } else {
3d7b417e 1226 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 1227 }
f78fb44e 1228 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
e1571908 1229 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1230}
1231/* addis */
1232GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1233{
76a66253 1234 target_long simm = SIMM(ctx->opcode);
79aceca5
FB		 1235
1236 if (rA(ctx->opcode) == 0) {
76a66253 1237 /* lis case */
02f4f6c2 1238 tcg_gen_movi_tl(cpu_T[0], simm << 16);
79aceca5 1239 } else {
f78fb44e 1240 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 1241 if (likely(simm != 0))
39dd32ee 1242 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << 16);
79aceca5 1243 }
f78fb44e 1244 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1245}
1246/* mulli */
1247GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1248{
f78fb44e 1249 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
79aceca5 1250 gen_op_mulli(SIMM(ctx->opcode));
f78fb44e 1251 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1252}
1253/* subfic */
1254GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1255{
f78fb44e 1256 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
d9bce9d9
JM		 1257#if defined(TARGET_PPC64)
1258 if (ctx->sf_mode)
1259 gen_op_subfic_64(SIMM(ctx->opcode));
1260 else
1261#endif
1262 gen_op_subfic(SIMM(ctx->opcode));
f78fb44e 1263 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1264}
1265
d9bce9d9
JM		 1266#if defined(TARGET_PPC64)
1267/* mulhd mulhd. */
a750fc0b 1268GEN_INT_ARITHN (mulhd, 0x1F, 0x09, 0x02, PPC_64B);
d9bce9d9 1269/* mulhdu mulhdu. */
a750fc0b 1270GEN_INT_ARITHN (mulhdu, 0x1F, 0x09, 0x00, PPC_64B);
d9bce9d9 1271/* mulld mulld. mulldo mulldo. */
a750fc0b 1272GEN_INT_ARITH2 (mulld, 0x1F, 0x09, 0x07, PPC_64B);
d9bce9d9 1273/* divd divd. divdo divdo. */
a750fc0b 1274GEN_INT_ARITH2 (divd, 0x1F, 0x09, 0x0F, PPC_64B);
d9bce9d9 1275/* divdu divdu. divduo divduo. */
a750fc0b 1276GEN_INT_ARITH2 (divdu, 0x1F, 0x09, 0x0E, PPC_64B);
d9bce9d9
JM		 1277#endif
1278
79aceca5 1279/*** Integer logical ***/
d9bce9d9
JM		 1280#define __GEN_LOGICAL2(name, opc2, opc3, type) \
1281GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type) \
79aceca5 1282{ \
f78fb44e
AJ		 1283 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
1284 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]); \
79aceca5 1285 gen_op_##name(); \
f78fb44e 1286 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
76a66253 1287 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 1288 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5 1289}
d9bce9d9
JM		 1290#define GEN_LOGICAL2(name, opc, type) \
1291__GEN_LOGICAL2(name, 0x1C, opc, type)
79aceca5 1292
d9bce9d9
JM		 1293#define GEN_LOGICAL1(name, opc, type) \
1294GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1295{ \
f78fb44e 1296 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]); \
79aceca5 1297 gen_op_##name(); \
f78fb44e 1298 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
76a66253 1299 if (unlikely(Rc(ctx->opcode) != 0)) \
e1571908 1300 gen_set_Rc0(ctx, cpu_T[0]); \
79aceca5
FB		 1301}
1302
1303/* and & and. */
d9bce9d9 1304GEN_LOGICAL2(and, 0x00, PPC_INTEGER);
79aceca5 1305/* andc & andc. */
d9bce9d9 1306GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
79aceca5 1307/* andi. */
c7697e1f 1308GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1309{
f78fb44e 1310 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
0df5bdbe 1311 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
f78fb44e 1312 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
e1571908 1313 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1314}
1315/* andis. */
c7697e1f 1316GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1317{
f78fb44e 1318 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
0df5bdbe 1319 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
f78fb44e 1320 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
e1571908 1321 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1322}
1323
1324/* cntlzw */
d9bce9d9 1325GEN_LOGICAL1(cntlzw, 0x00, PPC_INTEGER);
79aceca5 1326/* eqv & eqv. */
d9bce9d9 1327GEN_LOGICAL2(eqv, 0x08, PPC_INTEGER);
79aceca5 1328/* extsb & extsb. */
d9bce9d9 1329GEN_LOGICAL1(extsb, 0x1D, PPC_INTEGER);
79aceca5 1330/* extsh & extsh. */
d9bce9d9 1331GEN_LOGICAL1(extsh, 0x1C, PPC_INTEGER);
79aceca5 1332/* nand & nand. */
d9bce9d9 1333GEN_LOGICAL2(nand, 0x0E, PPC_INTEGER);
79aceca5 1334/* nor & nor. */
d9bce9d9 1335GEN_LOGICAL2(nor, 0x03, PPC_INTEGER);
9a64fbe4 1336
79aceca5 1337/* or & or. */
9a64fbe4
FB		 1338GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1339{
76a66253
JM		 1340 int rs, ra, rb;
1341
1342 rs = rS(ctx->opcode);
1343 ra = rA(ctx->opcode);
1344 rb = rB(ctx->opcode);
1345 /* Optimisation for mr. ri case */
1346 if (rs != ra || rs != rb) {
f78fb44e 1347 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
76a66253 1348 if (rs != rb) {
f78fb44e 1349 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 1350 gen_op_or();
1351 }
f78fb44e 1352 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253 1353 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1354 gen_set_Rc0(ctx, cpu_T[0]);
76a66253 1355 } else if (unlikely(Rc(ctx->opcode) != 0)) {
f78fb44e 1356 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
e1571908 1357 gen_set_Rc0(ctx, cpu_T[0]);
c80f84e3
JM		 1358#if defined(TARGET_PPC64)
1359 } else {
1360 switch (rs) {
1361 case 1:
1362 /* Set process priority to low */
1363 gen_op_store_pri(2);
1364 break;
1365 case 6:
1366 /* Set process priority to medium-low */
1367 gen_op_store_pri(3);
1368 break;
1369 case 2:
1370 /* Set process priority to normal */
1371 gen_op_store_pri(4);
1372 break;
be147d08
JM		 1373#if !defined(CONFIG_USER_ONLY)
1374 case 31:
1375 if (ctx->supervisor > 0) {
1376 /* Set process priority to very low */
1377 gen_op_store_pri(1);
1378 }
1379 break;
1380 case 5:
1381 if (ctx->supervisor > 0) {
1382 /* Set process priority to medium-hight */
1383 gen_op_store_pri(5);
1384 }
1385 break;
1386 case 3:
1387 if (ctx->supervisor > 0) {
1388 /* Set process priority to high */
1389 gen_op_store_pri(6);
1390 }
1391 break;
be147d08
JM		 1392 case 7:
1393 if (ctx->supervisor > 1) {
1394 /* Set process priority to very high */
1395 gen_op_store_pri(7);
1396 }
1397 break;
be147d08 1398#endif
c80f84e3
JM		 1399 default:
1400 /* nop */
1401 break;
1402 }
1403#endif
9a64fbe4 1404 }
9a64fbe4
FB		 1405}
1406
79aceca5 1407/* orc & orc. */
d9bce9d9 1408GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
79aceca5 1409/* xor & xor. */
9a64fbe4
FB		 1410GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1411{
f78fb44e 1412 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4
FB		 1413 /* Optimisation for "set to zero" case */
1414 if (rS(ctx->opcode) != rB(ctx->opcode)) {
f78fb44e 1415 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
9a64fbe4
FB		 1416 gen_op_xor();
1417 } else {
86c581dc 1418 tcg_gen_movi_tl(cpu_T[0], 0);
9a64fbe4 1419 }
f78fb44e 1420 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1421 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1422 gen_set_Rc0(ctx, cpu_T[0]);
9a64fbe4 1423}
79aceca5
FB		 1424/* ori */
1425GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1426{
76a66253 1427 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1428
9a64fbe4
FB		 1429 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1430 /* NOP */
76a66253 1431 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1432 return;
76a66253 1433 }
f78fb44e 1434 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253 1435 if (likely(uimm != 0))
79aceca5 1436 gen_op_ori(uimm);
f78fb44e 1437 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1438}
1439/* oris */
1440GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1441{
76a66253 1442 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1443
9a64fbe4
FB		 1444 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1445 /* NOP */
1446 return;
76a66253 1447 }
f78fb44e 1448 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253 1449 if (likely(uimm != 0))
79aceca5 1450 gen_op_ori(uimm << 16);
f78fb44e 1451 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1452}
1453/* xori */
1454GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1455{
76a66253 1456 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1457
1458 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1459 /* NOP */
1460 return;
1461 }
f78fb44e 1462 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1463 if (likely(uimm != 0))
1464 gen_op_xori(uimm);
f78fb44e 1465 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1466}
1467
1468/* xoris */
1469GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1470{
76a66253 1471 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1472
1473 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1474 /* NOP */
1475 return;
1476 }
f78fb44e 1477 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1478 if (likely(uimm != 0))
1479 gen_op_xori(uimm << 16);
f78fb44e 1480 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
79aceca5
FB		 1481}
1482
d9bce9d9 1483/* popcntb : PowerPC 2.03 specification */
05332d70 1484GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1485{
f78fb44e 1486 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1487#if defined(TARGET_PPC64)
1488 if (ctx->sf_mode)
6676f424 1489 gen_op_popcntb_64();
d9bce9d9
JM		 1490 else
1491#endif
6676f424 1492 gen_op_popcntb();
f78fb44e 1493 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9
JM		 1494}
1495
1496#if defined(TARGET_PPC64)
1497/* extsw & extsw. */
1498GEN_LOGICAL1(extsw, 0x1E, PPC_64B);
1499/* cntlzd */
1500GEN_LOGICAL1(cntlzd, 0x01, PPC_64B);
1501#endif
1502
79aceca5
FB		 1503/*** Integer rotate ***/
1504/* rlwimi & rlwimi. */
1505GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1506{
76a66253
JM		 1507 target_ulong mask;
1508 uint32_t mb, me, sh;
79aceca5
FB		 1509
1510 mb = MB(ctx->opcode);
1511 me = ME(ctx->opcode);
76a66253 1512 sh = SH(ctx->opcode);
76a66253
JM		 1513 if (likely(sh == 0)) {
1514 if (likely(mb == 0 && me == 31)) {
f78fb44e 1515 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1516 goto do_store;
1517 } else if (likely(mb == 31 && me == 0)) {
f78fb44e 1518 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1519 goto do_store;
1520 }
f78fb44e
AJ		 1521 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1522 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1523 goto do_mask;
1524 }
f78fb44e
AJ		 1525 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1526 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 1527 gen_op_rotli32_T0(SH(ctx->opcode));
1528 do_mask:
1529#if defined(TARGET_PPC64)
1530 mb += 32;
1531 me += 32;
1532#endif
1533 mask = MASK(mb, me);
0df5bdbe
AJ		 1534 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1535 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
76a66253
JM		 1536 gen_op_or();
1537 do_store:
f78fb44e 1538 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1539 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1540 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1541}
1542/* rlwinm & rlwinm. */
1543GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1544{
1545 uint32_t mb, me, sh;
3b46e624 1546
79aceca5
FB		 1547 sh = SH(ctx->opcode);
1548 mb = MB(ctx->opcode);
1549 me = ME(ctx->opcode);
f78fb44e 1550 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 1551 if (likely(sh == 0)) {
1552 goto do_mask;
1553 }
1554 if (likely(mb == 0)) {
1555 if (likely(me == 31)) {
1556 gen_op_rotli32_T0(sh);
1557 goto do_store;
1558 } else if (likely(me == (31 - sh))) {
1559 gen_op_sli_T0(sh);
1560 goto do_store;
79aceca5 1561 }
76a66253
JM		 1562 } else if (likely(me == 31)) {
1563 if (likely(sh == (32 - mb))) {
1564 gen_op_srli_T0(mb);
1565 goto do_store;
79aceca5
FB		 1566 }
1567 }
76a66253
JM		 1568 gen_op_rotli32_T0(sh);
1569 do_mask:
1570#if defined(TARGET_PPC64)
1571 mb += 32;
1572 me += 32;
1573#endif
0df5bdbe 1574 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
76a66253 1575 do_store:
f78fb44e 1576 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1577 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1578 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1579}
1580/* rlwnm & rlwnm. */
1581GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1582{
1583 uint32_t mb, me;
1584
1585 mb = MB(ctx->opcode);
1586 me = ME(ctx->opcode);
f78fb44e
AJ		 1587 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1588 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 1589 gen_op_rotl32_T0_T1();
1590 if (unlikely(mb != 0 || me != 31)) {
1591#if defined(TARGET_PPC64)
1592 mb += 32;
1593 me += 32;
1594#endif
0df5bdbe 1595 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
79aceca5 1596 }
f78fb44e 1597 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1598 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1599 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1600}
1601
d9bce9d9
JM		 1602#if defined(TARGET_PPC64)
1603#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1604GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1605{ \
1606 gen_##name(ctx, 0); \
1607} \
c7697e1f
JM		 1608GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1609 PPC_64B) \
d9bce9d9
JM		 1610{ \
1611 gen_##name(ctx, 1); \
1612}
1613#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1614GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1615{ \
1616 gen_##name(ctx, 0, 0); \
1617} \
c7697e1f
JM		 1618GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1619 PPC_64B) \
d9bce9d9
JM		 1620{ \
1621 gen_##name(ctx, 0, 1); \
1622} \
c7697e1f
JM		 1623GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1624 PPC_64B) \
d9bce9d9
JM		 1625{ \
1626 gen_##name(ctx, 1, 0); \
1627} \
c7697e1f
JM		 1628GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1629 PPC_64B) \
d9bce9d9
JM		 1630{ \
1631 gen_##name(ctx, 1, 1); \
1632}
51789c41 1633
b068d6a7
JM		 1634static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1635 uint32_t me, uint32_t sh)
51789c41 1636{
f78fb44e 1637 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41
JM		 1638 if (likely(sh == 0)) {
1639 goto do_mask;
1640 }
1641 if (likely(mb == 0)) {
1642 if (likely(me == 63)) {
40d0591e 1643 gen_op_rotli64_T0(sh);
51789c41
JM		 1644 goto do_store;
1645 } else if (likely(me == (63 - sh))) {
1646 gen_op_sli_T0(sh);
1647 goto do_store;
1648 }
1649 } else if (likely(me == 63)) {
1650 if (likely(sh == (64 - mb))) {
40d0591e 1651 gen_op_srli_T0_64(mb);
51789c41
JM		 1652 goto do_store;
1653 }
1654 }
1655 gen_op_rotli64_T0(sh);
1656 do_mask:
0df5bdbe 1657 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1658 do_store:
f78fb44e 1659 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41 1660 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1661 gen_set_Rc0(ctx, cpu_T[0]);
51789c41 1662}
d9bce9d9 1663/* rldicl - rldicl. */
b068d6a7 1664static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1665{
51789c41 1666 uint32_t sh, mb;
d9bce9d9 1667
9d53c753
JM		 1668 sh = SH(ctx->opcode) | (shn << 5);
1669 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1670 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1671}
51789c41 1672GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1673/* rldicr - rldicr. */
b068d6a7 1674static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1675{
51789c41 1676 uint32_t sh, me;
d9bce9d9 1677
9d53c753
JM		 1678 sh = SH(ctx->opcode) | (shn << 5);
1679 me = MB(ctx->opcode) | (men << 5);
51789c41 1680 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1681}
51789c41 1682GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1683/* rldic - rldic. */
b068d6a7 1684static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1685{
51789c41 1686 uint32_t sh, mb;
d9bce9d9 1687
9d53c753
JM		 1688 sh = SH(ctx->opcode) | (shn << 5);
1689 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1690 gen_rldinm(ctx, mb, 63 - sh, sh);
1691}
1692GEN_PPC64_R4(rldic, 0x1E, 0x04);
1693
b068d6a7
JM		 1694static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1695 uint32_t me)
51789c41 1696{
f78fb44e
AJ		 1697 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1698 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
51789c41
JM		 1699 gen_op_rotl64_T0_T1();
1700 if (unlikely(mb != 0 || me != 63)) {
0df5bdbe 1701 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
51789c41 1702 }
f78fb44e 1703 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41 1704 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1705 gen_set_Rc0(ctx, cpu_T[0]);
d9bce9d9 1706}
51789c41 1707
d9bce9d9 1708/* rldcl - rldcl. */
b068d6a7 1709static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1710{
51789c41 1711 uint32_t mb;
d9bce9d9 1712
9d53c753 1713 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1714 gen_rldnm(ctx, mb, 63);
d9bce9d9 1715}
36081602 1716GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1717/* rldcr - rldcr. */
b068d6a7 1718static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1719{
51789c41 1720 uint32_t me;
d9bce9d9 1721
9d53c753 1722 me = MB(ctx->opcode) | (men << 5);
51789c41 1723 gen_rldnm(ctx, 0, me);
d9bce9d9 1724}
36081602 1725GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1726/* rldimi - rldimi. */
b068d6a7 1727static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1728{
51789c41 1729 uint64_t mask;
271a916e 1730 uint32_t sh, mb, me;
d9bce9d9 1731
9d53c753
JM		 1732 sh = SH(ctx->opcode) | (shn << 5);
1733 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1734 me = 63 - sh;
51789c41
JM		 1735 if (likely(sh == 0)) {
1736 if (likely(mb == 0)) {
f78fb44e 1737 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
51789c41 1738 goto do_store;
51789c41 1739 }
f78fb44e
AJ		 1740 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1741 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
51789c41
JM		 1742 goto do_mask;
1743 }
f78fb44e
AJ		 1744 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
1745 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
40d0591e 1746 gen_op_rotli64_T0(sh);
51789c41 1747 do_mask:
271a916e 1748 mask = MASK(mb, me);
0df5bdbe
AJ		 1749 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
1750 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
51789c41
JM		 1751 gen_op_or();
1752 do_store:
f78fb44e 1753 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
51789c41 1754 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1755 gen_set_Rc0(ctx, cpu_T[0]);
d9bce9d9 1756}
36081602 1757GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1758#endif
1759
79aceca5
FB		 1760/*** Integer shift ***/
1761/* slw & slw. */
d9bce9d9 1762__GEN_LOGICAL2(slw, 0x18, 0x00, PPC_INTEGER);
79aceca5 1763/* sraw & sraw. */
d9bce9d9 1764__GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
79aceca5
FB		 1765/* srawi & srawi. */
1766GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1767{
d9bce9d9 1768 int mb, me;
f78fb44e 1769 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9 1770 if (SH(ctx->opcode) != 0) {
e55fd934 1771 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1772 mb = 32 - SH(ctx->opcode);
1773 me = 31;
1774#if defined(TARGET_PPC64)
1775 mb += 32;
1776 me += 32;
1777#endif
1778 gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
1779 }
f78fb44e 1780 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 1781 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1782 gen_set_Rc0(ctx, cpu_T[0]);
79aceca5
FB		 1783}
1784/* srw & srw. */
d9bce9d9
JM		 1785__GEN_LOGICAL2(srw, 0x18, 0x10, PPC_INTEGER);
1786
1787#if defined(TARGET_PPC64)
1788/* sld & sld. */
1789__GEN_LOGICAL2(sld, 0x1B, 0x00, PPC_64B);
1790/* srad & srad. */
1791__GEN_LOGICAL2(srad, 0x1A, 0x18, PPC_64B);
1792/* sradi & sradi. */
b068d6a7 1793static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9
JM		 1794{
1795 uint64_t mask;
1796 int sh, mb, me;
1797
f78fb44e 1798 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1799 sh = SH(ctx->opcode) + (n << 5);
1800 if (sh != 0) {
e55fd934 1801 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
d9bce9d9
JM		 1802 mb = 64 - SH(ctx->opcode);
1803 me = 63;
1804 mask = MASK(mb, me);
1805 gen_op_sradi(sh, mask >> 32, mask);
1806 }
f78fb44e 1807 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
d9bce9d9 1808 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 1809 gen_set_Rc0(ctx, cpu_T[0]);
d9bce9d9 1810}
c7697e1f 1811GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1812{
1813 gen_sradi(ctx, 0);
1814}
c7697e1f 1815GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 1816{
1817 gen_sradi(ctx, 1);
1818}
1819/* srd & srd. */
1820__GEN_LOGICAL2(srd, 0x1B, 0x10, PPC_64B);
1821#endif
79aceca5
FB		 1822
1823/*** Floating-Point arithmetic ***/
7c58044c 1824#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 1825GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 1826{ \
76a66253 1827 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1828 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1829 return; \
1830 } \
a5e26afa
AJ		 1831 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1832 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
1833 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1834 gen_reset_fpstatus(); \
4ecc3190
FB		 1835 gen_op_f##op(); \
1836 if (isfloat) { \
1837 gen_op_frsp(); \
1838 } \
a5e26afa 1839 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1840 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 1841}
1842
7c58044c
JM		 1843#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1844_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1845_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 1846
7c58044c
JM		 1847#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1848GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1849{ \
76a66253 1850 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1851 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1852 return; \
1853 } \
a5e26afa
AJ		 1854 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1855 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1856 gen_reset_fpstatus(); \
4ecc3190
FB		 1857 gen_op_f##op(); \
1858 if (isfloat) { \
1859 gen_op_frsp(); \
1860 } \
a5e26afa 1861 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1862 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1863}
7c58044c
JM		 1864#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1865_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1866_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1867
7c58044c
JM		 1868#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1869GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 1870{ \
76a66253 1871 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1872 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1873 return; \
1874 } \
a5e26afa
AJ		 1875 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
1876 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
7c58044c 1877 gen_reset_fpstatus(); \
4ecc3190
FB		 1878 gen_op_f##op(); \
1879 if (isfloat) { \
1880 gen_op_frsp(); \
1881 } \
a5e26afa 1882 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1883 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 1884}
7c58044c
JM		 1885#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1886_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1887_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 1888
7c58044c 1889#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 1890GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 1891{ \
76a66253 1892 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1893 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1894 return; \
1895 } \
a5e26afa 1896 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1897 gen_reset_fpstatus(); \
9a64fbe4 1898 gen_op_f##name(); \
a5e26afa 1899 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1900 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1901}
1902
7c58044c 1903#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 1904GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 1905{ \
76a66253 1906 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 1907 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 1908 return; \
1909 } \
a5e26afa 1910 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 1911 gen_reset_fpstatus(); \
9a64fbe4 1912 gen_op_f##name(); \
a5e26afa 1913 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 1914 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 1915}
1916
9a64fbe4 1917/* fadd - fadds */
7c58044c 1918GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1919/* fdiv - fdivs */
7c58044c 1920GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 1921/* fmul - fmuls */
7c58044c 1922GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 1923
d7e4b87e 1924/* fre */
7c58044c 1925GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 1926
a750fc0b 1927/* fres */
7c58044c 1928GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 1929
a750fc0b 1930/* frsqrte */
7c58044c
JM		 1931GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
1932
1933/* frsqrtes */
1934static always_inline void gen_op_frsqrtes (void)
1935{
1936 gen_op_frsqrte();
1937 gen_op_frsp();
1938}
1b413d55 1939GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 1940
a750fc0b 1941/* fsel */
7c58044c 1942_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 1943/* fsub - fsubs */
7c58044c 1944GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 1945/* Optional: */
1946/* fsqrt */
a750fc0b 1947GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 1948{
76a66253 1949 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1950 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 1951 return;
1952 }
a5e26afa 1953 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1954 gen_reset_fpstatus();
c7d344af 1955 gen_op_fsqrt();
a5e26afa 1956 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1957 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 1958}
79aceca5 1959
a750fc0b 1960GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 1961{
76a66253 1962 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 1963 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 1964 return;
1965 }
a5e26afa 1966 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 1967 gen_reset_fpstatus();
4ecc3190
FB		 1968 gen_op_fsqrt();
1969 gen_op_frsp();
a5e26afa 1970 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 1971 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 1972}
1973
1974/*** Floating-Point multiply-and-add ***/
4ecc3190 1975/* fmadd - fmadds */
7c58044c 1976GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 1977/* fmsub - fmsubs */
7c58044c 1978GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 1979/* fnmadd - fnmadds */
7c58044c 1980GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 1981/* fnmsub - fnmsubs */
7c58044c 1982GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 1983
1984/*** Floating-Point round & convert ***/
1985/* fctiw */
7c58044c 1986GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 1987/* fctiwz */
7c58044c 1988GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 1989/* frsp */
7c58044c 1990GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 1991#if defined(TARGET_PPC64)
1992/* fcfid */
7c58044c 1993GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 1994/* fctid */
7c58044c 1995GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 1996/* fctidz */
7c58044c 1997GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 1998#endif
79aceca5 1999
d7e4b87e 2000/* frin */
7c58044c 2001GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2002/* friz */
7c58044c 2003GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2004/* frip */
7c58044c 2005GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2006/* frim */
7c58044c 2007GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2008
79aceca5
FB		 2009/*** Floating-Point compare ***/
2010/* fcmpo */
76a66253 2011GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2012{
76a66253 2013 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2014 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2015 return;
2016 }
a5e26afa
AJ		 2017 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2018 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2019 gen_reset_fpstatus();
e1571908 2020 tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2021 gen_op_float_check_status();
79aceca5
FB		 2022}
2023
2024/* fcmpu */
76a66253 2025GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2026{
76a66253 2027 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2028 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2029 return;
2030 }
a5e26afa
AJ		 2031 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2032 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2033 gen_reset_fpstatus();
e1571908 2034 tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2035 gen_op_float_check_status();
79aceca5
FB		 2036}
2037
9a64fbe4
FB		 2038/*** Floating-point move ***/
2039/* fabs */
7c58044c
JM		 2040/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2041GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2042
2043/* fmr - fmr. */
7c58044c 2044/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2045GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2046{
76a66253 2047 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2048 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2049 return;
2050 }
a5e26afa
AJ		 2051 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2052 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2053 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2054}
2055
2056/* fnabs */
7c58044c
JM		 2057/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2058GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2059/* fneg */
7c58044c
JM		 2060/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2061GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2062
79aceca5
FB		 2063/*** Floating-Point status & ctrl register ***/
2064/* mcrfs */
2065GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2066{
7c58044c
JM		 2067 int bfa;
2068
76a66253 2069 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2070 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2071 return;
2072 }
7c58044c
JM		 2073 gen_optimize_fprf();
2074 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2075 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2076 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
7c58044c 2077 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 2078}
2079
2080/* mffs */
2081GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2082{
76a66253 2083 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2084 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2085 return;
2086 }
7c58044c
JM		 2087 gen_optimize_fprf();
2088 gen_reset_fpstatus();
2089 gen_op_load_fpscr_FT0();
a5e26afa 2090 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2091 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2092}
2093
2094/* mtfsb0 */
2095GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2096{
fb0eaffc 2097 uint8_t crb;
3b46e624 2098
76a66253 2099 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2100 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2101 return;
2102 }
7c58044c
JM		 2103 crb = 32 - (crbD(ctx->opcode) >> 2);
2104 gen_optimize_fprf();
2105 gen_reset_fpstatus();
2106 if (likely(crb != 30 && crb != 29))
2107 gen_op_fpscr_resetbit(~(1 << crb));
2108 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2109 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2110 }
79aceca5
FB		 2111}
2112
2113/* mtfsb1 */
2114GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2115{
fb0eaffc 2116 uint8_t crb;
3b46e624 2117
76a66253 2118 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2119 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2120 return;
2121 }
7c58044c
JM		 2122 crb = 32 - (crbD(ctx->opcode) >> 2);
2123 gen_optimize_fprf();
2124 gen_reset_fpstatus();
2125 /* XXX: we pretend we can only do IEEE floating-point computations */
2126 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2127 gen_op_fpscr_setbit(crb);
2128 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2129 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2130 }
2131 /* We can raise a differed exception */
2132 gen_op_float_check_status();
79aceca5
FB		 2133}
2134
2135/* mtfsf */
2136GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2137{
76a66253 2138 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2139 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2140 return;
2141 }
7c58044c 2142 gen_optimize_fprf();
a5e26afa 2143 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2144 gen_reset_fpstatus();
28b6751f 2145 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c 2146 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2147 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2148 }
2149 /* We can raise a differed exception */
2150 gen_op_float_check_status();
79aceca5
FB		 2151}
2152
2153/* mtfsfi */
2154GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2155{
7c58044c
JM		 2156 int bf, sh;
2157
76a66253 2158 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2159 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2160 return;
2161 }
7c58044c
JM		 2162 bf = crbD(ctx->opcode) >> 2;
2163 sh = 7 - bf;
2164 gen_optimize_fprf();
489251fa 2165 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
7c58044c
JM		 2166 gen_reset_fpstatus();
2167 gen_op_store_fpscr(1 << sh);
2168 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2169 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2170 }
2171 /* We can raise a differed exception */
2172 gen_op_float_check_status();
79aceca5
FB		 2173}
2174
76a66253
JM		 2175/*** Addressing modes ***/
2176/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2177static always_inline void gen_addr_imm_index (TCGv EA,
2178 DisasContext *ctx,
b068d6a7 2179 target_long maskl)
76a66253
JM		 2180{
2181 target_long simm = SIMM(ctx->opcode);
2182
be147d08 2183 simm &= ~maskl;
e2be8d8d
AJ		 2184 if (rA(ctx->opcode) == 0)
2185 tcg_gen_movi_tl(EA, simm);
2186 else if (likely(simm != 0))
2187 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2188 else
2189 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2190}
2191
e2be8d8d
AJ		 2192static always_inline void gen_addr_reg_index (TCGv EA,
2193 DisasContext *ctx)
76a66253 2194{
e2be8d8d
AJ		 2195 if (rA(ctx->opcode) == 0)
2196 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2197 else
2198 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2199}
2200
e2be8d8d
AJ		 2201static always_inline void gen_addr_register (TCGv EA,
2202 DisasContext *ctx)
76a66253 2203{
e2be8d8d
AJ		 2204 if (rA(ctx->opcode) == 0)
2205 tcg_gen_movi_tl(EA, 0);
2206 else
2207 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2208}
2209
7863667f
JM		 2210#if defined(TARGET_PPC64)
2211#define _GEN_MEM_FUNCS(name, mode) \
2212 &gen_op_##name##_##mode, \
2213 &gen_op_##name##_le_##mode, \
2214 &gen_op_##name##_64_##mode, \
2215 &gen_op_##name##_le_64_##mode
2216#else
2217#define _GEN_MEM_FUNCS(name, mode) \
2218 &gen_op_##name##_##mode, \
2219 &gen_op_##name##_le_##mode
2220#endif
9a64fbe4 2221#if defined(CONFIG_USER_ONLY)
d9bce9d9 2222#if defined(TARGET_PPC64)
7863667f 2223#define NB_MEM_FUNCS 4
d9bce9d9 2224#else
7863667f 2225#define NB_MEM_FUNCS 2
d9bce9d9 2226#endif
7863667f
JM		 2227#define GEN_MEM_FUNCS(name) \
2228 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2229#else
d9bce9d9 2230#if defined(TARGET_PPC64)
7863667f 2231#define NB_MEM_FUNCS 12
2857068e 2232#else
7863667f 2233#define NB_MEM_FUNCS 6
2857068e 2234#endif
7863667f
JM		 2235#define GEN_MEM_FUNCS(name) \
2236 _GEN_MEM_FUNCS(name, user), \
2237 _GEN_MEM_FUNCS(name, kernel), \
2238 _GEN_MEM_FUNCS(name, hypv)
2239#endif
2240
2241/*** Integer load ***/
2242#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
d9bce9d9 2243#define OP_LD_TABLE(width) \
7863667f
JM		 2244static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2245 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2246};
2247#define OP_ST_TABLE(width) \
7863667f
JM		 2248static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2249 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2250};
9a64fbe4 2251
b61f2753
AJ		 2252
2253#if defined(TARGET_PPC64)
2254#define GEN_QEMU_LD_PPC64(width) \
2255static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2256{ \
2257 if (likely(flags & 2)) \
2258 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2259 else { \
2260 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2261 tcg_gen_ext32u_tl(addr, t1); \
2262 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2263 tcg_temp_free(addr); \
2264 } \
2265}
2266GEN_QEMU_LD_PPC64(8u)
2267GEN_QEMU_LD_PPC64(8s)
2268GEN_QEMU_LD_PPC64(16u)
2269GEN_QEMU_LD_PPC64(16s)
2270GEN_QEMU_LD_PPC64(32u)
2271GEN_QEMU_LD_PPC64(32s)
2272GEN_QEMU_LD_PPC64(64)
2273
2274#define GEN_QEMU_ST_PPC64(width) \
2275static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2276{ \
2277 if (likely(flags & 2)) \
2278 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2279 else { \
2280 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2281 tcg_gen_ext32u_tl(addr, t1); \
2282 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2283 tcg_temp_free(addr); \
2284 } \
2285}
2286GEN_QEMU_ST_PPC64(8)
2287GEN_QEMU_ST_PPC64(16)
2288GEN_QEMU_ST_PPC64(32)
2289GEN_QEMU_ST_PPC64(64)
2290
2291static always_inline void gen_qemu_ld8u(TCGv t0, TCGv t1, int flags)
2292{
2293 gen_qemu_ld8u_ppc64(t0, t1, flags);
2294}
2295
2296static always_inline void gen_qemu_ld8s(TCGv t0, TCGv t1, int flags)
2297{
2298 gen_qemu_ld8s_ppc64(t0, t1, flags);
2299}
2300
2301static always_inline void gen_qemu_ld16u(TCGv t0, TCGv t1, int flags)
2302{
2303 if (unlikely(flags & 1)) {
2304 TCGv t0_32;
2305 gen_qemu_ld16u_ppc64(t0, t1, flags);
2306 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2307 tcg_gen_trunc_tl_i32(t0_32, t0);
2308 tcg_gen_bswap16_i32(t0_32, t0_32);
2309 tcg_gen_extu_i32_tl(t0, t0_32);
2310 tcg_temp_free(t0_32);
2311 } else
2312 gen_qemu_ld16u_ppc64(t0, t1, flags);
2313}
2314
2315static always_inline void gen_qemu_ld16s(TCGv t0, TCGv t1, int flags)
2316{
2317 if (unlikely(flags & 1)) {
2318 TCGv t0_32;
2319 gen_qemu_ld16u_ppc64(t0, t1, flags);
2320 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2321 tcg_gen_trunc_tl_i32(t0_32, t0);
2322 tcg_gen_bswap16_i32(t0_32, t0_32);
2323 tcg_gen_extu_i32_tl(t0, t0_32);
2324 tcg_gen_ext16s_tl(t0, t0);
2325 tcg_temp_free(t0_32);
2326 } else
2327 gen_qemu_ld16s_ppc64(t0, t1, flags);
2328}
2329
2330static always_inline void gen_qemu_ld32u(TCGv t0, TCGv t1, int flags)
2331{
2332 if (unlikely(flags & 1)) {
2333 TCGv t0_32;
2334 gen_qemu_ld32u_ppc64(t0, t1, flags);
2335 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2336 tcg_gen_trunc_tl_i32(t0_32, t0);
2337 tcg_gen_bswap_i32(t0_32, t0_32);
2338 tcg_gen_extu_i32_tl(t0, t0_32);
2339 tcg_temp_free(t0_32);
2340 } else
2341 gen_qemu_ld32u_ppc64(t0, t1, flags);
2342}
2343
2344static always_inline void gen_qemu_ld32s(TCGv t0, TCGv t1, int flags)
2345{
2346 if (unlikely(flags & 1)) {
2347 TCGv t0_32;
2348 gen_qemu_ld32u_ppc64(t0, t1, flags);
2349 t0_32 = tcg_temp_new(TCG_TYPE_I32);
2350 tcg_gen_trunc_tl_i32(t0_32, t0);
2351 tcg_gen_bswap_i32(t0_32, t0_32);
2352 tcg_gen_ext_i32_tl(t0, t0_32);
2353 tcg_temp_free(t0_32);
2354 } else
2355 gen_qemu_ld32s_ppc64(t0, t1, flags);
2356}
2357
2358static always_inline void gen_qemu_ld64(TCGv t0, TCGv t1, int flags)
2359{
2360 gen_qemu_ld64_ppc64(t0, t1, flags);
2361 if (unlikely(flags & 1))
2362 tcg_gen_bswap_i64(t0, t0);
2363}
2364
2365static always_inline void gen_qemu_st8(TCGv t0, TCGv t1, int flags)
2366{
2367 gen_qemu_st8_ppc64(t0, t1, flags);
2368}
2369
2370static always_inline void gen_qemu_st16(TCGv t0, TCGv t1, int flags)
2371{
2372 if (unlikely(flags & 1)) {
2373 TCGv temp1, temp2;
2374 temp1 = tcg_temp_new(TCG_TYPE_I32);
2375 tcg_gen_trunc_tl_i32(temp1, t0);
2376 tcg_gen_ext16u_i32(temp1, temp1);
2377 tcg_gen_bswap16_i32(temp1, temp1);
2378 temp2 = tcg_temp_new(TCG_TYPE_I64);
2379 tcg_gen_extu_i32_tl(temp2, temp1);
2380 tcg_temp_free(temp1);
2381 gen_qemu_st16_ppc64(temp2, t1, flags);
2382 tcg_temp_free(temp2);
2383 } else
2384 gen_qemu_st16_ppc64(t0, t1, flags);
2385}
2386
2387static always_inline void gen_qemu_st32(TCGv t0, TCGv t1, int flags)
2388{
2389 if (unlikely(flags & 1)) {
2390 TCGv temp1, temp2;
2391 temp1 = tcg_temp_new(TCG_TYPE_I32);
2392 tcg_gen_trunc_tl_i32(temp1, t0);
2393 tcg_gen_bswap_i32(temp1, temp1);
2394 temp2 = tcg_temp_new(TCG_TYPE_I64);
2395 tcg_gen_extu_i32_tl(temp2, temp1);
2396 tcg_temp_free(temp1);
2397 gen_qemu_st32_ppc64(temp2, t1, flags);
2398 tcg_temp_free(temp2);
2399 } else
2400 gen_qemu_st32_ppc64(t0, t1, flags);
2401}
2402
2403static always_inline void gen_qemu_st64(TCGv t0, TCGv t1, int flags)
2404{
2405 if (unlikely(flags & 1)) {
2406 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2407 tcg_gen_bswap_i64(temp, t0);
2408 gen_qemu_st64_ppc64(temp, t1, flags);
2409 tcg_temp_free(temp);
2410 } else
2411 gen_qemu_st64_ppc64(t0, t1, flags);
2412}
2413
2414
2415#else /* defined(TARGET_PPC64) */
2416#define GEN_QEMU_LD_PPC32(width) \
2417static always_inline void gen_qemu_ld##width##_ppc32(TCGv t0, TCGv t1, int flags)\
2418{ \
2419 tcg_gen_qemu_ld##width(t0, t1, flags >> 1); \
2420}
2421GEN_QEMU_LD_PPC32(8u)
2422GEN_QEMU_LD_PPC32(8s)
2423GEN_QEMU_LD_PPC32(16u)
2424GEN_QEMU_LD_PPC32(16s)
2425GEN_QEMU_LD_PPC32(32u)
2426GEN_QEMU_LD_PPC32(32s)
2427GEN_QEMU_LD_PPC32(64)
2428
2429#define GEN_QEMU_ST_PPC32(width) \
2430static always_inline void gen_qemu_st##width##_ppc32(TCGv t0, TCGv t1, int flags)\
2431{ \
2432 tcg_gen_qemu_st##width(t0, t1, flags >> 1); \
2433}
2434GEN_QEMU_ST_PPC32(8)
2435GEN_QEMU_ST_PPC32(16)
2436GEN_QEMU_ST_PPC32(32)
2437GEN_QEMU_ST_PPC32(64)
2438
2439static always_inline void gen_qemu_ld8u(TCGv t0, TCGv t1, int flags)
2440{
2441 gen_qemu_ld8u_ppc32(t0, t1, flags >> 1);
2442}
2443
2444static always_inline void gen_qemu_ld8s(TCGv t0, TCGv t1, int flags)
2445{
2446 gen_qemu_ld8s_ppc32(t0, t1, flags >> 1);
2447}
2448
2449static always_inline void gen_qemu_ld16u(TCGv t0, TCGv t1, int flags)
2450{
2451 gen_qemu_ld16u_ppc32(t0, t1, flags >> 1);
2452 if (unlikely(flags & 1))
2453 tcg_gen_bswap16_i32(t0, t0);
2454}
2455
2456static always_inline void gen_qemu_ld16s(TCGv t0, TCGv t1, int flags)
2457{
2458 if (unlikely(flags & 1)) {
2459 gen_qemu_ld16u_ppc32(t0, t1, flags);
2460 tcg_gen_bswap16_i32(t0, t0);
2461 tcg_gen_ext16s_i32(t0, t0);
2462 } else
2463 gen_qemu_ld16s_ppc32(t0, t1, flags);
2464}
2465
2466static always_inline void gen_qemu_ld32u(TCGv t0, TCGv t1, int flags)
2467{
2468 gen_qemu_ld32u_ppc32(t0, t1, flags);
2469 if (unlikely(flags & 1))
2470 tcg_gen_bswap_i32(t0, t0);
2471}
2472
2473static always_inline void gen_qemu_ld64(TCGv t0, TCGv t1, int flags)
2474{
2475 gen_qemu_ld64_ppc32(t0, t1, flags);
2476 if (unlikely(flags & 1))
2477 tcg_gen_bswap_i64(t0, t0);
2478}
2479
2480static always_inline void gen_qemu_st8(TCGv t0, TCGv t1, int flags)
2481{
2482 gen_qemu_st8_ppc32(t0, t1, flags >> 1);
2483}
2484
2485static always_inline void gen_qemu_st16(TCGv t0, TCGv t1, int flags)
2486{
2487 if (unlikely(flags & 1)) {
2488 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2489 tcg_gen_ext16u_i32(temp, t0);
2490 tcg_gen_bswap16_i32(temp, temp);
2491 gen_qemu_st16_ppc32(temp, t1, flags >> 1);
2492 tcg_temp_free(temp);
2493 } else
2494 gen_qemu_st16_ppc32(t0, t1, flags >> 1);
2495}
2496
2497static always_inline void gen_qemu_st32(TCGv t0, TCGv t1, int flags)
2498{
2499 if (unlikely(flags & 1)) {
2500 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2501 tcg_gen_bswap_i32(temp, t0);
2502 gen_qemu_st32_ppc32(temp, t1, flags >> 1);
2503 tcg_temp_free(temp);
2504 } else
2505 gen_qemu_st32_ppc32(t0, t1, flags >> 1);
2506}
2507
2508static always_inline void gen_qemu_st64(TCGv t0, TCGv t1, int flags)
2509{
2510 if (unlikely(flags & 1)) {
2511 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
2512 tcg_gen_bswap_i64(temp, t0);
2513 gen_qemu_st64_ppc32(temp, t1, flags >> 1);
2514 tcg_temp_free(temp);
2515 } else
2516 gen_qemu_st64_ppc32(t0, t1, flags >> 1);
2517}
2518
2519#endif
2520
d9bce9d9
JM		 2521#define GEN_LD(width, opc, type) \
2522GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2523{ \
b61f2753
AJ		 2524 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2525 gen_addr_imm_index(EA, ctx, 0); \
2526 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2527 tcg_temp_free(EA); \
79aceca5
FB		 2528}
2529
d9bce9d9
JM		 2530#define GEN_LDU(width, opc, type) \
2531GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2532{ \
b61f2753 2533 TCGv EA; \
76a66253
JM		 2534 if (unlikely(rA(ctx->opcode) == 0 || \
2535 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2536 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2537 return; \
9a64fbe4 2538 } \
b61f2753 2539 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2540 if (type == PPC_64B) \
b61f2753 2541 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2542 else \
b61f2753
AJ		 2543 gen_addr_imm_index(EA, ctx, 0); \
2544 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2545 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2546 tcg_temp_free(EA); \
79aceca5
FB		 2547}
2548
d9bce9d9
JM		 2549#define GEN_LDUX(width, opc2, opc3, type) \
2550GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2551{ \
b61f2753 2552 TCGv EA; \
76a66253
JM		 2553 if (unlikely(rA(ctx->opcode) == 0 || \
2554 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2555 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2556 return; \
9a64fbe4 2557 } \
b61f2753
AJ		 2558 EA = tcg_temp_new(TCG_TYPE_TL); \
2559 gen_addr_reg_index(EA, ctx); \
2560 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2561 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2562 tcg_temp_free(EA); \
79aceca5
FB		 2563}
2564
d9bce9d9
JM		 2565#define GEN_LDX(width, opc2, opc3, type) \
2566GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2567{ \
b61f2753
AJ		 2568 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2569 gen_addr_reg_index(EA, ctx); \
2570 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2571 tcg_temp_free(EA); \
79aceca5
FB		 2572}
2573
d9bce9d9 2574#define GEN_LDS(width, op, type) \
d9bce9d9
JM		 2575GEN_LD(width, op | 0x20, type); \
2576GEN_LDU(width, op | 0x21, type); \
2577GEN_LDUX(width, 0x17, op | 0x01, type); \
2578GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2579
2580/* lbz lbzu lbzux lbzx */
b61f2753 2581GEN_LDS(8u, 0x02, PPC_INTEGER);
79aceca5 2582/* lha lhau lhaux lhax */
b61f2753 2583GEN_LDS(16s, 0x0A, PPC_INTEGER);
79aceca5 2584/* lhz lhzu lhzux lhzx */
b61f2753 2585GEN_LDS(16u, 0x08, PPC_INTEGER);
79aceca5 2586/* lwz lwzu lwzux lwzx */
b61f2753 2587GEN_LDS(32u, 0x00, PPC_INTEGER);
d9bce9d9 2588#if defined(TARGET_PPC64)
d9bce9d9 2589/* lwaux */
b61f2753 2590GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2591/* lwax */
b61f2753 2592GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2593/* ldux */
b61f2753 2594GEN_LDUX(64, 0x15, 0x01, PPC_64B);
d9bce9d9 2595/* ldx */
b61f2753 2596GEN_LDX(64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2597GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2598{
b61f2753 2599 TCGv EA;
d9bce9d9
JM		 2600 if (Rc(ctx->opcode)) {
2601 if (unlikely(rA(ctx->opcode) == 0 ||
2602 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2603 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2604 return;
2605 }
2606 }
b61f2753
AJ		 2607 EA = tcg_temp_new(TCG_TYPE_TL);
2608 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2609 if (ctx->opcode & 0x02) {
2610 /* lwa (lwau is undefined) */
b61f2753 2611 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2612 } else {
2613 /* ld - ldu */
b61f2753 2614 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2615 }
d9bce9d9 2616 if (Rc(ctx->opcode))
b61f2753
AJ		 2617 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2618 tcg_temp_free(EA);
d9bce9d9 2619}
be147d08
JM		 2620/* lq */
2621GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2622{
2623#if defined(CONFIG_USER_ONLY)
2624 GEN_EXCP_PRIVOPC(ctx);
2625#else
2626 int ra, rd;
b61f2753 2627 TCGv EA;
be147d08
JM		 2628
2629 /* Restore CPU state */
2630 if (unlikely(ctx->supervisor == 0)) {
2631 GEN_EXCP_PRIVOPC(ctx);
2632 return;
2633 }
2634 ra = rA(ctx->opcode);
2635 rd = rD(ctx->opcode);
2636 if (unlikely((rd & 1) || rd == ra)) {
2637 GEN_EXCP_INVAL(ctx);
2638 return;
2639 }
2640 if (unlikely(ctx->mem_idx & 1)) {
2641 /* Little-endian mode is not handled */
2642 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2643 return;
2644 }
b61f2753
AJ		 2645 EA = tcg_temp_new(TCG_TYPE_TL);
2646 gen_addr_imm_index(EA, ctx, 0x0F);
2647 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2648 tcg_gen_addi_tl(EA, EA, 8);
2649 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2650 tcg_temp_free(EA);
be147d08
JM		 2651#endif
2652}
d9bce9d9 2653#endif
79aceca5
FB		 2654
2655/*** Integer store ***/
d9bce9d9
JM		 2656#define GEN_ST(width, opc, type) \
2657GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2658{ \
b61f2753
AJ		 2659 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2660 gen_addr_imm_index(EA, ctx, 0); \
2661 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2662 tcg_temp_free(EA); \
79aceca5
FB		 2663}
2664
d9bce9d9
JM		 2665#define GEN_STU(width, opc, type) \
2666GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2667{ \
b61f2753 2668 TCGv EA; \
76a66253 2669 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2670 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2671 return; \
9a64fbe4 2672 } \
b61f2753 2673 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2674 if (type == PPC_64B) \
b61f2753 2675 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2676 else \
b61f2753
AJ		 2677 gen_addr_imm_index(EA, ctx, 0); \
2678 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2679 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2680 tcg_temp_free(EA); \
79aceca5
FB		 2681}
2682
d9bce9d9
JM		 2683#define GEN_STUX(width, opc2, opc3, type) \
2684GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2685{ \
b61f2753 2686 TCGv EA; \
76a66253 2687 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2688 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2689 return; \
9a64fbe4 2690 } \
b61f2753
AJ		 2691 EA = tcg_temp_new(TCG_TYPE_TL); \
2692 gen_addr_reg_index(EA, ctx); \
2693 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2694 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2695 tcg_temp_free(EA); \
79aceca5
FB		 2696}
2697
d9bce9d9
JM		 2698#define GEN_STX(width, opc2, opc3, type) \
2699GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2700{ \
b61f2753
AJ		 2701 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2702 gen_addr_reg_index(EA, ctx); \
2703 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2704 tcg_temp_free(EA); \
79aceca5
FB		 2705}
2706
d9bce9d9 2707#define GEN_STS(width, op, type) \
d9bce9d9
JM		 2708GEN_ST(width, op | 0x20, type); \
2709GEN_STU(width, op | 0x21, type); \
2710GEN_STUX(width, 0x17, op | 0x01, type); \
2711GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2712
2713/* stb stbu stbux stbx */
b61f2753 2714GEN_STS(8, 0x06, PPC_INTEGER);
79aceca5 2715/* sth sthu sthux sthx */
b61f2753 2716GEN_STS(16, 0x0C, PPC_INTEGER);
79aceca5 2717/* stw stwu stwux stwx */
b61f2753 2718GEN_STS(32, 0x04, PPC_INTEGER);
d9bce9d9 2719#if defined(TARGET_PPC64)
b61f2753
AJ		 2720GEN_STUX(64, 0x15, 0x05, PPC_64B);
2721GEN_STX(64, 0x15, 0x04, PPC_64B);
be147d08 2722GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 2723{
be147d08 2724 int rs;
b61f2753 2725 TCGv EA;
be147d08
JM		 2726
2727 rs = rS(ctx->opcode);
2728 if ((ctx->opcode & 0x3) == 0x2) {
2729#if defined(CONFIG_USER_ONLY)
2730 GEN_EXCP_PRIVOPC(ctx);
2731#else
2732 /* stq */
2733 if (unlikely(ctx->supervisor == 0)) {
2734 GEN_EXCP_PRIVOPC(ctx);
2735 return;
2736 }
2737 if (unlikely(rs & 1)) {
e1833e1f 2738 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2739 return;
2740 }
be147d08
JM		 2741 if (unlikely(ctx->mem_idx & 1)) {
2742 /* Little-endian mode is not handled */
2743 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2744 return;
2745 }
b61f2753
AJ		 2746 EA = tcg_temp_new(TCG_TYPE_TL);
2747 gen_addr_imm_index(EA, ctx, 0x03);
2748 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
2749 tcg_gen_addi_tl(EA, EA, 8);
2750 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
2751 tcg_temp_free(EA);
be147d08
JM		 2752#endif
2753 } else {
2754 /* std / stdu */
2755 if (Rc(ctx->opcode)) {
2756 if (unlikely(rA(ctx->opcode) == 0)) {
2757 GEN_EXCP_INVAL(ctx);
2758 return;
2759 }
2760 }
b61f2753
AJ		 2761 EA = tcg_temp_new(TCG_TYPE_TL);
2762 gen_addr_imm_index(EA, ctx, 0x03);
2763 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 2764 if (Rc(ctx->opcode))
b61f2753
AJ		 2765 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2766 tcg_temp_free(EA);
d9bce9d9 2767 }
d9bce9d9
JM		 2768}
2769#endif
79aceca5
FB		 2770/*** Integer load and store with byte reverse ***/
2771/* lhbrx */
b61f2753
AJ		 2772void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
2773{
2774 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2775 gen_qemu_ld16u(temp, t1, flags);
2776 tcg_gen_bswap16_i32(temp, temp);
2777 tcg_gen_extu_i32_tl(t0, temp);
2778 tcg_temp_free(temp);
2779}
2780GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
2781
79aceca5 2782/* lwbrx */
b61f2753
AJ		 2783void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
2784{
2785 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2786 gen_qemu_ld32u(temp, t1, flags);
2787 tcg_gen_bswap_i32(temp, temp);
2788 tcg_gen_extu_i32_tl(t0, temp);
2789 tcg_temp_free(temp);
2790}
2791GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
2792
79aceca5 2793/* sthbrx */
b61f2753
AJ		 2794void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
2795{
2796 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2797 tcg_gen_trunc_tl_i32(temp, t0);
2798 tcg_gen_ext16u_i32(temp, temp);
2799 tcg_gen_bswap16_i32(temp, temp);
2800 gen_qemu_st16(temp, t1, flags);
2801 tcg_temp_free(temp);
2802}
2803GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
2804
79aceca5 2805/* stwbrx */
b61f2753
AJ		 2806void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
2807{
2808 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
2809 tcg_gen_trunc_tl_i32(temp, t0);
2810 tcg_gen_bswap_i32(temp, temp);
2811 gen_qemu_st32(temp, t1, flags);
2812 tcg_temp_free(temp);
2813}
2814GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 2815
2816/*** Integer load and store multiple ***/
111bfab3 2817#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 2818static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
2819 GEN_MEM_FUNCS(lmw),
d9bce9d9 2820};
7863667f
JM		 2821static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
2822 GEN_MEM_FUNCS(stmw),
d9bce9d9 2823};
9a64fbe4 2824
79aceca5
FB		 2825/* lmw */
2826GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2827{
76a66253 2828 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2829 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2830 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2831 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 2832}
2833
2834/* stmw */
2835GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
2836{
76a66253 2837 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2838 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2839 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 2840 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 2841}
2842
2843/*** Integer load and store strings ***/
9a64fbe4
FB		 2844#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
2845#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 2846/* string load & stores are by definition endian-safe */
2847#define gen_op_lswi_le_raw gen_op_lswi_raw
2848#define gen_op_lswi_le_user gen_op_lswi_user
2849#define gen_op_lswi_le_kernel gen_op_lswi_kernel
2850#define gen_op_lswi_le_hypv gen_op_lswi_hypv
2851#define gen_op_lswi_le_64_raw gen_op_lswi_raw
2852#define gen_op_lswi_le_64_user gen_op_lswi_user
2853#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
2854#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 2855static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
2856 GEN_MEM_FUNCS(lswi),
d9bce9d9 2857};
e7c24003
JM		 2858#define gen_op_lswx_le_raw gen_op_lswx_raw
2859#define gen_op_lswx_le_user gen_op_lswx_user
2860#define gen_op_lswx_le_kernel gen_op_lswx_kernel
2861#define gen_op_lswx_le_hypv gen_op_lswx_hypv
2862#define gen_op_lswx_le_64_raw gen_op_lswx_raw
2863#define gen_op_lswx_le_64_user gen_op_lswx_user
2864#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
2865#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 2866static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
2867 GEN_MEM_FUNCS(lswx),
d9bce9d9 2868};
e7c24003
JM		 2869#define gen_op_stsw_le_raw gen_op_stsw_raw
2870#define gen_op_stsw_le_user gen_op_stsw_user
2871#define gen_op_stsw_le_kernel gen_op_stsw_kernel
2872#define gen_op_stsw_le_hypv gen_op_stsw_hypv
2873#define gen_op_stsw_le_64_raw gen_op_stsw_raw
2874#define gen_op_stsw_le_64_user gen_op_stsw_user
2875#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
2876#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 2877static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
2878 GEN_MEM_FUNCS(stsw),
9a64fbe4 2879};
9a64fbe4 2880
79aceca5 2881/* lswi */
3fc6c082 2882/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 2883 * rA is in the range of registers to be loaded.
2884 * In an other hand, IBM says this is valid, but rA won't be loaded.
2885 * For now, I'll follow the spec...
2886 */
05332d70 2887GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 2888{
2889 int nb = NB(ctx->opcode);
2890 int start = rD(ctx->opcode);
9a64fbe4 2891 int ra = rA(ctx->opcode);
79aceca5
FB		 2892 int nr;
2893
2894 if (nb == 0)
2895 nb = 32;
2896 nr = nb / 4;
76a66253
JM		 2897 if (unlikely(((start + nr) > 32 &&
2898 start <= ra && (start + nr - 32) > ra) ||
2899 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 2900 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
2901 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 2902 return;
297d8e62 2903 }
8dd4983c 2904 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2905 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2906 gen_addr_register(cpu_T[0], ctx);
86c581dc 2907 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 2908 op_ldsts(lswi, start);
79aceca5
FB		 2909}
2910
2911/* lswx */
05332d70 2912GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 2913{
9a64fbe4
FB		 2914 int ra = rA(ctx->opcode);
2915 int rb = rB(ctx->opcode);
2916
76a66253 2917 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2918 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2919 gen_addr_reg_index(cpu_T[0], ctx);
9a64fbe4 2920 if (ra == 0) {
9a64fbe4 2921 ra = rb;
79aceca5 2922 }
3d7b417e 2923 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 2924 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 2925}
2926
2927/* stswi */
05332d70 2928GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 2929{
4b3686fa
FB		 2930 int nb = NB(ctx->opcode);
2931
76a66253 2932 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 2933 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2934 gen_addr_register(cpu_T[0], ctx);
4b3686fa
FB		 2935 if (nb == 0)
2936 nb = 32;
86c581dc 2937 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 2938 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2939}
2940
2941/* stswx */
05332d70 2942GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 2943{
8dd4983c 2944 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 2945 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2946 gen_addr_reg_index(cpu_T[0], ctx);
3d7b417e 2947 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 2948 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 2949}
2950
2951/*** Memory synchronisation ***/
2952/* eieio */
0db1b20e 2953GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 2954{
79aceca5
FB		 2955}
2956
2957/* isync */
0db1b20e 2958GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 2959{
e1833e1f 2960 GEN_STOP(ctx);
79aceca5
FB		 2961}
2962
111bfab3
FB		 2963#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
2964#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 2965static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
2966 GEN_MEM_FUNCS(lwarx),
111bfab3 2967};
7863667f
JM		 2968static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
2969 GEN_MEM_FUNCS(stwcx),
985a19d6 2970};
9a64fbe4 2971
111bfab3 2972/* lwarx */
76a66253 2973GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 2974{
30032c94
JM		 2975 /* NIP cannot be restored if the memory exception comes from an helper */
2976 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2977 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 2978 op_lwarx();
f78fb44e 2979 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 2980}
2981
2982/* stwcx. */
c7697e1f 2983GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 2984{
30032c94
JM		 2985 /* NIP cannot be restored if the memory exception comes from an helper */
2986 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 2987 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 2988 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 2989 op_stwcx();
79aceca5
FB		 2990}
2991
426613db
JM		 2992#if defined(TARGET_PPC64)
2993#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
2994#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 2995static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
2996 GEN_MEM_FUNCS(ldarx),
426613db 2997};
7863667f
JM		 2998static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
2999 GEN_MEM_FUNCS(stdcx),
426613db 3000};
426613db
JM		 3001
3002/* ldarx */
a750fc0b 3003GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3004{
30032c94
JM		 3005 /* NIP cannot be restored if the memory exception comes from an helper */
3006 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3007 gen_addr_reg_index(cpu_T[0], ctx);
426613db 3008 op_ldarx();
f78fb44e 3009 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 3010}
3011
3012/* stdcx. */
c7697e1f 3013GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3014{
30032c94
JM		 3015 /* NIP cannot be restored if the memory exception comes from an helper */
3016 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3017 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3018 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 3019 op_stdcx();
3020}
3021#endif /* defined(TARGET_PPC64) */
3022
79aceca5 3023/* sync */
a902d886 3024GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3025{
79aceca5
FB		 3026}
3027
0db1b20e
JM		 3028/* wait */
3029GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3030{
3031 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 3032 gen_op_wait();
3033 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3034}
3035
79aceca5 3036/*** Floating-point load ***/
477023a6
JM		 3037#define GEN_LDF(width, opc, type) \
3038GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3039{ \
76a66253 3040 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3041 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3042 return; \
3043 } \
e2be8d8d 3044 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3045 op_ldst(l##width); \
a5e26afa 3046 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3047}
3048
477023a6
JM		 3049#define GEN_LDUF(width, opc, type) \
3050GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3051{ \
76a66253 3052 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3053 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3054 return; \
3055 } \
76a66253 3056 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3057 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3058 return; \
9a64fbe4 3059 } \
e2be8d8d 3060 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3061 op_ldst(l##width); \
a5e26afa 3062 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3063 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3064}
3065
477023a6
JM		 3066#define GEN_LDUXF(width, opc, type) \
3067GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3068{ \
76a66253 3069 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3070 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3071 return; \
3072 } \
76a66253 3073 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3074 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3075 return; \
9a64fbe4 3076 } \
e2be8d8d 3077 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3078 op_ldst(l##width); \
a5e26afa 3079 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3080 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3081}
3082
477023a6
JM		 3083#define GEN_LDXF(width, opc2, opc3, type) \
3084GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3085{ \
76a66253 3086 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3087 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3088 return; \
3089 } \
e2be8d8d 3090 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3091 op_ldst(l##width); \
a5e26afa 3092 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3093}
3094
477023a6 3095#define GEN_LDFS(width, op, type) \
9a64fbe4 3096OP_LD_TABLE(width); \
477023a6
JM		 3097GEN_LDF(width, op | 0x20, type); \
3098GEN_LDUF(width, op | 0x21, type); \
3099GEN_LDUXF(width, op | 0x01, type); \
3100GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3101
3102/* lfd lfdu lfdux lfdx */
477023a6 3103GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 3104/* lfs lfsu lfsux lfsx */
477023a6 3105GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3106
3107/*** Floating-point store ***/
477023a6
JM		 3108#define GEN_STF(width, opc, type) \
3109GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3110{ \
76a66253 3111 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3112 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3113 return; \
3114 } \
e2be8d8d 3115 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3116 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3117 op_ldst(st##width); \
79aceca5
FB		 3118}
3119
477023a6
JM		 3120#define GEN_STUF(width, opc, type) \
3121GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3122{ \
76a66253 3123 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3124 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3125 return; \
3126 } \
76a66253 3127 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3128 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3129 return; \
9a64fbe4 3130 } \
e2be8d8d 3131 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3132 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3133 op_ldst(st##width); \
f78fb44e 3134 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3135}
3136
477023a6
JM		 3137#define GEN_STUXF(width, opc, type) \
3138GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3139{ \
76a66253 3140 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3141 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3142 return; \
3143 } \
76a66253 3144 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3145 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3146 return; \
9a64fbe4 3147 } \
e2be8d8d 3148 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3149 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3150 op_ldst(st##width); \
f78fb44e 3151 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3152}
3153
477023a6
JM		 3154#define GEN_STXF(width, opc2, opc3, type) \
3155GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3156{ \
76a66253 3157 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3158 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3159 return; \
3160 } \
e2be8d8d 3161 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3162 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3163 op_ldst(st##width); \
79aceca5
FB		 3164}
3165
477023a6 3166#define GEN_STFS(width, op, type) \
9a64fbe4 3167OP_ST_TABLE(width); \
477023a6
JM		 3168GEN_STF(width, op | 0x20, type); \
3169GEN_STUF(width, op | 0x21, type); \
3170GEN_STUXF(width, op | 0x01, type); \
3171GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3172
3173/* stfd stfdu stfdux stfdx */
477023a6 3174GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 3175/* stfs stfsu stfsux stfsx */
477023a6 3176GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3177
3178/* Optional: */
3179/* stfiwx */
5b8105fa
JM		 3180OP_ST_TABLE(fiw);
3181GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3182
3183/*** Branch ***/
b068d6a7
JM		 3184static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3185 target_ulong dest)
c1942362
FB		 3186{
3187 TranslationBlock *tb;
3188 tb = ctx->tb;
57fec1fe 3189 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3190 likely(!ctx->singlestep_enabled)) {
57fec1fe 3191 tcg_gen_goto_tb(n);
02f4f6c2 3192 tcg_gen_movi_tl(cpu_T[1], dest);
d9bce9d9
JM		 3193#if defined(TARGET_PPC64)
3194 if (ctx->sf_mode)
bd568f18 3195 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 3196 else
3197#endif
bd568f18 3198 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
57fec1fe 3199 tcg_gen_exit_tb((long)tb + n);
c1942362 3200 } else {
02f4f6c2 3201 tcg_gen_movi_tl(cpu_T[1], dest);
d9bce9d9
JM		 3202#if defined(TARGET_PPC64)
3203 if (ctx->sf_mode)
bd568f18 3204 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 3205 else
3206#endif
bd568f18 3207 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
8cbcb4fa
AJ		 3208 if (unlikely(ctx->singlestep_enabled)) {
3209 if ((ctx->singlestep_enabled &
3210 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3211 ctx->exception == POWERPC_EXCP_BRANCH) {
3212 target_ulong tmp = ctx->nip;
3213 ctx->nip = dest;
3214 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3215 ctx->nip = tmp;
3216 }
3217 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3218 gen_update_nip(ctx, dest);
3219 gen_op_debug();
3220 }
3221 }
57fec1fe 3222 tcg_gen_exit_tb(0);
c1942362 3223 }
c53be334
FB		 3224}
3225
b068d6a7 3226static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3227{
3228#if defined(TARGET_PPC64)
3229 if (ctx->sf_mode != 0 && (nip >> 32))
3230 gen_op_setlr_64(ctx->nip >> 32, ctx->nip);
3231 else
3232#endif
3233 gen_op_setlr(ctx->nip);
3234}
3235
79aceca5
FB		 3236/* b ba bl bla */
3237GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3238{
76a66253 3239 target_ulong li, target;
38a64f9d 3240
8cbcb4fa 3241 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3242 /* sign extend LI */
76a66253 3243#if defined(TARGET_PPC64)
d9bce9d9
JM		 3244 if (ctx->sf_mode)
3245 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3246 else
76a66253 3247#endif
d9bce9d9 3248 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3249 if (likely(AA(ctx->opcode) == 0))
046d6672 3250 target = ctx->nip + li - 4;
79aceca5 3251 else
9a64fbe4 3252 target = li;
d9bce9d9 3253#if defined(TARGET_PPC64)
e1833e1f
JM		 3254 if (!ctx->sf_mode)
3255 target = (uint32_t)target;
d9bce9d9 3256#endif
e1833e1f
JM		 3257 if (LK(ctx->opcode))
3258 gen_setlr(ctx, ctx->nip);
c1942362 3259 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3260}
3261
e98a6e40
FB		 3262#define BCOND_IM 0
3263#define BCOND_LR 1
3264#define BCOND_CTR 2
3265
b068d6a7 3266static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3267{
76a66253
JM		 3268 target_ulong target = 0;
3269 target_ulong li;
d9bce9d9
JM		 3270 uint32_t bo = BO(ctx->opcode);
3271 uint32_t bi = BI(ctx->opcode);
3272 uint32_t mask;
e98a6e40 3273
8cbcb4fa 3274 ctx->exception = POWERPC_EXCP_BRANCH;
e98a6e40 3275 if ((bo & 0x4) == 0)
d9bce9d9 3276 gen_op_dec_ctr();
e98a6e40
FB		 3277 switch(type) {
3278 case BCOND_IM:
76a66253
JM		 3279 li = (target_long)((int16_t)(BD(ctx->opcode)));
3280 if (likely(AA(ctx->opcode) == 0)) {
046d6672 3281 target = ctx->nip + li - 4;
e98a6e40
FB		 3282 } else {
3283 target = li;
3284 }
e1833e1f
JM		 3285#if defined(TARGET_PPC64)
3286 if (!ctx->sf_mode)
3287 target = (uint32_t)target;
3288#endif
e98a6e40
FB		 3289 break;
3290 case BCOND_CTR:
3291 gen_op_movl_T1_ctr();
3292 break;
3293 default:
3294 case BCOND_LR:
3295 gen_op_movl_T1_lr();
3296 break;
3297 }
e1833e1f
JM		 3298 if (LK(ctx->opcode))
3299 gen_setlr(ctx, ctx->nip);
e98a6e40 3300 if (bo & 0x10) {
d9bce9d9
JM		 3301 /* No CR condition */
3302 switch (bo & 0x6) {
3303 case 0:
3304#if defined(TARGET_PPC64)
3305 if (ctx->sf_mode)
3306 gen_op_test_ctr_64();
3307 else
3308#endif
3309 gen_op_test_ctr();
3310 break;
3311 case 2:
3312#if defined(TARGET_PPC64)
3313 if (ctx->sf_mode)
3314 gen_op_test_ctrz_64();
3315 else
3316#endif
3317 gen_op_test_ctrz();
e98a6e40 3318 break;
e98a6e40 3319 default:
d9bce9d9
JM		 3320 case 4:
3321 case 6:
e98a6e40 3322 if (type == BCOND_IM) {
c1942362 3323 gen_goto_tb(ctx, 0, target);
8cbcb4fa 3324 return;
e98a6e40 3325 } else {
d9bce9d9
JM		 3326#if defined(TARGET_PPC64)
3327 if (ctx->sf_mode)
bd568f18 3328 tcg_gen_andi_tl(cpu_nip, cpu_T[1], ~3);
d9bce9d9
JM		 3329 else
3330#endif
bd568f18 3331 tcg_gen_andi_tl(cpu_nip, cpu_T[1], (uint32_t)~3);
056b05f8 3332 goto no_test;
e98a6e40 3333 }
056b05f8 3334 break;
e98a6e40 3335 }
d9bce9d9
JM		 3336 } else {
3337 mask = 1 << (3 - (bi & 0x03));
47e4661c 3338 tcg_gen_mov_i32(cpu_T[0], cpu_crf[bi >> 2]);
d9bce9d9
JM		 3339 if (bo & 0x8) {
3340 switch (bo & 0x6) {
3341 case 0:
3342#if defined(TARGET_PPC64)
3343 if (ctx->sf_mode)
3344 gen_op_test_ctr_true_64(mask);
3345 else
3346#endif
3347 gen_op_test_ctr_true(mask);
3348 break;
3349 case 2:
3350#if defined(TARGET_PPC64)
3351 if (ctx->sf_mode)
3352 gen_op_test_ctrz_true_64(mask);
3353 else
3354#endif
3355 gen_op_test_ctrz_true(mask);
3356 break;
3357 default:
3358 case 4:
3359 case 6:
e98a6e40 3360 gen_op_test_true(mask);
d9bce9d9
JM		 3361 break;
3362 }
3363 } else {
3364 switch (bo & 0x6) {
3365 case 0:
3366#if defined(TARGET_PPC64)
3367 if (ctx->sf_mode)
3368 gen_op_test_ctr_false_64(mask);
3369 else
3370#endif
3371 gen_op_test_ctr_false(mask);
3b46e624 3372 break;
d9bce9d9
JM		 3373 case 2:
3374#if defined(TARGET_PPC64)
3375 if (ctx->sf_mode)
3376 gen_op_test_ctrz_false_64(mask);
3377 else
3378#endif
3379 gen_op_test_ctrz_false(mask);
3380 break;
e98a6e40 3381 default:
d9bce9d9
JM		 3382 case 4:
3383 case 6:
e98a6e40 3384 gen_op_test_false(mask);
d9bce9d9
JM		 3385 break;
3386 }
3387 }
3388 }
e98a6e40 3389 if (type == BCOND_IM) {
c53be334
FB		 3390 int l1 = gen_new_label();
3391 gen_op_jz_T0(l1);
c1942362 3392 gen_goto_tb(ctx, 0, target);
c53be334 3393 gen_set_label(l1);
c1942362 3394 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3395 } else {
d9bce9d9
JM		 3396#if defined(TARGET_PPC64)
3397 if (ctx->sf_mode)
3398 gen_op_btest_T1_64(ctx->nip >> 32, ctx->nip);
3399 else
3400#endif
3401 gen_op_btest_T1(ctx->nip);
36081602 3402 no_test:
57fec1fe 3403 tcg_gen_exit_tb(0);
08e46e54 3404 }
e98a6e40
FB		 3405}
3406
3407GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3408{
e98a6e40
FB		 3409 gen_bcond(ctx, BCOND_IM);
3410}
3411
3412GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3413{
e98a6e40
FB		 3414 gen_bcond(ctx, BCOND_CTR);
3415}
3416
3417GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3418{
e98a6e40
FB		 3419 gen_bcond(ctx, BCOND_LR);
3420}
79aceca5
FB		 3421
3422/*** Condition register logical ***/
e1571908
AJ		 3423#define GEN_CRLOGIC(name, tcg_op, opc) \
3424GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3425{ \
fc0d441e
JM		 3426 uint8_t bitmask; \
3427 int sh; \
e1571908 3428 TCGv temp1, temp2; \
fc0d441e 3429 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
e1571908 3430 temp1 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e 3431 if (sh > 0) \
e1571908 3432 tcg_gen_shri_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3433 else if (sh < 0) \
e1571908
AJ		 3434 tcg_gen_shli_i32(temp1, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3435 else \
3436 tcg_gen_mov_i32(temp1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3437 temp2 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e
JM		 3438 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3439 if (sh > 0) \
e1571908 3440 tcg_gen_shri_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3441 else if (sh < 0) \
e1571908
AJ		 3442 tcg_gen_shli_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3443 else \
3444 tcg_gen_mov_i32(temp2, cpu_crf[crbB(ctx->opcode) >> 2]); \
3445 tcg_op(temp1, temp1, temp2); \
fc0d441e 3446 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
e1571908
AJ		 3447 tcg_gen_andi_i32(temp1, temp1, bitmask); \
3448 tcg_gen_andi_i32(temp2, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3449 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], temp1, temp2); \
3450 tcg_temp_free(temp1); \
3451 tcg_temp_free(temp2); \
79aceca5
FB		 3452}
3453
3454/* crand */
e1571908 3455GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3456/* crandc */
e1571908 3457GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3458/* creqv */
e1571908 3459GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3460/* crnand */
e1571908 3461GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3462/* crnor */
e1571908 3463GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3464/* cror */
e1571908 3465GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3466/* crorc */
e1571908 3467GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3468/* crxor */
e1571908 3469GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3470/* mcrf */
3471GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3472{
47e4661c 3473 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3474}
3475
3476/*** System linkage ***/
3477/* rfi (supervisor only) */
76a66253 3478GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3479{
9a64fbe4 3480#if defined(CONFIG_USER_ONLY)
e1833e1f 3481 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3482#else
3483 /* Restore CPU state */
76a66253 3484 if (unlikely(!ctx->supervisor)) {
e1833e1f 3485 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3486 return;
9a64fbe4 3487 }
a42bd6cc 3488 gen_op_rfi();
e1833e1f 3489 GEN_SYNC(ctx);
9a64fbe4 3490#endif
79aceca5
FB		 3491}
3492
426613db 3493#if defined(TARGET_PPC64)
a750fc0b 3494GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3495{
3496#if defined(CONFIG_USER_ONLY)
e1833e1f 3497 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3498#else
3499 /* Restore CPU state */
3500 if (unlikely(!ctx->supervisor)) {
e1833e1f 3501 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3502 return;
3503 }
a42bd6cc 3504 gen_op_rfid();
e1833e1f 3505 GEN_SYNC(ctx);
426613db
JM		 3506#endif
3507}
426613db 3508
5b8105fa 3509GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3510{
3511#if defined(CONFIG_USER_ONLY)
3512 GEN_EXCP_PRIVOPC(ctx);
3513#else
3514 /* Restore CPU state */
3515 if (unlikely(ctx->supervisor <= 1)) {
3516 GEN_EXCP_PRIVOPC(ctx);
3517 return;
3518 }
3519 gen_op_hrfid();
3520 GEN_SYNC(ctx);
3521#endif
3522}
3523#endif
3524
79aceca5 3525/* sc */
417bf010
JM		 3526#if defined(CONFIG_USER_ONLY)
3527#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3528#else
3529#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3530#endif
e1833e1f 3531GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3532{
e1833e1f
JM		 3533 uint32_t lev;
3534
3535 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3536 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3537}
3538
3539/*** Trap ***/
3540/* tw */
76a66253 3541GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3542{
f78fb44e
AJ		 3543 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3544 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
a0ae05aa 3545 /* Update the nip since this might generate a trap exception */
d9bce9d9 3546 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3547 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3548}
3549
3550/* twi */
3551GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3552{
f78fb44e 3553 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3554 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3555 /* Update the nip since this might generate a trap exception */
3556 gen_update_nip(ctx, ctx->nip);
76a66253 3557 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3558}
3559
d9bce9d9
JM		 3560#if defined(TARGET_PPC64)
3561/* td */
3562GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3563{
f78fb44e
AJ		 3564 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3565 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3566 /* Update the nip since this might generate a trap exception */
3567 gen_update_nip(ctx, ctx->nip);
3568 gen_op_td(TO(ctx->opcode));
3569}
3570
3571/* tdi */
3572GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3573{
f78fb44e 3574 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3575 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3576 /* Update the nip since this might generate a trap exception */
3577 gen_update_nip(ctx, ctx->nip);
3578 gen_op_td(TO(ctx->opcode));
3579}
3580#endif
3581
79aceca5 3582/*** Processor control ***/
79aceca5
FB		 3583/* mcrxr */
3584GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3585{
3d7b417e
AJ		 3586 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3587 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
3588 tcg_gen_andi_i32(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3589}
3590
3591/* mfcr */
76a66253 3592GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3593{
76a66253 3594 uint32_t crm, crn;
3b46e624 3595
76a66253
JM		 3596 if (likely(ctx->opcode & 0x00100000)) {
3597 crm = CRM(ctx->opcode);
3598 if (likely((crm ^ (crm - 1)) == 0)) {
3599 crn = ffs(crm);
e1571908 3600 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3601 }
d9bce9d9 3602 } else {
e1571908 3603 tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3604 }
79aceca5
FB		 3605}
3606
3607/* mfmsr */
3608GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3609{
9a64fbe4 3610#if defined(CONFIG_USER_ONLY)
e1833e1f 3611 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3612#else
76a66253 3613 if (unlikely(!ctx->supervisor)) {
e1833e1f 3614 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3615 return;
9a64fbe4 3616 }
6676f424 3617 gen_op_load_msr();
f78fb44e 3618 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3619#endif
79aceca5
FB		 3620}
3621
a11b8151 3622#if 1
6f2d8978 3623#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3624#else
3625static void spr_noaccess (void *opaque, int sprn)
3626{
3627 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3628 printf("ERROR: try to access SPR %d !\n", sprn);
3629}
3630#define SPR_NOACCESS (&spr_noaccess)
3631#endif
3632
79aceca5 3633/* mfspr */
b068d6a7 3634static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3635{
3fc6c082 3636 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3637 uint32_t sprn = SPR(ctx->opcode);
3638
3fc6c082 3639#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3640 if (ctx->supervisor == 2)
3641 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3642 else if (ctx->supervisor)
3fc6c082
FB		 3643 read_cb = ctx->spr_cb[sprn].oea_read;
3644 else
9a64fbe4 3645#endif
3fc6c082 3646 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3647 if (likely(read_cb != NULL)) {
3648 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3649 (*read_cb)(ctx, sprn);
f78fb44e 3650 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3651 } else {
3652 /* Privilege exception */
9fceefa7
JM		 3653 /* This is a hack to avoid warnings when running Linux:
3654 * this OS breaks the PowerPC virtualisation model,
3655 * allowing userland application to read the PVR
3656 */
3657 if (sprn != SPR_PVR) {
3658 if (loglevel != 0) {
6b542af7 3659 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3660 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3661 }
077fc206
JM		 3662 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3663 sprn, sprn, ctx->nip);
f24e5695 3664 }
e1833e1f 3665 GEN_EXCP_PRIVREG(ctx);
79aceca5 3666 }
3fc6c082
FB		 3667 } else {
3668 /* Not defined */
4a057712 3669 if (loglevel != 0) {
077fc206
JM		 3670 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3671 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3672 }
077fc206
JM		 3673 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3674 sprn, sprn, ctx->nip);
e1833e1f
JM		 3675 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3676 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3677 }
79aceca5
FB		 3678}
3679
3fc6c082 3680GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3681{
3fc6c082 3682 gen_op_mfspr(ctx);
76a66253 3683}
3fc6c082
FB		 3684
3685/* mftb */
a750fc0b 3686GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3687{
3688 gen_op_mfspr(ctx);
79aceca5
FB		 3689}
3690
3691/* mtcrf */
8dd4983c 3692GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3693{
76a66253 3694 uint32_t crm, crn;
3b46e624 3695
76a66253
JM		 3696 crm = CRM(ctx->opcode);
3697 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3698 crn = ffs(crm);
e1571908
AJ		 3699 tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3700 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
76a66253 3701 } else {
e1571908
AJ		 3702 TCGv temp = tcg_const_tl(crm);
3703 tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], temp);
3704 tcg_temp_free(temp);
76a66253 3705 }
79aceca5
FB		 3706}
3707
3708/* mtmsr */
426613db 3709#if defined(TARGET_PPC64)
be147d08 3710GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3711{
3712#if defined(CONFIG_USER_ONLY)
e1833e1f 3713 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3714#else
3715 if (unlikely(!ctx->supervisor)) {
e1833e1f 3716 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3717 return;
3718 }
f78fb44e 3719 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3720 if (ctx->opcode & 0x00010000) {
3721 /* Special form that does not need any synchronisation */
3722 gen_op_update_riee();
3723 } else {
056b05f8
JM		 3724 /* XXX: we need to update nip before the store
3725 * if we enter power saving mode, we will exit the loop
3726 * directly from ppc_store_msr
3727 */
be147d08 3728 gen_update_nip(ctx, ctx->nip);
6676f424 3729 gen_op_store_msr();
be147d08
JM		 3730 /* Must stop the translation as machine state (may have) changed */
3731 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3732 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3733 }
426613db
JM		 3734#endif
3735}
3736#endif
3737
79aceca5
FB		 3738GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3739{
9a64fbe4 3740#if defined(CONFIG_USER_ONLY)
e1833e1f 3741 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3742#else
76a66253 3743 if (unlikely(!ctx->supervisor)) {
e1833e1f 3744 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3745 return;
9a64fbe4 3746 }
f78fb44e 3747 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3748 if (ctx->opcode & 0x00010000) {
3749 /* Special form that does not need any synchronisation */
3750 gen_op_update_riee();
3751 } else {
056b05f8
JM		 3752 /* XXX: we need to update nip before the store
3753 * if we enter power saving mode, we will exit the loop
3754 * directly from ppc_store_msr
3755 */
be147d08 3756 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3757#if defined(TARGET_PPC64)
be147d08 3758 if (!ctx->sf_mode)
6676f424 3759 gen_op_store_msr_32();
be147d08 3760 else
d9bce9d9 3761#endif
6676f424 3762 gen_op_store_msr();
be147d08
JM		 3763 /* Must stop the translation as machine state (may have) changed */
3764 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3765 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3766 }
9a64fbe4 3767#endif
79aceca5
FB		 3768}
3769
3770/* mtspr */
3771GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3772{
3fc6c082 3773 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 3774 uint32_t sprn = SPR(ctx->opcode);
3775
3fc6c082 3776#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3777 if (ctx->supervisor == 2)
3778 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 3779 else if (ctx->supervisor)
3fc6c082
FB		 3780 write_cb = ctx->spr_cb[sprn].oea_write;
3781 else
9a64fbe4 3782#endif
3fc6c082 3783 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 3784 if (likely(write_cb != NULL)) {
3785 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 3786 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 3787 (*write_cb)(ctx, sprn);
3788 } else {
3789 /* Privilege exception */
4a057712 3790 if (loglevel != 0) {
077fc206
JM		 3791 fprintf(logfile, "Trying to write privileged spr %d %03x at "
3792 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3793 }
077fc206
JM		 3794 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
3795 sprn, sprn, ctx->nip);
e1833e1f 3796 GEN_EXCP_PRIVREG(ctx);
76a66253 3797 }
3fc6c082
FB		 3798 } else {
3799 /* Not defined */
4a057712 3800 if (loglevel != 0) {
077fc206
JM		 3801 fprintf(logfile, "Trying to write invalid spr %d %03x at "
3802 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3803 }
077fc206
JM		 3804 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
3805 sprn, sprn, ctx->nip);
e1833e1f
JM		 3806 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3807 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3808 }
79aceca5
FB		 3809}
3810
3811/*** Cache management ***/
79aceca5 3812/* dcbf */
0db1b20e 3813GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 3814{
dac454af 3815 /* XXX: specification says this is treated as a load by the MMU */
b61f2753
AJ		 3816 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3817 gen_addr_reg_index(temp, ctx);
3818 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3819 tcg_temp_free(temp);
79aceca5
FB		 3820}
3821
3822/* dcbi (Supervisor only) */
9a64fbe4 3823GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 3824{
a541f297 3825#if defined(CONFIG_USER_ONLY)
e1833e1f 3826 GEN_EXCP_PRIVOPC(ctx);
a541f297 3827#else
b61f2753 3828 TCGv EA, val;
76a66253 3829 if (unlikely(!ctx->supervisor)) {
e1833e1f 3830 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3831 return;
9a64fbe4 3832 }
b61f2753
AJ		 3833 EA = tcg_temp_new(TCG_TYPE_TL);
3834 gen_addr_reg_index(EA, ctx);
ed69522c 3835 val = tcg_temp_new(TCG_TYPE_TL);
76a66253 3836 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 3837 gen_qemu_ld8u(val, EA, ctx->mem_idx);
3838 gen_qemu_st8(val, EA, ctx->mem_idx);
3839 tcg_temp_free(val);
3840 tcg_temp_free(EA);
a541f297 3841#endif
79aceca5
FB		 3842}
3843
3844/* dcdst */
9a64fbe4 3845GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 3846{
76a66253 3847 /* XXX: specification say this is treated as a load by the MMU */
b61f2753
AJ		 3848 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3849 gen_addr_reg_index(temp, ctx);
3850 gen_qemu_ld8u(temp, temp, ctx->mem_idx);
3851 tcg_temp_free(temp);
79aceca5
FB		 3852}
3853
3854/* dcbt */
0db1b20e 3855GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 3856{
0db1b20e 3857 /* interpreted as no-op */
76a66253
JM		 3858 /* XXX: specification say this is treated as a load by the MMU
3859 * but does not generate any exception
3860 */
79aceca5
FB		 3861}
3862
3863/* dcbtst */
0db1b20e 3864GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 3865{
0db1b20e 3866 /* interpreted as no-op */
76a66253
JM		 3867 /* XXX: specification say this is treated as a load by the MMU
3868 * but does not generate any exception
3869 */
79aceca5
FB		 3870}
3871
3872/* dcbz */
d63001d1 3873#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 3874static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
3875 /* 32 bytes cache line size */
d63001d1 3876 {
7863667f
JM		 3877#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
3878#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
3879#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
3880#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
3881#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
3882#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
3883#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
3884#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
3885 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 3886 },
7863667f 3887 /* 64 bytes cache line size */
d63001d1 3888 {
7863667f
JM		 3889#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
3890#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
3891#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
3892#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
3893#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
3894#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
3895#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
3896#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
3897 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 3898 },
7863667f 3899 /* 128 bytes cache line size */
d63001d1 3900 {
7863667f
JM		 3901#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
3902#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
3903#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
3904#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
3905#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
3906#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
3907#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
3908#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
3909 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 3910 },
7863667f 3911 /* tunable cache line size */
d63001d1 3912 {
7863667f
JM		 3913#define gen_op_dcbz_le_raw gen_op_dcbz_raw
3914#define gen_op_dcbz_le_user gen_op_dcbz_user
3915#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
3916#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
3917#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
3918#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
3919#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
3920#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
3921 GEN_MEM_FUNCS(dcbz),
d63001d1 3922 },
76a66253 3923};
9a64fbe4 3924
b068d6a7
JM		 3925static always_inline void handler_dcbz (DisasContext *ctx,
3926 int dcache_line_size)
d63001d1
JM		 3927{
3928 int n;
3929
3930 switch (dcache_line_size) {
3931 case 32:
3932 n = 0;
3933 break;
3934 case 64:
3935 n = 1;
3936 break;
3937 case 128:
3938 n = 2;
3939 break;
3940 default:
3941 n = 3;
3942 break;
3943 }
3944 op_dcbz(n);
3945}
3946
3947GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 3948{
e2be8d8d 3949 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 3950 handler_dcbz(ctx, ctx->dcache_line_size);
3951 gen_op_check_reservation();
3952}
3953
c7697e1f 3954GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 3955{
e2be8d8d 3956 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 3957 if (ctx->opcode & 0x00200000)
3958 handler_dcbz(ctx, ctx->dcache_line_size);
3959 else
3960 handler_dcbz(ctx, -1);
4b3686fa 3961 gen_op_check_reservation();
79aceca5
FB		 3962}
3963
3964/* icbi */
36f69651 3965#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 3966#define gen_op_icbi_le_raw gen_op_icbi_raw
3967#define gen_op_icbi_le_user gen_op_icbi_user
3968#define gen_op_icbi_le_kernel gen_op_icbi_kernel
3969#define gen_op_icbi_le_hypv gen_op_icbi_hypv
3970#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
3971#define gen_op_icbi_le_64_user gen_op_icbi_64_user
3972#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
3973#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
3974static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
3975 GEN_MEM_FUNCS(icbi),
36f69651 3976};
e1833e1f 3977
1b413d55 3978GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 3979{
30032c94
JM		 3980 /* NIP cannot be restored if the memory exception comes from an helper */
3981 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3982 gen_addr_reg_index(cpu_T[0], ctx);
36f69651 3983 op_icbi();
79aceca5
FB		 3984}
3985
3986/* Optional: */
3987/* dcba */
a750fc0b 3988GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 3989{
0db1b20e
JM		 3990 /* interpreted as no-op */
3991 /* XXX: specification say this is treated as a store by the MMU
3992 * but does not generate any exception
3993 */
79aceca5
FB		 3994}
3995
3996/*** Segment register manipulation ***/
3997/* Supervisor only: */
3998/* mfsr */
3999GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4000{
9a64fbe4 4001#if defined(CONFIG_USER_ONLY)
e1833e1f 4002 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4003#else
76a66253 4004 if (unlikely(!ctx->supervisor)) {
e1833e1f 4005 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4006 return;
9a64fbe4 4007 }
86c581dc 4008 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4009 gen_op_load_sr();
f78fb44e 4010 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4011#endif
79aceca5
FB		 4012}
4013
4014/* mfsrin */
9a64fbe4 4015GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4016{
9a64fbe4 4017#if defined(CONFIG_USER_ONLY)
e1833e1f 4018 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4019#else
76a66253 4020 if (unlikely(!ctx->supervisor)) {
e1833e1f 4021 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4022 return;
9a64fbe4 4023 }
f78fb44e 4024 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4025 gen_op_srli_T1(28);
4026 gen_op_load_sr();
f78fb44e 4027 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4028#endif
79aceca5
FB		 4029}
4030
4031/* mtsr */
e63c59cb 4032GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4033{
9a64fbe4 4034#if defined(CONFIG_USER_ONLY)
e1833e1f 4035 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4036#else
76a66253 4037 if (unlikely(!ctx->supervisor)) {
e1833e1f 4038 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4039 return;
9a64fbe4 4040 }
f78fb44e 4041 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4042 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4043 gen_op_store_sr();
9a64fbe4 4044#endif
79aceca5
FB		 4045}
4046
4047/* mtsrin */
9a64fbe4 4048GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4049{
9a64fbe4 4050#if defined(CONFIG_USER_ONLY)
e1833e1f 4051 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4052#else
76a66253 4053 if (unlikely(!ctx->supervisor)) {
e1833e1f 4054 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4055 return;
9a64fbe4 4056 }
f78fb44e
AJ		 4057 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4058 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4059 gen_op_srli_T1(28);
4060 gen_op_store_sr();
9a64fbe4 4061#endif
79aceca5
FB		 4062}
4063
12de9a39
JM		 4064#if defined(TARGET_PPC64)
4065/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4066/* mfsr */
c7697e1f 4067GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4068{
4069#if defined(CONFIG_USER_ONLY)
4070 GEN_EXCP_PRIVREG(ctx);
4071#else
4072 if (unlikely(!ctx->supervisor)) {
4073 GEN_EXCP_PRIVREG(ctx);
4074 return;
4075 }
86c581dc 4076 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4077 gen_op_load_slb();
f78fb44e 4078 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4079#endif
4080}
4081
4082/* mfsrin */
c7697e1f
JM		 4083GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4084 PPC_SEGMENT_64B)
12de9a39
JM		 4085{
4086#if defined(CONFIG_USER_ONLY)
4087 GEN_EXCP_PRIVREG(ctx);
4088#else
4089 if (unlikely(!ctx->supervisor)) {
4090 GEN_EXCP_PRIVREG(ctx);
4091 return;
4092 }
f78fb44e 4093 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4094 gen_op_srli_T1(28);
4095 gen_op_load_slb();
f78fb44e 4096 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4097#endif
4098}
4099
4100/* mtsr */
c7697e1f 4101GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4102{
4103#if defined(CONFIG_USER_ONLY)
4104 GEN_EXCP_PRIVREG(ctx);
4105#else
4106 if (unlikely(!ctx->supervisor)) {
4107 GEN_EXCP_PRIVREG(ctx);
4108 return;
4109 }
f78fb44e 4110 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4111 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4112 gen_op_store_slb();
4113#endif
4114}
4115
4116/* mtsrin */
c7697e1f
JM		 4117GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4118 PPC_SEGMENT_64B)
12de9a39
JM		 4119{
4120#if defined(CONFIG_USER_ONLY)
4121 GEN_EXCP_PRIVREG(ctx);
4122#else
4123 if (unlikely(!ctx->supervisor)) {
4124 GEN_EXCP_PRIVREG(ctx);
4125 return;
4126 }
f78fb44e
AJ		 4127 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4128 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4129 gen_op_srli_T1(28);
4130 gen_op_store_slb();
4131#endif
4132}
4133#endif /* defined(TARGET_PPC64) */
4134
79aceca5
FB		 4135/*** Lookaside buffer management ***/
4136/* Optional & supervisor only: */
4137/* tlbia */
3fc6c082 4138GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4139{
9a64fbe4 4140#if defined(CONFIG_USER_ONLY)
e1833e1f 4141 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4142#else
76a66253 4143 if (unlikely(!ctx->supervisor)) {
e1833e1f 4144 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4145 return;
9a64fbe4
FB		 4146 }
4147 gen_op_tlbia();
4148#endif
79aceca5
FB		 4149}
4150
4151/* tlbie */
76a66253 4152GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4153{
9a64fbe4 4154#if defined(CONFIG_USER_ONLY)
e1833e1f 4155 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4156#else
76a66253 4157 if (unlikely(!ctx->supervisor)) {
e1833e1f 4158 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4159 return;
9a64fbe4 4160 }
f78fb44e 4161 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4162#if defined(TARGET_PPC64)
4163 if (ctx->sf_mode)
4164 gen_op_tlbie_64();
4165 else
4166#endif
4167 gen_op_tlbie();
9a64fbe4 4168#endif
79aceca5
FB		 4169}
4170
4171/* tlbsync */
76a66253 4172GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4173{
9a64fbe4 4174#if defined(CONFIG_USER_ONLY)
e1833e1f 4175 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4176#else
76a66253 4177 if (unlikely(!ctx->supervisor)) {
e1833e1f 4178 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4179 return;
9a64fbe4
FB		 4180 }
4181 /* This has no effect: it should ensure that all previous
4182 * tlbie have completed
4183 */
e1833e1f 4184 GEN_STOP(ctx);
9a64fbe4 4185#endif
79aceca5
FB		 4186}
4187
426613db
JM		 4188#if defined(TARGET_PPC64)
4189/* slbia */
4190GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4191{
4192#if defined(CONFIG_USER_ONLY)
e1833e1f 4193 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4194#else
4195 if (unlikely(!ctx->supervisor)) {
e1833e1f 4196 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4197 return;
4198 }
4199 gen_op_slbia();
426613db
JM		 4200#endif
4201}
4202
4203/* slbie */
4204GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4205{
4206#if defined(CONFIG_USER_ONLY)
e1833e1f 4207 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4208#else
4209 if (unlikely(!ctx->supervisor)) {
e1833e1f 4210 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4211 return;
4212 }
f78fb44e 4213 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4214 gen_op_slbie();
426613db
JM		 4215#endif
4216}
4217#endif
4218
79aceca5
FB		 4219/*** External control ***/
4220/* Optional: */
9a64fbe4
FB		 4221#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4222#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4223static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4224 GEN_MEM_FUNCS(eciwx),
111bfab3 4225};
7863667f
JM		 4226static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4227 GEN_MEM_FUNCS(ecowx),
111bfab3 4228};
9a64fbe4 4229
111bfab3 4230/* eciwx */
79aceca5
FB		 4231GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4232{
9a64fbe4 4233 /* Should check EAR[E] & alignment ! */
e2be8d8d 4234 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4235 op_eciwx();
f78fb44e 4236 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4237}
4238
4239/* ecowx */
4240GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4241{
4242 /* Should check EAR[E] & alignment ! */
e2be8d8d 4243 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4244 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4245 op_ecowx();
4246}
4247
4248/* PowerPC 601 specific instructions */
4249/* abs - abs. */
4250GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4251{
f78fb44e 4252 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4253 gen_op_POWER_abs();
f78fb44e 4254 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4255 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4256 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4257}
4258
4259/* abso - abso. */
4260GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4261{
f78fb44e 4262 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4263 gen_op_POWER_abso();
f78fb44e 4264 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4265 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4266 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4267}
4268
4269/* clcs */
a750fc0b 4270GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4271{
f78fb44e 4272 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4273 gen_op_POWER_clcs();
c7697e1f 4274 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4275 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4276}
4277
4278/* div - div. */
4279GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4280{
f78fb44e
AJ		 4281 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4282 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4283 gen_op_POWER_div();
f78fb44e 4284 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4285 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4286 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4287}
4288
4289/* divo - divo. */
4290GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4291{
f78fb44e
AJ		 4292 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4293 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4294 gen_op_POWER_divo();
f78fb44e 4295 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4296 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4297 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4298}
4299
4300/* divs - divs. */
4301GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4302{
f78fb44e
AJ		 4303 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4304 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4305 gen_op_POWER_divs();
f78fb44e 4306 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4307 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4308 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4309}
4310
4311/* divso - divso. */
4312GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4313{
f78fb44e
AJ		 4314 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4315 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4316 gen_op_POWER_divso();
f78fb44e 4317 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4318 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4319 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4320}
4321
4322/* doz - doz. */
4323GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4324{
f78fb44e
AJ		 4325 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4326 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4327 gen_op_POWER_doz();
f78fb44e 4328 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4329 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4330 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4331}
4332
4333/* dozo - dozo. */
4334GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4335{
f78fb44e
AJ		 4336 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4337 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4338 gen_op_POWER_dozo();
f78fb44e 4339 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4340 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4341 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4342}
4343
4344/* dozi */
4345GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4346{
f78fb44e 4347 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4348 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4349 gen_op_POWER_doz();
f78fb44e 4350 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4351}
4352
7863667f
JM		 4353/* As lscbx load from memory byte after byte, it's always endian safe.
4354 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4355 */
2857068e 4356#define op_POWER_lscbx(start, ra, rb) \
76a66253 4357(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 4358#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4359#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4360#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4361#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4362#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4363#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4364#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4365#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4366#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4367#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4368#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4369#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4370static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4371 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4372};
76a66253
JM		 4373
4374/* lscbx - lscbx. */
4375GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4376{
4377 int ra = rA(ctx->opcode);
4378 int rb = rB(ctx->opcode);
4379
e2be8d8d 4380 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4381 if (ra == 0) {
4382 ra = rb;
4383 }
4384 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4385 gen_update_nip(ctx, ctx->nip - 4);
3d7b417e
AJ		 4386 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4387 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4388 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
76a66253 4389 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3d7b417e
AJ		 4390 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4391 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253 4392 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4393 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4394}
4395
4396/* maskg - maskg. */
4397GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4398{
f78fb44e
AJ		 4399 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4400 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4401 gen_op_POWER_maskg();
f78fb44e 4402 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4403 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4404 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4405}
4406
4407/* maskir - maskir. */
4408GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4409{
f78fb44e
AJ		 4410 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4411 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4412 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4413 gen_op_POWER_maskir();
f78fb44e 4414 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4415 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4416 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4417}
4418
4419/* mul - mul. */
4420GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4421{
f78fb44e
AJ		 4422 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4423 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4424 gen_op_POWER_mul();
f78fb44e 4425 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4426 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4427 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4428}
4429
4430/* mulo - mulo. */
4431GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4432{
f78fb44e
AJ		 4433 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4434 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4435 gen_op_POWER_mulo();
f78fb44e 4436 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4437 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4438 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4439}
4440
4441/* nabs - nabs. */
4442GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4443{
f78fb44e 4444 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4445 gen_op_POWER_nabs();
f78fb44e 4446 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4447 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4448 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4449}
4450
4451/* nabso - nabso. */
4452GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4453{
f78fb44e 4454 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4455 gen_op_POWER_nabso();
f78fb44e 4456 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4457 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4458 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4459}
4460
4461/* rlmi - rlmi. */
4462GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4463{
4464 uint32_t mb, me;
4465
4466 mb = MB(ctx->opcode);
4467 me = ME(ctx->opcode);
f78fb44e
AJ		 4468 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4469 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4470 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4471 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4472 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4473 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4474 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4475}
4476
4477/* rrib - rrib. */
4478GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4479{
f78fb44e
AJ		 4480 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4481 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4482 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4483 gen_op_POWER_rrib();
f78fb44e 4484 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4485 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4486 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4487}
4488
4489/* sle - sle. */
4490GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4491{
f78fb44e
AJ		 4492 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4493 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4494 gen_op_POWER_sle();
f78fb44e 4495 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4496 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4497 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4498}
4499
4500/* sleq - sleq. */
4501GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4502{
f78fb44e
AJ		 4503 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4504 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4505 gen_op_POWER_sleq();
f78fb44e 4506 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4507 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4508 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4509}
4510
4511/* sliq - sliq. */
4512GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4513{
f78fb44e 4514 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4515 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4516 gen_op_POWER_sle();
f78fb44e 4517 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4518 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4519 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4520}
4521
4522/* slliq - slliq. */
4523GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4524{
f78fb44e 4525 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4526 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4527 gen_op_POWER_sleq();
f78fb44e 4528 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4529 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4530 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4531}
4532
4533/* sllq - sllq. */
4534GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4535{
f78fb44e
AJ		 4536 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4537 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4538 gen_op_POWER_sllq();
f78fb44e 4539 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4540 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4541 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4542}
4543
4544/* slq - slq. */
4545GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4546{
f78fb44e
AJ		 4547 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4548 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4549 gen_op_POWER_slq();
f78fb44e 4550 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4551 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4552 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4553}
4554
d9bce9d9 4555/* sraiq - sraiq. */
76a66253
JM		 4556GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4557{
f78fb44e 4558 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4559 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4560 gen_op_POWER_sraq();
f78fb44e 4561 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4562 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4563 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4564}
4565
4566/* sraq - sraq. */
4567GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4568{
f78fb44e
AJ		 4569 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4570 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4571 gen_op_POWER_sraq();
f78fb44e 4572 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4573 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4574 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4575}
4576
4577/* sre - sre. */
4578GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4579{
f78fb44e
AJ		 4580 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4581 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4582 gen_op_POWER_sre();
f78fb44e 4583 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4584 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4585 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4586}
4587
4588/* srea - srea. */
4589GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4590{
f78fb44e
AJ		 4591 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4592 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4593 gen_op_POWER_srea();
f78fb44e 4594 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4595 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4596 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4597}
4598
4599/* sreq */
4600GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4601{
f78fb44e
AJ		 4602 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4603 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4604 gen_op_POWER_sreq();
f78fb44e 4605 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4606 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4607 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4608}
4609
4610/* sriq */
4611GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4612{
f78fb44e 4613 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4614 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4615 gen_op_POWER_srq();
f78fb44e 4616 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4617 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4618 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4619}
4620
4621/* srliq */
4622GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4623{
f78fb44e
AJ		 4624 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4625 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4626 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4627 gen_op_POWER_srlq();
f78fb44e 4628 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4629 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4630 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4631}
4632
4633/* srlq */
4634GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4635{
f78fb44e
AJ		 4636 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4637 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4638 gen_op_POWER_srlq();
f78fb44e 4639 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4640 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4641 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4642}
4643
4644/* srq */
4645GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4646{
f78fb44e
AJ		 4647 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4648 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4649 gen_op_POWER_srq();
f78fb44e 4650 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4651 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4652 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4653}
4654
4655/* PowerPC 602 specific instructions */
4656/* dsa */
4657GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4658{
4659 /* XXX: TODO */
e1833e1f 4660 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4661}
4662
4663/* esa */
4664GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4665{
4666 /* XXX: TODO */
e1833e1f 4667 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4668}
4669
4670/* mfrom */
4671GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4672{
4673#if defined(CONFIG_USER_ONLY)
e1833e1f 4674 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4675#else
4676 if (unlikely(!ctx->supervisor)) {
e1833e1f 4677 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4678 return;
4679 }
f78fb44e 4680 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4681 gen_op_602_mfrom();
f78fb44e 4682 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4683#endif
4684}
4685
4686/* 602 - 603 - G2 TLB management */
4687/* tlbld */
c7697e1f 4688GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4689{
4690#if defined(CONFIG_USER_ONLY)
e1833e1f 4691 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4692#else
4693 if (unlikely(!ctx->supervisor)) {
e1833e1f 4694 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4695 return;
4696 }
f78fb44e 4697 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4698 gen_op_6xx_tlbld();
76a66253
JM		 4699#endif
4700}
4701
4702/* tlbli */
c7697e1f 4703GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4704{
4705#if defined(CONFIG_USER_ONLY)
e1833e1f 4706 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4707#else
4708 if (unlikely(!ctx->supervisor)) {
e1833e1f 4709 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4710 return;
4711 }
f78fb44e 4712 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4713 gen_op_6xx_tlbli();
76a66253
JM		 4714#endif
4715}
4716
7dbe11ac
JM		 4717/* 74xx TLB management */
4718/* tlbld */
c7697e1f 4719GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4720{
4721#if defined(CONFIG_USER_ONLY)
4722 GEN_EXCP_PRIVOPC(ctx);
4723#else
4724 if (unlikely(!ctx->supervisor)) {
4725 GEN_EXCP_PRIVOPC(ctx);
4726 return;
4727 }
f78fb44e 4728 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4729 gen_op_74xx_tlbld();
4730#endif
4731}
4732
4733/* tlbli */
c7697e1f 4734GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4735{
4736#if defined(CONFIG_USER_ONLY)
4737 GEN_EXCP_PRIVOPC(ctx);
4738#else
4739 if (unlikely(!ctx->supervisor)) {
4740 GEN_EXCP_PRIVOPC(ctx);
4741 return;
4742 }
f78fb44e 4743 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4744 gen_op_74xx_tlbli();
4745#endif
4746}
4747
76a66253
JM		 4748/* POWER instructions not in PowerPC 601 */
4749/* clf */
4750GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4751{
4752 /* Cache line flush: implemented as no-op */
4753}
4754
4755/* cli */
4756GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4757{
7f75ffd3 4758 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4759#if defined(CONFIG_USER_ONLY)
e1833e1f 4760 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4761#else
4762 if (unlikely(!ctx->supervisor)) {
e1833e1f 4763 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4764 return;
4765 }
4766#endif
4767}
4768
4769/* dclst */
4770GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4771{
4772 /* Data cache line store: treated as no-op */
4773}
4774
4775GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
4776{
4777#if defined(CONFIG_USER_ONLY)
e1833e1f 4778 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4779#else
4780 if (unlikely(!ctx->supervisor)) {
e1833e1f 4781 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4782 return;
4783 }
4784 int ra = rA(ctx->opcode);
4785 int rd = rD(ctx->opcode);
4786
e2be8d8d 4787 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4788 gen_op_POWER_mfsri();
f78fb44e 4789 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 4790 if (ra != 0 && ra != rd)
f78fb44e 4791 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 4792#endif
4793}
4794
4795GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
4796{
4797#if defined(CONFIG_USER_ONLY)
e1833e1f 4798 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4799#else
4800 if (unlikely(!ctx->supervisor)) {
e1833e1f 4801 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4802 return;
4803 }
e2be8d8d 4804 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4805 gen_op_POWER_rac();
f78fb44e 4806 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4807#endif
4808}
4809
4810GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
4811{
4812#if defined(CONFIG_USER_ONLY)
e1833e1f 4813 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4814#else
4815 if (unlikely(!ctx->supervisor)) {
e1833e1f 4816 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4817 return;
4818 }
4819 gen_op_POWER_rfsvc();
e1833e1f 4820 GEN_SYNC(ctx);
76a66253
JM		 4821#endif
4822}
4823
4824/* svc is not implemented for now */
4825
4826/* POWER2 specific instructions */
4827/* Quad manipulation (load/store two floats at a time) */
7863667f 4828/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 4829#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
4830#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 4831#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
4832#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
4833#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
4834#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
4835#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
4836#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
4837#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
4838#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
4839#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
4840#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
4841#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
4842#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
4843#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
4844#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
4845#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
4846#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
4847static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
4848 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 4849};
7863667f
JM		 4850static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
4851 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 4852};
76a66253
JM		 4853
4854/* lfq */
4855GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4856{
4857 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4858 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4859 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4860 op_POWER2_lfq();
a5e26afa
AJ		 4861 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4862 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4863}
4864
4865/* lfqu */
4866GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4867{
4868 int ra = rA(ctx->opcode);
4869
4870 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4871 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4872 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 4873 op_POWER2_lfq();
a5e26afa
AJ		 4874 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4875 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4876 if (ra != 0)
f78fb44e 4877 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4878}
4879
4880/* lfqux */
4881GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
4882{
4883 int ra = rA(ctx->opcode);
4884
4885 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4886 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4887 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4888 op_POWER2_lfq();
a5e26afa
AJ		 4889 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4890 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 4891 if (ra != 0)
f78fb44e 4892 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4893}
4894
4895/* lfqx */
4896GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
4897{
4898 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4899 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4900 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4901 op_POWER2_lfq();
a5e26afa
AJ		 4902 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
4903 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 4904}
4905
4906/* stfq */
4907GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4908{
4909 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4910 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4911 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4912 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4913 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4914 op_POWER2_stfq();
4915}
4916
4917/* stfqu */
4918GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
4919{
4920 int ra = rA(ctx->opcode);
4921
4922 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4923 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4924 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 4925 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4926 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4927 op_POWER2_stfq();
4928 if (ra != 0)
f78fb44e 4929 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4930}
4931
4932/* stfqux */
4933GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
4934{
4935 int ra = rA(ctx->opcode);
4936
4937 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4938 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4939 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 4940 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4941 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4942 op_POWER2_stfq();
4943 if (ra != 0)
f78fb44e 4944 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 4945}
4946
4947/* stfqx */
4948GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
4949{
4950 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4951 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4952 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 4953 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
4954 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 4955 op_POWER2_stfq();
4956}
4957
4958/* BookE specific instructions */
2662a059 4959/* XXX: not implemented on 440 ? */
05332d70 4960GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 4961{
4962 /* XXX: TODO */
e1833e1f 4963 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4964}
4965
2662a059 4966/* XXX: not implemented on 440 ? */
05332d70 4967GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 4968{
4969#if defined(CONFIG_USER_ONLY)
e1833e1f 4970 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4971#else
4972 if (unlikely(!ctx->supervisor)) {
e1833e1f 4973 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4974 return;
4975 }
e2be8d8d 4976 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4977 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 4978#if defined(TARGET_PPC64)
4979 if (ctx->sf_mode)
4980 gen_op_tlbie_64();
4981 else
4982#endif
4983 gen_op_tlbie();
76a66253
JM		 4984#endif
4985}
4986
4987/* All 405 MAC instructions are translated here */
b068d6a7
JM		 4988static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
4989 int opc2, int opc3,
4990 int ra, int rb, int rt, int Rc)
76a66253 4991{
f78fb44e
AJ		 4992 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
4993 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
76a66253
JM		 4994 switch (opc3 & 0x0D) {
4995 case 0x05:
4996 /* macchw - macchw. - macchwo - macchwo. */
4997 /* macchws - macchws. - macchwso - macchwso. */
4998 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
4999 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5000 /* mulchw - mulchw. */
5001 gen_op_405_mulchw();
5002 break;
5003 case 0x04:
5004 /* macchwu - macchwu. - macchwuo - macchwuo. */
5005 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5006 /* mulchwu - mulchwu. */
5007 gen_op_405_mulchwu();
5008 break;
5009 case 0x01:
5010 /* machhw - machhw. - machhwo - machhwo. */
5011 /* machhws - machhws. - machhwso - machhwso. */
5012 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5013 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5014 /* mulhhw - mulhhw. */
5015 gen_op_405_mulhhw();
5016 break;
5017 case 0x00:
5018 /* machhwu - machhwu. - machhwuo - machhwuo. */
5019 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5020 /* mulhhwu - mulhhwu. */
5021 gen_op_405_mulhhwu();
5022 break;
5023 case 0x0D:
5024 /* maclhw - maclhw. - maclhwo - maclhwo. */
5025 /* maclhws - maclhws. - maclhwso - maclhwso. */
5026 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5027 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5028 /* mullhw - mullhw. */
5029 gen_op_405_mullhw();
5030 break;
5031 case 0x0C:
5032 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5033 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5034 /* mullhwu - mullhwu. */
5035 gen_op_405_mullhwu();
5036 break;
5037 }
5038 if (opc2 & 0x02) {
5039 /* nmultiply-and-accumulate (0x0E) */
5040 gen_op_neg();
5041 }
5042 if (opc2 & 0x04) {
5043 /* (n)multiply-and-accumulate (0x0C - 0x0E) */
f78fb44e 5044 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
e55fd934 5045 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
76a66253
JM		 5046 gen_op_405_add_T0_T2();
5047 }
5048 if (opc3 & 0x10) {
5049 /* Check overflow */
5050 if (opc3 & 0x01)
c3e10c7b 5051 gen_op_check_addo();
76a66253
JM		 5052 else
5053 gen_op_405_check_ovu();
5054 }
5055 if (opc3 & 0x02) {
5056 /* Saturate */
5057 if (opc3 & 0x01)
5058 gen_op_405_check_sat();
5059 else
5060 gen_op_405_check_satu();
5061 }
f78fb44e 5062 tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
76a66253
JM		 5063 if (unlikely(Rc) != 0) {
5064 /* Update Rc0 */
e1571908 5065 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 5066 }
5067}
5068
a750fc0b
JM		 5069#define GEN_MAC_HANDLER(name, opc2, opc3) \
5070GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5071{ \
5072 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5073 rD(ctx->opcode), Rc(ctx->opcode)); \
5074}
5075
5076/* macchw - macchw. */
a750fc0b 5077GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5078/* macchwo - macchwo. */
a750fc0b 5079GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5080/* macchws - macchws. */
a750fc0b 5081GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5082/* macchwso - macchwso. */
a750fc0b 5083GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5084/* macchwsu - macchwsu. */
a750fc0b 5085GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5086/* macchwsuo - macchwsuo. */
a750fc0b 5087GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5088/* macchwu - macchwu. */
a750fc0b 5089GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5090/* macchwuo - macchwuo. */
a750fc0b 5091GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5092/* machhw - machhw. */
a750fc0b 5093GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5094/* machhwo - machhwo. */
a750fc0b 5095GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5096/* machhws - machhws. */
a750fc0b 5097GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5098/* machhwso - machhwso. */
a750fc0b 5099GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5100/* machhwsu - machhwsu. */
a750fc0b 5101GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5102/* machhwsuo - machhwsuo. */
a750fc0b 5103GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5104/* machhwu - machhwu. */
a750fc0b 5105GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5106/* machhwuo - machhwuo. */
a750fc0b 5107GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5108/* maclhw - maclhw. */
a750fc0b 5109GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5110/* maclhwo - maclhwo. */
a750fc0b 5111GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5112/* maclhws - maclhws. */
a750fc0b 5113GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5114/* maclhwso - maclhwso. */
a750fc0b 5115GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5116/* maclhwu - maclhwu. */
a750fc0b 5117GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5118/* maclhwuo - maclhwuo. */
a750fc0b 5119GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5120/* maclhwsu - maclhwsu. */
a750fc0b 5121GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5122/* maclhwsuo - maclhwsuo. */
a750fc0b 5123GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5124/* nmacchw - nmacchw. */
a750fc0b 5125GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5126/* nmacchwo - nmacchwo. */
a750fc0b 5127GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5128/* nmacchws - nmacchws. */
a750fc0b 5129GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5130/* nmacchwso - nmacchwso. */
a750fc0b 5131GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5132/* nmachhw - nmachhw. */
a750fc0b 5133GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5134/* nmachhwo - nmachhwo. */
a750fc0b 5135GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5136/* nmachhws - nmachhws. */
a750fc0b 5137GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5138/* nmachhwso - nmachhwso. */
a750fc0b 5139GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5140/* nmaclhw - nmaclhw. */
a750fc0b 5141GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5142/* nmaclhwo - nmaclhwo. */
a750fc0b 5143GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5144/* nmaclhws - nmaclhws. */
a750fc0b 5145GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5146/* nmaclhwso - nmaclhwso. */
a750fc0b 5147GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5148
5149/* mulchw - mulchw. */
a750fc0b 5150GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5151/* mulchwu - mulchwu. */
a750fc0b 5152GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5153/* mulhhw - mulhhw. */
a750fc0b 5154GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5155/* mulhhwu - mulhhwu. */
a750fc0b 5156GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5157/* mullhw - mullhw. */
a750fc0b 5158GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5159/* mullhwu - mullhwu. */
a750fc0b 5160GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5161
5162/* mfdcr */
05332d70 5163GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5164{
5165#if defined(CONFIG_USER_ONLY)
e1833e1f 5166 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5167#else
5168 uint32_t dcrn = SPR(ctx->opcode);
5169
5170 if (unlikely(!ctx->supervisor)) {
e1833e1f 5171 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5172 return;
5173 }
86c581dc 5174 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5175 gen_op_load_dcr();
f78fb44e 5176 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5177#endif
5178}
5179
5180/* mtdcr */
05332d70 5181GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5182{
5183#if defined(CONFIG_USER_ONLY)
e1833e1f 5184 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5185#else
5186 uint32_t dcrn = SPR(ctx->opcode);
5187
5188 if (unlikely(!ctx->supervisor)) {
e1833e1f 5189 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5190 return;
5191 }
86c581dc 5192 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5193 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5194 gen_op_store_dcr();
5195#endif
5196}
5197
5198/* mfdcrx */
2662a059 5199/* XXX: not implemented on 440 ? */
05332d70 5200GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5201{
5202#if defined(CONFIG_USER_ONLY)
e1833e1f 5203 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5204#else
5205 if (unlikely(!ctx->supervisor)) {
e1833e1f 5206 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5207 return;
5208 }
f78fb44e 5209 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5210 gen_op_load_dcr();
f78fb44e 5211 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5212 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5213#endif
5214}
5215
5216/* mtdcrx */
2662a059 5217/* XXX: not implemented on 440 ? */
05332d70 5218GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5219{
5220#if defined(CONFIG_USER_ONLY)
e1833e1f 5221 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5222#else
5223 if (unlikely(!ctx->supervisor)) {
e1833e1f 5224 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5225 return;
5226 }
f78fb44e
AJ		 5227 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5228 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5229 gen_op_store_dcr();
a750fc0b 5230 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5231#endif
5232}
5233
a750fc0b
JM		 5234/* mfdcrux (PPC 460) : user-mode access to DCR */
5235GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5236{
f78fb44e 5237 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5238 gen_op_load_dcr();
f78fb44e 5239 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5240 /* Note: Rc update flag set leads to undefined state of Rc0 */
5241}
5242
5243/* mtdcrux (PPC 460) : user-mode access to DCR */
5244GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5245{
f78fb44e
AJ		 5246 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5247 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5248 gen_op_store_dcr();
5249 /* Note: Rc update flag set leads to undefined state of Rc0 */
5250}
5251
76a66253
JM		 5252/* dccci */
5253GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5254{
5255#if defined(CONFIG_USER_ONLY)
e1833e1f 5256 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5257#else
5258 if (unlikely(!ctx->supervisor)) {
e1833e1f 5259 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5260 return;
5261 }
5262 /* interpreted as no-op */
5263#endif
5264}
5265
5266/* dcread */
5267GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5268{
5269#if defined(CONFIG_USER_ONLY)
e1833e1f 5270 GEN_EXCP_PRIVOPC(ctx);
76a66253 5271#else
b61f2753 5272 TCGv EA, val;
76a66253 5273 if (unlikely(!ctx->supervisor)) {
e1833e1f 5274 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5275 return;
5276 }
b61f2753
AJ		 5277 EA = tcg_temp_new(TCG_TYPE_TL);
5278 gen_addr_reg_index(EA, ctx);
5279 val = tcg_temp_new(TCG_TYPE_TL);
5280 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5281 tcg_temp_free(val);
5282 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5283 tcg_temp_free(EA);
76a66253
JM		 5284#endif
5285}
5286
5287/* icbt */
c7697e1f 5288GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5289{
5290 /* interpreted as no-op */
5291 /* XXX: specification say this is treated as a load by the MMU
5292 * but does not generate any exception
5293 */
5294}
5295
5296/* iccci */
5297GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5298{
5299#if defined(CONFIG_USER_ONLY)
e1833e1f 5300 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5301#else
5302 if (unlikely(!ctx->supervisor)) {
e1833e1f 5303 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5304 return;
5305 }
5306 /* interpreted as no-op */
5307#endif
5308}
5309
5310/* icread */
5311GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5312{
5313#if defined(CONFIG_USER_ONLY)
e1833e1f 5314 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5315#else
5316 if (unlikely(!ctx->supervisor)) {
e1833e1f 5317 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5318 return;
5319 }
5320 /* interpreted as no-op */
5321#endif
5322}
5323
5324/* rfci (supervisor only) */
c7697e1f 5325GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5326{
5327#if defined(CONFIG_USER_ONLY)
e1833e1f 5328 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5329#else
5330 if (unlikely(!ctx->supervisor)) {
e1833e1f 5331 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5332 return;
5333 }
5334 /* Restore CPU state */
5335 gen_op_40x_rfci();
e1833e1f 5336 GEN_SYNC(ctx);
a42bd6cc
JM		 5337#endif
5338}
5339
5340GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5341{
5342#if defined(CONFIG_USER_ONLY)
e1833e1f 5343 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5344#else
5345 if (unlikely(!ctx->supervisor)) {
e1833e1f 5346 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5347 return;
5348 }
5349 /* Restore CPU state */
5350 gen_op_rfci();
e1833e1f 5351 GEN_SYNC(ctx);
a42bd6cc
JM		 5352#endif
5353}
5354
5355/* BookE specific */
2662a059 5356/* XXX: not implemented on 440 ? */
05332d70 5357GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5358{
5359#if defined(CONFIG_USER_ONLY)
e1833e1f 5360 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5361#else
5362 if (unlikely(!ctx->supervisor)) {
e1833e1f 5363 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5364 return;
5365 }
5366 /* Restore CPU state */
a42bd6cc 5367 gen_op_rfdi();
e1833e1f 5368 GEN_SYNC(ctx);
76a66253
JM		 5369#endif
5370}
5371
2662a059 5372/* XXX: not implemented on 440 ? */
a750fc0b 5373GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5374{
5375#if defined(CONFIG_USER_ONLY)
e1833e1f 5376 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5377#else
5378 if (unlikely(!ctx->supervisor)) {
e1833e1f 5379 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5380 return;
5381 }
5382 /* Restore CPU state */
5383 gen_op_rfmci();
e1833e1f 5384 GEN_SYNC(ctx);
a42bd6cc
JM		 5385#endif
5386}
5eb7995e 5387
d9bce9d9 5388/* TLB management - PowerPC 405 implementation */
76a66253 5389/* tlbre */
c7697e1f 5390GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5391{
5392#if defined(CONFIG_USER_ONLY)
e1833e1f 5393 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5394#else
5395 if (unlikely(!ctx->supervisor)) {
e1833e1f 5396 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5397 return;
5398 }
5399 switch (rB(ctx->opcode)) {
5400 case 0:
f78fb44e 5401 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5402 gen_op_4xx_tlbre_hi();
f78fb44e 5403 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5404 break;
5405 case 1:
f78fb44e 5406 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5407 gen_op_4xx_tlbre_lo();
f78fb44e 5408 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5409 break;
5410 default:
e1833e1f 5411 GEN_EXCP_INVAL(ctx);
76a66253 5412 break;
9a64fbe4 5413 }
76a66253
JM		 5414#endif
5415}
5416
d9bce9d9 5417/* tlbsx - tlbsx. */
c7697e1f 5418GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5419{
5420#if defined(CONFIG_USER_ONLY)
e1833e1f 5421 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5422#else
5423 if (unlikely(!ctx->supervisor)) {
e1833e1f 5424 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5425 return;
5426 }
e2be8d8d 5427 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5428 gen_op_4xx_tlbsx();
76a66253 5429 if (Rc(ctx->opcode))
daf4f96e 5430 gen_op_4xx_tlbsx_check();
f78fb44e 5431 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5432#endif
79aceca5
FB		 5433}
5434
76a66253 5435/* tlbwe */
c7697e1f 5436GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5437{
76a66253 5438#if defined(CONFIG_USER_ONLY)
e1833e1f 5439 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5440#else
5441 if (unlikely(!ctx->supervisor)) {
e1833e1f 5442 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5443 return;
5444 }
5445 switch (rB(ctx->opcode)) {
5446 case 0:
f78fb44e
AJ		 5447 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5448 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5449 gen_op_4xx_tlbwe_hi();
5450 break;
5451 case 1:
f78fb44e
AJ		 5452 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5453 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5454 gen_op_4xx_tlbwe_lo();
5455 break;
5456 default:
e1833e1f 5457 GEN_EXCP_INVAL(ctx);
76a66253 5458 break;
9a64fbe4 5459 }
76a66253
JM		 5460#endif
5461}
5462
a4bb6c3e 5463/* TLB management - PowerPC 440 implementation */
5eb7995e 5464/* tlbre */
c7697e1f 5465GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5466{
5467#if defined(CONFIG_USER_ONLY)
e1833e1f 5468 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5469#else
5470 if (unlikely(!ctx->supervisor)) {
e1833e1f 5471 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5472 return;
5473 }
5474 switch (rB(ctx->opcode)) {
5475 case 0:
5eb7995e 5476 case 1:
5eb7995e 5477 case 2:
f78fb44e 5478 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5479 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5480 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5481 break;
5482 default:
e1833e1f 5483 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5484 break;
5485 }
5486#endif
5487}
5488
5489/* tlbsx - tlbsx. */
c7697e1f 5490GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5491{
5492#if defined(CONFIG_USER_ONLY)
e1833e1f 5493 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5494#else
5495 if (unlikely(!ctx->supervisor)) {
e1833e1f 5496 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5497 return;
5498 }
e2be8d8d 5499 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5500 gen_op_440_tlbsx();
5eb7995e 5501 if (Rc(ctx->opcode))
daf4f96e 5502 gen_op_4xx_tlbsx_check();
f78fb44e 5503 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5504#endif
5505}
5506
5507/* tlbwe */
c7697e1f 5508GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5509{
5510#if defined(CONFIG_USER_ONLY)
e1833e1f 5511 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5512#else
5513 if (unlikely(!ctx->supervisor)) {
e1833e1f 5514 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5515 return;
5516 }
5517 switch (rB(ctx->opcode)) {
5518 case 0:
5eb7995e 5519 case 1:
5eb7995e 5520 case 2:
f78fb44e
AJ		 5521 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5522 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5523 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5524 break;
5525 default:
e1833e1f 5526 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5527 break;
5528 }
5529#endif
5530}
5531
76a66253 5532/* wrtee */
05332d70 5533GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5534{
5535#if defined(CONFIG_USER_ONLY)
e1833e1f 5536 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5537#else
5538 if (unlikely(!ctx->supervisor)) {
e1833e1f 5539 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5540 return;
5541 }
f78fb44e 5542 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5543 gen_op_wrte();
dee96f6c
JM		 5544 /* Stop translation to have a chance to raise an exception
5545 * if we just set msr_ee to 1
5546 */
e1833e1f 5547 GEN_STOP(ctx);
76a66253
JM		 5548#endif
5549}
5550
5551/* wrteei */
05332d70 5552GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5553{
5554#if defined(CONFIG_USER_ONLY)
e1833e1f 5555 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5556#else
5557 if (unlikely(!ctx->supervisor)) {
e1833e1f 5558 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5559 return;
5560 }
86c581dc 5561 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5562 gen_op_wrte();
dee96f6c
JM		 5563 /* Stop translation to have a chance to raise an exception
5564 * if we just set msr_ee to 1
5565 */
e1833e1f 5566 GEN_STOP(ctx);
76a66253
JM		 5567#endif
5568}
5569
08e46e54 5570/* PowerPC 440 specific instructions */
76a66253
JM		 5571/* dlmzb */
5572GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5573{
f78fb44e
AJ		 5574 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5575 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5576 gen_op_440_dlmzb();
f78fb44e 5577 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5578 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5579 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5580 if (Rc(ctx->opcode)) {
5581 gen_op_440_dlmzb_update_Rc();
47e4661c 5582 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
76a66253
JM		 5583 }
5584}
5585
5586/* mbar replaces eieio on 440 */
5587GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5588{
5589 /* interpreted as no-op */
5590}
5591
5592/* msync replaces sync on 440 */
0db1b20e 5593GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5594{
5595 /* interpreted as no-op */
5596}
5597
5598/* icbt */
c7697e1f 5599GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5600{
5601 /* interpreted as no-op */
5602 /* XXX: specification say this is treated as a load by the MMU
5603 * but does not generate any exception
5604 */
79aceca5
FB		 5605}
5606
a9d9eb8f
JM		 5607/*** Altivec vector extension ***/
5608/* Altivec registers moves */
a9d9eb8f 5609
1d542695
AJ		 5610static always_inline void gen_load_avr(int t, int reg) {
5611 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5612 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5613}
5614
5615static always_inline void gen_store_avr(int reg, int t) {
5616 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5617 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5618}
a9d9eb8f
JM		 5619
5620#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5621#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5622static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5623 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5624};
5625#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5626static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5627 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5628};
a9d9eb8f
JM		 5629
5630#define GEN_VR_LDX(name, opc2, opc3) \
5631GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5632{ \
5633 if (unlikely(!ctx->altivec_enabled)) { \
5634 GEN_EXCP_NO_VR(ctx); \
5635 return; \
5636 } \
e2be8d8d 5637 gen_addr_reg_index(cpu_T[0], ctx); \
a9d9eb8f 5638 op_vr_ldst(vr_l##name); \
1d542695 5639 gen_store_avr(rD(ctx->opcode), 0); \
a9d9eb8f
JM		 5640}
5641
5642#define GEN_VR_STX(name, opc2, opc3) \
5643GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5644{ \
5645 if (unlikely(!ctx->altivec_enabled)) { \
5646 GEN_EXCP_NO_VR(ctx); \
5647 return; \
5648 } \
e2be8d8d 5649 gen_addr_reg_index(cpu_T[0], ctx); \
1d542695 5650 gen_load_avr(0, rS(ctx->opcode)); \
a9d9eb8f
JM		 5651 op_vr_ldst(vr_st##name); \
5652}
5653
5654OP_VR_LD_TABLE(vx);
5655GEN_VR_LDX(vx, 0x07, 0x03);
5656/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5657#define gen_op_vr_lvxl gen_op_vr_lvx
5658GEN_VR_LDX(vxl, 0x07, 0x0B);
5659
5660OP_VR_ST_TABLE(vx);
5661GEN_VR_STX(vx, 0x07, 0x07);
5662/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5663#define gen_op_vr_stvxl gen_op_vr_stvx
5664GEN_VR_STX(vxl, 0x07, 0x0F);
5665
0487d6a8 5666/*** SPE extension ***/
0487d6a8 5667/* Register moves */
3cd7d1dd 5668
f78fb44e
AJ		 5669static always_inline void gen_load_gpr64(TCGv t, int reg) {
5670#if defined(TARGET_PPC64)
5671 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5672#else
36aa55dc 5673 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5674#endif
f78fb44e 5675}
3cd7d1dd 5676
f78fb44e
AJ		 5677static always_inline void gen_store_gpr64(int reg, TCGv t) {
5678#if defined(TARGET_PPC64)
5679 tcg_gen_mov_i64(cpu_gpr[reg], t);
5680#else
5681 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
19f98ff6 5682 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
f78fb44e
AJ		 5683 tcg_gen_shri_i64(tmp, t, 32);
5684 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5685 tcg_temp_free(tmp);
3cd7d1dd 5686#endif
f78fb44e 5687}
3cd7d1dd 5688
0487d6a8
JM		 5689#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5690GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5691{ \
5692 if (Rc(ctx->opcode)) \
5693 gen_##name1(ctx); \
5694 else \
5695 gen_##name0(ctx); \
5696}
5697
5698/* Handler for undefined SPE opcodes */
b068d6a7 5699static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5700{
e1833e1f 5701 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5702}
5703
5704/* SPE load and stores */
f0aabd1a 5705static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
0487d6a8
JM		 5706{
5707 target_long simm = rB(ctx->opcode);
5708
f0aabd1a
AJ		 5709 if (rA(ctx->opcode) == 0)
5710 tcg_gen_movi_tl(EA, simm << sh);
5711 else if (likely(simm != 0))
5712 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5713 else
5714 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
0487d6a8
JM		 5715}
5716
5717#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5718#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5719static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5720 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5721};
5722#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5723static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5724 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5725};
0487d6a8
JM		 5726
5727#define GEN_SPE_LD(name, sh) \
b068d6a7 5728static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5729{ \
5730 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5731 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5732 return; \
5733 } \
f0aabd1a 5734 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
0487d6a8 5735 op_spe_ldst(spe_l##name); \
f78fb44e 5736 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5737}
5738
5739#define GEN_SPE_LDX(name) \
b068d6a7 5740static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 5741{ \
5742 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5743 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5744 return; \
5745 } \
e2be8d8d 5746 gen_addr_reg_index(cpu_T[0], ctx); \
0487d6a8 5747 op_spe_ldst(spe_l##name); \
f78fb44e 5748 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 5749}
5750
5751#define GEN_SPEOP_LD(name, sh) \
5752OP_SPE_LD_TABLE(name); \
5753GEN_SPE_LD(name, sh); \
5754GEN_SPE_LDX(name)
5755
5756#define GEN_SPE_ST(name, sh) \
b068d6a7 5757static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 5758{ \
5759 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5760 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5761 return; \
5762 } \
f0aabd1a 5763 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
f78fb44e 5764 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5765 op_spe_ldst(spe_st##name); \
5766}
5767
5768#define GEN_SPE_STX(name) \
b068d6a7 5769static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 5770{ \
5771 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5772 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5773 return; \
5774 } \
e2be8d8d 5775 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 5776 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 5777 op_spe_ldst(spe_st##name); \
5778}
5779
5780#define GEN_SPEOP_ST(name, sh) \
5781OP_SPE_ST_TABLE(name); \
5782GEN_SPE_ST(name, sh); \
5783GEN_SPE_STX(name)
5784
5785#define GEN_SPEOP_LDST(name, sh) \
5786GEN_SPEOP_LD(name, sh); \
5787GEN_SPEOP_ST(name, sh)
5788
5789/* SPE arithmetic and logic */
5790#define GEN_SPEOP_ARITH2(name) \
b068d6a7 5791static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5792{ \
5793 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5794 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5795 return; \
5796 } \
f78fb44e
AJ		 5797 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5798 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5799 gen_op_##name(); \
f78fb44e 5800 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5801}
5802
cf960816 5803#define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \
3d3a6a0a
AJ		 5804static always_inline void gen_##name (DisasContext *ctx) \
5805{ \
5806 if (unlikely(!ctx->spe_enabled)) { \
5807 GEN_EXCP_NO_AP(ctx); \
5808 return; \
5809 } \
5810 TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \
5811 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
5812 gen_load_gpr64(t0, rA(ctx->opcode)); \
5813 gen_load_gpr64(t1, rB(ctx->opcode)); \
cf960816 5814 tcg_op(t0, t0, t1); \
3d3a6a0a
AJ		 5815 gen_store_gpr64(rD(ctx->opcode), t0); \
5816 tcg_temp_free(t0); \
5817 tcg_temp_free(t1); \
5818}
5819
0487d6a8 5820#define GEN_SPEOP_ARITH1(name) \
b068d6a7 5821static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5822{ \
5823 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5824 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5825 return; \
5826 } \
f78fb44e 5827 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8 5828 gen_op_##name(); \
f78fb44e 5829 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5830}
5831
5832#define GEN_SPEOP_COMP(name) \
b068d6a7 5833static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 5834{ \
5835 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5836 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5837 return; \
5838 } \
f78fb44e
AJ		 5839 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
5840 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 5841 gen_op_##name(); \
47e4661c 5842 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
0487d6a8
JM		 5843}
5844
5845/* Logical */
cf960816
AJ		 5846GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64);
5847GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64);
5848GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64);
5849GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64);
5850GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64);
5851GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64);
5852GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64);
5853GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64);
0487d6a8
JM		 5854GEN_SPEOP_ARITH2(evsrwu);
5855GEN_SPEOP_ARITH2(evsrws);
5856GEN_SPEOP_ARITH2(evslw);
5857GEN_SPEOP_ARITH2(evrlw);
5858GEN_SPEOP_ARITH2(evmergehi);
5859GEN_SPEOP_ARITH2(evmergelo);
5860GEN_SPEOP_ARITH2(evmergehilo);
5861GEN_SPEOP_ARITH2(evmergelohi);
5862
5863/* Arithmetic */
5864GEN_SPEOP_ARITH2(evaddw);
5865GEN_SPEOP_ARITH2(evsubfw);
5866GEN_SPEOP_ARITH1(evabs);
5867GEN_SPEOP_ARITH1(evneg);
5868GEN_SPEOP_ARITH1(evextsb);
5869GEN_SPEOP_ARITH1(evextsh);
5870GEN_SPEOP_ARITH1(evrndw);
5871GEN_SPEOP_ARITH1(evcntlzw);
5872GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 5873static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 5874{
5875 /* Note: brinc is usable even if SPE is disabled */
f78fb44e
AJ		 5876 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5877 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 5878 gen_op_brinc();
f78fb44e 5879 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
0487d6a8
JM		 5880}
5881
5882#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 5883static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5884{ \
5885 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5886 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5887 return; \
5888 } \
f78fb44e 5889 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8
JM		 5890 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
5891 gen_op_##name(); \
f78fb44e 5892 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5893}
5894
5895#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 5896static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 5897{ \
5898 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5899 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5900 return; \
5901 } \
f78fb44e 5902 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8
JM		 5903 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
5904 gen_op_##name(); \
f78fb44e 5905 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 5906}
5907
5908GEN_SPEOP_ARITH_IMM2(evaddw);
5909#define gen_evaddiw gen_evaddwi
5910GEN_SPEOP_ARITH_IMM2(evsubfw);
5911#define gen_evsubifw gen_evsubfwi
5912GEN_SPEOP_LOGIC_IMM2(evslw);
5913GEN_SPEOP_LOGIC_IMM2(evsrwu);
5914#define gen_evsrwis gen_evsrwsi
5915GEN_SPEOP_LOGIC_IMM2(evsrws);
5916#define gen_evsrwiu gen_evsrwui
5917GEN_SPEOP_LOGIC_IMM2(evrlw);
5918
b068d6a7 5919static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 5920{
5921 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
5922
5923 gen_op_splatwi_T0_64(imm);
f78fb44e 5924 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5925}
5926
b068d6a7 5927static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 5928{
5929 uint32_t imm = rA(ctx->opcode) << 27;
5930
5931 gen_op_splatwi_T0_64(imm);
f78fb44e 5932 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5933}
5934
5935/* Comparison */
5936GEN_SPEOP_COMP(evcmpgtu);
5937GEN_SPEOP_COMP(evcmpgts);
5938GEN_SPEOP_COMP(evcmpltu);
5939GEN_SPEOP_COMP(evcmplts);
5940GEN_SPEOP_COMP(evcmpeq);
5941
5942GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
5943GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
5944GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
5945GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
5946GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
5947GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
5948GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
5949GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
5950GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
5951GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
5952GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
5953GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
5954GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
5955GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
5956GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
5957GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
5958GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
5959GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
5960GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
5961GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
5962GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
5963GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
5964GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
5965GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
5966GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
5967
b068d6a7 5968static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 5969{
5970 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 5971 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 5972 return;
5973 }
47e4661c 5974 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
f78fb44e
AJ		 5975 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
5976 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
0487d6a8 5977 gen_op_evsel();
f78fb44e 5978 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 5979}
5980
c7697e1f 5981GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5982{
5983 gen_evsel(ctx);
5984}
c7697e1f 5985GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5986{
5987 gen_evsel(ctx);
5988}
c7697e1f 5989GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5990{
5991 gen_evsel(ctx);
5992}
c7697e1f 5993GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 5994{
5995 gen_evsel(ctx);
5996}
5997
5998/* Load and stores */
0487d6a8
JM		 5999GEN_SPEOP_LDST(dd, 3);
6000GEN_SPEOP_LDST(dw, 3);
6001GEN_SPEOP_LDST(dh, 3);
6002GEN_SPEOP_LDST(whe, 2);
6003GEN_SPEOP_LD(whou, 2);
6004GEN_SPEOP_LD(whos, 2);
6005GEN_SPEOP_ST(who, 2);
6006
0487d6a8 6007#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 6008static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 6009{ \
6010 gen_op_srli32_T1_64(); \
6011 gen_op_spe_stwwo_##suffix(); \
6012}
6013#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 6014static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 6015{ \
6016 gen_op_srli32_T1_64(); \
6017 gen_op_spe_stwwo_le_##suffix(); \
6018}
6019#if defined(TARGET_PPC64)
6020#define GEN_OP_SPE_STWWE(suffix) \
6021_GEN_OP_SPE_STWWE(suffix); \
6022_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 6023static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 6024{ \
6025 gen_op_srli32_T1_64(); \
6026 gen_op_spe_stwwo_64_##suffix(); \
6027} \
b068d6a7 6028static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 6029{ \
6030 gen_op_srli32_T1_64(); \
6031 gen_op_spe_stwwo_le_64_##suffix(); \
6032}
6033#else
6034#define GEN_OP_SPE_STWWE(suffix) \
6035_GEN_OP_SPE_STWWE(suffix); \
6036_GEN_OP_SPE_STWWE_LE(suffix)
6037#endif
6038#if defined(CONFIG_USER_ONLY)
6039GEN_OP_SPE_STWWE(raw);
6040#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 6041GEN_OP_SPE_STWWE(user);
7863667f
JM		 6042GEN_OP_SPE_STWWE(kernel);
6043GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 6044#endif /* defined(CONFIG_USER_ONLY) */
6045GEN_SPEOP_ST(wwe, 2);
6046GEN_SPEOP_ST(wwo, 2);
6047
6048#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 6049static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 6050{ \
6051 gen_op_##op##_##suffix(); \
6052 gen_op_splatw_T1_64(); \
6053}
6054
6055#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 6056static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 6057{ \
6058 gen_op_spe_lh_##suffix(); \
6059 gen_op_sli16_T1_64(); \
6060}
6061
6062#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 6063static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 6064{ \
6065 gen_op_spe_lh_##suffix(); \
6066 gen_op_extsh_T1_64(); \
6067}
6068
6069#if defined(CONFIG_USER_ONLY)
6070GEN_OP_SPE_LHE(raw);
6071GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6072GEN_OP_SPE_LHE(le_raw);
6073GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6074GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6075GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6076GEN_OP_SPE_LHX(raw);
6077GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6078GEN_OP_SPE_LHX(le_raw);
6079GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6080#if defined(TARGET_PPC64)
6081GEN_OP_SPE_LHE(64_raw);
6082GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6083GEN_OP_SPE_LHE(le_64_raw);
6084GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6085GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6086GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6087GEN_OP_SPE_LHX(64_raw);
6088GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6089GEN_OP_SPE_LHX(le_64_raw);
6090GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6091#endif
6092#else
0487d6a8 6093GEN_OP_SPE_LHE(user);
7863667f
JM		 6094GEN_OP_SPE_LHE(kernel);
6095GEN_OP_SPE_LHE(hypv);
0487d6a8 6096GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 6097GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6098GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 6099GEN_OP_SPE_LHE(le_user);
7863667f
JM		 6100GEN_OP_SPE_LHE(le_kernel);
6101GEN_OP_SPE_LHE(le_hypv);
0487d6a8 6102GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 6103GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6104GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 6105GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 6106GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6107GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 6108GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 6109GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6110GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 6111GEN_OP_SPE_LHX(user);
7863667f
JM		 6112GEN_OP_SPE_LHX(kernel);
6113GEN_OP_SPE_LHX(hypv);
0487d6a8 6114GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 6115GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6116GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 6117GEN_OP_SPE_LHX(le_user);
7863667f
JM		 6118GEN_OP_SPE_LHX(le_kernel);
6119GEN_OP_SPE_LHX(le_hypv);
0487d6a8 6120GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 6121GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6122GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 6123#if defined(TARGET_PPC64)
0487d6a8 6124GEN_OP_SPE_LHE(64_user);
7863667f
JM		 6125GEN_OP_SPE_LHE(64_kernel);
6126GEN_OP_SPE_LHE(64_hypv);
0487d6a8 6127GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 6128GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6129GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 6130GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 6131GEN_OP_SPE_LHE(le_64_kernel);
6132GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 6133GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 6134GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6135GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 6136GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 6137GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6138GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 6139GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 6140GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6141GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 6142GEN_OP_SPE_LHX(64_user);
7863667f
JM		 6143GEN_OP_SPE_LHX(64_kernel);
6144GEN_OP_SPE_LHX(64_hypv);
0487d6a8 6145GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 6146GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6147GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 6148GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 6149GEN_OP_SPE_LHX(le_64_kernel);
6150GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 6151GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 6152GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6153GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 6154#endif
6155#endif
6156GEN_SPEOP_LD(hhesplat, 1);
6157GEN_SPEOP_LD(hhousplat, 1);
6158GEN_SPEOP_LD(hhossplat, 1);
6159GEN_SPEOP_LD(wwsplat, 2);
6160GEN_SPEOP_LD(whsplat, 2);
6161
6162GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6163GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6164GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6165GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6166GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6167GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6168GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6169GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6170GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6171GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6172GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6173GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6174GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6175GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6176GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6177GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6178GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6179GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6180
6181/* Multiply and add - TODO */
6182#if 0
6183GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6184GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6185GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6186GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6187GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6188GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6189GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6190GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6191GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6192GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6193GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6194GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6195
6196GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6197GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6198GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6199GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6200GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6201GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6202GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6203GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6204GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6205GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6206GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6207GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6208GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6209GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6210
6211GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6212GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6213GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6214GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6215GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6216GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6217
6218GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6219GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6220GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6221GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6222GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6223GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6224GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6225GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6226GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6227GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6228GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6229GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6230
6231GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6232GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6233GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6234GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6235GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6236
6237GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6238GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6239GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6240GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6241GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6242GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6243GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6244GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6245GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6246GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6247GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6248GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6249
6250GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6251GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6252GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6253GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6254GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6255#endif
6256
6257/*** SPE floating-point extension ***/
6258#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 6259static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6260{ \
f78fb44e 6261 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8 6262 gen_op_##name(); \
f78fb44e 6263 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6264}
6265
6266/* Single precision floating-point vectors operations */
6267/* Arithmetic */
6268GEN_SPEOP_ARITH2(evfsadd);
6269GEN_SPEOP_ARITH2(evfssub);
6270GEN_SPEOP_ARITH2(evfsmul);
6271GEN_SPEOP_ARITH2(evfsdiv);
6272GEN_SPEOP_ARITH1(evfsabs);
6273GEN_SPEOP_ARITH1(evfsnabs);
6274GEN_SPEOP_ARITH1(evfsneg);
6275/* Conversion */
6276GEN_SPEFPUOP_CONV(evfscfui);
6277GEN_SPEFPUOP_CONV(evfscfsi);
6278GEN_SPEFPUOP_CONV(evfscfuf);
6279GEN_SPEFPUOP_CONV(evfscfsf);
6280GEN_SPEFPUOP_CONV(evfsctui);
6281GEN_SPEFPUOP_CONV(evfsctsi);
6282GEN_SPEFPUOP_CONV(evfsctuf);
6283GEN_SPEFPUOP_CONV(evfsctsf);
6284GEN_SPEFPUOP_CONV(evfsctuiz);
6285GEN_SPEFPUOP_CONV(evfsctsiz);
6286/* Comparison */
6287GEN_SPEOP_COMP(evfscmpgt);
6288GEN_SPEOP_COMP(evfscmplt);
6289GEN_SPEOP_COMP(evfscmpeq);
6290GEN_SPEOP_COMP(evfststgt);
6291GEN_SPEOP_COMP(evfststlt);
6292GEN_SPEOP_COMP(evfststeq);
6293
6294/* Opcodes definitions */
6295GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6296GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6297GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6298GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6299GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6300GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6301GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6302GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6303GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6304GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6305GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6306GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6307GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6308GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6309
6310/* Single precision floating-point operations */
6311/* Arithmetic */
6312GEN_SPEOP_ARITH2(efsadd);
6313GEN_SPEOP_ARITH2(efssub);
6314GEN_SPEOP_ARITH2(efsmul);
6315GEN_SPEOP_ARITH2(efsdiv);
6316GEN_SPEOP_ARITH1(efsabs);
6317GEN_SPEOP_ARITH1(efsnabs);
6318GEN_SPEOP_ARITH1(efsneg);
6319/* Conversion */
6320GEN_SPEFPUOP_CONV(efscfui);
6321GEN_SPEFPUOP_CONV(efscfsi);
6322GEN_SPEFPUOP_CONV(efscfuf);
6323GEN_SPEFPUOP_CONV(efscfsf);
6324GEN_SPEFPUOP_CONV(efsctui);
6325GEN_SPEFPUOP_CONV(efsctsi);
6326GEN_SPEFPUOP_CONV(efsctuf);
6327GEN_SPEFPUOP_CONV(efsctsf);
6328GEN_SPEFPUOP_CONV(efsctuiz);
6329GEN_SPEFPUOP_CONV(efsctsiz);
6330GEN_SPEFPUOP_CONV(efscfd);
6331/* Comparison */
6332GEN_SPEOP_COMP(efscmpgt);
6333GEN_SPEOP_COMP(efscmplt);
6334GEN_SPEOP_COMP(efscmpeq);
6335GEN_SPEOP_COMP(efststgt);
6336GEN_SPEOP_COMP(efststlt);
6337GEN_SPEOP_COMP(efststeq);
6338
6339/* Opcodes definitions */
05332d70 6340GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 6341GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6342GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6343GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6344GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6345GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6346GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6347GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6348GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6349GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 6350GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6351GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 6352GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6353GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6354
6355/* Double precision floating-point operations */
6356/* Arithmetic */
6357GEN_SPEOP_ARITH2(efdadd);
6358GEN_SPEOP_ARITH2(efdsub);
6359GEN_SPEOP_ARITH2(efdmul);
6360GEN_SPEOP_ARITH2(efddiv);
6361GEN_SPEOP_ARITH1(efdabs);
6362GEN_SPEOP_ARITH1(efdnabs);
6363GEN_SPEOP_ARITH1(efdneg);
6364/* Conversion */
6365
6366GEN_SPEFPUOP_CONV(efdcfui);
6367GEN_SPEFPUOP_CONV(efdcfsi);
6368GEN_SPEFPUOP_CONV(efdcfuf);
6369GEN_SPEFPUOP_CONV(efdcfsf);
6370GEN_SPEFPUOP_CONV(efdctui);
6371GEN_SPEFPUOP_CONV(efdctsi);
6372GEN_SPEFPUOP_CONV(efdctuf);
6373GEN_SPEFPUOP_CONV(efdctsf);
6374GEN_SPEFPUOP_CONV(efdctuiz);
6375GEN_SPEFPUOP_CONV(efdctsiz);
6376GEN_SPEFPUOP_CONV(efdcfs);
6377GEN_SPEFPUOP_CONV(efdcfuid);
6378GEN_SPEFPUOP_CONV(efdcfsid);
6379GEN_SPEFPUOP_CONV(efdctuidz);
6380GEN_SPEFPUOP_CONV(efdctsidz);
6381/* Comparison */
6382GEN_SPEOP_COMP(efdcmpgt);
6383GEN_SPEOP_COMP(efdcmplt);
6384GEN_SPEOP_COMP(efdcmpeq);
6385GEN_SPEOP_COMP(efdtstgt);
6386GEN_SPEOP_COMP(efdtstlt);
6387GEN_SPEOP_COMP(efdtsteq);
6388
6389/* Opcodes definitions */
6390GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6391GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6392GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6393GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6394GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6395GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6396GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6397GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6398GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6399GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6400GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6401GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6402GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6403GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6404GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6405GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6406
79aceca5
FB		 6407/* End opcode list */
6408GEN_OPCODE_MARK(end);
6409
3fc6c082 6410#include "translate_init.c"
0411a972 6411#include "helper_regs.h"
79aceca5 6412
9a64fbe4 6413/*****************************************************************************/
3fc6c082 6414/* Misc PowerPC helpers */
36081602
JM		 6415void cpu_dump_state (CPUState *env, FILE *f,
6416 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6417 int flags)
79aceca5 6418{
3fc6c082
FB		 6419#define RGPL 4
6420#define RFPL 4
3fc6c082 6421
79aceca5
FB		 6422 int i;
6423
077fc206 6424 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 6425 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 6426 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6427 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 6428#if !defined(NO_TIMER_DUMP)
077fc206 6429 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6430#if !defined(CONFIG_USER_ONLY)
6431 "DECR %08x"
6432#endif
6433 "\n",
077fc206 6434 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6435#if !defined(CONFIG_USER_ONLY)
6436 , cpu_ppc_load_decr(env)
6437#endif
6438 );
077fc206 6439#endif
76a66253 6440 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6441 if ((i & (RGPL - 1)) == 0)
6442 cpu_fprintf(f, "GPR%02d", i);
6b542af7 6443 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 6444 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6445 cpu_fprintf(f, "\n");
76a66253 6446 }
3fc6c082 6447 cpu_fprintf(f, "CR ");
76a66253 6448 for (i = 0; i < 8; i++)
7fe48483
FB		 6449 cpu_fprintf(f, "%01x", env->crf[i]);
6450 cpu_fprintf(f, " [");
76a66253
JM		 6451 for (i = 0; i < 8; i++) {
6452 char a = '-';
6453 if (env->crf[i] & 0x08)
6454 a = 'L';
6455 else if (env->crf[i] & 0x04)
6456 a = 'G';
6457 else if (env->crf[i] & 0x02)
6458 a = 'E';
7fe48483 6459 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6460 }
6b542af7 6461 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 6462 for (i = 0; i < 32; i++) {
6463 if ((i & (RFPL - 1)) == 0)
6464 cpu_fprintf(f, "FPR%02d", i);
26a76461 6465 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6466 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6467 cpu_fprintf(f, "\n");
79aceca5 6468 }
f2e63a42 6469#if !defined(CONFIG_USER_ONLY)
6b542af7 6470 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 6471 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6472#endif
79aceca5 6473
3fc6c082
FB		 6474#undef RGPL
6475#undef RFPL
79aceca5
FB		 6476}
6477
76a66253
JM		 6478void cpu_dump_statistics (CPUState *env, FILE*f,
6479 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6480 int flags)
6481{
6482#if defined(DO_PPC_STATISTICS)
6483 opc_handler_t **t1, **t2, **t3, *handler;
6484 int op1, op2, op3;
6485
6486 t1 = env->opcodes;
6487 for (op1 = 0; op1 < 64; op1++) {
6488 handler = t1[op1];
6489 if (is_indirect_opcode(handler)) {
6490 t2 = ind_table(handler);
6491 for (op2 = 0; op2 < 32; op2++) {
6492 handler = t2[op2];
6493 if (is_indirect_opcode(handler)) {
6494 t3 = ind_table(handler);
6495 for (op3 = 0; op3 < 32; op3++) {
6496 handler = t3[op3];
6497 if (handler->count == 0)
6498 continue;
6499 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6500 "%016llx %lld\n",
6501 op1, op2, op3, op1, (op3 << 5) | op2,
6502 handler->oname,
6503 handler->count, handler->count);
6504 }
6505 } else {
6506 if (handler->count == 0)
6507 continue;
6508 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6509 "%016llx %lld\n",
6510 op1, op2, op1, op2, handler->oname,
6511 handler->count, handler->count);
6512 }
6513 }
6514 } else {
6515 if (handler->count == 0)
6516 continue;
6517 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6518 op1, op1, handler->oname,
6519 handler->count, handler->count);
6520 }
6521 }
6522#endif
6523}
6524
9a64fbe4 6525/*****************************************************************************/
2cfc5f17
TS		 6526static always_inline void gen_intermediate_code_internal (CPUState *env,
6527 TranslationBlock *tb,
6528 int search_pc)
79aceca5 6529{
9fddaa0c 6530 DisasContext ctx, *ctxp = &ctx;
79aceca5 6531 opc_handler_t **table, *handler;
0fa85d43 6532 target_ulong pc_start;
79aceca5 6533 uint16_t *gen_opc_end;
056401ea 6534 int supervisor, little_endian;
79aceca5 6535 int j, lj = -1;
2e70f6ef
PB		 6536 int num_insns;
6537 int max_insns;
79aceca5
FB		 6538
6539 pc_start = tb->pc;
79aceca5 6540 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 6541#if defined(OPTIMIZE_FPRF_UPDATE)
6542 gen_fprf_ptr = gen_fprf_buf;
6543#endif
046d6672 6544 ctx.nip = pc_start;
79aceca5 6545 ctx.tb = tb;
e1833e1f 6546 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6547 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6548 supervisor = env->mmu_idx;
6549#if !defined(CONFIG_USER_ONLY)
2857068e 6550 ctx.supervisor = supervisor;
d9bce9d9 6551#endif
056401ea 6552 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6553#if defined(TARGET_PPC64)
6554 ctx.sf_mode = msr_sf;
056401ea 6555 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6556#else
056401ea 6557 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6558#endif
d63001d1 6559 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6560 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6561 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6562 ctx.spe_enabled = msr_spe;
6563 else
6564 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6565 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6566 ctx.altivec_enabled = msr_vr;
6567 else
6568 ctx.altivec_enabled = 0;
d26bfc9a 6569 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 6570 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 6571 else
8cbcb4fa 6572 ctx.singlestep_enabled = 0;
d26bfc9a 6573 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 6574 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6575 if (unlikely(env->singlestep_enabled))
6576 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 6577#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6578 /* Single step trace mode */
6579 msr_se = 1;
6580#endif
2e70f6ef
PB		 6581 num_insns = 0;
6582 max_insns = tb->cflags & CF_COUNT_MASK;
6583 if (max_insns == 0)
6584 max_insns = CF_COUNT_MASK;
6585
6586 gen_icount_start();
9a64fbe4 6587 /* Set env in case of segfault during code fetch */
e1833e1f 6588 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6589 if (unlikely(env->nb_breakpoints > 0)) {
6590 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6591 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6592 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6593 gen_op_debug();
6594 break;
6595 }
6596 }
6597 }
76a66253 6598 if (unlikely(search_pc)) {
79aceca5
FB		 6599 j = gen_opc_ptr - gen_opc_buf;
6600 if (lj < j) {
6601 lj++;
6602 while (lj < j)
6603 gen_opc_instr_start[lj++] = 0;
046d6672 6604 gen_opc_pc[lj] = ctx.nip;
79aceca5 6605 gen_opc_instr_start[lj] = 1;
2e70f6ef 6606 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 6607 }
6608 }
9fddaa0c
FB		 6609#if defined PPC_DEBUG_DISAS
6610 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6611 fprintf(logfile, "----------------\n");
1b9eb036 6612 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6613 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6614 }
6615#endif
2e70f6ef
PB		 6616 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6617 gen_io_start();
056401ea
JM		 6618 if (unlikely(little_endian)) {
6619 ctx.opcode = bswap32(ldl_code(ctx.nip));
6620 } else {
6621 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6622 }
9fddaa0c
FB		 6623#if defined PPC_DEBUG_DISAS
6624 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6625 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6626 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6627 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6628 }
6629#endif
046d6672 6630 ctx.nip += 4;
3fc6c082 6631 table = env->opcodes;
2e70f6ef 6632 num_insns++;
79aceca5
FB		 6633 handler = table[opc1(ctx.opcode)];
6634 if (is_indirect_opcode(handler)) {
6635 table = ind_table(handler);
6636 handler = table[opc2(ctx.opcode)];
6637 if (is_indirect_opcode(handler)) {
6638 table = ind_table(handler);
6639 handler = table[opc3(ctx.opcode)];
6640 }
6641 }
6642 /* Is opcode *REALLY* valid ? */
76a66253 6643 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6644 if (loglevel != 0) {
76a66253 6645 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 6646 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 6647 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6648 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6649 } else {
6650 printf("invalid/unsupported opcode: "
6b542af7 6651 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 6652 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6653 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6654 }
76a66253
JM		 6655 } else {
6656 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6657 if (loglevel != 0) {
79aceca5 6658 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 6659 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 6660 ctx.opcode & handler->inval, opc1(ctx.opcode),
6661 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6662 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6663 } else {
6664 printf("invalid bits: %08x for opcode: "
6b542af7 6665 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 6666 ctx.opcode & handler->inval, opc1(ctx.opcode),
6667 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6668 ctx.opcode, ctx.nip - 4);
76a66253 6669 }
e1833e1f 6670 GEN_EXCP_INVAL(ctxp);
4b3686fa 6671 break;
79aceca5 6672 }
79aceca5 6673 }
4b3686fa 6674 (*(handler->handler))(&ctx);
76a66253
JM		 6675#if defined(DO_PPC_STATISTICS)
6676 handler->count++;
6677#endif
9a64fbe4 6678 /* Check trace mode exceptions */
8cbcb4fa
AJ		 6679 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6680 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6681 ctx.exception != POWERPC_SYSCALL &&
6682 ctx.exception != POWERPC_EXCP_TRAP &&
6683 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 6684 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 6685 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 6686 (env->singlestep_enabled) ||
6687 num_insns >= max_insns)) {
d26bfc9a
JM		 6688 /* if we reach a page boundary or are single stepping, stop
6689 * generation
6690 */
8dd4983c 6691 break;
76a66253 6692 }
3fc6c082
FB		 6693#if defined (DO_SINGLE_STEP)
6694 break;
6695#endif
6696 }
2e70f6ef
PB		 6697 if (tb->cflags & CF_LAST_IO)
6698 gen_io_end();
e1833e1f 6699 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6700 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6701 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 6702 if (unlikely(env->singlestep_enabled)) {
6703 gen_update_nip(&ctx, ctx.nip);
6704 gen_op_debug();
6705 }
76a66253 6706 /* Generate the return instruction */
57fec1fe 6707 tcg_gen_exit_tb(0);
9a64fbe4 6708 }
2e70f6ef 6709 gen_icount_end(tb, num_insns);
79aceca5 6710 *gen_opc_ptr = INDEX_op_end;
76a66253 6711 if (unlikely(search_pc)) {
9a64fbe4
FB		 6712 j = gen_opc_ptr - gen_opc_buf;
6713 lj++;
6714 while (lj <= j)
6715 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6716 } else {
046d6672 6717 tb->size = ctx.nip - pc_start;
2e70f6ef 6718 tb->icount = num_insns;
9a64fbe4 6719 }
d9bce9d9 6720#if defined(DEBUG_DISAS)
9fddaa0c 6721 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6722 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6723 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6724 }
6725 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6726 int flags;
237c0af0 6727 flags = env->bfd_mach;
056401ea 6728 flags |= little_endian << 16;
0fa85d43 6729 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6730 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6731 fprintf(logfile, "\n");
9fddaa0c 6732 }
79aceca5 6733#endif
79aceca5
FB		 6734}
6735
2cfc5f17 6736void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 6737{
2cfc5f17 6738 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 6739}
6740
2cfc5f17 6741void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 6742{
2cfc5f17 6743 gen_intermediate_code_internal(env, tb, 1);
79aceca5 6744}
d2856f1a
AJ		 6745
6746void gen_pc_load(CPUState *env, TranslationBlock *tb,
6747 unsigned long searched_pc, int pc_pos, void *puc)
6748{
6749 int type, c;
6750 /* for PPC, we need to look at the micro operation to get the
6751 * access type */
6752 env->nip = gen_opc_pc[pc_pos];
6753 c = gen_opc_buf[pc_pos];
6754 switch(c) {
6755#if defined(CONFIG_USER_ONLY)
6756#define CASE3(op)\
6757 case INDEX_op_ ## op ## _raw
6758#else
6759#define CASE3(op)\
6760 case INDEX_op_ ## op ## _user:\
6761 case INDEX_op_ ## op ## _kernel:\
6762 case INDEX_op_ ## op ## _hypv
6763#endif
6764
6765 CASE3(stfd):
6766 CASE3(stfs):
6767 CASE3(lfd):
6768 CASE3(lfs):
6769 type = ACCESS_FLOAT;
6770 break;
6771 CASE3(lwarx):
6772 type = ACCESS_RES;
6773 break;
6774 CASE3(stwcx):
6775 type = ACCESS_RES;
6776 break;
6777 CASE3(eciwx):
6778 CASE3(ecowx):
6779 type = ACCESS_EXT;
6780 break;
6781 default:
6782 type = ACCESS_INT;
6783 break;
6784 }
6785 env->access_type = type;
6786}
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