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target-ppc: be more consistent with temp variables naming
[mirror_qemu.git] / target-ppc / translate.c
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation for qemu: main translation routines.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5 28#include "disas.h"
f10dc08e 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
79aceca5 32
8cbcb4fa
AJ		 33#define CPU_SINGLE_STEP 0x1
34#define CPU_BRANCH_STEP 0x2
35#define GDBSTUB_SINGLE_STEP 0x4
36
a750fc0b 37/* Include definitions for instructions classes and implementations flags */
79aceca5 38//#define DO_SINGLE_STEP
9fddaa0c 39//#define PPC_DEBUG_DISAS
76a66253 40//#define DO_PPC_STATISTICS
7c58044c 41//#define OPTIMIZE_FPRF_UPDATE
79aceca5 42
a750fc0b
JM		 43/*****************************************************************************/
44/* Code translation helpers */
c53be334 45
f78fb44e
AJ		 46/* global register indexes */
47static TCGv cpu_env;
1d542695 48static char cpu_reg_names[10*3 + 22*4 /* GPR */
f78fb44e 49#if !defined(TARGET_PPC64)
1d542695 50 + 10*4 + 22*5 /* SPE GPRh */
f78fb44e 51#endif
a5e26afa 52 + 10*4 + 22*5 /* FPR */
47e4661c
AJ		 53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
f78fb44e
AJ		 55static TCGv cpu_gpr[32];
56#if !defined(TARGET_PPC64)
57static TCGv cpu_gprh[32];
58#endif
a5e26afa 59static TCGv cpu_fpr[32];
1d542695 60static TCGv cpu_avrh[32], cpu_avrl[32];
47e4661c 61static TCGv cpu_crf[8];
bd568f18 62static TCGv cpu_nip;
cfdcd37a
AJ		 63static TCGv cpu_ctr;
64static TCGv cpu_lr;
3d7b417e 65static TCGv cpu_xer;
e1571908 66static TCGv cpu_fpscr;
f78fb44e
AJ		 67
68/* dyngen register indexes */
69static TCGv cpu_T[3];
70#if defined(TARGET_PPC64)
71#define cpu_T64 cpu_T
72#else
73static TCGv cpu_T64[3];
74#endif
a5e26afa 75static TCGv cpu_FT[3];
1d542695 76static TCGv cpu_AVRh[3], cpu_AVRl[3];
2e70f6ef
PB		 77
78#include "gen-icount.h"
79
80void ppc_translate_init(void)
81{
f78fb44e
AJ		 82 int i;
83 char* p;
b2437bf2 84 static int done_init = 0;
f78fb44e 85
2e70f6ef
PB		 86 if (done_init)
87 return;
f78fb44e 88
2e70f6ef 89 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
1c73fe5b
AJ		 90#if TARGET_LONG_BITS > HOST_LONG_BITS
91 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
92 TCG_AREG0, offsetof(CPUState, t0), "T0");
93 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
94 TCG_AREG0, offsetof(CPUState, t1), "T1");
95 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
96 TCG_AREG0, offsetof(CPUState, t2), "T2");
97#else
98 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
99 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
100 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
101#endif
f78fb44e
AJ		 102#if !defined(TARGET_PPC64)
103 cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 104 TCG_AREG0, offsetof(CPUState, t0_64),
f78fb44e
AJ		 105 "T0_64");
106 cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 107 TCG_AREG0, offsetof(CPUState, t1_64),
f78fb44e
AJ		 108 "T1_64");
109 cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
bd7d9a6d 110 TCG_AREG0, offsetof(CPUState, t2_64),
f78fb44e
AJ		 111 "T2_64");
112#endif
a5e26afa
AJ		 113
114 cpu_FT[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
115 offsetof(CPUState, ft0), "FT0");
116 cpu_FT[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
117 offsetof(CPUState, ft1), "FT1");
118 cpu_FT[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
119 offsetof(CPUState, ft2), "FT2");
120
1d542695
AJ		 121 cpu_AVRh[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
122 offsetof(CPUState, avr0.u64[0]), "AVR0H");
123 cpu_AVRl[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
124 offsetof(CPUState, avr0.u64[1]), "AVR0L");
125 cpu_AVRh[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
126 offsetof(CPUState, avr1.u64[0]), "AVR1H");
127 cpu_AVRl[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
128 offsetof(CPUState, avr1.u64[1]), "AVR1L");
129 cpu_AVRh[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
130 offsetof(CPUState, avr2.u64[0]), "AVR2H");
131 cpu_AVRl[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
132 offsetof(CPUState, avr2.u64[1]), "AVR2L");
133
f78fb44e 134 p = cpu_reg_names;
47e4661c
AJ		 135
136 for (i = 0; i < 8; i++) {
137 sprintf(p, "crf%d", i);
138 cpu_crf[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
139 offsetof(CPUState, crf[i]), p);
140 p += 5;
141 }
142
f78fb44e
AJ		 143 for (i = 0; i < 32; i++) {
144 sprintf(p, "r%d", i);
145 cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
146 offsetof(CPUState, gpr[i]), p);
147 p += (i < 10) ? 3 : 4;
148#if !defined(TARGET_PPC64)
149 sprintf(p, "r%dH", i);
150 cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
151 offsetof(CPUState, gprh[i]), p);
152 p += (i < 10) ? 4 : 5;
153#endif
1d542695 154
a5e26afa
AJ		 155 sprintf(p, "fp%d", i);
156 cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
157 offsetof(CPUState, fpr[i]), p);
ec1ac72d 158 p += (i < 10) ? 4 : 5;
a5e26afa 159
1d542695
AJ		 160 sprintf(p, "avr%dH", i);
161 cpu_avrh[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
162 offsetof(CPUState, avr[i].u64[0]), p);
163 p += (i < 10) ? 6 : 7;
ec1ac72d 164
1d542695
AJ		 165 sprintf(p, "avr%dL", i);
166 cpu_avrl[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
167 offsetof(CPUState, avr[i].u64[1]), p);
168 p += (i < 10) ? 6 : 7;
f78fb44e 169 }
f10dc08e 170
bd568f18
AJ		 171 cpu_nip = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
172 offsetof(CPUState, nip), "nip");
173
cfdcd37a
AJ		 174 cpu_ctr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
175 offsetof(CPUState, ctr), "ctr");
176
177 cpu_lr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
178 offsetof(CPUState, lr), "lr");
179
3d7b417e
AJ		 180 cpu_xer = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
181 offsetof(CPUState, xer), "xer");
182
e1571908
AJ		 183 cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
184 offsetof(CPUState, fpscr), "fpscr");
185
f10dc08e
AJ		 186 /* register helpers */
187#undef DEF_HELPER
188#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
189#include "helper.h"
190
2e70f6ef
PB		 191 done_init = 1;
192}
193
7c58044c
JM		 194#if defined(OPTIMIZE_FPRF_UPDATE)
195static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];
196static uint16_t **gen_fprf_ptr;
197#endif
79aceca5 198
79aceca5
FB		 199/* internal defines */
200typedef struct DisasContext {
201 struct TranslationBlock *tb;
0fa85d43 202 target_ulong nip;
79aceca5 203 uint32_t opcode;
9a64fbe4 204 uint32_t exception;
3cc62370
FB		 205 /* Routine used to access memory */
206 int mem_idx;
207 /* Translation flags */
9a64fbe4 208#if !defined(CONFIG_USER_ONLY)
79aceca5 209 int supervisor;
d9bce9d9
JM		 210#endif
211#if defined(TARGET_PPC64)
212 int sf_mode;
9a64fbe4 213#endif
3cc62370 214 int fpu_enabled;
a9d9eb8f 215 int altivec_enabled;
0487d6a8 216 int spe_enabled;
3fc6c082 217 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
ea4e754f 218 int singlestep_enabled;
d63001d1 219 int dcache_line_size;
79aceca5
FB		 220} DisasContext;
221
3fc6c082 222struct opc_handler_t {
79aceca5
FB		 223 /* invalid bits */
224 uint32_t inval;
9a64fbe4 225 /* instruction type */
0487d6a8 226 uint64_t type;
79aceca5
FB		 227 /* handler */
228 void (*handler)(DisasContext *ctx);
a750fc0b 229#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
b55266b5 230 const char *oname;
a750fc0b
JM		 231#endif
232#if defined(DO_PPC_STATISTICS)
76a66253
JM		 233 uint64_t count;
234#endif
3fc6c082 235};
79aceca5 236
7c58044c
JM		 237static always_inline void gen_reset_fpstatus (void)
238{
239#ifdef CONFIG_SOFTFLOAT
240 gen_op_reset_fpstatus();
241#endif
242}
243
244static always_inline void gen_compute_fprf (int set_fprf, int set_rc)
245{
246 if (set_fprf != 0) {
247 /* This case might be optimized later */
248#if defined(OPTIMIZE_FPRF_UPDATE)
249 *gen_fprf_ptr++ = gen_opc_ptr;
250#endif
251 gen_op_compute_fprf(1);
252 if (unlikely(set_rc))
47e4661c 253 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 254 gen_op_float_check_status();
255 } else if (unlikely(set_rc)) {
256 /* We always need to compute fpcc */
257 gen_op_compute_fprf(0);
47e4661c 258 tcg_gen_andi_i32(cpu_crf[1], cpu_T[0], 0xf);
7c58044c
JM		 259 if (set_fprf)
260 gen_op_float_check_status();
261 }
262}
263
264static always_inline void gen_optimize_fprf (void)
265{
266#if defined(OPTIMIZE_FPRF_UPDATE)
267 uint16_t **ptr;
268
269 for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)
270 *ptr = INDEX_op_nop1;
271 gen_fprf_ptr = gen_fprf_buf;
272#endif
273}
274
b068d6a7 275static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
d9bce9d9
JM		 276{
277#if defined(TARGET_PPC64)
278 if (ctx->sf_mode)
bd568f18 279 tcg_gen_movi_tl(cpu_nip, nip);
d9bce9d9
JM		 280 else
281#endif
bd568f18 282 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
d9bce9d9
JM		 283}
284
e1833e1f 285#define GEN_EXCP(ctx, excp, error) \
79aceca5 286do { \
e1833e1f 287 if ((ctx)->exception == POWERPC_EXCP_NONE) { \
d9bce9d9 288 gen_update_nip(ctx, (ctx)->nip); \
9fddaa0c
FB		 289 } \
290 gen_op_raise_exception_err((excp), (error)); \
291 ctx->exception = (excp); \
79aceca5
FB		 292} while (0)
293
e1833e1f
JM		 294#define GEN_EXCP_INVAL(ctx) \
295GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
296 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)
9fddaa0c 297
e1833e1f
JM		 298#define GEN_EXCP_PRIVOPC(ctx) \
299GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
300 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)
9a64fbe4 301
e1833e1f
JM		 302#define GEN_EXCP_PRIVREG(ctx) \
303GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM, \
304 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)
305
306#define GEN_EXCP_NO_FP(ctx) \
307GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)
308
309#define GEN_EXCP_NO_AP(ctx) \
310GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)
9a64fbe4 311
a9d9eb8f
JM		 312#define GEN_EXCP_NO_VR(ctx) \
313GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)
314
f24e5695 315/* Stop translation */
b068d6a7 316static always_inline void GEN_STOP (DisasContext *ctx)
3fc6c082 317{
d9bce9d9 318 gen_update_nip(ctx, ctx->nip);
e1833e1f 319 ctx->exception = POWERPC_EXCP_STOP;
3fc6c082
FB		 320}
321
f24e5695 322/* No need to update nip here, as execution flow will change */
b068d6a7 323static always_inline void GEN_SYNC (DisasContext *ctx)
2be0071f 324{
e1833e1f 325 ctx->exception = POWERPC_EXCP_SYNC;
2be0071f
FB		 326}
327
79aceca5
FB		 328#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329static void gen_##name (DisasContext *ctx); \
330GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
331static void gen_##name (DisasContext *ctx)
332
c7697e1f
JM		 333#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
334static void gen_##name (DisasContext *ctx); \
335GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type); \
336static void gen_##name (DisasContext *ctx)
337
79aceca5
FB		 338typedef struct opcode_t {
339 unsigned char opc1, opc2, opc3;
1235fc06 340#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
18fba28c
FB		 341 unsigned char pad[5];
342#else
343 unsigned char pad[1];
344#endif
79aceca5 345 opc_handler_t handler;
b55266b5 346 const char *oname;
79aceca5
FB		 347} opcode_t;
348
a750fc0b 349/*****************************************************************************/
79aceca5
FB		 350/*** Instruction decoding ***/
351#define EXTRACT_HELPER(name, shift, nb) \
b068d6a7 352static always_inline uint32_t name (uint32_t opcode) \
79aceca5
FB		 353{ \
354 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
355}
356
357#define EXTRACT_SHELPER(name, shift, nb) \
b068d6a7 358static always_inline int32_t name (uint32_t opcode) \
79aceca5 359{ \
18fba28c 360 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
79aceca5
FB		 361}
362
363/* Opcode part 1 */
364EXTRACT_HELPER(opc1, 26, 6);
365/* Opcode part 2 */
366EXTRACT_HELPER(opc2, 1, 5);
367/* Opcode part 3 */
368EXTRACT_HELPER(opc3, 6, 5);
369/* Update Cr0 flags */
370EXTRACT_HELPER(Rc, 0, 1);
371/* Destination */
372EXTRACT_HELPER(rD, 21, 5);
373/* Source */
374EXTRACT_HELPER(rS, 21, 5);
375/* First operand */
376EXTRACT_HELPER(rA, 16, 5);
377/* Second operand */
378EXTRACT_HELPER(rB, 11, 5);
379/* Third operand */
380EXTRACT_HELPER(rC, 6, 5);
381/*** Get CRn ***/
382EXTRACT_HELPER(crfD, 23, 3);
383EXTRACT_HELPER(crfS, 18, 3);
384EXTRACT_HELPER(crbD, 21, 5);
385EXTRACT_HELPER(crbA, 16, 5);
386EXTRACT_HELPER(crbB, 11, 5);
387/* SPR / TBL */
3fc6c082 388EXTRACT_HELPER(_SPR, 11, 10);
b068d6a7 389static always_inline uint32_t SPR (uint32_t opcode)
3fc6c082
FB		 390{
391 uint32_t sprn = _SPR(opcode);
392
393 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
394}
79aceca5
FB		 395/*** Get constants ***/
396EXTRACT_HELPER(IMM, 12, 8);
397/* 16 bits signed immediate value */
398EXTRACT_SHELPER(SIMM, 0, 16);
399/* 16 bits unsigned immediate value */
400EXTRACT_HELPER(UIMM, 0, 16);
401/* Bit count */
402EXTRACT_HELPER(NB, 11, 5);
403/* Shift count */
404EXTRACT_HELPER(SH, 11, 5);
405/* Mask start */
406EXTRACT_HELPER(MB, 6, 5);
407/* Mask end */
408EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 409/* Trap operand */
410EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 411
412EXTRACT_HELPER(CRM, 12, 8);
413EXTRACT_HELPER(FM, 17, 8);
414EXTRACT_HELPER(SR, 16, 4);
e4bb997e 415EXTRACT_HELPER(FPIMM, 12, 4);
fb0eaffc 416
79aceca5
FB		 417/*** Jump target decoding ***/
418/* Displacement */
419EXTRACT_SHELPER(d, 0, 16);
420/* Immediate address */
b068d6a7 421static always_inline target_ulong LI (uint32_t opcode)
79aceca5
FB		 422{
423 return (opcode >> 0) & 0x03FFFFFC;
424}
425
b068d6a7 426static always_inline uint32_t BD (uint32_t opcode)
79aceca5
FB		 427{
428 return (opcode >> 0) & 0xFFFC;
429}
430
431EXTRACT_HELPER(BO, 21, 5);
432EXTRACT_HELPER(BI, 16, 5);
433/* Absolute/relative address */
434EXTRACT_HELPER(AA, 1, 1);
435/* Link */
436EXTRACT_HELPER(LK, 0, 1);
437
438/* Create a mask between <start> and <end> bits */
b068d6a7 439static always_inline target_ulong MASK (uint32_t start, uint32_t end)
79aceca5 440{
76a66253 441 target_ulong ret;
79aceca5 442
76a66253
JM		 443#if defined(TARGET_PPC64)
444 if (likely(start == 0)) {
6f2d8978 445 ret = UINT64_MAX << (63 - end);
76a66253 446 } else if (likely(end == 63)) {
6f2d8978 447 ret = UINT64_MAX >> start;
76a66253
JM		 448 }
449#else
450 if (likely(start == 0)) {
6f2d8978 451 ret = UINT32_MAX << (31 - end);
76a66253 452 } else if (likely(end == 31)) {
6f2d8978 453 ret = UINT32_MAX >> start;
76a66253
JM		 454 }
455#endif
456 else {
457 ret = (((target_ulong)(-1ULL)) >> (start)) ^
458 (((target_ulong)(-1ULL) >> (end)) >> 1);
459 if (unlikely(start > end))
460 return ~ret;
461 }
79aceca5
FB		 462
463 return ret;
464}
465
a750fc0b
JM		 466/*****************************************************************************/
467/* PowerPC Instructions types definitions */
468enum {
1b413d55 469 PPC_NONE = 0x0000000000000000ULL,
12de9a39 470 /* PowerPC base instructions set */
1b413d55
JM		 471 PPC_INSNS_BASE = 0x0000000000000001ULL,
472 /* integer operations instructions */
a750fc0b 473#define PPC_INTEGER PPC_INSNS_BASE
1b413d55 474 /* flow control instructions */
a750fc0b 475#define PPC_FLOW PPC_INSNS_BASE
1b413d55 476 /* virtual memory instructions */
a750fc0b 477#define PPC_MEM PPC_INSNS_BASE
1b413d55 478 /* ld/st with reservation instructions */
a750fc0b 479#define PPC_RES PPC_INSNS_BASE
1b413d55 480 /* spr/msr access instructions */
a750fc0b 481#define PPC_MISC PPC_INSNS_BASE
1b413d55
JM		 482 /* Deprecated instruction sets */
483 /* Original POWER instruction set */
f610349f 484 PPC_POWER = 0x0000000000000002ULL,
1b413d55 485 /* POWER2 instruction set extension */
f610349f 486 PPC_POWER2 = 0x0000000000000004ULL,
1b413d55 487 /* Power RTC support */
f610349f 488 PPC_POWER_RTC = 0x0000000000000008ULL,
1b413d55 489 /* Power-to-PowerPC bridge (601) */
f610349f 490 PPC_POWER_BR = 0x0000000000000010ULL,
1b413d55 491 /* 64 bits PowerPC instruction set */
f610349f 492 PPC_64B = 0x0000000000000020ULL,
1b413d55 493 /* New 64 bits extensions (PowerPC 2.0x) */
f610349f 494 PPC_64BX = 0x0000000000000040ULL,
1b413d55 495 /* 64 bits hypervisor extensions */
f610349f 496 PPC_64H = 0x0000000000000080ULL,
1b413d55 497 /* New wait instruction (PowerPC 2.0x) */
f610349f 498 PPC_WAIT = 0x0000000000000100ULL,
1b413d55 499 /* Time base mftb instruction */
f610349f 500 PPC_MFTB = 0x0000000000000200ULL,
1b413d55
JM		 501
502 /* Fixed-point unit extensions */
503 /* PowerPC 602 specific */
f610349f 504 PPC_602_SPEC = 0x0000000000000400ULL,
05332d70
JM		 505 /* isel instruction */
506 PPC_ISEL = 0x0000000000000800ULL,
507 /* popcntb instruction */
508 PPC_POPCNTB = 0x0000000000001000ULL,
509 /* string load / store */
510 PPC_STRING = 0x0000000000002000ULL,
1b413d55
JM		 511
512 /* Floating-point unit extensions */
513 /* Optional floating point instructions */
514 PPC_FLOAT = 0x0000000000010000ULL,
515 /* New floating-point extensions (PowerPC 2.0x) */
516 PPC_FLOAT_EXT = 0x0000000000020000ULL,
517 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
518 PPC_FLOAT_FRES = 0x0000000000080000ULL,
519 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
520 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
521 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
522 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
523
524 /* Vector/SIMD extensions */
525 /* Altivec support */
526 PPC_ALTIVEC = 0x0000000001000000ULL,
1b413d55 527 /* PowerPC 2.03 SPE extension */
05332d70 528 PPC_SPE = 0x0000000002000000ULL,
1b413d55 529 /* PowerPC 2.03 SPE floating-point extension */
05332d70 530 PPC_SPEFPU = 0x0000000004000000ULL,
1b413d55 531
12de9a39 532 /* Optional memory control instructions */
1b413d55
JM		 533 PPC_MEM_TLBIA = 0x0000000010000000ULL,
534 PPC_MEM_TLBIE = 0x0000000020000000ULL,
535 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
536 /* sync instruction */
537 PPC_MEM_SYNC = 0x0000000080000000ULL,
538 /* eieio instruction */
539 PPC_MEM_EIEIO = 0x0000000100000000ULL,
540
541 /* Cache control instructions */
c8623f2e 542 PPC_CACHE = 0x0000000200000000ULL,
1b413d55 543 /* icbi instruction */
05332d70 544 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1b413d55 545 /* dcbz instruction with fixed cache line size */
05332d70 546 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1b413d55 547 /* dcbz instruction with tunable cache line size */
05332d70 548 PPC_CACHE_DCBZT = 0x0000001000000000ULL,
1b413d55 549 /* dcba instruction */
05332d70
JM		 550 PPC_CACHE_DCBA = 0x0000002000000000ULL,
551 /* Freescale cache locking instructions */
552 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1b413d55
JM		 553
554 /* MMU related extensions */
555 /* external control instructions */
05332d70 556 PPC_EXTERN = 0x0000010000000000ULL,
1b413d55 557 /* segment register access instructions */
05332d70 558 PPC_SEGMENT = 0x0000020000000000ULL,
1b413d55 559 /* PowerPC 6xx TLB management instructions */
05332d70 560 PPC_6xx_TLB = 0x0000040000000000ULL,
1b413d55 561 /* PowerPC 74xx TLB management instructions */
05332d70 562 PPC_74xx_TLB = 0x0000080000000000ULL,
1b413d55 563 /* PowerPC 40x TLB management instructions */
05332d70 564 PPC_40x_TLB = 0x0000100000000000ULL,
1b413d55 565 /* segment register access instructions for PowerPC 64 "bridge" */
05332d70 566 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1b413d55 567 /* SLB management */
05332d70 568 PPC_SLBI = 0x0000400000000000ULL,
1b413d55 569
12de9a39 570 /* Embedded PowerPC dedicated instructions */
05332d70 571 PPC_WRTEE = 0x0001000000000000ULL,
12de9a39 572 /* PowerPC 40x exception model */
05332d70 573 PPC_40x_EXCP = 0x0002000000000000ULL,
12de9a39 574 /* PowerPC 405 Mac instructions */
05332d70 575 PPC_405_MAC = 0x0004000000000000ULL,
12de9a39 576 /* PowerPC 440 specific instructions */
05332d70 577 PPC_440_SPEC = 0x0008000000000000ULL,
12de9a39 578 /* BookE (embedded) PowerPC specification */
05332d70
JM		 579 PPC_BOOKE = 0x0010000000000000ULL,
580 /* mfapidi instruction */
581 PPC_MFAPIDI = 0x0020000000000000ULL,
582 /* tlbiva instruction */
583 PPC_TLBIVA = 0x0040000000000000ULL,
584 /* tlbivax instruction */
585 PPC_TLBIVAX = 0x0080000000000000ULL,
12de9a39 586 /* PowerPC 4xx dedicated instructions */
05332d70 587 PPC_4xx_COMMON = 0x0100000000000000ULL,
12de9a39 588 /* PowerPC 40x ibct instructions */
05332d70 589 PPC_40x_ICBT = 0x0200000000000000ULL,
12de9a39 590 /* rfmci is not implemented in all BookE PowerPC */
05332d70
JM		 591 PPC_RFMCI = 0x0400000000000000ULL,
592 /* rfdi instruction */
593 PPC_RFDI = 0x0800000000000000ULL,
594 /* DCR accesses */
595 PPC_DCR = 0x1000000000000000ULL,
596 /* DCR extended accesse */
597 PPC_DCRX = 0x2000000000000000ULL,
12de9a39 598 /* user-mode DCR access, implemented in PowerPC 460 */
05332d70 599 PPC_DCRUX = 0x4000000000000000ULL,
a750fc0b
JM		 600};
601
602/*****************************************************************************/
603/* PowerPC instructions table */
3fc6c082
FB		 604#if HOST_LONG_BITS == 64
605#define OPC_ALIGN 8
606#else
607#define OPC_ALIGN 4
608#endif
1b039c09 609#if defined(__APPLE__)
d9bce9d9 610#define OPCODES_SECTION \
3fc6c082 611 __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb 612#else
d9bce9d9 613#define OPCODES_SECTION \
3fc6c082 614 __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))
933dc6eb
FB		 615#endif
616
76a66253 617#if defined(DO_PPC_STATISTICS)
79aceca5 618#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
18fba28c 619OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 620 .opc1 = op1, \
621 .opc2 = op2, \
622 .opc3 = op3, \
18fba28c 623 .pad = { 0, }, \
79aceca5
FB		 624 .handler = { \
625 .inval = invl, \
9a64fbe4 626 .type = _typ, \
79aceca5 627 .handler = &gen_##name, \
76a66253 628 .oname = stringify(name), \
79aceca5 629 }, \
3fc6c082 630 .oname = stringify(name), \
79aceca5 631}
c7697e1f
JM		 632#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
633OPCODES_SECTION opcode_t opc_##name = { \
634 .opc1 = op1, \
635 .opc2 = op2, \
636 .opc3 = op3, \
637 .pad = { 0, }, \
638 .handler = { \
639 .inval = invl, \
640 .type = _typ, \
641 .handler = &gen_##name, \
642 .oname = onam, \
643 }, \
644 .oname = onam, \
645}
76a66253
JM		 646#else
647#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
648OPCODES_SECTION opcode_t opc_##name = { \
649 .opc1 = op1, \
650 .opc2 = op2, \
651 .opc3 = op3, \
652 .pad = { 0, }, \
653 .handler = { \
654 .inval = invl, \
655 .type = _typ, \
656 .handler = &gen_##name, \
657 }, \
658 .oname = stringify(name), \
659}
c7697e1f
JM		 660#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ) \
661OPCODES_SECTION opcode_t opc_##name = { \
662 .opc1 = op1, \
663 .opc2 = op2, \
664 .opc3 = op3, \
665 .pad = { 0, }, \
666 .handler = { \
667 .inval = invl, \
668 .type = _typ, \
669 .handler = &gen_##name, \
670 }, \
671 .oname = onam, \
672}
76a66253 673#endif
79aceca5
FB		 674
675#define GEN_OPCODE_MARK(name) \
18fba28c 676OPCODES_SECTION opcode_t opc_##name = { \
79aceca5
FB		 677 .opc1 = 0xFF, \
678 .opc2 = 0xFF, \
679 .opc3 = 0xFF, \
18fba28c 680 .pad = { 0, }, \
79aceca5
FB		 681 .handler = { \
682 .inval = 0x00000000, \
9a64fbe4 683 .type = 0x00, \
79aceca5
FB		 684 .handler = NULL, \
685 }, \
3fc6c082 686 .oname = stringify(name), \
79aceca5
FB		 687}
688
689/* Start opcode list */
690GEN_OPCODE_MARK(start);
691
692/* Invalid instruction */
9a64fbe4
FB		 693GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
694{
e1833e1f 695 GEN_EXCP_INVAL(ctx);
9a64fbe4
FB		 696}
697
79aceca5
FB		 698static opc_handler_t invalid_handler = {
699 .inval = 0xFFFFFFFF,
9a64fbe4 700 .type = PPC_NONE,
79aceca5
FB		 701 .handler = gen_invalid,
702};
703
e1571908
AJ		 704/*** Integer comparison ***/
705
ea363694 706static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
e1571908
AJ		 707{
708 int l1, l2, l3;
709
269f3e95
AJ		 710 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);
711 tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);
e1571908
AJ		 712 tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);
713
714 l1 = gen_new_label();
715 l2 = gen_new_label();
716 l3 = gen_new_label();
717 if (s) {
ea363694
AJ		 718 tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);
719 tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);
e1571908 720 } else {
ea363694
AJ		 721 tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);
722 tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);
e1571908
AJ		 723 }
724 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);
725 tcg_gen_br(l3);
726 gen_set_label(l1);
727 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);
728 tcg_gen_br(l3);
729 gen_set_label(l2);
730 tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);
731 gen_set_label(l3);
732}
733
ea363694 734static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 735{
ea363694
AJ		 736 TCGv t0 = tcg_const_local_tl(arg1);
737 gen_op_cmp(arg0, t0, s, crf);
738 tcg_temp_free(t0);
e1571908
AJ		 739}
740
741#if defined(TARGET_PPC64)
ea363694 742static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
e1571908 743{
ea363694
AJ		 744 TCGv t0, t1;
745 t0 = tcg_temp_local_new(TCG_TYPE_TL);
746 t1 = tcg_temp_local_new(TCG_TYPE_TL);
e1571908 747 if (s) {
ea363694
AJ		 748 tcg_gen_ext32s_tl(t0, arg0);
749 tcg_gen_ext32s_tl(t1, arg1);
e1571908 750 } else {
ea363694
AJ		 751 tcg_gen_ext32u_tl(t0, arg0);
752 tcg_gen_ext32u_tl(t1, arg1);
e1571908 753 }
ea363694
AJ		 754 gen_op_cmp(t0, t1, s, crf);
755 tcg_temp_free(t1);
756 tcg_temp_free(t0);
e1571908
AJ		 757}
758
ea363694 759static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
e1571908 760{
ea363694
AJ		 761 TCGv t0 = tcg_const_local_tl(arg1);
762 gen_op_cmp32(arg0, t0, s, crf);
763 tcg_temp_free(t0);
e1571908
AJ		 764}
765#endif
766
767static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
768{
769#if defined(TARGET_PPC64)
770 if (!(ctx->sf_mode))
771 gen_op_cmpi32(reg, 0, 1, 0);
772 else
773#endif
774 gen_op_cmpi(reg, 0, 1, 0);
775}
776
777/* cmp */
778GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)
779{
780#if defined(TARGET_PPC64)
781 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
782 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
783 1, crfD(ctx->opcode));
784 else
785#endif
786 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
787 1, crfD(ctx->opcode));
788}
789
790/* cmpi */
791GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
792{
793#if defined(TARGET_PPC64)
794 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
795 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
796 1, crfD(ctx->opcode));
797 else
798#endif
799 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
800 1, crfD(ctx->opcode));
801}
802
803/* cmpl */
804GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)
805{
806#if defined(TARGET_PPC64)
807 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
808 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
809 0, crfD(ctx->opcode));
810 else
811#endif
812 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
813 0, crfD(ctx->opcode));
814}
815
816/* cmpli */
817GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
818{
819#if defined(TARGET_PPC64)
820 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
821 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
822 0, crfD(ctx->opcode));
823 else
824#endif
825 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
826 0, crfD(ctx->opcode));
827}
828
829/* isel (PowerPC 2.03 specification) */
830GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
831{
832 int l1, l2;
833 uint32_t bi = rC(ctx->opcode);
834 uint32_t mask;
fea0c503 835 TCGv t0;
e1571908
AJ		 836
837 l1 = gen_new_label();
838 l2 = gen_new_label();
839
840 mask = 1 << (3 - (bi & 0x03));
fea0c503
AJ		 841 t0 = tcg_temp_new(TCG_TYPE_I32);
842 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
843 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
e1571908
AJ		 844 if (rA(ctx->opcode) == 0)
845 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
846 else
847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
848 tcg_gen_br(l2);
849 gen_set_label(l1);
850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
851 gen_set_label(l2);
852}
853
79aceca5 854/*** Integer arithmetic ***/
79aceca5 855
74637406
AJ		 856static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
857{
858 int l1;
859 TCGv t0;
79aceca5 860
74637406
AJ		 861 l1 = gen_new_label();
862 /* Start with XER OV disabled, the most likely case */
863 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
864 t0 = tcg_temp_local_new(TCG_TYPE_TL);
865 tcg_gen_xor_tl(t0, arg0, arg1);
866#if defined(TARGET_PPC64)
867 if (!ctx->sf_mode)
868 tcg_gen_ext32s_tl(t0, t0);
869#endif
870 if (sub)
871 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
872 else
873 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
874 tcg_gen_xor_tl(t0, arg1, arg2);
875#if defined(TARGET_PPC64)
876 if (!ctx->sf_mode)
877 tcg_gen_ext32s_tl(t0, t0);
878#endif
879 if (sub)
880 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
881 else
882 tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l1);
883 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
884 gen_set_label(l1);
885 tcg_temp_free(t0);
79aceca5
FB		 886}
887
74637406
AJ		 888static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
889{
890 int l1 = gen_new_label();
d9bce9d9
JM		 891
892#if defined(TARGET_PPC64)
74637406
AJ		 893 if (!(ctx->sf_mode)) {
894 TCGv t0, t1;
895 t0 = tcg_temp_new(TCG_TYPE_TL);
896 t1 = tcg_temp_new(TCG_TYPE_TL);
d9bce9d9 897
74637406
AJ		 898 tcg_gen_ext32u_tl(t0, arg1);
899 tcg_gen_ext32u_tl(t1, arg2);
900 if (sub) {
901 tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
902 } else {
903 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
904 }
905 } else
906#endif
907 if (sub) {
908 tcg_gen_brcond_tl(TCG_COND_GTU, arg1, arg2, l1);
909 } else {
910 tcg_gen_brcond_tl(TCG_COND_GEU, arg1, arg2, l1);
911 }
912 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
913 gen_set_label(l1);
d9bce9d9
JM		 914}
915
74637406
AJ		 916/* Common add function */
917static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
918 int add_ca, int compute_ca, int compute_ov)
919{
920 TCGv t0, t1;
d9bce9d9 921
74637406
AJ		 922 if ((!compute_ca && !compute_ov) ||
923 (GET_TCGV(ret) != GET_TCGV(arg1) && GET_TCGV(ret) != GET_TCGV(arg2))) {
924 t0 = ret;
925 } else {
926 t0 = tcg_temp_local_new(TCG_TYPE_TL);
927 }
79aceca5 928
74637406
AJ		 929 if (add_ca) {
930 t1 = tcg_temp_local_new(TCG_TYPE_TL);
931 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
932 tcg_gen_shri_tl(t1, t1, XER_CA);
933 }
79aceca5 934
74637406
AJ		 935 if (compute_ca && compute_ov) {
936 /* Start with XER CA and OV disabled, the most likely case */
937 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
938 } else if (compute_ca) {
939 /* Start with XER CA disabled, the most likely case */
940 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
941 } else if (compute_ov) {
942 /* Start with XER OV disabled, the most likely case */
943 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
944 }
79aceca5 945
74637406
AJ		 946 tcg_gen_add_tl(t0, arg1, arg2);
947
948 if (compute_ca) {
949 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
950 }
951 if (add_ca) {
952 tcg_gen_add_tl(t0, t0, t1);
953 gen_op_arith_compute_ca(ctx, t0, t1, 0);
954 tcg_temp_free(t1);
955 }
956 if (compute_ov) {
957 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
958 }
959
960 if (unlikely(Rc(ctx->opcode) != 0))
961 gen_set_Rc0(ctx, t0);
962
963 if (GET_TCGV(t0) != GET_TCGV(ret)) {
964 tcg_gen_mov_tl(ret, t0);
965 tcg_temp_free(t0);
966 }
39dd32ee 967}
74637406
AJ		 968/* Add functions with two operands */
969#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
970GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER) \
971{ \
972 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
973 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
974 add_ca, compute_ca, compute_ov); \
975}
976/* Add functions with one operand and one immediate */
977#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
978 add_ca, compute_ca, compute_ov) \
979GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER) \
980{ \
981 TCGv t0 = tcg_const_local_tl(const_val); \
982 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], t0, \
984 add_ca, compute_ca, compute_ov); \
985 tcg_temp_free(t0); \
986}
987
988/* add add. addo addo. */
989GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
990GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
991/* addc addc. addco addco. */
992GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
993GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
994/* adde adde. addeo addeo. */
995GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
996GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
997/* addme addme. addmeo addmeo. */
998GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
999GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
1000/* addze addze. addzeo addzeo.*/
1001GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
1002GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
1003/* addi */
1004GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1005{
74637406
AJ		 1006 target_long simm = SIMM(ctx->opcode);
1007
1008 if (rA(ctx->opcode) == 0) {
1009 /* li case */
1010 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
1011 } else {
1012 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm);
1013 }
d9bce9d9 1014}
74637406
AJ		 1015/* addic addic.*/
1016static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
1017 int compute_Rc0)
d9bce9d9 1018{
74637406
AJ		 1019 target_long simm = SIMM(ctx->opcode);
1020
1021 /* Start with XER CA and OV disabled, the most likely case */
1022 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1023
1024 if (likely(simm != 0)) {
1025 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1026 tcg_gen_addi_tl(t0, arg1, simm);
1027 gen_op_arith_compute_ca(ctx, t0, arg1, 0);
1028 tcg_gen_mov_tl(ret, t0);
1029 tcg_temp_free(t0);
1030 } else {
1031 tcg_gen_mov_tl(ret, arg1);
1032 }
1033 if (compute_Rc0) {
1034 gen_set_Rc0(ctx, ret);
1035 }
d9bce9d9 1036}
74637406 1037GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1038{
74637406 1039 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1040}
74637406 1041GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1042{
74637406 1043 gen_op_addic(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
d9bce9d9 1044}
74637406
AJ		 1045/* addis */
1046GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1047{
74637406
AJ		 1048 target_long simm = SIMM(ctx->opcode);
1049
1050 if (rA(ctx->opcode) == 0) {
1051 /* lis case */
1052 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
1053 } else {
1054 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], simm << 16);
1055 }
d9bce9d9 1056}
74637406
AJ		 1057
1058static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1059 int sign, int compute_ov)
d9bce9d9 1060{
74637406
AJ		 1061 int l1, l2, l3;
1062 TCGv t0, t1, t2;
1063
1064#if defined(TARGET_PPC64)
1065 t0 = tcg_temp_local_new(TCG_TYPE_I32);
1066 t1 = t0;
1067 t2 = tcg_temp_local_new(TCG_TYPE_I32);
1068 tcg_gen_trunc_i64_i32(t1, arg1);
1069 tcg_gen_trunc_i64_i32(t2, arg2);
1070#else
1071 t0 = ret;
1072 t1 = arg1;
1073 t2 = arg2;
d9bce9d9 1074#endif
74637406
AJ		 1075 l1 = gen_new_label();
1076 l2 = gen_new_label();
1077 tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l1);
1078 if (sign) {
1079 l3 = gen_new_label();
1080 tcg_gen_brcondi_i32(TCG_COND_NE, t2, -1, l3);
1081 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, INT32_MIN, l1);
1082 gen_set_label(l3);
1083 }
1084 if (sign) {
1085 tcg_gen_div_i32(t0, t1, t2);
1086 } else {
1087 tcg_gen_divu_i32(t0, t1, t2);
1088 }
1089 if (compute_ov) {
1090 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1091 }
1092 tcg_gen_br(l2);
1093 gen_set_label(l1);
1094 if (sign) {
1095 tcg_gen_sari_i32(t0, t1, 31);
1096 } else {
1097 tcg_gen_movi_i32(t0, 0);
1098 }
1099 if (compute_ov) {
1100 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1101 }
1102 gen_set_label(l2);
d9bce9d9 1103#if defined(TARGET_PPC64)
74637406
AJ		 1104 tcg_gen_extu_i32_i64(ret, t0);
1105 tcg_temp_free(t0);
d9bce9d9 1106#endif
74637406
AJ		 1107 if (unlikely(Rc(ctx->opcode) != 0))
1108 gen_set_Rc0(ctx, ret);
d9bce9d9 1109}
74637406
AJ		 1110/* Div functions */
1111#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1112GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) \
1113{ \
1114 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1115 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1116 sign, compute_ov); \
1117}
1118/* divwu divwu. divwuo divwuo. */
1119GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
1120GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1121/* divw divw. divwo divwo. */
1122GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1123GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
d9bce9d9 1124#if defined(TARGET_PPC64)
74637406
AJ		 1125static always_inline void gen_op_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1126 int sign, int compute_ov)
d9bce9d9 1127{
74637406
AJ		 1128 int l1, l2, l3;
1129
1130 l1 = gen_new_label();
1131 l2 = gen_new_label();
1132
1133 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1134 if (sign) {
1135 l3 = gen_new_label();
1136 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1137 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1138 gen_set_label(l3);
1139 }
1140 if (sign) {
1141 tcg_gen_div_i64(ret, arg1, arg2);
1142 } else {
1143 tcg_gen_divu_i64(ret, arg1, arg2);
1144 }
1145 if (compute_ov) {
1146 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1147 }
1148 tcg_gen_br(l2);
1149 gen_set_label(l1);
1150 if (sign) {
1151 tcg_gen_sari_i64(ret, arg1, 63);
1152 } else {
1153 tcg_gen_movi_i64(ret, 0);
1154 }
1155 if (compute_ov) {
1156 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1157 }
1158 gen_set_label(l2);
1159 if (unlikely(Rc(ctx->opcode) != 0))
1160 gen_set_Rc0(ctx, ret);
d9bce9d9 1161}
74637406
AJ		 1162#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1163GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1164{ \
1165 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1166 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1167 sign, compute_ov); \
1168}
1169/* divwu divwu. divwuo divwuo. */
1170GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1171GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1172/* divw divw. divwo divwo. */
1173GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1174GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
d9bce9d9 1175#endif
74637406
AJ		 1176
1177/* mulhw mulhw. */
1178GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER)
d9bce9d9 1179{
74637406
AJ		 1180 TCGv t0, t1;
1181
1182 t0 = tcg_temp_new(TCG_TYPE_I64);
1183 t1 = tcg_temp_new(TCG_TYPE_I64);
1184#if defined(TARGET_PPC64)
1185 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1186 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1187 tcg_gen_mul_i64(t0, t0, t1);
1188 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1189#else
1190 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1191 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1192 tcg_gen_mul_i64(t0, t0, t1);
1193 tcg_gen_shri_i64(t0, t0, 32);
1194 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1195#endif
1196 tcg_temp_free(t0);
1197 tcg_temp_free(t1);
1198 if (unlikely(Rc(ctx->opcode) != 0))
1199 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1200}
74637406
AJ		 1201/* mulhwu mulhwu. */
1202GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER)
d9bce9d9 1203{
74637406
AJ		 1204 TCGv t0, t1;
1205
1206 t0 = tcg_temp_new(TCG_TYPE_I64);
1207 t1 = tcg_temp_new(TCG_TYPE_I64);
d9bce9d9 1208#if defined(TARGET_PPC64)
74637406
AJ		 1209 tcg_gen_ext32u_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1210 tcg_gen_ext32u_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1211 tcg_gen_mul_i64(t0, t0, t1);
1212 tcg_gen_shri_i64(cpu_gpr[rD(ctx->opcode)], t0, 32);
1213#else
1214 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1215 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1216 tcg_gen_mul_i64(t0, t0, t1);
1217 tcg_gen_shri_i64(t0, t0, 32);
1218 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1219#endif
1220 tcg_temp_free(t0);
1221 tcg_temp_free(t1);
1222 if (unlikely(Rc(ctx->opcode) != 0))
1223 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1224}
74637406
AJ		 1225/* mullw mullw. */
1226GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER)
d9bce9d9 1227{
74637406
AJ		 1228#if defined(TARGET_PPC64)
1229 TCGv t0, t1;
1230 t0 = tcg_temp_new(TCG_TYPE_TL);
1231 t1 = tcg_temp_new(TCG_TYPE_TL);
1232 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1233 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1234 tcg_gen_mul_tl(t0, t0, t1);
1235 tcg_temp_free(t0);
1236 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], t0);
1237 tcg_temp_free(t1);
1238#else
1239 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1240 cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1241#endif
74637406
AJ		 1242 if (unlikely(Rc(ctx->opcode) != 0))
1243 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1244}
74637406
AJ		 1245/* mullwo mullwo. */
1246GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER)
d9bce9d9 1247{
74637406
AJ		 1248 int l1;
1249 TCGv t0, t1;
1250
1251 t0 = tcg_temp_local_new(TCG_TYPE_I64);
1252 t1 = tcg_temp_local_new(TCG_TYPE_I64);
1253 l1 = gen_new_label();
1254 /* Start with XER OV disabled, the most likely case */
1255 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1256#if defined(TARGET_PPC64)
1257 tcg_gen_ext32s_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1258 tcg_gen_ext32s_i64(t1, cpu_gpr[rB(ctx->opcode)]);
1259#else
1260 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
1261 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
d9bce9d9 1262#endif
74637406
AJ		 1263 tcg_gen_mul_i64(t0, t0, t1);
1264#if defined(TARGET_PPC64)
1265 tcg_gen_ext32s_i64(cpu_gpr[rD(ctx->opcode)], t0);
1266 tcg_gen_brcond_i64(TCG_COND_EQ, t0, cpu_gpr[rD(ctx->opcode)], l1);
1267#else
1268 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t0);
1269 tcg_gen_ext32s_i64(t1, t0);
1270 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
1271#endif
1272 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1273 gen_set_label(l1);
1274 if (unlikely(Rc(ctx->opcode) != 0))
1275 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1276}
74637406
AJ		 1277/* mulli */
1278GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
d9bce9d9 1279{
74637406
AJ		 1280 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1281 SIMM(ctx->opcode));
d9bce9d9
JM		 1282}
1283#if defined(TARGET_PPC64)
74637406
AJ		 1284#define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
1285GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1286{ \
1287 tcg_gen_helper_1_2(helper_##name, cpu_gpr[rD(ctx->opcode)], \
1288 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
1289 if (unlikely(Rc(ctx->opcode) != 0)) \
1290 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
d9bce9d9 1291}
74637406
AJ		 1292/* mulhd mulhd. */
1293GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00);
1294/* mulhdu mulhdu. */
1295GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02);
1296/* mulld mulld. */
1297GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B)
d9bce9d9 1298{
74637406
AJ		 1299 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1300 cpu_gpr[rB(ctx->opcode)]);
1301 if (unlikely(Rc(ctx->opcode) != 0))
1302 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 1303}
74637406
AJ		 1304/* mulldo mulldo. */
1305GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
d9bce9d9 1306#endif
74637406
AJ		 1307
1308/* neg neg. nego nego. */
1309static always_inline void gen_op_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
d9bce9d9 1310{
74637406
AJ		 1311 int l1, l2;
1312
1313 l1 = gen_new_label();
1314 l2 = gen_new_label();
d9bce9d9 1315#if defined(TARGET_PPC64)
74637406
AJ		 1316 if (ctx->sf_mode) {
1317 tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT64_MIN, l1);
1318 } else {
1319 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1320 tcg_gen_ext32s_tl(t0, arg1);
1321 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1322 }
1323#else
1324 tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT32_MIN, l1);
1325#endif
1326 tcg_gen_neg_tl(ret, arg1);
1327 if (ov_check) {
1328 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1329 }
1330 tcg_gen_br(l2);
1331 gen_set_label(l1);
1332 tcg_gen_mov_tl(ret, arg1);
1333 if (ov_check) {
1334 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1335 }
1336 gen_set_label(l2);
1337 if (unlikely(Rc(ctx->opcode) != 0))
1338 gen_set_Rc0(ctx, ret);
1339}
1340GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
d9bce9d9 1341{
74637406 1342 gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
d9bce9d9 1343}
74637406 1344GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
79aceca5 1345{
74637406 1346 gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
79aceca5 1347}
74637406
AJ		 1348
1349/* Common subf function */
1350static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1351 int add_ca, int compute_ca, int compute_ov)
79aceca5 1352{
74637406 1353 TCGv t0, t1;
76a66253 1354
74637406
AJ		 1355 if ((!compute_ca && !compute_ov) ||
1356 (GET_TCGV(ret) != GET_TCGV(arg1) && GET_TCGV(ret) != GET_TCGV(arg2))) {
1357 t0 = ret;
e864cabd 1358 } else {
74637406 1359 t0 = tcg_temp_local_new(TCG_TYPE_TL);
d9bce9d9 1360 }
76a66253 1361
74637406
AJ		 1362 if (add_ca) {
1363 t1 = tcg_temp_local_new(TCG_TYPE_TL);
1364 tcg_gen_andi_tl(t1, cpu_xer, (1 << XER_CA));
1365 tcg_gen_shri_tl(t1, t1, XER_CA);
d9bce9d9 1366 }
79aceca5 1367
74637406
AJ		 1368 if (compute_ca && compute_ov) {
1369 /* Start with XER CA and OV disabled, the most likely case */
1370 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~((1 << XER_CA) | (1 << XER_OV)));
1371 } else if (compute_ca) {
1372 /* Start with XER CA disabled, the most likely case */
1373 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1374 } else if (compute_ov) {
1375 /* Start with XER OV disabled, the most likely case */
1376 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1377 }
1378
1379 if (add_ca) {
1380 tcg_gen_not_tl(t0, arg1);
1381 tcg_gen_add_tl(t0, t0, arg2);
1382 gen_op_arith_compute_ca(ctx, t0, arg2, 0);
1383 tcg_gen_add_tl(t0, t0, t1);
1384 gen_op_arith_compute_ca(ctx, t0, t1, 0);
1385 tcg_temp_free(t1);
79aceca5 1386 } else {
74637406
AJ		 1387 tcg_gen_sub_tl(t0, arg2, arg1);
1388 if (compute_ca) {
1389 gen_op_arith_compute_ca(ctx, t0, arg2, 1);
1390 }
1391 }
1392 if (compute_ov) {
1393 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1394 }
1395
1396 if (unlikely(Rc(ctx->opcode) != 0))
1397 gen_set_Rc0(ctx, t0);
1398
1399 if (GET_TCGV(t0) != GET_TCGV(ret)) {
1400 tcg_gen_mov_tl(ret, t0);
1401 tcg_temp_free(t0);
79aceca5 1402 }
79aceca5 1403}
74637406
AJ		 1404/* Sub functions with Two operands functions */
1405#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1406GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER) \
1407{ \
1408 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1409 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1410 add_ca, compute_ca, compute_ov); \
1411}
1412/* Sub functions with one operand and one immediate */
1413#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1414 add_ca, compute_ca, compute_ov) \
1415GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER) \
1416{ \
1417 TCGv t0 = tcg_const_local_tl(const_val); \
1418 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1419 cpu_gpr[rA(ctx->opcode)], t0, \
1420 add_ca, compute_ca, compute_ov); \
1421 tcg_temp_free(t0); \
1422}
1423/* subf subf. subfo subfo. */
1424GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1425GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1426/* subfc subfc. subfco subfco. */
1427GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1428GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1429/* subfe subfe. subfeo subfo. */
1430GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1431GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1432/* subfme subfme. subfmeo subfmeo. */
1433GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1434GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1435/* subfze subfze. subfzeo subfzeo.*/
1436GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1437GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
79aceca5
FB		 1438/* subfic */
1439GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1440{
74637406
AJ		 1441 /* Start with XER CA and OV disabled, the most likely case */
1442 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
1443 TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1444 TCGv t1 = tcg_const_local_tl(SIMM(ctx->opcode));
1445 tcg_gen_sub_tl(t0, t1, cpu_gpr[rA(ctx->opcode)]);
1446 gen_op_arith_compute_ca(ctx, t0, t1, 1);
1447 tcg_temp_free(t1);
1448 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
1449 tcg_temp_free(t0);
79aceca5
FB		 1450}
1451
79aceca5 1452/*** Integer logical ***/
26d67362
AJ		 1453#define GEN_LOGICAL2(name, tcg_op, opc, type) \
1454GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) \
79aceca5 1455{ \
26d67362
AJ		 1456 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1457 cpu_gpr[rB(ctx->opcode)]); \
76a66253 1458 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1459 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5 1460}
79aceca5 1461
26d67362 1462#define GEN_LOGICAL1(name, tcg_op, opc, type) \
d9bce9d9 1463GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) \
79aceca5 1464{ \
26d67362 1465 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
76a66253 1466 if (unlikely(Rc(ctx->opcode) != 0)) \
26d67362 1467 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
79aceca5
FB		 1468}
1469
1470/* and & and. */
26d67362 1471GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
79aceca5 1472/* andc & andc. */
26d67362 1473GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
79aceca5 1474/* andi. */
c7697e1f 1475GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1476{
26d67362
AJ		 1477 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1478 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1479}
1480/* andis. */
c7697e1f 1481GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
79aceca5 1482{
26d67362
AJ		 1483 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5 1485}
79aceca5 1486/* cntlzw */
26d67362
AJ		 1487GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER)
1488{
1489 tcg_gen_helper_1_1(helper_cntlzw, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1490 if (unlikely(Rc(ctx->opcode) != 0))
2e31f5d3 1491 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
26d67362 1492}
79aceca5 1493/* eqv & eqv. */
26d67362 1494GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
79aceca5 1495/* extsb & extsb. */
26d67362 1496GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
79aceca5 1497/* extsh & extsh. */
26d67362 1498GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
79aceca5 1499/* nand & nand. */
26d67362 1500GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
79aceca5 1501/* nor & nor. */
26d67362 1502GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
79aceca5 1503/* or & or. */
9a64fbe4
FB		 1504GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
1505{
76a66253
JM		 1506 int rs, ra, rb;
1507
1508 rs = rS(ctx->opcode);
1509 ra = rA(ctx->opcode);
1510 rb = rB(ctx->opcode);
1511 /* Optimisation for mr. ri case */
1512 if (rs != ra || rs != rb) {
26d67362
AJ		 1513 if (rs != rb)
1514 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1515 else
1516 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
76a66253 1517 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1518 gen_set_Rc0(ctx, cpu_gpr[ra]);
76a66253 1519 } else if (unlikely(Rc(ctx->opcode) != 0)) {
26d67362 1520 gen_set_Rc0(ctx, cpu_gpr[rs]);
c80f84e3
JM		 1521#if defined(TARGET_PPC64)
1522 } else {
26d67362
AJ		 1523 int prio = 0;
1524
c80f84e3
JM		 1525 switch (rs) {
1526 case 1:
1527 /* Set process priority to low */
26d67362 1528 prio = 2;
c80f84e3
JM		 1529 break;
1530 case 6:
1531 /* Set process priority to medium-low */
26d67362 1532 prio = 3;
c80f84e3
JM		 1533 break;
1534 case 2:
1535 /* Set process priority to normal */
26d67362 1536 prio = 4;
c80f84e3 1537 break;
be147d08
JM		 1538#if !defined(CONFIG_USER_ONLY)
1539 case 31:
1540 if (ctx->supervisor > 0) {
1541 /* Set process priority to very low */
26d67362 1542 prio = 1;
be147d08
JM		 1543 }
1544 break;
1545 case 5:
1546 if (ctx->supervisor > 0) {
1547 /* Set process priority to medium-hight */
26d67362 1548 prio = 5;
be147d08
JM		 1549 }
1550 break;
1551 case 3:
1552 if (ctx->supervisor > 0) {
1553 /* Set process priority to high */
26d67362 1554 prio = 6;
be147d08
JM		 1555 }
1556 break;
be147d08
JM		 1557 case 7:
1558 if (ctx->supervisor > 1) {
1559 /* Set process priority to very high */
26d67362 1560 prio = 7;
be147d08
JM		 1561 }
1562 break;
be147d08 1563#endif
c80f84e3
JM		 1564 default:
1565 /* nop */
1566 break;
1567 }
26d67362 1568 if (prio) {
ea363694
AJ		 1569 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1570 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1571 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1572 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1573 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, spr[SPR_PPR]));
1574 tcg_temp_free(t0);
26d67362 1575 }
c80f84e3 1576#endif
9a64fbe4 1577 }
9a64fbe4 1578}
79aceca5 1579/* orc & orc. */
26d67362 1580GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
79aceca5 1581/* xor & xor. */
9a64fbe4
FB		 1582GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
1583{
9a64fbe4 1584 /* Optimisation for "set to zero" case */
26d67362 1585 if (rS(ctx->opcode) != rB(ctx->opcode))
312179c4 1586 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
26d67362
AJ		 1587 else
1588 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
76a66253 1589 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 1590 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
9a64fbe4 1591}
79aceca5
FB		 1592/* ori */
1593GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1594{
76a66253 1595 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1596
9a64fbe4
FB		 1597 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1598 /* NOP */
76a66253 1599 /* XXX: should handle special NOPs for POWER series */
9a64fbe4 1600 return;
76a66253 1601 }
26d67362 1602 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5
FB		 1603}
1604/* oris */
1605GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1606{
76a66253 1607 target_ulong uimm = UIMM(ctx->opcode);
79aceca5 1608
9a64fbe4
FB		 1609 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1610 /* NOP */
1611 return;
76a66253 1612 }
26d67362 1613 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5
FB		 1614}
1615/* xori */
1616GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1617{
76a66253 1618 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1619
1620 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1621 /* NOP */
1622 return;
1623 }
26d67362 1624 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
79aceca5 1625}
79aceca5
FB		 1626/* xoris */
1627GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1628{
76a66253 1629 target_ulong uimm = UIMM(ctx->opcode);
9a64fbe4
FB		 1630
1631 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1632 /* NOP */
1633 return;
1634 }
26d67362 1635 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
79aceca5 1636}
d9bce9d9 1637/* popcntb : PowerPC 2.03 specification */
05332d70 1638GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
d9bce9d9 1639{
d9bce9d9
JM		 1640#if defined(TARGET_PPC64)
1641 if (ctx->sf_mode)
26d67362 1642 tcg_gen_helper_1_1(helper_popcntb_64, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1643 else
1644#endif
26d67362 1645 tcg_gen_helper_1_1(helper_popcntb, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
d9bce9d9
JM		 1646}
1647
1648#if defined(TARGET_PPC64)
1649/* extsw & extsw. */
26d67362 1650GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
d9bce9d9 1651/* cntlzd */
26d67362
AJ		 1652GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B)
1653{
1654 tcg_gen_helper_1_1(helper_cntlzd, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1655 if (unlikely(Rc(ctx->opcode) != 0))
1656 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1657}
d9bce9d9
JM		 1658#endif
1659
79aceca5
FB		 1660/*** Integer rotate ***/
1661/* rlwimi & rlwimi. */
1662GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1663{
76a66253 1664 uint32_t mb, me, sh;
79aceca5
FB		 1665
1666 mb = MB(ctx->opcode);
1667 me = ME(ctx->opcode);
76a66253 1668 sh = SH(ctx->opcode);
d03ef511
AJ		 1669 if (likely(sh == 0 && mb == 0 && me == 31)) {
1670 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1671 } else {
1672 TCGv t0, t1;
1673 target_ulong mask;
1674
1675 t0 = tcg_temp_new(TCG_TYPE_TL);
1676 t1 = tcg_temp_new(TCG_TYPE_TL);
1677 if (likely(sh == 0)) {
1678 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1679 } else {
1680 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1681 tcg_gen_shli_tl(t0, t1, sh);
1682 tcg_gen_shri_tl(t1, t1, 32 - sh);
1683 tcg_gen_or_tl(t0, t0, t1);
76a66253 1684 }
76a66253 1685#if defined(TARGET_PPC64)
d03ef511
AJ		 1686 mb += 32;
1687 me += 32;
76a66253 1688#endif
d03ef511
AJ		 1689 mask = MASK(mb, me);
1690 tcg_gen_andi_tl(t0, t0, mask);
1691 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1692 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1693 tcg_temp_free(t0);
1694 tcg_temp_free(t1);
1695 }
76a66253 1696 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1698}
1699/* rlwinm & rlwinm. */
1700GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1701{
1702 uint32_t mb, me, sh;
3b46e624 1703
79aceca5
FB		 1704 sh = SH(ctx->opcode);
1705 mb = MB(ctx->opcode);
1706 me = ME(ctx->opcode);
d03ef511
AJ		 1707
1708 if (likely(mb == 0 && me == (31 - sh))) {
1709 if (likely(sh == 0)) {
1710 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1711 } else {
1712 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1713 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1714 tcg_gen_shli_tl(t0, t0, sh);
1715 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1716 tcg_temp_free(t0);
79aceca5 1717 }
d03ef511
AJ		 1718 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1719 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1720 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1721 tcg_gen_shri_tl(t0, t0, mb);
1722 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1723 tcg_temp_free(t0);
1724 } else {
1725 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1726 if (likely(sh != 0)) {
1727 TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
1728 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1729 tcg_gen_shli_tl(t1, t0, sh);
1730 tcg_gen_shri_tl(t0, t0, 32 - sh);
1731 tcg_gen_or_tl(t0, t0, t1);
1732 tcg_temp_free(t1);
1733 } else {
1734 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
79aceca5 1735 }
76a66253 1736#if defined(TARGET_PPC64)
d03ef511
AJ		 1737 mb += 32;
1738 me += 32;
76a66253 1739#endif
d03ef511
AJ		 1740 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1741 tcg_temp_free(t0);
1742 }
76a66253 1743 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1744 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1745}
1746/* rlwnm & rlwnm. */
1747GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1748{
1749 uint32_t mb, me;
d03ef511 1750 TCGv t0, t1, t2, t3;
79aceca5
FB		 1751
1752 mb = MB(ctx->opcode);
1753 me = ME(ctx->opcode);
d03ef511
AJ		 1754 t0 = tcg_temp_new(TCG_TYPE_TL);
1755 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1756 t1 = tcg_temp_new(TCG_TYPE_TL);
1757 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
1758 t2 = tcg_temp_new(TCG_TYPE_TL);
1759 tcg_gen_shl_tl(t2, t1, t0);
1760 t3 = tcg_const_tl(32);
1761 tcg_gen_sub_tl(t0, t3, t0);
1762 tcg_temp_free(t3);
1763 tcg_gen_shr_tl(t1, t1, t0);
1764 tcg_temp_free(t0);
1765 tcg_gen_or_tl(t2, t2, t1);
1766 tcg_temp_free(t1);
76a66253
JM		 1767 if (unlikely(mb != 0 || me != 31)) {
1768#if defined(TARGET_PPC64)
1769 mb += 32;
1770 me += 32;
1771#endif
d03ef511
AJ		 1772 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t2, MASK(mb, me));
1773 } else {
1774 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t2);
79aceca5 1775 }
d03ef511 1776 tcg_temp_free(t2);
76a66253 1777 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1778 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 1779}
1780
d9bce9d9
JM		 1781#if defined(TARGET_PPC64)
1782#define GEN_PPC64_R2(name, opc1, opc2) \
c7697e1f 1783GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1784{ \
1785 gen_##name(ctx, 0); \
1786} \
c7697e1f
JM		 1787GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1788 PPC_64B) \
d9bce9d9
JM		 1789{ \
1790 gen_##name(ctx, 1); \
1791}
1792#define GEN_PPC64_R4(name, opc1, opc2) \
c7697e1f 1793GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B) \
d9bce9d9
JM		 1794{ \
1795 gen_##name(ctx, 0, 0); \
1796} \
c7697e1f
JM		 1797GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
1798 PPC_64B) \
d9bce9d9
JM		 1799{ \
1800 gen_##name(ctx, 0, 1); \
1801} \
c7697e1f
JM		 1802GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
1803 PPC_64B) \
d9bce9d9
JM		 1804{ \
1805 gen_##name(ctx, 1, 0); \
1806} \
c7697e1f
JM		 1807GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
1808 PPC_64B) \
d9bce9d9
JM		 1809{ \
1810 gen_##name(ctx, 1, 1); \
1811}
51789c41 1812
b068d6a7
JM		 1813static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
1814 uint32_t me, uint32_t sh)
51789c41 1815{
d03ef511
AJ		 1816 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1817 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1818 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1819 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1820 } else {
1821 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1822 if (likely(sh != 0)) {
1823 TCGv t1 = tcg_temp_new(TCG_TYPE_TL);
1824 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1825 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
1826 tcg_gen_or_tl(t0, t0, t1);
1827 tcg_temp_free(t1);
1828 } else {
1829 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
51789c41 1830 }
d03ef511
AJ		 1831 if (likely(mb == 0 && me == 63)) {
1832 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1833 } else {
1834 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
51789c41 1835 }
d03ef511 1836 tcg_temp_free(t0);
51789c41 1837 }
51789c41 1838 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1839 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
51789c41 1840}
d9bce9d9 1841/* rldicl - rldicl. */
b068d6a7 1842static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1843{
51789c41 1844 uint32_t sh, mb;
d9bce9d9 1845
9d53c753
JM		 1846 sh = SH(ctx->opcode) | (shn << 5);
1847 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1848 gen_rldinm(ctx, mb, 63, sh);
d9bce9d9 1849}
51789c41 1850GEN_PPC64_R4(rldicl, 0x1E, 0x00);
d9bce9d9 1851/* rldicr - rldicr. */
b068d6a7 1852static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
d9bce9d9 1853{
51789c41 1854 uint32_t sh, me;
d9bce9d9 1855
9d53c753
JM		 1856 sh = SH(ctx->opcode) | (shn << 5);
1857 me = MB(ctx->opcode) | (men << 5);
51789c41 1858 gen_rldinm(ctx, 0, me, sh);
d9bce9d9 1859}
51789c41 1860GEN_PPC64_R4(rldicr, 0x1E, 0x02);
d9bce9d9 1861/* rldic - rldic. */
b068d6a7 1862static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1863{
51789c41 1864 uint32_t sh, mb;
d9bce9d9 1865
9d53c753
JM		 1866 sh = SH(ctx->opcode) | (shn << 5);
1867 mb = MB(ctx->opcode) | (mbn << 5);
51789c41
JM		 1868 gen_rldinm(ctx, mb, 63 - sh, sh);
1869}
1870GEN_PPC64_R4(rldic, 0x1E, 0x04);
1871
b068d6a7
JM		 1872static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
1873 uint32_t me)
51789c41 1874{
d03ef511
AJ		 1875 TCGv t0, t1, t2;
1876
1877 mb = MB(ctx->opcode);
1878 me = ME(ctx->opcode);
1879 t0 = tcg_temp_new(TCG_TYPE_TL);
1880 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1881 t1 = tcg_temp_new(TCG_TYPE_TL);
1882 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t0);
1883 t2 = tcg_const_tl(32);
1884 tcg_gen_sub_tl(t0, t2, t0);
1885 tcg_temp_free(t2);
1886 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1887 tcg_gen_or_tl(t1, t1, t0);
1888 tcg_temp_free(t0);
51789c41 1889 if (unlikely(mb != 0 || me != 63)) {
d03ef511
AJ		 1890 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t1, MASK(mb, me));
1891 } else
1892 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
1893 tcg_temp_free(t1);
51789c41 1894 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1895 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1896}
51789c41 1897
d9bce9d9 1898/* rldcl - rldcl. */
b068d6a7 1899static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
d9bce9d9 1900{
51789c41 1901 uint32_t mb;
d9bce9d9 1902
9d53c753 1903 mb = MB(ctx->opcode) | (mbn << 5);
51789c41 1904 gen_rldnm(ctx, mb, 63);
d9bce9d9 1905}
36081602 1906GEN_PPC64_R2(rldcl, 0x1E, 0x08);
d9bce9d9 1907/* rldcr - rldcr. */
b068d6a7 1908static always_inline void gen_rldcr (DisasContext *ctx, int men)
d9bce9d9 1909{
51789c41 1910 uint32_t me;
d9bce9d9 1911
9d53c753 1912 me = MB(ctx->opcode) | (men << 5);
51789c41 1913 gen_rldnm(ctx, 0, me);
d9bce9d9 1914}
36081602 1915GEN_PPC64_R2(rldcr, 0x1E, 0x09);
d9bce9d9 1916/* rldimi - rldimi. */
b068d6a7 1917static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
d9bce9d9 1918{
271a916e 1919 uint32_t sh, mb, me;
d9bce9d9 1920
9d53c753
JM		 1921 sh = SH(ctx->opcode) | (shn << 5);
1922 mb = MB(ctx->opcode) | (mbn << 5);
271a916e 1923 me = 63 - sh;
d03ef511
AJ		 1924 if (unlikely(sh == 0 && mb == 0)) {
1925 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1926 } else {
1927 TCGv t0, t1;
1928 target_ulong mask;
1929
1930 t0 = tcg_temp_new(TCG_TYPE_TL);
1931 t1 = tcg_temp_new(TCG_TYPE_TL);
1932 if (likely(sh == 0)) {
1933 tcg_gen_mov_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1934 } else {
1935 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1936 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 64 - sh);
1937 tcg_gen_or_tl(t0, t0, t1);
51789c41 1938 }
d03ef511
AJ		 1939 mask = MASK(mb, me);
1940 tcg_gen_andi_tl(t0, t0, mask);
1941 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1942 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1943 tcg_temp_free(t0);
1944 tcg_temp_free(t1);
51789c41 1945 }
51789c41 1946 if (unlikely(Rc(ctx->opcode) != 0))
d03ef511 1947 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 1948}
36081602 1949GEN_PPC64_R4(rldimi, 0x1E, 0x06);
d9bce9d9
JM		 1950#endif
1951
79aceca5
FB		 1952/*** Integer shift ***/
1953/* slw & slw. */
26d67362
AJ		 1954GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER)
1955{
fea0c503 1956 TCGv t0;
26d67362
AJ		 1957 int l1, l2;
1958 l1 = gen_new_label();
1959 l2 = gen_new_label();
1960
fea0c503
AJ		 1961 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1962 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
1963 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
26d67362
AJ		 1964 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1965 tcg_gen_br(l2);
1966 gen_set_label(l1);
fea0c503
AJ		 1967 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1968 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362
AJ		 1969 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1970 gen_set_label(l2);
fea0c503 1971 tcg_temp_free(t0);
26d67362
AJ		 1972 if (unlikely(Rc(ctx->opcode) != 0))
1973 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1974}
79aceca5 1975/* sraw & sraw. */
26d67362
AJ		 1976GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER)
1977{
1978 tcg_gen_helper_1_2(helper_sraw, cpu_gpr[rA(ctx->opcode)],
1979 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1980 if (unlikely(Rc(ctx->opcode) != 0))
1981 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1982}
79aceca5
FB		 1983/* srawi & srawi. */
1984GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
1985{
26d67362
AJ		 1986 int sh = SH(ctx->opcode);
1987 if (sh != 0) {
1988 int l1, l2;
fea0c503 1989 TCGv t0;
26d67362
AJ		 1990 l1 = gen_new_label();
1991 l2 = gen_new_label();
fea0c503
AJ		 1992 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1993 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1994 tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l1);
1995 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
1996 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 1997 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 1998 tcg_gen_br(l2);
1999 gen_set_label(l1);
269f3e95 2000 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362 2001 gen_set_label(l2);
fea0c503
AJ		 2002 tcg_gen_ext32s_tl(t0, cpu_gpr[rS(ctx->opcode)]);
2003 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], t0, sh);
2004 tcg_temp_free(t0);
26d67362
AJ		 2005 } else {
2006 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2007 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2008 }
76a66253 2009 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2010 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
79aceca5
FB		 2011}
2012/* srw & srw. */
26d67362
AJ		 2013GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER)
2014{
fea0c503 2015 TCGv t0, t1;
26d67362
AJ		 2016 int l1, l2;
2017 l1 = gen_new_label();
2018 l2 = gen_new_label();
d9bce9d9 2019
fea0c503
AJ		 2020 t0 = tcg_temp_local_new(TCG_TYPE_TL);
2021 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
2022 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
26d67362
AJ		 2023 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2024 tcg_gen_br(l2);
2025 gen_set_label(l1);
fea0c503
AJ		 2026 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
2027 t1 = tcg_temp_new(TCG_TYPE_TL);
2028 tcg_gen_ext32u_tl(t1, cpu_gpr[rS(ctx->opcode)]);
2029 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t1, t0);
2030 tcg_temp_free(t1);
26d67362 2031 gen_set_label(l2);
fea0c503 2032 tcg_temp_free(t0);
26d67362
AJ		 2033 if (unlikely(Rc(ctx->opcode) != 0))
2034 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2035}
d9bce9d9
JM		 2036#if defined(TARGET_PPC64)
2037/* sld & sld. */
26d67362
AJ		 2038GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B)
2039{
fea0c503 2040 TCGv t0;
26d67362
AJ		 2041 int l1, l2;
2042 l1 = gen_new_label();
2043 l2 = gen_new_label();
2044
fea0c503
AJ		 2045 t0 = tcg_temp_local_new(TCG_TYPE_TL);
2046 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x40);
2047 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
26d67362
AJ		 2048 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2049 tcg_gen_br(l2);
2050 gen_set_label(l1);
fea0c503
AJ		 2051 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2052 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2053 gen_set_label(l2);
fea0c503 2054 tcg_temp_free(t0);
26d67362
AJ		 2055 if (unlikely(Rc(ctx->opcode) != 0))
2056 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2057}
d9bce9d9 2058/* srad & srad. */
26d67362
AJ		 2059GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B)
2060{
2061 tcg_gen_helper_1_2(helper_srad, cpu_gpr[rA(ctx->opcode)],
2062 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2063 if (unlikely(Rc(ctx->opcode) != 0))
2064 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2065}
d9bce9d9 2066/* sradi & sradi. */
b068d6a7 2067static always_inline void gen_sradi (DisasContext *ctx, int n)
d9bce9d9 2068{
26d67362 2069 int sh = SH(ctx->opcode) + (n << 5);
d9bce9d9 2070 if (sh != 0) {
26d67362 2071 int l1, l2;
fea0c503 2072 TCGv t0;
26d67362
AJ		 2073 l1 = gen_new_label();
2074 l2 = gen_new_label();
2075 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
fea0c503
AJ		 2076 t0 = tcg_temp_new(TCG_TYPE_TL);
2077 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1ULL << sh) - 1);
2078 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
269f3e95 2079 tcg_gen_ori_tl(cpu_xer, cpu_xer, 1 << XER_CA);
26d67362
AJ		 2080 tcg_gen_br(l2);
2081 gen_set_label(l1);
269f3e95 2082 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
26d67362
AJ		 2083 gen_set_label(l2);
2084 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
2085 } else {
2086 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
269f3e95 2087 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_CA));
d9bce9d9 2088 }
d9bce9d9 2089 if (unlikely(Rc(ctx->opcode) != 0))
26d67362 2090 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
d9bce9d9 2091}
c7697e1f 2092GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2093{
2094 gen_sradi(ctx, 0);
2095}
c7697e1f 2096GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B)
d9bce9d9
JM		 2097{
2098 gen_sradi(ctx, 1);
2099}
2100/* srd & srd. */
26d67362
AJ		 2101GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B)
2102{
fea0c503 2103 TCGv t0;
26d67362
AJ		 2104 int l1, l2;
2105 l1 = gen_new_label();
2106 l2 = gen_new_label();
2107
fea0c503
AJ		 2108 t0 = tcg_temp_local_new(TCG_TYPE_TL);
2109 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x40);
2110 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
26d67362
AJ		 2111 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
2112 tcg_gen_br(l2);
2113 gen_set_label(l1);
fea0c503
AJ		 2114 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x7f);
2115 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t0);
26d67362 2116 gen_set_label(l2);
fea0c503 2117 tcg_temp_free(t0);
26d67362
AJ		 2118 if (unlikely(Rc(ctx->opcode) != 0))
2119 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2120}
d9bce9d9 2121#endif
79aceca5
FB		 2122
2123/*** Floating-Point arithmetic ***/
7c58044c 2124#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
a750fc0b 2125GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type) \
9a64fbe4 2126{ \
76a66253 2127 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2128 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2129 return; \
2130 } \
a5e26afa
AJ		 2131 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2132 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
2133 tcg_gen_mov_i64(cpu_FT[2], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2134 gen_reset_fpstatus(); \
4ecc3190
FB		 2135 gen_op_f##op(); \
2136 if (isfloat) { \
2137 gen_op_frsp(); \
2138 } \
a5e26afa 2139 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2140 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4
FB		 2141}
2142
7c58044c
JM		 2143#define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2144_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2145_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
9a64fbe4 2146
7c58044c
JM		 2147#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2148GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2149{ \
76a66253 2150 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2151 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2152 return; \
2153 } \
a5e26afa
AJ		 2154 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2155 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2156 gen_reset_fpstatus(); \
4ecc3190
FB		 2157 gen_op_f##op(); \
2158 if (isfloat) { \
2159 gen_op_frsp(); \
2160 } \
a5e26afa 2161 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2162 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2163}
7c58044c
JM		 2164#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2165_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2166_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2167
7c58044c
JM		 2168#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2169GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type) \
9a64fbe4 2170{ \
76a66253 2171 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2172 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2173 return; \
2174 } \
a5e26afa
AJ		 2175 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]); \
2176 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rC(ctx->opcode)]); \
7c58044c 2177 gen_reset_fpstatus(); \
4ecc3190
FB		 2178 gen_op_f##op(); \
2179 if (isfloat) { \
2180 gen_op_frsp(); \
2181 } \
a5e26afa 2182 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2183 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
9a64fbe4 2184}
7c58044c
JM		 2185#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2186_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2187_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
9a64fbe4 2188
7c58044c 2189#define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
a750fc0b 2190GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type) \
9a64fbe4 2191{ \
76a66253 2192 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2193 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2194 return; \
2195 } \
a5e26afa 2196 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2197 gen_reset_fpstatus(); \
9a64fbe4 2198 gen_op_f##name(); \
a5e26afa 2199 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2200 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2201}
2202
7c58044c 2203#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
a750fc0b 2204GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type) \
9a64fbe4 2205{ \
76a66253 2206 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 2207 GEN_EXCP_NO_FP(ctx); \
3cc62370
FB		 2208 return; \
2209 } \
a5e26afa 2210 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]); \
7c58044c 2211 gen_reset_fpstatus(); \
9a64fbe4 2212 gen_op_f##name(); \
a5e26afa 2213 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
7c58044c 2214 gen_compute_fprf(set_fprf, Rc(ctx->opcode) != 0); \
79aceca5
FB		 2215}
2216
9a64fbe4 2217/* fadd - fadds */
7c58044c 2218GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2219/* fdiv - fdivs */
7c58044c 2220GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
4ecc3190 2221/* fmul - fmuls */
7c58044c 2222GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
79aceca5 2223
d7e4b87e 2224/* fre */
7c58044c 2225GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
d7e4b87e 2226
a750fc0b 2227/* fres */
7c58044c 2228GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
79aceca5 2229
a750fc0b 2230/* frsqrte */
7c58044c
JM		 2231GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2232
2233/* frsqrtes */
2234static always_inline void gen_op_frsqrtes (void)
2235{
2236 gen_op_frsqrte();
2237 gen_op_frsp();
2238}
1b413d55 2239GEN_FLOAT_BS(rsqrtes, 0x3B, 0x1A, 1, PPC_FLOAT_FRSQRTES);
79aceca5 2240
a750fc0b 2241/* fsel */
7c58044c 2242_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
4ecc3190 2243/* fsub - fsubs */
7c58044c 2244GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
79aceca5
FB		 2245/* Optional: */
2246/* fsqrt */
a750fc0b 2247GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
c7d344af 2248{
76a66253 2249 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2250 GEN_EXCP_NO_FP(ctx);
c7d344af
FB		 2251 return;
2252 }
a5e26afa 2253 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2254 gen_reset_fpstatus();
c7d344af 2255 gen_op_fsqrt();
a5e26afa 2256 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2257 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
c7d344af 2258}
79aceca5 2259
a750fc0b 2260GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT)
79aceca5 2261{
76a66253 2262 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2263 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2264 return;
2265 }
a5e26afa 2266 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2267 gen_reset_fpstatus();
4ecc3190
FB		 2268 gen_op_fsqrt();
2269 gen_op_frsp();
a5e26afa 2270 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2271 gen_compute_fprf(1, Rc(ctx->opcode) != 0);
79aceca5
FB		 2272}
2273
2274/*** Floating-Point multiply-and-add ***/
4ecc3190 2275/* fmadd - fmadds */
7c58044c 2276GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
4ecc3190 2277/* fmsub - fmsubs */
7c58044c 2278GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
4ecc3190 2279/* fnmadd - fnmadds */
7c58044c 2280GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
4ecc3190 2281/* fnmsub - fnmsubs */
7c58044c 2282GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
79aceca5
FB		 2283
2284/*** Floating-Point round & convert ***/
2285/* fctiw */
7c58044c 2286GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
79aceca5 2287/* fctiwz */
7c58044c 2288GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
79aceca5 2289/* frsp */
7c58044c 2290GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
426613db
JM		 2291#if defined(TARGET_PPC64)
2292/* fcfid */
7c58044c 2293GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
426613db 2294/* fctid */
7c58044c 2295GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
426613db 2296/* fctidz */
7c58044c 2297GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
426613db 2298#endif
79aceca5 2299
d7e4b87e 2300/* frin */
7c58044c 2301GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
d7e4b87e 2302/* friz */
7c58044c 2303GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
d7e4b87e 2304/* frip */
7c58044c 2305GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
d7e4b87e 2306/* frim */
7c58044c 2307GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
d7e4b87e 2308
79aceca5
FB		 2309/*** Floating-Point compare ***/
2310/* fcmpo */
76a66253 2311GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
79aceca5 2312{
76a66253 2313 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2314 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2315 return;
2316 }
a5e26afa
AJ		 2317 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2318 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2319 gen_reset_fpstatus();
e1571908 2320 tcg_gen_helper_1_0(helper_fcmpo, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2321 gen_op_float_check_status();
79aceca5
FB		 2322}
2323
2324/* fcmpu */
76a66253 2325GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
79aceca5 2326{
76a66253 2327 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2328 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2329 return;
2330 }
a5e26afa
AJ		 2331 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rA(ctx->opcode)]);
2332 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2333 gen_reset_fpstatus();
e1571908 2334 tcg_gen_helper_1_0(helper_fcmpu, cpu_crf[crfD(ctx->opcode)]);
7c58044c 2335 gen_op_float_check_status();
79aceca5
FB		 2336}
2337
9a64fbe4
FB		 2338/*** Floating-point move ***/
2339/* fabs */
7c58044c
JM		 2340/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2341GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
9a64fbe4
FB		 2342
2343/* fmr - fmr. */
7c58044c 2344/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
9a64fbe4
FB		 2345GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
2346{
76a66253 2347 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2348 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2349 return;
2350 }
a5e26afa
AJ		 2351 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
2352 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2353 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
9a64fbe4
FB		 2354}
2355
2356/* fnabs */
7c58044c
JM		 2357/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2358GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
9a64fbe4 2359/* fneg */
7c58044c
JM		 2360/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2361GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
9a64fbe4 2362
79aceca5
FB		 2363/*** Floating-Point status & ctrl register ***/
2364/* mcrfs */
2365GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
2366{
7c58044c
JM		 2367 int bfa;
2368
76a66253 2369 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2370 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2371 return;
2372 }
7c58044c
JM		 2373 gen_optimize_fprf();
2374 bfa = 4 * (7 - crfS(ctx->opcode));
e1571908
AJ		 2375 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
2376 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
7c58044c 2377 gen_op_fpscr_resetbit(~(0xF << bfa));
79aceca5
FB		 2378}
2379
2380/* mffs */
2381GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
2382{
76a66253 2383 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2384 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2385 return;
2386 }
7c58044c
JM		 2387 gen_optimize_fprf();
2388 gen_reset_fpstatus();
2389 gen_op_load_fpscr_FT0();
a5e26afa 2390 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
7c58044c 2391 gen_compute_fprf(0, Rc(ctx->opcode) != 0);
79aceca5
FB		 2392}
2393
2394/* mtfsb0 */
2395GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
2396{
fb0eaffc 2397 uint8_t crb;
3b46e624 2398
76a66253 2399 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2400 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2401 return;
2402 }
7c58044c
JM		 2403 crb = 32 - (crbD(ctx->opcode) >> 2);
2404 gen_optimize_fprf();
2405 gen_reset_fpstatus();
2406 if (likely(crb != 30 && crb != 29))
2407 gen_op_fpscr_resetbit(~(1 << crb));
2408 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2409 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c 2410 }
79aceca5
FB		 2411}
2412
2413/* mtfsb1 */
2414GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
2415{
fb0eaffc 2416 uint8_t crb;
3b46e624 2417
76a66253 2418 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2419 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2420 return;
2421 }
7c58044c
JM		 2422 crb = 32 - (crbD(ctx->opcode) >> 2);
2423 gen_optimize_fprf();
2424 gen_reset_fpstatus();
2425 /* XXX: we pretend we can only do IEEE floating-point computations */
2426 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI))
2427 gen_op_fpscr_setbit(crb);
2428 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2429 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2430 }
2431 /* We can raise a differed exception */
2432 gen_op_float_check_status();
79aceca5
FB		 2433}
2434
2435/* mtfsf */
2436GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
2437{
76a66253 2438 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2439 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2440 return;
2441 }
7c58044c 2442 gen_optimize_fprf();
a5e26afa 2443 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rB(ctx->opcode)]);
7c58044c 2444 gen_reset_fpstatus();
28b6751f 2445 gen_op_store_fpscr(FM(ctx->opcode));
7c58044c 2446 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2447 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2448 }
2449 /* We can raise a differed exception */
2450 gen_op_float_check_status();
79aceca5
FB		 2451}
2452
2453/* mtfsfi */
2454GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
2455{
7c58044c
JM		 2456 int bf, sh;
2457
76a66253 2458 if (unlikely(!ctx->fpu_enabled)) {
e1833e1f 2459 GEN_EXCP_NO_FP(ctx);
3cc62370
FB		 2460 return;
2461 }
7c58044c
JM		 2462 bf = crbD(ctx->opcode) >> 2;
2463 sh = 7 - bf;
2464 gen_optimize_fprf();
489251fa 2465 tcg_gen_movi_i64(cpu_FT[0], FPIMM(ctx->opcode) << (4 * sh));
7c58044c
JM		 2466 gen_reset_fpstatus();
2467 gen_op_store_fpscr(1 << sh);
2468 if (unlikely(Rc(ctx->opcode) != 0)) {
e1571908 2469 tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
7c58044c
JM		 2470 }
2471 /* We can raise a differed exception */
2472 gen_op_float_check_status();
79aceca5
FB		 2473}
2474
76a66253
JM		 2475/*** Addressing modes ***/
2476/* Register indirect with immediate index : EA = (rA|0) + SIMM */
e2be8d8d
AJ		 2477static always_inline void gen_addr_imm_index (TCGv EA,
2478 DisasContext *ctx,
b068d6a7 2479 target_long maskl)
76a66253
JM		 2480{
2481 target_long simm = SIMM(ctx->opcode);
2482
be147d08 2483 simm &= ~maskl;
e2be8d8d
AJ		 2484 if (rA(ctx->opcode) == 0)
2485 tcg_gen_movi_tl(EA, simm);
2486 else if (likely(simm != 0))
2487 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2488 else
2489 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2490}
2491
e2be8d8d
AJ		 2492static always_inline void gen_addr_reg_index (TCGv EA,
2493 DisasContext *ctx)
76a66253 2494{
e2be8d8d
AJ		 2495 if (rA(ctx->opcode) == 0)
2496 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2497 else
2498 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 2499}
2500
e2be8d8d
AJ		 2501static always_inline void gen_addr_register (TCGv EA,
2502 DisasContext *ctx)
76a66253 2503{
e2be8d8d
AJ		 2504 if (rA(ctx->opcode) == 0)
2505 tcg_gen_movi_tl(EA, 0);
2506 else
2507 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
76a66253
JM		 2508}
2509
7863667f
JM		 2510#if defined(TARGET_PPC64)
2511#define _GEN_MEM_FUNCS(name, mode) \
2512 &gen_op_##name##_##mode, \
2513 &gen_op_##name##_le_##mode, \
2514 &gen_op_##name##_64_##mode, \
2515 &gen_op_##name##_le_64_##mode
2516#else
2517#define _GEN_MEM_FUNCS(name, mode) \
2518 &gen_op_##name##_##mode, \
2519 &gen_op_##name##_le_##mode
2520#endif
9a64fbe4 2521#if defined(CONFIG_USER_ONLY)
d9bce9d9 2522#if defined(TARGET_PPC64)
7863667f 2523#define NB_MEM_FUNCS 4
d9bce9d9 2524#else
7863667f 2525#define NB_MEM_FUNCS 2
d9bce9d9 2526#endif
7863667f
JM		 2527#define GEN_MEM_FUNCS(name) \
2528 _GEN_MEM_FUNCS(name, raw)
9a64fbe4 2529#else
d9bce9d9 2530#if defined(TARGET_PPC64)
7863667f 2531#define NB_MEM_FUNCS 12
2857068e 2532#else
7863667f 2533#define NB_MEM_FUNCS 6
2857068e 2534#endif
7863667f
JM		 2535#define GEN_MEM_FUNCS(name) \
2536 _GEN_MEM_FUNCS(name, user), \
2537 _GEN_MEM_FUNCS(name, kernel), \
2538 _GEN_MEM_FUNCS(name, hypv)
2539#endif
2540
2541/*** Integer load ***/
2542#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
d9bce9d9 2543#define OP_LD_TABLE(width) \
7863667f
JM		 2544static GenOpFunc *gen_op_l##width[NB_MEM_FUNCS] = { \
2545 GEN_MEM_FUNCS(l##width), \
d9bce9d9
JM		 2546};
2547#define OP_ST_TABLE(width) \
7863667f
JM		 2548static GenOpFunc *gen_op_st##width[NB_MEM_FUNCS] = { \
2549 GEN_MEM_FUNCS(st##width), \
d9bce9d9 2550};
9a64fbe4 2551
b61f2753
AJ		 2552
2553#if defined(TARGET_PPC64)
2554#define GEN_QEMU_LD_PPC64(width) \
2555static always_inline void gen_qemu_ld##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2556{ \
2557 if (likely(flags & 2)) \
2558 tcg_gen_qemu_ld##width(t0, t1, flags >> 2); \
2559 else { \
2560 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2561 tcg_gen_ext32u_tl(addr, t1); \
2562 tcg_gen_qemu_ld##width(t0, addr, flags >> 2); \
2563 tcg_temp_free(addr); \
2564 } \
2565}
2566GEN_QEMU_LD_PPC64(8u)
2567GEN_QEMU_LD_PPC64(8s)
2568GEN_QEMU_LD_PPC64(16u)
2569GEN_QEMU_LD_PPC64(16s)
2570GEN_QEMU_LD_PPC64(32u)
2571GEN_QEMU_LD_PPC64(32s)
2572GEN_QEMU_LD_PPC64(64)
2573
2574#define GEN_QEMU_ST_PPC64(width) \
2575static always_inline void gen_qemu_st##width##_ppc64(TCGv t0, TCGv t1, int flags)\
2576{ \
2577 if (likely(flags & 2)) \
2578 tcg_gen_qemu_st##width(t0, t1, flags >> 2); \
2579 else { \
2580 TCGv addr = tcg_temp_new(TCG_TYPE_TL); \
2581 tcg_gen_ext32u_tl(addr, t1); \
2582 tcg_gen_qemu_st##width(t0, addr, flags >> 2); \
2583 tcg_temp_free(addr); \
2584 } \
2585}
2586GEN_QEMU_ST_PPC64(8)
2587GEN_QEMU_ST_PPC64(16)
2588GEN_QEMU_ST_PPC64(32)
2589GEN_QEMU_ST_PPC64(64)
2590
ea363694 2591static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2592{
ea363694 2593 gen_qemu_ld8u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2594}
2595
ea363694 2596static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2597{
ea363694 2598 gen_qemu_ld8s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2599}
2600
ea363694 2601static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2602{
2603 if (unlikely(flags & 1)) {
ea363694
AJ		 2604 TCGv t0;
2605 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2606 t0 = tcg_temp_new(TCG_TYPE_I32);
2607 tcg_gen_trunc_tl_i32(t0, arg0);
2608 tcg_gen_bswap16_i32(t0, t0);
2609 tcg_gen_extu_i32_tl(arg0, t0);
2610 tcg_temp_free(t0);
b61f2753 2611 } else
ea363694 2612 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2613}
2614
ea363694 2615static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2616{
2617 if (unlikely(flags & 1)) {
ea363694
AJ		 2618 TCGv t0;
2619 gen_qemu_ld16u_ppc64(arg0, arg1, flags);
2620 t0 = tcg_temp_new(TCG_TYPE_I32);
2621 tcg_gen_trunc_tl_i32(t0, arg0);
2622 tcg_gen_bswap16_i32(t0, t0);
2623 tcg_gen_extu_i32_tl(arg0, t0);
2624 tcg_gen_ext16s_tl(arg0, arg0);
2625 tcg_temp_free(t0);
b61f2753 2626 } else
ea363694 2627 gen_qemu_ld16s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2628}
2629
ea363694 2630static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2631{
2632 if (unlikely(flags & 1)) {
ea363694
AJ		 2633 TCGv t0;
2634 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2635 t0 = tcg_temp_new(TCG_TYPE_I32);
2636 tcg_gen_trunc_tl_i32(t0, arg0);
2637 tcg_gen_bswap_i32(t0, t0);
2638 tcg_gen_extu_i32_tl(arg0, t0);
2639 tcg_temp_free(t0);
b61f2753 2640 } else
ea363694 2641 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2642}
2643
ea363694 2644static always_inline void gen_qemu_ld32s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2645{
2646 if (unlikely(flags & 1)) {
ea363694
AJ		 2647 TCGv t0;
2648 gen_qemu_ld32u_ppc64(arg0, arg1, flags);
2649 t0 = tcg_temp_new(TCG_TYPE_I32);
2650 tcg_gen_trunc_tl_i32(t0, arg0);
2651 tcg_gen_bswap_i32(t0, t0);
2652 tcg_gen_ext_i32_tl(arg0, t0);
2653 tcg_temp_free(t0);
b61f2753 2654 } else
ea363694 2655 gen_qemu_ld32s_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2656}
2657
ea363694 2658static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2659{
ea363694 2660 gen_qemu_ld64_ppc64(arg0, arg1, flags);
b61f2753 2661 if (unlikely(flags & 1))
ea363694 2662 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2663}
2664
ea363694 2665static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2666{
ea363694 2667 gen_qemu_st8_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2668}
2669
ea363694 2670static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2671{
2672 if (unlikely(flags & 1)) {
ea363694
AJ		 2673 TCGv t0, t1;
2674 t0 = tcg_temp_new(TCG_TYPE_I32);
2675 tcg_gen_trunc_tl_i32(t0, arg0);
2676 tcg_gen_ext16u_i32(t0, t0);
2677 tcg_gen_bswap16_i32(t0, t0);
2678 t1 = tcg_temp_new(TCG_TYPE_I64);
2679 tcg_gen_extu_i32_tl(t1, t0);
2680 tcg_temp_free(t0);
2681 gen_qemu_st16_ppc64(t1, arg1, flags);
2682 tcg_temp_free(t1);
b61f2753 2683 } else
ea363694 2684 gen_qemu_st16_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2685}
2686
ea363694 2687static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2688{
2689 if (unlikely(flags & 1)) {
ea363694
AJ		 2690 TCGv t0, t1;
2691 t0 = tcg_temp_new(TCG_TYPE_I32);
2692 tcg_gen_trunc_tl_i32(t0, arg0);
2693 tcg_gen_bswap_i32(t0, t0);
2694 t1 = tcg_temp_new(TCG_TYPE_I64);
2695 tcg_gen_extu_i32_tl(t1, t0);
2696 tcg_temp_free(t0);
2697 gen_qemu_st32_ppc64(t1, arg1, flags);
2698 tcg_temp_free(t1);
b61f2753 2699 } else
ea363694 2700 gen_qemu_st32_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2701}
2702
ea363694 2703static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2704{
2705 if (unlikely(flags & 1)) {
ea363694
AJ		 2706 TCGv t0 = tcg_temp_new(TCG_TYPE_I64);
2707 tcg_gen_bswap_i64(t0, arg0);
2708 gen_qemu_st64_ppc64(t0, arg1, flags);
2709 tcg_temp_free(t0);
b61f2753 2710 } else
ea363694 2711 gen_qemu_st64_ppc64(arg0, arg1, flags);
b61f2753
AJ		 2712}
2713
2714
2715#else /* defined(TARGET_PPC64) */
2716#define GEN_QEMU_LD_PPC32(width) \
ea363694 2717static always_inline void gen_qemu_ld##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
b61f2753 2718{ \
ea363694 2719 tcg_gen_qemu_ld##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2720}
2721GEN_QEMU_LD_PPC32(8u)
2722GEN_QEMU_LD_PPC32(8s)
2723GEN_QEMU_LD_PPC32(16u)
2724GEN_QEMU_LD_PPC32(16s)
2725GEN_QEMU_LD_PPC32(32u)
2726GEN_QEMU_LD_PPC32(32s)
2727GEN_QEMU_LD_PPC32(64)
2728
2729#define GEN_QEMU_ST_PPC32(width) \
ea363694 2730static always_inline void gen_qemu_st##width##_ppc32(TCGv arg0, TCGv arg1, int flags)\
b61f2753 2731{ \
ea363694 2732 tcg_gen_qemu_st##width(arg0, arg1, flags >> 1); \
b61f2753
AJ		 2733}
2734GEN_QEMU_ST_PPC32(8)
2735GEN_QEMU_ST_PPC32(16)
2736GEN_QEMU_ST_PPC32(32)
2737GEN_QEMU_ST_PPC32(64)
2738
ea363694 2739static always_inline void gen_qemu_ld8u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2740{
ea363694 2741 gen_qemu_ld8u_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2742}
2743
ea363694 2744static always_inline void gen_qemu_ld8s(TCGv arg0, TCGv arg1, int flags)
b61f2753 2745{
ea363694 2746 gen_qemu_ld8s_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2747}
2748
ea363694 2749static always_inline void gen_qemu_ld16u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2750{
ea363694 2751 gen_qemu_ld16u_ppc32(arg0, arg1, flags >> 1);
b61f2753 2752 if (unlikely(flags & 1))
ea363694 2753 tcg_gen_bswap16_i32(arg0, arg0);
b61f2753
AJ		 2754}
2755
ea363694 2756static always_inline void gen_qemu_ld16s(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2757{
2758 if (unlikely(flags & 1)) {
ea363694
AJ		 2759 gen_qemu_ld16u_ppc32(arg0, arg1, flags);
2760 tcg_gen_bswap16_i32(arg0, arg0);
2761 tcg_gen_ext16s_i32(arg0, arg0);
b61f2753 2762 } else
ea363694 2763 gen_qemu_ld16s_ppc32(arg0, arg1, flags);
b61f2753
AJ		 2764}
2765
ea363694 2766static always_inline void gen_qemu_ld32u(TCGv arg0, TCGv arg1, int flags)
b61f2753 2767{
ea363694 2768 gen_qemu_ld32u_ppc32(arg0, arg1, flags);
b61f2753 2769 if (unlikely(flags & 1))
ea363694 2770 tcg_gen_bswap_i32(arg0, arg0);
b61f2753
AJ		 2771}
2772
ea363694 2773static always_inline void gen_qemu_ld64(TCGv arg0, TCGv arg1, int flags)
b61f2753 2774{
ea363694 2775 gen_qemu_ld64_ppc32(arg0, arg1, flags);
b61f2753 2776 if (unlikely(flags & 1))
ea363694 2777 tcg_gen_bswap_i64(arg0, arg0);
b61f2753
AJ		 2778}
2779
ea363694 2780static always_inline void gen_qemu_st8(TCGv arg0, TCGv arg1, int flags)
b61f2753 2781{
ea363694 2782 gen_qemu_st8_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2783}
2784
ea363694 2785static always_inline void gen_qemu_st16(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2786{
2787 if (unlikely(flags & 1)) {
2788 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
ea363694 2789 tcg_gen_ext16u_i32(temp, arg0);
b61f2753 2790 tcg_gen_bswap16_i32(temp, temp);
ea363694 2791 gen_qemu_st16_ppc32(temp, arg1, flags >> 1);
312179c4 2792 tcg_temp_free(temp);
b61f2753 2793 } else
ea363694 2794 gen_qemu_st16_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2795}
2796
ea363694 2797static always_inline void gen_qemu_st32(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2798{
2799 if (unlikely(flags & 1)) {
2800 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
ea363694
AJ		 2801 tcg_gen_bswap_i32(temp, arg0);
2802 gen_qemu_st32_ppc32(temp, arg1, flags >> 1);
312179c4 2803 tcg_temp_free(temp);
b61f2753 2804 } else
ea363694 2805 gen_qemu_st32_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2806}
2807
ea363694 2808static always_inline void gen_qemu_st64(TCGv arg0, TCGv arg1, int flags)
b61f2753
AJ		 2809{
2810 if (unlikely(flags & 1)) {
2811 TCGv temp = tcg_temp_new(TCG_TYPE_I64);
ea363694
AJ		 2812 tcg_gen_bswap_i64(temp, arg0);
2813 gen_qemu_st64_ppc32(temp, arg1, flags >> 1);
312179c4 2814 tcg_temp_free(temp);
b61f2753 2815 } else
ea363694 2816 gen_qemu_st64_ppc32(arg0, arg1, flags >> 1);
b61f2753
AJ		 2817}
2818
2819#endif
2820
d9bce9d9
JM		 2821#define GEN_LD(width, opc, type) \
2822GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2823{ \
b61f2753
AJ		 2824 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2825 gen_addr_imm_index(EA, ctx, 0); \
2826 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2827 tcg_temp_free(EA); \
79aceca5
FB		 2828}
2829
d9bce9d9
JM		 2830#define GEN_LDU(width, opc, type) \
2831GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2832{ \
b61f2753 2833 TCGv EA; \
76a66253
JM		 2834 if (unlikely(rA(ctx->opcode) == 0 || \
2835 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2836 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2837 return; \
9a64fbe4 2838 } \
b61f2753 2839 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2840 if (type == PPC_64B) \
b61f2753 2841 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2842 else \
b61f2753
AJ		 2843 gen_addr_imm_index(EA, ctx, 0); \
2844 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2845 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2846 tcg_temp_free(EA); \
79aceca5
FB		 2847}
2848
d9bce9d9
JM		 2849#define GEN_LDUX(width, opc2, opc3, type) \
2850GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2851{ \
b61f2753 2852 TCGv EA; \
76a66253
JM		 2853 if (unlikely(rA(ctx->opcode) == 0 || \
2854 rA(ctx->opcode) == rD(ctx->opcode))) { \
e1833e1f 2855 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2856 return; \
9a64fbe4 2857 } \
b61f2753
AJ		 2858 EA = tcg_temp_new(TCG_TYPE_TL); \
2859 gen_addr_reg_index(EA, ctx); \
2860 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2861 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2862 tcg_temp_free(EA); \
79aceca5
FB		 2863}
2864
d9bce9d9
JM		 2865#define GEN_LDX(width, opc2, opc3, type) \
2866GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2867{ \
b61f2753
AJ		 2868 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2869 gen_addr_reg_index(EA, ctx); \
2870 gen_qemu_ld##width(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx); \
2871 tcg_temp_free(EA); \
79aceca5
FB		 2872}
2873
d9bce9d9 2874#define GEN_LDS(width, op, type) \
d9bce9d9
JM		 2875GEN_LD(width, op | 0x20, type); \
2876GEN_LDU(width, op | 0x21, type); \
2877GEN_LDUX(width, 0x17, op | 0x01, type); \
2878GEN_LDX(width, 0x17, op | 0x00, type)
79aceca5
FB		 2879
2880/* lbz lbzu lbzux lbzx */
b61f2753 2881GEN_LDS(8u, 0x02, PPC_INTEGER);
79aceca5 2882/* lha lhau lhaux lhax */
b61f2753 2883GEN_LDS(16s, 0x0A, PPC_INTEGER);
79aceca5 2884/* lhz lhzu lhzux lhzx */
b61f2753 2885GEN_LDS(16u, 0x08, PPC_INTEGER);
79aceca5 2886/* lwz lwzu lwzux lwzx */
b61f2753 2887GEN_LDS(32u, 0x00, PPC_INTEGER);
d9bce9d9 2888#if defined(TARGET_PPC64)
d9bce9d9 2889/* lwaux */
b61f2753 2890GEN_LDUX(32s, 0x15, 0x0B, PPC_64B);
d9bce9d9 2891/* lwax */
b61f2753 2892GEN_LDX(32s, 0x15, 0x0A, PPC_64B);
d9bce9d9 2893/* ldux */
b61f2753 2894GEN_LDUX(64, 0x15, 0x01, PPC_64B);
d9bce9d9 2895/* ldx */
b61f2753 2896GEN_LDX(64, 0x15, 0x00, PPC_64B);
d9bce9d9
JM		 2897GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
2898{
b61f2753 2899 TCGv EA;
d9bce9d9
JM		 2900 if (Rc(ctx->opcode)) {
2901 if (unlikely(rA(ctx->opcode) == 0 ||
2902 rA(ctx->opcode) == rD(ctx->opcode))) {
e1833e1f 2903 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 2904 return;
2905 }
2906 }
b61f2753
AJ		 2907 EA = tcg_temp_new(TCG_TYPE_TL);
2908 gen_addr_imm_index(EA, ctx, 0x03);
d9bce9d9
JM		 2909 if (ctx->opcode & 0x02) {
2910 /* lwa (lwau is undefined) */
b61f2753 2911 gen_qemu_ld32s(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9
JM		 2912 } else {
2913 /* ld - ldu */
b61f2753 2914 gen_qemu_ld64(cpu_gpr[rD(ctx->opcode)], EA, ctx->mem_idx);
d9bce9d9 2915 }
d9bce9d9 2916 if (Rc(ctx->opcode))
b61f2753
AJ		 2917 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2918 tcg_temp_free(EA);
d9bce9d9 2919}
be147d08
JM		 2920/* lq */
2921GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
2922{
2923#if defined(CONFIG_USER_ONLY)
2924 GEN_EXCP_PRIVOPC(ctx);
2925#else
2926 int ra, rd;
b61f2753 2927 TCGv EA;
be147d08
JM		 2928
2929 /* Restore CPU state */
2930 if (unlikely(ctx->supervisor == 0)) {
2931 GEN_EXCP_PRIVOPC(ctx);
2932 return;
2933 }
2934 ra = rA(ctx->opcode);
2935 rd = rD(ctx->opcode);
2936 if (unlikely((rd & 1) || rd == ra)) {
2937 GEN_EXCP_INVAL(ctx);
2938 return;
2939 }
2940 if (unlikely(ctx->mem_idx & 1)) {
2941 /* Little-endian mode is not handled */
2942 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2943 return;
2944 }
b61f2753
AJ		 2945 EA = tcg_temp_new(TCG_TYPE_TL);
2946 gen_addr_imm_index(EA, ctx, 0x0F);
2947 gen_qemu_ld64(cpu_gpr[rd], EA, ctx->mem_idx);
2948 tcg_gen_addi_tl(EA, EA, 8);
2949 gen_qemu_ld64(cpu_gpr[rd+1], EA, ctx->mem_idx);
2950 tcg_temp_free(EA);
be147d08
JM		 2951#endif
2952}
d9bce9d9 2953#endif
79aceca5
FB		 2954
2955/*** Integer store ***/
d9bce9d9
JM		 2956#define GEN_ST(width, opc, type) \
2957GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2958{ \
b61f2753
AJ		 2959 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
2960 gen_addr_imm_index(EA, ctx, 0); \
2961 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2962 tcg_temp_free(EA); \
79aceca5
FB		 2963}
2964
d9bce9d9
JM		 2965#define GEN_STU(width, opc, type) \
2966GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 2967{ \
b61f2753 2968 TCGv EA; \
76a66253 2969 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2970 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2971 return; \
9a64fbe4 2972 } \
b61f2753 2973 EA = tcg_temp_new(TCG_TYPE_TL); \
9d53c753 2974 if (type == PPC_64B) \
b61f2753 2975 gen_addr_imm_index(EA, ctx, 0x03); \
9d53c753 2976 else \
b61f2753
AJ		 2977 gen_addr_imm_index(EA, ctx, 0); \
2978 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2979 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2980 tcg_temp_free(EA); \
79aceca5
FB		 2981}
2982
d9bce9d9
JM		 2983#define GEN_STUX(width, opc2, opc3, type) \
2984GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 2985{ \
b61f2753 2986 TCGv EA; \
76a66253 2987 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 2988 GEN_EXCP_INVAL(ctx); \
9fddaa0c 2989 return; \
9a64fbe4 2990 } \
b61f2753
AJ		 2991 EA = tcg_temp_new(TCG_TYPE_TL); \
2992 gen_addr_reg_index(EA, ctx); \
2993 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
2994 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2995 tcg_temp_free(EA); \
79aceca5
FB		 2996}
2997
d9bce9d9
JM		 2998#define GEN_STX(width, opc2, opc3, type) \
2999GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3000{ \
b61f2753
AJ		 3001 TCGv EA = tcg_temp_new(TCG_TYPE_TL); \
3002 gen_addr_reg_index(EA, ctx); \
3003 gen_qemu_st##width(cpu_gpr[rS(ctx->opcode)], EA, ctx->mem_idx); \
3004 tcg_temp_free(EA); \
79aceca5
FB		 3005}
3006
d9bce9d9 3007#define GEN_STS(width, op, type) \
d9bce9d9
JM		 3008GEN_ST(width, op | 0x20, type); \
3009GEN_STU(width, op | 0x21, type); \
3010GEN_STUX(width, 0x17, op | 0x01, type); \
3011GEN_STX(width, 0x17, op | 0x00, type)
79aceca5
FB		 3012
3013/* stb stbu stbux stbx */
b61f2753 3014GEN_STS(8, 0x06, PPC_INTEGER);
79aceca5 3015/* sth sthu sthux sthx */
b61f2753 3016GEN_STS(16, 0x0C, PPC_INTEGER);
79aceca5 3017/* stw stwu stwux stwx */
b61f2753 3018GEN_STS(32, 0x04, PPC_INTEGER);
d9bce9d9 3019#if defined(TARGET_PPC64)
b61f2753
AJ		 3020GEN_STUX(64, 0x15, 0x05, PPC_64B);
3021GEN_STX(64, 0x15, 0x04, PPC_64B);
be147d08 3022GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
d9bce9d9 3023{
be147d08 3024 int rs;
b61f2753 3025 TCGv EA;
be147d08
JM		 3026
3027 rs = rS(ctx->opcode);
3028 if ((ctx->opcode & 0x3) == 0x2) {
3029#if defined(CONFIG_USER_ONLY)
3030 GEN_EXCP_PRIVOPC(ctx);
3031#else
3032 /* stq */
3033 if (unlikely(ctx->supervisor == 0)) {
3034 GEN_EXCP_PRIVOPC(ctx);
3035 return;
3036 }
3037 if (unlikely(rs & 1)) {
e1833e1f 3038 GEN_EXCP_INVAL(ctx);
d9bce9d9
JM		 3039 return;
3040 }
be147d08
JM		 3041 if (unlikely(ctx->mem_idx & 1)) {
3042 /* Little-endian mode is not handled */
3043 GEN_EXCP(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3044 return;
3045 }
b61f2753
AJ		 3046 EA = tcg_temp_new(TCG_TYPE_TL);
3047 gen_addr_imm_index(EA, ctx, 0x03);
3048 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
3049 tcg_gen_addi_tl(EA, EA, 8);
3050 gen_qemu_st64(cpu_gpr[rs+1], EA, ctx->mem_idx);
3051 tcg_temp_free(EA);
be147d08
JM		 3052#endif
3053 } else {
3054 /* std / stdu */
3055 if (Rc(ctx->opcode)) {
3056 if (unlikely(rA(ctx->opcode) == 0)) {
3057 GEN_EXCP_INVAL(ctx);
3058 return;
3059 }
3060 }
b61f2753
AJ		 3061 EA = tcg_temp_new(TCG_TYPE_TL);
3062 gen_addr_imm_index(EA, ctx, 0x03);
3063 gen_qemu_st64(cpu_gpr[rs], EA, ctx->mem_idx);
be147d08 3064 if (Rc(ctx->opcode))
b61f2753
AJ		 3065 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3066 tcg_temp_free(EA);
d9bce9d9 3067 }
d9bce9d9
JM		 3068}
3069#endif
79aceca5
FB		 3070/*** Integer load and store with byte reverse ***/
3071/* lhbrx */
b61f2753
AJ		 3072void always_inline gen_qemu_ld16ur(TCGv t0, TCGv t1, int flags)
3073{
3074 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3075 gen_qemu_ld16u(temp, t1, flags);
3076 tcg_gen_bswap16_i32(temp, temp);
3077 tcg_gen_extu_i32_tl(t0, temp);
3078 tcg_temp_free(temp);
3079}
3080GEN_LDX(16ur, 0x16, 0x18, PPC_INTEGER);
3081
79aceca5 3082/* lwbrx */
b61f2753
AJ		 3083void always_inline gen_qemu_ld32ur(TCGv t0, TCGv t1, int flags)
3084{
3085 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3086 gen_qemu_ld32u(temp, t1, flags);
3087 tcg_gen_bswap_i32(temp, temp);
3088 tcg_gen_extu_i32_tl(t0, temp);
3089 tcg_temp_free(temp);
3090}
3091GEN_LDX(32ur, 0x16, 0x10, PPC_INTEGER);
3092
79aceca5 3093/* sthbrx */
b61f2753
AJ		 3094void always_inline gen_qemu_st16r(TCGv t0, TCGv t1, int flags)
3095{
3096 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3097 tcg_gen_trunc_tl_i32(temp, t0);
3098 tcg_gen_ext16u_i32(temp, temp);
3099 tcg_gen_bswap16_i32(temp, temp);
3100 gen_qemu_st16(temp, t1, flags);
3101 tcg_temp_free(temp);
3102}
3103GEN_STX(16r, 0x16, 0x1C, PPC_INTEGER);
3104
79aceca5 3105/* stwbrx */
b61f2753
AJ		 3106void always_inline gen_qemu_st32r(TCGv t0, TCGv t1, int flags)
3107{
3108 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3109 tcg_gen_trunc_tl_i32(temp, t0);
3110 tcg_gen_bswap_i32(temp, temp);
3111 gen_qemu_st32(temp, t1, flags);
3112 tcg_temp_free(temp);
3113}
3114GEN_STX(32r, 0x16, 0x14, PPC_INTEGER);
79aceca5
FB		 3115
3116/*** Integer load and store multiple ***/
111bfab3 3117#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
7863667f
JM		 3118static GenOpFunc1 *gen_op_lmw[NB_MEM_FUNCS] = {
3119 GEN_MEM_FUNCS(lmw),
d9bce9d9 3120};
7863667f
JM		 3121static GenOpFunc1 *gen_op_stmw[NB_MEM_FUNCS] = {
3122 GEN_MEM_FUNCS(stmw),
d9bce9d9 3123};
9a64fbe4 3124
79aceca5
FB		 3125/* lmw */
3126GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3127{
76a66253 3128 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3129 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3130 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 3131 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 3132}
3133
3134/* stmw */
3135GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
3136{
76a66253 3137 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3138 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3139 gen_addr_imm_index(cpu_T[0], ctx, 0);
9a64fbe4 3140 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 3141}
3142
3143/*** Integer load and store strings ***/
9a64fbe4
FB		 3144#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
3145#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
e7c24003
JM		 3146/* string load & stores are by definition endian-safe */
3147#define gen_op_lswi_le_raw gen_op_lswi_raw
3148#define gen_op_lswi_le_user gen_op_lswi_user
3149#define gen_op_lswi_le_kernel gen_op_lswi_kernel
3150#define gen_op_lswi_le_hypv gen_op_lswi_hypv
3151#define gen_op_lswi_le_64_raw gen_op_lswi_raw
3152#define gen_op_lswi_le_64_user gen_op_lswi_user
3153#define gen_op_lswi_le_64_kernel gen_op_lswi_kernel
3154#define gen_op_lswi_le_64_hypv gen_op_lswi_hypv
7863667f
JM		 3155static GenOpFunc1 *gen_op_lswi[NB_MEM_FUNCS] = {
3156 GEN_MEM_FUNCS(lswi),
d9bce9d9 3157};
e7c24003
JM		 3158#define gen_op_lswx_le_raw gen_op_lswx_raw
3159#define gen_op_lswx_le_user gen_op_lswx_user
3160#define gen_op_lswx_le_kernel gen_op_lswx_kernel
3161#define gen_op_lswx_le_hypv gen_op_lswx_hypv
3162#define gen_op_lswx_le_64_raw gen_op_lswx_raw
3163#define gen_op_lswx_le_64_user gen_op_lswx_user
3164#define gen_op_lswx_le_64_kernel gen_op_lswx_kernel
3165#define gen_op_lswx_le_64_hypv gen_op_lswx_hypv
7863667f
JM		 3166static GenOpFunc3 *gen_op_lswx[NB_MEM_FUNCS] = {
3167 GEN_MEM_FUNCS(lswx),
d9bce9d9 3168};
e7c24003
JM		 3169#define gen_op_stsw_le_raw gen_op_stsw_raw
3170#define gen_op_stsw_le_user gen_op_stsw_user
3171#define gen_op_stsw_le_kernel gen_op_stsw_kernel
3172#define gen_op_stsw_le_hypv gen_op_stsw_hypv
3173#define gen_op_stsw_le_64_raw gen_op_stsw_raw
3174#define gen_op_stsw_le_64_user gen_op_stsw_user
3175#define gen_op_stsw_le_64_kernel gen_op_stsw_kernel
3176#define gen_op_stsw_le_64_hypv gen_op_stsw_hypv
7863667f
JM		 3177static GenOpFunc1 *gen_op_stsw[NB_MEM_FUNCS] = {
3178 GEN_MEM_FUNCS(stsw),
9a64fbe4 3179};
9a64fbe4 3180
79aceca5 3181/* lswi */
3fc6c082 3182/* PowerPC32 specification says we must generate an exception if
9a64fbe4
FB		 3183 * rA is in the range of registers to be loaded.
3184 * In an other hand, IBM says this is valid, but rA won't be loaded.
3185 * For now, I'll follow the spec...
3186 */
05332d70 3187GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING)
79aceca5
FB		 3188{
3189 int nb = NB(ctx->opcode);
3190 int start = rD(ctx->opcode);
9a64fbe4 3191 int ra = rA(ctx->opcode);
79aceca5
FB		 3192 int nr;
3193
3194 if (nb == 0)
3195 nb = 32;
3196 nr = nb / 4;
76a66253
JM		 3197 if (unlikely(((start + nr) > 32 &&
3198 start <= ra && (start + nr - 32) > ra) ||
3199 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
e1833e1f
JM		 3200 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3201 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_LSWX);
9fddaa0c 3202 return;
297d8e62 3203 }
8dd4983c 3204 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3205 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3206 gen_addr_register(cpu_T[0], ctx);
86c581dc 3207 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3208 op_ldsts(lswi, start);
79aceca5
FB		 3209}
3210
3211/* lswx */
05332d70 3212GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING)
79aceca5 3213{
9a64fbe4
FB		 3214 int ra = rA(ctx->opcode);
3215 int rb = rB(ctx->opcode);
3216
76a66253 3217 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3218 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3219 gen_addr_reg_index(cpu_T[0], ctx);
9a64fbe4 3220 if (ra == 0) {
9a64fbe4 3221 ra = rb;
79aceca5 3222 }
3d7b417e 3223 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3224 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 3225}
3226
3227/* stswi */
05332d70 3228GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING)
79aceca5 3229{
4b3686fa
FB		 3230 int nb = NB(ctx->opcode);
3231
76a66253 3232 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 3233 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3234 gen_addr_register(cpu_T[0], ctx);
4b3686fa
FB		 3235 if (nb == 0)
3236 nb = 32;
86c581dc 3237 tcg_gen_movi_tl(cpu_T[1], nb);
9a64fbe4 3238 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3239}
3240
3241/* stswx */
05332d70 3242GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING)
79aceca5 3243{
8dd4983c 3244 /* NIP cannot be restored if the memory exception comes from an helper */
5fafdf24 3245 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3246 gen_addr_reg_index(cpu_T[0], ctx);
3d7b417e 3247 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
9a64fbe4 3248 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 3249}
3250
3251/*** Memory synchronisation ***/
3252/* eieio */
0db1b20e 3253GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO)
79aceca5 3254{
79aceca5
FB		 3255}
3256
3257/* isync */
0db1b20e 3258GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM)
79aceca5 3259{
e1833e1f 3260 GEN_STOP(ctx);
79aceca5
FB		 3261}
3262
111bfab3
FB		 3263#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
3264#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
7863667f
JM		 3265static GenOpFunc *gen_op_lwarx[NB_MEM_FUNCS] = {
3266 GEN_MEM_FUNCS(lwarx),
111bfab3 3267};
7863667f
JM		 3268static GenOpFunc *gen_op_stwcx[NB_MEM_FUNCS] = {
3269 GEN_MEM_FUNCS(stwcx),
985a19d6 3270};
9a64fbe4 3271
111bfab3 3272/* lwarx */
76a66253 3273GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
79aceca5 3274{
30032c94
JM		 3275 /* NIP cannot be restored if the memory exception comes from an helper */
3276 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3277 gen_addr_reg_index(cpu_T[0], ctx);
985a19d6 3278 op_lwarx();
f78fb44e 3279 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
79aceca5
FB		 3280}
3281
3282/* stwcx. */
c7697e1f 3283GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 3284{
30032c94
JM		 3285 /* NIP cannot be restored if the memory exception comes from an helper */
3286 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3287 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3288 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
9a64fbe4 3289 op_stwcx();
79aceca5
FB		 3290}
3291
426613db
JM		 3292#if defined(TARGET_PPC64)
3293#define op_ldarx() (*gen_op_ldarx[ctx->mem_idx])()
3294#define op_stdcx() (*gen_op_stdcx[ctx->mem_idx])()
7863667f
JM		 3295static GenOpFunc *gen_op_ldarx[NB_MEM_FUNCS] = {
3296 GEN_MEM_FUNCS(ldarx),
426613db 3297};
7863667f
JM		 3298static GenOpFunc *gen_op_stdcx[NB_MEM_FUNCS] = {
3299 GEN_MEM_FUNCS(stdcx),
426613db 3300};
426613db
JM		 3301
3302/* ldarx */
a750fc0b 3303GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
426613db 3304{
30032c94
JM		 3305 /* NIP cannot be restored if the memory exception comes from an helper */
3306 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3307 gen_addr_reg_index(cpu_T[0], ctx);
426613db 3308 op_ldarx();
f78fb44e 3309 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
426613db
JM		 3310}
3311
3312/* stdcx. */
c7697e1f 3313GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
426613db 3314{
30032c94
JM		 3315 /* NIP cannot be restored if the memory exception comes from an helper */
3316 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 3317 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 3318 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
426613db
JM		 3319 op_stdcx();
3320}
3321#endif /* defined(TARGET_PPC64) */
3322
79aceca5 3323/* sync */
a902d886 3324GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC)
79aceca5 3325{
79aceca5
FB		 3326}
3327
0db1b20e
JM		 3328/* wait */
3329GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT)
3330{
3331 /* Stop translation, as the CPU is supposed to sleep from now */
be147d08
JM		 3332 gen_op_wait();
3333 GEN_EXCP(ctx, EXCP_HLT, 1);
0db1b20e
JM		 3334}
3335
79aceca5 3336/*** Floating-point load ***/
477023a6
JM		 3337#define GEN_LDF(width, opc, type) \
3338GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3339{ \
76a66253 3340 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3341 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3342 return; \
3343 } \
e2be8d8d 3344 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3345 op_ldst(l##width); \
a5e26afa 3346 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3347}
3348
477023a6
JM		 3349#define GEN_LDUF(width, opc, type) \
3350GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3351{ \
76a66253 3352 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3353 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3354 return; \
3355 } \
76a66253 3356 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3357 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3358 return; \
9a64fbe4 3359 } \
e2be8d8d 3360 gen_addr_imm_index(cpu_T[0], ctx, 0); \
9a64fbe4 3361 op_ldst(l##width); \
a5e26afa 3362 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3363 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3364}
3365
477023a6
JM		 3366#define GEN_LDUXF(width, opc, type) \
3367GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3368{ \
76a66253 3369 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3370 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3371 return; \
3372 } \
76a66253 3373 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3374 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3375 return; \
9a64fbe4 3376 } \
e2be8d8d 3377 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3378 op_ldst(l##width); \
a5e26afa 3379 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
f78fb44e 3380 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3381}
3382
477023a6
JM		 3383#define GEN_LDXF(width, opc2, opc3, type) \
3384GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3385{ \
76a66253 3386 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3387 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3388 return; \
3389 } \
e2be8d8d 3390 gen_addr_reg_index(cpu_T[0], ctx); \
9a64fbe4 3391 op_ldst(l##width); \
a5e26afa 3392 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]); \
79aceca5
FB		 3393}
3394
477023a6 3395#define GEN_LDFS(width, op, type) \
9a64fbe4 3396OP_LD_TABLE(width); \
477023a6
JM		 3397GEN_LDF(width, op | 0x20, type); \
3398GEN_LDUF(width, op | 0x21, type); \
3399GEN_LDUXF(width, op | 0x01, type); \
3400GEN_LDXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3401
3402/* lfd lfdu lfdux lfdx */
477023a6 3403GEN_LDFS(fd, 0x12, PPC_FLOAT);
79aceca5 3404/* lfs lfsu lfsux lfsx */
477023a6 3405GEN_LDFS(fs, 0x10, PPC_FLOAT);
79aceca5
FB		 3406
3407/*** Floating-point store ***/
477023a6
JM		 3408#define GEN_STF(width, opc, type) \
3409GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3410{ \
76a66253 3411 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3412 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3413 return; \
3414 } \
e2be8d8d 3415 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3416 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3417 op_ldst(st##width); \
79aceca5
FB		 3418}
3419
477023a6
JM		 3420#define GEN_STUF(width, opc, type) \
3421GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
79aceca5 3422{ \
76a66253 3423 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3424 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3425 return; \
3426 } \
76a66253 3427 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3428 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3429 return; \
9a64fbe4 3430 } \
e2be8d8d 3431 gen_addr_imm_index(cpu_T[0], ctx, 0); \
a5e26afa 3432 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3433 op_ldst(st##width); \
f78fb44e 3434 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3435}
3436
477023a6
JM		 3437#define GEN_STUXF(width, opc, type) \
3438GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type) \
79aceca5 3439{ \
76a66253 3440 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3441 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3442 return; \
3443 } \
76a66253 3444 if (unlikely(rA(ctx->opcode) == 0)) { \
e1833e1f 3445 GEN_EXCP_INVAL(ctx); \
9fddaa0c 3446 return; \
9a64fbe4 3447 } \
e2be8d8d 3448 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3449 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3450 op_ldst(st##width); \
f78fb44e 3451 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]); \
79aceca5
FB		 3452}
3453
477023a6
JM		 3454#define GEN_STXF(width, opc2, opc3, type) \
3455GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type) \
79aceca5 3456{ \
76a66253 3457 if (unlikely(!ctx->fpu_enabled)) { \
e1833e1f 3458 GEN_EXCP_NO_FP(ctx); \
4ecc3190
FB		 3459 return; \
3460 } \
e2be8d8d 3461 gen_addr_reg_index(cpu_T[0], ctx); \
a5e26afa 3462 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]); \
9a64fbe4 3463 op_ldst(st##width); \
79aceca5
FB		 3464}
3465
477023a6 3466#define GEN_STFS(width, op, type) \
9a64fbe4 3467OP_ST_TABLE(width); \
477023a6
JM		 3468GEN_STF(width, op | 0x20, type); \
3469GEN_STUF(width, op | 0x21, type); \
3470GEN_STUXF(width, op | 0x01, type); \
3471GEN_STXF(width, 0x17, op | 0x00, type)
79aceca5
FB		 3472
3473/* stfd stfdu stfdux stfdx */
477023a6 3474GEN_STFS(fd, 0x16, PPC_FLOAT);
79aceca5 3475/* stfs stfsu stfsux stfsx */
477023a6 3476GEN_STFS(fs, 0x14, PPC_FLOAT);
79aceca5
FB		 3477
3478/* Optional: */
3479/* stfiwx */
5b8105fa
JM		 3480OP_ST_TABLE(fiw);
3481GEN_STXF(fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
79aceca5
FB		 3482
3483/*** Branch ***/
b068d6a7
JM		 3484static always_inline void gen_goto_tb (DisasContext *ctx, int n,
3485 target_ulong dest)
c1942362
FB		 3486{
3487 TranslationBlock *tb;
3488 tb = ctx->tb;
a2ffb812
AJ		 3489#if defined(TARGET_PPC64)
3490 if (!ctx->sf_mode)
3491 dest = (uint32_t) dest;
3492#endif
57fec1fe 3493 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
8cbcb4fa 3494 likely(!ctx->singlestep_enabled)) {
57fec1fe 3495 tcg_gen_goto_tb(n);
a2ffb812 3496 tcg_gen_movi_tl(cpu_nip, dest & ~3);
57fec1fe 3497 tcg_gen_exit_tb((long)tb + n);
c1942362 3498 } else {
a2ffb812 3499 tcg_gen_movi_tl(cpu_nip, dest & ~3);
8cbcb4fa
AJ		 3500 if (unlikely(ctx->singlestep_enabled)) {
3501 if ((ctx->singlestep_enabled &
3502 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3503 ctx->exception == POWERPC_EXCP_BRANCH) {
3504 target_ulong tmp = ctx->nip;
3505 ctx->nip = dest;
3506 GEN_EXCP(ctx, POWERPC_EXCP_TRACE, 0);
3507 ctx->nip = tmp;
3508 }
3509 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3510 gen_update_nip(ctx, dest);
3511 gen_op_debug();
3512 }
3513 }
57fec1fe 3514 tcg_gen_exit_tb(0);
c1942362 3515 }
c53be334
FB		 3516}
3517
b068d6a7 3518static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
e1833e1f
JM		 3519{
3520#if defined(TARGET_PPC64)
a2ffb812
AJ		 3521 if (ctx->sf_mode == 0)
3522 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
e1833e1f
JM		 3523 else
3524#endif
a2ffb812 3525 tcg_gen_movi_tl(cpu_lr, nip);
e1833e1f
JM		 3526}
3527
79aceca5
FB		 3528/* b ba bl bla */
3529GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3530{
76a66253 3531 target_ulong li, target;
38a64f9d 3532
8cbcb4fa 3533 ctx->exception = POWERPC_EXCP_BRANCH;
38a64f9d 3534 /* sign extend LI */
76a66253 3535#if defined(TARGET_PPC64)
d9bce9d9
JM		 3536 if (ctx->sf_mode)
3537 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3538 else
76a66253 3539#endif
d9bce9d9 3540 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
76a66253 3541 if (likely(AA(ctx->opcode) == 0))
046d6672 3542 target = ctx->nip + li - 4;
79aceca5 3543 else
9a64fbe4 3544 target = li;
e1833e1f
JM		 3545 if (LK(ctx->opcode))
3546 gen_setlr(ctx, ctx->nip);
c1942362 3547 gen_goto_tb(ctx, 0, target);
79aceca5
FB		 3548}
3549
e98a6e40
FB		 3550#define BCOND_IM 0
3551#define BCOND_LR 1
3552#define BCOND_CTR 2
3553
b068d6a7 3554static always_inline void gen_bcond (DisasContext *ctx, int type)
d9bce9d9 3555{
d9bce9d9 3556 uint32_t bo = BO(ctx->opcode);
a2ffb812
AJ		 3557 int l1 = gen_new_label();
3558 TCGv target;
e98a6e40 3559
8cbcb4fa 3560 ctx->exception = POWERPC_EXCP_BRANCH;
a2ffb812
AJ		 3561 if (type == BCOND_LR || type == BCOND_CTR) {
3562 target = tcg_temp_local_new(TCG_TYPE_TL);
3563 if (type == BCOND_CTR)
3564 tcg_gen_mov_tl(target, cpu_ctr);
3565 else
3566 tcg_gen_mov_tl(target, cpu_lr);
e98a6e40 3567 }
e1833e1f
JM		 3568 if (LK(ctx->opcode))
3569 gen_setlr(ctx, ctx->nip);
a2ffb812
AJ		 3570 l1 = gen_new_label();
3571 if ((bo & 0x4) == 0) {
3572 /* Decrement and test CTR */
3573 TCGv temp = tcg_temp_new(TCG_TYPE_TL);
3574 if (unlikely(type == BCOND_CTR)) {
3575 GEN_EXCP_INVAL(ctx);
3576 return;
3577 }
3578 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
d9bce9d9 3579#if defined(TARGET_PPC64)
a2ffb812
AJ		 3580 if (!ctx->sf_mode)
3581 tcg_gen_ext32u_tl(temp, cpu_ctr);
3582 else
d9bce9d9 3583#endif
a2ffb812
AJ		 3584 tcg_gen_mov_tl(temp, cpu_ctr);
3585 if (bo & 0x2) {
3586 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3587 } else {
3588 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
e98a6e40 3589 }
a2ffb812
AJ		 3590 }
3591 if ((bo & 0x10) == 0) {
3592 /* Test CR */
3593 uint32_t bi = BI(ctx->opcode);
3594 uint32_t mask = 1 << (3 - (bi & 0x03));
3595 TCGv temp = tcg_temp_new(TCG_TYPE_I32);
3596
d9bce9d9 3597 if (bo & 0x8) {
a2ffb812
AJ		 3598 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3599 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
d9bce9d9 3600 } else {
a2ffb812
AJ		 3601 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3602 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
d9bce9d9
JM		 3603 }
3604 }
e98a6e40 3605 if (type == BCOND_IM) {
a2ffb812
AJ		 3606
3607 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3608 if (likely(AA(ctx->opcode) == 0)) {
3609 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3610 } else {
3611 gen_goto_tb(ctx, 0, li);
3612 }
c53be334 3613 gen_set_label(l1);
c1942362 3614 gen_goto_tb(ctx, 1, ctx->nip);
e98a6e40 3615 } else {
d9bce9d9 3616#if defined(TARGET_PPC64)
a2ffb812
AJ		 3617 if (!(ctx->sf_mode))
3618 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3619 else
3620#endif
3621 tcg_gen_andi_tl(cpu_nip, target, ~3);
3622 tcg_gen_exit_tb(0);
3623 gen_set_label(l1);
3624#if defined(TARGET_PPC64)
3625 if (!(ctx->sf_mode))
3626 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
d9bce9d9
JM		 3627 else
3628#endif
a2ffb812 3629 tcg_gen_movi_tl(cpu_nip, ctx->nip);
57fec1fe 3630 tcg_gen_exit_tb(0);
08e46e54 3631 }
e98a6e40
FB		 3632}
3633
3634GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3b46e624 3635{
e98a6e40
FB		 3636 gen_bcond(ctx, BCOND_IM);
3637}
3638
3639GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
3b46e624 3640{
e98a6e40
FB		 3641 gen_bcond(ctx, BCOND_CTR);
3642}
3643
3644GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
3b46e624 3645{
e98a6e40
FB		 3646 gen_bcond(ctx, BCOND_LR);
3647}
79aceca5
FB		 3648
3649/*** Condition register logical ***/
e1571908
AJ		 3650#define GEN_CRLOGIC(name, tcg_op, opc) \
3651GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
79aceca5 3652{ \
fc0d441e
JM		 3653 uint8_t bitmask; \
3654 int sh; \
fea0c503 3655 TCGv t0, t1; \
fc0d441e 3656 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
fea0c503 3657 t0 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e 3658 if (sh > 0) \
fea0c503 3659 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
fc0d441e 3660 else if (sh < 0) \
fea0c503 3661 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
e1571908 3662 else \
fea0c503
AJ		 3663 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3664 t1 = tcg_temp_new(TCG_TYPE_I32); \
fc0d441e
JM		 3665 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3666 if (sh > 0) \
fea0c503 3667 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
fc0d441e 3668 else if (sh < 0) \
fea0c503 3669 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
e1571908 3670 else \
fea0c503
AJ		 3671 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3672 tcg_op(t0, t0, t1); \
fc0d441e 3673 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
fea0c503
AJ		 3674 tcg_gen_andi_i32(t0, t0, bitmask); \
3675 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3676 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3677 tcg_temp_free(t0); \
3678 tcg_temp_free(t1); \
79aceca5
FB		 3679}
3680
3681/* crand */
e1571908 3682GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
79aceca5 3683/* crandc */
e1571908 3684GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
79aceca5 3685/* creqv */
e1571908 3686GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
79aceca5 3687/* crnand */
e1571908 3688GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
79aceca5 3689/* crnor */
e1571908 3690GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
79aceca5 3691/* cror */
e1571908 3692GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
79aceca5 3693/* crorc */
e1571908 3694GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
79aceca5 3695/* crxor */
e1571908 3696GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
79aceca5
FB		 3697/* mcrf */
3698GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
3699{
47e4661c 3700 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
79aceca5
FB		 3701}
3702
3703/*** System linkage ***/
3704/* rfi (supervisor only) */
76a66253 3705GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW)
79aceca5 3706{
9a64fbe4 3707#if defined(CONFIG_USER_ONLY)
e1833e1f 3708 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4
FB		 3709#else
3710 /* Restore CPU state */
76a66253 3711 if (unlikely(!ctx->supervisor)) {
e1833e1f 3712 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 3713 return;
9a64fbe4 3714 }
a42bd6cc 3715 gen_op_rfi();
e1833e1f 3716 GEN_SYNC(ctx);
9a64fbe4 3717#endif
79aceca5
FB		 3718}
3719
426613db 3720#if defined(TARGET_PPC64)
a750fc0b 3721GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B)
426613db
JM		 3722{
3723#if defined(CONFIG_USER_ONLY)
e1833e1f 3724 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3725#else
3726 /* Restore CPU state */
3727 if (unlikely(!ctx->supervisor)) {
e1833e1f 3728 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 3729 return;
3730 }
a42bd6cc 3731 gen_op_rfid();
e1833e1f 3732 GEN_SYNC(ctx);
426613db
JM		 3733#endif
3734}
426613db 3735
5b8105fa 3736GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H)
be147d08
JM		 3737{
3738#if defined(CONFIG_USER_ONLY)
3739 GEN_EXCP_PRIVOPC(ctx);
3740#else
3741 /* Restore CPU state */
3742 if (unlikely(ctx->supervisor <= 1)) {
3743 GEN_EXCP_PRIVOPC(ctx);
3744 return;
3745 }
3746 gen_op_hrfid();
3747 GEN_SYNC(ctx);
3748#endif
3749}
3750#endif
3751
79aceca5 3752/* sc */
417bf010
JM		 3753#if defined(CONFIG_USER_ONLY)
3754#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3755#else
3756#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3757#endif
e1833e1f 3758GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
79aceca5 3759{
e1833e1f
JM		 3760 uint32_t lev;
3761
3762 lev = (ctx->opcode >> 5) & 0x7F;
417bf010 3763 GEN_EXCP(ctx, POWERPC_SYSCALL, lev);
79aceca5
FB		 3764}
3765
3766/*** Trap ***/
3767/* tw */
76a66253 3768GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
79aceca5 3769{
f78fb44e
AJ		 3770 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3771 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
a0ae05aa 3772 /* Update the nip since this might generate a trap exception */
d9bce9d9 3773 gen_update_nip(ctx, ctx->nip);
9a64fbe4 3774 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3775}
3776
3777/* twi */
3778GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
3779{
f78fb44e 3780 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3781 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3782 /* Update the nip since this might generate a trap exception */
3783 gen_update_nip(ctx, ctx->nip);
76a66253 3784 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 3785}
3786
d9bce9d9
JM		 3787#if defined(TARGET_PPC64)
3788/* td */
3789GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
3790{
f78fb44e
AJ		 3791 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
3792 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 3793 /* Update the nip since this might generate a trap exception */
3794 gen_update_nip(ctx, ctx->nip);
3795 gen_op_td(TO(ctx->opcode));
3796}
3797
3798/* tdi */
3799GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
3800{
f78fb44e 3801 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
02f4f6c2 3802 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
d9bce9d9
JM		 3803 /* Update the nip since this might generate a trap exception */
3804 gen_update_nip(ctx, ctx->nip);
3805 gen_op_td(TO(ctx->opcode));
3806}
3807#endif
3808
79aceca5 3809/*** Processor control ***/
79aceca5
FB		 3810/* mcrxr */
3811GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
3812{
3d7b417e
AJ		 3813 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], cpu_xer);
3814 tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], XER_CA);
269f3e95 3815 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_SO | 1 << XER_OV | 1 << XER_CA));
79aceca5
FB		 3816}
3817
3818/* mfcr */
76a66253 3819GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
79aceca5 3820{
76a66253 3821 uint32_t crm, crn;
3b46e624 3822
76a66253
JM		 3823 if (likely(ctx->opcode & 0x00100000)) {
3824 crm = CRM(ctx->opcode);
3825 if (likely((crm ^ (crm - 1)) == 0)) {
3826 crn = ffs(crm);
e1571908 3827 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
76a66253 3828 }
d9bce9d9 3829 } else {
e1571908 3830 tcg_gen_helper_1_0(helper_load_cr, cpu_gpr[rD(ctx->opcode)]);
d9bce9d9 3831 }
79aceca5
FB		 3832}
3833
3834/* mfmsr */
3835GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
3836{
9a64fbe4 3837#if defined(CONFIG_USER_ONLY)
e1833e1f 3838 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3839#else
76a66253 3840 if (unlikely(!ctx->supervisor)) {
e1833e1f 3841 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3842 return;
9a64fbe4 3843 }
6676f424 3844 gen_op_load_msr();
f78fb44e 3845 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 3846#endif
79aceca5
FB		 3847}
3848
a11b8151 3849#if 1
6f2d8978 3850#define SPR_NOACCESS ((void *)(-1UL))
3fc6c082
FB		 3851#else
3852static void spr_noaccess (void *opaque, int sprn)
3853{
3854 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3855 printf("ERROR: try to access SPR %d !\n", sprn);
3856}
3857#define SPR_NOACCESS (&spr_noaccess)
3858#endif
3859
79aceca5 3860/* mfspr */
b068d6a7 3861static always_inline void gen_op_mfspr (DisasContext *ctx)
79aceca5 3862{
3fc6c082 3863 void (*read_cb)(void *opaque, int sprn);
79aceca5
FB		 3864 uint32_t sprn = SPR(ctx->opcode);
3865
3fc6c082 3866#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 3867 if (ctx->supervisor == 2)
3868 read_cb = ctx->spr_cb[sprn].hea_read;
7863667f 3869 else if (ctx->supervisor)
3fc6c082
FB		 3870 read_cb = ctx->spr_cb[sprn].oea_read;
3871 else
9a64fbe4 3872#endif
3fc6c082 3873 read_cb = ctx->spr_cb[sprn].uea_read;
76a66253
JM		 3874 if (likely(read_cb != NULL)) {
3875 if (likely(read_cb != SPR_NOACCESS)) {
3fc6c082 3876 (*read_cb)(ctx, sprn);
f78fb44e 3877 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
3fc6c082
FB		 3878 } else {
3879 /* Privilege exception */
9fceefa7
JM		 3880 /* This is a hack to avoid warnings when running Linux:
3881 * this OS breaks the PowerPC virtualisation model,
3882 * allowing userland application to read the PVR
3883 */
3884 if (sprn != SPR_PVR) {
3885 if (loglevel != 0) {
6b542af7 3886 fprintf(logfile, "Trying to read privileged spr %d %03x at "
077fc206 3887 ADDRX "\n", sprn, sprn, ctx->nip);
9fceefa7 3888 }
077fc206
JM		 3889 printf("Trying to read privileged spr %d %03x at " ADDRX "\n",
3890 sprn, sprn, ctx->nip);
f24e5695 3891 }
e1833e1f 3892 GEN_EXCP_PRIVREG(ctx);
79aceca5 3893 }
3fc6c082
FB		 3894 } else {
3895 /* Not defined */
4a057712 3896 if (loglevel != 0) {
077fc206
JM		 3897 fprintf(logfile, "Trying to read invalid spr %d %03x at "
3898 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 3899 }
077fc206
JM		 3900 printf("Trying to read invalid spr %d %03x at " ADDRX "\n",
3901 sprn, sprn, ctx->nip);
e1833e1f
JM		 3902 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
3903 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 3904 }
79aceca5
FB		 3905}
3906
3fc6c082 3907GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
79aceca5 3908{
3fc6c082 3909 gen_op_mfspr(ctx);
76a66253 3910}
3fc6c082
FB		 3911
3912/* mftb */
a750fc0b 3913GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB)
3fc6c082
FB		 3914{
3915 gen_op_mfspr(ctx);
79aceca5
FB		 3916}
3917
3918/* mtcrf */
8dd4983c 3919GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
79aceca5 3920{
76a66253 3921 uint32_t crm, crn;
3b46e624 3922
76a66253
JM		 3923 crm = CRM(ctx->opcode);
3924 if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
3925 crn = ffs(crm);
e1571908
AJ		 3926 tcg_gen_shri_i32(cpu_crf[7 - crn], cpu_gpr[rS(ctx->opcode)], crn * 4);
3927 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
76a66253 3928 } else {
fea0c503
AJ		 3929 TCGv t0 = tcg_const_tl(crm);
3930 tcg_gen_helper_0_2(helper_store_cr, cpu_gpr[rS(ctx->opcode)], t0);
3931 tcg_temp_free(t0);
76a66253 3932 }
79aceca5
FB		 3933}
3934
3935/* mtmsr */
426613db 3936#if defined(TARGET_PPC64)
be147d08 3937GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
426613db
JM		 3938{
3939#if defined(CONFIG_USER_ONLY)
e1833e1f 3940 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3941#else
3942 if (unlikely(!ctx->supervisor)) {
e1833e1f 3943 GEN_EXCP_PRIVREG(ctx);
426613db
JM		 3944 return;
3945 }
f78fb44e 3946 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3947 if (ctx->opcode & 0x00010000) {
3948 /* Special form that does not need any synchronisation */
3949 gen_op_update_riee();
3950 } else {
056b05f8
JM		 3951 /* XXX: we need to update nip before the store
3952 * if we enter power saving mode, we will exit the loop
3953 * directly from ppc_store_msr
3954 */
be147d08 3955 gen_update_nip(ctx, ctx->nip);
6676f424 3956 gen_op_store_msr();
be147d08
JM		 3957 /* Must stop the translation as machine state (may have) changed */
3958 /* Note that mtmsr is not always defined as context-synchronizing */
056b05f8 3959 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3960 }
426613db
JM		 3961#endif
3962}
3963#endif
3964
79aceca5
FB		 3965GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
3966{
9a64fbe4 3967#if defined(CONFIG_USER_ONLY)
e1833e1f 3968 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 3969#else
76a66253 3970 if (unlikely(!ctx->supervisor)) {
e1833e1f 3971 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 3972 return;
9a64fbe4 3973 }
f78fb44e 3974 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
be147d08
JM		 3975 if (ctx->opcode & 0x00010000) {
3976 /* Special form that does not need any synchronisation */
3977 gen_op_update_riee();
3978 } else {
056b05f8
JM		 3979 /* XXX: we need to update nip before the store
3980 * if we enter power saving mode, we will exit the loop
3981 * directly from ppc_store_msr
3982 */
be147d08 3983 gen_update_nip(ctx, ctx->nip);
d9bce9d9 3984#if defined(TARGET_PPC64)
be147d08 3985 if (!ctx->sf_mode)
6676f424 3986 gen_op_store_msr_32();
be147d08 3987 else
d9bce9d9 3988#endif
6676f424 3989 gen_op_store_msr();
be147d08
JM		 3990 /* Must stop the translation as machine state (may have) changed */
3991 /* Note that mtmsrd is not always defined as context-synchronizing */
056b05f8 3992 ctx->exception = POWERPC_EXCP_STOP;
be147d08 3993 }
9a64fbe4 3994#endif
79aceca5
FB		 3995}
3996
3997/* mtspr */
3998GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
3999{
3fc6c082 4000 void (*write_cb)(void *opaque, int sprn);
79aceca5
FB		 4001 uint32_t sprn = SPR(ctx->opcode);
4002
3fc6c082 4003#if !defined(CONFIG_USER_ONLY)
be147d08
JM		 4004 if (ctx->supervisor == 2)
4005 write_cb = ctx->spr_cb[sprn].hea_write;
7863667f 4006 else if (ctx->supervisor)
3fc6c082
FB		 4007 write_cb = ctx->spr_cb[sprn].oea_write;
4008 else
9a64fbe4 4009#endif
3fc6c082 4010 write_cb = ctx->spr_cb[sprn].uea_write;
76a66253
JM		 4011 if (likely(write_cb != NULL)) {
4012 if (likely(write_cb != SPR_NOACCESS)) {
f78fb44e 4013 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
3fc6c082
FB		 4014 (*write_cb)(ctx, sprn);
4015 } else {
4016 /* Privilege exception */
4a057712 4017 if (loglevel != 0) {
077fc206
JM		 4018 fprintf(logfile, "Trying to write privileged spr %d %03x at "
4019 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4020 }
077fc206
JM		 4021 printf("Trying to write privileged spr %d %03x at " ADDRX "\n",
4022 sprn, sprn, ctx->nip);
e1833e1f 4023 GEN_EXCP_PRIVREG(ctx);
76a66253 4024 }
3fc6c082
FB		 4025 } else {
4026 /* Not defined */
4a057712 4027 if (loglevel != 0) {
077fc206
JM		 4028 fprintf(logfile, "Trying to write invalid spr %d %03x at "
4029 ADDRX "\n", sprn, sprn, ctx->nip);
f24e5695 4030 }
077fc206
JM		 4031 printf("Trying to write invalid spr %d %03x at " ADDRX "\n",
4032 sprn, sprn, ctx->nip);
e1833e1f
JM		 4033 GEN_EXCP(ctx, POWERPC_EXCP_PROGRAM,
4034 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_SPR);
79aceca5 4035 }
79aceca5
FB		 4036}
4037
4038/*** Cache management ***/
79aceca5 4039/* dcbf */
0db1b20e 4040GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
79aceca5 4041{
dac454af 4042 /* XXX: specification says this is treated as a load by the MMU */
fea0c503
AJ		 4043 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
4044 gen_addr_reg_index(t0, ctx);
4045 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4046 tcg_temp_free(t0);
79aceca5
FB		 4047}
4048
4049/* dcbi (Supervisor only) */
9a64fbe4 4050GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 4051{
a541f297 4052#if defined(CONFIG_USER_ONLY)
e1833e1f 4053 GEN_EXCP_PRIVOPC(ctx);
a541f297 4054#else
b61f2753 4055 TCGv EA, val;
76a66253 4056 if (unlikely(!ctx->supervisor)) {
e1833e1f 4057 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4058 return;
9a64fbe4 4059 }
b61f2753
AJ		 4060 EA = tcg_temp_new(TCG_TYPE_TL);
4061 gen_addr_reg_index(EA, ctx);
ed69522c 4062 val = tcg_temp_new(TCG_TYPE_TL);
76a66253 4063 /* XXX: specification says this should be treated as a store by the MMU */
b61f2753
AJ		 4064 gen_qemu_ld8u(val, EA, ctx->mem_idx);
4065 gen_qemu_st8(val, EA, ctx->mem_idx);
4066 tcg_temp_free(val);
4067 tcg_temp_free(EA);
a541f297 4068#endif
79aceca5
FB		 4069}
4070
4071/* dcdst */
9a64fbe4 4072GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 4073{
76a66253 4074 /* XXX: specification say this is treated as a load by the MMU */
fea0c503
AJ		 4075 TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
4076 gen_addr_reg_index(t0, ctx);
4077 gen_qemu_ld8u(t0, t0, ctx->mem_idx);
4078 tcg_temp_free(t0);
79aceca5
FB		 4079}
4080
4081/* dcbt */
0db1b20e 4082GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE)
79aceca5 4083{
0db1b20e 4084 /* interpreted as no-op */
76a66253
JM		 4085 /* XXX: specification say this is treated as a load by the MMU
4086 * but does not generate any exception
4087 */
79aceca5
FB		 4088}
4089
4090/* dcbtst */
0db1b20e 4091GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
79aceca5 4092{
0db1b20e 4093 /* interpreted as no-op */
76a66253
JM		 4094 /* XXX: specification say this is treated as a load by the MMU
4095 * but does not generate any exception
4096 */
79aceca5
FB		 4097}
4098
4099/* dcbz */
d63001d1 4100#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
7863667f
JM		 4101static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
4102 /* 32 bytes cache line size */
d63001d1 4103 {
7863667f
JM		 4104#define gen_op_dcbz_l32_le_raw gen_op_dcbz_l32_raw
4105#define gen_op_dcbz_l32_le_user gen_op_dcbz_l32_user
4106#define gen_op_dcbz_l32_le_kernel gen_op_dcbz_l32_kernel
4107#define gen_op_dcbz_l32_le_hypv gen_op_dcbz_l32_hypv
4108#define gen_op_dcbz_l32_le_64_raw gen_op_dcbz_l32_64_raw
4109#define gen_op_dcbz_l32_le_64_user gen_op_dcbz_l32_64_user
4110#define gen_op_dcbz_l32_le_64_kernel gen_op_dcbz_l32_64_kernel
4111#define gen_op_dcbz_l32_le_64_hypv gen_op_dcbz_l32_64_hypv
4112 GEN_MEM_FUNCS(dcbz_l32),
d63001d1 4113 },
7863667f 4114 /* 64 bytes cache line size */
d63001d1 4115 {
7863667f
JM		 4116#define gen_op_dcbz_l64_le_raw gen_op_dcbz_l64_raw
4117#define gen_op_dcbz_l64_le_user gen_op_dcbz_l64_user
4118#define gen_op_dcbz_l64_le_kernel gen_op_dcbz_l64_kernel
4119#define gen_op_dcbz_l64_le_hypv gen_op_dcbz_l64_hypv
4120#define gen_op_dcbz_l64_le_64_raw gen_op_dcbz_l64_64_raw
4121#define gen_op_dcbz_l64_le_64_user gen_op_dcbz_l64_64_user
4122#define gen_op_dcbz_l64_le_64_kernel gen_op_dcbz_l64_64_kernel
4123#define gen_op_dcbz_l64_le_64_hypv gen_op_dcbz_l64_64_hypv
4124 GEN_MEM_FUNCS(dcbz_l64),
d63001d1 4125 },
7863667f 4126 /* 128 bytes cache line size */
d63001d1 4127 {
7863667f
JM		 4128#define gen_op_dcbz_l128_le_raw gen_op_dcbz_l128_raw
4129#define gen_op_dcbz_l128_le_user gen_op_dcbz_l128_user
4130#define gen_op_dcbz_l128_le_kernel gen_op_dcbz_l128_kernel
4131#define gen_op_dcbz_l128_le_hypv gen_op_dcbz_l128_hypv
4132#define gen_op_dcbz_l128_le_64_raw gen_op_dcbz_l128_64_raw
4133#define gen_op_dcbz_l128_le_64_user gen_op_dcbz_l128_64_user
4134#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
4135#define gen_op_dcbz_l128_le_64_hypv gen_op_dcbz_l128_64_hypv
4136 GEN_MEM_FUNCS(dcbz_l128),
d63001d1 4137 },
7863667f 4138 /* tunable cache line size */
d63001d1 4139 {
7863667f
JM		 4140#define gen_op_dcbz_le_raw gen_op_dcbz_raw
4141#define gen_op_dcbz_le_user gen_op_dcbz_user
4142#define gen_op_dcbz_le_kernel gen_op_dcbz_kernel
4143#define gen_op_dcbz_le_hypv gen_op_dcbz_hypv
4144#define gen_op_dcbz_le_64_raw gen_op_dcbz_64_raw
4145#define gen_op_dcbz_le_64_user gen_op_dcbz_64_user
4146#define gen_op_dcbz_le_64_kernel gen_op_dcbz_64_kernel
4147#define gen_op_dcbz_le_64_hypv gen_op_dcbz_64_hypv
4148 GEN_MEM_FUNCS(dcbz),
d63001d1 4149 },
76a66253 4150};
9a64fbe4 4151
b068d6a7
JM		 4152static always_inline void handler_dcbz (DisasContext *ctx,
4153 int dcache_line_size)
d63001d1
JM		 4154{
4155 int n;
4156
4157 switch (dcache_line_size) {
4158 case 32:
4159 n = 0;
4160 break;
4161 case 64:
4162 n = 1;
4163 break;
4164 case 128:
4165 n = 2;
4166 break;
4167 default:
4168 n = 3;
4169 break;
4170 }
4171 op_dcbz(n);
4172}
4173
4174GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
79aceca5 4175{
e2be8d8d 4176 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 4177 handler_dcbz(ctx, ctx->dcache_line_size);
4178 gen_op_check_reservation();
4179}
4180
c7697e1f 4181GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
d63001d1 4182{
e2be8d8d 4183 gen_addr_reg_index(cpu_T[0], ctx);
d63001d1
JM		 4184 if (ctx->opcode & 0x00200000)
4185 handler_dcbz(ctx, ctx->dcache_line_size);
4186 else
4187 handler_dcbz(ctx, -1);
4b3686fa 4188 gen_op_check_reservation();
79aceca5
FB		 4189}
4190
4191/* icbi */
36f69651 4192#define op_icbi() (*gen_op_icbi[ctx->mem_idx])()
7863667f
JM		 4193#define gen_op_icbi_le_raw gen_op_icbi_raw
4194#define gen_op_icbi_le_user gen_op_icbi_user
4195#define gen_op_icbi_le_kernel gen_op_icbi_kernel
4196#define gen_op_icbi_le_hypv gen_op_icbi_hypv
4197#define gen_op_icbi_le_64_raw gen_op_icbi_64_raw
4198#define gen_op_icbi_le_64_user gen_op_icbi_64_user
4199#define gen_op_icbi_le_64_kernel gen_op_icbi_64_kernel
4200#define gen_op_icbi_le_64_hypv gen_op_icbi_64_hypv
4201static GenOpFunc *gen_op_icbi[NB_MEM_FUNCS] = {
4202 GEN_MEM_FUNCS(icbi),
36f69651 4203};
e1833e1f 4204
1b413d55 4205GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI)
79aceca5 4206{
30032c94
JM		 4207 /* NIP cannot be restored if the memory exception comes from an helper */
4208 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 4209 gen_addr_reg_index(cpu_T[0], ctx);
36f69651 4210 op_icbi();
79aceca5
FB		 4211}
4212
4213/* Optional: */
4214/* dcba */
a750fc0b 4215GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA)
79aceca5 4216{
0db1b20e
JM		 4217 /* interpreted as no-op */
4218 /* XXX: specification say this is treated as a store by the MMU
4219 * but does not generate any exception
4220 */
79aceca5
FB		 4221}
4222
4223/*** Segment register manipulation ***/
4224/* Supervisor only: */
4225/* mfsr */
4226GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
4227{
9a64fbe4 4228#if defined(CONFIG_USER_ONLY)
e1833e1f 4229 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4230#else
76a66253 4231 if (unlikely(!ctx->supervisor)) {
e1833e1f 4232 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4233 return;
9a64fbe4 4234 }
86c581dc 4235 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4236 gen_op_load_sr();
f78fb44e 4237 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4238#endif
79aceca5
FB		 4239}
4240
4241/* mfsrin */
9a64fbe4 4242GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 4243{
9a64fbe4 4244#if defined(CONFIG_USER_ONLY)
e1833e1f 4245 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4246#else
76a66253 4247 if (unlikely(!ctx->supervisor)) {
e1833e1f 4248 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4249 return;
9a64fbe4 4250 }
f78fb44e 4251 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4252 gen_op_srli_T1(28);
4253 gen_op_load_sr();
f78fb44e 4254 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
9a64fbe4 4255#endif
79aceca5
FB		 4256}
4257
4258/* mtsr */
e63c59cb 4259GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 4260{
9a64fbe4 4261#if defined(CONFIG_USER_ONLY)
e1833e1f 4262 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4263#else
76a66253 4264 if (unlikely(!ctx->supervisor)) {
e1833e1f 4265 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4266 return;
9a64fbe4 4267 }
f78fb44e 4268 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4269 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
76a66253 4270 gen_op_store_sr();
9a64fbe4 4271#endif
79aceca5
FB		 4272}
4273
4274/* mtsrin */
9a64fbe4 4275GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 4276{
9a64fbe4 4277#if defined(CONFIG_USER_ONLY)
e1833e1f 4278 GEN_EXCP_PRIVREG(ctx);
9a64fbe4 4279#else
76a66253 4280 if (unlikely(!ctx->supervisor)) {
e1833e1f 4281 GEN_EXCP_PRIVREG(ctx);
9fddaa0c 4282 return;
9a64fbe4 4283 }
f78fb44e
AJ		 4284 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4285 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253
JM		 4286 gen_op_srli_T1(28);
4287 gen_op_store_sr();
9a64fbe4 4288#endif
79aceca5
FB		 4289}
4290
12de9a39
JM		 4291#if defined(TARGET_PPC64)
4292/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4293/* mfsr */
c7697e1f 4294GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4295{
4296#if defined(CONFIG_USER_ONLY)
4297 GEN_EXCP_PRIVREG(ctx);
4298#else
4299 if (unlikely(!ctx->supervisor)) {
4300 GEN_EXCP_PRIVREG(ctx);
4301 return;
4302 }
86c581dc 4303 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39 4304 gen_op_load_slb();
f78fb44e 4305 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4306#endif
4307}
4308
4309/* mfsrin */
c7697e1f
JM		 4310GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
4311 PPC_SEGMENT_64B)
12de9a39
JM		 4312{
4313#if defined(CONFIG_USER_ONLY)
4314 GEN_EXCP_PRIVREG(ctx);
4315#else
4316 if (unlikely(!ctx->supervisor)) {
4317 GEN_EXCP_PRIVREG(ctx);
4318 return;
4319 }
f78fb44e 4320 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4321 gen_op_srli_T1(28);
4322 gen_op_load_slb();
f78fb44e 4323 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
12de9a39
JM		 4324#endif
4325}
4326
4327/* mtsr */
c7697e1f 4328GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
12de9a39
JM		 4329{
4330#if defined(CONFIG_USER_ONLY)
4331 GEN_EXCP_PRIVREG(ctx);
4332#else
4333 if (unlikely(!ctx->supervisor)) {
4334 GEN_EXCP_PRIVREG(ctx);
4335 return;
4336 }
f78fb44e 4337 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4338 tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
12de9a39
JM		 4339 gen_op_store_slb();
4340#endif
4341}
4342
4343/* mtsrin */
c7697e1f
JM		 4344GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
4345 PPC_SEGMENT_64B)
12de9a39
JM		 4346{
4347#if defined(CONFIG_USER_ONLY)
4348 GEN_EXCP_PRIVREG(ctx);
4349#else
4350 if (unlikely(!ctx->supervisor)) {
4351 GEN_EXCP_PRIVREG(ctx);
4352 return;
4353 }
f78fb44e
AJ		 4354 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4355 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
12de9a39
JM		 4356 gen_op_srli_T1(28);
4357 gen_op_store_slb();
4358#endif
4359}
4360#endif /* defined(TARGET_PPC64) */
4361
79aceca5
FB		 4362/*** Lookaside buffer management ***/
4363/* Optional & supervisor only: */
4364/* tlbia */
3fc6c082 4365GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA)
79aceca5 4366{
9a64fbe4 4367#if defined(CONFIG_USER_ONLY)
e1833e1f 4368 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4369#else
76a66253 4370 if (unlikely(!ctx->supervisor)) {
e1833e1f 4371 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4372 return;
9a64fbe4
FB		 4373 }
4374 gen_op_tlbia();
4375#endif
79aceca5
FB		 4376}
4377
4378/* tlbie */
76a66253 4379GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
79aceca5 4380{
9a64fbe4 4381#if defined(CONFIG_USER_ONLY)
e1833e1f 4382 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4383#else
76a66253 4384 if (unlikely(!ctx->supervisor)) {
e1833e1f 4385 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4386 return;
9a64fbe4 4387 }
f78fb44e 4388 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
d9bce9d9
JM		 4389#if defined(TARGET_PPC64)
4390 if (ctx->sf_mode)
4391 gen_op_tlbie_64();
4392 else
4393#endif
4394 gen_op_tlbie();
9a64fbe4 4395#endif
79aceca5
FB		 4396}
4397
4398/* tlbsync */
76a66253 4399GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC)
79aceca5 4400{
9a64fbe4 4401#if defined(CONFIG_USER_ONLY)
e1833e1f 4402 GEN_EXCP_PRIVOPC(ctx);
9a64fbe4 4403#else
76a66253 4404 if (unlikely(!ctx->supervisor)) {
e1833e1f 4405 GEN_EXCP_PRIVOPC(ctx);
9fddaa0c 4406 return;
9a64fbe4
FB		 4407 }
4408 /* This has no effect: it should ensure that all previous
4409 * tlbie have completed
4410 */
e1833e1f 4411 GEN_STOP(ctx);
9a64fbe4 4412#endif
79aceca5
FB		 4413}
4414
426613db
JM		 4415#if defined(TARGET_PPC64)
4416/* slbia */
4417GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI)
4418{
4419#if defined(CONFIG_USER_ONLY)
e1833e1f 4420 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4421#else
4422 if (unlikely(!ctx->supervisor)) {
e1833e1f 4423 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4424 return;
4425 }
4426 gen_op_slbia();
426613db
JM		 4427#endif
4428}
4429
4430/* slbie */
4431GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
4432{
4433#if defined(CONFIG_USER_ONLY)
e1833e1f 4434 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4435#else
4436 if (unlikely(!ctx->supervisor)) {
e1833e1f 4437 GEN_EXCP_PRIVOPC(ctx);
426613db
JM		 4438 return;
4439 }
f78fb44e 4440 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
426613db 4441 gen_op_slbie();
426613db
JM		 4442#endif
4443}
4444#endif
4445
79aceca5
FB		 4446/*** External control ***/
4447/* Optional: */
9a64fbe4
FB		 4448#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
4449#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
7863667f
JM		 4450static GenOpFunc *gen_op_eciwx[NB_MEM_FUNCS] = {
4451 GEN_MEM_FUNCS(eciwx),
111bfab3 4452};
7863667f
JM		 4453static GenOpFunc *gen_op_ecowx[NB_MEM_FUNCS] = {
4454 GEN_MEM_FUNCS(ecowx),
111bfab3 4455};
9a64fbe4 4456
111bfab3 4457/* eciwx */
79aceca5
FB		 4458GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
4459{
9a64fbe4 4460 /* Should check EAR[E] & alignment ! */
e2be8d8d 4461 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 4462 op_eciwx();
f78fb44e 4463 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4464}
4465
4466/* ecowx */
4467GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
4468{
4469 /* Should check EAR[E] & alignment ! */
e2be8d8d 4470 gen_addr_reg_index(cpu_T[0], ctx);
f78fb44e 4471 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 4472 op_ecowx();
4473}
4474
4475/* PowerPC 601 specific instructions */
4476/* abs - abs. */
4477GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
4478{
f78fb44e 4479 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4480 gen_op_POWER_abs();
f78fb44e 4481 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4482 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4483 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4484}
4485
4486/* abso - abso. */
4487GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
4488{
f78fb44e 4489 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4490 gen_op_POWER_abso();
f78fb44e 4491 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4492 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4493 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4494}
4495
4496/* clcs */
a750fc0b 4497GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
76a66253 4498{
f78fb44e 4499 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4500 gen_op_POWER_clcs();
c7697e1f 4501 /* Rc=1 sets CR0 to an undefined state */
f78fb44e 4502 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4503}
4504
4505/* div - div. */
4506GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
4507{
f78fb44e
AJ		 4508 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4509 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4510 gen_op_POWER_div();
f78fb44e 4511 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4512 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4513 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4514}
4515
4516/* divo - divo. */
4517GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
4518{
f78fb44e
AJ		 4519 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4520 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4521 gen_op_POWER_divo();
f78fb44e 4522 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4523 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4524 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4525}
4526
4527/* divs - divs. */
4528GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
4529{
f78fb44e
AJ		 4530 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4531 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4532 gen_op_POWER_divs();
f78fb44e 4533 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4534 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4535 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4536}
4537
4538/* divso - divso. */
4539GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
4540{
f78fb44e
AJ		 4541 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4542 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4543 gen_op_POWER_divso();
f78fb44e 4544 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4545 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4546 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4547}
4548
4549/* doz - doz. */
4550GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
4551{
f78fb44e
AJ		 4552 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4553 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4554 gen_op_POWER_doz();
f78fb44e 4555 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4556 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4557 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4558}
4559
4560/* dozo - dozo. */
4561GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
4562{
f78fb44e
AJ		 4563 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4564 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4565 gen_op_POWER_dozo();
f78fb44e 4566 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4567 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4568 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4569}
4570
4571/* dozi */
4572GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4573{
f78fb44e 4574 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
86c581dc 4575 tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
76a66253 4576 gen_op_POWER_doz();
f78fb44e 4577 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4578}
4579
7863667f
JM		 4580/* As lscbx load from memory byte after byte, it's always endian safe.
4581 * Original POWER is 32 bits only, define 64 bits ops as 32 bits ones
4582 */
2857068e 4583#define op_POWER_lscbx(start, ra, rb) \
76a66253 4584(*gen_op_POWER_lscbx[ctx->mem_idx])(start, ra, rb)
7863667f
JM		 4585#define gen_op_POWER_lscbx_64_raw gen_op_POWER_lscbx_raw
4586#define gen_op_POWER_lscbx_64_user gen_op_POWER_lscbx_user
4587#define gen_op_POWER_lscbx_64_kernel gen_op_POWER_lscbx_kernel
4588#define gen_op_POWER_lscbx_64_hypv gen_op_POWER_lscbx_hypv
4589#define gen_op_POWER_lscbx_le_raw gen_op_POWER_lscbx_raw
4590#define gen_op_POWER_lscbx_le_user gen_op_POWER_lscbx_user
4591#define gen_op_POWER_lscbx_le_kernel gen_op_POWER_lscbx_kernel
4592#define gen_op_POWER_lscbx_le_hypv gen_op_POWER_lscbx_hypv
4593#define gen_op_POWER_lscbx_le_64_raw gen_op_POWER_lscbx_raw
4594#define gen_op_POWER_lscbx_le_64_user gen_op_POWER_lscbx_user
4595#define gen_op_POWER_lscbx_le_64_kernel gen_op_POWER_lscbx_kernel
4596#define gen_op_POWER_lscbx_le_64_hypv gen_op_POWER_lscbx_hypv
4597static GenOpFunc3 *gen_op_POWER_lscbx[NB_MEM_FUNCS] = {
4598 GEN_MEM_FUNCS(POWER_lscbx),
76a66253 4599};
76a66253
JM		 4600
4601/* lscbx - lscbx. */
4602GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
4603{
4604 int ra = rA(ctx->opcode);
4605 int rb = rB(ctx->opcode);
4606
e2be8d8d 4607 gen_addr_reg_index(cpu_T[0], ctx);
76a66253
JM		 4608 if (ra == 0) {
4609 ra = rb;
4610 }
4611 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 4612 gen_update_nip(ctx, ctx->nip - 4);
3d7b417e
AJ		 4613 tcg_gen_andi_tl(cpu_T[1], cpu_xer, 0x7F);
4614 tcg_gen_shri_tl(cpu_T[2], cpu_xer, XER_CMP);
4615 tcg_gen_andi_tl(cpu_T[2], cpu_T[2], 0xFF);
76a66253 4616 op_POWER_lscbx(rD(ctx->opcode), ra, rb);
3d7b417e
AJ		 4617 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4618 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253 4619 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4620 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4621}
4622
4623/* maskg - maskg. */
4624GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
4625{
f78fb44e
AJ		 4626 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4627 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4628 gen_op_POWER_maskg();
f78fb44e 4629 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4630 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4631 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4632}
4633
4634/* maskir - maskir. */
4635GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
4636{
f78fb44e
AJ		 4637 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4638 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
4639 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4640 gen_op_POWER_maskir();
f78fb44e 4641 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4642 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4643 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4644}
4645
4646/* mul - mul. */
4647GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
4648{
f78fb44e
AJ		 4649 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4650 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4651 gen_op_POWER_mul();
f78fb44e 4652 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4653 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4654 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4655}
4656
4657/* mulo - mulo. */
4658GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
4659{
f78fb44e
AJ		 4660 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
4661 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4662 gen_op_POWER_mulo();
f78fb44e 4663 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4664 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4665 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4666}
4667
4668/* nabs - nabs. */
4669GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
4670{
f78fb44e 4671 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4672 gen_op_POWER_nabs();
f78fb44e 4673 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4674 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4675 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4676}
4677
4678/* nabso - nabso. */
4679GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
4680{
f78fb44e 4681 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4682 gen_op_POWER_nabso();
f78fb44e 4683 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 4684 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4685 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4686}
4687
4688/* rlmi - rlmi. */
4689GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
4690{
4691 uint32_t mb, me;
4692
4693 mb = MB(ctx->opcode);
4694 me = ME(ctx->opcode);
f78fb44e
AJ		 4695 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4696 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4697 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4698 gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
f78fb44e 4699 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4700 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4701 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4702}
4703
4704/* rrib - rrib. */
4705GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
4706{
f78fb44e
AJ		 4707 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4708 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
4709 tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
76a66253 4710 gen_op_POWER_rrib();
f78fb44e 4711 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4712 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4713 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4714}
4715
4716/* sle - sle. */
4717GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
4718{
f78fb44e
AJ		 4719 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4720 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4721 gen_op_POWER_sle();
f78fb44e 4722 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4723 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4724 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4725}
4726
4727/* sleq - sleq. */
4728GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
4729{
f78fb44e
AJ		 4730 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4731 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4732 gen_op_POWER_sleq();
f78fb44e 4733 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4734 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4735 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4736}
4737
4738/* sliq - sliq. */
4739GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
4740{
f78fb44e 4741 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4742 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4743 gen_op_POWER_sle();
f78fb44e 4744 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4745 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4746 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4747}
4748
4749/* slliq - slliq. */
4750GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
4751{
f78fb44e 4752 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4753 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4754 gen_op_POWER_sleq();
f78fb44e 4755 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4756 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4757 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4758}
4759
4760/* sllq - sllq. */
4761GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
4762{
f78fb44e
AJ		 4763 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4764 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4765 gen_op_POWER_sllq();
f78fb44e 4766 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4767 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4768 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4769}
4770
4771/* slq - slq. */
4772GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
4773{
f78fb44e
AJ		 4774 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4775 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4776 gen_op_POWER_slq();
f78fb44e 4777 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4778 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4779 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4780}
4781
d9bce9d9 4782/* sraiq - sraiq. */
76a66253
JM		 4783GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
4784{
f78fb44e 4785 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4786 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4787 gen_op_POWER_sraq();
f78fb44e 4788 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4789 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4790 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4791}
4792
4793/* sraq - sraq. */
4794GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
4795{
f78fb44e
AJ		 4796 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4797 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4798 gen_op_POWER_sraq();
f78fb44e 4799 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4800 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4801 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4802}
4803
4804/* sre - sre. */
4805GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
4806{
f78fb44e
AJ		 4807 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4808 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4809 gen_op_POWER_sre();
f78fb44e 4810 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4811 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4812 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4813}
4814
4815/* srea - srea. */
4816GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
4817{
f78fb44e
AJ		 4818 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4819 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4820 gen_op_POWER_srea();
f78fb44e 4821 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4822 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4823 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4824}
4825
4826/* sreq */
4827GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
4828{
f78fb44e
AJ		 4829 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4830 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4831 gen_op_POWER_sreq();
f78fb44e 4832 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4833 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4834 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4835}
4836
4837/* sriq */
4838GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
4839{
f78fb44e 4840 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
86c581dc 4841 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4842 gen_op_POWER_srq();
f78fb44e 4843 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4844 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4845 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4846}
4847
4848/* srliq */
4849GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
4850{
f78fb44e
AJ		 4851 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4852 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
86c581dc 4853 tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
76a66253 4854 gen_op_POWER_srlq();
f78fb44e 4855 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4856 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4857 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4858}
4859
4860/* srlq */
4861GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
4862{
f78fb44e
AJ		 4863 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4864 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4865 gen_op_POWER_srlq();
f78fb44e 4866 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4867 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4868 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4869}
4870
4871/* srq */
4872GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
4873{
f78fb44e
AJ		 4874 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
4875 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 4876 gen_op_POWER_srq();
f78fb44e 4877 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
76a66253 4878 if (unlikely(Rc(ctx->opcode) != 0))
e1571908 4879 gen_set_Rc0(ctx, cpu_T[0]);
76a66253
JM		 4880}
4881
4882/* PowerPC 602 specific instructions */
4883/* dsa */
4884GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC)
4885{
4886 /* XXX: TODO */
e1833e1f 4887 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4888}
4889
4890/* esa */
4891GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC)
4892{
4893 /* XXX: TODO */
e1833e1f 4894 GEN_EXCP_INVAL(ctx);
76a66253
JM		 4895}
4896
4897/* mfrom */
4898GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
4899{
4900#if defined(CONFIG_USER_ONLY)
e1833e1f 4901 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4902#else
4903 if (unlikely(!ctx->supervisor)) {
e1833e1f 4904 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4905 return;
4906 }
f78fb44e 4907 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 4908 gen_op_602_mfrom();
f78fb44e 4909 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 4910#endif
4911}
4912
4913/* 602 - 603 - G2 TLB management */
4914/* tlbld */
c7697e1f 4915GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4916{
4917#if defined(CONFIG_USER_ONLY)
e1833e1f 4918 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4919#else
4920 if (unlikely(!ctx->supervisor)) {
e1833e1f 4921 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4922 return;
4923 }
f78fb44e 4924 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4925 gen_op_6xx_tlbld();
76a66253
JM		 4926#endif
4927}
4928
4929/* tlbli */
c7697e1f 4930GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
76a66253
JM		 4931{
4932#if defined(CONFIG_USER_ONLY)
e1833e1f 4933 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4934#else
4935 if (unlikely(!ctx->supervisor)) {
e1833e1f 4936 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4937 return;
4938 }
f78fb44e 4939 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
76a66253 4940 gen_op_6xx_tlbli();
76a66253
JM		 4941#endif
4942}
4943
7dbe11ac
JM		 4944/* 74xx TLB management */
4945/* tlbld */
c7697e1f 4946GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4947{
4948#if defined(CONFIG_USER_ONLY)
4949 GEN_EXCP_PRIVOPC(ctx);
4950#else
4951 if (unlikely(!ctx->supervisor)) {
4952 GEN_EXCP_PRIVOPC(ctx);
4953 return;
4954 }
f78fb44e 4955 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4956 gen_op_74xx_tlbld();
4957#endif
4958}
4959
4960/* tlbli */
c7697e1f 4961GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
7dbe11ac
JM		 4962{
4963#if defined(CONFIG_USER_ONLY)
4964 GEN_EXCP_PRIVOPC(ctx);
4965#else
4966 if (unlikely(!ctx->supervisor)) {
4967 GEN_EXCP_PRIVOPC(ctx);
4968 return;
4969 }
f78fb44e 4970 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
7dbe11ac
JM		 4971 gen_op_74xx_tlbli();
4972#endif
4973}
4974
76a66253
JM		 4975/* POWER instructions not in PowerPC 601 */
4976/* clf */
4977GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER)
4978{
4979 /* Cache line flush: implemented as no-op */
4980}
4981
4982/* cli */
4983GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER)
4984{
7f75ffd3 4985 /* Cache line invalidate: privileged and treated as no-op */
76a66253 4986#if defined(CONFIG_USER_ONLY)
e1833e1f 4987 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4988#else
4989 if (unlikely(!ctx->supervisor)) {
e1833e1f 4990 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 4991 return;
4992 }
4993#endif
4994}
4995
4996/* dclst */
4997GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER)
4998{
4999 /* Data cache line store: treated as no-op */
5000}
5001
5002GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
5003{
5004#if defined(CONFIG_USER_ONLY)
e1833e1f 5005 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5006#else
5007 if (unlikely(!ctx->supervisor)) {
e1833e1f 5008 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5009 return;
5010 }
5011 int ra = rA(ctx->opcode);
5012 int rd = rD(ctx->opcode);
5013
e2be8d8d 5014 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5015 gen_op_POWER_mfsri();
f78fb44e 5016 tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
76a66253 5017 if (ra != 0 && ra != rd)
f78fb44e 5018 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
76a66253
JM		 5019#endif
5020}
5021
5022GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
5023{
5024#if defined(CONFIG_USER_ONLY)
e1833e1f 5025 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5026#else
5027 if (unlikely(!ctx->supervisor)) {
e1833e1f 5028 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5029 return;
5030 }
e2be8d8d 5031 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5032 gen_op_POWER_rac();
f78fb44e 5033 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5034#endif
5035}
5036
5037GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER)
5038{
5039#if defined(CONFIG_USER_ONLY)
e1833e1f 5040 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5041#else
5042 if (unlikely(!ctx->supervisor)) {
e1833e1f 5043 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5044 return;
5045 }
5046 gen_op_POWER_rfsvc();
e1833e1f 5047 GEN_SYNC(ctx);
76a66253
JM		 5048#endif
5049}
5050
5051/* svc is not implemented for now */
5052
5053/* POWER2 specific instructions */
5054/* Quad manipulation (load/store two floats at a time) */
7863667f 5055/* Original POWER2 is 32 bits only, define 64 bits ops as 32 bits ones */
76a66253
JM		 5056#define op_POWER2_lfq() (*gen_op_POWER2_lfq[ctx->mem_idx])()
5057#define op_POWER2_stfq() (*gen_op_POWER2_stfq[ctx->mem_idx])()
7863667f
JM		 5058#define gen_op_POWER2_lfq_64_raw gen_op_POWER2_lfq_raw
5059#define gen_op_POWER2_lfq_64_user gen_op_POWER2_lfq_user
5060#define gen_op_POWER2_lfq_64_kernel gen_op_POWER2_lfq_kernel
5061#define gen_op_POWER2_lfq_64_hypv gen_op_POWER2_lfq_hypv
5062#define gen_op_POWER2_lfq_le_64_raw gen_op_POWER2_lfq_le_raw
5063#define gen_op_POWER2_lfq_le_64_user gen_op_POWER2_lfq_le_user
5064#define gen_op_POWER2_lfq_le_64_kernel gen_op_POWER2_lfq_le_kernel
5065#define gen_op_POWER2_lfq_le_64_hypv gen_op_POWER2_lfq_le_hypv
5066#define gen_op_POWER2_stfq_64_raw gen_op_POWER2_stfq_raw
5067#define gen_op_POWER2_stfq_64_user gen_op_POWER2_stfq_user
5068#define gen_op_POWER2_stfq_64_kernel gen_op_POWER2_stfq_kernel
5069#define gen_op_POWER2_stfq_64_hypv gen_op_POWER2_stfq_hypv
5070#define gen_op_POWER2_stfq_le_64_raw gen_op_POWER2_stfq_le_raw
5071#define gen_op_POWER2_stfq_le_64_user gen_op_POWER2_stfq_le_user
5072#define gen_op_POWER2_stfq_le_64_kernel gen_op_POWER2_stfq_le_kernel
5073#define gen_op_POWER2_stfq_le_64_hypv gen_op_POWER2_stfq_le_hypv
5074static GenOpFunc *gen_op_POWER2_lfq[NB_MEM_FUNCS] = {
5075 GEN_MEM_FUNCS(POWER2_lfq),
76a66253 5076};
7863667f
JM		 5077static GenOpFunc *gen_op_POWER2_stfq[NB_MEM_FUNCS] = {
5078 GEN_MEM_FUNCS(POWER2_stfq),
76a66253 5079};
76a66253
JM		 5080
5081/* lfq */
5082GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5083{
5084 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5085 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5086 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 5087 op_POWER2_lfq();
a5e26afa
AJ		 5088 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5089 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 5090}
5091
5092/* lfqu */
5093GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5094{
5095 int ra = rA(ctx->opcode);
5096
5097 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5098 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5099 gen_addr_imm_index(cpu_T[0], ctx, 0);
76a66253 5100 op_POWER2_lfq();
a5e26afa
AJ		 5101 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5102 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 5103 if (ra != 0)
f78fb44e 5104 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5105}
5106
5107/* lfqux */
5108GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
5109{
5110 int ra = rA(ctx->opcode);
5111
5112 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5113 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5114 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5115 op_POWER2_lfq();
a5e26afa
AJ		 5116 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5117 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253 5118 if (ra != 0)
f78fb44e 5119 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5120}
5121
5122/* lfqx */
5123GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2)
5124{
5125 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5126 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5127 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5128 op_POWER2_lfq();
a5e26afa
AJ		 5129 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_FT[0]);
5130 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode) + 1], cpu_FT[1]);
76a66253
JM		 5131}
5132
5133/* stfq */
5134GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5135{
5136 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5137 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5138 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 5139 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5140 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5141 op_POWER2_stfq();
5142}
5143
5144/* stfqu */
5145GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
5146{
5147 int ra = rA(ctx->opcode);
5148
5149 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5150 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5151 gen_addr_imm_index(cpu_T[0], ctx, 0);
a5e26afa
AJ		 5152 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5153 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5154 op_POWER2_stfq();
5155 if (ra != 0)
f78fb44e 5156 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5157}
5158
5159/* stfqux */
5160GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
5161{
5162 int ra = rA(ctx->opcode);
5163
5164 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5165 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5166 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 5167 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5168 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5169 op_POWER2_stfq();
5170 if (ra != 0)
f78fb44e 5171 tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
76a66253
JM		 5172}
5173
5174/* stfqx */
5175GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2)
5176{
5177 /* NIP cannot be restored if the memory exception comes from an helper */
d9bce9d9 5178 gen_update_nip(ctx, ctx->nip - 4);
e2be8d8d 5179 gen_addr_reg_index(cpu_T[0], ctx);
a5e26afa
AJ		 5180 tcg_gen_mov_i64(cpu_FT[0], cpu_fpr[rS(ctx->opcode)]);
5181 tcg_gen_mov_i64(cpu_FT[1], cpu_fpr[rS(ctx->opcode) + 1]);
76a66253
JM		 5182 op_POWER2_stfq();
5183}
5184
5185/* BookE specific instructions */
2662a059 5186/* XXX: not implemented on 440 ? */
05332d70 5187GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI)
76a66253
JM		 5188{
5189 /* XXX: TODO */
e1833e1f 5190 GEN_EXCP_INVAL(ctx);
76a66253
JM		 5191}
5192
2662a059 5193/* XXX: not implemented on 440 ? */
05332d70 5194GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA)
76a66253
JM		 5195{
5196#if defined(CONFIG_USER_ONLY)
e1833e1f 5197 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5198#else
5199 if (unlikely(!ctx->supervisor)) {
e1833e1f 5200 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5201 return;
5202 }
e2be8d8d 5203 gen_addr_reg_index(cpu_T[0], ctx);
76a66253 5204 /* Use the same micro-ops as for tlbie */
d9bce9d9
JM		 5205#if defined(TARGET_PPC64)
5206 if (ctx->sf_mode)
5207 gen_op_tlbie_64();
5208 else
5209#endif
5210 gen_op_tlbie();
76a66253
JM		 5211#endif
5212}
5213
5214/* All 405 MAC instructions are translated here */
b068d6a7
JM		 5215static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
5216 int opc2, int opc3,
5217 int ra, int rb, int rt, int Rc)
76a66253 5218{
182608d4
AJ		 5219 TCGv t0, t1;
5220
5221 t0 = tcg_temp_local_new(TCG_TYPE_TL);
5222 t1 = tcg_temp_local_new(TCG_TYPE_TL);
5223
76a66253
JM		 5224 switch (opc3 & 0x0D) {
5225 case 0x05:
5226 /* macchw - macchw. - macchwo - macchwo. */
5227 /* macchws - macchws. - macchwso - macchwso. */
5228 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5229 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5230 /* mulchw - mulchw. */
182608d4
AJ		 5231 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5232 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5233 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5234 break;
5235 case 0x04:
5236 /* macchwu - macchwu. - macchwuo - macchwuo. */
5237 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5238 /* mulchwu - mulchwu. */
182608d4
AJ		 5239 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5240 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5241 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5242 break;
5243 case 0x01:
5244 /* machhw - machhw. - machhwo - machhwo. */
5245 /* machhws - machhws. - machhwso - machhwso. */
5246 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5247 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5248 /* mulhhw - mulhhw. */
182608d4
AJ		 5249 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5250 tcg_gen_ext16s_tl(t0, t0);
5251 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5252 tcg_gen_ext16s_tl(t1, t1);
76a66253
JM		 5253 break;
5254 case 0x00:
5255 /* machhwu - machhwu. - machhwuo - machhwuo. */
5256 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5257 /* mulhhwu - mulhhwu. */
182608d4
AJ		 5258 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5259 tcg_gen_ext16u_tl(t0, t0);
5260 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5261 tcg_gen_ext16u_tl(t1, t1);
76a66253
JM		 5262 break;
5263 case 0x0D:
5264 /* maclhw - maclhw. - maclhwo - maclhwo. */
5265 /* maclhws - maclhws. - maclhwso - maclhwso. */
5266 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5267 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5268 /* mullhw - mullhw. */
182608d4
AJ		 5269 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5270 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5271 break;
5272 case 0x0C:
5273 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5274 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5275 /* mullhwu - mullhwu. */
182608d4
AJ		 5276 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5277 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
76a66253
JM		 5278 break;
5279 }
76a66253 5280 if (opc2 & 0x04) {
182608d4
AJ		 5281 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5282 tcg_gen_mul_tl(t1, t0, t1);
5283 if (opc2 & 0x02) {
5284 /* nmultiply-and-accumulate (0x0E) */
5285 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5286 } else {
5287 /* multiply-and-accumulate (0x0C) */
5288 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5289 }
5290
5291 if (opc3 & 0x12) {
5292 /* Check overflow and/or saturate */
5293 int l1 = gen_new_label();
5294
5295 if (opc3 & 0x10) {
5296 /* Start with XER OV disabled, the most likely case */
5297 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
5298 }
5299 if (opc3 & 0x01) {
5300 /* Signed */
5301 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5302 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5303 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5304 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5305 if (opc3 & 0x02) {
5306 /* Saturate */
5307 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5308 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5309 }
5310 } else {
5311 /* Unsigned */
5312 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5313 if (opc3 & 0x02) {
5314 /* Saturate */
5315 tcg_gen_movi_tl(t0, UINT32_MAX);
5316 }
5317 }
5318 if (opc3 & 0x10) {
5319 /* Check overflow */
5320 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
5321 }
5322 gen_set_label(l1);
5323 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5324 }
5325 } else {
5326 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
76a66253 5327 }
182608d4
AJ		 5328 tcg_temp_free(t0);
5329 tcg_temp_free(t1);
76a66253
JM		 5330 if (unlikely(Rc) != 0) {
5331 /* Update Rc0 */
182608d4 5332 gen_set_Rc0(ctx, cpu_gpr[rt]);
76a66253
JM		 5333 }
5334}
5335
a750fc0b
JM		 5336#define GEN_MAC_HANDLER(name, opc2, opc3) \
5337GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) \
76a66253
JM		 5338{ \
5339 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5340 rD(ctx->opcode), Rc(ctx->opcode)); \
5341}
5342
5343/* macchw - macchw. */
a750fc0b 5344GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
76a66253 5345/* macchwo - macchwo. */
a750fc0b 5346GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
76a66253 5347/* macchws - macchws. */
a750fc0b 5348GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
76a66253 5349/* macchwso - macchwso. */
a750fc0b 5350GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
76a66253 5351/* macchwsu - macchwsu. */
a750fc0b 5352GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
76a66253 5353/* macchwsuo - macchwsuo. */
a750fc0b 5354GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
76a66253 5355/* macchwu - macchwu. */
a750fc0b 5356GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
76a66253 5357/* macchwuo - macchwuo. */
a750fc0b 5358GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
76a66253 5359/* machhw - machhw. */
a750fc0b 5360GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
76a66253 5361/* machhwo - machhwo. */
a750fc0b 5362GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
76a66253 5363/* machhws - machhws. */
a750fc0b 5364GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
76a66253 5365/* machhwso - machhwso. */
a750fc0b 5366GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
76a66253 5367/* machhwsu - machhwsu. */
a750fc0b 5368GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
76a66253 5369/* machhwsuo - machhwsuo. */
a750fc0b 5370GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
76a66253 5371/* machhwu - machhwu. */
a750fc0b 5372GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
76a66253 5373/* machhwuo - machhwuo. */
a750fc0b 5374GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
76a66253 5375/* maclhw - maclhw. */
a750fc0b 5376GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
76a66253 5377/* maclhwo - maclhwo. */
a750fc0b 5378GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
76a66253 5379/* maclhws - maclhws. */
a750fc0b 5380GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
76a66253 5381/* maclhwso - maclhwso. */
a750fc0b 5382GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
76a66253 5383/* maclhwu - maclhwu. */
a750fc0b 5384GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
76a66253 5385/* maclhwuo - maclhwuo. */
a750fc0b 5386GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
76a66253 5387/* maclhwsu - maclhwsu. */
a750fc0b 5388GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
76a66253 5389/* maclhwsuo - maclhwsuo. */
a750fc0b 5390GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
76a66253 5391/* nmacchw - nmacchw. */
a750fc0b 5392GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
76a66253 5393/* nmacchwo - nmacchwo. */
a750fc0b 5394GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
76a66253 5395/* nmacchws - nmacchws. */
a750fc0b 5396GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
76a66253 5397/* nmacchwso - nmacchwso. */
a750fc0b 5398GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
76a66253 5399/* nmachhw - nmachhw. */
a750fc0b 5400GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
76a66253 5401/* nmachhwo - nmachhwo. */
a750fc0b 5402GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
76a66253 5403/* nmachhws - nmachhws. */
a750fc0b 5404GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
76a66253 5405/* nmachhwso - nmachhwso. */
a750fc0b 5406GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
76a66253 5407/* nmaclhw - nmaclhw. */
a750fc0b 5408GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
76a66253 5409/* nmaclhwo - nmaclhwo. */
a750fc0b 5410GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
76a66253 5411/* nmaclhws - nmaclhws. */
a750fc0b 5412GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
76a66253 5413/* nmaclhwso - nmaclhwso. */
a750fc0b 5414GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
76a66253
JM		 5415
5416/* mulchw - mulchw. */
a750fc0b 5417GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
76a66253 5418/* mulchwu - mulchwu. */
a750fc0b 5419GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
76a66253 5420/* mulhhw - mulhhw. */
a750fc0b 5421GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
76a66253 5422/* mulhhwu - mulhhwu. */
a750fc0b 5423GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
76a66253 5424/* mullhw - mullhw. */
a750fc0b 5425GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
76a66253 5426/* mullhwu - mullhwu. */
a750fc0b 5427GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
76a66253
JM		 5428
5429/* mfdcr */
05332d70 5430GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
76a66253
JM		 5431{
5432#if defined(CONFIG_USER_ONLY)
e1833e1f 5433 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5434#else
5435 uint32_t dcrn = SPR(ctx->opcode);
5436
5437 if (unlikely(!ctx->supervisor)) {
e1833e1f 5438 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5439 return;
5440 }
86c581dc 5441 tcg_gen_movi_tl(cpu_T[0], dcrn);
a42bd6cc 5442 gen_op_load_dcr();
f78fb44e 5443 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5444#endif
5445}
5446
5447/* mtdcr */
05332d70 5448GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
76a66253
JM		 5449{
5450#if defined(CONFIG_USER_ONLY)
e1833e1f 5451 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5452#else
5453 uint32_t dcrn = SPR(ctx->opcode);
5454
5455 if (unlikely(!ctx->supervisor)) {
e1833e1f 5456 GEN_EXCP_PRIVREG(ctx);
76a66253
JM		 5457 return;
5458 }
86c581dc 5459 tcg_gen_movi_tl(cpu_T[0], dcrn);
f78fb44e 5460 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc
JM		 5461 gen_op_store_dcr();
5462#endif
5463}
5464
5465/* mfdcrx */
2662a059 5466/* XXX: not implemented on 440 ? */
05332d70 5467GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5468{
5469#if defined(CONFIG_USER_ONLY)
e1833e1f 5470 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5471#else
5472 if (unlikely(!ctx->supervisor)) {
e1833e1f 5473 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5474 return;
5475 }
f78fb44e 5476 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a42bd6cc 5477 gen_op_load_dcr();
f78fb44e 5478 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b 5479 /* Note: Rc update flag set leads to undefined state of Rc0 */
a42bd6cc
JM		 5480#endif
5481}
5482
5483/* mtdcrx */
2662a059 5484/* XXX: not implemented on 440 ? */
05332d70 5485GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
a42bd6cc
JM		 5486{
5487#if defined(CONFIG_USER_ONLY)
e1833e1f 5488 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5489#else
5490 if (unlikely(!ctx->supervisor)) {
e1833e1f 5491 GEN_EXCP_PRIVREG(ctx);
a42bd6cc
JM		 5492 return;
5493 }
f78fb44e
AJ		 5494 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5495 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a42bd6cc 5496 gen_op_store_dcr();
a750fc0b 5497 /* Note: Rc update flag set leads to undefined state of Rc0 */
76a66253
JM		 5498#endif
5499}
5500
a750fc0b
JM		 5501/* mfdcrux (PPC 460) : user-mode access to DCR */
5502GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
5503{
f78fb44e 5504 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a750fc0b 5505 gen_op_load_dcr();
f78fb44e 5506 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
a750fc0b
JM		 5507 /* Note: Rc update flag set leads to undefined state of Rc0 */
5508}
5509
5510/* mtdcrux (PPC 460) : user-mode access to DCR */
5511GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
5512{
f78fb44e
AJ		 5513 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5514 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a750fc0b
JM		 5515 gen_op_store_dcr();
5516 /* Note: Rc update flag set leads to undefined state of Rc0 */
5517}
5518
76a66253
JM		 5519/* dccci */
5520GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON)
5521{
5522#if defined(CONFIG_USER_ONLY)
e1833e1f 5523 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5524#else
5525 if (unlikely(!ctx->supervisor)) {
e1833e1f 5526 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5527 return;
5528 }
5529 /* interpreted as no-op */
5530#endif
5531}
5532
5533/* dcread */
5534GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
5535{
5536#if defined(CONFIG_USER_ONLY)
e1833e1f 5537 GEN_EXCP_PRIVOPC(ctx);
76a66253 5538#else
b61f2753 5539 TCGv EA, val;
76a66253 5540 if (unlikely(!ctx->supervisor)) {
e1833e1f 5541 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5542 return;
5543 }
b61f2753
AJ		 5544 EA = tcg_temp_new(TCG_TYPE_TL);
5545 gen_addr_reg_index(EA, ctx);
5546 val = tcg_temp_new(TCG_TYPE_TL);
5547 gen_qemu_ld32u(val, EA, ctx->mem_idx);
5548 tcg_temp_free(val);
5549 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5550 tcg_temp_free(EA);
76a66253
JM		 5551#endif
5552}
5553
5554/* icbt */
c7697e1f 5555GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT)
76a66253
JM		 5556{
5557 /* interpreted as no-op */
5558 /* XXX: specification say this is treated as a load by the MMU
5559 * but does not generate any exception
5560 */
5561}
5562
5563/* iccci */
5564GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON)
5565{
5566#if defined(CONFIG_USER_ONLY)
e1833e1f 5567 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5568#else
5569 if (unlikely(!ctx->supervisor)) {
e1833e1f 5570 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5571 return;
5572 }
5573 /* interpreted as no-op */
5574#endif
5575}
5576
5577/* icread */
5578GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON)
5579{
5580#if defined(CONFIG_USER_ONLY)
e1833e1f 5581 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5582#else
5583 if (unlikely(!ctx->supervisor)) {
e1833e1f 5584 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5585 return;
5586 }
5587 /* interpreted as no-op */
5588#endif
5589}
5590
5591/* rfci (supervisor only) */
c7697e1f 5592GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP)
a42bd6cc
JM		 5593{
5594#if defined(CONFIG_USER_ONLY)
e1833e1f 5595 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5596#else
5597 if (unlikely(!ctx->supervisor)) {
e1833e1f 5598 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5599 return;
5600 }
5601 /* Restore CPU state */
5602 gen_op_40x_rfci();
e1833e1f 5603 GEN_SYNC(ctx);
a42bd6cc
JM		 5604#endif
5605}
5606
5607GEN_HANDLER(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE)
5608{
5609#if defined(CONFIG_USER_ONLY)
e1833e1f 5610 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5611#else
5612 if (unlikely(!ctx->supervisor)) {
e1833e1f 5613 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5614 return;
5615 }
5616 /* Restore CPU state */
5617 gen_op_rfci();
e1833e1f 5618 GEN_SYNC(ctx);
a42bd6cc
JM		 5619#endif
5620}
5621
5622/* BookE specific */
2662a059 5623/* XXX: not implemented on 440 ? */
05332d70 5624GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI)
76a66253
JM		 5625{
5626#if defined(CONFIG_USER_ONLY)
e1833e1f 5627 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5628#else
5629 if (unlikely(!ctx->supervisor)) {
e1833e1f 5630 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5631 return;
5632 }
5633 /* Restore CPU state */
a42bd6cc 5634 gen_op_rfdi();
e1833e1f 5635 GEN_SYNC(ctx);
76a66253
JM		 5636#endif
5637}
5638
2662a059 5639/* XXX: not implemented on 440 ? */
a750fc0b 5640GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI)
a42bd6cc
JM		 5641{
5642#if defined(CONFIG_USER_ONLY)
e1833e1f 5643 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5644#else
5645 if (unlikely(!ctx->supervisor)) {
e1833e1f 5646 GEN_EXCP_PRIVOPC(ctx);
a42bd6cc
JM		 5647 return;
5648 }
5649 /* Restore CPU state */
5650 gen_op_rfmci();
e1833e1f 5651 GEN_SYNC(ctx);
a42bd6cc
JM		 5652#endif
5653}
5eb7995e 5654
d9bce9d9 5655/* TLB management - PowerPC 405 implementation */
76a66253 5656/* tlbre */
c7697e1f 5657GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
76a66253
JM		 5658{
5659#if defined(CONFIG_USER_ONLY)
e1833e1f 5660 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5661#else
5662 if (unlikely(!ctx->supervisor)) {
e1833e1f 5663 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5664 return;
5665 }
5666 switch (rB(ctx->opcode)) {
5667 case 0:
f78fb44e 5668 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5669 gen_op_4xx_tlbre_hi();
f78fb44e 5670 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5671 break;
5672 case 1:
f78fb44e 5673 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
76a66253 5674 gen_op_4xx_tlbre_lo();
f78fb44e 5675 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253
JM		 5676 break;
5677 default:
e1833e1f 5678 GEN_EXCP_INVAL(ctx);
76a66253 5679 break;
9a64fbe4 5680 }
76a66253
JM		 5681#endif
5682}
5683
d9bce9d9 5684/* tlbsx - tlbsx. */
c7697e1f 5685GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
76a66253
JM		 5686{
5687#if defined(CONFIG_USER_ONLY)
e1833e1f 5688 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5689#else
5690 if (unlikely(!ctx->supervisor)) {
e1833e1f 5691 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5692 return;
5693 }
e2be8d8d 5694 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5695 gen_op_4xx_tlbsx();
76a66253 5696 if (Rc(ctx->opcode))
daf4f96e 5697 gen_op_4xx_tlbsx_check();
f78fb44e 5698 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
76a66253 5699#endif
79aceca5
FB		 5700}
5701
76a66253 5702/* tlbwe */
c7697e1f 5703GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
79aceca5 5704{
76a66253 5705#if defined(CONFIG_USER_ONLY)
e1833e1f 5706 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5707#else
5708 if (unlikely(!ctx->supervisor)) {
e1833e1f 5709 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5710 return;
5711 }
5712 switch (rB(ctx->opcode)) {
5713 case 0:
f78fb44e
AJ		 5714 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5715 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5716 gen_op_4xx_tlbwe_hi();
5717 break;
5718 case 1:
f78fb44e
AJ		 5719 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5720 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
76a66253
JM		 5721 gen_op_4xx_tlbwe_lo();
5722 break;
5723 default:
e1833e1f 5724 GEN_EXCP_INVAL(ctx);
76a66253 5725 break;
9a64fbe4 5726 }
76a66253
JM		 5727#endif
5728}
5729
a4bb6c3e 5730/* TLB management - PowerPC 440 implementation */
5eb7995e 5731/* tlbre */
c7697e1f 5732GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5733{
5734#if defined(CONFIG_USER_ONLY)
e1833e1f 5735 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5736#else
5737 if (unlikely(!ctx->supervisor)) {
e1833e1f 5738 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5739 return;
5740 }
5741 switch (rB(ctx->opcode)) {
5742 case 0:
5eb7995e 5743 case 1:
5eb7995e 5744 case 2:
f78fb44e 5745 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
a4bb6c3e 5746 gen_op_440_tlbre(rB(ctx->opcode));
f78fb44e 5747 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5748 break;
5749 default:
e1833e1f 5750 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5751 break;
5752 }
5753#endif
5754}
5755
5756/* tlbsx - tlbsx. */
c7697e1f 5757GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
5eb7995e
JM		 5758{
5759#if defined(CONFIG_USER_ONLY)
e1833e1f 5760 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5761#else
5762 if (unlikely(!ctx->supervisor)) {
e1833e1f 5763 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5764 return;
5765 }
e2be8d8d 5766 gen_addr_reg_index(cpu_T[0], ctx);
daf4f96e 5767 gen_op_440_tlbsx();
5eb7995e 5768 if (Rc(ctx->opcode))
daf4f96e 5769 gen_op_4xx_tlbsx_check();
f78fb44e 5770 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
5eb7995e
JM		 5771#endif
5772}
5773
5774/* tlbwe */
c7697e1f 5775GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
5eb7995e
JM		 5776{
5777#if defined(CONFIG_USER_ONLY)
e1833e1f 5778 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5779#else
5780 if (unlikely(!ctx->supervisor)) {
e1833e1f 5781 GEN_EXCP_PRIVOPC(ctx);
5eb7995e
JM		 5782 return;
5783 }
5784 switch (rB(ctx->opcode)) {
5785 case 0:
5eb7995e 5786 case 1:
5eb7995e 5787 case 2:
f78fb44e
AJ		 5788 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
5789 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
a4bb6c3e 5790 gen_op_440_tlbwe(rB(ctx->opcode));
5eb7995e
JM		 5791 break;
5792 default:
e1833e1f 5793 GEN_EXCP_INVAL(ctx);
5eb7995e
JM		 5794 break;
5795 }
5796#endif
5797}
5798
76a66253 5799/* wrtee */
05332d70 5800GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
76a66253
JM		 5801{
5802#if defined(CONFIG_USER_ONLY)
e1833e1f 5803 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5804#else
5805 if (unlikely(!ctx->supervisor)) {
e1833e1f 5806 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5807 return;
5808 }
f78fb44e 5809 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
a42bd6cc 5810 gen_op_wrte();
dee96f6c
JM		 5811 /* Stop translation to have a chance to raise an exception
5812 * if we just set msr_ee to 1
5813 */
e1833e1f 5814 GEN_STOP(ctx);
76a66253
JM		 5815#endif
5816}
5817
5818/* wrteei */
05332d70 5819GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
76a66253
JM		 5820{
5821#if defined(CONFIG_USER_ONLY)
e1833e1f 5822 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5823#else
5824 if (unlikely(!ctx->supervisor)) {
e1833e1f 5825 GEN_EXCP_PRIVOPC(ctx);
76a66253
JM		 5826 return;
5827 }
86c581dc 5828 tcg_gen_movi_tl(cpu_T[0], ctx->opcode & 0x00010000);
a42bd6cc 5829 gen_op_wrte();
dee96f6c
JM		 5830 /* Stop translation to have a chance to raise an exception
5831 * if we just set msr_ee to 1
5832 */
e1833e1f 5833 GEN_STOP(ctx);
76a66253
JM		 5834#endif
5835}
5836
08e46e54 5837/* PowerPC 440 specific instructions */
76a66253
JM		 5838/* dlmzb */
5839GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
5840{
f78fb44e
AJ		 5841 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
5842 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
76a66253 5843 gen_op_440_dlmzb();
f78fb44e 5844 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
3d7b417e
AJ		 5845 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5846 tcg_gen_or_tl(cpu_xer, cpu_xer, cpu_T[0]);
76a66253
JM		 5847 if (Rc(ctx->opcode)) {
5848 gen_op_440_dlmzb_update_Rc();
47e4661c 5849 tcg_gen_andi_i32(cpu_crf[0], cpu_T[0], 0xf);
76a66253
JM		 5850 }
5851}
5852
5853/* mbar replaces eieio on 440 */
5854GEN_HANDLER(mbar, 0x1F, 0x16, 0x13, 0x001FF801, PPC_BOOKE)
5855{
5856 /* interpreted as no-op */
5857}
5858
5859/* msync replaces sync on 440 */
0db1b20e 5860GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE)
76a66253
JM		 5861{
5862 /* interpreted as no-op */
5863}
5864
5865/* icbt */
c7697e1f 5866GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
76a66253
JM		 5867{
5868 /* interpreted as no-op */
5869 /* XXX: specification say this is treated as a load by the MMU
5870 * but does not generate any exception
5871 */
79aceca5
FB		 5872}
5873
a9d9eb8f
JM		 5874/*** Altivec vector extension ***/
5875/* Altivec registers moves */
a9d9eb8f 5876
1d542695
AJ		 5877static always_inline void gen_load_avr(int t, int reg) {
5878 tcg_gen_mov_i64(cpu_AVRh[t], cpu_avrh[reg]);
5879 tcg_gen_mov_i64(cpu_AVRl[t], cpu_avrl[reg]);
5880}
5881
5882static always_inline void gen_store_avr(int reg, int t) {
5883 tcg_gen_mov_i64(cpu_avrh[reg], cpu_AVRh[t]);
5884 tcg_gen_mov_i64(cpu_avrl[reg], cpu_AVRl[t]);
5885}
a9d9eb8f
JM		 5886
5887#define op_vr_ldst(name) (*gen_op_##name[ctx->mem_idx])()
a9d9eb8f 5888#define OP_VR_LD_TABLE(name) \
7863667f
JM		 5889static GenOpFunc *gen_op_vr_l##name[NB_MEM_FUNCS] = { \
5890 GEN_MEM_FUNCS(vr_l##name), \
a9d9eb8f
JM		 5891};
5892#define OP_VR_ST_TABLE(name) \
7863667f
JM		 5893static GenOpFunc *gen_op_vr_st##name[NB_MEM_FUNCS] = { \
5894 GEN_MEM_FUNCS(vr_st##name), \
a9d9eb8f 5895};
a9d9eb8f
JM		 5896
5897#define GEN_VR_LDX(name, opc2, opc3) \
5898GEN_HANDLER(l##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5899{ \
5900 if (unlikely(!ctx->altivec_enabled)) { \
5901 GEN_EXCP_NO_VR(ctx); \
5902 return; \
5903 } \
e2be8d8d 5904 gen_addr_reg_index(cpu_T[0], ctx); \
a9d9eb8f 5905 op_vr_ldst(vr_l##name); \
1d542695 5906 gen_store_avr(rD(ctx->opcode), 0); \
a9d9eb8f
JM		 5907}
5908
5909#define GEN_VR_STX(name, opc2, opc3) \
5910GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC) \
5911{ \
5912 if (unlikely(!ctx->altivec_enabled)) { \
5913 GEN_EXCP_NO_VR(ctx); \
5914 return; \
5915 } \
e2be8d8d 5916 gen_addr_reg_index(cpu_T[0], ctx); \
1d542695 5917 gen_load_avr(0, rS(ctx->opcode)); \
a9d9eb8f
JM		 5918 op_vr_ldst(vr_st##name); \
5919}
5920
5921OP_VR_LD_TABLE(vx);
5922GEN_VR_LDX(vx, 0x07, 0x03);
5923/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
5924#define gen_op_vr_lvxl gen_op_vr_lvx
5925GEN_VR_LDX(vxl, 0x07, 0x0B);
5926
5927OP_VR_ST_TABLE(vx);
5928GEN_VR_STX(vx, 0x07, 0x07);
5929/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
5930#define gen_op_vr_stvxl gen_op_vr_stvx
5931GEN_VR_STX(vxl, 0x07, 0x0F);
5932
0487d6a8 5933/*** SPE extension ***/
0487d6a8 5934/* Register moves */
3cd7d1dd 5935
f78fb44e
AJ		 5936static always_inline void gen_load_gpr64(TCGv t, int reg) {
5937#if defined(TARGET_PPC64)
5938 tcg_gen_mov_i64(t, cpu_gpr[reg]);
5939#else
36aa55dc 5940 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
3cd7d1dd 5941#endif
f78fb44e 5942}
3cd7d1dd 5943
f78fb44e
AJ		 5944static always_inline void gen_store_gpr64(int reg, TCGv t) {
5945#if defined(TARGET_PPC64)
5946 tcg_gen_mov_i64(cpu_gpr[reg], t);
5947#else
5948 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
19f98ff6 5949 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
f78fb44e
AJ		 5950 tcg_gen_shri_i64(tmp, t, 32);
5951 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
5952 tcg_temp_free(tmp);
3cd7d1dd 5953#endif
f78fb44e 5954}
3cd7d1dd 5955
0487d6a8
JM		 5956#define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5957GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
5958{ \
5959 if (Rc(ctx->opcode)) \
5960 gen_##name1(ctx); \
5961 else \
5962 gen_##name0(ctx); \
5963}
5964
5965/* Handler for undefined SPE opcodes */
b068d6a7 5966static always_inline void gen_speundef (DisasContext *ctx)
0487d6a8 5967{
e1833e1f 5968 GEN_EXCP_INVAL(ctx);
0487d6a8
JM		 5969}
5970
5971/* SPE load and stores */
f0aabd1a 5972static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh)
0487d6a8
JM		 5973{
5974 target_long simm = rB(ctx->opcode);
5975
f0aabd1a
AJ		 5976 if (rA(ctx->opcode) == 0)
5977 tcg_gen_movi_tl(EA, simm << sh);
5978 else if (likely(simm != 0))
5979 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh);
5980 else
5981 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
0487d6a8
JM		 5982}
5983
5984#define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])()
0487d6a8 5985#define OP_SPE_LD_TABLE(name) \
7863667f
JM		 5986static GenOpFunc *gen_op_spe_l##name[NB_MEM_FUNCS] = { \
5987 GEN_MEM_FUNCS(spe_l##name), \
0487d6a8
JM		 5988};
5989#define OP_SPE_ST_TABLE(name) \
7863667f
JM		 5990static GenOpFunc *gen_op_spe_st##name[NB_MEM_FUNCS] = { \
5991 GEN_MEM_FUNCS(spe_st##name), \
2857068e 5992};
0487d6a8
JM		 5993
5994#define GEN_SPE_LD(name, sh) \
b068d6a7 5995static always_inline void gen_evl##name (DisasContext *ctx) \
0487d6a8
JM		 5996{ \
5997 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 5998 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 5999 return; \
6000 } \
f0aabd1a 6001 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
0487d6a8 6002 op_spe_ldst(spe_l##name); \
f78fb44e 6003 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 6004}
6005
6006#define GEN_SPE_LDX(name) \
b068d6a7 6007static always_inline void gen_evl##name##x (DisasContext *ctx) \
0487d6a8
JM		 6008{ \
6009 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6010 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6011 return; \
6012 } \
e2be8d8d 6013 gen_addr_reg_index(cpu_T[0], ctx); \
0487d6a8 6014 op_spe_ldst(spe_l##name); \
f78fb44e 6015 gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \
0487d6a8
JM		 6016}
6017
6018#define GEN_SPEOP_LD(name, sh) \
6019OP_SPE_LD_TABLE(name); \
6020GEN_SPE_LD(name, sh); \
6021GEN_SPE_LDX(name)
6022
6023#define GEN_SPE_ST(name, sh) \
b068d6a7 6024static always_inline void gen_evst##name (DisasContext *ctx) \
0487d6a8
JM		 6025{ \
6026 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6027 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6028 return; \
6029 } \
f0aabd1a 6030 gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \
f78fb44e 6031 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 6032 op_spe_ldst(spe_st##name); \
6033}
6034
6035#define GEN_SPE_STX(name) \
b068d6a7 6036static always_inline void gen_evst##name##x (DisasContext *ctx) \
0487d6a8
JM		 6037{ \
6038 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6039 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6040 return; \
6041 } \
e2be8d8d 6042 gen_addr_reg_index(cpu_T[0], ctx); \
f78fb44e 6043 gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \
0487d6a8
JM		 6044 op_spe_ldst(spe_st##name); \
6045}
6046
6047#define GEN_SPEOP_ST(name, sh) \
6048OP_SPE_ST_TABLE(name); \
6049GEN_SPE_ST(name, sh); \
6050GEN_SPE_STX(name)
6051
6052#define GEN_SPEOP_LDST(name, sh) \
6053GEN_SPEOP_LD(name, sh); \
6054GEN_SPEOP_ST(name, sh)
6055
6056/* SPE arithmetic and logic */
6057#define GEN_SPEOP_ARITH2(name) \
b068d6a7 6058static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6059{ \
6060 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6061 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6062 return; \
6063 } \
f78fb44e
AJ		 6064 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6065 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 6066 gen_op_##name(); \
f78fb44e 6067 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6068}
6069
cf960816 6070#define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \
3d3a6a0a
AJ		 6071static always_inline void gen_##name (DisasContext *ctx) \
6072{ \
6073 if (unlikely(!ctx->spe_enabled)) { \
6074 GEN_EXCP_NO_AP(ctx); \
6075 return; \
6076 } \
6077 TCGv t0 = tcg_temp_new(TCG_TYPE_I64); \
6078 TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
6079 gen_load_gpr64(t0, rA(ctx->opcode)); \
6080 gen_load_gpr64(t1, rB(ctx->opcode)); \
cf960816 6081 tcg_op(t0, t0, t1); \
3d3a6a0a
AJ		 6082 gen_store_gpr64(rD(ctx->opcode), t0); \
6083 tcg_temp_free(t0); \
6084 tcg_temp_free(t1); \
6085}
6086
0487d6a8 6087#define GEN_SPEOP_ARITH1(name) \
b068d6a7 6088static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6089{ \
6090 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6091 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6092 return; \
6093 } \
f78fb44e 6094 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8 6095 gen_op_##name(); \
f78fb44e 6096 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6097}
6098
6099#define GEN_SPEOP_COMP(name) \
b068d6a7 6100static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8
JM		 6101{ \
6102 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6103 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6104 return; \
6105 } \
f78fb44e
AJ		 6106 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
6107 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode)); \
0487d6a8 6108 gen_op_##name(); \
47e4661c 6109 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_T[0], 0xf); \
0487d6a8
JM		 6110}
6111
6112/* Logical */
cf960816
AJ		 6113GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64);
6114GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64);
6115GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64);
6116GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64);
6117GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64);
6118GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64);
6119GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64);
6120GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64);
0487d6a8
JM		 6121GEN_SPEOP_ARITH2(evsrwu);
6122GEN_SPEOP_ARITH2(evsrws);
6123GEN_SPEOP_ARITH2(evslw);
6124GEN_SPEOP_ARITH2(evrlw);
6125GEN_SPEOP_ARITH2(evmergehi);
6126GEN_SPEOP_ARITH2(evmergelo);
6127GEN_SPEOP_ARITH2(evmergehilo);
6128GEN_SPEOP_ARITH2(evmergelohi);
6129
6130/* Arithmetic */
6131GEN_SPEOP_ARITH2(evaddw);
6132GEN_SPEOP_ARITH2(evsubfw);
6133GEN_SPEOP_ARITH1(evabs);
6134GEN_SPEOP_ARITH1(evneg);
6135GEN_SPEOP_ARITH1(evextsb);
6136GEN_SPEOP_ARITH1(evextsh);
6137GEN_SPEOP_ARITH1(evrndw);
6138GEN_SPEOP_ARITH1(evcntlzw);
6139GEN_SPEOP_ARITH1(evcntlsw);
b068d6a7 6140static always_inline void gen_brinc (DisasContext *ctx)
0487d6a8
JM		 6141{
6142 /* Note: brinc is usable even if SPE is disabled */
f78fb44e
AJ		 6143 tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
6144 tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
0487d6a8 6145 gen_op_brinc();
f78fb44e 6146 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
0487d6a8
JM		 6147}
6148
6149#define GEN_SPEOP_ARITH_IMM2(name) \
b068d6a7 6150static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 6151{ \
6152 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6153 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6154 return; \
6155 } \
f78fb44e 6156 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8
JM		 6157 gen_op_splatwi_T1_64(rA(ctx->opcode)); \
6158 gen_op_##name(); \
f78fb44e 6159 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6160}
6161
6162#define GEN_SPEOP_LOGIC_IMM2(name) \
b068d6a7 6163static always_inline void gen_##name##i (DisasContext *ctx) \
0487d6a8
JM		 6164{ \
6165 if (unlikely(!ctx->spe_enabled)) { \
e1833e1f 6166 GEN_EXCP_NO_AP(ctx); \
0487d6a8
JM		 6167 return; \
6168 } \
f78fb44e 6169 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode)); \
0487d6a8
JM		 6170 gen_op_splatwi_T1_64(rB(ctx->opcode)); \
6171 gen_op_##name(); \
f78fb44e 6172 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6173}
6174
6175GEN_SPEOP_ARITH_IMM2(evaddw);
6176#define gen_evaddiw gen_evaddwi
6177GEN_SPEOP_ARITH_IMM2(evsubfw);
6178#define gen_evsubifw gen_evsubfwi
6179GEN_SPEOP_LOGIC_IMM2(evslw);
6180GEN_SPEOP_LOGIC_IMM2(evsrwu);
6181#define gen_evsrwis gen_evsrwsi
6182GEN_SPEOP_LOGIC_IMM2(evsrws);
6183#define gen_evsrwiu gen_evsrwui
6184GEN_SPEOP_LOGIC_IMM2(evrlw);
6185
b068d6a7 6186static always_inline void gen_evsplati (DisasContext *ctx)
0487d6a8
JM		 6187{
6188 int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
6189
6190 gen_op_splatwi_T0_64(imm);
f78fb44e 6191 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 6192}
6193
b068d6a7 6194static always_inline void gen_evsplatfi (DisasContext *ctx)
0487d6a8
JM		 6195{
6196 uint32_t imm = rA(ctx->opcode) << 27;
6197
6198 gen_op_splatwi_T0_64(imm);
f78fb44e 6199 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 6200}
6201
6202/* Comparison */
6203GEN_SPEOP_COMP(evcmpgtu);
6204GEN_SPEOP_COMP(evcmpgts);
6205GEN_SPEOP_COMP(evcmpltu);
6206GEN_SPEOP_COMP(evcmplts);
6207GEN_SPEOP_COMP(evcmpeq);
6208
6209GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, PPC_SPE); ////
6210GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, PPC_SPE);
6211GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, PPC_SPE); ////
6212GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, PPC_SPE);
6213GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, PPC_SPE); ////
6214GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, PPC_SPE); ////
6215GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, PPC_SPE); ////
6216GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x00000000, PPC_SPE); //
6217GEN_SPE(speundef, evand, 0x08, 0x08, 0x00000000, PPC_SPE); ////
6218GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, PPC_SPE); ////
6219GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, PPC_SPE); ////
6220GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, PPC_SPE); ////
6221GEN_SPE(speundef, evorc, 0x0D, 0x08, 0x00000000, PPC_SPE); ////
6222GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, PPC_SPE); ////
6223GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, PPC_SPE); ////
6224GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, PPC_SPE);
6225GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, PPC_SPE); ////
6226GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, PPC_SPE);
6227GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, PPC_SPE); //
6228GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, PPC_SPE);
6229GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, PPC_SPE); ////
6230GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, PPC_SPE); ////
6231GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, PPC_SPE); ////
6232GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, PPC_SPE); ////
6233GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
6234
b068d6a7 6235static always_inline void gen_evsel (DisasContext *ctx)
0487d6a8
JM		 6236{
6237 if (unlikely(!ctx->spe_enabled)) {
e1833e1f 6238 GEN_EXCP_NO_AP(ctx);
0487d6a8
JM		 6239 return;
6240 }
47e4661c 6241 tcg_gen_mov_i32(cpu_T[0], cpu_crf[ctx->opcode & 0x7]);
f78fb44e
AJ		 6242 gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
6243 gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
0487d6a8 6244 gen_op_evsel();
f78fb44e 6245 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
0487d6a8
JM		 6246}
6247
c7697e1f 6248GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6249{
6250 gen_evsel(ctx);
6251}
c7697e1f 6252GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6253{
6254 gen_evsel(ctx);
6255}
c7697e1f 6256GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6257{
6258 gen_evsel(ctx);
6259}
c7697e1f 6260GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE)
0487d6a8
JM		 6261{
6262 gen_evsel(ctx);
6263}
6264
6265/* Load and stores */
0487d6a8
JM		 6266GEN_SPEOP_LDST(dd, 3);
6267GEN_SPEOP_LDST(dw, 3);
6268GEN_SPEOP_LDST(dh, 3);
6269GEN_SPEOP_LDST(whe, 2);
6270GEN_SPEOP_LD(whou, 2);
6271GEN_SPEOP_LD(whos, 2);
6272GEN_SPEOP_ST(who, 2);
6273
0487d6a8 6274#define _GEN_OP_SPE_STWWE(suffix) \
b068d6a7 6275static always_inline void gen_op_spe_stwwe_##suffix (void) \
0487d6a8
JM		 6276{ \
6277 gen_op_srli32_T1_64(); \
6278 gen_op_spe_stwwo_##suffix(); \
6279}
6280#define _GEN_OP_SPE_STWWE_LE(suffix) \
b068d6a7 6281static always_inline void gen_op_spe_stwwe_le_##suffix (void) \
0487d6a8
JM		 6282{ \
6283 gen_op_srli32_T1_64(); \
6284 gen_op_spe_stwwo_le_##suffix(); \
6285}
6286#if defined(TARGET_PPC64)
6287#define GEN_OP_SPE_STWWE(suffix) \
6288_GEN_OP_SPE_STWWE(suffix); \
6289_GEN_OP_SPE_STWWE_LE(suffix); \
b068d6a7 6290static always_inline void gen_op_spe_stwwe_64_##suffix (void) \
0487d6a8
JM		 6291{ \
6292 gen_op_srli32_T1_64(); \
6293 gen_op_spe_stwwo_64_##suffix(); \
6294} \
b068d6a7 6295static always_inline void gen_op_spe_stwwe_le_64_##suffix (void) \
0487d6a8
JM		 6296{ \
6297 gen_op_srli32_T1_64(); \
6298 gen_op_spe_stwwo_le_64_##suffix(); \
6299}
6300#else
6301#define GEN_OP_SPE_STWWE(suffix) \
6302_GEN_OP_SPE_STWWE(suffix); \
6303_GEN_OP_SPE_STWWE_LE(suffix)
6304#endif
6305#if defined(CONFIG_USER_ONLY)
6306GEN_OP_SPE_STWWE(raw);
6307#else /* defined(CONFIG_USER_ONLY) */
0487d6a8 6308GEN_OP_SPE_STWWE(user);
7863667f
JM		 6309GEN_OP_SPE_STWWE(kernel);
6310GEN_OP_SPE_STWWE(hypv);
0487d6a8
JM		 6311#endif /* defined(CONFIG_USER_ONLY) */
6312GEN_SPEOP_ST(wwe, 2);
6313GEN_SPEOP_ST(wwo, 2);
6314
6315#define GEN_SPE_LDSPLAT(name, op, suffix) \
b068d6a7 6316static always_inline void gen_op_spe_l##name##_##suffix (void) \
0487d6a8
JM		 6317{ \
6318 gen_op_##op##_##suffix(); \
6319 gen_op_splatw_T1_64(); \
6320}
6321
6322#define GEN_OP_SPE_LHE(suffix) \
b068d6a7 6323static always_inline void gen_op_spe_lhe_##suffix (void) \
0487d6a8
JM		 6324{ \
6325 gen_op_spe_lh_##suffix(); \
6326 gen_op_sli16_T1_64(); \
6327}
6328
6329#define GEN_OP_SPE_LHX(suffix) \
b068d6a7 6330static always_inline void gen_op_spe_lhx_##suffix (void) \
0487d6a8
JM		 6331{ \
6332 gen_op_spe_lh_##suffix(); \
6333 gen_op_extsh_T1_64(); \
6334}
6335
6336#if defined(CONFIG_USER_ONLY)
6337GEN_OP_SPE_LHE(raw);
6338GEN_SPE_LDSPLAT(hhesplat, spe_lhe, raw);
6339GEN_OP_SPE_LHE(le_raw);
6340GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_raw);
6341GEN_SPE_LDSPLAT(hhousplat, spe_lh, raw);
6342GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_raw);
6343GEN_OP_SPE_LHX(raw);
6344GEN_SPE_LDSPLAT(hhossplat, spe_lhx, raw);
6345GEN_OP_SPE_LHX(le_raw);
6346GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_raw);
6347#if defined(TARGET_PPC64)
6348GEN_OP_SPE_LHE(64_raw);
6349GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_raw);
6350GEN_OP_SPE_LHE(le_64_raw);
6351GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_raw);
6352GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_raw);
6353GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_raw);
6354GEN_OP_SPE_LHX(64_raw);
6355GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_raw);
6356GEN_OP_SPE_LHX(le_64_raw);
6357GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_raw);
6358#endif
6359#else
0487d6a8 6360GEN_OP_SPE_LHE(user);
7863667f
JM		 6361GEN_OP_SPE_LHE(kernel);
6362GEN_OP_SPE_LHE(hypv);
0487d6a8 6363GEN_SPE_LDSPLAT(hhesplat, spe_lhe, user);
7863667f
JM		 6364GEN_SPE_LDSPLAT(hhesplat, spe_lhe, kernel);
6365GEN_SPE_LDSPLAT(hhesplat, spe_lhe, hypv);
0487d6a8 6366GEN_OP_SPE_LHE(le_user);
7863667f
JM		 6367GEN_OP_SPE_LHE(le_kernel);
6368GEN_OP_SPE_LHE(le_hypv);
0487d6a8 6369GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_user);
7863667f
JM		 6370GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_kernel);
6371GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_hypv);
0487d6a8 6372GEN_SPE_LDSPLAT(hhousplat, spe_lh, user);
7863667f
JM		 6373GEN_SPE_LDSPLAT(hhousplat, spe_lh, kernel);
6374GEN_SPE_LDSPLAT(hhousplat, spe_lh, hypv);
0487d6a8 6375GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_user);
7863667f
JM		 6376GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_kernel);
6377GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_hypv);
0487d6a8 6378GEN_OP_SPE_LHX(user);
7863667f
JM		 6379GEN_OP_SPE_LHX(kernel);
6380GEN_OP_SPE_LHX(hypv);
0487d6a8 6381GEN_SPE_LDSPLAT(hhossplat, spe_lhx, user);
7863667f
JM		 6382GEN_SPE_LDSPLAT(hhossplat, spe_lhx, kernel);
6383GEN_SPE_LDSPLAT(hhossplat, spe_lhx, hypv);
0487d6a8 6384GEN_OP_SPE_LHX(le_user);
7863667f
JM		 6385GEN_OP_SPE_LHX(le_kernel);
6386GEN_OP_SPE_LHX(le_hypv);
0487d6a8 6387GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_user);
7863667f
JM		 6388GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_kernel);
6389GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_hypv);
0487d6a8 6390#if defined(TARGET_PPC64)
0487d6a8 6391GEN_OP_SPE_LHE(64_user);
7863667f
JM		 6392GEN_OP_SPE_LHE(64_kernel);
6393GEN_OP_SPE_LHE(64_hypv);
0487d6a8 6394GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_user);
7863667f
JM		 6395GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_kernel);
6396GEN_SPE_LDSPLAT(hhesplat, spe_lhe, 64_hypv);
0487d6a8 6397GEN_OP_SPE_LHE(le_64_user);
7863667f
JM		 6398GEN_OP_SPE_LHE(le_64_kernel);
6399GEN_OP_SPE_LHE(le_64_hypv);
0487d6a8 6400GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_user);
7863667f
JM		 6401GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_kernel);
6402GEN_SPE_LDSPLAT(hhesplat, spe_lhe, le_64_hypv);
0487d6a8 6403GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_user);
7863667f
JM		 6404GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_kernel);
6405GEN_SPE_LDSPLAT(hhousplat, spe_lh, 64_hypv);
0487d6a8 6406GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_user);
7863667f
JM		 6407GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_kernel);
6408GEN_SPE_LDSPLAT(hhousplat, spe_lh, le_64_hypv);
0487d6a8 6409GEN_OP_SPE_LHX(64_user);
7863667f
JM		 6410GEN_OP_SPE_LHX(64_kernel);
6411GEN_OP_SPE_LHX(64_hypv);
0487d6a8 6412GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_user);
7863667f
JM		 6413GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_kernel);
6414GEN_SPE_LDSPLAT(hhossplat, spe_lhx, 64_hypv);
0487d6a8 6415GEN_OP_SPE_LHX(le_64_user);
7863667f
JM		 6416GEN_OP_SPE_LHX(le_64_kernel);
6417GEN_OP_SPE_LHX(le_64_hypv);
0487d6a8 6418GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_user);
7863667f
JM		 6419GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_kernel);
6420GEN_SPE_LDSPLAT(hhossplat, spe_lhx, le_64_hypv);
0487d6a8
JM		 6421#endif
6422#endif
6423GEN_SPEOP_LD(hhesplat, 1);
6424GEN_SPEOP_LD(hhousplat, 1);
6425GEN_SPEOP_LD(hhossplat, 1);
6426GEN_SPEOP_LD(wwsplat, 2);
6427GEN_SPEOP_LD(whsplat, 2);
6428
6429GEN_SPE(evlddx, evldd, 0x00, 0x0C, 0x00000000, PPC_SPE); //
6430GEN_SPE(evldwx, evldw, 0x01, 0x0C, 0x00000000, PPC_SPE); //
6431GEN_SPE(evldhx, evldh, 0x02, 0x0C, 0x00000000, PPC_SPE); //
6432GEN_SPE(evlhhesplatx, evlhhesplat, 0x04, 0x0C, 0x00000000, PPC_SPE); //
6433GEN_SPE(evlhhousplatx, evlhhousplat, 0x06, 0x0C, 0x00000000, PPC_SPE); //
6434GEN_SPE(evlhhossplatx, evlhhossplat, 0x07, 0x0C, 0x00000000, PPC_SPE); //
6435GEN_SPE(evlwhex, evlwhe, 0x08, 0x0C, 0x00000000, PPC_SPE); //
6436GEN_SPE(evlwhoux, evlwhou, 0x0A, 0x0C, 0x00000000, PPC_SPE); //
6437GEN_SPE(evlwhosx, evlwhos, 0x0B, 0x0C, 0x00000000, PPC_SPE); //
6438GEN_SPE(evlwwsplatx, evlwwsplat, 0x0C, 0x0C, 0x00000000, PPC_SPE); //
6439GEN_SPE(evlwhsplatx, evlwhsplat, 0x0E, 0x0C, 0x00000000, PPC_SPE); //
6440GEN_SPE(evstddx, evstdd, 0x10, 0x0C, 0x00000000, PPC_SPE); //
6441GEN_SPE(evstdwx, evstdw, 0x11, 0x0C, 0x00000000, PPC_SPE); //
6442GEN_SPE(evstdhx, evstdh, 0x12, 0x0C, 0x00000000, PPC_SPE); //
6443GEN_SPE(evstwhex, evstwhe, 0x18, 0x0C, 0x00000000, PPC_SPE); //
6444GEN_SPE(evstwhox, evstwho, 0x1A, 0x0C, 0x00000000, PPC_SPE); //
6445GEN_SPE(evstwwex, evstwwe, 0x1C, 0x0C, 0x00000000, PPC_SPE); //
6446GEN_SPE(evstwwox, evstwwo, 0x1E, 0x0C, 0x00000000, PPC_SPE); //
6447
6448/* Multiply and add - TODO */
6449#if 0
6450GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0x00000000, PPC_SPE);
6451GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0x00000000, PPC_SPE);
6452GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, PPC_SPE);
6453GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0x00000000, PPC_SPE);
6454GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, PPC_SPE);
6455GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0x00000000, PPC_SPE);
6456GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0x00000000, PPC_SPE);
6457GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0x00000000, PPC_SPE);
6458GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, PPC_SPE);
6459GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0x00000000, PPC_SPE);
6460GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, PPC_SPE);
6461GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0x00000000, PPC_SPE);
6462
6463GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0x00000000, PPC_SPE);
6464GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, PPC_SPE);
6465GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, PPC_SPE);
6466GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0x00000000, PPC_SPE);
6467GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0x00000000, PPC_SPE);
6468GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, PPC_SPE);
6469GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0x00000000, PPC_SPE);
6470GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0x00000000, PPC_SPE);
6471GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, PPC_SPE);
6472GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, PPC_SPE);
6473GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0x00000000, PPC_SPE);
6474GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0x00000000, PPC_SPE);
6475GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, PPC_SPE);
6476GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0x00000000, PPC_SPE);
6477
6478GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, PPC_SPE);
6479GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, PPC_SPE);
6480GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, PPC_SPE);
6481GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, PPC_SPE);
6482GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, PPC_SPE);
6483GEN_SPE(evmra, speundef, 0x07, 0x13, 0x0000F800, PPC_SPE);
6484
6485GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, PPC_SPE);
6486GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0x00000000, PPC_SPE);
6487GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, PPC_SPE);
6488GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0x00000000, PPC_SPE);
6489GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, PPC_SPE);
6490GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0x00000000, PPC_SPE);
6491GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, PPC_SPE);
6492GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0x00000000, PPC_SPE);
6493GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, PPC_SPE);
6494GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0x00000000, PPC_SPE);
6495GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, PPC_SPE);
6496GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0x00000000, PPC_SPE);
6497
6498GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, PPC_SPE);
6499GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, PPC_SPE);
6500GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0x00000000, PPC_SPE);
6501GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, PPC_SPE);
6502GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0x00000000, PPC_SPE);
6503
6504GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, PPC_SPE);
6505GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0x00000000, PPC_SPE);
6506GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, PPC_SPE);
6507GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0x00000000, PPC_SPE);
6508GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, PPC_SPE);
6509GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0x00000000, PPC_SPE);
6510GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, PPC_SPE);
6511GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0x00000000, PPC_SPE);
6512GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, PPC_SPE);
6513GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0x00000000, PPC_SPE);
6514GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, PPC_SPE);
6515GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0x00000000, PPC_SPE);
6516
6517GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, PPC_SPE);
6518GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, PPC_SPE);
6519GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0x00000000, PPC_SPE);
6520GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, PPC_SPE);
6521GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0x00000000, PPC_SPE);
6522#endif
6523
6524/*** SPE floating-point extension ***/
6525#define GEN_SPEFPUOP_CONV(name) \
b068d6a7 6526static always_inline void gen_##name (DisasContext *ctx) \
0487d6a8 6527{ \
f78fb44e 6528 gen_load_gpr64(cpu_T64[0], rB(ctx->opcode)); \
0487d6a8 6529 gen_op_##name(); \
f78fb44e 6530 gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
0487d6a8
JM		 6531}
6532
6533/* Single precision floating-point vectors operations */
6534/* Arithmetic */
6535GEN_SPEOP_ARITH2(evfsadd);
6536GEN_SPEOP_ARITH2(evfssub);
6537GEN_SPEOP_ARITH2(evfsmul);
6538GEN_SPEOP_ARITH2(evfsdiv);
6539GEN_SPEOP_ARITH1(evfsabs);
6540GEN_SPEOP_ARITH1(evfsnabs);
6541GEN_SPEOP_ARITH1(evfsneg);
6542/* Conversion */
6543GEN_SPEFPUOP_CONV(evfscfui);
6544GEN_SPEFPUOP_CONV(evfscfsi);
6545GEN_SPEFPUOP_CONV(evfscfuf);
6546GEN_SPEFPUOP_CONV(evfscfsf);
6547GEN_SPEFPUOP_CONV(evfsctui);
6548GEN_SPEFPUOP_CONV(evfsctsi);
6549GEN_SPEFPUOP_CONV(evfsctuf);
6550GEN_SPEFPUOP_CONV(evfsctsf);
6551GEN_SPEFPUOP_CONV(evfsctuiz);
6552GEN_SPEFPUOP_CONV(evfsctsiz);
6553/* Comparison */
6554GEN_SPEOP_COMP(evfscmpgt);
6555GEN_SPEOP_COMP(evfscmplt);
6556GEN_SPEOP_COMP(evfscmpeq);
6557GEN_SPEOP_COMP(evfststgt);
6558GEN_SPEOP_COMP(evfststlt);
6559GEN_SPEOP_COMP(evfststeq);
6560
6561/* Opcodes definitions */
6562GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, PPC_SPEFPU); //
6563GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, PPC_SPEFPU); //
6564GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, PPC_SPEFPU); //
6565GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, PPC_SPEFPU); //
6566GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, PPC_SPEFPU); //
6567GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, PPC_SPEFPU); //
6568GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, PPC_SPEFPU); //
6569GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, PPC_SPEFPU); //
6570GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, PPC_SPEFPU); //
6571GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, PPC_SPEFPU); //
6572GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, PPC_SPEFPU); //
6573GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, PPC_SPEFPU); //
6574GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, PPC_SPEFPU); //
6575GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, PPC_SPEFPU); //
6576
6577/* Single precision floating-point operations */
6578/* Arithmetic */
6579GEN_SPEOP_ARITH2(efsadd);
6580GEN_SPEOP_ARITH2(efssub);
6581GEN_SPEOP_ARITH2(efsmul);
6582GEN_SPEOP_ARITH2(efsdiv);
6583GEN_SPEOP_ARITH1(efsabs);
6584GEN_SPEOP_ARITH1(efsnabs);
6585GEN_SPEOP_ARITH1(efsneg);
6586/* Conversion */
6587GEN_SPEFPUOP_CONV(efscfui);
6588GEN_SPEFPUOP_CONV(efscfsi);
6589GEN_SPEFPUOP_CONV(efscfuf);
6590GEN_SPEFPUOP_CONV(efscfsf);
6591GEN_SPEFPUOP_CONV(efsctui);
6592GEN_SPEFPUOP_CONV(efsctsi);
6593GEN_SPEFPUOP_CONV(efsctuf);
6594GEN_SPEFPUOP_CONV(efsctsf);
6595GEN_SPEFPUOP_CONV(efsctuiz);
6596GEN_SPEFPUOP_CONV(efsctsiz);
6597GEN_SPEFPUOP_CONV(efscfd);
6598/* Comparison */
6599GEN_SPEOP_COMP(efscmpgt);
6600GEN_SPEOP_COMP(efscmplt);
6601GEN_SPEOP_COMP(efscmpeq);
6602GEN_SPEOP_COMP(efststgt);
6603GEN_SPEOP_COMP(efststlt);
6604GEN_SPEOP_COMP(efststeq);
6605
6606/* Opcodes definitions */
05332d70 6607GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, PPC_SPEFPU); //
0487d6a8
JM		 6608GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, PPC_SPEFPU); //
6609GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, PPC_SPEFPU); //
6610GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, PPC_SPEFPU); //
6611GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, PPC_SPEFPU); //
6612GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, PPC_SPEFPU); //
6613GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, PPC_SPEFPU); //
6614GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, PPC_SPEFPU); //
6615GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, PPC_SPEFPU); //
6616GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, PPC_SPEFPU); //
9ceb2a77
TS		 6617GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, PPC_SPEFPU); //
6618GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, PPC_SPEFPU); //
0487d6a8
JM		 6619GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, PPC_SPEFPU); //
6620GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, PPC_SPEFPU); //
6621
6622/* Double precision floating-point operations */
6623/* Arithmetic */
6624GEN_SPEOP_ARITH2(efdadd);
6625GEN_SPEOP_ARITH2(efdsub);
6626GEN_SPEOP_ARITH2(efdmul);
6627GEN_SPEOP_ARITH2(efddiv);
6628GEN_SPEOP_ARITH1(efdabs);
6629GEN_SPEOP_ARITH1(efdnabs);
6630GEN_SPEOP_ARITH1(efdneg);
6631/* Conversion */
6632
6633GEN_SPEFPUOP_CONV(efdcfui);
6634GEN_SPEFPUOP_CONV(efdcfsi);
6635GEN_SPEFPUOP_CONV(efdcfuf);
6636GEN_SPEFPUOP_CONV(efdcfsf);
6637GEN_SPEFPUOP_CONV(efdctui);
6638GEN_SPEFPUOP_CONV(efdctsi);
6639GEN_SPEFPUOP_CONV(efdctuf);
6640GEN_SPEFPUOP_CONV(efdctsf);
6641GEN_SPEFPUOP_CONV(efdctuiz);
6642GEN_SPEFPUOP_CONV(efdctsiz);
6643GEN_SPEFPUOP_CONV(efdcfs);
6644GEN_SPEFPUOP_CONV(efdcfuid);
6645GEN_SPEFPUOP_CONV(efdcfsid);
6646GEN_SPEFPUOP_CONV(efdctuidz);
6647GEN_SPEFPUOP_CONV(efdctsidz);
6648/* Comparison */
6649GEN_SPEOP_COMP(efdcmpgt);
6650GEN_SPEOP_COMP(efdcmplt);
6651GEN_SPEOP_COMP(efdcmpeq);
6652GEN_SPEOP_COMP(efdtstgt);
6653GEN_SPEOP_COMP(efdtstlt);
6654GEN_SPEOP_COMP(efdtsteq);
6655
6656/* Opcodes definitions */
6657GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, PPC_SPEFPU); //
6658GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, PPC_SPEFPU); //
6659GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, PPC_SPEFPU); //
6660GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, PPC_SPEFPU); //
6661GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, PPC_SPEFPU); //
6662GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, PPC_SPEFPU); //
6663GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, PPC_SPEFPU); //
6664GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, PPC_SPEFPU); //
6665GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, PPC_SPEFPU); //
6666GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, PPC_SPEFPU); //
6667GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, PPC_SPEFPU); //
6668GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, PPC_SPEFPU); //
6669GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, PPC_SPEFPU); //
6670GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, PPC_SPEFPU); //
6671GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, PPC_SPEFPU); //
6672GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, PPC_SPEFPU); //
0487d6a8 6673
79aceca5
FB		 6674/* End opcode list */
6675GEN_OPCODE_MARK(end);
6676
3fc6c082 6677#include "translate_init.c"
0411a972 6678#include "helper_regs.h"
79aceca5 6679
9a64fbe4 6680/*****************************************************************************/
3fc6c082 6681/* Misc PowerPC helpers */
36081602
JM		 6682void cpu_dump_state (CPUState *env, FILE *f,
6683 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6684 int flags)
79aceca5 6685{
3fc6c082
FB		 6686#define RGPL 4
6687#define RFPL 4
3fc6c082 6688
79aceca5
FB		 6689 int i;
6690
077fc206 6691 cpu_fprintf(f, "NIP " ADDRX " LR " ADDRX " CTR " ADDRX " XER %08x\n",
3d7b417e 6692 env->nip, env->lr, env->ctr, env->xer);
6b542af7
JM		 6693 cpu_fprintf(f, "MSR " ADDRX " HID0 " ADDRX " HF " ADDRX " idx %d\n",
6694 env->msr, env->spr[SPR_HID0], env->hflags, env->mmu_idx);
d9bce9d9 6695#if !defined(NO_TIMER_DUMP)
077fc206 6696 cpu_fprintf(f, "TB %08x %08x "
76a66253
JM		 6697#if !defined(CONFIG_USER_ONLY)
6698 "DECR %08x"
6699#endif
6700 "\n",
077fc206 6701 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
76a66253
JM		 6702#if !defined(CONFIG_USER_ONLY)
6703 , cpu_ppc_load_decr(env)
6704#endif
6705 );
077fc206 6706#endif
76a66253 6707 for (i = 0; i < 32; i++) {
3fc6c082
FB		 6708 if ((i & (RGPL - 1)) == 0)
6709 cpu_fprintf(f, "GPR%02d", i);
6b542af7 6710 cpu_fprintf(f, " " REGX, ppc_dump_gpr(env, i));
3fc6c082 6711 if ((i & (RGPL - 1)) == (RGPL - 1))
7fe48483 6712 cpu_fprintf(f, "\n");
76a66253 6713 }
3fc6c082 6714 cpu_fprintf(f, "CR ");
76a66253 6715 for (i = 0; i < 8; i++)
7fe48483
FB		 6716 cpu_fprintf(f, "%01x", env->crf[i]);
6717 cpu_fprintf(f, " [");
76a66253
JM		 6718 for (i = 0; i < 8; i++) {
6719 char a = '-';
6720 if (env->crf[i] & 0x08)
6721 a = 'L';
6722 else if (env->crf[i] & 0x04)
6723 a = 'G';
6724 else if (env->crf[i] & 0x02)
6725 a = 'E';
7fe48483 6726 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
76a66253 6727 }
6b542af7 6728 cpu_fprintf(f, " ] RES " ADDRX "\n", env->reserve);
3fc6c082
FB		 6729 for (i = 0; i < 32; i++) {
6730 if ((i & (RFPL - 1)) == 0)
6731 cpu_fprintf(f, "FPR%02d", i);
26a76461 6732 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
3fc6c082 6733 if ((i & (RFPL - 1)) == (RFPL - 1))
7fe48483 6734 cpu_fprintf(f, "\n");
79aceca5 6735 }
f2e63a42 6736#if !defined(CONFIG_USER_ONLY)
6b542af7 6737 cpu_fprintf(f, "SRR0 " ADDRX " SRR1 " ADDRX " SDR1 " ADDRX "\n",
3fc6c082 6738 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
f2e63a42 6739#endif
79aceca5 6740
3fc6c082
FB		 6741#undef RGPL
6742#undef RFPL
79aceca5
FB		 6743}
6744
76a66253
JM		 6745void cpu_dump_statistics (CPUState *env, FILE*f,
6746 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
6747 int flags)
6748{
6749#if defined(DO_PPC_STATISTICS)
6750 opc_handler_t **t1, **t2, **t3, *handler;
6751 int op1, op2, op3;
6752
6753 t1 = env->opcodes;
6754 for (op1 = 0; op1 < 64; op1++) {
6755 handler = t1[op1];
6756 if (is_indirect_opcode(handler)) {
6757 t2 = ind_table(handler);
6758 for (op2 = 0; op2 < 32; op2++) {
6759 handler = t2[op2];
6760 if (is_indirect_opcode(handler)) {
6761 t3 = ind_table(handler);
6762 for (op3 = 0; op3 < 32; op3++) {
6763 handler = t3[op3];
6764 if (handler->count == 0)
6765 continue;
6766 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
6767 "%016llx %lld\n",
6768 op1, op2, op3, op1, (op3 << 5) | op2,
6769 handler->oname,
6770 handler->count, handler->count);
6771 }
6772 } else {
6773 if (handler->count == 0)
6774 continue;
6775 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
6776 "%016llx %lld\n",
6777 op1, op2, op1, op2, handler->oname,
6778 handler->count, handler->count);
6779 }
6780 }
6781 } else {
6782 if (handler->count == 0)
6783 continue;
6784 cpu_fprintf(f, "%02x (%02x ) %16s: %016llx %lld\n",
6785 op1, op1, handler->oname,
6786 handler->count, handler->count);
6787 }
6788 }
6789#endif
6790}
6791
9a64fbe4 6792/*****************************************************************************/
2cfc5f17
TS		 6793static always_inline void gen_intermediate_code_internal (CPUState *env,
6794 TranslationBlock *tb,
6795 int search_pc)
79aceca5 6796{
9fddaa0c 6797 DisasContext ctx, *ctxp = &ctx;
79aceca5 6798 opc_handler_t **table, *handler;
0fa85d43 6799 target_ulong pc_start;
79aceca5 6800 uint16_t *gen_opc_end;
056401ea 6801 int supervisor, little_endian;
79aceca5 6802 int j, lj = -1;
2e70f6ef
PB		 6803 int num_insns;
6804 int max_insns;
79aceca5
FB		 6805
6806 pc_start = tb->pc;
79aceca5 6807 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7c58044c
JM		 6808#if defined(OPTIMIZE_FPRF_UPDATE)
6809 gen_fprf_ptr = gen_fprf_buf;
6810#endif
046d6672 6811 ctx.nip = pc_start;
79aceca5 6812 ctx.tb = tb;
e1833e1f 6813 ctx.exception = POWERPC_EXCP_NONE;
3fc6c082 6814 ctx.spr_cb = env->spr_cb;
6ebbf390
JM		 6815 supervisor = env->mmu_idx;
6816#if !defined(CONFIG_USER_ONLY)
2857068e 6817 ctx.supervisor = supervisor;
d9bce9d9 6818#endif
056401ea 6819 little_endian = env->hflags & (1 << MSR_LE) ? 1 : 0;
d9bce9d9
JM		 6820#if defined(TARGET_PPC64)
6821 ctx.sf_mode = msr_sf;
056401ea 6822 ctx.mem_idx = (supervisor << 2) | (msr_sf << 1) | little_endian;
2857068e 6823#else
056401ea 6824 ctx.mem_idx = (supervisor << 1) | little_endian;
9a64fbe4 6825#endif
d63001d1 6826 ctx.dcache_line_size = env->dcache_line_size;
3cc62370 6827 ctx.fpu_enabled = msr_fp;
a9d9eb8f 6828 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
d26bfc9a
JM		 6829 ctx.spe_enabled = msr_spe;
6830 else
6831 ctx.spe_enabled = 0;
a9d9eb8f
JM		 6832 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
6833 ctx.altivec_enabled = msr_vr;
6834 else
6835 ctx.altivec_enabled = 0;
d26bfc9a 6836 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
8cbcb4fa 6837 ctx.singlestep_enabled = CPU_SINGLE_STEP;
d26bfc9a 6838 else
8cbcb4fa 6839 ctx.singlestep_enabled = 0;
d26bfc9a 6840 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
8cbcb4fa
AJ		 6841 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
6842 if (unlikely(env->singlestep_enabled))
6843 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
3fc6c082 6844#if defined (DO_SINGLE_STEP) && 0
9a64fbe4
FB		 6845 /* Single step trace mode */
6846 msr_se = 1;
6847#endif
2e70f6ef
PB		 6848 num_insns = 0;
6849 max_insns = tb->cflags & CF_COUNT_MASK;
6850 if (max_insns == 0)
6851 max_insns = CF_COUNT_MASK;
6852
6853 gen_icount_start();
9a64fbe4 6854 /* Set env in case of segfault during code fetch */
e1833e1f 6855 while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
76a66253
JM		 6856 if (unlikely(env->nb_breakpoints > 0)) {
6857 for (j = 0; j < env->nb_breakpoints; j++) {
ea4e754f 6858 if (env->breakpoints[j] == ctx.nip) {
5fafdf24 6859 gen_update_nip(&ctx, ctx.nip);
ea4e754f
FB		 6860 gen_op_debug();
6861 break;
6862 }
6863 }
6864 }
76a66253 6865 if (unlikely(search_pc)) {
79aceca5
FB		 6866 j = gen_opc_ptr - gen_opc_buf;
6867 if (lj < j) {
6868 lj++;
6869 while (lj < j)
6870 gen_opc_instr_start[lj++] = 0;
046d6672 6871 gen_opc_pc[lj] = ctx.nip;
79aceca5 6872 gen_opc_instr_start[lj] = 1;
2e70f6ef 6873 gen_opc_icount[lj] = num_insns;
79aceca5
FB		 6874 }
6875 }
9fddaa0c
FB		 6876#if defined PPC_DEBUG_DISAS
6877 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 6878 fprintf(logfile, "----------------\n");
1b9eb036 6879 fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
0411a972 6880 ctx.nip, supervisor, (int)msr_ir);
9a64fbe4
FB		 6881 }
6882#endif
2e70f6ef
PB		 6883 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
6884 gen_io_start();
056401ea
JM		 6885 if (unlikely(little_endian)) {
6886 ctx.opcode = bswap32(ldl_code(ctx.nip));
6887 } else {
6888 ctx.opcode = ldl_code(ctx.nip);
111bfab3 6889 }
9fddaa0c
FB		 6890#if defined PPC_DEBUG_DISAS
6891 if (loglevel & CPU_LOG_TB_IN_ASM) {
111bfab3 6892 fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
9a64fbe4 6893 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
056401ea 6894 opc3(ctx.opcode), little_endian ? "little" : "big");
79aceca5
FB		 6895 }
6896#endif
046d6672 6897 ctx.nip += 4;
3fc6c082 6898 table = env->opcodes;
2e70f6ef 6899 num_insns++;
79aceca5
FB		 6900 handler = table[opc1(ctx.opcode)];
6901 if (is_indirect_opcode(handler)) {
6902 table = ind_table(handler);
6903 handler = table[opc2(ctx.opcode)];
6904 if (is_indirect_opcode(handler)) {
6905 table = ind_table(handler);
6906 handler = table[opc3(ctx.opcode)];
6907 }
6908 }
6909 /* Is opcode *REALLY* valid ? */
76a66253 6910 if (unlikely(handler->handler == &gen_invalid)) {
4a057712 6911 if (loglevel != 0) {
76a66253 6912 fprintf(logfile, "invalid/unsupported opcode: "
6b542af7 6913 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
76a66253 6914 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6915 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa
FB		 6916 } else {
6917 printf("invalid/unsupported opcode: "
6b542af7 6918 "%02x - %02x - %02x (%08x) " ADDRX " %d\n",
4b3686fa 6919 opc1(ctx.opcode), opc2(ctx.opcode),
0411a972 6920 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
4b3686fa 6921 }
76a66253
JM		 6922 } else {
6923 if (unlikely((ctx.opcode & handler->inval) != 0)) {
4a057712 6924 if (loglevel != 0) {
79aceca5 6925 fprintf(logfile, "invalid bits: %08x for opcode: "
6b542af7 6926 "%02x - %02x - %02x (%08x) " ADDRX "\n",
79aceca5
FB		 6927 ctx.opcode & handler->inval, opc1(ctx.opcode),
6928 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6929 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 6930 } else {
6931 printf("invalid bits: %08x for opcode: "
6b542af7 6932 "%02x - %02x - %02x (%08x) " ADDRX "\n",
76a66253
JM		 6933 ctx.opcode & handler->inval, opc1(ctx.opcode),
6934 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 6935 ctx.opcode, ctx.nip - 4);
76a66253 6936 }
e1833e1f 6937 GEN_EXCP_INVAL(ctxp);
4b3686fa 6938 break;
79aceca5 6939 }
79aceca5 6940 }
4b3686fa 6941 (*(handler->handler))(&ctx);
76a66253
JM		 6942#if defined(DO_PPC_STATISTICS)
6943 handler->count++;
6944#endif
9a64fbe4 6945 /* Check trace mode exceptions */
8cbcb4fa
AJ		 6946 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
6947 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
6948 ctx.exception != POWERPC_SYSCALL &&
6949 ctx.exception != POWERPC_EXCP_TRAP &&
6950 ctx.exception != POWERPC_EXCP_BRANCH)) {
e1833e1f 6951 GEN_EXCP(ctxp, POWERPC_EXCP_TRACE, 0);
d26bfc9a 6952 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 6953 (env->singlestep_enabled) ||
6954 num_insns >= max_insns)) {
d26bfc9a
JM		 6955 /* if we reach a page boundary or are single stepping, stop
6956 * generation
6957 */
8dd4983c 6958 break;
76a66253 6959 }
3fc6c082
FB		 6960#if defined (DO_SINGLE_STEP)
6961 break;
6962#endif
6963 }
2e70f6ef
PB		 6964 if (tb->cflags & CF_LAST_IO)
6965 gen_io_end();
e1833e1f 6966 if (ctx.exception == POWERPC_EXCP_NONE) {
c1942362 6967 gen_goto_tb(&ctx, 0, ctx.nip);
e1833e1f 6968 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
8cbcb4fa
AJ		 6969 if (unlikely(env->singlestep_enabled)) {
6970 gen_update_nip(&ctx, ctx.nip);
6971 gen_op_debug();
6972 }
76a66253 6973 /* Generate the return instruction */
57fec1fe 6974 tcg_gen_exit_tb(0);
9a64fbe4 6975 }
2e70f6ef 6976 gen_icount_end(tb, num_insns);
79aceca5 6977 *gen_opc_ptr = INDEX_op_end;
76a66253 6978 if (unlikely(search_pc)) {
9a64fbe4
FB		 6979 j = gen_opc_ptr - gen_opc_buf;
6980 lj++;
6981 while (lj <= j)
6982 gen_opc_instr_start[lj++] = 0;
9a64fbe4 6983 } else {
046d6672 6984 tb->size = ctx.nip - pc_start;
2e70f6ef 6985 tb->icount = num_insns;
9a64fbe4 6986 }
d9bce9d9 6987#if defined(DEBUG_DISAS)
9fddaa0c 6988 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4 6989 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
7fe48483 6990 cpu_dump_state(env, logfile, fprintf, 0);
9fddaa0c
FB		 6991 }
6992 if (loglevel & CPU_LOG_TB_IN_ASM) {
76a66253 6993 int flags;
237c0af0 6994 flags = env->bfd_mach;
056401ea 6995 flags |= little_endian << 16;
0fa85d43 6996 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
76a66253 6997 target_disas(logfile, pc_start, ctx.nip - pc_start, flags);
79aceca5 6998 fprintf(logfile, "\n");
9fddaa0c 6999 }
79aceca5 7000#endif
79aceca5
FB		 7001}
7002
2cfc5f17 7003void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5 7004{
2cfc5f17 7005 gen_intermediate_code_internal(env, tb, 0);
79aceca5
FB		 7006}
7007
2cfc5f17 7008void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5 7009{
2cfc5f17 7010 gen_intermediate_code_internal(env, tb, 1);
79aceca5 7011}
d2856f1a
AJ		 7012
7013void gen_pc_load(CPUState *env, TranslationBlock *tb,
7014 unsigned long searched_pc, int pc_pos, void *puc)
7015{
7016 int type, c;
7017 /* for PPC, we need to look at the micro operation to get the
7018 * access type */
7019 env->nip = gen_opc_pc[pc_pos];
7020 c = gen_opc_buf[pc_pos];
7021 switch(c) {
7022#if defined(CONFIG_USER_ONLY)
7023#define CASE3(op)\
7024 case INDEX_op_ ## op ## _raw
7025#else
7026#define CASE3(op)\
7027 case INDEX_op_ ## op ## _user:\
7028 case INDEX_op_ ## op ## _kernel:\
7029 case INDEX_op_ ## op ## _hypv
7030#endif
7031
7032 CASE3(stfd):
7033 CASE3(stfs):
7034 CASE3(lfd):
7035 CASE3(lfs):
7036 type = ACCESS_FLOAT;
7037 break;
7038 CASE3(lwarx):
7039 type = ACCESS_RES;
7040 break;
7041 CASE3(stwcx):
7042 type = ACCESS_RES;
7043 break;
7044 CASE3(eciwx):
7045 CASE3(ecowx):
7046 type = ACCESS_EXT;
7047 break;
7048 default:
7049 type = ACCESS_INT;
7050 break;
7051 }
7052 env->access_type = type;
7053}
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