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PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type
[mirror_qemu.git] / target-ppc / translate_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
3fc6c082
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 18 */
19
20/* A lot of PowerPC definition have been included here.
21 * Most of them are not usable for now but have been kept
22 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
23 */
24
237c0af0 25#include "dis-asm.h"
4e47ea67 26#include "gdbstub.h"
237c0af0 27
3fc6c082
FB		 28//#define PPC_DUMP_CPU
29//#define PPC_DEBUG_SPR
80d11f44
JM		 30//#define PPC_DUMP_SPR_ACCESSES
31#if defined(CONFIG_USER_ONLY)
32#define TODO_USER_ONLY 1
33#endif
3fc6c082 34
c227f099 35struct ppc_def_t {
b55266b5 36 const char *name;
3fc6c082 37 uint32_t pvr;
80d11f44 38 uint32_t svr;
0487d6a8 39 uint64_t insns_flags;
a5858d7a 40 uint64_t insns_flags2;
3fc6c082 41 uint64_t msr_mask;
c227f099
AL		 42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
d26bfc9a 45 uint32_t flags;
237c0af0 46 int bfd_mach;
a750fc0b 47 void (*init_proc)(CPUPPCState *env);
4c1b1bfe 48 int (*check_pow)(CPUPPCState *env);
3fc6c082
FB		 49};
50
e9df014c
JM		 51/* For user-mode emulation, we don't emulate any IRQ controller */
52#if defined(CONFIG_USER_ONLY)
a750fc0b
JM		 53#define PPC_IRQ_INIT_FN(name) \
54static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55{ \
e9df014c
JM		 56}
57#else
a750fc0b 58#define PPC_IRQ_INIT_FN(name) \
e9df014c
JM		 59void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60#endif
a750fc0b 61
4e290a0b 62PPC_IRQ_INIT_FN(40x);
e9df014c 63PPC_IRQ_INIT_FN(6xx);
d0dfae6e 64PPC_IRQ_INIT_FN(970);
9d52e907 65PPC_IRQ_INIT_FN(POWER7);
9fdc60bf 66PPC_IRQ_INIT_FN(e500);
e9df014c 67
3fc6c082
FB		 68/* Generic callbacks:
69 * do nothing but store/retrieve spr value
70 */
45d827d2 71static void spr_read_generic (void *opaque, int gprn, int sprn)
a496775f 72{
45d827d2
AJ		 73 gen_load_spr(cpu_gpr[gprn], sprn);
74#ifdef PPC_DUMP_SPR_ACCESSES
75 {
1ff7854e 76 TCGv_i32 t0 = tcg_const_i32(sprn);
45d827d2
AJ		 77 gen_helper_load_dump_spr(t0);
78 tcg_temp_free_i32(t0);
79 }
80#endif
a496775f
JM		 81}
82
45d827d2 83static void spr_write_generic (void *opaque, int sprn, int gprn)
a496775f 84{
45d827d2
AJ		 85 gen_store_spr(sprn, cpu_gpr[gprn]);
86#ifdef PPC_DUMP_SPR_ACCESSES
87 {
1ff7854e 88 TCGv_i32 t0 = tcg_const_i32(sprn);
45d827d2
AJ		 89 gen_helper_store_dump_spr(t0);
90 tcg_temp_free_i32(t0);
91 }
04f20795 92#endif
45d827d2 93}
a496775f
JM		 94
95#if !defined(CONFIG_USER_ONLY)
45d827d2 96static void spr_write_clear (void *opaque, int sprn, int gprn)
a496775f 97{
45d827d2
AJ		 98 TCGv t0 = tcg_temp_new();
99 TCGv t1 = tcg_temp_new();
100 gen_load_spr(t0, sprn);
101 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
102 tcg_gen_and_tl(t0, t0, t1);
103 gen_store_spr(sprn, t0);
104 tcg_temp_free(t0);
105 tcg_temp_free(t1);
a496775f
JM		 106}
107#endif
108
76a66253 109/* SPR common to all PowerPC */
3fc6c082 110/* XER */
45d827d2 111static void spr_read_xer (void *opaque, int gprn, int sprn)
3fc6c082 112{
45d827d2 113 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_xer);
3fc6c082
FB		 114}
115
45d827d2 116static void spr_write_xer (void *opaque, int sprn, int gprn)
3fc6c082 117{
45d827d2 118 tcg_gen_mov_tl(cpu_xer, cpu_gpr[gprn]);
3fc6c082
FB		 119}
120
121/* LR */
45d827d2 122static void spr_read_lr (void *opaque, int gprn, int sprn)
3fc6c082 123{
45d827d2 124 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
3fc6c082
FB		 125}
126
45d827d2 127static void spr_write_lr (void *opaque, int sprn, int gprn)
3fc6c082 128{
45d827d2 129 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
3fc6c082
FB		 130}
131
132/* CTR */
45d827d2 133static void spr_read_ctr (void *opaque, int gprn, int sprn)
3fc6c082 134{
45d827d2 135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
3fc6c082
FB		 136}
137
45d827d2 138static void spr_write_ctr (void *opaque, int sprn, int gprn)
3fc6c082 139{
45d827d2 140 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
3fc6c082
FB		 141}
142
143/* User read access to SPR */
144/* USPRx */
145/* UMMCRx */
146/* UPMCx */
147/* USIA */
148/* UDECR */
45d827d2 149static void spr_read_ureg (void *opaque, int gprn, int sprn)
3fc6c082 150{
45d827d2 151 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
3fc6c082
FB		 152}
153
76a66253 154/* SPR common to all non-embedded PowerPC */
3fc6c082 155/* DECR */
76a66253 156#if !defined(CONFIG_USER_ONLY)
45d827d2 157static void spr_read_decr (void *opaque, int gprn, int sprn)
3fc6c082 158{
630ecca0
TG		 159 if (use_icount) {
160 gen_io_start();
161 }
45d827d2 162 gen_helper_load_decr(cpu_gpr[gprn]);
630ecca0
TG		 163 if (use_icount) {
164 gen_io_end();
165 gen_stop_exception(opaque);
166 }
3fc6c082
FB		 167}
168
45d827d2 169static void spr_write_decr (void *opaque, int sprn, int gprn)
3fc6c082 170{
630ecca0
TG		 171 if (use_icount) {
172 gen_io_start();
173 }
45d827d2 174 gen_helper_store_decr(cpu_gpr[gprn]);
630ecca0
TG		 175 if (use_icount) {
176 gen_io_end();
177 gen_stop_exception(opaque);
178 }
3fc6c082 179}
76a66253 180#endif
3fc6c082 181
76a66253 182/* SPR common to all non-embedded PowerPC, except 601 */
3fc6c082 183/* Time base */
45d827d2 184static void spr_read_tbl (void *opaque, int gprn, int sprn)
3fc6c082 185{
630ecca0
TG		 186 if (use_icount) {
187 gen_io_start();
188 }
45d827d2 189 gen_helper_load_tbl(cpu_gpr[gprn]);
630ecca0
TG		 190 if (use_icount) {
191 gen_io_end();
192 gen_stop_exception(opaque);
193 }
3fc6c082
FB		 194}
195
45d827d2 196static void spr_read_tbu (void *opaque, int gprn, int sprn)
3fc6c082 197{
630ecca0
TG		 198 if (use_icount) {
199 gen_io_start();
200 }
45d827d2 201 gen_helper_load_tbu(cpu_gpr[gprn]);
630ecca0
TG		 202 if (use_icount) {
203 gen_io_end();
204 gen_stop_exception(opaque);
205 }
3fc6c082
FB		 206}
207
a062e36c 208__attribute__ (( unused ))
45d827d2 209static void spr_read_atbl (void *opaque, int gprn, int sprn)
a062e36c 210{
45d827d2 211 gen_helper_load_atbl(cpu_gpr[gprn]);
a062e36c
JM		 212}
213
214__attribute__ (( unused ))
45d827d2 215static void spr_read_atbu (void *opaque, int gprn, int sprn)
a062e36c 216{
45d827d2 217 gen_helper_load_atbu(cpu_gpr[gprn]);
a062e36c
JM		 218}
219
76a66253 220#if !defined(CONFIG_USER_ONLY)
45d827d2 221static void spr_write_tbl (void *opaque, int sprn, int gprn)
3fc6c082 222{
630ecca0
TG		 223 if (use_icount) {
224 gen_io_start();
225 }
45d827d2 226 gen_helper_store_tbl(cpu_gpr[gprn]);
630ecca0
TG		 227 if (use_icount) {
228 gen_io_end();
229 gen_stop_exception(opaque);
230 }
3fc6c082
FB		 231}
232
45d827d2 233static void spr_write_tbu (void *opaque, int sprn, int gprn)
3fc6c082 234{
630ecca0
TG		 235 if (use_icount) {
236 gen_io_start();
237 }
45d827d2 238 gen_helper_store_tbu(cpu_gpr[gprn]);
630ecca0
TG		 239 if (use_icount) {
240 gen_io_end();
241 gen_stop_exception(opaque);
242 }
3fc6c082 243}
a062e36c
JM		 244
245__attribute__ (( unused ))
45d827d2 246static void spr_write_atbl (void *opaque, int sprn, int gprn)
a062e36c 247{
45d827d2 248 gen_helper_store_atbl(cpu_gpr[gprn]);
a062e36c
JM		 249}
250
251__attribute__ (( unused ))
45d827d2 252static void spr_write_atbu (void *opaque, int sprn, int gprn)
a062e36c 253{
45d827d2 254 gen_helper_store_atbu(cpu_gpr[gprn]);
a062e36c 255}
3a7f009a
DG		 256
257#if defined(TARGET_PPC64)
258__attribute__ (( unused ))
259static void spr_read_purr (void *opaque, int gprn, int sprn)
260{
261 gen_helper_load_purr(cpu_gpr[gprn]);
262}
263#endif
76a66253 264#endif
3fc6c082 265
76a66253 266#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 267/* IBAT0U...IBAT0U */
268/* IBAT0L...IBAT7L */
45d827d2 269static void spr_read_ibat (void *opaque, int gprn, int sprn)
3fc6c082 270{
45d827d2 271 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
3fc6c082
FB		 272}
273
45d827d2 274static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
3fc6c082 275{
45d827d2 276 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
3fc6c082
FB		 277}
278
45d827d2 279static void spr_write_ibatu (void *opaque, int sprn, int gprn)
3fc6c082 280{
45d827d2
AJ		 281 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
282 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
283 tcg_temp_free_i32(t0);
3fc6c082
FB		 284}
285
45d827d2 286static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
3fc6c082 287{
8daf1781 288 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
45d827d2
AJ		 289 gen_helper_store_ibatu(t0, cpu_gpr[gprn]);
290 tcg_temp_free_i32(t0);
3fc6c082
FB		 291}
292
45d827d2 293static void spr_write_ibatl (void *opaque, int sprn, int gprn)
3fc6c082 294{
45d827d2
AJ		 295 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
296 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
297 tcg_temp_free_i32(t0);
3fc6c082
FB		 298}
299
45d827d2 300static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
3fc6c082 301{
8daf1781 302 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
45d827d2
AJ		 303 gen_helper_store_ibatl(t0, cpu_gpr[gprn]);
304 tcg_temp_free_i32(t0);
3fc6c082
FB		 305}
306
307/* DBAT0U...DBAT7U */
308/* DBAT0L...DBAT7L */
45d827d2 309static void spr_read_dbat (void *opaque, int gprn, int sprn)
3fc6c082 310{
45d827d2 311 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
3fc6c082
FB		 312}
313
45d827d2 314static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
3fc6c082 315{
45d827d2 316 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
3fc6c082
FB		 317}
318
45d827d2 319static void spr_write_dbatu (void *opaque, int sprn, int gprn)
3fc6c082 320{
45d827d2
AJ		 321 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
322 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
323 tcg_temp_free_i32(t0);
3fc6c082
FB		 324}
325
45d827d2 326static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
3fc6c082 327{
45d827d2
AJ		 328 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
329 gen_helper_store_dbatu(t0, cpu_gpr[gprn]);
330 tcg_temp_free_i32(t0);
3fc6c082
FB		 331}
332
45d827d2 333static void spr_write_dbatl (void *opaque, int sprn, int gprn)
3fc6c082 334{
45d827d2
AJ		 335 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
336 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
337 tcg_temp_free_i32(t0);
3fc6c082
FB		 338}
339
45d827d2 340static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
3fc6c082 341{
45d827d2
AJ		 342 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
343 gen_helper_store_dbatl(t0, cpu_gpr[gprn]);
344 tcg_temp_free_i32(t0);
3fc6c082
FB		 345}
346
347/* SDR1 */
45d827d2 348static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
3fc6c082 349{
45d827d2 350 gen_helper_store_sdr1(cpu_gpr[gprn]);
3fc6c082
FB		 351}
352
76a66253
JM		 353/* 64 bits PowerPC specific SPRs */
354/* ASR */
578bb252 355#if defined(TARGET_PPC64)
2adab7d6
BS		 356static void spr_read_hior (void *opaque, int gprn, int sprn)
357{
358 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, excp_prefix));
359}
360
361static void spr_write_hior (void *opaque, int sprn, int gprn)
362{
363 TCGv t0 = tcg_temp_new();
364 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
365 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
366 tcg_temp_free(t0);
367}
368
45d827d2 369static void spr_read_asr (void *opaque, int gprn, int sprn)
76a66253 370{
45d827d2 371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, asr));
76a66253
JM		 372}
373
45d827d2 374static void spr_write_asr (void *opaque, int sprn, int gprn)
76a66253 375{
45d827d2 376 gen_helper_store_asr(cpu_gpr[gprn]);
76a66253
JM		 377}
378#endif
a750fc0b 379#endif
76a66253
JM		 380
381/* PowerPC 601 specific registers */
382/* RTC */
45d827d2 383static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
76a66253 384{
45d827d2 385 gen_helper_load_601_rtcl(cpu_gpr[gprn]);
76a66253
JM		 386}
387
45d827d2 388static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
76a66253 389{
45d827d2 390 gen_helper_load_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 391}
392
393#if !defined(CONFIG_USER_ONLY)
45d827d2 394static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
76a66253 395{
45d827d2 396 gen_helper_store_601_rtcu(cpu_gpr[gprn]);
76a66253
JM		 397}
398
45d827d2 399static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
76a66253 400{
45d827d2 401 gen_helper_store_601_rtcl(cpu_gpr[gprn]);
76a66253 402}
056401ea 403
45d827d2 404static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
056401ea
JM		 405{
406 DisasContext *ctx = opaque;
407
45d827d2 408 gen_helper_store_hid0_601(cpu_gpr[gprn]);
056401ea 409 /* Must stop the translation as endianness may have changed */
e06fcd75 410 gen_stop_exception(ctx);
056401ea 411}
76a66253
JM		 412#endif
413
414/* Unified bats */
415#if !defined(CONFIG_USER_ONLY)
45d827d2 416static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
76a66253 417{
45d827d2 418 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
76a66253
JM		 419}
420
45d827d2 421static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
76a66253 422{
45d827d2
AJ		 423 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
424 gen_helper_store_601_batl(t0, cpu_gpr[gprn]);
425 tcg_temp_free_i32(t0);
76a66253
JM		 426}
427
45d827d2 428static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
76a66253 429{
45d827d2
AJ		 430 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
431 gen_helper_store_601_batu(t0, cpu_gpr[gprn]);
432 tcg_temp_free_i32(t0);
76a66253
JM		 433}
434#endif
435
436/* PowerPC 40x specific registers */
437#if !defined(CONFIG_USER_ONLY)
45d827d2 438static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
76a66253 439{
45d827d2 440 gen_helper_load_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 441}
442
45d827d2 443static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
76a66253 444{
45d827d2 445 gen_helper_store_40x_pit(cpu_gpr[gprn]);
76a66253
JM		 446}
447
45d827d2 448static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
8ecc7913
JM		 449{
450 DisasContext *ctx = opaque;
451
45d827d2 452 gen_helper_store_40x_dbcr0(cpu_gpr[gprn]);
8ecc7913 453 /* We must stop translation as we may have rebooted */
e06fcd75 454 gen_stop_exception(ctx);
8ecc7913
JM		 455}
456
45d827d2 457static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
c294fc58 458{
45d827d2 459 gen_helper_store_40x_sler(cpu_gpr[gprn]);
c294fc58
JM		 460}
461
45d827d2 462static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
76a66253 463{
45d827d2 464 gen_helper_store_booke_tcr(cpu_gpr[gprn]);
76a66253
JM		 465}
466
45d827d2 467static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
76a66253 468{
45d827d2 469 gen_helper_store_booke_tsr(cpu_gpr[gprn]);
76a66253
JM		 470}
471#endif
472
473/* PowerPC 403 specific registers */
474/* PBL1 / PBU1 / PBL2 / PBU2 */
475#if !defined(CONFIG_USER_ONLY)
45d827d2 476static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
76a66253 477{
45d827d2 478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUState, pb[sprn - SPR_403_PBL1]));
76a66253
JM		 479}
480
45d827d2 481static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
76a66253 482{
45d827d2
AJ		 483 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
484 gen_helper_store_403_pbr(t0, cpu_gpr[gprn]);
485 tcg_temp_free_i32(t0);
76a66253
JM		 486}
487
45d827d2 488static void spr_write_pir (void *opaque, int sprn, int gprn)
3fc6c082 489{
45d827d2
AJ		 490 TCGv t0 = tcg_temp_new();
491 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
492 gen_store_spr(SPR_PIR, t0);
493 tcg_temp_free(t0);
3fc6c082 494}
76a66253 495#endif
3fc6c082 496
d34defbc
AJ		 497/* SPE specific registers */
498static void spr_read_spefscr (void *opaque, int gprn, int sprn)
499{
500 TCGv_i32 t0 = tcg_temp_new_i32();
515e2f7e 501 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
d34defbc
AJ		 502 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
503 tcg_temp_free_i32(t0);
504}
505
506static void spr_write_spefscr (void *opaque, int sprn, int gprn)
507{
508 TCGv_i32 t0 = tcg_temp_new_i32();
509 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
515e2f7e 510 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUState, spe_fscr));
d34defbc
AJ		 511 tcg_temp_free_i32(t0);
512}
513
6f5d427d
JM		 514#if !defined(CONFIG_USER_ONLY)
515/* Callback used to write the exception vector base */
45d827d2 516static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
6f5d427d 517{
45d827d2
AJ		 518 TCGv t0 = tcg_temp_new();
519 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivpr_mask));
520 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
521 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_prefix));
522 gen_store_spr(sprn, t0);
69bd5820 523 tcg_temp_free(t0);
6f5d427d
JM		 524}
525
45d827d2 526static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
6f5d427d
JM		 527{
528 DisasContext *ctx = opaque;
529
530 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
45d827d2
AJ		 531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR0]));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
6f5d427d 537 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
45d827d2
AJ		 538 TCGv t0 = tcg_temp_new();
539 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, ivor_mask));
540 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
541 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, excp_vectors[sprn - SPR_BOOKE_IVOR32 + 32]));
542 gen_store_spr(sprn, t0);
543 tcg_temp_free(t0);
6f5d427d
JM		 544 } else {
545 printf("Trying to write an unknown exception vector %d %03x\n",
546 sprn, sprn);
e06fcd75 547 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6f5d427d
JM		 548 }
549}
550#endif
551
cf8358c8
AJ		 552static inline void vscr_init (CPUPPCState *env, uint32_t val)
553{
554 env->vscr = val;
555 /* Altivec always uses round-to-nearest */
556 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
557 set_flush_to_zero(vscr_nj, &env->vec_status);
558}
559
76a66253
JM		 560#if defined(CONFIG_USER_ONLY)
561#define spr_register(env, num, name, uea_read, uea_write, \
562 oea_read, oea_write, initial_value) \
563do { \
564 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
565} while (0)
566static inline void _spr_register (CPUPPCState *env, int num,
b55266b5 567 const char *name,
45d827d2
AJ		 568 void (*uea_read)(void *opaque, int gprn, int sprn),
569 void (*uea_write)(void *opaque, int sprn, int gprn),
76a66253
JM		 570 target_ulong initial_value)
571#else
3fc6c082 572static inline void spr_register (CPUPPCState *env, int num,
b55266b5 573 const char *name,
45d827d2
AJ		 574 void (*uea_read)(void *opaque, int gprn, int sprn),
575 void (*uea_write)(void *opaque, int sprn, int gprn),
576 void (*oea_read)(void *opaque, int gprn, int sprn),
577 void (*oea_write)(void *opaque, int sprn, int gprn),
3fc6c082 578 target_ulong initial_value)
76a66253 579#endif
3fc6c082 580{
c227f099 581 ppc_spr_t *spr;
3fc6c082
FB		 582
583 spr = &env->spr_cb[num];
584 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
76a66253
JM		 585#if !defined(CONFIG_USER_ONLY)
586 spr->oea_read != NULL || spr->oea_write != NULL ||
587#endif
588 spr->uea_read != NULL || spr->uea_write != NULL) {
3fc6c082
FB		 589 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
590 exit(1);
591 }
592#if defined(PPC_DEBUG_SPR)
90e189ec
BS		 593 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
594 name, initial_value);
3fc6c082
FB		 595#endif
596 spr->name = name;
597 spr->uea_read = uea_read;
598 spr->uea_write = uea_write;
76a66253 599#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 600 spr->oea_read = oea_read;
601 spr->oea_write = oea_write;
76a66253 602#endif
3fc6c082
FB		 603 env->spr[num] = initial_value;
604}
605
606/* Generic PowerPC SPRs */
607static void gen_spr_generic (CPUPPCState *env)
608{
609 /* Integer processing */
610 spr_register(env, SPR_XER, "XER",
611 &spr_read_xer, &spr_write_xer,
612 &spr_read_xer, &spr_write_xer,
613 0x00000000);
614 /* Branch contol */
615 spr_register(env, SPR_LR, "LR",
616 &spr_read_lr, &spr_write_lr,
617 &spr_read_lr, &spr_write_lr,
618 0x00000000);
619 spr_register(env, SPR_CTR, "CTR",
620 &spr_read_ctr, &spr_write_ctr,
621 &spr_read_ctr, &spr_write_ctr,
622 0x00000000);
623 /* Interrupt processing */
624 spr_register(env, SPR_SRR0, "SRR0",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_generic, &spr_write_generic,
627 0x00000000);
628 spr_register(env, SPR_SRR1, "SRR1",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_generic, &spr_write_generic,
631 0x00000000);
632 /* Processor control */
633 spr_register(env, SPR_SPRG0, "SPRG0",
634 SPR_NOACCESS, SPR_NOACCESS,
635 &spr_read_generic, &spr_write_generic,
636 0x00000000);
637 spr_register(env, SPR_SPRG1, "SPRG1",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 spr_register(env, SPR_SPRG2, "SPRG2",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
645 spr_register(env, SPR_SPRG3, "SPRG3",
646 SPR_NOACCESS, SPR_NOACCESS,
647 &spr_read_generic, &spr_write_generic,
648 0x00000000);
649}
650
651/* SPR common to all non-embedded PowerPC, including 601 */
652static void gen_spr_ne_601 (CPUPPCState *env)
653{
654 /* Exception processing */
655 spr_register(env, SPR_DSISR, "DSISR",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_DAR, "DAR",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Timer */
664 spr_register(env, SPR_DECR, "DECR",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_decr, &spr_write_decr,
667 0x00000000);
668 /* Memory management */
669 spr_register(env, SPR_SDR1, "SDR1",
670 SPR_NOACCESS, SPR_NOACCESS,
bb593904 671 &spr_read_generic, &spr_write_sdr1,
3fc6c082
FB		 672 0x00000000);
673}
674
675/* BATs 0-3 */
676static void gen_low_BATs (CPUPPCState *env)
677{
f2e63a42 678#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 679 spr_register(env, SPR_IBAT0U, "IBAT0U",
680 SPR_NOACCESS, SPR_NOACCESS,
681 &spr_read_ibat, &spr_write_ibatu,
682 0x00000000);
683 spr_register(env, SPR_IBAT0L, "IBAT0L",
684 SPR_NOACCESS, SPR_NOACCESS,
685 &spr_read_ibat, &spr_write_ibatl,
686 0x00000000);
687 spr_register(env, SPR_IBAT1U, "IBAT1U",
688 SPR_NOACCESS, SPR_NOACCESS,
689 &spr_read_ibat, &spr_write_ibatu,
690 0x00000000);
691 spr_register(env, SPR_IBAT1L, "IBAT1L",
692 SPR_NOACCESS, SPR_NOACCESS,
693 &spr_read_ibat, &spr_write_ibatl,
694 0x00000000);
695 spr_register(env, SPR_IBAT2U, "IBAT2U",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_ibat, &spr_write_ibatu,
698 0x00000000);
699 spr_register(env, SPR_IBAT2L, "IBAT2L",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_ibat, &spr_write_ibatl,
702 0x00000000);
703 spr_register(env, SPR_IBAT3U, "IBAT3U",
704 SPR_NOACCESS, SPR_NOACCESS,
705 &spr_read_ibat, &spr_write_ibatu,
706 0x00000000);
707 spr_register(env, SPR_IBAT3L, "IBAT3L",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_ibat, &spr_write_ibatl,
710 0x00000000);
711 spr_register(env, SPR_DBAT0U, "DBAT0U",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_dbat, &spr_write_dbatu,
714 0x00000000);
715 spr_register(env, SPR_DBAT0L, "DBAT0L",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_dbat, &spr_write_dbatl,
718 0x00000000);
719 spr_register(env, SPR_DBAT1U, "DBAT1U",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_dbat, &spr_write_dbatu,
722 0x00000000);
723 spr_register(env, SPR_DBAT1L, "DBAT1L",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_dbat, &spr_write_dbatl,
726 0x00000000);
727 spr_register(env, SPR_DBAT2U, "DBAT2U",
728 SPR_NOACCESS, SPR_NOACCESS,
729 &spr_read_dbat, &spr_write_dbatu,
730 0x00000000);
731 spr_register(env, SPR_DBAT2L, "DBAT2L",
732 SPR_NOACCESS, SPR_NOACCESS,
733 &spr_read_dbat, &spr_write_dbatl,
734 0x00000000);
735 spr_register(env, SPR_DBAT3U, "DBAT3U",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_dbat, &spr_write_dbatu,
738 0x00000000);
739 spr_register(env, SPR_DBAT3L, "DBAT3L",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_dbat, &spr_write_dbatl,
742 0x00000000);
a750fc0b 743 env->nb_BATs += 4;
f2e63a42 744#endif
3fc6c082
FB		 745}
746
747/* BATs 4-7 */
748static void gen_high_BATs (CPUPPCState *env)
749{
f2e63a42 750#if !defined(CONFIG_USER_ONLY)
3fc6c082
FB		 751 spr_register(env, SPR_IBAT4U, "IBAT4U",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_ibat_h, &spr_write_ibatu_h,
754 0x00000000);
755 spr_register(env, SPR_IBAT4L, "IBAT4L",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_ibat_h, &spr_write_ibatl_h,
758 0x00000000);
759 spr_register(env, SPR_IBAT5U, "IBAT5U",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_ibat_h, &spr_write_ibatu_h,
762 0x00000000);
763 spr_register(env, SPR_IBAT5L, "IBAT5L",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_ibat_h, &spr_write_ibatl_h,
766 0x00000000);
767 spr_register(env, SPR_IBAT6U, "IBAT6U",
768 SPR_NOACCESS, SPR_NOACCESS,
769 &spr_read_ibat_h, &spr_write_ibatu_h,
770 0x00000000);
771 spr_register(env, SPR_IBAT6L, "IBAT6L",
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_ibat_h, &spr_write_ibatl_h,
774 0x00000000);
775 spr_register(env, SPR_IBAT7U, "IBAT7U",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_ibat_h, &spr_write_ibatu_h,
778 0x00000000);
779 spr_register(env, SPR_IBAT7L, "IBAT7L",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_ibat_h, &spr_write_ibatl_h,
782 0x00000000);
783 spr_register(env, SPR_DBAT4U, "DBAT4U",
784 SPR_NOACCESS, SPR_NOACCESS,
785 &spr_read_dbat_h, &spr_write_dbatu_h,
786 0x00000000);
787 spr_register(env, SPR_DBAT4L, "DBAT4L",
788 SPR_NOACCESS, SPR_NOACCESS,
789 &spr_read_dbat_h, &spr_write_dbatl_h,
790 0x00000000);
791 spr_register(env, SPR_DBAT5U, "DBAT5U",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_dbat_h, &spr_write_dbatu_h,
794 0x00000000);
795 spr_register(env, SPR_DBAT5L, "DBAT5L",
796 SPR_NOACCESS, SPR_NOACCESS,
797 &spr_read_dbat_h, &spr_write_dbatl_h,
798 0x00000000);
799 spr_register(env, SPR_DBAT6U, "DBAT6U",
800 SPR_NOACCESS, SPR_NOACCESS,
801 &spr_read_dbat_h, &spr_write_dbatu_h,
802 0x00000000);
803 spr_register(env, SPR_DBAT6L, "DBAT6L",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_dbat_h, &spr_write_dbatl_h,
806 0x00000000);
807 spr_register(env, SPR_DBAT7U, "DBAT7U",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_dbat_h, &spr_write_dbatu_h,
810 0x00000000);
811 spr_register(env, SPR_DBAT7L, "DBAT7L",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_dbat_h, &spr_write_dbatl_h,
814 0x00000000);
a750fc0b 815 env->nb_BATs += 4;
f2e63a42 816#endif
3fc6c082
FB		 817}
818
819/* Generic PowerPC time base */
820static void gen_tbl (CPUPPCState *env)
821{
822 spr_register(env, SPR_VTBL, "TBL",
823 &spr_read_tbl, SPR_NOACCESS,
824 &spr_read_tbl, SPR_NOACCESS,
825 0x00000000);
826 spr_register(env, SPR_TBL, "TBL",
de6a1dec
DI		 827 &spr_read_tbl, SPR_NOACCESS,
828 &spr_read_tbl, &spr_write_tbl,
3fc6c082
FB		 829 0x00000000);
830 spr_register(env, SPR_VTBU, "TBU",
831 &spr_read_tbu, SPR_NOACCESS,
832 &spr_read_tbu, SPR_NOACCESS,
833 0x00000000);
834 spr_register(env, SPR_TBU, "TBU",
de6a1dec
DI		 835 &spr_read_tbu, SPR_NOACCESS,
836 &spr_read_tbu, &spr_write_tbu,
3fc6c082
FB		 837 0x00000000);
838}
839
76a66253
JM		 840/* Softare table search registers */
841static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
842{
f2e63a42 843#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 844 env->nb_tlb = nb_tlbs;
845 env->nb_ways = nb_ways;
846 env->id_tlbs = 1;
847 spr_register(env, SPR_DMISS, "DMISS",
848 SPR_NOACCESS, SPR_NOACCESS,
849 &spr_read_generic, SPR_NOACCESS,
850 0x00000000);
851 spr_register(env, SPR_DCMP, "DCMP",
852 SPR_NOACCESS, SPR_NOACCESS,
853 &spr_read_generic, SPR_NOACCESS,
854 0x00000000);
855 spr_register(env, SPR_HASH1, "HASH1",
856 SPR_NOACCESS, SPR_NOACCESS,
857 &spr_read_generic, SPR_NOACCESS,
858 0x00000000);
859 spr_register(env, SPR_HASH2, "HASH2",
860 SPR_NOACCESS, SPR_NOACCESS,
861 &spr_read_generic, SPR_NOACCESS,
862 0x00000000);
863 spr_register(env, SPR_IMISS, "IMISS",
864 SPR_NOACCESS, SPR_NOACCESS,
865 &spr_read_generic, SPR_NOACCESS,
866 0x00000000);
867 spr_register(env, SPR_ICMP, "ICMP",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, SPR_NOACCESS,
870 0x00000000);
871 spr_register(env, SPR_RPA, "RPA",
872 SPR_NOACCESS, SPR_NOACCESS,
873 &spr_read_generic, &spr_write_generic,
874 0x00000000);
f2e63a42 875#endif
76a66253
JM		 876}
877
878/* SPR common to MPC755 and G2 */
879static void gen_spr_G2_755 (CPUPPCState *env)
880{
881 /* SGPRs */
882 spr_register(env, SPR_SPRG4, "SPRG4",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
885 0x00000000);
886 spr_register(env, SPR_SPRG5, "SPRG5",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_generic, &spr_write_generic,
889 0x00000000);
890 spr_register(env, SPR_SPRG6, "SPRG6",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_generic, &spr_write_generic,
893 0x00000000);
894 spr_register(env, SPR_SPRG7, "SPRG7",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, &spr_write_generic,
897 0x00000000);
76a66253
JM		 898}
899
3fc6c082
FB		 900/* SPR common to all 7xx PowerPC implementations */
901static void gen_spr_7xx (CPUPPCState *env)
902{
903 /* Breakpoints */
904 /* XXX : not implemented */
905 spr_register(env, SPR_DABR, "DABR",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 /* XXX : not implemented */
910 spr_register(env, SPR_IABR, "IABR",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_generic, &spr_write_generic,
913 0x00000000);
914 /* Cache management */
915 /* XXX : not implemented */
916 spr_register(env, SPR_ICTC, "ICTC",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, &spr_write_generic,
919 0x00000000);
920 /* Performance monitors */
921 /* XXX : not implemented */
922 spr_register(env, SPR_MMCR0, "MMCR0",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 /* XXX : not implemented */
927 spr_register(env, SPR_MMCR1, "MMCR1",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
931 /* XXX : not implemented */
932 spr_register(env, SPR_PMC1, "PMC1",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
936 /* XXX : not implemented */
937 spr_register(env, SPR_PMC2, "PMC2",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
941 /* XXX : not implemented */
942 spr_register(env, SPR_PMC3, "PMC3",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* XXX : not implemented */
947 spr_register(env, SPR_PMC4, "PMC4",
948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
951 /* XXX : not implemented */
a750fc0b 952 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, SPR_NOACCESS,
955 0x00000000);
578bb252 956 /* XXX : not implemented */
3fc6c082
FB		 957 spr_register(env, SPR_UMMCR0, "UMMCR0",
958 &spr_read_ureg, SPR_NOACCESS,
959 &spr_read_ureg, SPR_NOACCESS,
960 0x00000000);
578bb252 961 /* XXX : not implemented */
3fc6c082
FB		 962 spr_register(env, SPR_UMMCR1, "UMMCR1",
963 &spr_read_ureg, SPR_NOACCESS,
964 &spr_read_ureg, SPR_NOACCESS,
965 0x00000000);
578bb252 966 /* XXX : not implemented */
3fc6c082
FB		 967 spr_register(env, SPR_UPMC1, "UPMC1",
968 &spr_read_ureg, SPR_NOACCESS,
969 &spr_read_ureg, SPR_NOACCESS,
970 0x00000000);
578bb252 971 /* XXX : not implemented */
3fc6c082
FB		 972 spr_register(env, SPR_UPMC2, "UPMC2",
973 &spr_read_ureg, SPR_NOACCESS,
974 &spr_read_ureg, SPR_NOACCESS,
975 0x00000000);
578bb252 976 /* XXX : not implemented */
3fc6c082
FB		 977 spr_register(env, SPR_UPMC3, "UPMC3",
978 &spr_read_ureg, SPR_NOACCESS,
979 &spr_read_ureg, SPR_NOACCESS,
980 0x00000000);
578bb252 981 /* XXX : not implemented */
3fc6c082
FB		 982 spr_register(env, SPR_UPMC4, "UPMC4",
983 &spr_read_ureg, SPR_NOACCESS,
984 &spr_read_ureg, SPR_NOACCESS,
985 0x00000000);
578bb252 986 /* XXX : not implemented */
a750fc0b 987 spr_register(env, SPR_USIAR, "USIAR",
3fc6c082
FB		 988 &spr_read_ureg, SPR_NOACCESS,
989 &spr_read_ureg, SPR_NOACCESS,
990 0x00000000);
a750fc0b 991 /* External access control */
3fc6c082 992 /* XXX : not implemented */
a750fc0b 993 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 994 SPR_NOACCESS, SPR_NOACCESS,
995 &spr_read_generic, &spr_write_generic,
996 0x00000000);
a750fc0b
JM		 997}
998
999static void gen_spr_thrm (CPUPPCState *env)
1000{
1001 /* Thermal management */
3fc6c082 1002 /* XXX : not implemented */
a750fc0b 1003 spr_register(env, SPR_THRM1, "THRM1",
3fc6c082
FB		 1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 0x00000000);
1007 /* XXX : not implemented */
a750fc0b 1008 spr_register(env, SPR_THRM2, "THRM2",
3fc6c082
FB		 1009 SPR_NOACCESS, SPR_NOACCESS,
1010 &spr_read_generic, &spr_write_generic,
1011 0x00000000);
3fc6c082 1012 /* XXX : not implemented */
a750fc0b 1013 spr_register(env, SPR_THRM3, "THRM3",
3fc6c082
FB		 1014 SPR_NOACCESS, SPR_NOACCESS,
1015 &spr_read_generic, &spr_write_generic,
1016 0x00000000);
1017}
1018
1019/* SPR specific to PowerPC 604 implementation */
1020static void gen_spr_604 (CPUPPCState *env)
1021{
1022 /* Processor identification */
1023 spr_register(env, SPR_PIR, "PIR",
1024 SPR_NOACCESS, SPR_NOACCESS,
1025 &spr_read_generic, &spr_write_pir,
1026 0x00000000);
1027 /* Breakpoints */
1028 /* XXX : not implemented */
1029 spr_register(env, SPR_IABR, "IABR",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, &spr_write_generic,
1032 0x00000000);
1033 /* XXX : not implemented */
1034 spr_register(env, SPR_DABR, "DABR",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 /* Performance counters */
1039 /* XXX : not implemented */
1040 spr_register(env, SPR_MMCR0, "MMCR0",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
3fc6c082
FB		 1045 spr_register(env, SPR_PMC1, "PMC1",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_PMC2, "PMC2",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, &spr_write_generic,
1053 0x00000000);
1054 /* XXX : not implemented */
a750fc0b 1055 spr_register(env, SPR_SIAR, "SIAR",
3fc6c082
FB		 1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, SPR_NOACCESS,
1058 0x00000000);
1059 /* XXX : not implemented */
1060 spr_register(env, SPR_SDA, "SDA",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, SPR_NOACCESS,
1063 0x00000000);
1064 /* External access control */
1065 /* XXX : not implemented */
1066 spr_register(env, SPR_EAR, "EAR",
1067 SPR_NOACCESS, SPR_NOACCESS,
1068 &spr_read_generic, &spr_write_generic,
1069 0x00000000);
1070}
1071
76a66253
JM		 1072/* SPR specific to PowerPC 603 implementation */
1073static void gen_spr_603 (CPUPPCState *env)
3fc6c082 1074{
76a66253
JM		 1075 /* External access control */
1076 /* XXX : not implemented */
1077 spr_register(env, SPR_EAR, "EAR",
3fc6c082 1078 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
3fc6c082
FB		 1081}
1082
76a66253
JM		 1083/* SPR specific to PowerPC G2 implementation */
1084static void gen_spr_G2 (CPUPPCState *env)
3fc6c082 1085{
76a66253
JM		 1086 /* Memory base address */
1087 /* MBAR */
578bb252 1088 /* XXX : not implemented */
76a66253
JM		 1089 spr_register(env, SPR_MBAR, "MBAR",
1090 SPR_NOACCESS, SPR_NOACCESS,
1091 &spr_read_generic, &spr_write_generic,
1092 0x00000000);
76a66253 1093 /* Exception processing */
363be49c 1094 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1095 SPR_NOACCESS, SPR_NOACCESS,
1096 &spr_read_generic, &spr_write_generic,
1097 0x00000000);
363be49c 1098 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
1102 /* Breakpoints */
1103 /* XXX : not implemented */
1104 spr_register(env, SPR_DABR, "DABR",
1105 SPR_NOACCESS, SPR_NOACCESS,
1106 &spr_read_generic, &spr_write_generic,
1107 0x00000000);
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_DABR2, "DABR2",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
1114 spr_register(env, SPR_IABR, "IABR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 0x00000000);
1118 /* XXX : not implemented */
1119 spr_register(env, SPR_IABR2, "IABR2",
1120 SPR_NOACCESS, SPR_NOACCESS,
1121 &spr_read_generic, &spr_write_generic,
1122 0x00000000);
1123 /* XXX : not implemented */
1124 spr_register(env, SPR_IBCR, "IBCR",
1125 SPR_NOACCESS, SPR_NOACCESS,
1126 &spr_read_generic, &spr_write_generic,
1127 0x00000000);
1128 /* XXX : not implemented */
1129 spr_register(env, SPR_DBCR, "DBCR",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_generic, &spr_write_generic,
1132 0x00000000);
1133}
1134
1135/* SPR specific to PowerPC 602 implementation */
1136static void gen_spr_602 (CPUPPCState *env)
1137{
1138 /* ESA registers */
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_SER, "SER",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, &spr_write_generic,
1143 0x00000000);
1144 /* XXX : not implemented */
1145 spr_register(env, SPR_SEBR, "SEBR",
1146 SPR_NOACCESS, SPR_NOACCESS,
1147 &spr_read_generic, &spr_write_generic,
1148 0x00000000);
1149 /* XXX : not implemented */
a750fc0b 1150 spr_register(env, SPR_ESASRR, "ESASRR",
76a66253
JM		 1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, &spr_write_generic,
1153 0x00000000);
1154 /* Floating point status */
1155 /* XXX : not implemented */
1156 spr_register(env, SPR_SP, "SP",
1157 SPR_NOACCESS, SPR_NOACCESS,
1158 &spr_read_generic, &spr_write_generic,
1159 0x00000000);
1160 /* XXX : not implemented */
1161 spr_register(env, SPR_LT, "LT",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
1165 /* Watchdog timer */
1166 /* XXX : not implemented */
1167 spr_register(env, SPR_TCR, "TCR",
1168 SPR_NOACCESS, SPR_NOACCESS,
1169 &spr_read_generic, &spr_write_generic,
1170 0x00000000);
1171 /* Interrupt base */
1172 spr_register(env, SPR_IBR, "IBR",
1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
a750fc0b
JM		 1176 /* XXX : not implemented */
1177 spr_register(env, SPR_IABR, "IABR",
1178 SPR_NOACCESS, SPR_NOACCESS,
1179 &spr_read_generic, &spr_write_generic,
1180 0x00000000);
76a66253
JM		 1181}
1182
1183/* SPR specific to PowerPC 601 implementation */
1184static void gen_spr_601 (CPUPPCState *env)
1185{
1186 /* Multiplication/division register */
1187 /* MQ */
1188 spr_register(env, SPR_MQ, "MQ",
1189 &spr_read_generic, &spr_write_generic,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* RTC registers */
1193 spr_register(env, SPR_601_RTCU, "RTCU",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 SPR_NOACCESS, &spr_write_601_rtcu,
1196 0x00000000);
1197 spr_register(env, SPR_601_VRTCU, "RTCU",
1198 &spr_read_601_rtcu, SPR_NOACCESS,
1199 &spr_read_601_rtcu, SPR_NOACCESS,
1200 0x00000000);
1201 spr_register(env, SPR_601_RTCL, "RTCL",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 SPR_NOACCESS, &spr_write_601_rtcl,
1204 0x00000000);
1205 spr_register(env, SPR_601_VRTCL, "RTCL",
1206 &spr_read_601_rtcl, SPR_NOACCESS,
1207 &spr_read_601_rtcl, SPR_NOACCESS,
1208 0x00000000);
1209 /* Timer */
1210#if 0 /* ? */
1211 spr_register(env, SPR_601_UDECR, "UDECR",
1212 &spr_read_decr, SPR_NOACCESS,
1213 &spr_read_decr, SPR_NOACCESS,
1214 0x00000000);
1215#endif
1216 /* External access control */
1217 /* XXX : not implemented */
1218 spr_register(env, SPR_EAR, "EAR",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* Memory management */
f2e63a42 1223#if !defined(CONFIG_USER_ONLY)
76a66253
JM		 1224 spr_register(env, SPR_IBAT0U, "IBAT0U",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_601_ubat, &spr_write_601_ubatu,
1227 0x00000000);
1228 spr_register(env, SPR_IBAT0L, "IBAT0L",
1229 SPR_NOACCESS, SPR_NOACCESS,
1230 &spr_read_601_ubat, &spr_write_601_ubatl,
1231 0x00000000);
1232 spr_register(env, SPR_IBAT1U, "IBAT1U",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_601_ubat, &spr_write_601_ubatu,
1235 0x00000000);
1236 spr_register(env, SPR_IBAT1L, "IBAT1L",
1237 SPR_NOACCESS, SPR_NOACCESS,
1238 &spr_read_601_ubat, &spr_write_601_ubatl,
1239 0x00000000);
1240 spr_register(env, SPR_IBAT2U, "IBAT2U",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_601_ubat, &spr_write_601_ubatu,
1243 0x00000000);
1244 spr_register(env, SPR_IBAT2L, "IBAT2L",
1245 SPR_NOACCESS, SPR_NOACCESS,
1246 &spr_read_601_ubat, &spr_write_601_ubatl,
1247 0x00000000);
1248 spr_register(env, SPR_IBAT3U, "IBAT3U",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_601_ubat, &spr_write_601_ubatu,
1251 0x00000000);
1252 spr_register(env, SPR_IBAT3L, "IBAT3L",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_601_ubat, &spr_write_601_ubatl,
1255 0x00000000);
a750fc0b 1256 env->nb_BATs = 4;
f2e63a42 1257#endif
a750fc0b
JM		 1258}
1259
1260static void gen_spr_74xx (CPUPPCState *env)
1261{
1262 /* Processor identification */
1263 spr_register(env, SPR_PIR, "PIR",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_generic, &spr_write_pir,
1266 0x00000000);
1267 /* XXX : not implemented */
1268 spr_register(env, SPR_MMCR2, "MMCR2",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1271 0x00000000);
578bb252 1272 /* XXX : not implemented */
a750fc0b
JM		 1273 spr_register(env, SPR_UMMCR2, "UMMCR2",
1274 &spr_read_ureg, SPR_NOACCESS,
1275 &spr_read_ureg, SPR_NOACCESS,
1276 0x00000000);
1277 /* XXX: not implemented */
1278 spr_register(env, SPR_BAMR, "BAMR",
1279 SPR_NOACCESS, SPR_NOACCESS,
1280 &spr_read_generic, &spr_write_generic,
1281 0x00000000);
578bb252 1282 /* XXX : not implemented */
a750fc0b
JM		 1283 spr_register(env, SPR_MSSCR0, "MSSCR0",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_generic,
1286 0x00000000);
1287 /* Hardware implementation registers */
1288 /* XXX : not implemented */
1289 spr_register(env, SPR_HID0, "HID0",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293 /* XXX : not implemented */
1294 spr_register(env, SPR_HID1, "HID1",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298 /* Altivec */
1299 spr_register(env, SPR_VRSAVE, "VRSAVE",
1300 &spr_read_generic, &spr_write_generic,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
bd928eba
JM		 1303 /* XXX : not implemented */
1304 spr_register(env, SPR_L2CR, "L2CR",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
cf8358c8
AJ		 1308 /* Not strictly an SPR */
1309 vscr_init(env, 0x00010000);
a750fc0b
JM		 1310}
1311
a750fc0b
JM		 1312static void gen_l3_ctrl (CPUPPCState *env)
1313{
1314 /* L3CR */
1315 /* XXX : not implemented */
1316 spr_register(env, SPR_L3CR, "L3CR",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
1320 /* L3ITCR0 */
578bb252 1321 /* XXX : not implemented */
a750fc0b
JM		 1322 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1323 SPR_NOACCESS, SPR_NOACCESS,
1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
a750fc0b 1326 /* L3PM */
578bb252 1327 /* XXX : not implemented */
a750fc0b
JM		 1328 spr_register(env, SPR_L3PM, "L3PM",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_generic, &spr_write_generic,
1331 0x00000000);
1332}
a750fc0b 1333
578bb252 1334static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
a750fc0b 1335{
f2e63a42 1336#if !defined(CONFIG_USER_ONLY)
578bb252
JM		 1337 env->nb_tlb = nb_tlbs;
1338 env->nb_ways = nb_ways;
1339 env->id_tlbs = 1;
1340 /* XXX : not implemented */
a750fc0b
JM		 1341 spr_register(env, SPR_PTEHI, "PTEHI",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
578bb252 1345 /* XXX : not implemented */
a750fc0b
JM		 1346 spr_register(env, SPR_PTELO, "PTELO",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
578bb252 1350 /* XXX : not implemented */
a750fc0b
JM		 1351 spr_register(env, SPR_TLBMISS, "TLBMISS",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
f2e63a42 1355#endif
76a66253
JM		 1356}
1357
01662f3e
AG		 1358#if !defined(CONFIG_USER_ONLY)
1359static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1360{
1361 TCGv t0 = tcg_temp_new();
1362
1363 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1364 gen_store_spr(sprn, t0);
1365 tcg_temp_free(t0);
1366}
1367
1368static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1369{
1ff7854e 1370 TCGv_i32 t0 = tcg_const_i32(sprn);
01662f3e 1371 gen_helper_booke206_tlbflush(t0);
1ff7854e 1372 tcg_temp_free_i32(t0);
01662f3e
AG		 1373}
1374
1375static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1376{
1ff7854e 1377 TCGv_i32 t0 = tcg_const_i32(sprn);
01662f3e 1378 gen_helper_booke_setpid(t0, cpu_gpr[gprn]);
1ff7854e 1379 tcg_temp_free_i32(t0);
01662f3e
AG		 1380}
1381#endif
1382
80d11f44 1383static void gen_spr_usprgh (CPUPPCState *env)
76a66253 1384{
80d11f44
JM		 1385 spr_register(env, SPR_USPRG4, "USPRG4",
1386 &spr_read_ureg, SPR_NOACCESS,
1387 &spr_read_ureg, SPR_NOACCESS,
1388 0x00000000);
1389 spr_register(env, SPR_USPRG5, "USPRG5",
1390 &spr_read_ureg, SPR_NOACCESS,
1391 &spr_read_ureg, SPR_NOACCESS,
1392 0x00000000);
1393 spr_register(env, SPR_USPRG6, "USPRG6",
1394 &spr_read_ureg, SPR_NOACCESS,
1395 &spr_read_ureg, SPR_NOACCESS,
1396 0x00000000);
1397 spr_register(env, SPR_USPRG7, "USPRG7",
1398 &spr_read_ureg, SPR_NOACCESS,
1399 &spr_read_ureg, SPR_NOACCESS,
76a66253 1400 0x00000000);
80d11f44
JM		 1401}
1402
1403/* PowerPC BookE SPR */
1404static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1405{
b55266b5 1406 const char *ivor_names[64] = {
80d11f44
JM		 1407 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1408 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1409 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1410 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1411 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1412 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1413 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1414 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1415 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1416 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1417 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1418 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1419 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1420 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1421 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1422 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1423 };
1424#define SPR_BOOKE_IVORxx (-1)
1425 int ivor_sprn[64] = {
1426 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1427 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1428 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1429 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1430 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1431 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1432 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1433 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1434 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1435 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1436 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1437 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1438 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1439 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1440 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1441 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1442 };
1443 int i;
1444
76a66253 1445 /* Interrupt processing */
363be49c 1446 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 1447 SPR_NOACCESS, SPR_NOACCESS,
1448 &spr_read_generic, &spr_write_generic,
1449 0x00000000);
363be49c
JM		 1450 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1451 SPR_NOACCESS, SPR_NOACCESS,
1452 &spr_read_generic, &spr_write_generic,
1453 0x00000000);
76a66253
JM		 1454 /* Debug */
1455 /* XXX : not implemented */
1456 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1457 SPR_NOACCESS, SPR_NOACCESS,
1458 &spr_read_generic, &spr_write_generic,
1459 0x00000000);
1460 /* XXX : not implemented */
1461 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_generic, &spr_write_generic,
1464 0x00000000);
1465 /* XXX : not implemented */
76a66253
JM		 1466 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1467 SPR_NOACCESS, SPR_NOACCESS,
1468 &spr_read_generic, &spr_write_generic,
1469 0x00000000);
1470 /* XXX : not implemented */
1471 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1472 SPR_NOACCESS, SPR_NOACCESS,
1473 &spr_read_generic, &spr_write_generic,
1474 0x00000000);
1475 /* XXX : not implemented */
76a66253
JM		 1476 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_generic, &spr_write_generic,
1479 0x00000000);
1480 /* XXX : not implemented */
1481 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1482 SPR_NOACCESS, SPR_NOACCESS,
1483 &spr_read_generic, &spr_write_generic,
1484 0x00000000);
1485 /* XXX : not implemented */
1486 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_generic,
1489 0x00000000);
1490 /* XXX : not implemented */
1491 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1492 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1493 &spr_read_generic, &spr_write_clear,
76a66253
JM		 1494 0x00000000);
1495 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1496 SPR_NOACCESS, SPR_NOACCESS,
1497 &spr_read_generic, &spr_write_generic,
1498 0x00000000);
1499 spr_register(env, SPR_BOOKE_ESR, "ESR",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, &spr_write_generic,
1502 0x00000000);
363be49c
JM		 1503 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1504 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1505 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 1506 0x00000000);
1507 /* Exception vectors */
80d11f44
JM		 1508 for (i = 0; i < 64; i++) {
1509 if (ivor_mask & (1ULL << i)) {
1510 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1511 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1512 exit(1);
1513 }
1514 spr_register(env, ivor_sprn[i], ivor_names[i],
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_excp_vector,
1517 0x00000000);
1518 }
1519 }
76a66253
JM		 1520 spr_register(env, SPR_BOOKE_PID, "PID",
1521 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1522 &spr_read_generic, &spr_write_booke_pid,
76a66253
JM		 1523 0x00000000);
1524 spr_register(env, SPR_BOOKE_TCR, "TCR",
1525 SPR_NOACCESS, SPR_NOACCESS,
1526 &spr_read_generic, &spr_write_booke_tcr,
1527 0x00000000);
1528 spr_register(env, SPR_BOOKE_TSR, "TSR",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_booke_tsr,
1531 0x00000000);
1532 /* Timer */
1533 spr_register(env, SPR_DECR, "DECR",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_decr, &spr_write_decr,
1536 0x00000000);
1537 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1538 SPR_NOACCESS, SPR_NOACCESS,
1539 SPR_NOACCESS, &spr_write_generic,
1540 0x00000000);
1541 /* SPRGs */
1542 spr_register(env, SPR_USPRG0, "USPRG0",
1543 &spr_read_generic, &spr_write_generic,
1544 &spr_read_generic, &spr_write_generic,
1545 0x00000000);
1546 spr_register(env, SPR_SPRG4, "SPRG4",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
76a66253
JM		 1550 spr_register(env, SPR_SPRG5, "SPRG5",
1551 SPR_NOACCESS, SPR_NOACCESS,
1552 &spr_read_generic, &spr_write_generic,
1553 0x00000000);
76a66253
JM		 1554 spr_register(env, SPR_SPRG6, "SPRG6",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
76a66253
JM		 1558 spr_register(env, SPR_SPRG7, "SPRG7",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
76a66253
JM		 1562}
1563
01662f3e
AG		 1564static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1565 uint32_t maxsize, uint32_t flags,
1566 uint32_t nentries)
1567{
1568 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1569 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1570 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1571 flags | nentries;
1572}
1573
1574/* BookE 2.06 storage control registers */
1575static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1576 uint32_t *tlbncfg)
363be49c 1577{
f2e63a42 1578#if !defined(CONFIG_USER_ONLY)
b55266b5 1579 const char *mas_names[8] = {
80d11f44
JM		 1580 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1581 };
1582 int mas_sprn[8] = {
1583 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1584 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1585 };
1586 int i;
1587
363be49c 1588 /* TLB assist registers */
578bb252 1589 /* XXX : not implemented */
80d11f44
JM		 1590 for (i = 0; i < 8; i++) {
1591 if (mas_mask & (1 << i)) {
1592 spr_register(env, mas_sprn[i], mas_names[i],
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_generic,
1595 0x00000000);
1596 }
1597 }
363be49c 1598 if (env->nb_pids > 1) {
578bb252 1599 /* XXX : not implemented */
363be49c
JM		 1600 spr_register(env, SPR_BOOKE_PID1, "PID1",
1601 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1602 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1603 0x00000000);
1604 }
1605 if (env->nb_pids > 2) {
578bb252 1606 /* XXX : not implemented */
363be49c
JM		 1607 spr_register(env, SPR_BOOKE_PID2, "PID2",
1608 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 1609 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 1610 0x00000000);
1611 }
578bb252 1612 /* XXX : not implemented */
65f9ee8d 1613 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, SPR_NOACCESS,
1616 0x00000000); /* TOFIX */
363be49c
JM		 1617 switch (env->nb_ways) {
1618 case 4:
1619 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, SPR_NOACCESS,
01662f3e 1622 tlbncfg[3]);
363be49c
JM		 1623 /* Fallthru */
1624 case 3:
1625 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, SPR_NOACCESS,
01662f3e 1628 tlbncfg[2]);
363be49c
JM		 1629 /* Fallthru */
1630 case 2:
1631 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1632 SPR_NOACCESS, SPR_NOACCESS,
1633 &spr_read_generic, SPR_NOACCESS,
01662f3e 1634 tlbncfg[1]);
363be49c
JM		 1635 /* Fallthru */
1636 case 1:
1637 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1638 SPR_NOACCESS, SPR_NOACCESS,
1639 &spr_read_generic, SPR_NOACCESS,
01662f3e 1640 tlbncfg[0]);
363be49c
JM		 1641 /* Fallthru */
1642 case 0:
1643 default:
1644 break;
1645 }
f2e63a42 1646#endif
01662f3e
AG		 1647
1648 gen_spr_usprgh(env);
363be49c
JM		 1649}
1650
76a66253
JM		 1651/* SPR specific to PowerPC 440 implementation */
1652static void gen_spr_440 (CPUPPCState *env)
1653{
1654 /* Cache control */
1655 /* XXX : not implemented */
1656 spr_register(env, SPR_440_DNV0, "DNV0",
1657 SPR_NOACCESS, SPR_NOACCESS,
1658 &spr_read_generic, &spr_write_generic,
1659 0x00000000);
1660 /* XXX : not implemented */
1661 spr_register(env, SPR_440_DNV1, "DNV1",
1662 SPR_NOACCESS, SPR_NOACCESS,
1663 &spr_read_generic, &spr_write_generic,
1664 0x00000000);
1665 /* XXX : not implemented */
1666 spr_register(env, SPR_440_DNV2, "DNV2",
1667 SPR_NOACCESS, SPR_NOACCESS,
1668 &spr_read_generic, &spr_write_generic,
1669 0x00000000);
1670 /* XXX : not implemented */
1671 spr_register(env, SPR_440_DNV3, "DNV3",
1672 SPR_NOACCESS, SPR_NOACCESS,
1673 &spr_read_generic, &spr_write_generic,
1674 0x00000000);
1675 /* XXX : not implemented */
2662a059 1676 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 1677 SPR_NOACCESS, SPR_NOACCESS,
1678 &spr_read_generic, &spr_write_generic,
1679 0x00000000);
1680 /* XXX : not implemented */
2662a059 1681 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 1682 SPR_NOACCESS, SPR_NOACCESS,
1683 &spr_read_generic, &spr_write_generic,
1684 0x00000000);
1685 /* XXX : not implemented */
2662a059 1686 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 1687 SPR_NOACCESS, SPR_NOACCESS,
1688 &spr_read_generic, &spr_write_generic,
1689 0x00000000);
1690 /* XXX : not implemented */
2662a059 1691 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 1692 SPR_NOACCESS, SPR_NOACCESS,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
1695 /* XXX : not implemented */
1696 spr_register(env, SPR_440_DVLIM, "DVLIM",
1697 SPR_NOACCESS, SPR_NOACCESS,
1698 &spr_read_generic, &spr_write_generic,
1699 0x00000000);
1700 /* XXX : not implemented */
1701 spr_register(env, SPR_440_INV0, "INV0",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_generic,
1704 0x00000000);
1705 /* XXX : not implemented */
1706 spr_register(env, SPR_440_INV1, "INV1",
1707 SPR_NOACCESS, SPR_NOACCESS,
1708 &spr_read_generic, &spr_write_generic,
1709 0x00000000);
1710 /* XXX : not implemented */
1711 spr_register(env, SPR_440_INV2, "INV2",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, &spr_write_generic,
1714 0x00000000);
1715 /* XXX : not implemented */
1716 spr_register(env, SPR_440_INV3, "INV3",
1717 SPR_NOACCESS, SPR_NOACCESS,
1718 &spr_read_generic, &spr_write_generic,
1719 0x00000000);
1720 /* XXX : not implemented */
2662a059 1721 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 1722 SPR_NOACCESS, SPR_NOACCESS,
1723 &spr_read_generic, &spr_write_generic,
1724 0x00000000);
1725 /* XXX : not implemented */
2662a059 1726 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, &spr_write_generic,
1729 0x00000000);
1730 /* XXX : not implemented */
2662a059 1731 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1732 SPR_NOACCESS, SPR_NOACCESS,
1733 &spr_read_generic, &spr_write_generic,
1734 0x00000000);
1735 /* XXX : not implemented */
2662a059 1736 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, &spr_write_generic,
1739 0x00000000);
1740 /* XXX : not implemented */
1741 spr_register(env, SPR_440_IVLIM, "IVLIM",
1742 SPR_NOACCESS, SPR_NOACCESS,
1743 &spr_read_generic, &spr_write_generic,
1744 0x00000000);
1745 /* Cache debug */
1746 /* XXX : not implemented */
2662a059 1747 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1748 SPR_NOACCESS, SPR_NOACCESS,
1749 &spr_read_generic, SPR_NOACCESS,
1750 0x00000000);
1751 /* XXX : not implemented */
2662a059 1752 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1753 SPR_NOACCESS, SPR_NOACCESS,
1754 &spr_read_generic, SPR_NOACCESS,
1755 0x00000000);
1756 /* XXX : not implemented */
2662a059 1757 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, SPR_NOACCESS,
1760 0x00000000);
1761 /* XXX : not implemented */
2662a059 1762 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, SPR_NOACCESS,
1765 0x00000000);
1766 /* XXX : not implemented */
2662a059 1767 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, SPR_NOACCESS,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_440_DBDR, "DBDR",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, &spr_write_generic,
1775 0x00000000);
1776 /* Processor control */
1777 spr_register(env, SPR_4xx_CCR0, "CCR0",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1782 SPR_NOACCESS, SPR_NOACCESS,
1783 &spr_read_generic, SPR_NOACCESS,
1784 0x00000000);
1785 /* Storage control */
1786 spr_register(env, SPR_440_MMUCR, "MMUCR",
1787 SPR_NOACCESS, SPR_NOACCESS,
1788 &spr_read_generic, &spr_write_generic,
1789 0x00000000);
1790}
1791
1792/* SPR shared between PowerPC 40x implementations */
1793static void gen_spr_40x (CPUPPCState *env)
1794{
1795 /* Cache */
035feb88 1796 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1797 spr_register(env, SPR_40x_DCCR, "DCCR",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 &spr_read_generic, &spr_write_generic,
1800 0x00000000);
035feb88 1801 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1802 spr_register(env, SPR_40x_ICCR, "ICCR",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
578bb252 1806 /* not emulated, as Qemu do not emulate caches */
2662a059 1807 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, SPR_NOACCESS,
1810 0x00000000);
76a66253
JM		 1811 /* Exception */
1812 spr_register(env, SPR_40x_DEAR, "DEAR",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 spr_register(env, SPR_40x_ESR, "ESR",
1817 SPR_NOACCESS, SPR_NOACCESS,
1818 &spr_read_generic, &spr_write_generic,
1819 0x00000000);
1820 spr_register(env, SPR_40x_EVPR, "EVPR",
1821 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1822 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1823 0x00000000);
1824 spr_register(env, SPR_40x_SRR2, "SRR2",
1825 &spr_read_generic, &spr_write_generic,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 spr_register(env, SPR_40x_SRR3, "SRR3",
1829 &spr_read_generic, &spr_write_generic,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 /* Timers */
1833 spr_register(env, SPR_40x_PIT, "PIT",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_40x_pit, &spr_write_40x_pit,
1836 0x00000000);
1837 spr_register(env, SPR_40x_TCR, "TCR",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_booke_tcr,
1840 0x00000000);
1841 spr_register(env, SPR_40x_TSR, "TSR",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, &spr_write_booke_tsr,
1844 0x00000000);
2662a059
JM		 1845}
1846
1847/* SPR specific to PowerPC 405 implementation */
1848static void gen_spr_405 (CPUPPCState *env)
1849{
1850 /* MMU */
1851 spr_register(env, SPR_40x_PID, "PID",
76a66253
JM		 1852 SPR_NOACCESS, SPR_NOACCESS,
1853 &spr_read_generic, &spr_write_generic,
1854 0x00000000);
2662a059 1855 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1856 SPR_NOACCESS, SPR_NOACCESS,
1857 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1858 0x00700000);
1859 /* Debug interface */
76a66253
JM		 1860 /* XXX : not implemented */
1861 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1862 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1863 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253
JM		 1864 0x00000000);
1865 /* XXX : not implemented */
2662a059
JM		 1866 spr_register(env, SPR_405_DBCR1, "DBCR1",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_generic,
1869 0x00000000);
1870 /* XXX : not implemented */
76a66253
JM		 1871 spr_register(env, SPR_40x_DBSR, "DBSR",
1872 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1873 &spr_read_generic, &spr_write_clear,
1874 /* Last reset was system reset */
76a66253
JM		 1875 0x00000300);
1876 /* XXX : not implemented */
2662a059 1877 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, &spr_write_generic,
1880 0x00000000);
2662a059 1881 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1882 SPR_NOACCESS, SPR_NOACCESS,
1883 &spr_read_generic, &spr_write_generic,
1884 0x00000000);
2662a059
JM		 1885 /* XXX : not implemented */
1886 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_generic,
2662a059 1889 0x00000000);
76a66253 1890 /* XXX : not implemented */
2662a059 1891 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_generic,
1894 0x00000000);
1895 /* XXX : not implemented */
2662a059 1896 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_generic, &spr_write_generic,
1899 0x00000000);
2662a059 1900 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1901 SPR_NOACCESS, SPR_NOACCESS,
1902 &spr_read_generic, &spr_write_generic,
1903 0x00000000);
1904 /* XXX : not implemented */
1905 spr_register(env, SPR_405_IAC3, "IAC3",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 /* XXX : not implemented */
1910 spr_register(env, SPR_405_IAC4, "IAC4",
1911 SPR_NOACCESS, SPR_NOACCESS,
1912 &spr_read_generic, &spr_write_generic,
1913 0x00000000);
1914 /* Storage control */
035feb88 1915 /* XXX: TODO: not implemented */
76a66253
JM		 1916 spr_register(env, SPR_405_SLER, "SLER",
1917 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1918 &spr_read_generic, &spr_write_40x_sler,
76a66253 1919 0x00000000);
2662a059
JM		 1920 spr_register(env, SPR_40x_ZPR, "ZPR",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
76a66253
JM		 1924 /* XXX : not implemented */
1925 spr_register(env, SPR_405_SU0R, "SU0R",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 /* SPRG */
1930 spr_register(env, SPR_USPRG0, "USPRG0",
1931 &spr_read_ureg, SPR_NOACCESS,
1932 &spr_read_ureg, SPR_NOACCESS,
1933 0x00000000);
1934 spr_register(env, SPR_SPRG4, "SPRG4",
1935 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1936 &spr_read_generic, &spr_write_generic,
76a66253 1937 0x00000000);
76a66253
JM		 1938 spr_register(env, SPR_SPRG5, "SPRG5",
1939 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1940 spr_read_generic, &spr_write_generic,
76a66253 1941 0x00000000);
76a66253
JM		 1942 spr_register(env, SPR_SPRG6, "SPRG6",
1943 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1944 spr_read_generic, &spr_write_generic,
76a66253 1945 0x00000000);
76a66253
JM		 1946 spr_register(env, SPR_SPRG7, "SPRG7",
1947 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1948 spr_read_generic, &spr_write_generic,
76a66253 1949 0x00000000);
80d11f44 1950 gen_spr_usprgh(env);
76a66253
JM		 1951}
1952
1953/* SPR shared between PowerPC 401 & 403 implementations */
1954static void gen_spr_401_403 (CPUPPCState *env)
1955{
1956 /* Time base */
1957 spr_register(env, SPR_403_VTBL, "TBL",
1958 &spr_read_tbl, SPR_NOACCESS,
1959 &spr_read_tbl, SPR_NOACCESS,
1960 0x00000000);
1961 spr_register(env, SPR_403_TBL, "TBL",
1962 SPR_NOACCESS, SPR_NOACCESS,
1963 SPR_NOACCESS, &spr_write_tbl,
1964 0x00000000);
1965 spr_register(env, SPR_403_VTBU, "TBU",
1966 &spr_read_tbu, SPR_NOACCESS,
1967 &spr_read_tbu, SPR_NOACCESS,
1968 0x00000000);
1969 spr_register(env, SPR_403_TBU, "TBU",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 SPR_NOACCESS, &spr_write_tbu,
1972 0x00000000);
1973 /* Debug */
578bb252 1974 /* not emulated, as Qemu do not emulate caches */
76a66253
JM		 1975 spr_register(env, SPR_403_CDBCR, "CDBCR",
1976 SPR_NOACCESS, SPR_NOACCESS,
1977 &spr_read_generic, &spr_write_generic,
1978 0x00000000);
1979}
1980
2662a059
JM		 1981/* SPR specific to PowerPC 401 implementation */
1982static void gen_spr_401 (CPUPPCState *env)
1983{
1984 /* Debug interface */
1985 /* XXX : not implemented */
1986 spr_register(env, SPR_40x_DBCR0, "DBCR",
1987 SPR_NOACCESS, SPR_NOACCESS,
1988 &spr_read_generic, &spr_write_40x_dbcr0,
1989 0x00000000);
1990 /* XXX : not implemented */
1991 spr_register(env, SPR_40x_DBSR, "DBSR",
1992 SPR_NOACCESS, SPR_NOACCESS,
1993 &spr_read_generic, &spr_write_clear,
1994 /* Last reset was system reset */
1995 0x00000300);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_40x_DAC1, "DAC",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 /* XXX : not implemented */
2002 spr_register(env, SPR_40x_IAC1, "IAC",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006 /* Storage control */
035feb88 2007 /* XXX: TODO: not implemented */
2662a059
JM		 2008 spr_register(env, SPR_405_SLER, "SLER",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_40x_sler,
2011 0x00000000);
035feb88
JM		 2012 /* not emulated, as Qemu never does speculative access */
2013 spr_register(env, SPR_40x_SGR, "SGR",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0xFFFFFFFF);
2017 /* not emulated, as Qemu do not emulate caches */
2018 spr_register(env, SPR_40x_DCWR, "DCWR",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, &spr_write_generic,
2021 0x00000000);
2662a059
JM		 2022}
2023
a750fc0b
JM		 2024static void gen_spr_401x2 (CPUPPCState *env)
2025{
2026 gen_spr_401(env);
2027 spr_register(env, SPR_40x_PID, "PID",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
2031 spr_register(env, SPR_40x_ZPR, "ZPR",
2032 SPR_NOACCESS, SPR_NOACCESS,
2033 &spr_read_generic, &spr_write_generic,
2034 0x00000000);
2035}
2036
76a66253
JM		 2037/* SPR specific to PowerPC 403 implementation */
2038static void gen_spr_403 (CPUPPCState *env)
2039{
2662a059
JM		 2040 /* Debug interface */
2041 /* XXX : not implemented */
2042 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_40x_dbcr0,
2045 0x00000000);
2046 /* XXX : not implemented */
2047 spr_register(env, SPR_40x_DBSR, "DBSR",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 &spr_read_generic, &spr_write_clear,
2050 /* Last reset was system reset */
2051 0x00000300);
2052 /* XXX : not implemented */
2053 spr_register(env, SPR_40x_DAC1, "DAC1",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, &spr_write_generic,
2056 0x00000000);
578bb252 2057 /* XXX : not implemented */
2662a059
JM		 2058 spr_register(env, SPR_40x_DAC2, "DAC2",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062 /* XXX : not implemented */
2063 spr_register(env, SPR_40x_IAC1, "IAC1",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_generic, &spr_write_generic,
2066 0x00000000);
578bb252 2067 /* XXX : not implemented */
2662a059
JM		 2068 spr_register(env, SPR_40x_IAC2, "IAC2",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
a750fc0b
JM		 2072}
2073
2074static void gen_spr_403_real (CPUPPCState *env)
2075{
76a66253
JM		 2076 spr_register(env, SPR_403_PBL1, "PBL1",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_403_pbr, &spr_write_403_pbr,
2079 0x00000000);
2080 spr_register(env, SPR_403_PBU1, "PBU1",
2081 SPR_NOACCESS, SPR_NOACCESS,
2082 &spr_read_403_pbr, &spr_write_403_pbr,
2083 0x00000000);
2084 spr_register(env, SPR_403_PBL2, "PBL2",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_403_pbr, &spr_write_403_pbr,
2087 0x00000000);
2088 spr_register(env, SPR_403_PBU2, "PBU2",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_403_pbr, &spr_write_403_pbr,
2091 0x00000000);
a750fc0b
JM		 2092}
2093
2094static void gen_spr_403_mmu (CPUPPCState *env)
2095{
2096 /* MMU */
2097 spr_register(env, SPR_40x_PID, "PID",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2662a059 2101 spr_register(env, SPR_40x_ZPR, "ZPR",
76a66253
JM		 2102 SPR_NOACCESS, SPR_NOACCESS,
2103 &spr_read_generic, &spr_write_generic,
2104 0x00000000);
2105}
2106
2107/* SPR specific to PowerPC compression coprocessor extension */
76a66253
JM		 2108static void gen_spr_compress (CPUPPCState *env)
2109{
578bb252 2110 /* XXX : not implemented */
76a66253
JM		 2111 spr_register(env, SPR_401_SKR, "SKR",
2112 SPR_NOACCESS, SPR_NOACCESS,
2113 &spr_read_generic, &spr_write_generic,
2114 0x00000000);
2115}
a750fc0b
JM		 2116
2117#if defined (TARGET_PPC64)
a750fc0b
JM		 2118/* SPR specific to PowerPC 620 */
2119static void gen_spr_620 (CPUPPCState *env)
2120{
082c6681
JM		 2121 /* Processor identification */
2122 spr_register(env, SPR_PIR, "PIR",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, &spr_write_pir,
2125 0x00000000);
2126 spr_register(env, SPR_ASR, "ASR",
2127 SPR_NOACCESS, SPR_NOACCESS,
2128 &spr_read_asr, &spr_write_asr,
2129 0x00000000);
2130 /* Breakpoints */
2131 /* XXX : not implemented */
2132 spr_register(env, SPR_IABR, "IABR",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 /* XXX : not implemented */
2137 spr_register(env, SPR_DABR, "DABR",
2138 SPR_NOACCESS, SPR_NOACCESS,
2139 &spr_read_generic, &spr_write_generic,
2140 0x00000000);
2141 /* XXX : not implemented */
2142 spr_register(env, SPR_SIAR, "SIAR",
2143 SPR_NOACCESS, SPR_NOACCESS,
2144 &spr_read_generic, SPR_NOACCESS,
2145 0x00000000);
2146 /* XXX : not implemented */
2147 spr_register(env, SPR_SDA, "SDA",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_generic, SPR_NOACCESS,
2150 0x00000000);
2151 /* XXX : not implemented */
2152 spr_register(env, SPR_620_PMC1R, "PMC1",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, SPR_NOACCESS,
2155 0x00000000);
2156 spr_register(env, SPR_620_PMC1W, "PMC1",
2157 SPR_NOACCESS, SPR_NOACCESS,
2158 SPR_NOACCESS, &spr_write_generic,
2159 0x00000000);
2160 /* XXX : not implemented */
2161 spr_register(env, SPR_620_PMC2R, "PMC2",
2162 SPR_NOACCESS, SPR_NOACCESS,
2163 &spr_read_generic, SPR_NOACCESS,
2164 0x00000000);
2165 spr_register(env, SPR_620_PMC2W, "PMC2",
2166 SPR_NOACCESS, SPR_NOACCESS,
2167 SPR_NOACCESS, &spr_write_generic,
2168 0x00000000);
2169 /* XXX : not implemented */
2170 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2171 SPR_NOACCESS, SPR_NOACCESS,
2172 &spr_read_generic, SPR_NOACCESS,
2173 0x00000000);
2174 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2175 SPR_NOACCESS, SPR_NOACCESS,
2176 SPR_NOACCESS, &spr_write_generic,
2177 0x00000000);
2178 /* External access control */
2179 /* XXX : not implemented */
2180 spr_register(env, SPR_EAR, "EAR",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_generic, &spr_write_generic,
2183 0x00000000);
2184#if 0 // XXX: check this
578bb252 2185 /* XXX : not implemented */
a750fc0b
JM		 2186 spr_register(env, SPR_620_PMR0, "PMR0",
2187 SPR_NOACCESS, SPR_NOACCESS,
2188 &spr_read_generic, &spr_write_generic,
2189 0x00000000);
578bb252 2190 /* XXX : not implemented */
a750fc0b
JM		 2191 spr_register(env, SPR_620_PMR1, "PMR1",
2192 SPR_NOACCESS, SPR_NOACCESS,
2193 &spr_read_generic, &spr_write_generic,
2194 0x00000000);
578bb252 2195 /* XXX : not implemented */
a750fc0b
JM		 2196 spr_register(env, SPR_620_PMR2, "PMR2",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_generic,
2199 0x00000000);
578bb252 2200 /* XXX : not implemented */
a750fc0b
JM		 2201 spr_register(env, SPR_620_PMR3, "PMR3",
2202 SPR_NOACCESS, SPR_NOACCESS,
2203 &spr_read_generic, &spr_write_generic,
2204 0x00000000);
578bb252 2205 /* XXX : not implemented */
a750fc0b
JM		 2206 spr_register(env, SPR_620_PMR4, "PMR4",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
578bb252 2210 /* XXX : not implemented */
a750fc0b
JM		 2211 spr_register(env, SPR_620_PMR5, "PMR5",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
578bb252 2215 /* XXX : not implemented */
a750fc0b
JM		 2216 spr_register(env, SPR_620_PMR6, "PMR6",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 0x00000000);
578bb252 2220 /* XXX : not implemented */
a750fc0b
JM		 2221 spr_register(env, SPR_620_PMR7, "PMR7",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_generic, &spr_write_generic,
2224 0x00000000);
578bb252 2225 /* XXX : not implemented */
a750fc0b
JM		 2226 spr_register(env, SPR_620_PMR8, "PMR8",
2227 SPR_NOACCESS, SPR_NOACCESS,
2228 &spr_read_generic, &spr_write_generic,
2229 0x00000000);
578bb252 2230 /* XXX : not implemented */
a750fc0b
JM		 2231 spr_register(env, SPR_620_PMR9, "PMR9",
2232 SPR_NOACCESS, SPR_NOACCESS,
2233 &spr_read_generic, &spr_write_generic,
2234 0x00000000);
578bb252 2235 /* XXX : not implemented */
a750fc0b
JM		 2236 spr_register(env, SPR_620_PMRA, "PMR10",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
578bb252 2240 /* XXX : not implemented */
a750fc0b
JM		 2241 spr_register(env, SPR_620_PMRB, "PMR11",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
578bb252 2245 /* XXX : not implemented */
a750fc0b
JM		 2246 spr_register(env, SPR_620_PMRC, "PMR12",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
578bb252 2250 /* XXX : not implemented */
a750fc0b
JM		 2251 spr_register(env, SPR_620_PMRD, "PMR13",
2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
578bb252 2255 /* XXX : not implemented */
a750fc0b
JM		 2256 spr_register(env, SPR_620_PMRE, "PMR14",
2257 SPR_NOACCESS, SPR_NOACCESS,
2258 &spr_read_generic, &spr_write_generic,
2259 0x00000000);
578bb252 2260 /* XXX : not implemented */
a750fc0b
JM		 2261 spr_register(env, SPR_620_PMRF, "PMR15",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
082c6681 2265#endif
578bb252 2266 /* XXX : not implemented */
082c6681 2267 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
a750fc0b
JM		 2268 SPR_NOACCESS, SPR_NOACCESS,
2269 &spr_read_generic, &spr_write_generic,
2270 0x00000000);
578bb252 2271 /* XXX : not implemented */
082c6681
JM		 2272 spr_register(env, SPR_620_L2CR, "L2CR",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_generic,
2275 0x00000000);
2276 /* XXX : not implemented */
2277 spr_register(env, SPR_620_L2SR, "L2SR",
a750fc0b
JM		 2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_generic,
2280 0x00000000);
2281}
a750fc0b 2282#endif /* defined (TARGET_PPC64) */
76a66253 2283
80d11f44 2284static void gen_spr_5xx_8xx (CPUPPCState *env)
e1833e1f 2285{
80d11f44
JM		 2286 /* Exception processing */
2287 spr_register(env, SPR_DSISR, "DSISR",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0x00000000);
2291 spr_register(env, SPR_DAR, "DAR",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_generic, &spr_write_generic,
2294 0x00000000);
2295 /* Timer */
2296 spr_register(env, SPR_DECR, "DECR",
2297 SPR_NOACCESS, SPR_NOACCESS,
2298 &spr_read_decr, &spr_write_decr,
2299 0x00000000);
2300 /* XXX : not implemented */
2301 spr_register(env, SPR_MPC_EIE, "EIE",
2302 SPR_NOACCESS, SPR_NOACCESS,
2303 &spr_read_generic, &spr_write_generic,
2304 0x00000000);
2305 /* XXX : not implemented */
2306 spr_register(env, SPR_MPC_EID, "EID",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_generic, &spr_write_generic,
2309 0x00000000);
2310 /* XXX : not implemented */
2311 spr_register(env, SPR_MPC_NRI, "NRI",
2312 SPR_NOACCESS, SPR_NOACCESS,
2313 &spr_read_generic, &spr_write_generic,
2314 0x00000000);
2315 /* XXX : not implemented */
2316 spr_register(env, SPR_MPC_CMPA, "CMPA",
2317 SPR_NOACCESS, SPR_NOACCESS,
2318 &spr_read_generic, &spr_write_generic,
2319 0x00000000);
2320 /* XXX : not implemented */
2321 spr_register(env, SPR_MPC_CMPB, "CMPB",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_generic, &spr_write_generic,
2324 0x00000000);
2325 /* XXX : not implemented */
2326 spr_register(env, SPR_MPC_CMPC, "CMPC",
2327 SPR_NOACCESS, SPR_NOACCESS,
2328 &spr_read_generic, &spr_write_generic,
2329 0x00000000);
2330 /* XXX : not implemented */
2331 spr_register(env, SPR_MPC_CMPD, "CMPD",
2332 SPR_NOACCESS, SPR_NOACCESS,
2333 &spr_read_generic, &spr_write_generic,
2334 0x00000000);
2335 /* XXX : not implemented */
2336 spr_register(env, SPR_MPC_ECR, "ECR",
2337 SPR_NOACCESS, SPR_NOACCESS,
2338 &spr_read_generic, &spr_write_generic,
2339 0x00000000);
2340 /* XXX : not implemented */
2341 spr_register(env, SPR_MPC_DER, "DER",
2342 SPR_NOACCESS, SPR_NOACCESS,
2343 &spr_read_generic, &spr_write_generic,
2344 0x00000000);
2345 /* XXX : not implemented */
2346 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2347 SPR_NOACCESS, SPR_NOACCESS,
2348 &spr_read_generic, &spr_write_generic,
2349 0x00000000);
2350 /* XXX : not implemented */
2351 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
2355 /* XXX : not implemented */
2356 spr_register(env, SPR_MPC_CMPE, "CMPE",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360 /* XXX : not implemented */
2361 spr_register(env, SPR_MPC_CMPF, "CMPF",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2365 /* XXX : not implemented */
2366 spr_register(env, SPR_MPC_CMPG, "CMPG",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_generic, &spr_write_generic,
2369 0x00000000);
2370 /* XXX : not implemented */
2371 spr_register(env, SPR_MPC_CMPH, "CMPH",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_MPC_BAR, "BAR",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_MPC_DPDR, "DPDR",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_MPC_IMMR, "IMMR",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400}
2401
2402static void gen_spr_5xx (CPUPPCState *env)
2403{
2404 /* XXX : not implemented */
2405 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2406 SPR_NOACCESS, SPR_NOACCESS,
2407 &spr_read_generic, &spr_write_generic,
2408 0x00000000);
2409 /* XXX : not implemented */
2410 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2411 SPR_NOACCESS, SPR_NOACCESS,
2412 &spr_read_generic, &spr_write_generic,
2413 0x00000000);
2414 /* XXX : not implemented */
2415 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2416 SPR_NOACCESS, SPR_NOACCESS,
2417 &spr_read_generic, &spr_write_generic,
2418 0x00000000);
2419 /* XXX : not implemented */
2420 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2421 SPR_NOACCESS, SPR_NOACCESS,
2422 &spr_read_generic, &spr_write_generic,
2423 0x00000000);
2424 /* XXX : not implemented */
2425 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 /* XXX : not implemented */
2435 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2436 SPR_NOACCESS, SPR_NOACCESS,
2437 &spr_read_generic, &spr_write_generic,
2438 0x00000000);
2439 /* XXX : not implemented */
2440 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2441 SPR_NOACCESS, SPR_NOACCESS,
2442 &spr_read_generic, &spr_write_generic,
2443 0x00000000);
2444 /* XXX : not implemented */
2445 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2446 SPR_NOACCESS, SPR_NOACCESS,
2447 &spr_read_generic, &spr_write_generic,
2448 0x00000000);
2449 /* XXX : not implemented */
2450 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2451 SPR_NOACCESS, SPR_NOACCESS,
2452 &spr_read_generic, &spr_write_generic,
2453 0x00000000);
2454 /* XXX : not implemented */
2455 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 /* XXX : not implemented */
2460 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2461 SPR_NOACCESS, SPR_NOACCESS,
2462 &spr_read_generic, &spr_write_generic,
2463 0x00000000);
2464 /* XXX : not implemented */
2465 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 /* XXX : not implemented */
2470 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_generic, &spr_write_generic,
2473 0x00000000);
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509}
2510
2511static void gen_spr_8xx (CPUPPCState *env)
2512{
2513 /* XXX : not implemented */
2514 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2515 SPR_NOACCESS, SPR_NOACCESS,
2516 &spr_read_generic, &spr_write_generic,
2517 0x00000000);
2518 /* XXX : not implemented */
2519 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2520 SPR_NOACCESS, SPR_NOACCESS,
2521 &spr_read_generic, &spr_write_generic,
2522 0x00000000);
2523 /* XXX : not implemented */
2524 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2525 SPR_NOACCESS, SPR_NOACCESS,
2526 &spr_read_generic, &spr_write_generic,
2527 0x00000000);
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 /* XXX : not implemented */
2564 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2565 SPR_NOACCESS, SPR_NOACCESS,
2566 &spr_read_generic, &spr_write_generic,
2567 0x00000000);
2568 /* XXX : not implemented */
2569 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2570 SPR_NOACCESS, SPR_NOACCESS,
2571 &spr_read_generic, &spr_write_generic,
2572 0x00000000);
2573 /* XXX : not implemented */
2574 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2575 SPR_NOACCESS, SPR_NOACCESS,
2576 &spr_read_generic, &spr_write_generic,
2577 0x00000000);
2578 /* XXX : not implemented */
2579 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2580 SPR_NOACCESS, SPR_NOACCESS,
2581 &spr_read_generic, &spr_write_generic,
2582 0x00000000);
2583 /* XXX : not implemented */
2584 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2585 SPR_NOACCESS, SPR_NOACCESS,
2586 &spr_read_generic, &spr_write_generic,
2587 0x00000000);
2588 /* XXX : not implemented */
2589 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2590 SPR_NOACCESS, SPR_NOACCESS,
2591 &spr_read_generic, &spr_write_generic,
2592 0x00000000);
2593 /* XXX : not implemented */
2594 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2595 SPR_NOACCESS, SPR_NOACCESS,
2596 &spr_read_generic, &spr_write_generic,
2597 0x00000000);
2598 /* XXX : not implemented */
2599 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2600 SPR_NOACCESS, SPR_NOACCESS,
2601 &spr_read_generic, &spr_write_generic,
2602 0x00000000);
2603 /* XXX : not implemented */
2604 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2605 SPR_NOACCESS, SPR_NOACCESS,
2606 &spr_read_generic, &spr_write_generic,
2607 0x00000000);
2608 /* XXX : not implemented */
2609 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2610 SPR_NOACCESS, SPR_NOACCESS,
2611 &spr_read_generic, &spr_write_generic,
2612 0x00000000);
2613 /* XXX : not implemented */
2614 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2615 SPR_NOACCESS, SPR_NOACCESS,
2616 &spr_read_generic, &spr_write_generic,
2617 0x00000000);
2618 /* XXX : not implemented */
2619 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2622 0x00000000);
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 /* XXX : not implemented */
2629 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2630 SPR_NOACCESS, SPR_NOACCESS,
2631 &spr_read_generic, &spr_write_generic,
2632 0x00000000);
2633 /* XXX : not implemented */
2634 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2635 SPR_NOACCESS, SPR_NOACCESS,
2636 &spr_read_generic, &spr_write_generic,
2637 0x00000000);
2638}
2639
2640// XXX: TODO
2641/*
2642 * AMR => SPR 29 (Power 2.04)
2643 * CTRL => SPR 136 (Power 2.04)
2644 * CTRL => SPR 152 (Power 2.04)
2645 * SCOMC => SPR 276 (64 bits ?)
2646 * SCOMD => SPR 277 (64 bits ?)
2647 * TBU40 => SPR 286 (Power 2.04 hypv)
2648 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2649 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2650 * HDSISR => SPR 306 (Power 2.04 hypv)
2651 * HDAR => SPR 307 (Power 2.04 hypv)
2652 * PURR => SPR 309 (Power 2.04 hypv)
2653 * HDEC => SPR 310 (Power 2.04 hypv)
2654 * HIOR => SPR 311 (hypv)
2655 * RMOR => SPR 312 (970)
2656 * HRMOR => SPR 313 (Power 2.04 hypv)
2657 * HSRR0 => SPR 314 (Power 2.04 hypv)
2658 * HSRR1 => SPR 315 (Power 2.04 hypv)
2659 * LPCR => SPR 316 (970)
2660 * LPIDR => SPR 317 (970)
80d11f44
JM		 2661 * EPR => SPR 702 (Power 2.04 emb)
2662 * perf => 768-783 (Power 2.04)
2663 * perf => 784-799 (Power 2.04)
2664 * PPR => SPR 896 (Power 2.04)
2665 * EPLC => SPR 947 (Power 2.04 emb)
2666 * EPSC => SPR 948 (Power 2.04 emb)
2667 * DABRX => 1015 (Power 2.04 hypv)
2668 * FPECR => SPR 1022 (?)
2669 * ... and more (thermal management, performance counters, ...)
2670 */
2671
2672/*****************************************************************************/
2673/* Exception vectors models */
2674static void init_excp_4xx_real (CPUPPCState *env)
2675{
2676#if !defined(CONFIG_USER_ONLY)
2677 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2678 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2679 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2680 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2681 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2682 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2683 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2684 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2685 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2686 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2687 env->hreset_excp_prefix = 0x00000000UL;
80d11f44 2688 env->ivor_mask = 0x0000FFF0UL;
faadf50e 2689 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb
JM		 2690 /* Hardware reset vector */
2691 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2692#endif
2693}
2694
80d11f44
JM		 2695static void init_excp_4xx_softmmu (CPUPPCState *env)
2696{
2697#if !defined(CONFIG_USER_ONLY)
2698 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2699 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2700 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2701 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2702 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2703 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2704 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2705 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2706 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2707 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2708 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2709 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2710 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2711 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
fc1c67bc 2712 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2713 env->ivor_mask = 0x0000FFF0UL;
2714 env->ivpr_mask = 0xFFFF0000UL;
2715 /* Hardware reset vector */
2716 env->hreset_vector = 0xFFFFFFFCUL;
2717#endif
2718}
2719
2720static void init_excp_MPC5xx (CPUPPCState *env)
2721{
2722#if !defined(CONFIG_USER_ONLY)
2723 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2724 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2725 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2726 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2727 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2728 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2729 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2730 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2731 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2732 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2733 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2734 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2735 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2736 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2737 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2738 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2739 env->ivor_mask = 0x0000FFF0UL;
2740 env->ivpr_mask = 0xFFFF0000UL;
2741 /* Hardware reset vector */
2742 env->hreset_vector = 0xFFFFFFFCUL;
2743#endif
2744}
2745
2746static void init_excp_MPC8xx (CPUPPCState *env)
e1833e1f
JM		 2747{
2748#if !defined(CONFIG_USER_ONLY)
2749 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2750 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2751 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2752 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2753 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2754 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2755 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
80d11f44 2756 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
e1833e1f 2757 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2758 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 2759 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2760 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2761 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2762 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2763 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2764 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2765 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2766 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2767 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2768 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2769 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
fc1c67bc 2770 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2771 env->ivor_mask = 0x0000FFF0UL;
2772 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 2773 /* Hardware reset vector */
80d11f44 2774 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2775#endif
2776}
2777
80d11f44 2778static void init_excp_G2 (CPUPPCState *env)
e1833e1f
JM		 2779{
2780#if !defined(CONFIG_USER_ONLY)
2781 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2782 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2783 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2784 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2785 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2786 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2787 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2788 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2789 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 2790 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 2791 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2792 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2793 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2794 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2795 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2796 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2797 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2798 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2799 /* Hardware reset vector */
2800 env->hreset_vector = 0xFFFFFFFCUL;
2801#endif
2802}
2803
2804static void init_excp_e200 (CPUPPCState *env)
2805{
2806#if !defined(CONFIG_USER_ONLY)
2807 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2808 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2809 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2810 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2811 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2812 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2813 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2814 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2815 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2816 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2817 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2818 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2819 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2820 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2821 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2822 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2823 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2824 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2825 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2826 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
fc1c67bc 2827 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2828 env->ivor_mask = 0x0000FFF7UL;
2829 env->ivpr_mask = 0xFFFF0000UL;
2830 /* Hardware reset vector */
2831 env->hreset_vector = 0xFFFFFFFCUL;
2832#endif
2833}
2834
2835static void init_excp_BookE (CPUPPCState *env)
2836{
2837#if !defined(CONFIG_USER_ONLY)
2838 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2839 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2840 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2841 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2842 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2843 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2844 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2845 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2846 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2847 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2848 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2849 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2850 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2851 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2852 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2853 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
fc1c67bc 2854 env->hreset_excp_prefix = 0x00000000UL;
80d11f44
JM		 2855 env->ivor_mask = 0x0000FFE0UL;
2856 env->ivpr_mask = 0xFFFF0000UL;
2857 /* Hardware reset vector */
2858 env->hreset_vector = 0xFFFFFFFCUL;
2859#endif
2860}
2861
2862static void init_excp_601 (CPUPPCState *env)
2863{
2864#if !defined(CONFIG_USER_ONLY)
2865 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2866 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2867 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2868 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2869 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2870 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2871 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2872 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2873 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2874 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2875 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2876 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
fc1c67bc 2877 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2878 /* Hardware reset vector */
80d11f44 2879 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2880#endif
2881}
2882
80d11f44 2883static void init_excp_602 (CPUPPCState *env)
e1833e1f
JM		 2884{
2885#if !defined(CONFIG_USER_ONLY)
082c6681 2886 /* XXX: exception prefix has a special behavior on 602 */
e1833e1f
JM		 2887 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2888 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2889 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2890 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2891 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2892 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2893 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2894 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2895 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2896 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2897 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2898 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2899 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2900 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2901 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2902 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44
JM		 2903 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2904 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
fc1c67bc 2905 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb
JM		 2906 /* Hardware reset vector */
2907 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2908#endif
2909}
2910
80d11f44 2911static void init_excp_603 (CPUPPCState *env)
e1833e1f
JM		 2912{
2913#if !defined(CONFIG_USER_ONLY)
2914 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2915 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2916 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2917 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2918 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2919 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2920 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2921 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2922 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 2923 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2924 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2925 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2926 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2927 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2928 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2929 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2930 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 2931 /* Hardware reset vector */
2932 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 2933#endif
2934}
2935
2936static void init_excp_604 (CPUPPCState *env)
2937{
2938#if !defined(CONFIG_USER_ONLY)
2939 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2940 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2941 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2942 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2943 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2944 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2945 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2946 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2947 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2948 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2949 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2950 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2951 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2952 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2d3eb7bf 2953 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2954 /* Hardware reset vector */
2d3eb7bf 2955 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 2956#endif
2957}
2958
578bb252 2959#if defined(TARGET_PPC64)
e1833e1f
JM		 2960static void init_excp_620 (CPUPPCState *env)
2961{
2962#if !defined(CONFIG_USER_ONLY)
2963 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2964 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2965 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2966 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2967 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2968 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2969 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2970 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2971 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2972 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2973 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 2974 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2975 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2976 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 2977 env->hreset_excp_prefix = 0xFFF00000UL;
1c27f8fb 2978 /* Hardware reset vector */
faadf50e 2979 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2980#endif
2981}
578bb252 2982#endif /* defined(TARGET_PPC64) */
e1833e1f
JM		 2983
2984static void init_excp_7x0 (CPUPPCState *env)
2985{
2986#if !defined(CONFIG_USER_ONLY)
2987 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2988 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2989 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2990 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2991 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2992 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2993 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2994 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2995 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2996 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2997 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2998 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2999 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 3000 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 3001 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3002 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3003 /* Hardware reset vector */
3004 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3005#endif
3006}
3007
bd928eba 3008static void init_excp_750cl (CPUPPCState *env)
e1833e1f
JM		 3009{
3010#if !defined(CONFIG_USER_ONLY)
3011 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3012 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3013 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3014 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3015 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3016 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3017 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3018 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3019 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3020 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3021 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3022 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3023 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3024 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
fc1c67bc 3025 env->hreset_excp_prefix = 0x00000000UL;
bd928eba
JM		 3026 /* Hardware reset vector */
3027 env->hreset_vector = 0xFFFFFFFCUL;
3028#endif
3029}
3030
3031static void init_excp_750cx (CPUPPCState *env)
3032{
3033#if !defined(CONFIG_USER_ONLY)
3034 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3035 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3036 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3037 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3038 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3039 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3040 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3041 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3042 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3043 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3044 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3045 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3046 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 3047 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3048 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3049 /* Hardware reset vector */
3050 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3051#endif
3052}
3053
7a3a6927
JM		 3054/* XXX: Check if this is correct */
3055static void init_excp_7x5 (CPUPPCState *env)
3056{
3057#if !defined(CONFIG_USER_ONLY)
3058 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3059 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3060 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3061 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3062 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3063 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3064 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3065 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3066 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3067 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3068 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 3069 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 3070 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3071 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3072 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 3073 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3074 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 3075 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3076 env->hreset_excp_prefix = 0x00000000UL;
7a3a6927
JM		 3077 /* Hardware reset vector */
3078 env->hreset_vector = 0xFFFFFFFCUL;
3079#endif
3080}
3081
e1833e1f
JM		 3082static void init_excp_7400 (CPUPPCState *env)
3083{
3084#if !defined(CONFIG_USER_ONLY)
3085 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3086 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3087 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3088 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3089 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3090 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3091 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3092 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3093 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3094 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3095 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3096 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3097 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3098 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3099 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3100 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3101 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
fc1c67bc 3102 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3103 /* Hardware reset vector */
3104 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3105#endif
3106}
3107
e1833e1f
JM		 3108static void init_excp_7450 (CPUPPCState *env)
3109{
3110#if !defined(CONFIG_USER_ONLY)
3111 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3112 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3113 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3114 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3115 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3116 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3117 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3118 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3119 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3120 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3121 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3122 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3123 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3124 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3125 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3126 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3127 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3128 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3129 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
fc1c67bc 3130 env->hreset_excp_prefix = 0x00000000UL;
1c27f8fb
JM		 3131 /* Hardware reset vector */
3132 env->hreset_vector = 0xFFFFFFFCUL;
e1833e1f
JM		 3133#endif
3134}
e1833e1f
JM		 3135
3136#if defined (TARGET_PPC64)
3137static void init_excp_970 (CPUPPCState *env)
3138{
3139#if !defined(CONFIG_USER_ONLY)
3140 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3141 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3142 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3143 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3144 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3145 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3146 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3147 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3148 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3149 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3150 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 3151 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 3152 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3153 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3154 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3155 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3156 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3157 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3158 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3159 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
fc1c67bc 3160 env->hreset_excp_prefix = 0x00000000FFF00000ULL;
1c27f8fb
JM		 3161 /* Hardware reset vector */
3162 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 3163#endif
3164}
9d52e907
DG		 3165
3166static void init_excp_POWER7 (CPUPPCState *env)
3167{
3168#if !defined(CONFIG_USER_ONLY)
3169 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3170 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3171 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3172 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3173 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3174 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3175 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3176 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3177 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3178 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3179 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3180 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3181 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3182 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3183 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3184 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3185 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3186 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3187 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3188 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3189 env->hreset_excp_prefix = 0;
3190 /* Hardware reset vector */
3191 env->hreset_vector = 0x0000000000000100ULL;
3192#endif
3193}
e1833e1f
JM		 3194#endif
3195
2f462816
JM		 3196/*****************************************************************************/
3197/* Power management enable checks */
3198static int check_pow_none (CPUPPCState *env)
3199{
3200 return 0;
3201}
3202
3203static int check_pow_nocheck (CPUPPCState *env)
3204{
3205 return 1;
3206}
3207
3208static int check_pow_hid0 (CPUPPCState *env)
3209{
3210 if (env->spr[SPR_HID0] & 0x00E00000)
3211 return 1;
3212
3213 return 0;
3214}
3215
4e777442
JM		 3216static int check_pow_hid0_74xx (CPUPPCState *env)
3217{
3218 if (env->spr[SPR_HID0] & 0x00600000)
3219 return 1;
3220
3221 return 0;
3222}
3223
a750fc0b
JM		 3224/*****************************************************************************/
3225/* PowerPC implementations definitions */
76a66253 3226
a750fc0b 3227/* PowerPC 401 */
082c6681
JM		 3228#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3229 PPC_WRTEE | PPC_DCR | \
3230 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3231 PPC_CACHE_DCBZ | \
a750fc0b 3232 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3233 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3234#define POWERPC_INSNS2_401 (PPC_NONE)
a750fc0b 3235#define POWERPC_MSRM_401 (0x00000000000FD201ULL)
b4095fed 3236#define POWERPC_MMU_401 (POWERPC_MMU_REAL)
a750fc0b
JM		 3237#define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3238#define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
237c0af0 3239#define POWERPC_BFDM_401 (bfd_mach_ppc_403)
4018bae9
JM		 3240#define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3241 POWERPC_FLAG_BUS_CLK)
2f462816 3242#define check_pow_401 check_pow_nocheck
76a66253 3243
a750fc0b
JM		 3244static void init_proc_401 (CPUPPCState *env)
3245{
3246 gen_spr_40x(env);
3247 gen_spr_401_403(env);
3248 gen_spr_401(env);
e1833e1f 3249 init_excp_4xx_real(env);
d63001d1
JM		 3250 env->dcache_line_size = 32;
3251 env->icache_line_size = 32;
4e290a0b
JM		 3252 /* Allocate hardware IRQ controller */
3253 ppc40x_irq_init(env);
a750fc0b 3254}
76a66253 3255
a750fc0b 3256/* PowerPC 401x2 */
082c6681
JM		 3257#define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3258 PPC_DCR | PPC_WRTEE | \
3259 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3260 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3261 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3262 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3263 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3264#define POWERPC_INSNS2_401x2 (PPC_NONE)
a750fc0b
JM		 3265#define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3266#define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3267#define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3268#define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
237c0af0 3269#define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
4018bae9
JM		 3270#define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3271 POWERPC_FLAG_BUS_CLK)
2f462816 3272#define check_pow_401x2 check_pow_nocheck
a750fc0b
JM		 3273
3274static void init_proc_401x2 (CPUPPCState *env)
3275{
3276 gen_spr_40x(env);
3277 gen_spr_401_403(env);
3278 gen_spr_401x2(env);
3279 gen_spr_compress(env);
a750fc0b 3280 /* Memory management */
f2e63a42 3281#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3282 env->nb_tlb = 64;
3283 env->nb_ways = 1;
3284 env->id_tlbs = 0;
f2e63a42 3285#endif
e1833e1f 3286 init_excp_4xx_softmmu(env);
d63001d1
JM		 3287 env->dcache_line_size = 32;
3288 env->icache_line_size = 32;
4e290a0b
JM		 3289 /* Allocate hardware IRQ controller */
3290 ppc40x_irq_init(env);
76a66253
JM		 3291}
3292
a750fc0b 3293/* PowerPC 401x3 */
082c6681
JM		 3294#define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3295 PPC_DCR | PPC_WRTEE | \
3296 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3297 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3298 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3299 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3300 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3301#define POWERPC_INSNS2_401x3 (PPC_NONE)
a750fc0b
JM		 3302#define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3303#define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3304#define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3305#define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
237c0af0 3306#define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
4018bae9
JM		 3307#define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3308 POWERPC_FLAG_BUS_CLK)
2f462816 3309#define check_pow_401x3 check_pow_nocheck
a750fc0b 3310
578bb252 3311__attribute__ (( unused ))
e1833e1f 3312static void init_proc_401x3 (CPUPPCState *env)
76a66253 3313{
4e290a0b
JM		 3314 gen_spr_40x(env);
3315 gen_spr_401_403(env);
3316 gen_spr_401(env);
3317 gen_spr_401x2(env);
3318 gen_spr_compress(env);
e1833e1f 3319 init_excp_4xx_softmmu(env);
d63001d1
JM		 3320 env->dcache_line_size = 32;
3321 env->icache_line_size = 32;
4e290a0b
JM		 3322 /* Allocate hardware IRQ controller */
3323 ppc40x_irq_init(env);
3fc6c082 3324}
a750fc0b
JM		 3325
3326/* IOP480 */
082c6681
JM		 3327#define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3328 PPC_DCR | PPC_WRTEE | \
3329 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3330 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
a750fc0b
JM		 3331 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3332 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3333 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3334#define POWERPC_INSNS2_IOP480 (PPC_NONE)
a750fc0b
JM		 3335#define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3336#define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3337#define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3338#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
237c0af0 3339#define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
4018bae9
JM		 3340#define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3341 POWERPC_FLAG_BUS_CLK)
2f462816 3342#define check_pow_IOP480 check_pow_nocheck
a750fc0b
JM		 3343
3344static void init_proc_IOP480 (CPUPPCState *env)
3fc6c082 3345{
a750fc0b
JM		 3346 gen_spr_40x(env);
3347 gen_spr_401_403(env);
3348 gen_spr_401x2(env);
3349 gen_spr_compress(env);
a750fc0b 3350 /* Memory management */
f2e63a42 3351#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3352 env->nb_tlb = 64;
3353 env->nb_ways = 1;
3354 env->id_tlbs = 0;
f2e63a42 3355#endif
e1833e1f 3356 init_excp_4xx_softmmu(env);
d63001d1
JM		 3357 env->dcache_line_size = 32;
3358 env->icache_line_size = 32;
4e290a0b
JM		 3359 /* Allocate hardware IRQ controller */
3360 ppc40x_irq_init(env);
3fc6c082
FB		 3361}
3362
a750fc0b 3363/* PowerPC 403 */
082c6681
JM		 3364#define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3365 PPC_DCR | PPC_WRTEE | \
3366 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3367 PPC_CACHE_DCBZ | \
a750fc0b 3368 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
082c6681 3369 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3370#define POWERPC_INSNS2_403 (PPC_NONE)
a750fc0b 3371#define POWERPC_MSRM_403 (0x000000000007D00DULL)
b4095fed 3372#define POWERPC_MMU_403 (POWERPC_MMU_REAL)
a750fc0b
JM		 3373#define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3374#define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
237c0af0 3375#define POWERPC_BFDM_403 (bfd_mach_ppc_403)
4018bae9
JM		 3376#define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3377 POWERPC_FLAG_BUS_CLK)
2f462816 3378#define check_pow_403 check_pow_nocheck
a750fc0b
JM		 3379
3380static void init_proc_403 (CPUPPCState *env)
3fc6c082 3381{
a750fc0b
JM		 3382 gen_spr_40x(env);
3383 gen_spr_401_403(env);
3384 gen_spr_403(env);
3385 gen_spr_403_real(env);
e1833e1f 3386 init_excp_4xx_real(env);
d63001d1
JM		 3387 env->dcache_line_size = 32;
3388 env->icache_line_size = 32;
4e290a0b
JM		 3389 /* Allocate hardware IRQ controller */
3390 ppc40x_irq_init(env);
3fc6c082
FB		 3391}
3392
a750fc0b 3393/* PowerPC 403 GCX */
082c6681
JM		 3394#define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3395 PPC_DCR | PPC_WRTEE | \
3396 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3397 PPC_CACHE_DCBZ | \
a750fc0b
JM		 3398 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3399 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3400 PPC_4xx_COMMON | PPC_40x_EXCP)
a5858d7a 3401#define POWERPC_INSNS2_403GCX (PPC_NONE)
a750fc0b
JM		 3402#define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3403#define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3404#define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3405#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
237c0af0 3406#define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
4018bae9
JM		 3407#define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3408 POWERPC_FLAG_BUS_CLK)
2f462816 3409#define check_pow_403GCX check_pow_nocheck
a750fc0b
JM		 3410
3411static void init_proc_403GCX (CPUPPCState *env)
3fc6c082 3412{
a750fc0b
JM		 3413 gen_spr_40x(env);
3414 gen_spr_401_403(env);
3415 gen_spr_403(env);
3416 gen_spr_403_real(env);
3417 gen_spr_403_mmu(env);
3418 /* Bus access control */
035feb88 3419 /* not emulated, as Qemu never does speculative access */
a750fc0b
JM		 3420 spr_register(env, SPR_40x_SGR, "SGR",
3421 SPR_NOACCESS, SPR_NOACCESS,
3422 &spr_read_generic, &spr_write_generic,
3423 0xFFFFFFFF);
035feb88 3424 /* not emulated, as Qemu do not emulate caches */
a750fc0b
JM		 3425 spr_register(env, SPR_40x_DCWR, "DCWR",
3426 SPR_NOACCESS, SPR_NOACCESS,
3427 &spr_read_generic, &spr_write_generic,
3428 0x00000000);
3429 /* Memory management */
f2e63a42 3430#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3431 env->nb_tlb = 64;
3432 env->nb_ways = 1;
3433 env->id_tlbs = 0;
f2e63a42 3434#endif
80d11f44
JM		 3435 init_excp_4xx_softmmu(env);
3436 env->dcache_line_size = 32;
3437 env->icache_line_size = 32;
3438 /* Allocate hardware IRQ controller */
3439 ppc40x_irq_init(env);
3440}
3441
3442/* PowerPC 405 */
082c6681
JM		 3443#define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3444 PPC_DCR | PPC_WRTEE | \
3445 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3446 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3447 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
80d11f44 3448 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
082c6681 3449 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
a5858d7a 3450#define POWERPC_INSNS2_405 (PPC_NONE)
80d11f44
JM		 3451#define POWERPC_MSRM_405 (0x000000000006E630ULL)
3452#define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3453#define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3454#define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3455#define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3456#define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3457 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3458#define check_pow_405 check_pow_nocheck
3459
3460static void init_proc_405 (CPUPPCState *env)
3461{
3462 /* Time base */
3463 gen_tbl(env);
3464 gen_spr_40x(env);
3465 gen_spr_405(env);
3466 /* Bus access control */
3467 /* not emulated, as Qemu never does speculative access */
3468 spr_register(env, SPR_40x_SGR, "SGR",
3469 SPR_NOACCESS, SPR_NOACCESS,
3470 &spr_read_generic, &spr_write_generic,
3471 0xFFFFFFFF);
3472 /* not emulated, as Qemu do not emulate caches */
3473 spr_register(env, SPR_40x_DCWR, "DCWR",
3474 SPR_NOACCESS, SPR_NOACCESS,
3475 &spr_read_generic, &spr_write_generic,
3476 0x00000000);
3477 /* Memory management */
3478#if !defined(CONFIG_USER_ONLY)
3479 env->nb_tlb = 64;
3480 env->nb_ways = 1;
3481 env->id_tlbs = 0;
3482#endif
3483 init_excp_4xx_softmmu(env);
3484 env->dcache_line_size = 32;
3485 env->icache_line_size = 32;
3486 /* Allocate hardware IRQ controller */
3487 ppc40x_irq_init(env);
3488}
3489
3490/* PowerPC 440 EP */
082c6681
JM		 3491#define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3492 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3493 PPC_CACHE | PPC_CACHE_ICBI | \
3494 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3495 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3496 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3497 PPC_440_SPEC)
a5858d7a 3498#define POWERPC_INSNS2_440EP (PPC_NONE)
80d11f44
JM		 3499#define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3500#define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3501#define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3502#define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3503#define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3504#define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3505 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3506#define check_pow_440EP check_pow_nocheck
3507
3508__attribute__ (( unused ))
3509static void init_proc_440EP (CPUPPCState *env)
3510{
3511 /* Time base */
3512 gen_tbl(env);
3513 gen_spr_BookE(env, 0x000000000000FFFFULL);
3514 gen_spr_440(env);
3515 gen_spr_usprgh(env);
3516 /* Processor identification */
3517 spr_register(env, SPR_BOOKE_PIR, "PIR",
3518 SPR_NOACCESS, SPR_NOACCESS,
3519 &spr_read_generic, &spr_write_pir,
3520 0x00000000);
3521 /* XXX : not implemented */
3522 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3523 SPR_NOACCESS, SPR_NOACCESS,
3524 &spr_read_generic, &spr_write_generic,
3525 0x00000000);
3526 /* XXX : not implemented */
3527 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3528 SPR_NOACCESS, SPR_NOACCESS,
3529 &spr_read_generic, &spr_write_generic,
3530 0x00000000);
3531 /* XXX : not implemented */
3532 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3533 SPR_NOACCESS, SPR_NOACCESS,
3534 &spr_read_generic, &spr_write_generic,
3535 0x00000000);
3536 /* XXX : not implemented */
3537 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3538 SPR_NOACCESS, SPR_NOACCESS,
3539 &spr_read_generic, &spr_write_generic,
3540 0x00000000);
3541 /* XXX : not implemented */
3542 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3543 SPR_NOACCESS, SPR_NOACCESS,
3544 &spr_read_generic, &spr_write_generic,
3545 0x00000000);
3546 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3547 SPR_NOACCESS, SPR_NOACCESS,
3548 &spr_read_generic, &spr_write_generic,
3549 0x00000000);
3550 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3551 SPR_NOACCESS, SPR_NOACCESS,
3552 &spr_read_generic, &spr_write_generic,
3553 0x00000000);
3554 /* XXX : not implemented */
3555 spr_register(env, SPR_440_CCR1, "CCR1",
3556 SPR_NOACCESS, SPR_NOACCESS,
3557 &spr_read_generic, &spr_write_generic,
3558 0x00000000);
3559 /* Memory management */
3560#if !defined(CONFIG_USER_ONLY)
3561 env->nb_tlb = 64;
3562 env->nb_ways = 1;
3563 env->id_tlbs = 0;
3564#endif
3565 init_excp_BookE(env);
3566 env->dcache_line_size = 32;
3567 env->icache_line_size = 32;
3568 /* XXX: TODO: allocate internal IRQ controller */
3569}
3570
3571/* PowerPC 440 GP */
082c6681
JM		 3572#define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3573 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3574 PPC_CACHE | PPC_CACHE_ICBI | \
3575 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3576 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | \
082c6681
JM		 3577 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3578 PPC_440_SPEC)
a5858d7a 3579#define POWERPC_INSNS2_440GP (PPC_NONE)
80d11f44
JM		 3580#define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3581#define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3582#define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3583#define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3584#define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3585#define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3586 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3587#define check_pow_440GP check_pow_nocheck
3588
3589__attribute__ (( unused ))
3590static void init_proc_440GP (CPUPPCState *env)
3591{
3592 /* Time base */
3593 gen_tbl(env);
3594 gen_spr_BookE(env, 0x000000000000FFFFULL);
3595 gen_spr_440(env);
3596 gen_spr_usprgh(env);
3597 /* Processor identification */
3598 spr_register(env, SPR_BOOKE_PIR, "PIR",
3599 SPR_NOACCESS, SPR_NOACCESS,
3600 &spr_read_generic, &spr_write_pir,
3601 0x00000000);
3602 /* XXX : not implemented */
3603 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3604 SPR_NOACCESS, SPR_NOACCESS,
3605 &spr_read_generic, &spr_write_generic,
3606 0x00000000);
3607 /* XXX : not implemented */
3608 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3609 SPR_NOACCESS, SPR_NOACCESS,
3610 &spr_read_generic, &spr_write_generic,
3611 0x00000000);
3612 /* XXX : not implemented */
3613 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3614 SPR_NOACCESS, SPR_NOACCESS,
3615 &spr_read_generic, &spr_write_generic,
3616 0x00000000);
3617 /* XXX : not implemented */
3618 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3619 SPR_NOACCESS, SPR_NOACCESS,
3620 &spr_read_generic, &spr_write_generic,
3621 0x00000000);
3622 /* Memory management */
3623#if !defined(CONFIG_USER_ONLY)
3624 env->nb_tlb = 64;
3625 env->nb_ways = 1;
3626 env->id_tlbs = 0;
3627#endif
3628 init_excp_BookE(env);
3629 env->dcache_line_size = 32;
3630 env->icache_line_size = 32;
3631 /* XXX: TODO: allocate internal IRQ controller */
3632}
3633
3634/* PowerPC 440x4 */
082c6681
JM		 3635#define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3636 PPC_DCR | PPC_WRTEE | \
3637 PPC_CACHE | PPC_CACHE_ICBI | \
3638 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3639 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44
JM		 3640 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3641 PPC_440_SPEC)
a5858d7a 3642#define POWERPC_INSNS2_440x4 (PPC_NONE)
80d11f44
JM		 3643#define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3644#define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3645#define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3646#define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3647#define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3648#define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3649 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3650#define check_pow_440x4 check_pow_nocheck
3651
3652__attribute__ (( unused ))
3653static void init_proc_440x4 (CPUPPCState *env)
3654{
3655 /* Time base */
3656 gen_tbl(env);
3657 gen_spr_BookE(env, 0x000000000000FFFFULL);
3658 gen_spr_440(env);
3659 gen_spr_usprgh(env);
3660 /* Processor identification */
3661 spr_register(env, SPR_BOOKE_PIR, "PIR",
3662 SPR_NOACCESS, SPR_NOACCESS,
3663 &spr_read_generic, &spr_write_pir,
3664 0x00000000);
3665 /* XXX : not implemented */
3666 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_generic,
3669 0x00000000);
3670 /* XXX : not implemented */
3671 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
3675 /* XXX : not implemented */
3676 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3677 SPR_NOACCESS, SPR_NOACCESS,
3678 &spr_read_generic, &spr_write_generic,
3679 0x00000000);
3680 /* XXX : not implemented */
3681 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3682 SPR_NOACCESS, SPR_NOACCESS,
3683 &spr_read_generic, &spr_write_generic,
3684 0x00000000);
3685 /* Memory management */
3686#if !defined(CONFIG_USER_ONLY)
3687 env->nb_tlb = 64;
3688 env->nb_ways = 1;
3689 env->id_tlbs = 0;
3690#endif
3691 init_excp_BookE(env);
d63001d1
JM		 3692 env->dcache_line_size = 32;
3693 env->icache_line_size = 32;
80d11f44 3694 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3695}
3696
80d11f44 3697/* PowerPC 440x5 */
082c6681
JM		 3698#define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3699 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3700 PPC_CACHE | PPC_CACHE_ICBI | \
3701 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
f4078236 3702 PPC_MEM_TLBSYNC | PPC_MFTB | \
80d11f44 3703 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
082c6681 3704 PPC_440_SPEC)
a5858d7a 3705#define POWERPC_INSNS2_440x5 (PPC_NONE)
80d11f44
JM		 3706#define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3707#define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3708#define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3709#define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3710#define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3711#define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3712 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3713#define check_pow_440x5 check_pow_nocheck
a750fc0b 3714
80d11f44 3715static void init_proc_440x5 (CPUPPCState *env)
3fc6c082 3716{
a750fc0b
JM		 3717 /* Time base */
3718 gen_tbl(env);
80d11f44
JM		 3719 gen_spr_BookE(env, 0x000000000000FFFFULL);
3720 gen_spr_440(env);
3721 gen_spr_usprgh(env);
3722 /* Processor identification */
3723 spr_register(env, SPR_BOOKE_PIR, "PIR",
3724 SPR_NOACCESS, SPR_NOACCESS,
3725 &spr_read_generic, &spr_write_pir,
3726 0x00000000);
3727 /* XXX : not implemented */
3728 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
a750fc0b
JM		 3729 SPR_NOACCESS, SPR_NOACCESS,
3730 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 3731 0x00000000);
3732 /* XXX : not implemented */
3733 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3734 SPR_NOACCESS, SPR_NOACCESS,
3735 &spr_read_generic, &spr_write_generic,
3736 0x00000000);
3737 /* XXX : not implemented */
3738 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3739 SPR_NOACCESS, SPR_NOACCESS,
3740 &spr_read_generic, &spr_write_generic,
3741 0x00000000);
3742 /* XXX : not implemented */
3743 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3744 SPR_NOACCESS, SPR_NOACCESS,
3745 &spr_read_generic, &spr_write_generic,
3746 0x00000000);
3747 /* XXX : not implemented */
3748 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3749 SPR_NOACCESS, SPR_NOACCESS,
3750 &spr_read_generic, &spr_write_generic,
3751 0x00000000);
3752 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3753 SPR_NOACCESS, SPR_NOACCESS,
3754 &spr_read_generic, &spr_write_generic,
3755 0x00000000);
3756 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3757 SPR_NOACCESS, SPR_NOACCESS,
3758 &spr_read_generic, &spr_write_generic,
3759 0x00000000);
3760 /* XXX : not implemented */
3761 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 3762 SPR_NOACCESS, SPR_NOACCESS,
3763 &spr_read_generic, &spr_write_generic,
3764 0x00000000);
3765 /* Memory management */
f2e63a42 3766#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3767 env->nb_tlb = 64;
3768 env->nb_ways = 1;
3769 env->id_tlbs = 0;
f2e63a42 3770#endif
80d11f44 3771 init_excp_BookE(env);
d63001d1
JM		 3772 env->dcache_line_size = 32;
3773 env->icache_line_size = 32;
95070372 3774 ppc40x_irq_init(env);
3fc6c082
FB		 3775}
3776
80d11f44 3777/* PowerPC 460 (guessed) */
082c6681 3778#define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
80d11f44 3779 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
f4078236 3780 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB | \
082c6681
JM		 3781 PPC_CACHE | PPC_CACHE_ICBI | \
3782 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3783 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3784 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3785 PPC_440_SPEC)
a5858d7a 3786#define POWERPC_INSNS2_460 (PPC_NONE)
80d11f44
JM		 3787#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3788#define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3789#define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3790#define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3791#define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3792#define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3793 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3794#define check_pow_460 check_pow_nocheck
a750fc0b 3795
80d11f44
JM		 3796__attribute__ (( unused ))
3797static void init_proc_460 (CPUPPCState *env)
3fc6c082 3798{
a750fc0b
JM		 3799 /* Time base */
3800 gen_tbl(env);
80d11f44 3801 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3802 gen_spr_440(env);
80d11f44
JM		 3803 gen_spr_usprgh(env);
3804 /* Processor identification */
3805 spr_register(env, SPR_BOOKE_PIR, "PIR",
3806 SPR_NOACCESS, SPR_NOACCESS,
3807 &spr_read_generic, &spr_write_pir,
3808 0x00000000);
3809 /* XXX : not implemented */
3810 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3811 SPR_NOACCESS, SPR_NOACCESS,
3812 &spr_read_generic, &spr_write_generic,
3813 0x00000000);
3814 /* XXX : not implemented */
3815 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3816 SPR_NOACCESS, SPR_NOACCESS,
3817 &spr_read_generic, &spr_write_generic,
3818 0x00000000);
3819 /* XXX : not implemented */
3820 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3821 SPR_NOACCESS, SPR_NOACCESS,
3822 &spr_read_generic, &spr_write_generic,
3823 0x00000000);
3824 /* XXX : not implemented */
3825 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3826 SPR_NOACCESS, SPR_NOACCESS,
3827 &spr_read_generic, &spr_write_generic,
3828 0x00000000);
578bb252 3829 /* XXX : not implemented */
a750fc0b
JM		 3830 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3831 SPR_NOACCESS, SPR_NOACCESS,
3832 &spr_read_generic, &spr_write_generic,
3833 0x00000000);
3834 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3835 SPR_NOACCESS, SPR_NOACCESS,
3836 &spr_read_generic, &spr_write_generic,
3837 0x00000000);
3838 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3839 SPR_NOACCESS, SPR_NOACCESS,
3840 &spr_read_generic, &spr_write_generic,
3841 0x00000000);
578bb252 3842 /* XXX : not implemented */
a750fc0b
JM		 3843 spr_register(env, SPR_440_CCR1, "CCR1",
3844 SPR_NOACCESS, SPR_NOACCESS,
3845 &spr_read_generic, &spr_write_generic,
3846 0x00000000);
80d11f44
JM		 3847 /* XXX : not implemented */
3848 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3849 &spr_read_generic, &spr_write_generic,
3850 &spr_read_generic, &spr_write_generic,
3851 0x00000000);
a750fc0b 3852 /* Memory management */
f2e63a42 3853#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3854 env->nb_tlb = 64;
3855 env->nb_ways = 1;
3856 env->id_tlbs = 0;
f2e63a42 3857#endif
e1833e1f 3858 init_excp_BookE(env);
d63001d1
JM		 3859 env->dcache_line_size = 32;
3860 env->icache_line_size = 32;
a750fc0b 3861 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3862}
3863
80d11f44 3864/* PowerPC 460F (guessed) */
082c6681
JM		 3865#define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3866 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3867 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
f4078236 3868 PPC_FLOAT_STFIWX | PPC_MFTB | \
082c6681
JM		 3869 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3870 PPC_WRTEE | PPC_MFAPIDI | \
3871 PPC_CACHE | PPC_CACHE_ICBI | \
3872 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3873 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3874 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3875 PPC_440_SPEC)
a5858d7a 3876#define POWERPC_INSNS2_460F (PPC_NONE)
80d11f44
JM		 3877#define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3878#define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3879#define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3880#define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3881#define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3882#define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
4018bae9 3883 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
80d11f44 3884#define check_pow_460F check_pow_nocheck
a750fc0b 3885
80d11f44
JM		 3886__attribute__ (( unused ))
3887static void init_proc_460F (CPUPPCState *env)
3fc6c082 3888{
a750fc0b
JM		 3889 /* Time base */
3890 gen_tbl(env);
80d11f44 3891 gen_spr_BookE(env, 0x000000000000FFFFULL);
a750fc0b 3892 gen_spr_440(env);
80d11f44
JM		 3893 gen_spr_usprgh(env);
3894 /* Processor identification */
3895 spr_register(env, SPR_BOOKE_PIR, "PIR",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_pir,
3898 0x00000000);
3899 /* XXX : not implemented */
3900 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3901 SPR_NOACCESS, SPR_NOACCESS,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 /* XXX : not implemented */
3905 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3906 SPR_NOACCESS, SPR_NOACCESS,
3907 &spr_read_generic, &spr_write_generic,
3908 0x00000000);
3909 /* XXX : not implemented */
3910 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3911 SPR_NOACCESS, SPR_NOACCESS,
3912 &spr_read_generic, &spr_write_generic,
3913 0x00000000);
3914 /* XXX : not implemented */
3915 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3916 SPR_NOACCESS, SPR_NOACCESS,
3917 &spr_read_generic, &spr_write_generic,
3918 0x00000000);
3919 /* XXX : not implemented */
3920 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3921 SPR_NOACCESS, SPR_NOACCESS,
3922 &spr_read_generic, &spr_write_generic,
3923 0x00000000);
3924 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3925 SPR_NOACCESS, SPR_NOACCESS,
3926 &spr_read_generic, &spr_write_generic,
3927 0x00000000);
3928 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3929 SPR_NOACCESS, SPR_NOACCESS,
3930 &spr_read_generic, &spr_write_generic,
3931 0x00000000);
3932 /* XXX : not implemented */
3933 spr_register(env, SPR_440_CCR1, "CCR1",
3934 SPR_NOACCESS, SPR_NOACCESS,
3935 &spr_read_generic, &spr_write_generic,
3936 0x00000000);
3937 /* XXX : not implemented */
3938 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3939 &spr_read_generic, &spr_write_generic,
3940 &spr_read_generic, &spr_write_generic,
3941 0x00000000);
a750fc0b 3942 /* Memory management */
f2e63a42 3943#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 3944 env->nb_tlb = 64;
3945 env->nb_ways = 1;
3946 env->id_tlbs = 0;
f2e63a42 3947#endif
e1833e1f 3948 init_excp_BookE(env);
d63001d1
JM		 3949 env->dcache_line_size = 32;
3950 env->icache_line_size = 32;
a750fc0b 3951 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082
FB		 3952}
3953
80d11f44
JM		 3954/* Freescale 5xx cores (aka RCPU) */
3955#define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3956 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3957 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3958 PPC_MFTB)
a5858d7a 3959#define POWERPC_INSNS2_MPC5xx (PPC_NONE)
80d11f44
JM		 3960#define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3961#define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3962#define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3963#define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3964#define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
4018bae9
JM		 3965#define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3966 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3967#define check_pow_MPC5xx check_pow_none
3968
3969__attribute__ (( unused ))
3970static void init_proc_MPC5xx (CPUPPCState *env)
3971{
3972 /* Time base */
3973 gen_tbl(env);
3974 gen_spr_5xx_8xx(env);
3975 gen_spr_5xx(env);
3976 init_excp_MPC5xx(env);
3977 env->dcache_line_size = 32;
3978 env->icache_line_size = 32;
3979 /* XXX: TODO: allocate internal IRQ controller */
3980}
3981
3982/* Freescale 8xx cores (aka PowerQUICC) */
3983#define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3984 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3985 PPC_CACHE_ICBI | PPC_MFTB)
a5858d7a 3986#define POWERPC_INSNS2_MPC8xx (PPC_NONE)
80d11f44
JM		 3987#define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3988#define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3989#define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3990#define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3991#define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
4018bae9
JM		 3992#define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3993 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 3994#define check_pow_MPC8xx check_pow_none
3995
3996__attribute__ (( unused ))
3997static void init_proc_MPC8xx (CPUPPCState *env)
3998{
3999 /* Time base */
4000 gen_tbl(env);
4001 gen_spr_5xx_8xx(env);
4002 gen_spr_8xx(env);
4003 init_excp_MPC8xx(env);
4004 env->dcache_line_size = 32;
4005 env->icache_line_size = 32;
4006 /* XXX: TODO: allocate internal IRQ controller */
4007}
4008
4009/* Freescale 82xx cores (aka PowerQUICC-II) */
4010/* PowerPC G2 */
082c6681
JM		 4011#define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4012 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4013 PPC_FLOAT_STFIWX | \
4014 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4015 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4016 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4017 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4018#define POWERPC_INSNS2_G2 (PPC_NONE)
80d11f44
JM		 4019#define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
4020#define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
4021//#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
4022#define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
4023#define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
4024#define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4025 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4026#define check_pow_G2 check_pow_hid0
a750fc0b 4027
80d11f44 4028static void init_proc_G2 (CPUPPCState *env)
3fc6c082 4029{
80d11f44
JM		 4030 gen_spr_ne_601(env);
4031 gen_spr_G2_755(env);
4032 gen_spr_G2(env);
a750fc0b
JM		 4033 /* Time base */
4034 gen_tbl(env);
bd928eba
JM		 4035 /* External access control */
4036 /* XXX : not implemented */
4037 spr_register(env, SPR_EAR, "EAR",
4038 SPR_NOACCESS, SPR_NOACCESS,
4039 &spr_read_generic, &spr_write_generic,
4040 0x00000000);
80d11f44
JM		 4041 /* Hardware implementation register */
4042 /* XXX : not implemented */
4043 spr_register(env, SPR_HID0, "HID0",
4044 SPR_NOACCESS, SPR_NOACCESS,
4045 &spr_read_generic, &spr_write_generic,
4046 0x00000000);
4047 /* XXX : not implemented */
4048 spr_register(env, SPR_HID1, "HID1",
4049 SPR_NOACCESS, SPR_NOACCESS,
4050 &spr_read_generic, &spr_write_generic,
4051 0x00000000);
4052 /* XXX : not implemented */
4053 spr_register(env, SPR_HID2, "HID2",
4054 SPR_NOACCESS, SPR_NOACCESS,
4055 &spr_read_generic, &spr_write_generic,
4056 0x00000000);
a750fc0b 4057 /* Memory management */
80d11f44
JM		 4058 gen_low_BATs(env);
4059 gen_high_BATs(env);
4060 gen_6xx_7xx_soft_tlb(env, 64, 2);
4061 init_excp_G2(env);
d63001d1
JM		 4062 env->dcache_line_size = 32;
4063 env->icache_line_size = 32;
80d11f44
JM		 4064 /* Allocate hardware IRQ controller */
4065 ppc6xx_irq_init(env);
3fc6c082 4066}
a750fc0b 4067
80d11f44 4068/* PowerPC G2LE */
082c6681
JM		 4069#define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4070 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4071 PPC_FLOAT_STFIWX | \
4072 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4073 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4074 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4075 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4076#define POWERPC_INSNS2_G2LE (PPC_NONE)
80d11f44
JM		 4077#define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
4078#define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
4079#define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
4080#define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
4081#define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
4082#define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4083 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4084#define check_pow_G2LE check_pow_hid0
a750fc0b 4085
80d11f44 4086static void init_proc_G2LE (CPUPPCState *env)
3fc6c082 4087{
80d11f44
JM		 4088 gen_spr_ne_601(env);
4089 gen_spr_G2_755(env);
4090 gen_spr_G2(env);
a750fc0b
JM		 4091 /* Time base */
4092 gen_tbl(env);
bd928eba
JM		 4093 /* External access control */
4094 /* XXX : not implemented */
4095 spr_register(env, SPR_EAR, "EAR",
4096 SPR_NOACCESS, SPR_NOACCESS,
4097 &spr_read_generic, &spr_write_generic,
4098 0x00000000);
80d11f44 4099 /* Hardware implementation register */
578bb252 4100 /* XXX : not implemented */
80d11f44 4101 spr_register(env, SPR_HID0, "HID0",
a750fc0b
JM		 4102 SPR_NOACCESS, SPR_NOACCESS,
4103 &spr_read_generic, &spr_write_generic,
4104 0x00000000);
80d11f44
JM		 4105 /* XXX : not implemented */
4106 spr_register(env, SPR_HID1, "HID1",
a750fc0b
JM		 4107 SPR_NOACCESS, SPR_NOACCESS,
4108 &spr_read_generic, &spr_write_generic,
4109 0x00000000);
578bb252 4110 /* XXX : not implemented */
80d11f44 4111 spr_register(env, SPR_HID2, "HID2",
a750fc0b
JM		 4112 SPR_NOACCESS, SPR_NOACCESS,
4113 &spr_read_generic, &spr_write_generic,
4114 0x00000000);
4115 /* Memory management */
80d11f44
JM		 4116 gen_low_BATs(env);
4117 gen_high_BATs(env);
4118 gen_6xx_7xx_soft_tlb(env, 64, 2);
4119 init_excp_G2(env);
d63001d1
JM		 4120 env->dcache_line_size = 32;
4121 env->icache_line_size = 32;
80d11f44
JM		 4122 /* Allocate hardware IRQ controller */
4123 ppc6xx_irq_init(env);
3fc6c082
FB		 4124}
4125
80d11f44
JM		 4126/* e200 core */
4127/* XXX: unimplemented instructions:
4128 * dcblc
4129 * dcbtlst
4130 * dcbtstls
4131 * icblc
4132 * icbtls
4133 * tlbivax
4134 * all SPE multiply-accumulate instructions
4135 */
082c6681 4136#define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
40569b7e 4137 PPC_SPE | PPC_SPE_SINGLE | \
082c6681
JM		 4138 PPC_WRTEE | PPC_RFDI | \
4139 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4140 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
80d11f44 4141 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
082c6681 4142 PPC_BOOKE)
a5858d7a 4143#define POWERPC_INSNS2_e200 (PPC_NONE)
80d11f44 4144#define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
01662f3e 4145#define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE206)
80d11f44
JM		 4146#define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
4147#define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
4148#define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
4149#define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4018bae9
JM		 4150 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4151 POWERPC_FLAG_BUS_CLK)
80d11f44
JM		 4152#define check_pow_e200 check_pow_hid0
4153
578bb252 4154__attribute__ (( unused ))
80d11f44 4155static void init_proc_e200 (CPUPPCState *env)
3fc6c082 4156{
e1833e1f
JM		 4157 /* Time base */
4158 gen_tbl(env);
80d11f44 4159 gen_spr_BookE(env, 0x000000070000FFFFULL);
578bb252 4160 /* XXX : not implemented */
80d11f44 4161 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4162 &spr_read_spefscr, &spr_write_spefscr,
4163 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 4164 0x00000000);
80d11f44 4165 /* Memory management */
01662f3e 4166 gen_spr_BookE206(env, 0x0000005D, NULL);
80d11f44
JM		 4167 /* XXX : not implemented */
4168 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 4169 SPR_NOACCESS, SPR_NOACCESS,
4170 &spr_read_generic, &spr_write_generic,
4171 0x00000000);
80d11f44
JM		 4172 /* XXX : not implemented */
4173 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 4174 SPR_NOACCESS, SPR_NOACCESS,
4175 &spr_read_generic, &spr_write_generic,
4176 0x00000000);
578bb252 4177 /* XXX : not implemented */
80d11f44 4178 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 4179 SPR_NOACCESS, SPR_NOACCESS,
4180 &spr_read_generic, &spr_write_generic,
4181 0x00000000);
578bb252 4182 /* XXX : not implemented */
80d11f44
JM		 4183 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4184 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 4185 &spr_read_generic, &spr_write_generic,
80d11f44
JM		 4186 0x00000000);
4187 /* XXX : not implemented */
4188 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4189 SPR_NOACCESS, SPR_NOACCESS,
4190 &spr_read_generic, &spr_write_generic,
4191 0x00000000);
4192 /* XXX : not implemented */
4193 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4194 SPR_NOACCESS, SPR_NOACCESS,
4195 &spr_read_generic, &spr_write_generic,
4196 0x00000000);
4197 /* XXX : not implemented */
4198 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4199 SPR_NOACCESS, SPR_NOACCESS,
4200 &spr_read_generic, &spr_write_generic,
4201 0x00000000);
4202 /* XXX : not implemented */
4203 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4204 SPR_NOACCESS, SPR_NOACCESS,
4205 &spr_read_generic, &spr_write_generic,
4206 0x00000000);
4207 /* XXX : not implemented */
4208 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4209 SPR_NOACCESS, SPR_NOACCESS,
4210 &spr_read_generic, &spr_write_generic,
4211 0x00000000);
4212 /* XXX : not implemented */
4213 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4214 SPR_NOACCESS, SPR_NOACCESS,
4215 &spr_read_generic, &spr_write_generic,
4216 0x00000000);
4217 /* XXX : not implemented */
4218 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4219 SPR_NOACCESS, SPR_NOACCESS,
4220 &spr_read_generic, &spr_write_generic,
4221 0x00000000);
4222 /* XXX : not implemented */
4223 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4224 SPR_NOACCESS, SPR_NOACCESS,
4225 &spr_read_generic, &spr_write_generic,
4226 0x00000000);
4227 /* XXX : not implemented */
4228 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4229 SPR_NOACCESS, SPR_NOACCESS,
4230 &spr_read_generic, &spr_write_generic,
4231 0x00000000);
4232 /* XXX : not implemented */
4233 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4234 SPR_NOACCESS, SPR_NOACCESS,
4235 &spr_read_generic, &spr_write_generic,
4236 0x00000000);
01662f3e
AG		 4237 /* XXX : not implemented */
4238 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4239 SPR_NOACCESS, SPR_NOACCESS,
4240 &spr_read_generic, &spr_write_generic,
4241 0x00000000); /* TOFIX */
80d11f44
JM		 4242 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4243 SPR_NOACCESS, SPR_NOACCESS,
4244 &spr_read_generic, &spr_write_generic,
4245 0x00000000);
4246 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4247 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 4248 &spr_read_generic, &spr_write_generic,
4249 0x00000000);
f2e63a42 4250#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 4251 env->nb_tlb = 64;
4252 env->nb_ways = 1;
4253 env->id_tlbs = 0;
f2e63a42 4254#endif
80d11f44 4255 init_excp_e200(env);
d63001d1
JM		 4256 env->dcache_line_size = 32;
4257 env->icache_line_size = 32;
e1833e1f 4258 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 4259}
a750fc0b 4260
80d11f44 4261/* e300 core */
082c6681
JM		 4262#define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4263 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4264 PPC_FLOAT_STFIWX | \
4265 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4266 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4267 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4268 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4269#define POWERPC_INSNS2_e300 (PPC_NONE)
80d11f44
JM		 4270#define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4271#define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4272#define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4273#define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4274#define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4275#define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4276 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
80d11f44 4277#define check_pow_e300 check_pow_hid0
a750fc0b 4278
578bb252 4279__attribute__ (( unused ))
80d11f44 4280static void init_proc_e300 (CPUPPCState *env)
3fc6c082 4281{
80d11f44
JM		 4282 gen_spr_ne_601(env);
4283 gen_spr_603(env);
a750fc0b
JM		 4284 /* Time base */
4285 gen_tbl(env);
80d11f44
JM		 4286 /* hardware implementation registers */
4287 /* XXX : not implemented */
4288 spr_register(env, SPR_HID0, "HID0",
4289 SPR_NOACCESS, SPR_NOACCESS,
4290 &spr_read_generic, &spr_write_generic,
4291 0x00000000);
4292 /* XXX : not implemented */
4293 spr_register(env, SPR_HID1, "HID1",
4294 SPR_NOACCESS, SPR_NOACCESS,
4295 &spr_read_generic, &spr_write_generic,
4296 0x00000000);
8daf1781
TM		 4297 /* XXX : not implemented */
4298 spr_register(env, SPR_HID2, "HID2",
4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
80d11f44
JM		 4302 /* Memory management */
4303 gen_low_BATs(env);
8daf1781 4304 gen_high_BATs(env);
80d11f44
JM		 4305 gen_6xx_7xx_soft_tlb(env, 64, 2);
4306 init_excp_603(env);
4307 env->dcache_line_size = 32;
4308 env->icache_line_size = 32;
4309 /* Allocate hardware IRQ controller */
4310 ppc6xx_irq_init(env);
4311}
4312
bd5ea513
AJ		 4313/* e500v1 core */
4314#define POWERPC_INSNS_e500v1 (PPC_INSNS_BASE | PPC_ISEL | \
4315 PPC_SPE | PPC_SPE_SINGLE | \
4316 PPC_WRTEE | PPC_RFDI | \
4317 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4318 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
01662f3e
AG		 4319 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4320#define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206)
bd5ea513 4321#define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL)
01662f3e 4322#define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4323#define POWERPC_EXCP_e500v1 (POWERPC_EXCP_BOOKE)
4324#define POWERPC_INPUT_e500v1 (PPC_FLAGS_INPUT_BookE)
4325#define POWERPC_BFDM_e500v1 (bfd_mach_ppc_860)
4326#define POWERPC_FLAG_e500v1 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4327 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4328 POWERPC_FLAG_BUS_CLK)
4329#define check_pow_e500v1 check_pow_hid0
01662f3e 4330#define init_proc_e500v1 init_proc_e500v1
bd5ea513
AJ		 4331
4332/* e500v2 core */
4333#define POWERPC_INSNS_e500v2 (PPC_INSNS_BASE | PPC_ISEL | \
4334 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | \
4335 PPC_WRTEE | PPC_RFDI | \
4336 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4337 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
01662f3e
AG		 4338 PPC_MEM_TLBSYNC | PPC_TLBIVAX)
4339#define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206)
bd5ea513 4340#define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL)
01662f3e 4341#define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206)
bd5ea513
AJ		 4342#define POWERPC_EXCP_e500v2 (POWERPC_EXCP_BOOKE)
4343#define POWERPC_INPUT_e500v2 (PPC_FLAGS_INPUT_BookE)
4344#define POWERPC_BFDM_e500v2 (bfd_mach_ppc_860)
4345#define POWERPC_FLAG_e500v2 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4346 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4347 POWERPC_FLAG_BUS_CLK)
4348#define check_pow_e500v2 check_pow_hid0
01662f3e 4349#define init_proc_e500v2 init_proc_e500v2
80d11f44 4350
01662f3e 4351static void init_proc_e500 (CPUPPCState *env, int version)
80d11f44 4352{
01662f3e
AG		 4353 uint32_t tlbncfg[2];
4354#if !defined(CONFIG_USER_ONLY)
4355 int i;
4356#endif
4357
80d11f44
JM		 4358 /* Time base */
4359 gen_tbl(env);
01662f3e
AG		 4360 /*
4361 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4362 * complain when accessing them.
4363 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4364 */
4365 gen_spr_BookE(env, 0x0000000F0000FFFFULL);
80d11f44
JM		 4366 /* Processor identification */
4367 spr_register(env, SPR_BOOKE_PIR, "PIR",
4368 SPR_NOACCESS, SPR_NOACCESS,
4369 &spr_read_generic, &spr_write_pir,
4370 0x00000000);
4371 /* XXX : not implemented */
4372 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 4373 &spr_read_spefscr, &spr_write_spefscr,
4374 &spr_read_spefscr, &spr_write_spefscr,
80d11f44
JM		 4375 0x00000000);
4376 /* Memory management */
4377#if !defined(CONFIG_USER_ONLY)
4378 env->nb_pids = 3;
01662f3e
AG		 4379 env->nb_ways = 2;
4380 env->id_tlbs = 0;
4381 switch (version) {
4382 case 1:
4383 /* e500v1 */
4384 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4385 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4386 break;
4387 case 2:
4388 /* e500v2 */
4389 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4390 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4391 break;
4392 default:
4393 cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4394 }
80d11f44 4395#endif
01662f3e 4396 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
80d11f44
JM		 4397 /* XXX : not implemented */
4398 spr_register(env, SPR_HID0, "HID0",
4399 SPR_NOACCESS, SPR_NOACCESS,
4400 &spr_read_generic, &spr_write_generic,
4401 0x00000000);
4402 /* XXX : not implemented */
4403 spr_register(env, SPR_HID1, "HID1",
4404 SPR_NOACCESS, SPR_NOACCESS,
4405 &spr_read_generic, &spr_write_generic,
4406 0x00000000);
4407 /* XXX : not implemented */
4408 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4409 SPR_NOACCESS, SPR_NOACCESS,
4410 &spr_read_generic, &spr_write_generic,
4411 0x00000000);
4412 /* XXX : not implemented */
4413 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4414 SPR_NOACCESS, SPR_NOACCESS,
4415 &spr_read_generic, &spr_write_generic,
4416 0x00000000);
4417 /* XXX : not implemented */
4418 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4419 SPR_NOACCESS, SPR_NOACCESS,
4420 &spr_read_generic, &spr_write_generic,
4421 0x00000000);
578bb252 4422 /* XXX : not implemented */
a750fc0b
JM		 4423 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4424 SPR_NOACCESS, SPR_NOACCESS,
4425 &spr_read_generic, &spr_write_generic,
4426 0x00000000);
80d11f44
JM		 4427 /* XXX : not implemented */
4428 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 4429 SPR_NOACCESS, SPR_NOACCESS,
4430 &spr_read_generic, &spr_write_generic,
4431 0x00000000);
80d11f44
JM		 4432 /* XXX : not implemented */
4433 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 4434 SPR_NOACCESS, SPR_NOACCESS,
4435 &spr_read_generic, &spr_write_generic,
4436 0x00000000);
578bb252 4437 /* XXX : not implemented */
80d11f44 4438 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
a750fc0b
JM		 4439 SPR_NOACCESS, SPR_NOACCESS,
4440 &spr_read_generic, &spr_write_generic,
4441 0x00000000);
578bb252 4442 /* XXX : not implemented */
80d11f44
JM		 4443 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4444 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 4445 &spr_read_generic, &spr_write_e500_l1csr0,
80d11f44
JM		 4446 0x00000000);
4447 /* XXX : not implemented */
4448 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4449 SPR_NOACCESS, SPR_NOACCESS,
4450 &spr_read_generic, &spr_write_generic,
4451 0x00000000);
80d11f44
JM		 4452 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4453 SPR_NOACCESS, SPR_NOACCESS,
4454 &spr_read_generic, &spr_write_generic,
4455 0x00000000);
4456 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4457 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 4458 &spr_read_generic, &spr_write_generic,
4459 0x00000000);
01662f3e
AG		 4460 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4461 SPR_NOACCESS, SPR_NOACCESS,
4462 &spr_read_generic, &spr_write_booke206_mmucsr0,
4463 0x00000000);
4464
f2e63a42 4465#if !defined(CONFIG_USER_ONLY)
01662f3e
AG		 4466 env->nb_tlb = 0;
4467 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4468 env->nb_tlb += booke206_tlb_size(env, i);
4469 }
f2e63a42 4470#endif
01662f3e 4471
80d11f44 4472 init_excp_e200(env);
d63001d1
JM		 4473 env->dcache_line_size = 32;
4474 env->icache_line_size = 32;
9fdc60bf
AJ		 4475 /* Allocate hardware IRQ controller */
4476 ppce500_irq_init(env);
3fc6c082 4477}
a750fc0b 4478
01662f3e
AG		 4479static void init_proc_e500v1(CPUPPCState *env)
4480{
4481 init_proc_e500(env, 1);
4482}
4483
4484static void init_proc_e500v2(CPUPPCState *env)
4485{
4486 init_proc_e500(env, 2);
4487}
4488
a750fc0b 4489/* Non-embedded PowerPC */
a750fc0b
JM		 4490
4491/* POWER : same as 601, without mfmsr, mfsr */
4492#if defined(TODO)
4493#define POWERPC_INSNS_POWER (XXX_TODO)
4494/* POWER RSC (from RAD6000) */
4495#define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4496#endif /* TODO */
4497
4498/* PowerPC 601 */
082c6681
JM		 4499#define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4500 PPC_FLOAT | \
4501 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4502 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4503 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4504#define POWERPC_INSNS2_601 (PPC_NONE)
25ba3a68 4505#define POWERPC_MSRM_601 (0x000000000000FD70ULL)
082c6681 4506#define POWERPC_MSRR_601 (0x0000000000001040ULL)
faadf50e 4507//#define POWERPC_MMU_601 (POWERPC_MMU_601)
a750fc0b
JM		 4508//#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4509#define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
237c0af0 4510#define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4018bae9 4511#define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
2f462816 4512#define check_pow_601 check_pow_none
a750fc0b
JM		 4513
4514static void init_proc_601 (CPUPPCState *env)
3fc6c082 4515{
a750fc0b
JM		 4516 gen_spr_ne_601(env);
4517 gen_spr_601(env);
4518 /* Hardware implementation registers */
4519 /* XXX : not implemented */
4520 spr_register(env, SPR_HID0, "HID0",
4521 SPR_NOACCESS, SPR_NOACCESS,
056401ea 4522 &spr_read_generic, &spr_write_hid0_601,
faadf50e 4523 0x80010080);
a750fc0b
JM		 4524 /* XXX : not implemented */
4525 spr_register(env, SPR_HID1, "HID1",
4526 SPR_NOACCESS, SPR_NOACCESS,
4527 &spr_read_generic, &spr_write_generic,
4528 0x00000000);
4529 /* XXX : not implemented */
4530 spr_register(env, SPR_601_HID2, "HID2",
4531 SPR_NOACCESS, SPR_NOACCESS,
4532 &spr_read_generic, &spr_write_generic,
4533 0x00000000);
4534 /* XXX : not implemented */
4535 spr_register(env, SPR_601_HID5, "HID5",
4536 SPR_NOACCESS, SPR_NOACCESS,
4537 &spr_read_generic, &spr_write_generic,
4538 0x00000000);
a750fc0b 4539 /* Memory management */
e1833e1f 4540 init_excp_601(env);
082c6681
JM		 4541 /* XXX: beware that dcache line size is 64
4542 * but dcbz uses 32 bytes "sectors"
4543 * XXX: this breaks clcs instruction !
4544 */
4545 env->dcache_line_size = 32;
d63001d1 4546 env->icache_line_size = 64;
faadf50e
JM		 4547 /* Allocate hardware IRQ controller */
4548 ppc6xx_irq_init(env);
3fc6c082
FB		 4549}
4550
082c6681
JM		 4551/* PowerPC 601v */
4552#define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4553 PPC_FLOAT | \
4554 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4555 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4556 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4557#define POWERPC_INSNS2_601v (PPC_NONE)
082c6681
JM		 4558#define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4559#define POWERPC_MSRR_601v (0x0000000000001040ULL)
4560#define POWERPC_MMU_601v (POWERPC_MMU_601)
4561#define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4562#define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4563#define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4564#define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4565#define check_pow_601v check_pow_none
4566
4567static void init_proc_601v (CPUPPCState *env)
4568{
4569 init_proc_601(env);
4570 /* XXX : not implemented */
4571 spr_register(env, SPR_601_HID15, "HID15",
4572 SPR_NOACCESS, SPR_NOACCESS,
4573 &spr_read_generic, &spr_write_generic,
4574 0x00000000);
4575}
4576
a750fc0b 4577/* PowerPC 602 */
082c6681
JM		 4578#define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4579 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4580 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4581 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4582 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4583 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
12de9a39 4584 PPC_SEGMENT | PPC_602_SPEC)
a5858d7a 4585#define POWERPC_INSNS2_602 (PPC_NONE)
082c6681
JM		 4586#define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4587/* XXX: 602 MMU is quite specific. Should add a special case */
a750fc0b
JM		 4588#define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4589//#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4590#define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
237c0af0 4591#define POWERPC_BFDM_602 (bfd_mach_ppc_602)
25ba3a68 4592#define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4593 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4594#define check_pow_602 check_pow_hid0
a750fc0b
JM		 4595
4596static void init_proc_602 (CPUPPCState *env)
3fc6c082 4597{
a750fc0b
JM		 4598 gen_spr_ne_601(env);
4599 gen_spr_602(env);
4600 /* Time base */
4601 gen_tbl(env);
4602 /* hardware implementation registers */
4603 /* XXX : not implemented */
4604 spr_register(env, SPR_HID0, "HID0",
4605 SPR_NOACCESS, SPR_NOACCESS,
4606 &spr_read_generic, &spr_write_generic,
4607 0x00000000);
4608 /* XXX : not implemented */
4609 spr_register(env, SPR_HID1, "HID1",
4610 SPR_NOACCESS, SPR_NOACCESS,
4611 &spr_read_generic, &spr_write_generic,
4612 0x00000000);
4613 /* Memory management */
4614 gen_low_BATs(env);
4615 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4616 init_excp_602(env);
d63001d1
JM		 4617 env->dcache_line_size = 32;
4618 env->icache_line_size = 32;
a750fc0b
JM		 4619 /* Allocate hardware IRQ controller */
4620 ppc6xx_irq_init(env);
4621}
3fc6c082 4622
a750fc0b 4623/* PowerPC 603 */
082c6681
JM		 4624#define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4625 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4626 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4627 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4628 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4629 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4630 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4631#define POWERPC_INSNS2_603 (PPC_NONE)
25ba3a68 4632#define POWERPC_MSRM_603 (0x000000000007FF73ULL)
a750fc0b
JM		 4633#define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4634//#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4635#define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
237c0af0 4636#define POWERPC_BFDM_603 (bfd_mach_ppc_603)
25ba3a68 4637#define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4638 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4639#define check_pow_603 check_pow_hid0
a750fc0b
JM		 4640
4641static void init_proc_603 (CPUPPCState *env)
4642{
4643 gen_spr_ne_601(env);
4644 gen_spr_603(env);
4645 /* Time base */
4646 gen_tbl(env);
4647 /* hardware implementation registers */
4648 /* XXX : not implemented */
4649 spr_register(env, SPR_HID0, "HID0",
4650 SPR_NOACCESS, SPR_NOACCESS,
4651 &spr_read_generic, &spr_write_generic,
4652 0x00000000);
4653 /* XXX : not implemented */
4654 spr_register(env, SPR_HID1, "HID1",
4655 SPR_NOACCESS, SPR_NOACCESS,
4656 &spr_read_generic, &spr_write_generic,
4657 0x00000000);
4658 /* Memory management */
4659 gen_low_BATs(env);
4660 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4661 init_excp_603(env);
d63001d1
JM		 4662 env->dcache_line_size = 32;
4663 env->icache_line_size = 32;
a750fc0b
JM		 4664 /* Allocate hardware IRQ controller */
4665 ppc6xx_irq_init(env);
3fc6c082
FB		 4666}
4667
a750fc0b 4668/* PowerPC 603e */
082c6681
JM		 4669#define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4670 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4671 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4672 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4673 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4674 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4675 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4676#define POWERPC_INSNS2_603E (PPC_NONE)
a750fc0b
JM		 4677#define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4678#define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4679//#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4680#define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
237c0af0 4681#define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
25ba3a68 4682#define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4018bae9 4683 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
2f462816 4684#define check_pow_603E check_pow_hid0
a750fc0b
JM		 4685
4686static void init_proc_603E (CPUPPCState *env)
4687{
4688 gen_spr_ne_601(env);
4689 gen_spr_603(env);
4690 /* Time base */
4691 gen_tbl(env);
4692 /* hardware implementation registers */
4693 /* XXX : not implemented */
4694 spr_register(env, SPR_HID0, "HID0",
4695 SPR_NOACCESS, SPR_NOACCESS,
4696 &spr_read_generic, &spr_write_generic,
4697 0x00000000);
4698 /* XXX : not implemented */
4699 spr_register(env, SPR_HID1, "HID1",
4700 SPR_NOACCESS, SPR_NOACCESS,
4701 &spr_read_generic, &spr_write_generic,
4702 0x00000000);
4703 /* XXX : not implemented */
4704 spr_register(env, SPR_IABR, "IABR",
4705 SPR_NOACCESS, SPR_NOACCESS,
4706 &spr_read_generic, &spr_write_generic,
4707 0x00000000);
4708 /* Memory management */
4709 gen_low_BATs(env);
4710 gen_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 4711 init_excp_603(env);
d63001d1
JM		 4712 env->dcache_line_size = 32;
4713 env->icache_line_size = 32;
a750fc0b
JM		 4714 /* Allocate hardware IRQ controller */
4715 ppc6xx_irq_init(env);
4716}
4717
a750fc0b 4718/* PowerPC 604 */
082c6681
JM		 4719#define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4720 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4721 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4722 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4723 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4724 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4725 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4726#define POWERPC_INSNS2_604 (PPC_NONE)
a750fc0b
JM		 4727#define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4728#define POWERPC_MMU_604 (POWERPC_MMU_32B)
4729//#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4730#define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
237c0af0 4731#define POWERPC_BFDM_604 (bfd_mach_ppc_604)
25ba3a68 4732#define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4733 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 4734#define check_pow_604 check_pow_nocheck
a750fc0b
JM		 4735
4736static void init_proc_604 (CPUPPCState *env)
4737{
4738 gen_spr_ne_601(env);
4739 gen_spr_604(env);
4740 /* Time base */
4741 gen_tbl(env);
4742 /* Hardware implementation registers */
4743 /* XXX : not implemented */
082c6681
JM		 4744 spr_register(env, SPR_HID0, "HID0",
4745 SPR_NOACCESS, SPR_NOACCESS,
4746 &spr_read_generic, &spr_write_generic,
4747 0x00000000);
4748 /* Memory management */
4749 gen_low_BATs(env);
4750 init_excp_604(env);
4751 env->dcache_line_size = 32;
4752 env->icache_line_size = 32;
4753 /* Allocate hardware IRQ controller */
4754 ppc6xx_irq_init(env);
4755}
4756
4757/* PowerPC 604E */
4758#define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4759 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4760 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4761 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4762 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4763 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4764 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4765#define POWERPC_INSNS2_604E (PPC_NONE)
082c6681
JM		 4766#define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4767#define POWERPC_MMU_604E (POWERPC_MMU_32B)
4768#define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4769#define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4770#define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4771#define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4772 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4773#define check_pow_604E check_pow_nocheck
4774
4775static void init_proc_604E (CPUPPCState *env)
4776{
4777 gen_spr_ne_601(env);
4778 gen_spr_604(env);
4779 /* XXX : not implemented */
4780 spr_register(env, SPR_MMCR1, "MMCR1",
4781 SPR_NOACCESS, SPR_NOACCESS,
4782 &spr_read_generic, &spr_write_generic,
4783 0x00000000);
4784 /* XXX : not implemented */
4785 spr_register(env, SPR_PMC3, "PMC3",
4786 SPR_NOACCESS, SPR_NOACCESS,
4787 &spr_read_generic, &spr_write_generic,
4788 0x00000000);
4789 /* XXX : not implemented */
4790 spr_register(env, SPR_PMC4, "PMC4",
4791 SPR_NOACCESS, SPR_NOACCESS,
4792 &spr_read_generic, &spr_write_generic,
4793 0x00000000);
4794 /* Time base */
4795 gen_tbl(env);
4796 /* Hardware implementation registers */
4797 /* XXX : not implemented */
a750fc0b
JM		 4798 spr_register(env, SPR_HID0, "HID0",
4799 SPR_NOACCESS, SPR_NOACCESS,
4800 &spr_read_generic, &spr_write_generic,
4801 0x00000000);
4802 /* XXX : not implemented */
4803 spr_register(env, SPR_HID1, "HID1",
4804 SPR_NOACCESS, SPR_NOACCESS,
4805 &spr_read_generic, &spr_write_generic,
4806 0x00000000);
4807 /* Memory management */
4808 gen_low_BATs(env);
e1833e1f 4809 init_excp_604(env);
d63001d1
JM		 4810 env->dcache_line_size = 32;
4811 env->icache_line_size = 32;
a750fc0b
JM		 4812 /* Allocate hardware IRQ controller */
4813 ppc6xx_irq_init(env);
4814}
4815
bd928eba
JM		 4816/* PowerPC 740 */
4817#define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 4818 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 4819 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 4820 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4821 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4822 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4823 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4824#define POWERPC_INSNS2_740 (PPC_NONE)
bd928eba
JM		 4825#define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4826#define POWERPC_MMU_740 (POWERPC_MMU_32B)
4827#define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4828#define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4829#define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4830#define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 4831 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 4832#define check_pow_740 check_pow_hid0
a750fc0b 4833
bd928eba 4834static void init_proc_740 (CPUPPCState *env)
a750fc0b
JM		 4835{
4836 gen_spr_ne_601(env);
4837 gen_spr_7xx(env);
4838 /* Time base */
4839 gen_tbl(env);
4840 /* Thermal management */
4841 gen_spr_thrm(env);
4842 /* Hardware implementation registers */
4843 /* XXX : not implemented */
4844 spr_register(env, SPR_HID0, "HID0",
4845 SPR_NOACCESS, SPR_NOACCESS,
4846 &spr_read_generic, &spr_write_generic,
4847 0x00000000);
4848 /* XXX : not implemented */
4849 spr_register(env, SPR_HID1, "HID1",
4850 SPR_NOACCESS, SPR_NOACCESS,
4851 &spr_read_generic, &spr_write_generic,
4852 0x00000000);
4853 /* Memory management */
4854 gen_low_BATs(env);
e1833e1f 4855 init_excp_7x0(env);
d63001d1
JM		 4856 env->dcache_line_size = 32;
4857 env->icache_line_size = 32;
a750fc0b
JM		 4858 /* Allocate hardware IRQ controller */
4859 ppc6xx_irq_init(env);
4860}
4861
bd928eba
JM		 4862/* PowerPC 750 */
4863#define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4864 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4865 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4866 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4867 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4868 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4869 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4870#define POWERPC_INSNS2_750 (PPC_NONE)
bd928eba
JM		 4871#define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4872#define POWERPC_MMU_750 (POWERPC_MMU_32B)
4873#define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4874#define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4875#define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4876#define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4877 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4878#define check_pow_750 check_pow_hid0
4879
4880static void init_proc_750 (CPUPPCState *env)
4881{
4882 gen_spr_ne_601(env);
4883 gen_spr_7xx(env);
4884 /* XXX : not implemented */
4885 spr_register(env, SPR_L2CR, "L2CR",
4886 SPR_NOACCESS, SPR_NOACCESS,
4887 &spr_read_generic, &spr_write_generic,
4888 0x00000000);
4889 /* Time base */
4890 gen_tbl(env);
4891 /* Thermal management */
4892 gen_spr_thrm(env);
4893 /* Hardware implementation registers */
4894 /* XXX : not implemented */
4895 spr_register(env, SPR_HID0, "HID0",
4896 SPR_NOACCESS, SPR_NOACCESS,
4897 &spr_read_generic, &spr_write_generic,
4898 0x00000000);
4899 /* XXX : not implemented */
4900 spr_register(env, SPR_HID1, "HID1",
4901 SPR_NOACCESS, SPR_NOACCESS,
4902 &spr_read_generic, &spr_write_generic,
4903 0x00000000);
4904 /* Memory management */
4905 gen_low_BATs(env);
4906 /* XXX: high BATs are also present but are known to be bugged on
4907 * die version 1.x
4908 */
4909 init_excp_7x0(env);
4910 env->dcache_line_size = 32;
4911 env->icache_line_size = 32;
4912 /* Allocate hardware IRQ controller */
4913 ppc6xx_irq_init(env);
4914}
4915
4916/* PowerPC 750 CL */
4917/* XXX: not implemented:
4918 * cache lock instructions:
4919 * dcbz_l
4920 * floating point paired instructions
4921 * psq_lux
4922 * psq_lx
4923 * psq_stux
4924 * psq_stx
4925 * ps_abs
4926 * ps_add
4927 * ps_cmpo0
4928 * ps_cmpo1
4929 * ps_cmpu0
4930 * ps_cmpu1
4931 * ps_div
4932 * ps_madd
4933 * ps_madds0
4934 * ps_madds1
4935 * ps_merge00
4936 * ps_merge01
4937 * ps_merge10
4938 * ps_merge11
4939 * ps_mr
4940 * ps_msub
4941 * ps_mul
4942 * ps_muls0
4943 * ps_muls1
4944 * ps_nabs
4945 * ps_neg
4946 * ps_nmadd
4947 * ps_nmsub
4948 * ps_res
4949 * ps_rsqrte
4950 * ps_sel
4951 * ps_sub
4952 * ps_sum0
4953 * ps_sum1
4954 */
4955#define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4956 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4957 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4958 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4959 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4960 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4961 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 4962#define POWERPC_INSNS2_750cl (PPC_NONE)
bd928eba
JM		 4963#define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4964#define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4965#define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4966#define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4967#define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4968#define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4969 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4970#define check_pow_750cl check_pow_hid0
4971
4972static void init_proc_750cl (CPUPPCState *env)
4973{
4974 gen_spr_ne_601(env);
4975 gen_spr_7xx(env);
4976 /* XXX : not implemented */
4977 spr_register(env, SPR_L2CR, "L2CR",
4978 SPR_NOACCESS, SPR_NOACCESS,
4979 &spr_read_generic, &spr_write_generic,
4980 0x00000000);
4981 /* Time base */
4982 gen_tbl(env);
4983 /* Thermal management */
4984 /* Those registers are fake on 750CL */
4985 spr_register(env, SPR_THRM1, "THRM1",
4986 SPR_NOACCESS, SPR_NOACCESS,
4987 &spr_read_generic, &spr_write_generic,
4988 0x00000000);
4989 spr_register(env, SPR_THRM2, "THRM2",
4990 SPR_NOACCESS, SPR_NOACCESS,
4991 &spr_read_generic, &spr_write_generic,
4992 0x00000000);
4993 spr_register(env, SPR_THRM3, "THRM3",
4994 SPR_NOACCESS, SPR_NOACCESS,
4995 &spr_read_generic, &spr_write_generic,
4996 0x00000000);
4997 /* XXX: not implemented */
4998 spr_register(env, SPR_750_TDCL, "TDCL",
4999 SPR_NOACCESS, SPR_NOACCESS,
5000 &spr_read_generic, &spr_write_generic,
5001 0x00000000);
5002 spr_register(env, SPR_750_TDCH, "TDCH",
5003 SPR_NOACCESS, SPR_NOACCESS,
5004 &spr_read_generic, &spr_write_generic,
5005 0x00000000);
5006 /* DMA */
5007 /* XXX : not implemented */
5008 spr_register(env, SPR_750_WPAR, "WPAR",
5009 SPR_NOACCESS, SPR_NOACCESS,
5010 &spr_read_generic, &spr_write_generic,
5011 0x00000000);
5012 spr_register(env, SPR_750_DMAL, "DMAL",
5013 SPR_NOACCESS, SPR_NOACCESS,
5014 &spr_read_generic, &spr_write_generic,
5015 0x00000000);
5016 spr_register(env, SPR_750_DMAU, "DMAU",
5017 SPR_NOACCESS, SPR_NOACCESS,
5018 &spr_read_generic, &spr_write_generic,
5019 0x00000000);
5020 /* Hardware implementation registers */
5021 /* XXX : not implemented */
5022 spr_register(env, SPR_HID0, "HID0",
5023 SPR_NOACCESS, SPR_NOACCESS,
5024 &spr_read_generic, &spr_write_generic,
5025 0x00000000);
5026 /* XXX : not implemented */
5027 spr_register(env, SPR_HID1, "HID1",
5028 SPR_NOACCESS, SPR_NOACCESS,
5029 &spr_read_generic, &spr_write_generic,
5030 0x00000000);
5031 /* XXX : not implemented */
5032 spr_register(env, SPR_750CL_HID2, "HID2",
5033 SPR_NOACCESS, SPR_NOACCESS,
5034 &spr_read_generic, &spr_write_generic,
5035 0x00000000);
5036 /* XXX : not implemented */
5037 spr_register(env, SPR_750CL_HID4, "HID4",
5038 SPR_NOACCESS, SPR_NOACCESS,
5039 &spr_read_generic, &spr_write_generic,
5040 0x00000000);
5041 /* Quantization registers */
5042 /* XXX : not implemented */
5043 spr_register(env, SPR_750_GQR0, "GQR0",
5044 SPR_NOACCESS, SPR_NOACCESS,
5045 &spr_read_generic, &spr_write_generic,
5046 0x00000000);
5047 /* XXX : not implemented */
5048 spr_register(env, SPR_750_GQR1, "GQR1",
5049 SPR_NOACCESS, SPR_NOACCESS,
5050 &spr_read_generic, &spr_write_generic,
5051 0x00000000);
5052 /* XXX : not implemented */
5053 spr_register(env, SPR_750_GQR2, "GQR2",
5054 SPR_NOACCESS, SPR_NOACCESS,
5055 &spr_read_generic, &spr_write_generic,
5056 0x00000000);
5057 /* XXX : not implemented */
5058 spr_register(env, SPR_750_GQR3, "GQR3",
5059 SPR_NOACCESS, SPR_NOACCESS,
5060 &spr_read_generic, &spr_write_generic,
5061 0x00000000);
5062 /* XXX : not implemented */
5063 spr_register(env, SPR_750_GQR4, "GQR4",
5064 SPR_NOACCESS, SPR_NOACCESS,
5065 &spr_read_generic, &spr_write_generic,
5066 0x00000000);
5067 /* XXX : not implemented */
5068 spr_register(env, SPR_750_GQR5, "GQR5",
5069 SPR_NOACCESS, SPR_NOACCESS,
5070 &spr_read_generic, &spr_write_generic,
5071 0x00000000);
5072 /* XXX : not implemented */
5073 spr_register(env, SPR_750_GQR6, "GQR6",
5074 SPR_NOACCESS, SPR_NOACCESS,
5075 &spr_read_generic, &spr_write_generic,
5076 0x00000000);
5077 /* XXX : not implemented */
5078 spr_register(env, SPR_750_GQR7, "GQR7",
5079 SPR_NOACCESS, SPR_NOACCESS,
5080 &spr_read_generic, &spr_write_generic,
5081 0x00000000);
5082 /* Memory management */
5083 gen_low_BATs(env);
5084 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5085 gen_high_BATs(env);
5086 init_excp_750cl(env);
5087 env->dcache_line_size = 32;
5088 env->icache_line_size = 32;
5089 /* Allocate hardware IRQ controller */
5090 ppc6xx_irq_init(env);
5091}
5092
4e777442 5093/* PowerPC 750CX */
bd928eba
JM		 5094#define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5095 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5096 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5097 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5098 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5099 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5100 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5101#define POWERPC_INSNS2_750cx (PPC_NONE)
bd928eba
JM		 5102#define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
5103#define POWERPC_MMU_750cx (POWERPC_MMU_32B)
5104#define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
5105#define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
5106#define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
5107#define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5108 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5109#define check_pow_750cx check_pow_hid0
5110
5111static void init_proc_750cx (CPUPPCState *env)
5112{
5113 gen_spr_ne_601(env);
5114 gen_spr_7xx(env);
5115 /* XXX : not implemented */
5116 spr_register(env, SPR_L2CR, "L2CR",
5117 SPR_NOACCESS, SPR_NOACCESS,
5118 &spr_read_generic, &spr_write_generic,
5119 0x00000000);
5120 /* Time base */
5121 gen_tbl(env);
5122 /* Thermal management */
5123 gen_spr_thrm(env);
5124 /* This register is not implemented but is present for compatibility */
5125 spr_register(env, SPR_SDA, "SDA",
5126 SPR_NOACCESS, SPR_NOACCESS,
5127 &spr_read_generic, &spr_write_generic,
5128 0x00000000);
5129 /* Hardware implementation registers */
5130 /* XXX : not implemented */
5131 spr_register(env, SPR_HID0, "HID0",
5132 SPR_NOACCESS, SPR_NOACCESS,
5133 &spr_read_generic, &spr_write_generic,
5134 0x00000000);
5135 /* XXX : not implemented */
5136 spr_register(env, SPR_HID1, "HID1",
5137 SPR_NOACCESS, SPR_NOACCESS,
5138 &spr_read_generic, &spr_write_generic,
5139 0x00000000);
5140 /* Memory management */
5141 gen_low_BATs(env);
4e777442
JM		 5142 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5143 gen_high_BATs(env);
bd928eba
JM		 5144 init_excp_750cx(env);
5145 env->dcache_line_size = 32;
5146 env->icache_line_size = 32;
5147 /* Allocate hardware IRQ controller */
5148 ppc6xx_irq_init(env);
5149}
5150
5151/* PowerPC 750FX */
082c6681
JM		 5152#define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5153 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba 5154 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5155 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5156 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5157 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5158 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5159#define POWERPC_INSNS2_750fx (PPC_NONE)
25ba3a68 5160#define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
a750fc0b
JM		 5161#define POWERPC_MMU_750fx (POWERPC_MMU_32B)
5162#define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
5163#define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
237c0af0 5164#define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
25ba3a68 5165#define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5166 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 5167#define check_pow_750fx check_pow_hid0
a750fc0b
JM		 5168
5169static void init_proc_750fx (CPUPPCState *env)
5170{
5171 gen_spr_ne_601(env);
5172 gen_spr_7xx(env);
bd928eba
JM		 5173 /* XXX : not implemented */
5174 spr_register(env, SPR_L2CR, "L2CR",
5175 SPR_NOACCESS, SPR_NOACCESS,
5176 &spr_read_generic, &spr_write_generic,
5177 0x00000000);
a750fc0b
JM		 5178 /* Time base */
5179 gen_tbl(env);
5180 /* Thermal management */
5181 gen_spr_thrm(env);
bd928eba
JM		 5182 /* XXX : not implemented */
5183 spr_register(env, SPR_750_THRM4, "THRM4",
5184 SPR_NOACCESS, SPR_NOACCESS,
5185 &spr_read_generic, &spr_write_generic,
5186 0x00000000);
a750fc0b
JM		 5187 /* Hardware implementation registers */
5188 /* XXX : not implemented */
5189 spr_register(env, SPR_HID0, "HID0",
5190 SPR_NOACCESS, SPR_NOACCESS,
5191 &spr_read_generic, &spr_write_generic,
5192 0x00000000);
5193 /* XXX : not implemented */
5194 spr_register(env, SPR_HID1, "HID1",
5195 SPR_NOACCESS, SPR_NOACCESS,
5196 &spr_read_generic, &spr_write_generic,
5197 0x00000000);
5198 /* XXX : not implemented */
bd928eba 5199 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 5200 SPR_NOACCESS, SPR_NOACCESS,
5201 &spr_read_generic, &spr_write_generic,
5202 0x00000000);
5203 /* Memory management */
5204 gen_low_BATs(env);
5205 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5206 gen_high_BATs(env);
bd928eba 5207 init_excp_7x0(env);
d63001d1
JM		 5208 env->dcache_line_size = 32;
5209 env->icache_line_size = 32;
a750fc0b
JM		 5210 /* Allocate hardware IRQ controller */
5211 ppc6xx_irq_init(env);
5212}
5213
bd928eba
JM		 5214/* PowerPC 750GX */
5215#define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
082c6681 5216 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
bd928eba
JM		 5217 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5218 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5219 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5220 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5221 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5222#define POWERPC_INSNS2_750gx (PPC_NONE)
bd928eba
JM		 5223#define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
5224#define POWERPC_MMU_750gx (POWERPC_MMU_32B)
5225#define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
5226#define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
5227#define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
5228#define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5229 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5230#define check_pow_750gx check_pow_hid0
5231
5232static void init_proc_750gx (CPUPPCState *env)
5233{
5234 gen_spr_ne_601(env);
5235 gen_spr_7xx(env);
5236 /* XXX : not implemented (XXX: different from 750fx) */
5237 spr_register(env, SPR_L2CR, "L2CR",
5238 SPR_NOACCESS, SPR_NOACCESS,
5239 &spr_read_generic, &spr_write_generic,
5240 0x00000000);
5241 /* Time base */
5242 gen_tbl(env);
5243 /* Thermal management */
5244 gen_spr_thrm(env);
5245 /* XXX : not implemented */
5246 spr_register(env, SPR_750_THRM4, "THRM4",
5247 SPR_NOACCESS, SPR_NOACCESS,
5248 &spr_read_generic, &spr_write_generic,
5249 0x00000000);
5250 /* Hardware implementation registers */
5251 /* XXX : not implemented (XXX: different from 750fx) */
5252 spr_register(env, SPR_HID0, "HID0",
5253 SPR_NOACCESS, SPR_NOACCESS,
5254 &spr_read_generic, &spr_write_generic,
5255 0x00000000);
5256 /* XXX : not implemented */
5257 spr_register(env, SPR_HID1, "HID1",
5258 SPR_NOACCESS, SPR_NOACCESS,
5259 &spr_read_generic, &spr_write_generic,
5260 0x00000000);
5261 /* XXX : not implemented (XXX: different from 750fx) */
5262 spr_register(env, SPR_750FX_HID2, "HID2",
5263 SPR_NOACCESS, SPR_NOACCESS,
5264 &spr_read_generic, &spr_write_generic,
5265 0x00000000);
5266 /* Memory management */
5267 gen_low_BATs(env);
5268 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5269 gen_high_BATs(env);
5270 init_excp_7x0(env);
5271 env->dcache_line_size = 32;
5272 env->icache_line_size = 32;
5273 /* Allocate hardware IRQ controller */
5274 ppc6xx_irq_init(env);
5275}
5276
5277/* PowerPC 745 */
5278#define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5279 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5280 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5281 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5282 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5283 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5284 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5285#define POWERPC_INSNS2_745 (PPC_NONE)
bd928eba
JM		 5286#define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5287#define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5288#define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5289#define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5290#define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5291#define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5292 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5293#define check_pow_745 check_pow_hid0
5294
5295static void init_proc_745 (CPUPPCState *env)
5296{
5297 gen_spr_ne_601(env);
5298 gen_spr_7xx(env);
5299 gen_spr_G2_755(env);
5300 /* Time base */
5301 gen_tbl(env);
5302 /* Thermal management */
5303 gen_spr_thrm(env);
5304 /* Hardware implementation registers */
5305 /* XXX : not implemented */
5306 spr_register(env, SPR_HID0, "HID0",
5307 SPR_NOACCESS, SPR_NOACCESS,
5308 &spr_read_generic, &spr_write_generic,
5309 0x00000000);
5310 /* XXX : not implemented */
5311 spr_register(env, SPR_HID1, "HID1",
5312 SPR_NOACCESS, SPR_NOACCESS,
5313 &spr_read_generic, &spr_write_generic,
5314 0x00000000);
5315 /* XXX : not implemented */
5316 spr_register(env, SPR_HID2, "HID2",
5317 SPR_NOACCESS, SPR_NOACCESS,
5318 &spr_read_generic, &spr_write_generic,
5319 0x00000000);
5320 /* Memory management */
5321 gen_low_BATs(env);
5322 gen_high_BATs(env);
5323 gen_6xx_7xx_soft_tlb(env, 64, 2);
5324 init_excp_7x5(env);
5325 env->dcache_line_size = 32;
5326 env->icache_line_size = 32;
5327 /* Allocate hardware IRQ controller */
5328 ppc6xx_irq_init(env);
5329}
5330
5331/* PowerPC 755 */
5332#define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5333 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5334 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
082c6681
JM		 5335 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5336 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5337 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5338 PPC_SEGMENT | PPC_EXTERN)
a5858d7a 5339#define POWERPC_INSNS2_755 (PPC_NONE)
bd928eba
JM		 5340#define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5341#define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5342#define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5343#define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5344#define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5345#define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4018bae9 5346 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
bd928eba 5347#define check_pow_755 check_pow_hid0
a750fc0b 5348
bd928eba 5349static void init_proc_755 (CPUPPCState *env)
a750fc0b
JM		 5350{
5351 gen_spr_ne_601(env);
bd928eba 5352 gen_spr_7xx(env);
a750fc0b
JM		 5353 gen_spr_G2_755(env);
5354 /* Time base */
5355 gen_tbl(env);
5356 /* L2 cache control */
5357 /* XXX : not implemented */
bd928eba 5358 spr_register(env, SPR_L2CR, "L2CR",
a750fc0b
JM		 5359 SPR_NOACCESS, SPR_NOACCESS,
5360 &spr_read_generic, &spr_write_generic,
5361 0x00000000);
5362 /* XXX : not implemented */
5363 spr_register(env, SPR_L2PMCR, "L2PMCR",
5364 SPR_NOACCESS, SPR_NOACCESS,
5365 &spr_read_generic, &spr_write_generic,
5366 0x00000000);
bd928eba
JM		 5367 /* Thermal management */
5368 gen_spr_thrm(env);
a750fc0b
JM		 5369 /* Hardware implementation registers */
5370 /* XXX : not implemented */
5371 spr_register(env, SPR_HID0, "HID0",
5372 SPR_NOACCESS, SPR_NOACCESS,
5373 &spr_read_generic, &spr_write_generic,
5374 0x00000000);
5375 /* XXX : not implemented */
5376 spr_register(env, SPR_HID1, "HID1",
5377 SPR_NOACCESS, SPR_NOACCESS,
5378 &spr_read_generic, &spr_write_generic,
5379 0x00000000);
5380 /* XXX : not implemented */
5381 spr_register(env, SPR_HID2, "HID2",
5382 SPR_NOACCESS, SPR_NOACCESS,
5383 &spr_read_generic, &spr_write_generic,
5384 0x00000000);
5385 /* Memory management */
5386 gen_low_BATs(env);
5387 gen_high_BATs(env);
5388 gen_6xx_7xx_soft_tlb(env, 64, 2);
7a3a6927 5389 init_excp_7x5(env);
d63001d1
JM		 5390 env->dcache_line_size = 32;
5391 env->icache_line_size = 32;
a750fc0b
JM		 5392 /* Allocate hardware IRQ controller */
5393 ppc6xx_irq_init(env);
5394}
5395
5396/* PowerPC 7400 (aka G4) */
082c6681
JM		 5397#define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5398 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5399 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5400 PPC_FLOAT_STFIWX | \
5401 PPC_CACHE | PPC_CACHE_ICBI | \
5402 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5403 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5404 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5405 PPC_MEM_TLBIA | \
5406 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5407 PPC_ALTIVEC)
a5858d7a 5408#define POWERPC_INSNS2_7400 (PPC_NONE)
a750fc0b
JM		 5409#define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5410#define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5411#define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5412#define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
237c0af0 5413#define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
25ba3a68 5414#define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5415 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5416 POWERPC_FLAG_BUS_CLK)
488243b0 5417#define check_pow_7400 check_pow_hid0
a750fc0b
JM		 5418
5419static void init_proc_7400 (CPUPPCState *env)
5420{
5421 gen_spr_ne_601(env);
5422 gen_spr_7xx(env);
5423 /* Time base */
5424 gen_tbl(env);
5425 /* 74xx specific SPR */
5426 gen_spr_74xx(env);
4e777442
JM		 5427 /* XXX : not implemented */
5428 spr_register(env, SPR_UBAMR, "UBAMR",
5429 &spr_read_ureg, SPR_NOACCESS,
5430 &spr_read_ureg, SPR_NOACCESS,
5431 0x00000000);
5432 /* XXX: this seems not implemented on all revisions. */
5433 /* XXX : not implemented */
5434 spr_register(env, SPR_MSSCR1, "MSSCR1",
5435 SPR_NOACCESS, SPR_NOACCESS,
5436 &spr_read_generic, &spr_write_generic,
5437 0x00000000);
a750fc0b
JM		 5438 /* Thermal management */
5439 gen_spr_thrm(env);
5440 /* Memory management */
5441 gen_low_BATs(env);
e1833e1f 5442 init_excp_7400(env);
d63001d1
JM		 5443 env->dcache_line_size = 32;
5444 env->icache_line_size = 32;
a750fc0b
JM		 5445 /* Allocate hardware IRQ controller */
5446 ppc6xx_irq_init(env);
5447}
5448
5449/* PowerPC 7410 (aka G4) */
082c6681
JM		 5450#define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5451 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5452 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5453 PPC_FLOAT_STFIWX | \
5454 PPC_CACHE | PPC_CACHE_ICBI | \
5455 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5456 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5457 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5458 PPC_MEM_TLBIA | \
5459 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5460 PPC_ALTIVEC)
a5858d7a 5461#define POWERPC_INSNS2_7410 (PPC_NONE)
a750fc0b
JM		 5462#define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5463#define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5464#define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5465#define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
237c0af0 5466#define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
25ba3a68 5467#define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5468 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5469 POWERPC_FLAG_BUS_CLK)
488243b0 5470#define check_pow_7410 check_pow_hid0
a750fc0b
JM		 5471
5472static void init_proc_7410 (CPUPPCState *env)
5473{
5474 gen_spr_ne_601(env);
5475 gen_spr_7xx(env);
5476 /* Time base */
5477 gen_tbl(env);
5478 /* 74xx specific SPR */
5479 gen_spr_74xx(env);
4e777442
JM		 5480 /* XXX : not implemented */
5481 spr_register(env, SPR_UBAMR, "UBAMR",
5482 &spr_read_ureg, SPR_NOACCESS,
5483 &spr_read_ureg, SPR_NOACCESS,
5484 0x00000000);
a750fc0b
JM		 5485 /* Thermal management */
5486 gen_spr_thrm(env);
5487 /* L2PMCR */
5488 /* XXX : not implemented */
5489 spr_register(env, SPR_L2PMCR, "L2PMCR",
5490 SPR_NOACCESS, SPR_NOACCESS,
5491 &spr_read_generic, &spr_write_generic,
5492 0x00000000);
5493 /* LDSTDB */
5494 /* XXX : not implemented */
5495 spr_register(env, SPR_LDSTDB, "LDSTDB",
5496 SPR_NOACCESS, SPR_NOACCESS,
5497 &spr_read_generic, &spr_write_generic,
5498 0x00000000);
5499 /* Memory management */
5500 gen_low_BATs(env);
e1833e1f 5501 init_excp_7400(env);
d63001d1
JM		 5502 env->dcache_line_size = 32;
5503 env->icache_line_size = 32;
a750fc0b
JM		 5504 /* Allocate hardware IRQ controller */
5505 ppc6xx_irq_init(env);
5506}
5507
5508/* PowerPC 7440 (aka G4) */
082c6681
JM		 5509#define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5510 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5511 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5512 PPC_FLOAT_STFIWX | \
5513 PPC_CACHE | PPC_CACHE_ICBI | \
5514 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5515 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5516 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5517 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5518 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5519 PPC_ALTIVEC)
a5858d7a 5520#define POWERPC_INSNS2_7440 (PPC_NONE)
a750fc0b
JM		 5521#define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5522#define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5523#define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5524#define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
237c0af0 5525#define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
25ba3a68 5526#define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5527 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5528 POWERPC_FLAG_BUS_CLK)
4e777442 5529#define check_pow_7440 check_pow_hid0_74xx
a750fc0b 5530
578bb252 5531__attribute__ (( unused ))
a750fc0b
JM		 5532static void init_proc_7440 (CPUPPCState *env)
5533{
5534 gen_spr_ne_601(env);
5535 gen_spr_7xx(env);
5536 /* Time base */
5537 gen_tbl(env);
5538 /* 74xx specific SPR */
5539 gen_spr_74xx(env);
4e777442
JM		 5540 /* XXX : not implemented */
5541 spr_register(env, SPR_UBAMR, "UBAMR",
5542 &spr_read_ureg, SPR_NOACCESS,
5543 &spr_read_ureg, SPR_NOACCESS,
5544 0x00000000);
a750fc0b
JM		 5545 /* LDSTCR */
5546 /* XXX : not implemented */
5547 spr_register(env, SPR_LDSTCR, "LDSTCR",
5548 SPR_NOACCESS, SPR_NOACCESS,
5549 &spr_read_generic, &spr_write_generic,
5550 0x00000000);
5551 /* ICTRL */
5552 /* XXX : not implemented */
5553 spr_register(env, SPR_ICTRL, "ICTRL",
5554 SPR_NOACCESS, SPR_NOACCESS,
5555 &spr_read_generic, &spr_write_generic,
5556 0x00000000);
5557 /* MSSSR0 */
578bb252 5558 /* XXX : not implemented */
a750fc0b
JM		 5559 spr_register(env, SPR_MSSSR0, "MSSSR0",
5560 SPR_NOACCESS, SPR_NOACCESS,
5561 &spr_read_generic, &spr_write_generic,
5562 0x00000000);
5563 /* PMC */
5564 /* XXX : not implemented */
5565 spr_register(env, SPR_PMC5, "PMC5",
5566 SPR_NOACCESS, SPR_NOACCESS,
5567 &spr_read_generic, &spr_write_generic,
5568 0x00000000);
578bb252 5569 /* XXX : not implemented */
a750fc0b
JM		 5570 spr_register(env, SPR_UPMC5, "UPMC5",
5571 &spr_read_ureg, SPR_NOACCESS,
5572 &spr_read_ureg, SPR_NOACCESS,
5573 0x00000000);
578bb252 5574 /* XXX : not implemented */
a750fc0b
JM		 5575 spr_register(env, SPR_PMC6, "PMC6",
5576 SPR_NOACCESS, SPR_NOACCESS,
5577 &spr_read_generic, &spr_write_generic,
5578 0x00000000);
578bb252 5579 /* XXX : not implemented */
a750fc0b
JM		 5580 spr_register(env, SPR_UPMC6, "UPMC6",
5581 &spr_read_ureg, SPR_NOACCESS,
5582 &spr_read_ureg, SPR_NOACCESS,
5583 0x00000000);
5584 /* Memory management */
5585 gen_low_BATs(env);
578bb252 5586 gen_74xx_soft_tlb(env, 128, 2);
1c27f8fb 5587 init_excp_7450(env);
d63001d1
JM		 5588 env->dcache_line_size = 32;
5589 env->icache_line_size = 32;
a750fc0b
JM		 5590 /* Allocate hardware IRQ controller */
5591 ppc6xx_irq_init(env);
5592}
a750fc0b
JM		 5593
5594/* PowerPC 7450 (aka G4) */
082c6681
JM		 5595#define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5596 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5597 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5598 PPC_FLOAT_STFIWX | \
5599 PPC_CACHE | PPC_CACHE_ICBI | \
5600 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5601 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5602 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5603 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5604 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5605 PPC_ALTIVEC)
a5858d7a 5606#define POWERPC_INSNS2_7450 (PPC_NONE)
a750fc0b
JM		 5607#define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5608#define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5609#define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5610#define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
237c0af0 5611#define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
25ba3a68 5612#define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5613 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5614 POWERPC_FLAG_BUS_CLK)
4e777442 5615#define check_pow_7450 check_pow_hid0_74xx
a750fc0b 5616
578bb252 5617__attribute__ (( unused ))
a750fc0b
JM		 5618static void init_proc_7450 (CPUPPCState *env)
5619{
5620 gen_spr_ne_601(env);
5621 gen_spr_7xx(env);
5622 /* Time base */
5623 gen_tbl(env);
5624 /* 74xx specific SPR */
5625 gen_spr_74xx(env);
5626 /* Level 3 cache control */
5627 gen_l3_ctrl(env);
4e777442
JM		 5628 /* L3ITCR1 */
5629 /* XXX : not implemented */
5630 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5631 SPR_NOACCESS, SPR_NOACCESS,
5632 &spr_read_generic, &spr_write_generic,
5633 0x00000000);
5634 /* L3ITCR2 */
5635 /* XXX : not implemented */
5636 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5637 SPR_NOACCESS, SPR_NOACCESS,
5638 &spr_read_generic, &spr_write_generic,
5639 0x00000000);
5640 /* L3ITCR3 */
5641 /* XXX : not implemented */
5642 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5643 SPR_NOACCESS, SPR_NOACCESS,
5644 &spr_read_generic, &spr_write_generic,
5645 0x00000000);
5646 /* L3OHCR */
5647 /* XXX : not implemented */
5648 spr_register(env, SPR_L3OHCR, "L3OHCR",
5649 SPR_NOACCESS, SPR_NOACCESS,
5650 &spr_read_generic, &spr_write_generic,
5651 0x00000000);
5652 /* XXX : not implemented */
5653 spr_register(env, SPR_UBAMR, "UBAMR",
5654 &spr_read_ureg, SPR_NOACCESS,
5655 &spr_read_ureg, SPR_NOACCESS,
5656 0x00000000);
a750fc0b
JM		 5657 /* LDSTCR */
5658 /* XXX : not implemented */
5659 spr_register(env, SPR_LDSTCR, "LDSTCR",
5660 SPR_NOACCESS, SPR_NOACCESS,
5661 &spr_read_generic, &spr_write_generic,
5662 0x00000000);
5663 /* ICTRL */
5664 /* XXX : not implemented */
5665 spr_register(env, SPR_ICTRL, "ICTRL",
5666 SPR_NOACCESS, SPR_NOACCESS,
5667 &spr_read_generic, &spr_write_generic,
5668 0x00000000);
5669 /* MSSSR0 */
578bb252 5670 /* XXX : not implemented */
a750fc0b
JM		 5671 spr_register(env, SPR_MSSSR0, "MSSSR0",
5672 SPR_NOACCESS, SPR_NOACCESS,
5673 &spr_read_generic, &spr_write_generic,
5674 0x00000000);
5675 /* PMC */
5676 /* XXX : not implemented */
5677 spr_register(env, SPR_PMC5, "PMC5",
5678 SPR_NOACCESS, SPR_NOACCESS,
5679 &spr_read_generic, &spr_write_generic,
5680 0x00000000);
578bb252 5681 /* XXX : not implemented */
a750fc0b
JM		 5682 spr_register(env, SPR_UPMC5, "UPMC5",
5683 &spr_read_ureg, SPR_NOACCESS,
5684 &spr_read_ureg, SPR_NOACCESS,
5685 0x00000000);
578bb252 5686 /* XXX : not implemented */
a750fc0b
JM		 5687 spr_register(env, SPR_PMC6, "PMC6",
5688 SPR_NOACCESS, SPR_NOACCESS,
5689 &spr_read_generic, &spr_write_generic,
5690 0x00000000);
578bb252 5691 /* XXX : not implemented */
a750fc0b
JM		 5692 spr_register(env, SPR_UPMC6, "UPMC6",
5693 &spr_read_ureg, SPR_NOACCESS,
5694 &spr_read_ureg, SPR_NOACCESS,
5695 0x00000000);
5696 /* Memory management */
5697 gen_low_BATs(env);
578bb252 5698 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5699 init_excp_7450(env);
d63001d1
JM		 5700 env->dcache_line_size = 32;
5701 env->icache_line_size = 32;
a750fc0b
JM		 5702 /* Allocate hardware IRQ controller */
5703 ppc6xx_irq_init(env);
5704}
a750fc0b
JM		 5705
5706/* PowerPC 7445 (aka G4) */
082c6681
JM		 5707#define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5708 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5709 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5710 PPC_FLOAT_STFIWX | \
5711 PPC_CACHE | PPC_CACHE_ICBI | \
5712 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5713 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5714 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5715 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5716 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5717 PPC_ALTIVEC)
a5858d7a 5718#define POWERPC_INSNS2_7445 (PPC_NONE)
a750fc0b
JM		 5719#define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5720#define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5721#define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5722#define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
237c0af0 5723#define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
25ba3a68 5724#define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5725 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5726 POWERPC_FLAG_BUS_CLK)
4e777442 5727#define check_pow_7445 check_pow_hid0_74xx
a750fc0b 5728
578bb252 5729__attribute__ (( unused ))
a750fc0b
JM		 5730static void init_proc_7445 (CPUPPCState *env)
5731{
5732 gen_spr_ne_601(env);
5733 gen_spr_7xx(env);
5734 /* Time base */
5735 gen_tbl(env);
5736 /* 74xx specific SPR */
5737 gen_spr_74xx(env);
5738 /* LDSTCR */
5739 /* XXX : not implemented */
5740 spr_register(env, SPR_LDSTCR, "LDSTCR",
5741 SPR_NOACCESS, SPR_NOACCESS,
5742 &spr_read_generic, &spr_write_generic,
5743 0x00000000);
5744 /* ICTRL */
5745 /* XXX : not implemented */
5746 spr_register(env, SPR_ICTRL, "ICTRL",
5747 SPR_NOACCESS, SPR_NOACCESS,
5748 &spr_read_generic, &spr_write_generic,
5749 0x00000000);
5750 /* MSSSR0 */
578bb252 5751 /* XXX : not implemented */
a750fc0b
JM		 5752 spr_register(env, SPR_MSSSR0, "MSSSR0",
5753 SPR_NOACCESS, SPR_NOACCESS,
5754 &spr_read_generic, &spr_write_generic,
5755 0x00000000);
5756 /* PMC */
5757 /* XXX : not implemented */
5758 spr_register(env, SPR_PMC5, "PMC5",
5759 SPR_NOACCESS, SPR_NOACCESS,
5760 &spr_read_generic, &spr_write_generic,
5761 0x00000000);
578bb252 5762 /* XXX : not implemented */
a750fc0b
JM		 5763 spr_register(env, SPR_UPMC5, "UPMC5",
5764 &spr_read_ureg, SPR_NOACCESS,
5765 &spr_read_ureg, SPR_NOACCESS,
5766 0x00000000);
578bb252 5767 /* XXX : not implemented */
a750fc0b
JM		 5768 spr_register(env, SPR_PMC6, "PMC6",
5769 SPR_NOACCESS, SPR_NOACCESS,
5770 &spr_read_generic, &spr_write_generic,
5771 0x00000000);
578bb252 5772 /* XXX : not implemented */
a750fc0b
JM		 5773 spr_register(env, SPR_UPMC6, "UPMC6",
5774 &spr_read_ureg, SPR_NOACCESS,
5775 &spr_read_ureg, SPR_NOACCESS,
5776 0x00000000);
5777 /* SPRGs */
5778 spr_register(env, SPR_SPRG4, "SPRG4",
5779 SPR_NOACCESS, SPR_NOACCESS,
5780 &spr_read_generic, &spr_write_generic,
5781 0x00000000);
5782 spr_register(env, SPR_USPRG4, "USPRG4",
5783 &spr_read_ureg, SPR_NOACCESS,
5784 &spr_read_ureg, SPR_NOACCESS,
5785 0x00000000);
5786 spr_register(env, SPR_SPRG5, "SPRG5",
5787 SPR_NOACCESS, SPR_NOACCESS,
5788 &spr_read_generic, &spr_write_generic,
5789 0x00000000);
5790 spr_register(env, SPR_USPRG5, "USPRG5",
5791 &spr_read_ureg, SPR_NOACCESS,
5792 &spr_read_ureg, SPR_NOACCESS,
5793 0x00000000);
5794 spr_register(env, SPR_SPRG6, "SPRG6",
5795 SPR_NOACCESS, SPR_NOACCESS,
5796 &spr_read_generic, &spr_write_generic,
5797 0x00000000);
5798 spr_register(env, SPR_USPRG6, "USPRG6",
5799 &spr_read_ureg, SPR_NOACCESS,
5800 &spr_read_ureg, SPR_NOACCESS,
5801 0x00000000);
5802 spr_register(env, SPR_SPRG7, "SPRG7",
5803 SPR_NOACCESS, SPR_NOACCESS,
5804 &spr_read_generic, &spr_write_generic,
5805 0x00000000);
5806 spr_register(env, SPR_USPRG7, "USPRG7",
5807 &spr_read_ureg, SPR_NOACCESS,
5808 &spr_read_ureg, SPR_NOACCESS,
5809 0x00000000);
5810 /* Memory management */
5811 gen_low_BATs(env);
5812 gen_high_BATs(env);
578bb252 5813 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5814 init_excp_7450(env);
d63001d1
JM		 5815 env->dcache_line_size = 32;
5816 env->icache_line_size = 32;
a750fc0b
JM		 5817 /* Allocate hardware IRQ controller */
5818 ppc6xx_irq_init(env);
5819}
a750fc0b
JM		 5820
5821/* PowerPC 7455 (aka G4) */
082c6681
JM		 5822#define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5823 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5824 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5825 PPC_FLOAT_STFIWX | \
5826 PPC_CACHE | PPC_CACHE_ICBI | \
5827 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5828 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5829 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5830 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5831 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 5832 PPC_ALTIVEC)
a5858d7a 5833#define POWERPC_INSNS2_7455 (PPC_NONE)
a750fc0b
JM		 5834#define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5835#define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5836#define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5837#define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
237c0af0 5838#define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
25ba3a68 5839#define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 5840 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5841 POWERPC_FLAG_BUS_CLK)
4e777442 5842#define check_pow_7455 check_pow_hid0_74xx
a750fc0b 5843
578bb252 5844__attribute__ (( unused ))
a750fc0b
JM		 5845static void init_proc_7455 (CPUPPCState *env)
5846{
5847 gen_spr_ne_601(env);
5848 gen_spr_7xx(env);
5849 /* Time base */
5850 gen_tbl(env);
5851 /* 74xx specific SPR */
5852 gen_spr_74xx(env);
5853 /* Level 3 cache control */
5854 gen_l3_ctrl(env);
5855 /* LDSTCR */
5856 /* XXX : not implemented */
5857 spr_register(env, SPR_LDSTCR, "LDSTCR",
5858 SPR_NOACCESS, SPR_NOACCESS,
5859 &spr_read_generic, &spr_write_generic,
5860 0x00000000);
5861 /* ICTRL */
5862 /* XXX : not implemented */
5863 spr_register(env, SPR_ICTRL, "ICTRL",
5864 SPR_NOACCESS, SPR_NOACCESS,
5865 &spr_read_generic, &spr_write_generic,
5866 0x00000000);
5867 /* MSSSR0 */
578bb252 5868 /* XXX : not implemented */
a750fc0b
JM		 5869 spr_register(env, SPR_MSSSR0, "MSSSR0",
5870 SPR_NOACCESS, SPR_NOACCESS,
5871 &spr_read_generic, &spr_write_generic,
5872 0x00000000);
5873 /* PMC */
5874 /* XXX : not implemented */
5875 spr_register(env, SPR_PMC5, "PMC5",
5876 SPR_NOACCESS, SPR_NOACCESS,
5877 &spr_read_generic, &spr_write_generic,
5878 0x00000000);
578bb252 5879 /* XXX : not implemented */
a750fc0b
JM		 5880 spr_register(env, SPR_UPMC5, "UPMC5",
5881 &spr_read_ureg, SPR_NOACCESS,
5882 &spr_read_ureg, SPR_NOACCESS,
5883 0x00000000);
578bb252 5884 /* XXX : not implemented */
a750fc0b
JM		 5885 spr_register(env, SPR_PMC6, "PMC6",
5886 SPR_NOACCESS, SPR_NOACCESS,
5887 &spr_read_generic, &spr_write_generic,
5888 0x00000000);
578bb252 5889 /* XXX : not implemented */
a750fc0b
JM		 5890 spr_register(env, SPR_UPMC6, "UPMC6",
5891 &spr_read_ureg, SPR_NOACCESS,
5892 &spr_read_ureg, SPR_NOACCESS,
5893 0x00000000);
5894 /* SPRGs */
5895 spr_register(env, SPR_SPRG4, "SPRG4",
5896 SPR_NOACCESS, SPR_NOACCESS,
5897 &spr_read_generic, &spr_write_generic,
5898 0x00000000);
5899 spr_register(env, SPR_USPRG4, "USPRG4",
5900 &spr_read_ureg, SPR_NOACCESS,
5901 &spr_read_ureg, SPR_NOACCESS,
5902 0x00000000);
5903 spr_register(env, SPR_SPRG5, "SPRG5",
5904 SPR_NOACCESS, SPR_NOACCESS,
5905 &spr_read_generic, &spr_write_generic,
5906 0x00000000);
5907 spr_register(env, SPR_USPRG5, "USPRG5",
5908 &spr_read_ureg, SPR_NOACCESS,
5909 &spr_read_ureg, SPR_NOACCESS,
5910 0x00000000);
5911 spr_register(env, SPR_SPRG6, "SPRG6",
5912 SPR_NOACCESS, SPR_NOACCESS,
5913 &spr_read_generic, &spr_write_generic,
5914 0x00000000);
5915 spr_register(env, SPR_USPRG6, "USPRG6",
5916 &spr_read_ureg, SPR_NOACCESS,
5917 &spr_read_ureg, SPR_NOACCESS,
5918 0x00000000);
5919 spr_register(env, SPR_SPRG7, "SPRG7",
5920 SPR_NOACCESS, SPR_NOACCESS,
5921 &spr_read_generic, &spr_write_generic,
5922 0x00000000);
5923 spr_register(env, SPR_USPRG7, "USPRG7",
5924 &spr_read_ureg, SPR_NOACCESS,
5925 &spr_read_ureg, SPR_NOACCESS,
5926 0x00000000);
5927 /* Memory management */
5928 gen_low_BATs(env);
5929 gen_high_BATs(env);
578bb252 5930 gen_74xx_soft_tlb(env, 128, 2);
e1833e1f 5931 init_excp_7450(env);
d63001d1
JM		 5932 env->dcache_line_size = 32;
5933 env->icache_line_size = 32;
a750fc0b
JM		 5934 /* Allocate hardware IRQ controller */
5935 ppc6xx_irq_init(env);
5936}
a750fc0b 5937
4e777442
JM		 5938/* PowerPC 7457 (aka G4) */
5939#define POWERPC_INSNS_7457 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5940 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5941 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5942 PPC_FLOAT_STFIWX | \
5943 PPC_CACHE | PPC_CACHE_ICBI | \
5944 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5945 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5946 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5947 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5948 PPC_SEGMENT | PPC_EXTERN | \
5949 PPC_ALTIVEC)
a5858d7a 5950#define POWERPC_INSNS2_7457 (PPC_NONE)
4e777442
JM		 5951#define POWERPC_MSRM_7457 (0x000000000205FF77ULL)
5952#define POWERPC_MMU_7457 (POWERPC_MMU_SOFT_74xx)
5953#define POWERPC_EXCP_7457 (POWERPC_EXCP_74xx)
5954#define POWERPC_INPUT_7457 (PPC_FLAGS_INPUT_6xx)
5955#define POWERPC_BFDM_7457 (bfd_mach_ppc_7400)
5956#define POWERPC_FLAG_7457 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5957 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5958 POWERPC_FLAG_BUS_CLK)
5959#define check_pow_7457 check_pow_hid0_74xx
5960
5961__attribute__ (( unused ))
5962static void init_proc_7457 (CPUPPCState *env)
5963{
5964 gen_spr_ne_601(env);
5965 gen_spr_7xx(env);
5966 /* Time base */
5967 gen_tbl(env);
5968 /* 74xx specific SPR */
5969 gen_spr_74xx(env);
5970 /* Level 3 cache control */
5971 gen_l3_ctrl(env);
5972 /* L3ITCR1 */
5973 /* XXX : not implemented */
5974 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
5975 SPR_NOACCESS, SPR_NOACCESS,
5976 &spr_read_generic, &spr_write_generic,
5977 0x00000000);
5978 /* L3ITCR2 */
5979 /* XXX : not implemented */
5980 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
5981 SPR_NOACCESS, SPR_NOACCESS,
5982 &spr_read_generic, &spr_write_generic,
5983 0x00000000);
5984 /* L3ITCR3 */
5985 /* XXX : not implemented */
5986 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
5987 SPR_NOACCESS, SPR_NOACCESS,
5988 &spr_read_generic, &spr_write_generic,
5989 0x00000000);
5990 /* L3OHCR */
5991 /* XXX : not implemented */
5992 spr_register(env, SPR_L3OHCR, "L3OHCR",
5993 SPR_NOACCESS, SPR_NOACCESS,
5994 &spr_read_generic, &spr_write_generic,
5995 0x00000000);
5996 /* LDSTCR */
5997 /* XXX : not implemented */
5998 spr_register(env, SPR_LDSTCR, "LDSTCR",
5999 SPR_NOACCESS, SPR_NOACCESS,
6000 &spr_read_generic, &spr_write_generic,
6001 0x00000000);
6002 /* ICTRL */
6003 /* XXX : not implemented */
6004 spr_register(env, SPR_ICTRL, "ICTRL",
6005 SPR_NOACCESS, SPR_NOACCESS,
6006 &spr_read_generic, &spr_write_generic,
6007 0x00000000);
6008 /* MSSSR0 */
6009 /* XXX : not implemented */
6010 spr_register(env, SPR_MSSSR0, "MSSSR0",
6011 SPR_NOACCESS, SPR_NOACCESS,
6012 &spr_read_generic, &spr_write_generic,
6013 0x00000000);
6014 /* PMC */
6015 /* XXX : not implemented */
6016 spr_register(env, SPR_PMC5, "PMC5",
6017 SPR_NOACCESS, SPR_NOACCESS,
6018 &spr_read_generic, &spr_write_generic,
6019 0x00000000);
6020 /* XXX : not implemented */
6021 spr_register(env, SPR_UPMC5, "UPMC5",
6022 &spr_read_ureg, SPR_NOACCESS,
6023 &spr_read_ureg, SPR_NOACCESS,
6024 0x00000000);
6025 /* XXX : not implemented */
6026 spr_register(env, SPR_PMC6, "PMC6",
6027 SPR_NOACCESS, SPR_NOACCESS,
6028 &spr_read_generic, &spr_write_generic,
6029 0x00000000);
6030 /* XXX : not implemented */
6031 spr_register(env, SPR_UPMC6, "UPMC6",
6032 &spr_read_ureg, SPR_NOACCESS,
6033 &spr_read_ureg, SPR_NOACCESS,
6034 0x00000000);
6035 /* SPRGs */
6036 spr_register(env, SPR_SPRG4, "SPRG4",
6037 SPR_NOACCESS, SPR_NOACCESS,
6038 &spr_read_generic, &spr_write_generic,
6039 0x00000000);
6040 spr_register(env, SPR_USPRG4, "USPRG4",
6041 &spr_read_ureg, SPR_NOACCESS,
6042 &spr_read_ureg, SPR_NOACCESS,
6043 0x00000000);
6044 spr_register(env, SPR_SPRG5, "SPRG5",
6045 SPR_NOACCESS, SPR_NOACCESS,
6046 &spr_read_generic, &spr_write_generic,
6047 0x00000000);
6048 spr_register(env, SPR_USPRG5, "USPRG5",
6049 &spr_read_ureg, SPR_NOACCESS,
6050 &spr_read_ureg, SPR_NOACCESS,
6051 0x00000000);
6052 spr_register(env, SPR_SPRG6, "SPRG6",
6053 SPR_NOACCESS, SPR_NOACCESS,
6054 &spr_read_generic, &spr_write_generic,
6055 0x00000000);
6056 spr_register(env, SPR_USPRG6, "USPRG6",
6057 &spr_read_ureg, SPR_NOACCESS,
6058 &spr_read_ureg, SPR_NOACCESS,
6059 0x00000000);
6060 spr_register(env, SPR_SPRG7, "SPRG7",
6061 SPR_NOACCESS, SPR_NOACCESS,
6062 &spr_read_generic, &spr_write_generic,
6063 0x00000000);
6064 spr_register(env, SPR_USPRG7, "USPRG7",
6065 &spr_read_ureg, SPR_NOACCESS,
6066 &spr_read_ureg, SPR_NOACCESS,
6067 0x00000000);
6068 /* Memory management */
6069 gen_low_BATs(env);
6070 gen_high_BATs(env);
6071 gen_74xx_soft_tlb(env, 128, 2);
6072 init_excp_7450(env);
6073 env->dcache_line_size = 32;
6074 env->icache_line_size = 32;
6075 /* Allocate hardware IRQ controller */
6076 ppc6xx_irq_init(env);
6077}
6078
a750fc0b
JM		 6079#if defined (TARGET_PPC64)
6080/* PowerPC 970 */
082c6681
JM		 6081#define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6082 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6083 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6084 PPC_FLOAT_STFIWX | \
6085 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6086 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6087 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6088 PPC_64B | PPC_ALTIVEC | \
12de9a39 6089 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6090#define POWERPC_INSNS2_970 (PPC_NONE)
a750fc0b 6091#define POWERPC_MSRM_970 (0x900000000204FF36ULL)
12de9a39 6092#define POWERPC_MMU_970 (POWERPC_MMU_64B)
a750fc0b
JM		 6093//#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
6094#define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
237c0af0 6095#define POWERPC_BFDM_970 (bfd_mach_ppc64)
25ba3a68 6096#define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6097 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6098 POWERPC_FLAG_BUS_CLK)
a750fc0b 6099
417bf010
JM		 6100#if defined(CONFIG_USER_ONLY)
6101#define POWERPC970_HID5_INIT 0x00000080
6102#else
6103#define POWERPC970_HID5_INIT 0x00000000
6104#endif
6105
2f462816
JM		 6106static int check_pow_970 (CPUPPCState *env)
6107{
6108 if (env->spr[SPR_HID0] & 0x00600000)
6109 return 1;
6110
6111 return 0;
6112}
6113
a750fc0b
JM		 6114static void init_proc_970 (CPUPPCState *env)
6115{
6116 gen_spr_ne_601(env);
6117 gen_spr_7xx(env);
6118 /* Time base */
6119 gen_tbl(env);
6120 /* Hardware implementation registers */
6121 /* XXX : not implemented */
6122 spr_register(env, SPR_HID0, "HID0",
6123 SPR_NOACCESS, SPR_NOACCESS,
06403421 6124 &spr_read_generic, &spr_write_clear,
d63001d1 6125 0x60000000);
a750fc0b
JM		 6126 /* XXX : not implemented */
6127 spr_register(env, SPR_HID1, "HID1",
6128 SPR_NOACCESS, SPR_NOACCESS,
6129 &spr_read_generic, &spr_write_generic,
6130 0x00000000);
6131 /* XXX : not implemented */
bd928eba 6132 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6133 SPR_NOACCESS, SPR_NOACCESS,
6134 &spr_read_generic, &spr_write_generic,
6135 0x00000000);
e57448f1
JM		 6136 /* XXX : not implemented */
6137 spr_register(env, SPR_970_HID5, "HID5",
6138 SPR_NOACCESS, SPR_NOACCESS,
6139 &spr_read_generic, &spr_write_generic,
417bf010 6140 POWERPC970_HID5_INIT);
bd928eba
JM		 6141 /* XXX : not implemented */
6142 spr_register(env, SPR_L2CR, "L2CR",
6143 SPR_NOACCESS, SPR_NOACCESS,
6144 &spr_read_generic, &spr_write_generic,
6145 0x00000000);
a750fc0b
JM		 6146 /* Memory management */
6147 /* XXX: not correct */
6148 gen_low_BATs(env);
12de9a39
JM		 6149 /* XXX : not implemented */
6150 spr_register(env, SPR_MMUCFG, "MMUCFG",
6151 SPR_NOACCESS, SPR_NOACCESS,
6152 &spr_read_generic, SPR_NOACCESS,
6153 0x00000000); /* TOFIX */
6154 /* XXX : not implemented */
6155 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6156 SPR_NOACCESS, SPR_NOACCESS,
6157 &spr_read_generic, &spr_write_generic,
6158 0x00000000); /* TOFIX */
6159 spr_register(env, SPR_HIOR, "SPR_HIOR",
6160 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6161 &spr_read_hior, &spr_write_hior,
6162 0x00000000);
f2e63a42 6163#if !defined(CONFIG_USER_ONLY)
12de9a39 6164 env->slb_nr = 32;
f2e63a42 6165#endif
e1833e1f 6166 init_excp_970(env);
d63001d1
JM		 6167 env->dcache_line_size = 128;
6168 env->icache_line_size = 128;
a750fc0b
JM		 6169 /* Allocate hardware IRQ controller */
6170 ppc970_irq_init(env);
cf8358c8
AJ		 6171 /* Can't find information on what this should be on reset. This
6172 * value is the one used by 74xx processors. */
6173 vscr_init(env, 0x00010000);
a750fc0b 6174}
a750fc0b
JM		 6175
6176/* PowerPC 970FX (aka G5) */
082c6681
JM		 6177#define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6178 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6179 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6180 PPC_FLOAT_STFIWX | \
6181 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6182 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6183 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6184 PPC_64B | PPC_ALTIVEC | \
12de9a39 6185 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6186#define POWERPC_INSNS2_970FX (PPC_NONE)
a750fc0b 6187#define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
12de9a39 6188#define POWERPC_MMU_970FX (POWERPC_MMU_64B)
a750fc0b
JM		 6189#define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
6190#define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
237c0af0 6191#define POWERPC_BFDM_970FX (bfd_mach_ppc64)
25ba3a68 6192#define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6193 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6194 POWERPC_FLAG_BUS_CLK)
a750fc0b 6195
2f462816
JM		 6196static int check_pow_970FX (CPUPPCState *env)
6197{
6198 if (env->spr[SPR_HID0] & 0x00600000)
6199 return 1;
6200
6201 return 0;
6202}
6203
a750fc0b
JM		 6204static void init_proc_970FX (CPUPPCState *env)
6205{
6206 gen_spr_ne_601(env);
6207 gen_spr_7xx(env);
6208 /* Time base */
6209 gen_tbl(env);
6210 /* Hardware implementation registers */
6211 /* XXX : not implemented */
6212 spr_register(env, SPR_HID0, "HID0",
6213 SPR_NOACCESS, SPR_NOACCESS,
06403421 6214 &spr_read_generic, &spr_write_clear,
d63001d1 6215 0x60000000);
a750fc0b
JM		 6216 /* XXX : not implemented */
6217 spr_register(env, SPR_HID1, "HID1",
6218 SPR_NOACCESS, SPR_NOACCESS,
6219 &spr_read_generic, &spr_write_generic,
6220 0x00000000);
6221 /* XXX : not implemented */
bd928eba 6222 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6223 SPR_NOACCESS, SPR_NOACCESS,
6224 &spr_read_generic, &spr_write_generic,
6225 0x00000000);
d63001d1
JM		 6226 /* XXX : not implemented */
6227 spr_register(env, SPR_970_HID5, "HID5",
6228 SPR_NOACCESS, SPR_NOACCESS,
6229 &spr_read_generic, &spr_write_generic,
417bf010 6230 POWERPC970_HID5_INIT);
bd928eba
JM		 6231 /* XXX : not implemented */
6232 spr_register(env, SPR_L2CR, "L2CR",
6233 SPR_NOACCESS, SPR_NOACCESS,
6234 &spr_read_generic, &spr_write_generic,
6235 0x00000000);
a750fc0b
JM		 6236 /* Memory management */
6237 /* XXX: not correct */
6238 gen_low_BATs(env);
12de9a39
JM		 6239 /* XXX : not implemented */
6240 spr_register(env, SPR_MMUCFG, "MMUCFG",
6241 SPR_NOACCESS, SPR_NOACCESS,
6242 &spr_read_generic, SPR_NOACCESS,
6243 0x00000000); /* TOFIX */
6244 /* XXX : not implemented */
6245 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6246 SPR_NOACCESS, SPR_NOACCESS,
6247 &spr_read_generic, &spr_write_generic,
6248 0x00000000); /* TOFIX */
6249 spr_register(env, SPR_HIOR, "SPR_HIOR",
6250 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6251 &spr_read_hior, &spr_write_hior,
6252 0x00000000);
4e98d8cf
BS		 6253 spr_register(env, SPR_CTRL, "SPR_CTRL",
6254 SPR_NOACCESS, SPR_NOACCESS,
6255 &spr_read_generic, &spr_write_generic,
6256 0x00000000);
6257 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6258 SPR_NOACCESS, SPR_NOACCESS,
6259 &spr_read_generic, &spr_write_generic,
6260 0x00000000);
6261 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6262 &spr_read_generic, &spr_write_generic,
6263 &spr_read_generic, &spr_write_generic,
6264 0x00000000);
f2e63a42 6265#if !defined(CONFIG_USER_ONLY)
8eee0af9 6266 env->slb_nr = 64;
f2e63a42 6267#endif
e1833e1f 6268 init_excp_970(env);
d63001d1
JM		 6269 env->dcache_line_size = 128;
6270 env->icache_line_size = 128;
a750fc0b
JM		 6271 /* Allocate hardware IRQ controller */
6272 ppc970_irq_init(env);
cf8358c8
AJ		 6273 /* Can't find information on what this should be on reset. This
6274 * value is the one used by 74xx processors. */
6275 vscr_init(env, 0x00010000);
a750fc0b 6276}
a750fc0b
JM		 6277
6278/* PowerPC 970 GX */
082c6681
JM		 6279#define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6280 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6281 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6282 PPC_FLOAT_STFIWX | \
6283 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6284 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6285 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
a750fc0b 6286 PPC_64B | PPC_ALTIVEC | \
12de9a39 6287 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6288#define POWERPC_INSNS2_970GX (PPC_NONE)
a750fc0b 6289#define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
12de9a39 6290#define POWERPC_MMU_970GX (POWERPC_MMU_64B)
a750fc0b
JM		 6291#define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
6292#define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
237c0af0 6293#define POWERPC_BFDM_970GX (bfd_mach_ppc64)
25ba3a68 6294#define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6295 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6296 POWERPC_FLAG_BUS_CLK)
a750fc0b 6297
2f462816
JM		 6298static int check_pow_970GX (CPUPPCState *env)
6299{
6300 if (env->spr[SPR_HID0] & 0x00600000)
6301 return 1;
6302
6303 return 0;
6304}
6305
a750fc0b
JM		 6306static void init_proc_970GX (CPUPPCState *env)
6307{
6308 gen_spr_ne_601(env);
6309 gen_spr_7xx(env);
6310 /* Time base */
6311 gen_tbl(env);
6312 /* Hardware implementation registers */
6313 /* XXX : not implemented */
6314 spr_register(env, SPR_HID0, "HID0",
6315 SPR_NOACCESS, SPR_NOACCESS,
06403421 6316 &spr_read_generic, &spr_write_clear,
d63001d1 6317 0x60000000);
a750fc0b
JM		 6318 /* XXX : not implemented */
6319 spr_register(env, SPR_HID1, "HID1",
6320 SPR_NOACCESS, SPR_NOACCESS,
6321 &spr_read_generic, &spr_write_generic,
6322 0x00000000);
6323 /* XXX : not implemented */
bd928eba 6324 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 6325 SPR_NOACCESS, SPR_NOACCESS,
6326 &spr_read_generic, &spr_write_generic,
6327 0x00000000);
d63001d1
JM		 6328 /* XXX : not implemented */
6329 spr_register(env, SPR_970_HID5, "HID5",
6330 SPR_NOACCESS, SPR_NOACCESS,
6331 &spr_read_generic, &spr_write_generic,
417bf010 6332 POWERPC970_HID5_INIT);
bd928eba
JM		 6333 /* XXX : not implemented */
6334 spr_register(env, SPR_L2CR, "L2CR",
6335 SPR_NOACCESS, SPR_NOACCESS,
6336 &spr_read_generic, &spr_write_generic,
6337 0x00000000);
a750fc0b
JM		 6338 /* Memory management */
6339 /* XXX: not correct */
6340 gen_low_BATs(env);
12de9a39
JM		 6341 /* XXX : not implemented */
6342 spr_register(env, SPR_MMUCFG, "MMUCFG",
6343 SPR_NOACCESS, SPR_NOACCESS,
6344 &spr_read_generic, SPR_NOACCESS,
6345 0x00000000); /* TOFIX */
6346 /* XXX : not implemented */
6347 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6348 SPR_NOACCESS, SPR_NOACCESS,
6349 &spr_read_generic, &spr_write_generic,
6350 0x00000000); /* TOFIX */
6351 spr_register(env, SPR_HIOR, "SPR_HIOR",
6352 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6353 &spr_read_hior, &spr_write_hior,
6354 0x00000000);
f2e63a42 6355#if !defined(CONFIG_USER_ONLY)
12de9a39 6356 env->slb_nr = 32;
f2e63a42 6357#endif
e1833e1f 6358 init_excp_970(env);
d63001d1
JM		 6359 env->dcache_line_size = 128;
6360 env->icache_line_size = 128;
a750fc0b
JM		 6361 /* Allocate hardware IRQ controller */
6362 ppc970_irq_init(env);
cf8358c8
AJ		 6363 /* Can't find information on what this should be on reset. This
6364 * value is the one used by 74xx processors. */
6365 vscr_init(env, 0x00010000);
a750fc0b 6366}
a750fc0b 6367
2f462816 6368/* PowerPC 970 MP */
082c6681
JM		 6369#define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6370 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6371 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6372 PPC_FLOAT_STFIWX | \
6373 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6374 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6375 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
2f462816
JM		 6376 PPC_64B | PPC_ALTIVEC | \
6377 PPC_SEGMENT_64B | PPC_SLBI)
a5858d7a 6378#define POWERPC_INSNS2_970MP (PPC_NONE)
2f462816
JM		 6379#define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
6380#define POWERPC_MMU_970MP (POWERPC_MMU_64B)
6381#define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
6382#define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
6383#define POWERPC_BFDM_970MP (bfd_mach_ppc64)
6384#define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
4018bae9
JM		 6385 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6386 POWERPC_FLAG_BUS_CLK)
2f462816
JM		 6387
6388static int check_pow_970MP (CPUPPCState *env)
6389{
6390 if (env->spr[SPR_HID0] & 0x01C00000)
6391 return 1;
6392
6393 return 0;
6394}
6395
6396static void init_proc_970MP (CPUPPCState *env)
6397{
6398 gen_spr_ne_601(env);
6399 gen_spr_7xx(env);
6400 /* Time base */
6401 gen_tbl(env);
6402 /* Hardware implementation registers */
6403 /* XXX : not implemented */
6404 spr_register(env, SPR_HID0, "HID0",
6405 SPR_NOACCESS, SPR_NOACCESS,
6406 &spr_read_generic, &spr_write_clear,
6407 0x60000000);
6408 /* XXX : not implemented */
6409 spr_register(env, SPR_HID1, "HID1",
6410 SPR_NOACCESS, SPR_NOACCESS,
6411 &spr_read_generic, &spr_write_generic,
6412 0x00000000);
6413 /* XXX : not implemented */
bd928eba 6414 spr_register(env, SPR_750FX_HID2, "HID2",
2f462816
JM		 6415 SPR_NOACCESS, SPR_NOACCESS,
6416 &spr_read_generic, &spr_write_generic,
6417 0x00000000);
6418 /* XXX : not implemented */
6419 spr_register(env, SPR_970_HID5, "HID5",
6420 SPR_NOACCESS, SPR_NOACCESS,
6421 &spr_read_generic, &spr_write_generic,
6422 POWERPC970_HID5_INIT);
bd928eba
JM		 6423 /* XXX : not implemented */
6424 spr_register(env, SPR_L2CR, "L2CR",
6425 SPR_NOACCESS, SPR_NOACCESS,
6426 &spr_read_generic, &spr_write_generic,
6427 0x00000000);
2f462816
JM		 6428 /* Memory management */
6429 /* XXX: not correct */
6430 gen_low_BATs(env);
6431 /* XXX : not implemented */
6432 spr_register(env, SPR_MMUCFG, "MMUCFG",
6433 SPR_NOACCESS, SPR_NOACCESS,
6434 &spr_read_generic, SPR_NOACCESS,
6435 0x00000000); /* TOFIX */
6436 /* XXX : not implemented */
6437 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
6438 SPR_NOACCESS, SPR_NOACCESS,
6439 &spr_read_generic, &spr_write_generic,
6440 0x00000000); /* TOFIX */
6441 spr_register(env, SPR_HIOR, "SPR_HIOR",
6442 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 6443 &spr_read_hior, &spr_write_hior,
6444 0x00000000);
2f462816
JM		 6445#if !defined(CONFIG_USER_ONLY)
6446 env->slb_nr = 32;
6447#endif
6448 init_excp_970(env);
6449 env->dcache_line_size = 128;
6450 env->icache_line_size = 128;
6451 /* Allocate hardware IRQ controller */
6452 ppc970_irq_init(env);
cf8358c8
AJ		 6453 /* Can't find information on what this should be on reset. This
6454 * value is the one used by 74xx processors. */
6455 vscr_init(env, 0x00010000);
2f462816
JM		 6456}
6457
9d52e907
DG		 6458#if defined(TARGET_PPC64)
6459/* POWER7 */
6460#define POWERPC_INSNS_POWER7 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6461 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6462 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6463 PPC_FLOAT_STFIWX | \
6464 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
6465 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6466 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6467 PPC_64B | PPC_ALTIVEC | \
6468 PPC_SEGMENT_64B | PPC_SLBI | \
6469 PPC_POPCNTB | PPC_POPCNTWD)
a5858d7a 6470#define POWERPC_INSNS2_POWER7 (PPC_NONE)
9d52e907
DG		 6471#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
6472#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
6473#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
6474#define POWERPC_INPUT_POWER7 (PPC_FLAGS_INPUT_POWER7)
6475#define POWERPC_BFDM_POWER7 (bfd_mach_ppc64)
6476#define POWERPC_FLAG_POWER7 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
6477 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
6478 POWERPC_FLAG_BUS_CLK)
6479#define check_pow_POWER7 check_pow_nocheck
6480
6481static void init_proc_POWER7 (CPUPPCState *env)
6482{
6483 gen_spr_ne_601(env);
6484 gen_spr_7xx(env);
6485 /* Time base */
6486 gen_tbl(env);
6487#if !defined(CONFIG_USER_ONLY)
6488 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6489 spr_register(env, SPR_PURR, "PURR",
6490 &spr_read_purr, SPR_NOACCESS,
6491 &spr_read_purr, SPR_NOACCESS,
6492 0x00000000);
6493 spr_register(env, SPR_SPURR, "SPURR",
6494 &spr_read_purr, SPR_NOACCESS,
6495 &spr_read_purr, SPR_NOACCESS,
6496 0x00000000);
6497#endif /* !CONFIG_USER_ONLY */
6498 /* Memory management */
6499 /* XXX : not implemented */
6500 spr_register(env, SPR_MMUCFG, "MMUCFG",
6501 SPR_NOACCESS, SPR_NOACCESS,
6502 &spr_read_generic, SPR_NOACCESS,
6503 0x00000000); /* TOFIX */
6504 /* XXX : not implemented */
6505 spr_register(env, SPR_CTRL, "SPR_CTRLT",
6506 SPR_NOACCESS, SPR_NOACCESS,
6507 &spr_read_generic, &spr_write_generic,
6508 0x80800000);
6509 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
6510 SPR_NOACCESS, SPR_NOACCESS,
6511 &spr_read_generic, &spr_write_generic,
6512 0x80800000);
6513 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6514 &spr_read_generic, &spr_write_generic,
6515 &spr_read_generic, &spr_write_generic,
6516 0x00000000);
6517#if !defined(CONFIG_USER_ONLY)
6518 env->slb_nr = 32;
6519#endif
6520 init_excp_POWER7(env);
6521 env->dcache_line_size = 128;
6522 env->icache_line_size = 128;
6523 /* Allocate hardware IRQ controller */
6524 ppcPOWER7_irq_init(env);
6525 /* Can't find information on what this should be on reset. This
6526 * value is the one used by 74xx processors. */
6527 vscr_init(env, 0x00010000);
6528}
6529#endif /* TARGET_PPC64 */
6530
a750fc0b 6531/* PowerPC 620 */
082c6681
JM		 6532#define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
6533 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
6534 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
6535 PPC_FLOAT_STFIWX | \
6536 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
6537 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
6538 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
6539 PPC_SEGMENT | PPC_EXTERN | \
a750fc0b 6540 PPC_64B | PPC_SLBI)
a5858d7a 6541#define POWERPC_INSNS2_620 (PPC_NONE)
add78955
JM		 6542#define POWERPC_MSRM_620 (0x800000000005FF77ULL)
6543//#define POWERPC_MMU_620 (POWERPC_MMU_620)
a750fc0b 6544#define POWERPC_EXCP_620 (POWERPC_EXCP_970)
faadf50e 6545#define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
237c0af0 6546#define POWERPC_BFDM_620 (bfd_mach_ppc64)
4018bae9 6547#define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
add78955 6548 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
2f462816 6549#define check_pow_620 check_pow_nocheck /* Check this */
a750fc0b 6550
578bb252 6551__attribute__ (( unused ))
a750fc0b
JM		 6552static void init_proc_620 (CPUPPCState *env)
6553{
6554 gen_spr_ne_601(env);
6555 gen_spr_620(env);
6556 /* Time base */
6557 gen_tbl(env);
6558 /* Hardware implementation registers */
6559 /* XXX : not implemented */
6560 spr_register(env, SPR_HID0, "HID0",
6561 SPR_NOACCESS, SPR_NOACCESS,
6562 &spr_read_generic, &spr_write_generic,
6563 0x00000000);
6564 /* Memory management */
6565 gen_low_BATs(env);
e1833e1f 6566 init_excp_620(env);
d63001d1
JM		 6567 env->dcache_line_size = 64;
6568 env->icache_line_size = 64;
faadf50e
JM		 6569 /* Allocate hardware IRQ controller */
6570 ppc6xx_irq_init(env);
a750fc0b 6571}
a750fc0b
JM		 6572#endif /* defined (TARGET_PPC64) */
6573
6574/* Default 32 bits PowerPC target will be 604 */
6575#define CPU_POWERPC_PPC32 CPU_POWERPC_604
6576#define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
a5858d7a 6577#define POWERPC_INSNS2_PPC32 POWERPC_INSNS2_604
a750fc0b
JM		 6578#define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6579#define POWERPC_MMU_PPC32 POWERPC_MMU_604
6580#define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6581#define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
237c0af0 6582#define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
d26bfc9a 6583#define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
2f462816
JM		 6584#define check_pow_PPC32 check_pow_604
6585#define init_proc_PPC32 init_proc_604
a750fc0b
JM		 6586
6587/* Default 64 bits PowerPC target will be 970 FX */
6588#define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6589#define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
a5858d7a 6590#define POWERPC_INSNS2_PPC64 POWERPC_INSNS2_970FX
a750fc0b
JM		 6591#define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6592#define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6593#define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6594#define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
237c0af0 6595#define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
d26bfc9a 6596#define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
2f462816
JM		 6597#define check_pow_PPC64 check_pow_970FX
6598#define init_proc_PPC64 init_proc_970FX
a750fc0b
JM		 6599
6600/* Default PowerPC target will be PowerPC 32 */
6601#if defined (TARGET_PPC64) && 0 // XXX: TODO
a5858d7a
AG		 6602#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6603#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6604#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC64
6605#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6606#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6607#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6608#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6609#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6610#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6611#define check_pow_DEFAULT check_pow_PPC64
6612#define init_proc_DEFAULT init_proc_PPC64
a750fc0b 6613#else
a5858d7a
AG		 6614#define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6615#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6616#define POWERPC_INSNS2_DEFAULT POWERPC_INSNS_PPC32
6617#define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6618#define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6619#define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6620#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6621#define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6622#define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6623#define check_pow_DEFAULT check_pow_PPC32
6624#define init_proc_DEFAULT init_proc_PPC32
a750fc0b
JM		 6625#endif
6626
6627/*****************************************************************************/
6628/* PVR definitions for most known PowerPC */
6629enum {
6630 /* PowerPC 401 family */
6631 /* Generic PowerPC 401 */
80d11f44 6632#define CPU_POWERPC_401 CPU_POWERPC_401G2
a750fc0b 6633 /* PowerPC 401 cores */
80d11f44
JM		 6634 CPU_POWERPC_401A1 = 0x00210000,
6635 CPU_POWERPC_401B2 = 0x00220000,
a750fc0b 6636#if 0
80d11f44 6637 CPU_POWERPC_401B3 = xxx,
a750fc0b 6638#endif
80d11f44
JM		 6639 CPU_POWERPC_401C2 = 0x00230000,
6640 CPU_POWERPC_401D2 = 0x00240000,
6641 CPU_POWERPC_401E2 = 0x00250000,
6642 CPU_POWERPC_401F2 = 0x00260000,
6643 CPU_POWERPC_401G2 = 0x00270000,
a750fc0b
JM		 6644 /* PowerPC 401 microcontrolers */
6645#if 0
80d11f44 6646 CPU_POWERPC_401GF = xxx,
a750fc0b 6647#endif
80d11f44 6648#define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
a750fc0b 6649 /* IBM Processor for Network Resources */
80d11f44 6650 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
a750fc0b 6651#if 0
80d11f44 6652 CPU_POWERPC_XIPCHIP = xxx,
a750fc0b
JM		 6653#endif
6654 /* PowerPC 403 family */
6655 /* Generic PowerPC 403 */
80d11f44 6656#define CPU_POWERPC_403 CPU_POWERPC_403GC
a750fc0b 6657 /* PowerPC 403 microcontrollers */
80d11f44
JM		 6658 CPU_POWERPC_403GA = 0x00200011,
6659 CPU_POWERPC_403GB = 0x00200100,
6660 CPU_POWERPC_403GC = 0x00200200,
6661 CPU_POWERPC_403GCX = 0x00201400,
a750fc0b 6662#if 0
80d11f44 6663 CPU_POWERPC_403GP = xxx,
a750fc0b
JM		 6664#endif
6665 /* PowerPC 405 family */
6666 /* Generic PowerPC 405 */
80d11f44 6667#define CPU_POWERPC_405 CPU_POWERPC_405D4
a750fc0b
JM		 6668 /* PowerPC 405 cores */
6669#if 0
80d11f44 6670 CPU_POWERPC_405A3 = xxx,
a750fc0b
JM		 6671#endif
6672#if 0
80d11f44 6673 CPU_POWERPC_405A4 = xxx,
a750fc0b
JM		 6674#endif
6675#if 0
80d11f44 6676 CPU_POWERPC_405B3 = xxx,
a750fc0b
JM		 6677#endif
6678#if 0
80d11f44 6679 CPU_POWERPC_405B4 = xxx,
a750fc0b
JM		 6680#endif
6681#if 0
80d11f44 6682 CPU_POWERPC_405C3 = xxx,
a750fc0b
JM		 6683#endif
6684#if 0
80d11f44 6685 CPU_POWERPC_405C4 = xxx,
a750fc0b 6686#endif
80d11f44 6687 CPU_POWERPC_405D2 = 0x20010000,
a750fc0b 6688#if 0
80d11f44 6689 CPU_POWERPC_405D3 = xxx,
a750fc0b 6690#endif
80d11f44 6691 CPU_POWERPC_405D4 = 0x41810000,
a750fc0b 6692#if 0
80d11f44 6693 CPU_POWERPC_405D5 = xxx,
a750fc0b
JM		 6694#endif
6695#if 0
80d11f44 6696 CPU_POWERPC_405E4 = xxx,
a750fc0b
JM		 6697#endif
6698#if 0
80d11f44 6699 CPU_POWERPC_405F4 = xxx,
a750fc0b
JM		 6700#endif
6701#if 0
80d11f44 6702 CPU_POWERPC_405F5 = xxx,
a750fc0b
JM		 6703#endif
6704#if 0
80d11f44 6705 CPU_POWERPC_405F6 = xxx,
a750fc0b
JM		 6706#endif
6707 /* PowerPC 405 microcontrolers */
6708 /* XXX: missing 0x200108a0 */
80d11f44
JM		 6709#define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6710 CPU_POWERPC_405CRa = 0x40110041,
6711 CPU_POWERPC_405CRb = 0x401100C5,
6712 CPU_POWERPC_405CRc = 0x40110145,
6713 CPU_POWERPC_405EP = 0x51210950,
a750fc0b 6714#if 0
80d11f44 6715 CPU_POWERPC_405EXr = xxx,
a750fc0b 6716#endif
80d11f44 6717 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
a750fc0b 6718#if 0
80d11f44
JM		 6719 CPU_POWERPC_405FX = xxx,
6720#endif
6721#define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6722 CPU_POWERPC_405GPa = 0x40110000,
6723 CPU_POWERPC_405GPb = 0x40110040,
6724 CPU_POWERPC_405GPc = 0x40110082,
6725 CPU_POWERPC_405GPd = 0x401100C4,
6726#define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6727 CPU_POWERPC_405GPR = 0x50910951,
a750fc0b 6728#if 0
80d11f44 6729 CPU_POWERPC_405H = xxx,
a750fc0b
JM		 6730#endif
6731#if 0
80d11f44 6732 CPU_POWERPC_405L = xxx,
a750fc0b 6733#endif
80d11f44 6734 CPU_POWERPC_405LP = 0x41F10000,
a750fc0b 6735#if 0
80d11f44 6736 CPU_POWERPC_405PM = xxx,
a750fc0b
JM		 6737#endif
6738#if 0
80d11f44 6739 CPU_POWERPC_405PS = xxx,
a750fc0b
JM		 6740#endif
6741#if 0
80d11f44 6742 CPU_POWERPC_405S = xxx,
a750fc0b
JM		 6743#endif
6744 /* IBM network processors */
80d11f44
JM		 6745 CPU_POWERPC_NPE405H = 0x414100C0,
6746 CPU_POWERPC_NPE405H2 = 0x41410140,
6747 CPU_POWERPC_NPE405L = 0x416100C0,
6748 CPU_POWERPC_NPE4GS3 = 0x40B10000,
a750fc0b 6749#if 0
80d11f44 6750 CPU_POWERPC_NPCxx1 = xxx,
a750fc0b
JM		 6751#endif
6752#if 0
80d11f44 6753 CPU_POWERPC_NPR161 = xxx,
a750fc0b
JM		 6754#endif
6755#if 0
80d11f44 6756 CPU_POWERPC_LC77700 = xxx,
a750fc0b
JM		 6757#endif
6758 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6759#if 0
80d11f44 6760 CPU_POWERPC_STB01000 = xxx,
a750fc0b
JM		 6761#endif
6762#if 0
80d11f44 6763 CPU_POWERPC_STB01010 = xxx,
a750fc0b
JM		 6764#endif
6765#if 0
80d11f44 6766 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
a750fc0b 6767#endif
80d11f44 6768 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
a750fc0b 6769#if 0
80d11f44 6770 CPU_POWERPC_STB043 = xxx,
a750fc0b
JM		 6771#endif
6772#if 0
80d11f44 6773 CPU_POWERPC_STB045 = xxx,
a750fc0b 6774#endif
80d11f44
JM		 6775 CPU_POWERPC_STB04 = 0x41810000,
6776 CPU_POWERPC_STB25 = 0x51510950,
a750fc0b 6777#if 0
80d11f44 6778 CPU_POWERPC_STB130 = xxx,
a750fc0b
JM		 6779#endif
6780 /* Xilinx cores */
80d11f44
JM		 6781 CPU_POWERPC_X2VP4 = 0x20010820,
6782#define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6783 CPU_POWERPC_X2VP20 = 0x20010860,
6784#define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
a750fc0b 6785#if 0
80d11f44 6786 CPU_POWERPC_ZL10310 = xxx,
a750fc0b
JM		 6787#endif
6788#if 0
80d11f44 6789 CPU_POWERPC_ZL10311 = xxx,
a750fc0b
JM		 6790#endif
6791#if 0
80d11f44 6792 CPU_POWERPC_ZL10320 = xxx,
a750fc0b
JM		 6793#endif
6794#if 0
80d11f44 6795 CPU_POWERPC_ZL10321 = xxx,
a750fc0b
JM		 6796#endif
6797 /* PowerPC 440 family */
6798 /* Generic PowerPC 440 */
80d11f44 6799#define CPU_POWERPC_440 CPU_POWERPC_440GXf
a750fc0b
JM		 6800 /* PowerPC 440 cores */
6801#if 0
80d11f44 6802 CPU_POWERPC_440A4 = xxx,
a750fc0b 6803#endif
95070372 6804 CPU_POWERPC_440_XILINX = 0x7ff21910,
a750fc0b 6805#if 0
80d11f44 6806 CPU_POWERPC_440A5 = xxx,
a750fc0b
JM		 6807#endif
6808#if 0
80d11f44 6809 CPU_POWERPC_440B4 = xxx,
a750fc0b
JM		 6810#endif
6811#if 0
80d11f44 6812 CPU_POWERPC_440F5 = xxx,
a750fc0b
JM		 6813#endif
6814#if 0
80d11f44 6815 CPU_POWERPC_440G5 = xxx,
a750fc0b
JM		 6816#endif
6817#if 0
80d11f44 6818 CPU_POWERPC_440H4 = xxx,
a750fc0b
JM		 6819#endif
6820#if 0
80d11f44 6821 CPU_POWERPC_440H6 = xxx,
a750fc0b
JM		 6822#endif
6823 /* PowerPC 440 microcontrolers */
80d11f44
JM		 6824#define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6825 CPU_POWERPC_440EPa = 0x42221850,
6826 CPU_POWERPC_440EPb = 0x422218D3,
6827#define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6828 CPU_POWERPC_440GPb = 0x40120440,
6829 CPU_POWERPC_440GPc = 0x40120481,
6830#define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6831#define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6832 CPU_POWERPC_440GRX = 0x200008D0,
6833#define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6834#define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6835 CPU_POWERPC_440GXa = 0x51B21850,
6836 CPU_POWERPC_440GXb = 0x51B21851,
6837 CPU_POWERPC_440GXc = 0x51B21892,
6838 CPU_POWERPC_440GXf = 0x51B21894,
a750fc0b 6839#if 0
80d11f44 6840 CPU_POWERPC_440S = xxx,
a750fc0b 6841#endif
80d11f44
JM		 6842 CPU_POWERPC_440SP = 0x53221850,
6843 CPU_POWERPC_440SP2 = 0x53221891,
6844 CPU_POWERPC_440SPE = 0x53421890,
a750fc0b
JM		 6845 /* PowerPC 460 family */
6846#if 0
6847 /* Generic PowerPC 464 */
80d11f44 6848#define CPU_POWERPC_464 CPU_POWERPC_464H90
a750fc0b
JM		 6849#endif
6850 /* PowerPC 464 microcontrolers */
6851#if 0
80d11f44 6852 CPU_POWERPC_464H90 = xxx,
a750fc0b
JM		 6853#endif
6854#if 0
80d11f44 6855 CPU_POWERPC_464H90FP = xxx,
a750fc0b
JM		 6856#endif
6857 /* Freescale embedded PowerPC cores */
c3e36823 6858 /* PowerPC MPC 5xx cores (aka RCPU) */
80d11f44
JM		 6859 CPU_POWERPC_MPC5xx = 0x00020020,
6860#define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6861#define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6862#define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6863#define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6864#define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6865#define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6866#define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6867#define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6868#define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6869#define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6870#define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6871#define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6872#define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
c3e36823 6873 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
80d11f44
JM		 6874 CPU_POWERPC_MPC8xx = 0x00500000,
6875#define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6876#define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6877#define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6878#define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6879#define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6880#define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6881#define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6882#define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6883#define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6884#define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6885#define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6886#define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6887#define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6888#define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6889#define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
c3e36823 6890 /* G2 cores (aka PowerQUICC-II) */
80d11f44
JM		 6891 CPU_POWERPC_G2 = 0x00810011,
6892 CPU_POWERPC_G2H4 = 0x80811010,
6893 CPU_POWERPC_G2gp = 0x80821010,
6894 CPU_POWERPC_G2ls = 0x90810010,
6895 CPU_POWERPC_MPC603 = 0x00810100,
6896 CPU_POWERPC_G2_HIP3 = 0x00810101,
6897 CPU_POWERPC_G2_HIP4 = 0x80811014,
c3e36823 6898 /* G2_LE core (aka PowerQUICC-II) */
80d11f44
JM		 6899 CPU_POWERPC_G2LE = 0x80820010,
6900 CPU_POWERPC_G2LEgp = 0x80822010,
6901 CPU_POWERPC_G2LEls = 0xA0822010,
6902 CPU_POWERPC_G2LEgp1 = 0x80822011,
6903 CPU_POWERPC_G2LEgp3 = 0x80822013,
6904 /* MPC52xx microcontrollers */
c3e36823 6905 /* XXX: MPC 5121 ? */
80d11f44
JM		 6906#define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6907#define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6908#define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6909#define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6910#define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6911#define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6912#define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6913#define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6914 /* MPC82xx microcontrollers */
6915#define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6916#define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6917#define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6918#define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6919#define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6920#define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6921#define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6922#define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6923#define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6924#define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6925#define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6926#define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6927#define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6928#define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6929#define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6930#define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6931#define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6932#define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6933#define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6934#define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6935#define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6936#define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6937#define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6938#define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6939#define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6940#define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6941#define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6942#define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6943#define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
a750fc0b 6944 /* e200 family */
80d11f44
JM		 6945 /* e200 cores */
6946#define CPU_POWERPC_e200 CPU_POWERPC_e200z6
a750fc0b 6947#if 0
80d11f44 6948 CPU_POWERPC_e200z0 = xxx,
a750fc0b
JM		 6949#endif
6950#if 0
80d11f44 6951 CPU_POWERPC_e200z1 = xxx,
c3e36823
JM		 6952#endif
6953#if 0 /* ? */
80d11f44
JM		 6954 CPU_POWERPC_e200z3 = 0x81120000,
6955#endif
6956 CPU_POWERPC_e200z5 = 0x81000000,
6957 CPU_POWERPC_e200z6 = 0x81120000,
6958 /* MPC55xx microcontrollers */
6959#define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6960#if 0
6961#define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6962#define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6963#define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6964#define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6965#define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6966#define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6967#define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6968#define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6969#define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6970#define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6971#define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6972#define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6973#define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6974#define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6975#endif
6976#if 0
6977#define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6978#define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6979#endif
6980#define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6981#define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6982#define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6983#define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6984#define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6985#define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
a750fc0b 6986 /* e300 family */
80d11f44
JM		 6987 /* e300 cores */
6988#define CPU_POWERPC_e300 CPU_POWERPC_e300c3
6989 CPU_POWERPC_e300c1 = 0x00830010,
6990 CPU_POWERPC_e300c2 = 0x00840010,
6991 CPU_POWERPC_e300c3 = 0x00850010,
6992 CPU_POWERPC_e300c4 = 0x00860010,
6993 /* MPC83xx microcontrollers */
74d77cae
TM		 6994#define CPU_POWERPC_MPC831x CPU_POWERPC_e300c3
6995#define CPU_POWERPC_MPC832x CPU_POWERPC_e300c2
6996#define CPU_POWERPC_MPC834x CPU_POWERPC_e300c1
6997#define CPU_POWERPC_MPC835x CPU_POWERPC_e300c1
6998#define CPU_POWERPC_MPC836x CPU_POWERPC_e300c1
6999#define CPU_POWERPC_MPC837x CPU_POWERPC_e300c4
a750fc0b 7000 /* e500 family */
80d11f44
JM		 7001 /* e500 cores */
7002#define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
bd5ea513 7003#define CPU_POWERPC_e500v1 CPU_POWERPC_e500v1_v20
80d11f44 7004#define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
bd5ea513
AJ		 7005 CPU_POWERPC_e500v1_v10 = 0x80200010,
7006 CPU_POWERPC_e500v1_v20 = 0x80200020,
80d11f44
JM		 7007 CPU_POWERPC_e500v2_v10 = 0x80210010,
7008 CPU_POWERPC_e500v2_v11 = 0x80210011,
7009 CPU_POWERPC_e500v2_v20 = 0x80210020,
7010 CPU_POWERPC_e500v2_v21 = 0x80210021,
7011 CPU_POWERPC_e500v2_v22 = 0x80210022,
7012 CPU_POWERPC_e500v2_v30 = 0x80210030,
7013 /* MPC85xx microcontrollers */
7014#define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
7015#define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
7016#define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
7017#define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
7018#define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
7019#define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
7020#define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
bd5ea513
AJ		 7021#define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500v1_v10
7022#define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500v1_v20
7023#define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500v1_v20
80d11f44 7024#define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
bd5ea513
AJ		 7025#define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500v1_v20
7026#define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500v1_v20
80d11f44 7027#define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
bd5ea513
AJ		 7028#define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500v1_v20
7029#define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500v1_v20
80d11f44
JM		 7030#define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
7031#define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
7032#define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
7033#define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
7034#define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
7035#define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
7036#define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
7037#define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
7038#define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
7039#define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
7040#define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
7041#define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
7042#define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
7043#define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
7044#define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
7045#define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
7046#define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
7047#define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
7048#define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
7049#define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
7050#define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
7051#define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
7052#define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
7053#define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
7054#define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
7055#define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
7056#define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
7057#define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
7058#define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
7059#define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
7060#define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
7061#define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
7062#define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
7063#define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
7064#define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
7065#define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
7066#define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
7067#define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
7068#define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
7069#define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
7070#define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
7071#define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
7072#define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
7073#define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
7074#define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
7075#define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
7076#define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
7077#define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
7078#define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
7079#define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
7080#define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
7081#define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
7082#define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
7083#define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
a750fc0b 7084 /* e600 family */
80d11f44
JM		 7085 /* e600 cores */
7086 CPU_POWERPC_e600 = 0x80040010,
7087 /* MPC86xx microcontrollers */
7088#define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
7089#define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
7090#define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
a750fc0b 7091 /* PowerPC 6xx cores */
80d11f44
JM		 7092#define CPU_POWERPC_601 CPU_POWERPC_601_v2
7093 CPU_POWERPC_601_v0 = 0x00010001,
7094 CPU_POWERPC_601_v1 = 0x00010001,
bd928eba 7095#define CPU_POWERPC_601v CPU_POWERPC_601_v2
80d11f44
JM		 7096 CPU_POWERPC_601_v2 = 0x00010002,
7097 CPU_POWERPC_602 = 0x00050100,
7098 CPU_POWERPC_603 = 0x00030100,
7099#define CPU_POWERPC_603E CPU_POWERPC_603E_v41
7100 CPU_POWERPC_603E_v11 = 0x00060101,
7101 CPU_POWERPC_603E_v12 = 0x00060102,
7102 CPU_POWERPC_603E_v13 = 0x00060103,
7103 CPU_POWERPC_603E_v14 = 0x00060104,
7104 CPU_POWERPC_603E_v22 = 0x00060202,
7105 CPU_POWERPC_603E_v3 = 0x00060300,
7106 CPU_POWERPC_603E_v4 = 0x00060400,
7107 CPU_POWERPC_603E_v41 = 0x00060401,
7108 CPU_POWERPC_603E7t = 0x00071201,
7109 CPU_POWERPC_603E7v = 0x00070100,
7110 CPU_POWERPC_603E7v1 = 0x00070101,
7111 CPU_POWERPC_603E7v2 = 0x00070201,
7112 CPU_POWERPC_603E7 = 0x00070200,
7113 CPU_POWERPC_603P = 0x00070000,
7114#define CPU_POWERPC_603R CPU_POWERPC_603E7t
c3e36823 7115 /* XXX: missing 0x00040303 (604) */
80d11f44
JM		 7116 CPU_POWERPC_604 = 0x00040103,
7117#define CPU_POWERPC_604E CPU_POWERPC_604E_v24
c3e36823
JM		 7118 /* XXX: missing 0x00091203 */
7119 /* XXX: missing 0x00092110 */
7120 /* XXX: missing 0x00092120 */
80d11f44
JM		 7121 CPU_POWERPC_604E_v10 = 0x00090100,
7122 CPU_POWERPC_604E_v22 = 0x00090202,
7123 CPU_POWERPC_604E_v24 = 0x00090204,
c3e36823
JM		 7124 /* XXX: missing 0x000a0100 */
7125 /* XXX: missing 0x00093102 */
80d11f44 7126 CPU_POWERPC_604R = 0x000a0101,
a750fc0b 7127#if 0
80d11f44 7128 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
a750fc0b
JM		 7129#endif
7130 /* PowerPC 740/750 cores (aka G3) */
7131 /* XXX: missing 0x00084202 */
80d11f44 7132#define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
bd928eba 7133 CPU_POWERPC_7x0_v10 = 0x00080100,
80d11f44
JM		 7134 CPU_POWERPC_7x0_v20 = 0x00080200,
7135 CPU_POWERPC_7x0_v21 = 0x00080201,
7136 CPU_POWERPC_7x0_v22 = 0x00080202,
7137 CPU_POWERPC_7x0_v30 = 0x00080300,
7138 CPU_POWERPC_7x0_v31 = 0x00080301,
7139 CPU_POWERPC_740E = 0x00080100,
bd928eba 7140 CPU_POWERPC_750E = 0x00080200,
80d11f44 7141 CPU_POWERPC_7x0P = 0x10080000,
a750fc0b 7142 /* XXX: missing 0x00087010 (CL ?) */
bd928eba
JM		 7143#define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
7144 CPU_POWERPC_750CL_v10 = 0x00087200,
7145 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
80d11f44 7146#define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
bd928eba
JM		 7147 CPU_POWERPC_750CX_v10 = 0x00082100,
7148 CPU_POWERPC_750CX_v20 = 0x00082200,
80d11f44
JM		 7149 CPU_POWERPC_750CX_v21 = 0x00082201,
7150 CPU_POWERPC_750CX_v22 = 0x00082202,
7151#define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
7152 CPU_POWERPC_750CXE_v21 = 0x00082211,
7153 CPU_POWERPC_750CXE_v22 = 0x00082212,
7154 CPU_POWERPC_750CXE_v23 = 0x00082213,
7155 CPU_POWERPC_750CXE_v24 = 0x00082214,
7156 CPU_POWERPC_750CXE_v24b = 0x00083214,
bd928eba
JM		 7157 CPU_POWERPC_750CXE_v30 = 0x00082310,
7158 CPU_POWERPC_750CXE_v31 = 0x00082311,
80d11f44
JM		 7159 CPU_POWERPC_750CXE_v31b = 0x00083311,
7160 CPU_POWERPC_750CXR = 0x00083410,
bd928eba 7161 CPU_POWERPC_750FL = 0x70000203,
80d11f44
JM		 7162#define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
7163 CPU_POWERPC_750FX_v10 = 0x70000100,
7164 CPU_POWERPC_750FX_v20 = 0x70000200,
7165 CPU_POWERPC_750FX_v21 = 0x70000201,
7166 CPU_POWERPC_750FX_v22 = 0x70000202,
7167 CPU_POWERPC_750FX_v23 = 0x70000203,
7168 CPU_POWERPC_750GL = 0x70020102,
7169#define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
7170 CPU_POWERPC_750GX_v10 = 0x70020100,
7171 CPU_POWERPC_750GX_v11 = 0x70020101,
7172 CPU_POWERPC_750GX_v12 = 0x70020102,
7173#define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
bd928eba
JM		 7174 CPU_POWERPC_750L_v20 = 0x00088200,
7175 CPU_POWERPC_750L_v21 = 0x00088201,
80d11f44
JM		 7176 CPU_POWERPC_750L_v22 = 0x00088202,
7177 CPU_POWERPC_750L_v30 = 0x00088300,
7178 CPU_POWERPC_750L_v32 = 0x00088302,
a750fc0b 7179 /* PowerPC 745/755 cores */
80d11f44
JM		 7180#define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
7181 CPU_POWERPC_7x5_v10 = 0x00083100,
7182 CPU_POWERPC_7x5_v11 = 0x00083101,
7183 CPU_POWERPC_7x5_v20 = 0x00083200,
7184 CPU_POWERPC_7x5_v21 = 0x00083201,
7185 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
7186 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
7187 CPU_POWERPC_7x5_v24 = 0x00083204,
7188 CPU_POWERPC_7x5_v25 = 0x00083205,
7189 CPU_POWERPC_7x5_v26 = 0x00083206,
7190 CPU_POWERPC_7x5_v27 = 0x00083207,
7191 CPU_POWERPC_7x5_v28 = 0x00083208,
a750fc0b 7192#if 0
80d11f44 7193 CPU_POWERPC_7x5P = xxx,
a750fc0b
JM		 7194#endif
7195 /* PowerPC 74xx cores (aka G4) */
7196 /* XXX: missing 0x000C1101 */
80d11f44
JM		 7197#define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
7198 CPU_POWERPC_7400_v10 = 0x000C0100,
7199 CPU_POWERPC_7400_v11 = 0x000C0101,
7200 CPU_POWERPC_7400_v20 = 0x000C0200,
4e777442 7201 CPU_POWERPC_7400_v21 = 0x000C0201,
80d11f44
JM		 7202 CPU_POWERPC_7400_v22 = 0x000C0202,
7203 CPU_POWERPC_7400_v26 = 0x000C0206,
7204 CPU_POWERPC_7400_v27 = 0x000C0207,
7205 CPU_POWERPC_7400_v28 = 0x000C0208,
7206 CPU_POWERPC_7400_v29 = 0x000C0209,
7207#define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
7208 CPU_POWERPC_7410_v10 = 0x800C1100,
7209 CPU_POWERPC_7410_v11 = 0x800C1101,
7210 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
7211 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
7212 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
7213#define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
7214 CPU_POWERPC_7448_v10 = 0x80040100,
7215 CPU_POWERPC_7448_v11 = 0x80040101,
7216 CPU_POWERPC_7448_v20 = 0x80040200,
7217 CPU_POWERPC_7448_v21 = 0x80040201,
7218#define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
7219 CPU_POWERPC_7450_v10 = 0x80000100,
7220 CPU_POWERPC_7450_v11 = 0x80000101,
7221 CPU_POWERPC_7450_v12 = 0x80000102,
4e777442 7222 CPU_POWERPC_7450_v20 = 0x80000200, /* aka A, B, C, D: 2.04 */
80d11f44 7223 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
4e777442
JM		 7224#define CPU_POWERPC_74x1 CPU_POWERPC_74x1_v23
7225 CPU_POWERPC_74x1_v23 = 0x80000203, /* aka G: 2.3 */
7226 /* XXX: this entry might be a bug in some documentation */
7227 CPU_POWERPC_74x1_v210 = 0x80000210, /* aka G: 2.3 ? */
80d11f44
JM		 7228#define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
7229 CPU_POWERPC_74x5_v10 = 0x80010100,
c3e36823 7230 /* XXX: missing 0x80010200 */
80d11f44
JM		 7231 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
7232 CPU_POWERPC_74x5_v32 = 0x80010302,
7233 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
7234 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
7235#define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
80d11f44 7236 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
082c6681 7237 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
80d11f44 7238 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
082c6681
JM		 7239#define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
7240 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
7241 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
7242 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
a750fc0b 7243 /* 64 bits PowerPC */
00af685f 7244#if defined(TARGET_PPC64)
80d11f44
JM		 7245 CPU_POWERPC_620 = 0x00140000,
7246 CPU_POWERPC_630 = 0x00400000,
7247 CPU_POWERPC_631 = 0x00410104,
7248 CPU_POWERPC_POWER4 = 0x00350000,
7249 CPU_POWERPC_POWER4P = 0x00380000,
c3e36823 7250 /* XXX: missing 0x003A0201 */
80d11f44
JM		 7251 CPU_POWERPC_POWER5 = 0x003A0203,
7252#define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
7253 CPU_POWERPC_POWER5P = 0x003B0000,
7254#define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
7255 CPU_POWERPC_POWER6 = 0x003E0000,
7256 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
7257 CPU_POWERPC_POWER6A = 0x0F000002,
9d52e907
DG		 7258#define CPU_POWERPC_POWER7 CPU_POWERPC_POWER7_v20
7259 CPU_POWERPC_POWER7_v20 = 0x003F0200,
80d11f44
JM		 7260 CPU_POWERPC_970 = 0x00390202,
7261#define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
7262 CPU_POWERPC_970FX_v10 = 0x00391100,
7263 CPU_POWERPC_970FX_v20 = 0x003C0200,
7264 CPU_POWERPC_970FX_v21 = 0x003C0201,
7265 CPU_POWERPC_970FX_v30 = 0x003C0300,
7266 CPU_POWERPC_970FX_v31 = 0x003C0301,
7267 CPU_POWERPC_970GX = 0x00450000,
7268#define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
7269 CPU_POWERPC_970MP_v10 = 0x00440100,
7270 CPU_POWERPC_970MP_v11 = 0x00440101,
7271#define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
7272 CPU_POWERPC_CELL_v10 = 0x00700100,
7273 CPU_POWERPC_CELL_v20 = 0x00700400,
7274 CPU_POWERPC_CELL_v30 = 0x00700500,
7275 CPU_POWERPC_CELL_v31 = 0x00700501,
7276#define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
7277 CPU_POWERPC_RS64 = 0x00330000,
7278 CPU_POWERPC_RS64II = 0x00340000,
7279 CPU_POWERPC_RS64III = 0x00360000,
7280 CPU_POWERPC_RS64IV = 0x00370000,
00af685f 7281#endif /* defined(TARGET_PPC64) */
a750fc0b
JM		 7282 /* Original POWER */
7283 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
7284 * POWER2 (RIOS2) & RSC2 (P2SC) here
7285 */
7286#if 0
80d11f44 7287 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
a750fc0b
JM		 7288#endif
7289#if 0
80d11f44 7290 CPU_POWER2 = xxx, /* 0x40000 ? */
a750fc0b
JM		 7291#endif
7292 /* PA Semi core */
80d11f44 7293 CPU_POWERPC_PA6T = 0x00900000,
a750fc0b
JM		 7294};
7295
7296/* System version register (used on MPC 8xxx) */
7297enum {
80d11f44
JM		 7298 POWERPC_SVR_NONE = 0x00000000,
7299#define POWERPC_SVR_52xx POWERPC_SVR_5200
7300#define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
7301 POWERPC_SVR_5200_v10 = 0x80110010,
7302 POWERPC_SVR_5200_v11 = 0x80110011,
7303 POWERPC_SVR_5200_v12 = 0x80110012,
7304#define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
7305 POWERPC_SVR_5200B_v20 = 0x80110020,
7306 POWERPC_SVR_5200B_v21 = 0x80110021,
7307#define POWERPC_SVR_55xx POWERPC_SVR_5567
c3e36823 7308#if 0
80d11f44 7309 POWERPC_SVR_5533 = xxx,
c3e36823
JM		 7310#endif
7311#if 0
80d11f44 7312 POWERPC_SVR_5534 = xxx,
c3e36823
JM		 7313#endif
7314#if 0
80d11f44 7315 POWERPC_SVR_5553 = xxx,
c3e36823
JM		 7316#endif
7317#if 0
80d11f44 7318 POWERPC_SVR_5554 = xxx,
c3e36823
JM		 7319#endif
7320#if 0
80d11f44 7321 POWERPC_SVR_5561 = xxx,
c3e36823
JM		 7322#endif
7323#if 0
80d11f44 7324 POWERPC_SVR_5565 = xxx,
c3e36823
JM		 7325#endif
7326#if 0
80d11f44 7327 POWERPC_SVR_5566 = xxx,
c3e36823
JM		 7328#endif
7329#if 0
80d11f44 7330 POWERPC_SVR_5567 = xxx,
c3e36823
JM		 7331#endif
7332#if 0
80d11f44 7333 POWERPC_SVR_8313 = xxx,
c3e36823
JM		 7334#endif
7335#if 0
80d11f44 7336 POWERPC_SVR_8313E = xxx,
c3e36823
JM		 7337#endif
7338#if 0
80d11f44 7339 POWERPC_SVR_8314 = xxx,
c3e36823
JM		 7340#endif
7341#if 0
80d11f44 7342 POWERPC_SVR_8314E = xxx,
c3e36823
JM		 7343#endif
7344#if 0
80d11f44 7345 POWERPC_SVR_8315 = xxx,
c3e36823
JM		 7346#endif
7347#if 0
80d11f44 7348 POWERPC_SVR_8315E = xxx,
c3e36823
JM		 7349#endif
7350#if 0
80d11f44 7351 POWERPC_SVR_8321 = xxx,
c3e36823
JM		 7352#endif
7353#if 0
80d11f44 7354 POWERPC_SVR_8321E = xxx,
c3e36823
JM		 7355#endif
7356#if 0
80d11f44 7357 POWERPC_SVR_8323 = xxx,
c3e36823
JM		 7358#endif
7359#if 0
80d11f44
JM		 7360 POWERPC_SVR_8323E = xxx,
7361#endif
492d7bf5 7362 POWERPC_SVR_8343 = 0x80570010,
80d11f44 7363 POWERPC_SVR_8343A = 0x80570030,
492d7bf5 7364 POWERPC_SVR_8343E = 0x80560010,
80d11f44 7365 POWERPC_SVR_8343EA = 0x80560030,
492d7bf5
TM		 7366#define POWERPC_SVR_8347 POWERPC_SVR_8347T
7367 POWERPC_SVR_8347P = 0x80550010, /* PBGA package */
7368 POWERPC_SVR_8347T = 0x80530010, /* TBGA package */
80d11f44
JM		 7369#define POWERPC_SVR_8347A POWERPC_SVR_8347AT
7370 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
7371 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
492d7bf5
TM		 7372#define POWERPC_SVR_8347E POWERPC_SVR_8347ET
7373 POWERPC_SVR_8347EP = 0x80540010, /* PBGA package */
7374 POWERPC_SVR_8347ET = 0x80520010, /* TBGA package */
80d11f44
JM		 7375#define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
7376 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
7377 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
7378 POWERPC_SVR_8349 = 0x80510010,
7379 POWERPC_SVR_8349A = 0x80510030,
7380 POWERPC_SVR_8349E = 0x80500010,
7381 POWERPC_SVR_8349EA = 0x80500030,
c3e36823 7382#if 0
80d11f44 7383 POWERPC_SVR_8358E = xxx,
c3e36823
JM		 7384#endif
7385#if 0
80d11f44
JM		 7386 POWERPC_SVR_8360E = xxx,
7387#endif
7388#define POWERPC_SVR_E500 0x40000000
7389 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
7390 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
7391 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
7392 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
7393 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
7394 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
7395#define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
7396 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
7397 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
7398#define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
7399 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
7400 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
7401#define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
7402 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
7403 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
7404 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
7405#define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
7406 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
7407 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
7408#define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
7409 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
7410 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
7411#define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
7412 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
7413 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
7414 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
7415 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
7416#define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
7417 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
7418 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
7419 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
7420 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
7421#define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
7422 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
7423 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
7424#define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
7425 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
7426 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
7427#define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
7428 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
7429 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
7430#define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
7431 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
7432 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
7433#define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
7434 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
7435 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
7436#define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
7437 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
7438 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
7439 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
7440 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
7441#define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
7442 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
7443 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
7444 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
7445 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
7446#define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
7447 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
7448 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
7449#define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
7450 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
7451 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
7452#define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
7453 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
7454 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
7455 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
7456 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
7457 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
7458 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
7459 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
7460 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
7461 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
c3e36823 7462#if 0
80d11f44 7463 POWERPC_SVR_8610 = xxx,
c3e36823 7464#endif
80d11f44
JM		 7465 POWERPC_SVR_8641 = 0x80900021,
7466 POWERPC_SVR_8641D = 0x80900121,
a750fc0b
JM		 7467};
7468
3fc6c082 7469/*****************************************************************************/
a750fc0b 7470/* PowerPC CPU definitions */
80d11f44 7471#define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
a750fc0b 7472 { \
a5858d7a
AG		 7473 .name = _name, \
7474 .pvr = _pvr, \
7475 .svr = _svr, \
7476 .insns_flags = glue(POWERPC_INSNS_,_type), \
7477 .insns_flags2 = glue(POWERPC_INSNS2_,_type), \
7478 .msr_mask = glue(POWERPC_MSRM_,_type), \
7479 .mmu_model = glue(POWERPC_MMU_,_type), \
7480 .excp_model = glue(POWERPC_EXCP_,_type), \
7481 .bus_model = glue(POWERPC_INPUT_,_type), \
7482 .bfd_mach = glue(POWERPC_BFDM_,_type), \
7483 .flags = glue(POWERPC_FLAG_,_type), \
7484 .init_proc = &glue(init_proc_,_type), \
7485 .check_pow = &glue(check_pow_,_type), \
a750fc0b 7486 }
80d11f44
JM		 7487#define POWERPC_DEF(_name, _pvr, _type) \
7488POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
a750fc0b 7489
c227f099 7490static const ppc_def_t ppc_defs[] = {
a750fc0b
JM		 7491 /* Embedded PowerPC */
7492 /* PowerPC 401 family */
2662a059 7493 /* Generic PowerPC 401 */
80d11f44 7494 POWERPC_DEF("401", CPU_POWERPC_401, 401),
a750fc0b 7495 /* PowerPC 401 cores */
2662a059 7496 /* PowerPC 401A1 */
80d11f44 7497 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
a750fc0b 7498 /* PowerPC 401B2 */
80d11f44 7499 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
2662a059 7500#if defined (TODO)
a750fc0b 7501 /* PowerPC 401B3 */
80d11f44 7502 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
a750fc0b
JM		 7503#endif
7504 /* PowerPC 401C2 */
80d11f44 7505 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
a750fc0b 7506 /* PowerPC 401D2 */
80d11f44 7507 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
a750fc0b 7508 /* PowerPC 401E2 */
80d11f44 7509 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
a750fc0b 7510 /* PowerPC 401F2 */
80d11f44 7511 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
a750fc0b
JM		 7512 /* PowerPC 401G2 */
7513 /* XXX: to be checked */
80d11f44 7514 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
a750fc0b 7515 /* PowerPC 401 microcontrolers */
2662a059 7516#if defined (TODO)
a750fc0b 7517 /* PowerPC 401GF */
80d11f44 7518 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
3fc6c082 7519#endif
a750fc0b 7520 /* IOP480 (401 microcontroler) */
80d11f44 7521 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
a750fc0b 7522 /* IBM Processor for Network Resources */
80d11f44 7523 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
3fc6c082 7524#if defined (TODO)
80d11f44 7525 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
3fc6c082 7526#endif
a750fc0b
JM		 7527 /* PowerPC 403 family */
7528 /* Generic PowerPC 403 */
80d11f44 7529 POWERPC_DEF("403", CPU_POWERPC_403, 403),
a750fc0b
JM		 7530 /* PowerPC 403 microcontrolers */
7531 /* PowerPC 403 GA */
80d11f44 7532 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
a750fc0b 7533 /* PowerPC 403 GB */
80d11f44 7534 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
a750fc0b 7535 /* PowerPC 403 GC */
80d11f44 7536 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
a750fc0b 7537 /* PowerPC 403 GCX */
80d11f44 7538 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
3fc6c082 7539#if defined (TODO)
a750fc0b 7540 /* PowerPC 403 GP */
80d11f44 7541 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
3fc6c082 7542#endif
a750fc0b
JM		 7543 /* PowerPC 405 family */
7544 /* Generic PowerPC 405 */
80d11f44 7545 POWERPC_DEF("405", CPU_POWERPC_405, 405),
a750fc0b 7546 /* PowerPC 405 cores */
2662a059 7547#if defined (TODO)
a750fc0b 7548 /* PowerPC 405 A3 */
80d11f44 7549 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
3a607854 7550#endif
3a607854 7551#if defined (TODO)
a750fc0b 7552 /* PowerPC 405 A4 */
80d11f44 7553 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
3a607854 7554#endif
3a607854 7555#if defined (TODO)
a750fc0b 7556 /* PowerPC 405 B3 */
80d11f44 7557 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
3fc6c082
FB		 7558#endif
7559#if defined (TODO)
a750fc0b 7560 /* PowerPC 405 B4 */
80d11f44 7561 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
a750fc0b
JM		 7562#endif
7563#if defined (TODO)
7564 /* PowerPC 405 C3 */
80d11f44 7565 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
a750fc0b
JM		 7566#endif
7567#if defined (TODO)
7568 /* PowerPC 405 C4 */
80d11f44 7569 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
a750fc0b
JM		 7570#endif
7571 /* PowerPC 405 D2 */
80d11f44 7572 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
a750fc0b
JM		 7573#if defined (TODO)
7574 /* PowerPC 405 D3 */
80d11f44 7575 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
a750fc0b
JM		 7576#endif
7577 /* PowerPC 405 D4 */
80d11f44 7578 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
a750fc0b
JM		 7579#if defined (TODO)
7580 /* PowerPC 405 D5 */
80d11f44 7581 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
a750fc0b
JM		 7582#endif
7583#if defined (TODO)
7584 /* PowerPC 405 E4 */
80d11f44 7585 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
a750fc0b
JM		 7586#endif
7587#if defined (TODO)
7588 /* PowerPC 405 F4 */
80d11f44 7589 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
a750fc0b
JM		 7590#endif
7591#if defined (TODO)
7592 /* PowerPC 405 F5 */
80d11f44 7593 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
a750fc0b
JM		 7594#endif
7595#if defined (TODO)
7596 /* PowerPC 405 F6 */
80d11f44 7597 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
a750fc0b
JM		 7598#endif
7599 /* PowerPC 405 microcontrolers */
7600 /* PowerPC 405 CR */
80d11f44 7601 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
a750fc0b 7602 /* PowerPC 405 CRa */
80d11f44 7603 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
a750fc0b 7604 /* PowerPC 405 CRb */
80d11f44 7605 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
a750fc0b 7606 /* PowerPC 405 CRc */
80d11f44 7607 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
a750fc0b 7608 /* PowerPC 405 EP */
80d11f44 7609 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
a750fc0b
JM		 7610#if defined(TODO)
7611 /* PowerPC 405 EXr */
80d11f44 7612 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
a750fc0b
JM		 7613#endif
7614 /* PowerPC 405 EZ */
80d11f44 7615 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
a750fc0b
JM		 7616#if defined(TODO)
7617 /* PowerPC 405 FX */
80d11f44 7618 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
a750fc0b
JM		 7619#endif
7620 /* PowerPC 405 GP */
80d11f44 7621 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
a750fc0b 7622 /* PowerPC 405 GPa */
80d11f44 7623 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
a750fc0b 7624 /* PowerPC 405 GPb */
80d11f44 7625 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
a750fc0b 7626 /* PowerPC 405 GPc */
80d11f44 7627 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
a750fc0b 7628 /* PowerPC 405 GPd */
80d11f44 7629 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
a750fc0b 7630 /* PowerPC 405 GPe */
80d11f44 7631 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
a750fc0b 7632 /* PowerPC 405 GPR */
80d11f44 7633 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
a750fc0b
JM		 7634#if defined(TODO)
7635 /* PowerPC 405 H */
80d11f44 7636 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
a750fc0b
JM		 7637#endif
7638#if defined(TODO)
7639 /* PowerPC 405 L */
80d11f44 7640 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
a750fc0b
JM		 7641#endif
7642 /* PowerPC 405 LP */
80d11f44 7643 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
a750fc0b
JM		 7644#if defined(TODO)
7645 /* PowerPC 405 PM */
80d11f44 7646 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
a750fc0b
JM		 7647#endif
7648#if defined(TODO)
7649 /* PowerPC 405 PS */
80d11f44 7650 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
a750fc0b
JM		 7651#endif
7652#if defined(TODO)
7653 /* PowerPC 405 S */
80d11f44 7654 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
a750fc0b
JM		 7655#endif
7656 /* Npe405 H */
80d11f44 7657 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
a750fc0b 7658 /* Npe405 H2 */
80d11f44 7659 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
a750fc0b 7660 /* Npe405 L */
80d11f44 7661 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
a750fc0b 7662 /* Npe4GS3 */
80d11f44 7663 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
a750fc0b 7664#if defined (TODO)
80d11f44 7665 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
a750fc0b
JM		 7666#endif
7667#if defined (TODO)
80d11f44 7668 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
a750fc0b
JM		 7669#endif
7670#if defined (TODO)
7671 /* PowerPC LC77700 (Sanyo) */
80d11f44 7672 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
a750fc0b
JM		 7673#endif
7674 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7675#if defined (TODO)
7676 /* STB010000 */
80d11f44 7677 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
a750fc0b
JM		 7678#endif
7679#if defined (TODO)
7680 /* STB01010 */
80d11f44 7681 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
a750fc0b
JM		 7682#endif
7683#if defined (TODO)
7684 /* STB0210 */
80d11f44 7685 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
a750fc0b
JM		 7686#endif
7687 /* STB03xx */
80d11f44 7688 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
a750fc0b
JM		 7689#if defined (TODO)
7690 /* STB043x */
80d11f44 7691 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
a750fc0b
JM		 7692#endif
7693#if defined (TODO)
7694 /* STB045x */
80d11f44 7695 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
a750fc0b
JM		 7696#endif
7697 /* STB04xx */
80d11f44 7698 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
a750fc0b 7699 /* STB25xx */
80d11f44 7700 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
a750fc0b
JM		 7701#if defined (TODO)
7702 /* STB130 */
80d11f44 7703 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
a750fc0b
JM		 7704#endif
7705 /* Xilinx PowerPC 405 cores */
80d11f44
JM		 7706 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7707 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7708 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7709 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
a750fc0b
JM		 7710#if defined (TODO)
7711 /* Zarlink ZL10310 */
80d11f44 7712 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
a750fc0b
JM		 7713#endif
7714#if defined (TODO)
7715 /* Zarlink ZL10311 */
80d11f44 7716 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
a750fc0b
JM		 7717#endif
7718#if defined (TODO)
7719 /* Zarlink ZL10320 */
80d11f44 7720 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
a750fc0b
JM		 7721#endif
7722#if defined (TODO)
7723 /* Zarlink ZL10321 */
80d11f44 7724 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
a750fc0b
JM		 7725#endif
7726 /* PowerPC 440 family */
80d11f44 7727#if defined(TODO_USER_ONLY)
a750fc0b 7728 /* Generic PowerPC 440 */
80d11f44
JM		 7729 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7730#endif
a750fc0b
JM		 7731 /* PowerPC 440 cores */
7732#if defined (TODO)
7733 /* PowerPC 440 A4 */
80d11f44 7734 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
a750fc0b 7735#endif
95070372
EI		 7736 /* PowerPC 440 Xilinx 5 */
7737 POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5),
a750fc0b
JM		 7738#if defined (TODO)
7739 /* PowerPC 440 A5 */
80d11f44 7740 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
a750fc0b
JM		 7741#endif
7742#if defined (TODO)
7743 /* PowerPC 440 B4 */
80d11f44 7744 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
a750fc0b
JM		 7745#endif
7746#if defined (TODO)
7747 /* PowerPC 440 G4 */
80d11f44 7748 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
a750fc0b
JM		 7749#endif
7750#if defined (TODO)
7751 /* PowerPC 440 F5 */
80d11f44 7752 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
a750fc0b
JM		 7753#endif
7754#if defined (TODO)
7755 /* PowerPC 440 G5 */
80d11f44 7756 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
a750fc0b
JM		 7757#endif
7758#if defined (TODO)
7759 /* PowerPC 440H4 */
80d11f44 7760 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
a750fc0b
JM		 7761#endif
7762#if defined (TODO)
7763 /* PowerPC 440H6 */
80d11f44 7764 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
a750fc0b
JM		 7765#endif
7766 /* PowerPC 440 microcontrolers */
80d11f44 7767#if defined(TODO_USER_ONLY)
a750fc0b 7768 /* PowerPC 440 EP */
80d11f44
JM		 7769 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7770#endif
7771#if defined(TODO_USER_ONLY)
a750fc0b 7772 /* PowerPC 440 EPa */
80d11f44
JM		 7773 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7774#endif
7775#if defined(TODO_USER_ONLY)
a750fc0b 7776 /* PowerPC 440 EPb */
80d11f44
JM		 7777 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7778#endif
7779#if defined(TODO_USER_ONLY)
a750fc0b 7780 /* PowerPC 440 EPX */
80d11f44
JM		 7781 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7782#endif
7783#if defined(TODO_USER_ONLY)
a750fc0b 7784 /* PowerPC 440 GP */
80d11f44
JM		 7785 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7786#endif
7787#if defined(TODO_USER_ONLY)
a750fc0b 7788 /* PowerPC 440 GPb */
80d11f44
JM		 7789 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7790#endif
7791#if defined(TODO_USER_ONLY)
a750fc0b 7792 /* PowerPC 440 GPc */
80d11f44
JM		 7793 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7794#endif
7795#if defined(TODO_USER_ONLY)
a750fc0b 7796 /* PowerPC 440 GR */
80d11f44
JM		 7797 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7798#endif
7799#if defined(TODO_USER_ONLY)
a750fc0b 7800 /* PowerPC 440 GRa */
80d11f44
JM		 7801 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7802#endif
7803#if defined(TODO_USER_ONLY)
a750fc0b 7804 /* PowerPC 440 GRX */
80d11f44
JM		 7805 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7806#endif
7807#if defined(TODO_USER_ONLY)
a750fc0b 7808 /* PowerPC 440 GX */
80d11f44
JM		 7809 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7810#endif
7811#if defined(TODO_USER_ONLY)
a750fc0b 7812 /* PowerPC 440 GXa */
80d11f44
JM		 7813 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7814#endif
7815#if defined(TODO_USER_ONLY)
a750fc0b 7816 /* PowerPC 440 GXb */
80d11f44
JM		 7817 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7818#endif
7819#if defined(TODO_USER_ONLY)
a750fc0b 7820 /* PowerPC 440 GXc */
80d11f44
JM		 7821 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7822#endif
7823#if defined(TODO_USER_ONLY)
a750fc0b 7824 /* PowerPC 440 GXf */
80d11f44
JM		 7825 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7826#endif
a750fc0b
JM		 7827#if defined(TODO)
7828 /* PowerPC 440 S */
80d11f44 7829 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
a750fc0b 7830#endif
80d11f44 7831#if defined(TODO_USER_ONLY)
a750fc0b 7832 /* PowerPC 440 SP */
80d11f44
JM		 7833 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7834#endif
7835#if defined(TODO_USER_ONLY)
a750fc0b 7836 /* PowerPC 440 SP2 */
80d11f44
JM		 7837 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7838#endif
7839#if defined(TODO_USER_ONLY)
a750fc0b 7840 /* PowerPC 440 SPE */
80d11f44
JM		 7841 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7842#endif
a750fc0b
JM		 7843 /* PowerPC 460 family */
7844#if defined (TODO)
7845 /* Generic PowerPC 464 */
80d11f44 7846 POWERPC_DEF("464", CPU_POWERPC_464, 460),
a750fc0b
JM		 7847#endif
7848 /* PowerPC 464 microcontrolers */
7849#if defined (TODO)
7850 /* PowerPC 464H90 */
80d11f44 7851 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
a750fc0b
JM		 7852#endif
7853#if defined (TODO)
7854 /* PowerPC 464H90F */
80d11f44 7855 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
a750fc0b
JM		 7856#endif
7857 /* Freescale embedded PowerPC cores */
80d11f44
JM		 7858 /* MPC5xx family (aka RCPU) */
7859#if defined(TODO_USER_ONLY)
7860 /* Generic MPC5xx core */
7861 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7862#endif
7863#if defined(TODO_USER_ONLY)
7864 /* Codename for MPC5xx core */
7865 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7866#endif
7867 /* MPC5xx microcontrollers */
7868#if defined(TODO_USER_ONLY)
7869 /* MGT560 */
7870 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7871#endif
7872#if defined(TODO_USER_ONLY)
7873 /* MPC509 */
7874 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7875#endif
7876#if defined(TODO_USER_ONLY)
7877 /* MPC533 */
7878 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7879#endif
7880#if defined(TODO_USER_ONLY)
7881 /* MPC534 */
7882 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7883#endif
7884#if defined(TODO_USER_ONLY)
7885 /* MPC555 */
7886 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7887#endif
7888#if defined(TODO_USER_ONLY)
7889 /* MPC556 */
7890 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7891#endif
7892#if defined(TODO_USER_ONLY)
7893 /* MPC560 */
7894 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7895#endif
7896#if defined(TODO_USER_ONLY)
7897 /* MPC561 */
7898 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7899#endif
7900#if defined(TODO_USER_ONLY)
7901 /* MPC562 */
7902 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7903#endif
7904#if defined(TODO_USER_ONLY)
7905 /* MPC563 */
7906 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7907#endif
7908#if defined(TODO_USER_ONLY)
7909 /* MPC564 */
7910 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7911#endif
7912#if defined(TODO_USER_ONLY)
7913 /* MPC565 */
7914 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7915#endif
7916#if defined(TODO_USER_ONLY)
7917 /* MPC566 */
7918 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7919#endif
7920 /* MPC8xx family (aka PowerQUICC) */
7921#if defined(TODO_USER_ONLY)
7922 /* Generic MPC8xx core */
7923 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7924#endif
7925#if defined(TODO_USER_ONLY)
7926 /* Codename for MPC8xx core */
7927 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7928#endif
7929 /* MPC8xx microcontrollers */
7930#if defined(TODO_USER_ONLY)
7931 /* MGT823 */
7932 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7933#endif
7934#if defined(TODO_USER_ONLY)
7935 /* MPC821 */
7936 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7937#endif
7938#if defined(TODO_USER_ONLY)
7939 /* MPC823 */
7940 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7941#endif
7942#if defined(TODO_USER_ONLY)
7943 /* MPC850 */
7944 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7945#endif
7946#if defined(TODO_USER_ONLY)
7947 /* MPC852T */
7948 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7949#endif
7950#if defined(TODO_USER_ONLY)
7951 /* MPC855T */
7952 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7953#endif
7954#if defined(TODO_USER_ONLY)
7955 /* MPC857 */
7956 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7957#endif
7958#if defined(TODO_USER_ONLY)
7959 /* MPC859 */
7960 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7961#endif
7962#if defined(TODO_USER_ONLY)
7963 /* MPC860 */
7964 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
7965#endif
7966#if defined(TODO_USER_ONLY)
7967 /* MPC862 */
7968 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
7969#endif
7970#if defined(TODO_USER_ONLY)
7971 /* MPC866 */
7972 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
7973#endif
7974#if defined(TODO_USER_ONLY)
7975 /* MPC870 */
7976 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
7977#endif
7978#if defined(TODO_USER_ONLY)
7979 /* MPC875 */
7980 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
7981#endif
7982#if defined(TODO_USER_ONLY)
7983 /* MPC880 */
7984 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
7985#endif
7986#if defined(TODO_USER_ONLY)
7987 /* MPC885 */
7988 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
7989#endif
7990 /* MPC82xx family (aka PowerQUICC-II) */
7991 /* Generic MPC52xx core */
7992 POWERPC_DEF_SVR("MPC52xx",
7993 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
7994 /* Generic MPC82xx core */
7995 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
7996 /* Codename for MPC82xx */
7997 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
7998 /* PowerPC G2 core */
7999 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
8000 /* PowerPC G2 H4 core */
8001 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
8002 /* PowerPC G2 GP core */
8003 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
8004 /* PowerPC G2 LS core */
8005 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
8006 /* PowerPC G2 HiP3 core */
8007 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
8008 /* PowerPC G2 HiP4 core */
8009 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
8010 /* PowerPC MPC603 core */
8011 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
8012 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
8013 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
8014 /* PowerPC G2LE GP core */
8015 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
8016 /* PowerPC G2LE LS core */
8017 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
8018 /* PowerPC G2LE GP1 core */
8019 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
8020 /* PowerPC G2LE GP3 core */
8021 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
8022 /* PowerPC MPC603 microcontrollers */
8023 /* MPC8240 */
8024 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
8025 /* PowerPC G2 microcontrollers */
082c6681 8026#if defined(TODO)
80d11f44
JM		 8027 /* MPC5121 */
8028 POWERPC_DEF_SVR("MPC5121",
8029 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
8030#endif
8031 /* MPC5200 */
8032 POWERPC_DEF_SVR("MPC5200",
8033 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
8034 /* MPC5200 v1.0 */
8035 POWERPC_DEF_SVR("MPC5200_v10",
8036 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
8037 /* MPC5200 v1.1 */
8038 POWERPC_DEF_SVR("MPC5200_v11",
8039 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
8040 /* MPC5200 v1.2 */
8041 POWERPC_DEF_SVR("MPC5200_v12",
8042 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
8043 /* MPC5200B */
8044 POWERPC_DEF_SVR("MPC5200B",
8045 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
8046 /* MPC5200B v2.0 */
8047 POWERPC_DEF_SVR("MPC5200B_v20",
8048 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
8049 /* MPC5200B v2.1 */
8050 POWERPC_DEF_SVR("MPC5200B_v21",
8051 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
8052 /* MPC8241 */
8053 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
8054 /* MPC8245 */
8055 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
8056 /* MPC8247 */
8057 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
8058 /* MPC8248 */
8059 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
8060 /* MPC8250 */
8061 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
8062 /* MPC8250 HiP3 */
8063 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
8064 /* MPC8250 HiP4 */
8065 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
8066 /* MPC8255 */
8067 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
8068 /* MPC8255 HiP3 */
8069 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
8070 /* MPC8255 HiP4 */
8071 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
8072 /* MPC8260 */
8073 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
8074 /* MPC8260 HiP3 */
8075 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
8076 /* MPC8260 HiP4 */
8077 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
8078 /* MPC8264 */
8079 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
8080 /* MPC8264 HiP3 */
8081 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
8082 /* MPC8264 HiP4 */
8083 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
8084 /* MPC8265 */
8085 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
8086 /* MPC8265 HiP3 */
8087 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
8088 /* MPC8265 HiP4 */
8089 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
8090 /* MPC8266 */
8091 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
8092 /* MPC8266 HiP3 */
8093 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
8094 /* MPC8266 HiP4 */
8095 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
8096 /* MPC8270 */
8097 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
8098 /* MPC8271 */
8099 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
8100 /* MPC8272 */
8101 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
8102 /* MPC8275 */
8103 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
8104 /* MPC8280 */
8105 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
a750fc0b 8106 /* e200 family */
a750fc0b 8107 /* Generic PowerPC e200 core */
80d11f44
JM		 8108 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
8109 /* Generic MPC55xx core */
8110#if defined (TODO)
8111 POWERPC_DEF_SVR("MPC55xx",
8112 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
a750fc0b
JM		 8113#endif
8114#if defined (TODO)
80d11f44
JM		 8115 /* PowerPC e200z0 core */
8116 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
a750fc0b
JM		 8117#endif
8118#if defined (TODO)
80d11f44
JM		 8119 /* PowerPC e200z1 core */
8120 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
8121#endif
8122#if defined (TODO)
8123 /* PowerPC e200z3 core */
8124 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
8125#endif
8126 /* PowerPC e200z5 core */
8127 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
a750fc0b 8128 /* PowerPC e200z6 core */
80d11f44
JM		 8129 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
8130 /* PowerPC e200 microcontrollers */
8131#if defined (TODO)
8132 /* MPC5514E */
8133 POWERPC_DEF_SVR("MPC5514E",
8134 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
a750fc0b 8135#endif
a750fc0b 8136#if defined (TODO)
80d11f44
JM		 8137 /* MPC5514E v0 */
8138 POWERPC_DEF_SVR("MPC5514E_v0",
8139 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
a750fc0b
JM		 8140#endif
8141#if defined (TODO)
80d11f44
JM		 8142 /* MPC5514E v1 */
8143 POWERPC_DEF_SVR("MPC5514E_v1",
8144 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
a750fc0b
JM		 8145#endif
8146#if defined (TODO)
80d11f44
JM		 8147 /* MPC5514G */
8148 POWERPC_DEF_SVR("MPC5514G",
8149 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
a750fc0b
JM		 8150#endif
8151#if defined (TODO)
80d11f44
JM		 8152 /* MPC5514G v0 */
8153 POWERPC_DEF_SVR("MPC5514G_v0",
8154 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
a750fc0b 8155#endif
a750fc0b 8156#if defined (TODO)
80d11f44
JM		 8157 /* MPC5514G v1 */
8158 POWERPC_DEF_SVR("MPC5514G_v1",
8159 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
a750fc0b
JM		 8160#endif
8161#if defined (TODO)
80d11f44
JM		 8162 /* MPC5515S */
8163 POWERPC_DEF_SVR("MPC5515S",
8164 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
a750fc0b
JM		 8165#endif
8166#if defined (TODO)
80d11f44
JM		 8167 /* MPC5516E */
8168 POWERPC_DEF_SVR("MPC5516E",
8169 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
a750fc0b
JM		 8170#endif
8171#if defined (TODO)
80d11f44
JM		 8172 /* MPC5516E v0 */
8173 POWERPC_DEF_SVR("MPC5516E_v0",
8174 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
a750fc0b
JM		 8175#endif
8176#if defined (TODO)
80d11f44
JM		 8177 /* MPC5516E v1 */
8178 POWERPC_DEF_SVR("MPC5516E_v1",
8179 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
a750fc0b 8180#endif
a750fc0b 8181#if defined (TODO)
80d11f44
JM		 8182 /* MPC5516G */
8183 POWERPC_DEF_SVR("MPC5516G",
8184 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
a750fc0b 8185#endif
a750fc0b 8186#if defined (TODO)
80d11f44
JM		 8187 /* MPC5516G v0 */
8188 POWERPC_DEF_SVR("MPC5516G_v0",
8189 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
a750fc0b 8190#endif
a750fc0b 8191#if defined (TODO)
80d11f44
JM		 8192 /* MPC5516G v1 */
8193 POWERPC_DEF_SVR("MPC5516G_v1",
8194 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
a750fc0b 8195#endif
a750fc0b 8196#if defined (TODO)
80d11f44
JM		 8197 /* MPC5516S */
8198 POWERPC_DEF_SVR("MPC5516S",
8199 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
a750fc0b
JM		 8200#endif
8201#if defined (TODO)
80d11f44
JM		 8202 /* MPC5533 */
8203 POWERPC_DEF_SVR("MPC5533",
8204 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
a750fc0b
JM		 8205#endif
8206#if defined (TODO)
80d11f44
JM		 8207 /* MPC5534 */
8208 POWERPC_DEF_SVR("MPC5534",
8209 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
a750fc0b 8210#endif
80d11f44
JM		 8211#if defined (TODO)
8212 /* MPC5553 */
8213 POWERPC_DEF_SVR("MPC5553",
8214 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
8215#endif
8216#if defined (TODO)
8217 /* MPC5554 */
8218 POWERPC_DEF_SVR("MPC5554",
8219 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
8220#endif
8221#if defined (TODO)
8222 /* MPC5561 */
8223 POWERPC_DEF_SVR("MPC5561",
8224 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
8225#endif
8226#if defined (TODO)
8227 /* MPC5565 */
8228 POWERPC_DEF_SVR("MPC5565",
8229 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
8230#endif
8231#if defined (TODO)
8232 /* MPC5566 */
8233 POWERPC_DEF_SVR("MPC5566",
8234 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
8235#endif
8236#if defined (TODO)
8237 /* MPC5567 */
8238 POWERPC_DEF_SVR("MPC5567",
8239 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
8240#endif
8241 /* e300 family */
8242 /* Generic PowerPC e300 core */
8243 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
8244 /* PowerPC e300c1 core */
8245 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
8246 /* PowerPC e300c2 core */
8247 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
8248 /* PowerPC e300c3 core */
8249 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
8250 /* PowerPC e300c4 core */
8251 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
8252 /* PowerPC e300 microcontrollers */
8253#if defined (TODO)
8254 /* MPC8313 */
8255 POWERPC_DEF_SVR("MPC8313",
74d77cae 8256 CPU_POWERPC_MPC831x, POWERPC_SVR_8313, e300),
80d11f44
JM		 8257#endif
8258#if defined (TODO)
8259 /* MPC8313E */
8260 POWERPC_DEF_SVR("MPC8313E",
74d77cae 8261 CPU_POWERPC_MPC831x, POWERPC_SVR_8313E, e300),
80d11f44
JM		 8262#endif
8263#if defined (TODO)
8264 /* MPC8314 */
8265 POWERPC_DEF_SVR("MPC8314",
74d77cae 8266 CPU_POWERPC_MPC831x, POWERPC_SVR_8314, e300),
80d11f44
JM		 8267#endif
8268#if defined (TODO)
8269 /* MPC8314E */
8270 POWERPC_DEF_SVR("MPC8314E",
74d77cae 8271 CPU_POWERPC_MPC831x, POWERPC_SVR_8314E, e300),
80d11f44
JM		 8272#endif
8273#if defined (TODO)
8274 /* MPC8315 */
8275 POWERPC_DEF_SVR("MPC8315",
74d77cae 8276 CPU_POWERPC_MPC831x, POWERPC_SVR_8315, e300),
80d11f44
JM		 8277#endif
8278#if defined (TODO)
8279 /* MPC8315E */
8280 POWERPC_DEF_SVR("MPC8315E",
74d77cae 8281 CPU_POWERPC_MPC831x, POWERPC_SVR_8315E, e300),
80d11f44
JM		 8282#endif
8283#if defined (TODO)
8284 /* MPC8321 */
8285 POWERPC_DEF_SVR("MPC8321",
74d77cae 8286 CPU_POWERPC_MPC832x, POWERPC_SVR_8321, e300),
80d11f44
JM		 8287#endif
8288#if defined (TODO)
8289 /* MPC8321E */
8290 POWERPC_DEF_SVR("MPC8321E",
74d77cae 8291 CPU_POWERPC_MPC832x, POWERPC_SVR_8321E, e300),
80d11f44
JM		 8292#endif
8293#if defined (TODO)
8294 /* MPC8323 */
8295 POWERPC_DEF_SVR("MPC8323",
74d77cae 8296 CPU_POWERPC_MPC832x, POWERPC_SVR_8323, e300),
80d11f44
JM		 8297#endif
8298#if defined (TODO)
8299 /* MPC8323E */
8300 POWERPC_DEF_SVR("MPC8323E",
74d77cae 8301 CPU_POWERPC_MPC832x, POWERPC_SVR_8323E, e300),
80d11f44 8302#endif
492d7bf5
TM		 8303 /* MPC8343 */
8304 POWERPC_DEF_SVR("MPC8343",
74d77cae 8305 CPU_POWERPC_MPC834x, POWERPC_SVR_8343, e300),
80d11f44
JM		 8306 /* MPC8343A */
8307 POWERPC_DEF_SVR("MPC8343A",
74d77cae 8308 CPU_POWERPC_MPC834x, POWERPC_SVR_8343A, e300),
492d7bf5
TM		 8309 /* MPC8343E */
8310 POWERPC_DEF_SVR("MPC8343E",
74d77cae 8311 CPU_POWERPC_MPC834x, POWERPC_SVR_8343E, e300),
80d11f44
JM		 8312 /* MPC8343EA */
8313 POWERPC_DEF_SVR("MPC8343EA",
74d77cae 8314 CPU_POWERPC_MPC834x, POWERPC_SVR_8343EA, e300),
492d7bf5
TM		 8315 /* MPC8347 */
8316 POWERPC_DEF_SVR("MPC8347",
74d77cae 8317 CPU_POWERPC_MPC834x, POWERPC_SVR_8347, e300),
492d7bf5
TM		 8318 /* MPC8347T */
8319 POWERPC_DEF_SVR("MPC8347T",
74d77cae 8320 CPU_POWERPC_MPC834x, POWERPC_SVR_8347T, e300),
492d7bf5
TM		 8321 /* MPC8347P */
8322 POWERPC_DEF_SVR("MPC8347P",
74d77cae 8323 CPU_POWERPC_MPC834x, POWERPC_SVR_8347P, e300),
80d11f44
JM		 8324 /* MPC8347A */
8325 POWERPC_DEF_SVR("MPC8347A",
74d77cae 8326 CPU_POWERPC_MPC834x, POWERPC_SVR_8347A, e300),
80d11f44
JM		 8327 /* MPC8347AT */
8328 POWERPC_DEF_SVR("MPC8347AT",
74d77cae 8329 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AT, e300),
80d11f44
JM		 8330 /* MPC8347AP */
8331 POWERPC_DEF_SVR("MPC8347AP",
74d77cae 8332 CPU_POWERPC_MPC834x, POWERPC_SVR_8347AP, e300),
492d7bf5
TM		 8333 /* MPC8347E */
8334 POWERPC_DEF_SVR("MPC8347E",
74d77cae 8335 CPU_POWERPC_MPC834x, POWERPC_SVR_8347E, e300),
492d7bf5
TM		 8336 /* MPC8347ET */
8337 POWERPC_DEF_SVR("MPC8347ET",
74d77cae 8338 CPU_POWERPC_MPC834x, POWERPC_SVR_8347ET, e300),
492d7bf5
TM		 8339 /* MPC8343EP */
8340 POWERPC_DEF_SVR("MPC8347EP",
74d77cae 8341 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EP, e300),
80d11f44
JM		 8342 /* MPC8347EA */
8343 POWERPC_DEF_SVR("MPC8347EA",
74d77cae 8344 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EA, e300),
80d11f44
JM		 8345 /* MPC8347EAT */
8346 POWERPC_DEF_SVR("MPC8347EAT",
74d77cae 8347 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAT, e300),
80d11f44
JM		 8348 /* MPC8343EAP */
8349 POWERPC_DEF_SVR("MPC8347EAP",
74d77cae 8350 CPU_POWERPC_MPC834x, POWERPC_SVR_8347EAP, e300),
80d11f44
JM		 8351 /* MPC8349 */
8352 POWERPC_DEF_SVR("MPC8349",
74d77cae 8353 CPU_POWERPC_MPC834x, POWERPC_SVR_8349, e300),
80d11f44
JM		 8354 /* MPC8349A */
8355 POWERPC_DEF_SVR("MPC8349A",
74d77cae 8356 CPU_POWERPC_MPC834x, POWERPC_SVR_8349A, e300),
80d11f44
JM		 8357 /* MPC8349E */
8358 POWERPC_DEF_SVR("MPC8349E",
74d77cae 8359 CPU_POWERPC_MPC834x, POWERPC_SVR_8349E, e300),
80d11f44
JM		 8360 /* MPC8349EA */
8361 POWERPC_DEF_SVR("MPC8349EA",
74d77cae 8362 CPU_POWERPC_MPC834x, POWERPC_SVR_8349EA, e300),
80d11f44
JM		 8363#if defined (TODO)
8364 /* MPC8358E */
8365 POWERPC_DEF_SVR("MPC8358E",
74d77cae 8366 CPU_POWERPC_MPC835x, POWERPC_SVR_8358E, e300),
80d11f44
JM		 8367#endif
8368#if defined (TODO)
8369 /* MPC8360E */
8370 POWERPC_DEF_SVR("MPC8360E",
74d77cae 8371 CPU_POWERPC_MPC836x, POWERPC_SVR_8360E, e300),
80d11f44
JM		 8372#endif
8373 /* MPC8377 */
8374 POWERPC_DEF_SVR("MPC8377",
74d77cae 8375 CPU_POWERPC_MPC837x, POWERPC_SVR_8377, e300),
80d11f44
JM		 8376 /* MPC8377E */
8377 POWERPC_DEF_SVR("MPC8377E",
74d77cae 8378 CPU_POWERPC_MPC837x, POWERPC_SVR_8377E, e300),
80d11f44
JM		 8379 /* MPC8378 */
8380 POWERPC_DEF_SVR("MPC8378",
74d77cae 8381 CPU_POWERPC_MPC837x, POWERPC_SVR_8378, e300),
80d11f44
JM		 8382 /* MPC8378E */
8383 POWERPC_DEF_SVR("MPC8378E",
74d77cae 8384 CPU_POWERPC_MPC837x, POWERPC_SVR_8378E, e300),
80d11f44
JM		 8385 /* MPC8379 */
8386 POWERPC_DEF_SVR("MPC8379",
74d77cae 8387 CPU_POWERPC_MPC837x, POWERPC_SVR_8379, e300),
80d11f44
JM		 8388 /* MPC8379E */
8389 POWERPC_DEF_SVR("MPC8379E",
74d77cae 8390 CPU_POWERPC_MPC837x, POWERPC_SVR_8379E, e300),
80d11f44
JM		 8391 /* e500 family */
8392 /* PowerPC e500 core */
bd5ea513
AJ		 8393 POWERPC_DEF("e500", CPU_POWERPC_e500v2_v22, e500v2),
8394 /* PowerPC e500v1 core */
8395 POWERPC_DEF("e500v1", CPU_POWERPC_e500v1, e500v1),
80d11f44 8396 /* PowerPC e500 v1.0 core */
bd5ea513 8397 POWERPC_DEF("e500_v10", CPU_POWERPC_e500v1_v10, e500v1),
80d11f44 8398 /* PowerPC e500 v2.0 core */
bd5ea513 8399 POWERPC_DEF("e500_v20", CPU_POWERPC_e500v1_v20, e500v1),
80d11f44 8400 /* PowerPC e500v2 core */
bd5ea513 8401 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500v2),
80d11f44 8402 /* PowerPC e500v2 v1.0 core */
bd5ea513 8403 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500v2),
80d11f44 8404 /* PowerPC e500v2 v2.0 core */
bd5ea513 8405 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500v2),
80d11f44 8406 /* PowerPC e500v2 v2.1 core */
bd5ea513 8407 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500v2),
80d11f44 8408 /* PowerPC e500v2 v2.2 core */
bd5ea513 8409 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2),
80d11f44 8410 /* PowerPC e500v2 v3.0 core */
bd5ea513 8411 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2),
80d11f44
JM		 8412 /* PowerPC e500 microcontrollers */
8413 /* MPC8533 */
8414 POWERPC_DEF_SVR("MPC8533",
bd5ea513 8415 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500v2),
80d11f44
JM		 8416 /* MPC8533 v1.0 */
8417 POWERPC_DEF_SVR("MPC8533_v10",
bd5ea513 8418 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500v2),
80d11f44
JM		 8419 /* MPC8533 v1.1 */
8420 POWERPC_DEF_SVR("MPC8533_v11",
bd5ea513 8421 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500v2),
80d11f44
JM		 8422 /* MPC8533E */
8423 POWERPC_DEF_SVR("MPC8533E",
bd5ea513 8424 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500v2),
80d11f44
JM		 8425 /* MPC8533E v1.0 */
8426 POWERPC_DEF_SVR("MPC8533E_v10",
bd5ea513 8427 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500v2),
80d11f44 8428 POWERPC_DEF_SVR("MPC8533E_v11",
bd5ea513 8429 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500v2),
80d11f44
JM		 8430 /* MPC8540 */
8431 POWERPC_DEF_SVR("MPC8540",
bd5ea513 8432 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500v1),
80d11f44
JM		 8433 /* MPC8540 v1.0 */
8434 POWERPC_DEF_SVR("MPC8540_v10",
bd5ea513 8435 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500v1),
80d11f44
JM		 8436 /* MPC8540 v2.0 */
8437 POWERPC_DEF_SVR("MPC8540_v20",
bd5ea513 8438 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500v1),
80d11f44
JM		 8439 /* MPC8540 v2.1 */
8440 POWERPC_DEF_SVR("MPC8540_v21",
bd5ea513 8441 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500v1),
80d11f44
JM		 8442 /* MPC8541 */
8443 POWERPC_DEF_SVR("MPC8541",
bd5ea513 8444 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500v1),
80d11f44
JM		 8445 /* MPC8541 v1.0 */
8446 POWERPC_DEF_SVR("MPC8541_v10",
bd5ea513 8447 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500v1),
80d11f44
JM		 8448 /* MPC8541 v1.1 */
8449 POWERPC_DEF_SVR("MPC8541_v11",
bd5ea513 8450 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500v1),
80d11f44
JM		 8451 /* MPC8541E */
8452 POWERPC_DEF_SVR("MPC8541E",
bd5ea513 8453 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500v1),
80d11f44
JM		 8454 /* MPC8541E v1.0 */
8455 POWERPC_DEF_SVR("MPC8541E_v10",
bd5ea513 8456 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500v1),
80d11f44
JM		 8457 /* MPC8541E v1.1 */
8458 POWERPC_DEF_SVR("MPC8541E_v11",
bd5ea513 8459 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500v1),
80d11f44
JM		 8460 /* MPC8543 */
8461 POWERPC_DEF_SVR("MPC8543",
bd5ea513 8462 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500v2),
80d11f44
JM		 8463 /* MPC8543 v1.0 */
8464 POWERPC_DEF_SVR("MPC8543_v10",
bd5ea513 8465 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500v2),
80d11f44
JM		 8466 /* MPC8543 v1.1 */
8467 POWERPC_DEF_SVR("MPC8543_v11",
bd5ea513 8468 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500v2),
80d11f44
JM		 8469 /* MPC8543 v2.0 */
8470 POWERPC_DEF_SVR("MPC8543_v20",
bd5ea513 8471 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500v2),
80d11f44
JM		 8472 /* MPC8543 v2.1 */
8473 POWERPC_DEF_SVR("MPC8543_v21",
bd5ea513 8474 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500v2),
80d11f44
JM		 8475 /* MPC8543E */
8476 POWERPC_DEF_SVR("MPC8543E",
bd5ea513 8477 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500v2),
80d11f44
JM		 8478 /* MPC8543E v1.0 */
8479 POWERPC_DEF_SVR("MPC8543E_v10",
bd5ea513 8480 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500v2),
80d11f44
JM		 8481 /* MPC8543E v1.1 */
8482 POWERPC_DEF_SVR("MPC8543E_v11",
bd5ea513 8483 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500v2),
80d11f44
JM		 8484 /* MPC8543E v2.0 */
8485 POWERPC_DEF_SVR("MPC8543E_v20",
bd5ea513 8486 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500v2),
80d11f44
JM		 8487 /* MPC8543E v2.1 */
8488 POWERPC_DEF_SVR("MPC8543E_v21",
bd5ea513 8489 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500v2),
80d11f44
JM		 8490 /* MPC8544 */
8491 POWERPC_DEF_SVR("MPC8544",
bd5ea513 8492 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500v2),
80d11f44
JM		 8493 /* MPC8544 v1.0 */
8494 POWERPC_DEF_SVR("MPC8544_v10",
bd5ea513 8495 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500v2),
80d11f44
JM		 8496 /* MPC8544 v1.1 */
8497 POWERPC_DEF_SVR("MPC8544_v11",
bd5ea513 8498 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500v2),
80d11f44
JM		 8499 /* MPC8544E */
8500 POWERPC_DEF_SVR("MPC8544E",
bd5ea513 8501 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500v2),
80d11f44
JM		 8502 /* MPC8544E v1.0 */
8503 POWERPC_DEF_SVR("MPC8544E_v10",
bd5ea513 8504 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500v2),
80d11f44
JM		 8505 /* MPC8544E v1.1 */
8506 POWERPC_DEF_SVR("MPC8544E_v11",
bd5ea513 8507 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500v2),
80d11f44
JM		 8508 /* MPC8545 */
8509 POWERPC_DEF_SVR("MPC8545",
bd5ea513 8510 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500v2),
80d11f44
JM		 8511 /* MPC8545 v2.0 */
8512 POWERPC_DEF_SVR("MPC8545_v20",
bd5ea513 8513 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500v2),
80d11f44
JM		 8514 /* MPC8545 v2.1 */
8515 POWERPC_DEF_SVR("MPC8545_v21",
bd5ea513 8516 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500v2),
80d11f44
JM		 8517 /* MPC8545E */
8518 POWERPC_DEF_SVR("MPC8545E",
bd5ea513 8519 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500v2),
80d11f44
JM		 8520 /* MPC8545E v2.0 */
8521 POWERPC_DEF_SVR("MPC8545E_v20",
bd5ea513 8522 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500v2),
80d11f44
JM		 8523 /* MPC8545E v2.1 */
8524 POWERPC_DEF_SVR("MPC8545E_v21",
bd5ea513 8525 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500v2),
80d11f44
JM		 8526 /* MPC8547E */
8527 POWERPC_DEF_SVR("MPC8547E",
bd5ea513 8528 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500v2),
80d11f44
JM		 8529 /* MPC8547E v2.0 */
8530 POWERPC_DEF_SVR("MPC8547E_v20",
bd5ea513 8531 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500v2),
80d11f44
JM		 8532 /* MPC8547E v2.1 */
8533 POWERPC_DEF_SVR("MPC8547E_v21",
bd5ea513 8534 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500v2),
80d11f44
JM		 8535 /* MPC8548 */
8536 POWERPC_DEF_SVR("MPC8548",
bd5ea513 8537 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500v2),
80d11f44
JM		 8538 /* MPC8548 v1.0 */
8539 POWERPC_DEF_SVR("MPC8548_v10",
bd5ea513 8540 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500v2),
80d11f44
JM		 8541 /* MPC8548 v1.1 */
8542 POWERPC_DEF_SVR("MPC8548_v11",
bd5ea513 8543 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500v2),
80d11f44
JM		 8544 /* MPC8548 v2.0 */
8545 POWERPC_DEF_SVR("MPC8548_v20",
bd5ea513 8546 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500v2),
80d11f44
JM		 8547 /* MPC8548 v2.1 */
8548 POWERPC_DEF_SVR("MPC8548_v21",
bd5ea513 8549 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500v2),
80d11f44
JM		 8550 /* MPC8548E */
8551 POWERPC_DEF_SVR("MPC8548E",
bd5ea513 8552 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500v2),
80d11f44
JM		 8553 /* MPC8548E v1.0 */
8554 POWERPC_DEF_SVR("MPC8548E_v10",
bd5ea513 8555 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500v2),
80d11f44
JM		 8556 /* MPC8548E v1.1 */
8557 POWERPC_DEF_SVR("MPC8548E_v11",
bd5ea513 8558 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500v2),
80d11f44
JM		 8559 /* MPC8548E v2.0 */
8560 POWERPC_DEF_SVR("MPC8548E_v20",
bd5ea513 8561 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500v2),
80d11f44
JM		 8562 /* MPC8548E v2.1 */
8563 POWERPC_DEF_SVR("MPC8548E_v21",
bd5ea513 8564 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500v2),
80d11f44
JM		 8565 /* MPC8555 */
8566 POWERPC_DEF_SVR("MPC8555",
bd5ea513 8567 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500v2),
80d11f44
JM		 8568 /* MPC8555 v1.0 */
8569 POWERPC_DEF_SVR("MPC8555_v10",
bd5ea513 8570 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500v2),
80d11f44
JM		 8571 /* MPC8555 v1.1 */
8572 POWERPC_DEF_SVR("MPC8555_v11",
bd5ea513 8573 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500v2),
80d11f44
JM		 8574 /* MPC8555E */
8575 POWERPC_DEF_SVR("MPC8555E",
bd5ea513 8576 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500v2),
80d11f44
JM		 8577 /* MPC8555E v1.0 */
8578 POWERPC_DEF_SVR("MPC8555E_v10",
bd5ea513 8579 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500v2),
80d11f44
JM		 8580 /* MPC8555E v1.1 */
8581 POWERPC_DEF_SVR("MPC8555E_v11",
bd5ea513 8582 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500v2),
80d11f44
JM		 8583 /* MPC8560 */
8584 POWERPC_DEF_SVR("MPC8560",
bd5ea513 8585 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500v2),
80d11f44
JM		 8586 /* MPC8560 v1.0 */
8587 POWERPC_DEF_SVR("MPC8560_v10",
bd5ea513 8588 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500v2),
80d11f44
JM		 8589 /* MPC8560 v2.0 */
8590 POWERPC_DEF_SVR("MPC8560_v20",
bd5ea513 8591 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500v2),
80d11f44
JM		 8592 /* MPC8560 v2.1 */
8593 POWERPC_DEF_SVR("MPC8560_v21",
bd5ea513 8594 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500v2),
80d11f44
JM		 8595 /* MPC8567 */
8596 POWERPC_DEF_SVR("MPC8567",
bd5ea513 8597 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500v2),
80d11f44
JM		 8598 /* MPC8567E */
8599 POWERPC_DEF_SVR("MPC8567E",
bd5ea513 8600 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500v2),
80d11f44
JM		 8601 /* MPC8568 */
8602 POWERPC_DEF_SVR("MPC8568",
bd5ea513 8603 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500v2),
80d11f44
JM		 8604 /* MPC8568E */
8605 POWERPC_DEF_SVR("MPC8568E",
bd5ea513 8606 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500v2),
80d11f44
JM		 8607 /* MPC8572 */
8608 POWERPC_DEF_SVR("MPC8572",
bd5ea513 8609 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500v2),
80d11f44
JM		 8610 /* MPC8572E */
8611 POWERPC_DEF_SVR("MPC8572E",
bd5ea513 8612 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500v2),
80d11f44
JM		 8613 /* e600 family */
8614 /* PowerPC e600 core */
8615 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8616 /* PowerPC e600 microcontrollers */
8617#if defined (TODO)
8618 /* MPC8610 */
8619 POWERPC_DEF_SVR("MPC8610",
8620 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8621#endif
8622 /* MPC8641 */
8623 POWERPC_DEF_SVR("MPC8641",
8624 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8625 /* MPC8641D */
8626 POWERPC_DEF_SVR("MPC8641D",
8627 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
a750fc0b
JM		 8628 /* 32 bits "classic" PowerPC */
8629 /* PowerPC 6xx family */
8630 /* PowerPC 601 */
bd928eba 8631 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
c3e36823 8632 /* PowerPC 601v0 */
082c6681 8633 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
c3e36823 8634 /* PowerPC 601v1 */
082c6681
JM		 8635 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8636 /* PowerPC 601v */
bd928eba 8637 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
a750fc0b 8638 /* PowerPC 601v2 */
082c6681 8639 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
a750fc0b 8640 /* PowerPC 602 */
80d11f44 8641 POWERPC_DEF("602", CPU_POWERPC_602, 602),
a750fc0b 8642 /* PowerPC 603 */
80d11f44 8643 POWERPC_DEF("603", CPU_POWERPC_603, 603),
a750fc0b 8644 /* Code name for PowerPC 603 */
80d11f44 8645 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
082c6681 8646 /* PowerPC 603e (aka PID6) */
80d11f44 8647 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
a750fc0b 8648 /* Code name for PowerPC 603e */
80d11f44 8649 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
a750fc0b 8650 /* PowerPC 603e v1.1 */
80d11f44 8651 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
a750fc0b 8652 /* PowerPC 603e v1.2 */
80d11f44 8653 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
a750fc0b 8654 /* PowerPC 603e v1.3 */
80d11f44 8655 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
a750fc0b 8656 /* PowerPC 603e v1.4 */
80d11f44 8657 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
a750fc0b 8658 /* PowerPC 603e v2.2 */
80d11f44 8659 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
a750fc0b 8660 /* PowerPC 603e v3 */
80d11f44 8661 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
a750fc0b 8662 /* PowerPC 603e v4 */
80d11f44 8663 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
a750fc0b 8664 /* PowerPC 603e v4.1 */
80d11f44 8665 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
082c6681 8666 /* PowerPC 603e (aka PID7) */
80d11f44 8667 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
a750fc0b 8668 /* PowerPC 603e7t */
80d11f44 8669 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
a750fc0b 8670 /* PowerPC 603e7v */
80d11f44 8671 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
a750fc0b 8672 /* Code name for PowerPC 603ev */
80d11f44 8673 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
a750fc0b 8674 /* PowerPC 603e7v1 */
80d11f44 8675 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
a750fc0b 8676 /* PowerPC 603e7v2 */
80d11f44 8677 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
082c6681
JM		 8678 /* PowerPC 603p (aka PID7v) */
8679 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8680 /* PowerPC 603r (aka PID7t) */
80d11f44 8681 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
a750fc0b 8682 /* Code name for PowerPC 603r */
80d11f44 8683 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
a750fc0b 8684 /* PowerPC 604 */
80d11f44 8685 POWERPC_DEF("604", CPU_POWERPC_604, 604),
082c6681
JM		 8686 /* PowerPC 604e (aka PID9) */
8687 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8688 /* Code name for PowerPC 604e */
8689 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
a750fc0b 8690 /* PowerPC 604e v1.0 */
082c6681 8691 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
a750fc0b 8692 /* PowerPC 604e v2.2 */
082c6681 8693 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
a750fc0b 8694 /* PowerPC 604e v2.4 */
082c6681
JM		 8695 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8696 /* PowerPC 604r (aka PIDA) */
8697 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8698 /* Code name for PowerPC 604r */
8699 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
a750fc0b
JM		 8700#if defined(TODO)
8701 /* PowerPC 604ev */
082c6681 8702 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
a750fc0b
JM		 8703#endif
8704 /* PowerPC 7xx family */
8705 /* Generic PowerPC 740 (G3) */
bd928eba 8706 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
082c6681 8707 /* Code name for PowerPC 740 */
bd928eba 8708 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
a750fc0b 8709 /* Generic PowerPC 750 (G3) */
bd928eba 8710 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
082c6681 8711 /* Code name for PowerPC 750 */
bd928eba 8712 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
a750fc0b 8713 /* PowerPC 740/750 is also known as G3 */
bd928eba
JM		 8714 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8715 /* PowerPC 740 v1.0 (G3) */
8716 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8717 /* PowerPC 750 v1.0 (G3) */
8718 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
a750fc0b 8719 /* PowerPC 740 v2.0 (G3) */
bd928eba 8720 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
a750fc0b 8721 /* PowerPC 750 v2.0 (G3) */
bd928eba 8722 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
a750fc0b 8723 /* PowerPC 740 v2.1 (G3) */
bd928eba 8724 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
a750fc0b 8725 /* PowerPC 750 v2.1 (G3) */
bd928eba 8726 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
a750fc0b 8727 /* PowerPC 740 v2.2 (G3) */
bd928eba 8728 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
a750fc0b 8729 /* PowerPC 750 v2.2 (G3) */
bd928eba 8730 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
a750fc0b 8731 /* PowerPC 740 v3.0 (G3) */
bd928eba 8732 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
a750fc0b 8733 /* PowerPC 750 v3.0 (G3) */
bd928eba 8734 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
a750fc0b 8735 /* PowerPC 740 v3.1 (G3) */
bd928eba 8736 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
a750fc0b 8737 /* PowerPC 750 v3.1 (G3) */
bd928eba 8738 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
a750fc0b 8739 /* PowerPC 740E (G3) */
bd928eba
JM		 8740 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8741 /* PowerPC 750E (G3) */
8742 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
a750fc0b 8743 /* PowerPC 740P (G3) */
bd928eba 8744 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
a750fc0b 8745 /* PowerPC 750P (G3) */
bd928eba 8746 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
a750fc0b 8747 /* Code name for PowerPC 740P/750P (G3) */
bd928eba 8748 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
a750fc0b 8749 /* PowerPC 750CL (G3 embedded) */
bd928eba
JM		 8750 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8751 /* PowerPC 750CL v1.0 */
8752 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8753 /* PowerPC 750CL v2.0 */
8754 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
a750fc0b 8755 /* PowerPC 750CX (G3 embedded) */
bd928eba
JM		 8756 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8757 /* PowerPC 750CX v1.0 (G3 embedded) */
8758 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8759 /* PowerPC 750CX v2.1 (G3 embedded) */
8760 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
a750fc0b 8761 /* PowerPC 750CX v2.1 (G3 embedded) */
bd928eba 8762 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
a750fc0b 8763 /* PowerPC 750CX v2.2 (G3 embedded) */
bd928eba 8764 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
a750fc0b 8765 /* PowerPC 750CXe (G3 embedded) */
bd928eba 8766 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
a750fc0b 8767 /* PowerPC 750CXe v2.1 (G3 embedded) */
bd928eba 8768 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
a750fc0b 8769 /* PowerPC 750CXe v2.2 (G3 embedded) */
bd928eba 8770 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
a750fc0b 8771 /* PowerPC 750CXe v2.3 (G3 embedded) */
bd928eba 8772 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
a750fc0b 8773 /* PowerPC 750CXe v2.4 (G3 embedded) */
bd928eba 8774 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
a750fc0b 8775 /* PowerPC 750CXe v2.4b (G3 embedded) */
bd928eba
JM		 8776 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8777 /* PowerPC 750CXe v3.0 (G3 embedded) */
8778 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
a750fc0b 8779 /* PowerPC 750CXe v3.1 (G3 embedded) */
bd928eba 8780 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
a750fc0b 8781 /* PowerPC 750CXe v3.1b (G3 embedded) */
bd928eba 8782 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
a750fc0b 8783 /* PowerPC 750CXr (G3 embedded) */
bd928eba 8784 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
a750fc0b 8785 /* PowerPC 750FL (G3 embedded) */
80d11f44 8786 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
a750fc0b 8787 /* PowerPC 750FX (G3 embedded) */
80d11f44 8788 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
a750fc0b 8789 /* PowerPC 750FX v1.0 (G3 embedded) */
80d11f44 8790 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
a750fc0b 8791 /* PowerPC 750FX v2.0 (G3 embedded) */
80d11f44 8792 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
a750fc0b 8793 /* PowerPC 750FX v2.1 (G3 embedded) */
80d11f44 8794 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
a750fc0b 8795 /* PowerPC 750FX v2.2 (G3 embedded) */
80d11f44 8796 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
a750fc0b 8797 /* PowerPC 750FX v2.3 (G3 embedded) */
80d11f44 8798 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
a750fc0b 8799 /* PowerPC 750GL (G3 embedded) */
bd928eba 8800 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
a750fc0b 8801 /* PowerPC 750GX (G3 embedded) */
bd928eba 8802 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
a750fc0b 8803 /* PowerPC 750GX v1.0 (G3 embedded) */
bd928eba 8804 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
a750fc0b 8805 /* PowerPC 750GX v1.1 (G3 embedded) */
bd928eba 8806 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
a750fc0b 8807 /* PowerPC 750GX v1.2 (G3 embedded) */
bd928eba 8808 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
a750fc0b 8809 /* PowerPC 750L (G3 embedded) */
bd928eba 8810 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
a750fc0b 8811 /* Code name for PowerPC 750L (G3 embedded) */
bd928eba
JM		 8812 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8813 /* PowerPC 750L v2.0 (G3 embedded) */
8814 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8815 /* PowerPC 750L v2.1 (G3 embedded) */
8816 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
a750fc0b 8817 /* PowerPC 750L v2.2 (G3 embedded) */
bd928eba 8818 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
a750fc0b 8819 /* PowerPC 750L v3.0 (G3 embedded) */
bd928eba 8820 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
a750fc0b 8821 /* PowerPC 750L v3.2 (G3 embedded) */
bd928eba 8822 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
a750fc0b 8823 /* Generic PowerPC 745 */
bd928eba 8824 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
a750fc0b 8825 /* Generic PowerPC 755 */
bd928eba 8826 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
a750fc0b 8827 /* Code name for PowerPC 745/755 */
bd928eba 8828 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
a750fc0b 8829 /* PowerPC 745 v1.0 */
bd928eba 8830 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
a750fc0b 8831 /* PowerPC 755 v1.0 */
bd928eba 8832 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
a750fc0b 8833 /* PowerPC 745 v1.1 */
bd928eba 8834 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
a750fc0b 8835 /* PowerPC 755 v1.1 */
bd928eba 8836 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
a750fc0b 8837 /* PowerPC 745 v2.0 */
bd928eba 8838 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
a750fc0b 8839 /* PowerPC 755 v2.0 */
bd928eba 8840 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
a750fc0b 8841 /* PowerPC 745 v2.1 */
bd928eba 8842 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
a750fc0b 8843 /* PowerPC 755 v2.1 */
bd928eba 8844 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
a750fc0b 8845 /* PowerPC 745 v2.2 */
bd928eba 8846 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
a750fc0b 8847 /* PowerPC 755 v2.2 */
bd928eba 8848 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
a750fc0b 8849 /* PowerPC 745 v2.3 */
bd928eba 8850 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
a750fc0b 8851 /* PowerPC 755 v2.3 */
bd928eba 8852 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
a750fc0b 8853 /* PowerPC 745 v2.4 */
bd928eba 8854 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
a750fc0b 8855 /* PowerPC 755 v2.4 */
bd928eba 8856 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
a750fc0b 8857 /* PowerPC 745 v2.5 */
bd928eba 8858 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
a750fc0b 8859 /* PowerPC 755 v2.5 */
bd928eba 8860 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
a750fc0b 8861 /* PowerPC 745 v2.6 */
bd928eba 8862 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
a750fc0b 8863 /* PowerPC 755 v2.6 */
bd928eba 8864 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
a750fc0b 8865 /* PowerPC 745 v2.7 */
bd928eba 8866 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
a750fc0b 8867 /* PowerPC 755 v2.7 */
bd928eba 8868 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
a750fc0b 8869 /* PowerPC 745 v2.8 */
bd928eba 8870 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
a750fc0b 8871 /* PowerPC 755 v2.8 */
bd928eba 8872 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
a750fc0b
JM		 8873#if defined (TODO)
8874 /* PowerPC 745P (G3) */
bd928eba 8875 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
a750fc0b 8876 /* PowerPC 755P (G3) */
bd928eba 8877 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
a750fc0b
JM		 8878#endif
8879 /* PowerPC 74xx family */
8880 /* PowerPC 7400 (G4) */
80d11f44 8881 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
a750fc0b 8882 /* Code name for PowerPC 7400 */
80d11f44 8883 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
a750fc0b 8884 /* PowerPC 74xx is also well known as G4 */
80d11f44 8885 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
a750fc0b 8886 /* PowerPC 7400 v1.0 (G4) */
80d11f44 8887 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
a750fc0b 8888 /* PowerPC 7400 v1.1 (G4) */
80d11f44 8889 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
a750fc0b 8890 /* PowerPC 7400 v2.0 (G4) */
80d11f44 8891 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
4e777442
JM		 8892 /* PowerPC 7400 v2.1 (G4) */
8893 POWERPC_DEF("7400_v2.1", CPU_POWERPC_7400_v21, 7400),
a750fc0b 8894 /* PowerPC 7400 v2.2 (G4) */
80d11f44 8895 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
a750fc0b 8896 /* PowerPC 7400 v2.6 (G4) */
80d11f44 8897 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
a750fc0b 8898 /* PowerPC 7400 v2.7 (G4) */
80d11f44 8899 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
a750fc0b 8900 /* PowerPC 7400 v2.8 (G4) */
80d11f44 8901 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
a750fc0b 8902 /* PowerPC 7400 v2.9 (G4) */
80d11f44 8903 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
a750fc0b 8904 /* PowerPC 7410 (G4) */
80d11f44 8905 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
a750fc0b 8906 /* Code name for PowerPC 7410 */
80d11f44 8907 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
a750fc0b 8908 /* PowerPC 7410 v1.0 (G4) */
80d11f44 8909 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
a750fc0b 8910 /* PowerPC 7410 v1.1 (G4) */
80d11f44 8911 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
a750fc0b 8912 /* PowerPC 7410 v1.2 (G4) */
80d11f44 8913 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
a750fc0b 8914 /* PowerPC 7410 v1.3 (G4) */
80d11f44 8915 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
a750fc0b 8916 /* PowerPC 7410 v1.4 (G4) */
80d11f44 8917 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
a750fc0b 8918 /* PowerPC 7448 (G4) */
80d11f44 8919 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
a750fc0b 8920 /* PowerPC 7448 v1.0 (G4) */
80d11f44 8921 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
a750fc0b 8922 /* PowerPC 7448 v1.1 (G4) */
80d11f44 8923 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
a750fc0b 8924 /* PowerPC 7448 v2.0 (G4) */
80d11f44 8925 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
a750fc0b 8926 /* PowerPC 7448 v2.1 (G4) */
80d11f44 8927 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
a750fc0b 8928 /* PowerPC 7450 (G4) */
80d11f44 8929 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
a750fc0b 8930 /* Code name for PowerPC 7450 */
80d11f44 8931 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
a750fc0b 8932 /* PowerPC 7450 v1.0 (G4) */
80d11f44 8933 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
a750fc0b 8934 /* PowerPC 7450 v1.1 (G4) */
80d11f44 8935 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
a750fc0b 8936 /* PowerPC 7450 v1.2 (G4) */
80d11f44 8937 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
a750fc0b 8938 /* PowerPC 7450 v2.0 (G4) */
80d11f44 8939 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
a750fc0b 8940 /* PowerPC 7450 v2.1 (G4) */
80d11f44 8941 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
a750fc0b 8942 /* PowerPC 7441 (G4) */
80d11f44 8943 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
a750fc0b 8944 /* PowerPC 7451 (G4) */
80d11f44 8945 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
4e777442
JM		 8946 /* PowerPC 7441 v2.1 (G4) */
8947 POWERPC_DEF("7441_v2.1", CPU_POWERPC_7450_v21, 7440),
8948 /* PowerPC 7441 v2.3 (G4) */
8949 POWERPC_DEF("7441_v2.3", CPU_POWERPC_74x1_v23, 7440),
8950 /* PowerPC 7451 v2.3 (G4) */
8951 POWERPC_DEF("7451_v2.3", CPU_POWERPC_74x1_v23, 7450),
8952 /* PowerPC 7441 v2.10 (G4) */
8953 POWERPC_DEF("7441_v2.10", CPU_POWERPC_74x1_v210, 7440),
8954 /* PowerPC 7451 v2.10 (G4) */
8955 POWERPC_DEF("7451_v2.10", CPU_POWERPC_74x1_v210, 7450),
a750fc0b 8956 /* PowerPC 7445 (G4) */
80d11f44 8957 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
a750fc0b 8958 /* PowerPC 7455 (G4) */
80d11f44 8959 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
a750fc0b 8960 /* Code name for PowerPC 7445/7455 */
80d11f44 8961 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
a750fc0b 8962 /* PowerPC 7445 v1.0 (G4) */
80d11f44 8963 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
a750fc0b 8964 /* PowerPC 7455 v1.0 (G4) */
80d11f44 8965 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
a750fc0b 8966 /* PowerPC 7445 v2.1 (G4) */
80d11f44 8967 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
a750fc0b 8968 /* PowerPC 7455 v2.1 (G4) */
80d11f44 8969 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
a750fc0b 8970 /* PowerPC 7445 v3.2 (G4) */
80d11f44 8971 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
a750fc0b 8972 /* PowerPC 7455 v3.2 (G4) */
80d11f44 8973 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
a750fc0b 8974 /* PowerPC 7445 v3.3 (G4) */
80d11f44 8975 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
a750fc0b 8976 /* PowerPC 7455 v3.3 (G4) */
80d11f44 8977 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
a750fc0b 8978 /* PowerPC 7445 v3.4 (G4) */
80d11f44 8979 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
a750fc0b 8980 /* PowerPC 7455 v3.4 (G4) */
80d11f44 8981 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
a750fc0b 8982 /* PowerPC 7447 (G4) */
80d11f44 8983 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
a750fc0b 8984 /* PowerPC 7457 (G4) */
80d11f44 8985 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
a750fc0b 8986 /* Code name for PowerPC 7447/7457 */
80d11f44 8987 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
a750fc0b 8988 /* PowerPC 7447 v1.0 (G4) */
80d11f44 8989 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
a750fc0b 8990 /* PowerPC 7457 v1.0 (G4) */
80d11f44 8991 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
a750fc0b 8992 /* PowerPC 7447 v1.1 (G4) */
80d11f44 8993 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
a750fc0b 8994 /* PowerPC 7457 v1.1 (G4) */
80d11f44 8995 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
a750fc0b 8996 /* PowerPC 7457 v1.2 (G4) */
80d11f44 8997 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
082c6681
JM		 8998 /* PowerPC 7447A (G4) */
8999 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
9000 /* PowerPC 7457A (G4) */
9001 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
9002 /* PowerPC 7447A v1.0 (G4) */
9003 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
9004 /* PowerPC 7457A v1.0 (G4) */
9005 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
9006 /* Code name for PowerPC 7447A/7457A */
9007 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
9008 /* PowerPC 7447A v1.1 (G4) */
9009 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
9010 /* PowerPC 7457A v1.1 (G4) */
9011 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
9012 /* PowerPC 7447A v1.2 (G4) */
9013 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
9014 /* PowerPC 7457A v1.2 (G4) */
9015 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
a750fc0b
JM		 9016 /* 64 bits PowerPC */
9017#if defined (TARGET_PPC64)
a750fc0b 9018 /* PowerPC 620 */
80d11f44 9019 POWERPC_DEF("620", CPU_POWERPC_620, 620),
082c6681
JM		 9020 /* Code name for PowerPC 620 */
9021 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
3fc6c082 9022#if defined (TODO)
a750fc0b 9023 /* PowerPC 630 (POWER3) */
80d11f44
JM		 9024 POWERPC_DEF("630", CPU_POWERPC_630, 630),
9025 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
082c6681
JM		 9026 /* Code names for POWER3 */
9027 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
9028 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
a750fc0b 9029#endif
3a607854 9030#if defined (TODO)
a750fc0b 9031 /* PowerPC 631 (Power 3+) */
80d11f44
JM		 9032 POWERPC_DEF("631", CPU_POWERPC_631, 631),
9033 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
3a607854
JM		 9034#endif
9035#if defined (TODO)
a750fc0b 9036 /* POWER4 */
80d11f44 9037 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
a750fc0b 9038#endif
3a607854 9039#if defined (TODO)
a750fc0b 9040 /* POWER4p */
80d11f44 9041 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
a750fc0b 9042#endif
2662a059 9043#if defined (TODO)
a750fc0b 9044 /* POWER5 */
80d11f44 9045 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
a750fc0b 9046 /* POWER5GR */
80d11f44 9047 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
2662a059 9048#endif
3a607854 9049#if defined (TODO)
a750fc0b 9050 /* POWER5+ */
80d11f44 9051 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
a750fc0b 9052 /* POWER5GS */
80d11f44 9053 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
a750fc0b 9054#endif
2662a059 9055#if defined (TODO)
a750fc0b 9056 /* POWER6 */
80d11f44 9057 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
a750fc0b 9058 /* POWER6 running in POWER5 mode */
80d11f44 9059 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
a750fc0b 9060 /* POWER6A */
80d11f44 9061 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
2662a059 9062#endif
9d52e907
DG		 9063 /* POWER7 */
9064 POWERPC_DEF("POWER7", CPU_POWERPC_POWER7, POWER7),
9065 POWERPC_DEF("POWER7_v2.0", CPU_POWERPC_POWER7_v20, POWER7),
a750fc0b 9066 /* PowerPC 970 */
80d11f44 9067 POWERPC_DEF("970", CPU_POWERPC_970, 970),
a750fc0b 9068 /* PowerPC 970FX (G5) */
80d11f44 9069 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
a750fc0b 9070 /* PowerPC 970FX v1.0 (G5) */
80d11f44 9071 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
a750fc0b 9072 /* PowerPC 970FX v2.0 (G5) */
80d11f44 9073 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
a750fc0b 9074 /* PowerPC 970FX v2.1 (G5) */
80d11f44 9075 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
a750fc0b 9076 /* PowerPC 970FX v3.0 (G5) */
80d11f44 9077 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
a750fc0b 9078 /* PowerPC 970FX v3.1 (G5) */
80d11f44 9079 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
a750fc0b 9080 /* PowerPC 970GX (G5) */
80d11f44 9081 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
a750fc0b 9082 /* PowerPC 970MP */
80d11f44 9083 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
a750fc0b 9084 /* PowerPC 970MP v1.0 */
80d11f44 9085 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
a750fc0b 9086 /* PowerPC 970MP v1.1 */
80d11f44 9087 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
3a607854 9088#if defined (TODO)
a750fc0b 9089 /* PowerPC Cell */
80d11f44 9090 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
2662a059
JM		 9091#endif
9092#if defined (TODO)
a750fc0b 9093 /* PowerPC Cell v1.0 */
80d11f44 9094 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
2662a059
JM		 9095#endif
9096#if defined (TODO)
a750fc0b 9097 /* PowerPC Cell v2.0 */
80d11f44 9098 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
2662a059
JM		 9099#endif
9100#if defined (TODO)
a750fc0b 9101 /* PowerPC Cell v3.0 */
80d11f44 9102 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
3a607854 9103#endif
3a607854 9104#if defined (TODO)
a750fc0b 9105 /* PowerPC Cell v3.1 */
80d11f44 9106 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
2662a059
JM		 9107#endif
9108#if defined (TODO)
a750fc0b 9109 /* PowerPC Cell v3.2 */
80d11f44 9110 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
2662a059
JM		 9111#endif
9112#if defined (TODO)
a750fc0b
JM		 9113 /* RS64 (Apache/A35) */
9114 /* This one seems to support the whole POWER2 instruction set
9115 * and the PowerPC 64 one.
9116 */
9117 /* What about A10 & A30 ? */
80d11f44
JM		 9118 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
9119 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
9120 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
3a607854
JM		 9121#endif
9122#if defined (TODO)
a750fc0b 9123 /* RS64-II (NorthStar/A50) */
80d11f44
JM		 9124 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
9125 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
9126 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
3a607854
JM		 9127#endif
9128#if defined (TODO)
a750fc0b 9129 /* RS64-III (Pulsar) */
80d11f44
JM		 9130 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
9131 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
2662a059
JM		 9132#endif
9133#if defined (TODO)
a750fc0b 9134 /* RS64-IV (IceStar/IStar/SStar) */
80d11f44
JM		 9135 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
9136 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
9137 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
9138 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
3a607854 9139#endif
a750fc0b
JM		 9140#endif /* defined (TARGET_PPC64) */
9141 /* POWER */
3fc6c082 9142#if defined (TODO)
a750fc0b 9143 /* Original POWER */
80d11f44
JM		 9144 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
9145 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
9146 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
9147 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
9148 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
76a66253
JM		 9149#endif
9150#if defined (TODO)
a750fc0b 9151 /* POWER2 */
80d11f44
JM		 9152 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
9153 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
9154 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
a750fc0b
JM		 9155#endif
9156 /* PA semi cores */
9157#if defined (TODO)
9158 /* PA PA6T */
80d11f44 9159 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
a750fc0b
JM		 9160#endif
9161 /* Generic PowerPCs */
9162#if defined (TARGET_PPC64)
80d11f44 9163 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
a750fc0b 9164#endif
80d11f44
JM		 9165 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
9166 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b 9167 /* Fallback */
80d11f44 9168 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
a750fc0b
JM		 9169};
9170
9171/*****************************************************************************/
60b14d95 9172/* Generic CPU instantiation routine */
c227f099 9173static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9174{
9175#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 9176 int i;
9177
a750fc0b 9178 env->irq_inputs = NULL;
e1833e1f
JM		 9179 /* Set all exception vectors to an invalid address */
9180 for (i = 0; i < POWERPC_EXCP_NB; i++)
9181 env->excp_vectors[i] = (target_ulong)(-1ULL);
fc1c67bc 9182 env->hreset_excp_prefix = 0x00000000;
e1833e1f
JM		 9183 env->ivor_mask = 0x00000000;
9184 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 9185 /* Default MMU definitions */
9186 env->nb_BATs = 0;
9187 env->nb_tlb = 0;
9188 env->nb_ways = 0;
f2e63a42 9189#endif
a750fc0b
JM		 9190 /* Register SPR common to all PowerPC implementations */
9191 gen_spr_generic(env);
9192 spr_register(env, SPR_PVR, "PVR",
a139aa17
NF		 9193 /* Linux permits userspace to read PVR */
9194#if defined(CONFIG_LINUX_USER)
9195 &spr_read_generic,
9196#else
9197 SPR_NOACCESS,
9198#endif
9199 SPR_NOACCESS,
a750fc0b
JM		 9200 &spr_read_generic, SPR_NOACCESS,
9201 def->pvr);
80d11f44
JM		 9202 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
9203 if (def->svr != POWERPC_SVR_NONE) {
9204 if (def->svr & POWERPC_SVR_E500) {
9205 spr_register(env, SPR_E500_SVR, "SVR",
9206 SPR_NOACCESS, SPR_NOACCESS,
9207 &spr_read_generic, SPR_NOACCESS,
9208 def->svr & ~POWERPC_SVR_E500);
9209 } else {
9210 spr_register(env, SPR_SVR, "SVR",
9211 SPR_NOACCESS, SPR_NOACCESS,
9212 &spr_read_generic, SPR_NOACCESS,
9213 def->svr);
9214 }
9215 }
a750fc0b
JM		 9216 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
9217 (*def->init_proc)(env);
fc1c67bc
BS		 9218#if !defined(CONFIG_USER_ONLY)
9219 env->excp_prefix = env->hreset_excp_prefix;
9220#endif
25ba3a68
JM		 9221 /* MSR bits & flags consistency checks */
9222 if (env->msr_mask & (1 << 25)) {
9223 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9224 case POWERPC_FLAG_SPE:
9225 case POWERPC_FLAG_VRE:
9226 break;
9227 default:
9228 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9229 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
9230 exit(1);
9231 }
9232 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
9233 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9234 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
9235 exit(1);
9236 }
9237 if (env->msr_mask & (1 << 17)) {
9238 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9239 case POWERPC_FLAG_TGPR:
9240 case POWERPC_FLAG_CE:
9241 break;
9242 default:
9243 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9244 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
9245 exit(1);
9246 }
9247 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
9248 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9249 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
9250 exit(1);
9251 }
9252 if (env->msr_mask & (1 << 10)) {
9253 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9254 POWERPC_FLAG_UBLE)) {
9255 case POWERPC_FLAG_SE:
9256 case POWERPC_FLAG_DWE:
9257 case POWERPC_FLAG_UBLE:
9258 break;
9259 default:
9260 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9261 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
9262 "POWERPC_FLAG_UBLE\n");
9263 exit(1);
9264 }
9265 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
9266 POWERPC_FLAG_UBLE)) {
9267 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9268 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
9269 "POWERPC_FLAG_UBLE\n");
9270 exit(1);
9271 }
9272 if (env->msr_mask & (1 << 9)) {
9273 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9274 case POWERPC_FLAG_BE:
9275 case POWERPC_FLAG_DE:
9276 break;
9277 default:
9278 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9279 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
9280 exit(1);
9281 }
9282 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
9283 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9284 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
9285 exit(1);
9286 }
9287 if (env->msr_mask & (1 << 2)) {
9288 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9289 case POWERPC_FLAG_PX:
9290 case POWERPC_FLAG_PMM:
9291 break;
9292 default:
9293 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9294 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
9295 exit(1);
9296 }
9297 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
9298 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
9299 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
9300 exit(1);
9301 }
4018bae9
JM		 9302 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
9303 fprintf(stderr, "PowerPC flags inconsistency\n"
9304 "Should define the time-base and decrementer clock source\n");
9305 exit(1);
9306 }
a750fc0b 9307 /* Allocate TLBs buffer when needed */
f2e63a42 9308#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9309 if (env->nb_tlb != 0) {
9310 int nb_tlb = env->nb_tlb;
9311 if (env->id_tlbs != 0)
9312 nb_tlb *= 2;
c227f099 9313 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
a750fc0b
JM		 9314 /* Pre-compute some useful values */
9315 env->tlb_per_way = env->nb_tlb / env->nb_ways;
9316 }
a750fc0b
JM		 9317 if (env->irq_inputs == NULL) {
9318 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
9319 " Attempt Qemu to crash very soon !\n");
9320 }
9321#endif
2f462816
JM		 9322 if (env->check_pow == NULL) {
9323 fprintf(stderr, "WARNING: no power management check handler "
9324 "registered.\n"
9325 " Attempt Qemu to crash very soon !\n");
9326 }
a750fc0b
JM		 9327}
9328
9329#if defined(PPC_DUMP_CPU)
9330static void dump_ppc_sprs (CPUPPCState *env)
9331{
9332 ppc_spr_t *spr;
9333#if !defined(CONFIG_USER_ONLY)
9334 uint32_t sr, sw;
9335#endif
9336 uint32_t ur, uw;
9337 int i, j, n;
9338
9339 printf("Special purpose registers:\n");
9340 for (i = 0; i < 32; i++) {
9341 for (j = 0; j < 32; j++) {
9342 n = (i << 5) | j;
9343 spr = &env->spr_cb[n];
9344 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
9345 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
9346#if !defined(CONFIG_USER_ONLY)
9347 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
9348 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
9349 if (sw || sr || uw || ur) {
9350 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
9351 (i << 5) | j, (i << 5) | j, spr->name,
9352 sw ? 'w' : '-', sr ? 'r' : '-',
9353 uw ? 'w' : '-', ur ? 'r' : '-');
9354 }
9355#else
9356 if (uw || ur) {
9357 printf("SPR: %4d (%03x) %-8s u%c%c\n",
9358 (i << 5) | j, (i << 5) | j, spr->name,
9359 uw ? 'w' : '-', ur ? 'r' : '-');
9360 }
9361#endif
9362 }
9363 }
9364 fflush(stdout);
9365 fflush(stderr);
9366}
9367#endif
9368
9369/*****************************************************************************/
9370#include <stdlib.h>
9371#include <string.h>
9372
a750fc0b
JM		 9373/* Opcode types */
9374enum {
9375 PPC_DIRECT = 0, /* Opcode routine */
9376 PPC_INDIRECT = 1, /* Indirect opcode table */
9377};
9378
9379static inline int is_indirect_opcode (void *handler)
9380{
9381 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
9382}
9383
c227f099 9384static inline opc_handler_t **ind_table(void *handler)
a750fc0b 9385{
c227f099 9386 return (opc_handler_t **)((unsigned long)handler & ~3);
a750fc0b
JM		 9387}
9388
9389/* Instruction table creation */
9390/* Opcodes tables creation */
c227f099 9391static void fill_new_table (opc_handler_t **table, int len)
a750fc0b
JM		 9392{
9393 int i;
9394
9395 for (i = 0; i < len; i++)
9396 table[i] = &invalid_handler;
9397}
9398
c227f099 9399static int create_new_table (opc_handler_t **table, unsigned char idx)
a750fc0b 9400{
c227f099 9401 opc_handler_t **tmp;
a750fc0b 9402
c227f099 9403 tmp = malloc(0x20 * sizeof(opc_handler_t));
a750fc0b 9404 fill_new_table(tmp, 0x20);
c227f099 9405 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
a750fc0b
JM		 9406
9407 return 0;
9408}
9409
c227f099
AL		 9410static int insert_in_table (opc_handler_t **table, unsigned char idx,
9411 opc_handler_t *handler)
a750fc0b
JM		 9412{
9413 if (table[idx] != &invalid_handler)
9414 return -1;
9415 table[idx] = handler;
9416
9417 return 0;
9418}
9419
c227f099
AL		 9420static int register_direct_insn (opc_handler_t **ppc_opcodes,
9421 unsigned char idx, opc_handler_t *handler)
a750fc0b
JM		 9422{
9423 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9424 printf("*** ERROR: opcode %02x already assigned in main "
9425 "opcode table\n", idx);
4c1b1bfe
JM		 9426#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9427 printf(" Registered handler '%s' - new handler '%s'\n",
9428 ppc_opcodes[idx]->oname, handler->oname);
9429#endif
a750fc0b
JM		 9430 return -1;
9431 }
9432
9433 return 0;
9434}
9435
c227f099 9436static int register_ind_in_table (opc_handler_t **table,
a750fc0b 9437 unsigned char idx1, unsigned char idx2,
c227f099 9438 opc_handler_t *handler)
a750fc0b
JM		 9439{
9440 if (table[idx1] == &invalid_handler) {
9441 if (create_new_table(table, idx1) < 0) {
9442 printf("*** ERROR: unable to create indirect table "
9443 "idx=%02x\n", idx1);
9444 return -1;
9445 }
9446 } else {
9447 if (!is_indirect_opcode(table[idx1])) {
9448 printf("*** ERROR: idx %02x already assigned to a direct "
9449 "opcode\n", idx1);
4c1b1bfe
JM		 9450#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9451 printf(" Registered handler '%s' - new handler '%s'\n",
9452 ind_table(table[idx1])[idx2]->oname, handler->oname);
9453#endif
a750fc0b
JM		 9454 return -1;
9455 }
3a607854 9456 }
a750fc0b
JM		 9457 if (handler != NULL &&
9458 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9459 printf("*** ERROR: opcode %02x already assigned in "
9460 "opcode table %02x\n", idx2, idx1);
4c1b1bfe
JM		 9461#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
9462 printf(" Registered handler '%s' - new handler '%s'\n",
9463 ind_table(table[idx1])[idx2]->oname, handler->oname);
9464#endif
a750fc0b 9465 return -1;
3a607854 9466 }
a750fc0b
JM		 9467
9468 return 0;
9469}
9470
c227f099 9471static int register_ind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9472 unsigned char idx1, unsigned char idx2,
c227f099 9473 opc_handler_t *handler)
a750fc0b
JM		 9474{
9475 int ret;
9476
9477 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
9478
9479 return ret;
9480}
9481
c227f099 9482static int register_dblind_insn (opc_handler_t **ppc_opcodes,
a750fc0b 9483 unsigned char idx1, unsigned char idx2,
c227f099 9484 unsigned char idx3, opc_handler_t *handler)
a750fc0b
JM		 9485{
9486 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9487 printf("*** ERROR: unable to join indirect table idx "
9488 "[%02x-%02x]\n", idx1, idx2);
9489 return -1;
9490 }
9491 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
9492 handler) < 0) {
9493 printf("*** ERROR: unable to insert opcode "
9494 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
9495 return -1;
9496 }
9497
9498 return 0;
9499}
9500
c227f099 9501static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
a750fc0b
JM		 9502{
9503 if (insn->opc2 != 0xFF) {
9504 if (insn->opc3 != 0xFF) {
9505 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
9506 insn->opc3, &insn->handler) < 0)
9507 return -1;
9508 } else {
9509 if (register_ind_insn(ppc_opcodes, insn->opc1,
9510 insn->opc2, &insn->handler) < 0)
9511 return -1;
9512 }
9513 } else {
9514 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
9515 return -1;
9516 }
9517
9518 return 0;
9519}
9520
c227f099 9521static int test_opcode_table (opc_handler_t **table, int len)
a750fc0b
JM		 9522{
9523 int i, count, tmp;
9524
9525 for (i = 0, count = 0; i < len; i++) {
9526 /* Consistency fixup */
9527 if (table[i] == NULL)
9528 table[i] = &invalid_handler;
9529 if (table[i] != &invalid_handler) {
9530 if (is_indirect_opcode(table[i])) {
c227f099 9531 tmp = test_opcode_table(ind_table(table[i]), 0x20);
a750fc0b
JM		 9532 if (tmp == 0) {
9533 free(table[i]);
9534 table[i] = &invalid_handler;
9535 } else {
9536 count++;
9537 }
9538 } else {
9539 count++;
9540 }
9541 }
9542 }
9543
9544 return count;
9545}
9546
c227f099 9547static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
a750fc0b 9548{
c227f099 9549 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
a750fc0b
JM		 9550 printf("*** WARNING: no opcode defined !\n");
9551}
9552
9553/*****************************************************************************/
c227f099 9554static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
a750fc0b 9555{
c227f099 9556 opcode_t *opc;
a750fc0b
JM		 9557
9558 fill_new_table(env->opcodes, 0x40);
5c55ff99 9559 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
a5858d7a
AG		 9560 if (((opc->handler.type & def->insns_flags) != 0) ||
9561 ((opc->handler.type2 & def->insns_flags2) != 0)) {
a750fc0b
JM		 9562 if (register_insn(env->opcodes, opc) < 0) {
9563 printf("*** ERROR initializing PowerPC instruction "
9564 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
9565 opc->opc3);
9566 return -1;
9567 }
9568 }
9569 }
c227f099 9570 fix_opcode_tables(env->opcodes);
a750fc0b
JM		 9571 fflush(stdout);
9572 fflush(stderr);
9573
9574 return 0;
9575}
9576
9577#if defined(PPC_DUMP_CPU)
25ba3a68 9578static void dump_ppc_insns (CPUPPCState *env)
a750fc0b 9579{
c227f099 9580 opc_handler_t **table, *handler;
b55266b5 9581 const char *p, *q;
a750fc0b
JM		 9582 uint8_t opc1, opc2, opc3;
9583
9584 printf("Instructions set:\n");
9585 /* opc1 is 6 bits long */
9586 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
9587 table = env->opcodes;
9588 handler = table[opc1];
9589 if (is_indirect_opcode(handler)) {
9590 /* opc2 is 5 bits long */
9591 for (opc2 = 0; opc2 < 0x20; opc2++) {
9592 table = env->opcodes;
9593 handler = env->opcodes[opc1];
9594 table = ind_table(handler);
9595 handler = table[opc2];
9596 if (is_indirect_opcode(handler)) {
9597 table = ind_table(handler);
9598 /* opc3 is 5 bits long */
9599 for (opc3 = 0; opc3 < 0x20; opc3++) {
9600 handler = table[opc3];
9601 if (handler->handler != &gen_invalid) {
4c1b1bfe
JM		 9602 /* Special hack to properly dump SPE insns */
9603 p = strchr(handler->oname, '_');
9604 if (p == NULL) {
9605 printf("INSN: %02x %02x %02x (%02d %04d) : "
9606 "%s\n",
9607 opc1, opc2, opc3, opc1,
9608 (opc3 << 5) | opc2,
9609 handler->oname);
9610 } else {
9611 q = "speundef";
9612 if ((p - handler->oname) != strlen(q) ||
9613 memcmp(handler->oname, q, strlen(q)) != 0) {
9614 /* First instruction */
9615 printf("INSN: %02x %02x %02x (%02d %04d) : "
9616 "%.*s\n",
9617 opc1, opc2 << 1, opc3, opc1,
9618 (opc3 << 6) | (opc2 << 1),
9619 (int)(p - handler->oname),
9620 handler->oname);
9621 }
9622 if (strcmp(p + 1, q) != 0) {
9623 /* Second instruction */
9624 printf("INSN: %02x %02x %02x (%02d %04d) : "
9625 "%s\n",
9626 opc1, (opc2 << 1) | 1, opc3, opc1,
9627 (opc3 << 6) | (opc2 << 1) | 1,
9628 p + 1);
9629 }
9630 }
a750fc0b
JM		 9631 }
9632 }
9633 } else {
9634 if (handler->handler != &gen_invalid) {
9635 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9636 opc1, opc2, opc1, opc2, handler->oname);
9637 }
9638 }
9639 }
9640 } else {
9641 if (handler->handler != &gen_invalid) {
9642 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9643 opc1, opc1, handler->oname);
9644 }
9645 }
9646 }
9647}
3a607854 9648#endif
a750fc0b 9649
24951522
AJ		 9650static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9651{
9652 if (n < 32) {
9653 stfq_p(mem_buf, env->fpr[n]);
9654 return 8;
9655 }
9656 if (n == 32) {
9657 /* FPSCR not implemented */
9658 memset(mem_buf, 0, 4);
9659 return 4;
9660 }
9661 return 0;
9662}
9663
9664static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
9665{
9666 if (n < 32) {
9667 env->fpr[n] = ldfq_p(mem_buf);
9668 return 8;
9669 }
9670 if (n == 32) {
9671 /* FPSCR not implemented */
9672 return 4;
9673 }
9674 return 0;
9675}
9676
b4f8d821
AJ		 9677static int gdb_get_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9678{
9679 if (n < 32) {
e2542fe2 9680#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9681 stq_p(mem_buf, env->avr[n].u64[0]);
9682 stq_p(mem_buf+8, env->avr[n].u64[1]);
9683#else
9684 stq_p(mem_buf, env->avr[n].u64[1]);
9685 stq_p(mem_buf+8, env->avr[n].u64[0]);
9686#endif
9687 return 16;
9688 }
70976a79 9689 if (n == 32) {
b4f8d821
AJ		 9690 stl_p(mem_buf, env->vscr);
9691 return 4;
9692 }
70976a79 9693 if (n == 33) {
b4f8d821
AJ		 9694 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
9695 return 4;
9696 }
9697 return 0;
9698}
9699
9700static int gdb_set_avr_reg(CPUState *env, uint8_t *mem_buf, int n)
9701{
9702 if (n < 32) {
e2542fe2 9703#ifdef HOST_WORDS_BIGENDIAN
b4f8d821
AJ		 9704 env->avr[n].u64[0] = ldq_p(mem_buf);
9705 env->avr[n].u64[1] = ldq_p(mem_buf+8);
9706#else
9707 env->avr[n].u64[1] = ldq_p(mem_buf);
9708 env->avr[n].u64[0] = ldq_p(mem_buf+8);
9709#endif
9710 return 16;
9711 }
70976a79 9712 if (n == 32) {
b4f8d821
AJ		 9713 env->vscr = ldl_p(mem_buf);
9714 return 4;
9715 }
70976a79 9716 if (n == 33) {
b4f8d821
AJ		 9717 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
9718 return 4;
9719 }
9720 return 0;
9721}
9722
688890f7
AJ		 9723static int gdb_get_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9724{
9725 if (n < 32) {
9726#if defined(TARGET_PPC64)
9727 stl_p(mem_buf, env->gpr[n] >> 32);
9728#else
9729 stl_p(mem_buf, env->gprh[n]);
9730#endif
9731 return 4;
9732 }
70976a79 9733 if (n == 32) {
688890f7
AJ		 9734 stq_p(mem_buf, env->spe_acc);
9735 return 8;
9736 }
70976a79 9737 if (n == 33) {
d34defbc 9738 stl_p(mem_buf, env->spe_fscr);
688890f7
AJ		 9739 return 4;
9740 }
9741 return 0;
9742}
9743
9744static int gdb_set_spe_reg(CPUState *env, uint8_t *mem_buf, int n)
9745{
9746 if (n < 32) {
9747#if defined(TARGET_PPC64)
9748 target_ulong lo = (uint32_t)env->gpr[n];
9749 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
9750 env->gpr[n] = lo | hi;
9751#else
9752 env->gprh[n] = ldl_p(mem_buf);
9753#endif
9754 return 4;
9755 }
70976a79 9756 if (n == 32) {
688890f7
AJ		 9757 env->spe_acc = ldq_p(mem_buf);
9758 return 8;
9759 }
70976a79 9760 if (n == 33) {
d34defbc 9761 env->spe_fscr = ldl_p(mem_buf);
688890f7
AJ		 9762 return 4;
9763 }
9764 return 0;
9765}
9766
c227f099 9767int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
a750fc0b
JM		 9768{
9769 env->msr_mask = def->msr_mask;
9770 env->mmu_model = def->mmu_model;
9771 env->excp_model = def->excp_model;
9772 env->bus_model = def->bus_model;
c29b735c 9773 env->insns_flags = def->insns_flags;
a5858d7a 9774 env->insns_flags2 = def->insns_flags2;
d26bfc9a 9775 env->flags = def->flags;
237c0af0 9776 env->bfd_mach = def->bfd_mach;
2f462816 9777 env->check_pow = def->check_pow;
a750fc0b
JM		 9778 if (create_ppc_opcodes(env, def) < 0)
9779 return -1;
9780 init_ppc_proc(env, def);
24951522
AJ		 9781
9782 if (def->insns_flags & PPC_FLOAT) {
9783 gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
9784 33, "power-fpu.xml", 0);
9785 }
b4f8d821
AJ		 9786 if (def->insns_flags & PPC_ALTIVEC) {
9787 gdb_register_coprocessor(env, gdb_get_avr_reg, gdb_set_avr_reg,
9788 34, "power-altivec.xml", 0);
9789 }
40569b7e 9790 if (def->insns_flags & PPC_SPE) {
688890f7
AJ		 9791 gdb_register_coprocessor(env, gdb_get_spe_reg, gdb_set_spe_reg,
9792 34, "power-spe.xml", 0);
9793 }
9794
a750fc0b 9795#if defined(PPC_DUMP_CPU)
3a607854 9796 {
b55266b5 9797 const char *mmu_model, *excp_model, *bus_model;
a750fc0b
JM		 9798 switch (env->mmu_model) {
9799 case POWERPC_MMU_32B:
9800 mmu_model = "PowerPC 32";
9801 break;
a750fc0b
JM		 9802 case POWERPC_MMU_SOFT_6xx:
9803 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9804 break;
9805 case POWERPC_MMU_SOFT_74xx:
9806 mmu_model = "PowerPC 74xx with software driven TLBs";
9807 break;
9808 case POWERPC_MMU_SOFT_4xx:
9809 mmu_model = "PowerPC 4xx with software driven TLBs";
9810 break;
9811 case POWERPC_MMU_SOFT_4xx_Z:
9812 mmu_model = "PowerPC 4xx with software driven TLBs "
9813 "and zones protections";
9814 break;
b4095fed
JM		 9815 case POWERPC_MMU_REAL:
9816 mmu_model = "PowerPC real mode only";
9817 break;
9818 case POWERPC_MMU_MPC8xx:
9819 mmu_model = "PowerPC MPC8xx";
a750fc0b
JM		 9820 break;
9821 case POWERPC_MMU_BOOKE:
9822 mmu_model = "PowerPC BookE";
9823 break;
01662f3e
AG		 9824 case POWERPC_MMU_BOOKE206:
9825 mmu_model = "PowerPC BookE 2.06";
a750fc0b 9826 break;
b4095fed
JM		 9827 case POWERPC_MMU_601:
9828 mmu_model = "PowerPC 601";
9829 break;
00af685f
JM		 9830#if defined (TARGET_PPC64)
9831 case POWERPC_MMU_64B:
9832 mmu_model = "PowerPC 64";
9833 break;
add78955
JM		 9834 case POWERPC_MMU_620:
9835 mmu_model = "PowerPC 620";
9836 break;
00af685f 9837#endif
a750fc0b
JM		 9838 default:
9839 mmu_model = "Unknown or invalid";
9840 break;
9841 }
9842 switch (env->excp_model) {
9843 case POWERPC_EXCP_STD:
9844 excp_model = "PowerPC";
9845 break;
9846 case POWERPC_EXCP_40x:
9847 excp_model = "PowerPC 40x";
9848 break;
9849 case POWERPC_EXCP_601:
9850 excp_model = "PowerPC 601";
9851 break;
9852 case POWERPC_EXCP_602:
9853 excp_model = "PowerPC 602";
9854 break;
9855 case POWERPC_EXCP_603:
9856 excp_model = "PowerPC 603";
9857 break;
9858 case POWERPC_EXCP_603E:
9859 excp_model = "PowerPC 603e";
9860 break;
9861 case POWERPC_EXCP_604:
9862 excp_model = "PowerPC 604";
9863 break;
9864 case POWERPC_EXCP_7x0:
9865 excp_model = "PowerPC 740/750";
9866 break;
9867 case POWERPC_EXCP_7x5:
9868 excp_model = "PowerPC 745/755";
9869 break;
9870 case POWERPC_EXCP_74xx:
9871 excp_model = "PowerPC 74xx";
9872 break;
a750fc0b
JM		 9873 case POWERPC_EXCP_BOOKE:
9874 excp_model = "PowerPC BookE";
9875 break;
00af685f
JM		 9876#if defined (TARGET_PPC64)
9877 case POWERPC_EXCP_970:
9878 excp_model = "PowerPC 970";
9879 break;
9880#endif
a750fc0b
JM		 9881 default:
9882 excp_model = "Unknown or invalid";
9883 break;
9884 }
9885 switch (env->bus_model) {
9886 case PPC_FLAGS_INPUT_6xx:
9887 bus_model = "PowerPC 6xx";
9888 break;
9889 case PPC_FLAGS_INPUT_BookE:
9890 bus_model = "PowerPC BookE";
9891 break;
9892 case PPC_FLAGS_INPUT_405:
9893 bus_model = "PowerPC 405";
9894 break;
a750fc0b
JM		 9895 case PPC_FLAGS_INPUT_401:
9896 bus_model = "PowerPC 401/403";
9897 break;
b4095fed
JM		 9898 case PPC_FLAGS_INPUT_RCPU:
9899 bus_model = "RCPU / MPC8xx";
9900 break;
00af685f
JM		 9901#if defined (TARGET_PPC64)
9902 case PPC_FLAGS_INPUT_970:
9903 bus_model = "PowerPC 970";
9904 break;
9905#endif
a750fc0b
JM		 9906 default:
9907 bus_model = "Unknown or invalid";
9908 break;
9909 }
9910 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9911 " MMU model : %s\n",
9912 def->name, def->pvr, def->msr_mask, mmu_model);
f2e63a42 9913#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 9914 if (env->tlb != NULL) {
9915 printf(" %d %s TLB in %d ways\n",
9916 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9917 env->nb_ways);
9918 }
f2e63a42 9919#endif
a750fc0b
JM		 9920 printf(" Exceptions model : %s\n"
9921 " Bus model : %s\n",
9922 excp_model, bus_model);
25ba3a68
JM		 9923 printf(" MSR features :\n");
9924 if (env->flags & POWERPC_FLAG_SPE)
9925 printf(" signal processing engine enable"
9926 "\n");
9927 else if (env->flags & POWERPC_FLAG_VRE)
9928 printf(" vector processor enable\n");
9929 if (env->flags & POWERPC_FLAG_TGPR)
9930 printf(" temporary GPRs\n");
9931 else if (env->flags & POWERPC_FLAG_CE)
9932 printf(" critical input enable\n");
9933 if (env->flags & POWERPC_FLAG_SE)
9934 printf(" single-step trace mode\n");
9935 else if (env->flags & POWERPC_FLAG_DWE)
9936 printf(" debug wait enable\n");
9937 else if (env->flags & POWERPC_FLAG_UBLE)
9938 printf(" user BTB lock enable\n");
9939 if (env->flags & POWERPC_FLAG_BE)
9940 printf(" branch-step trace mode\n");
9941 else if (env->flags & POWERPC_FLAG_DE)
9942 printf(" debug interrupt enable\n");
9943 if (env->flags & POWERPC_FLAG_PX)
9944 printf(" inclusive protection\n");
9945 else if (env->flags & POWERPC_FLAG_PMM)
9946 printf(" performance monitor mark\n");
9947 if (env->flags == POWERPC_FLAG_NONE)
9948 printf(" none\n");
4018bae9
JM		 9949 printf(" Time-base/decrementer clock source: %s\n",
9950 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
a750fc0b
JM		 9951 }
9952 dump_ppc_insns(env);
9953 dump_ppc_sprs(env);
9954 fflush(stdout);
3a607854 9955#endif
a750fc0b
JM		 9956
9957 return 0;
9958}
3fc6c082 9959
c227f099 9960static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
3fc6c082 9961{
c227f099 9962 const ppc_def_t *ret;
ee4e83ed
JM		 9963 uint32_t pvr_rev;
9964 int i, best, match, best_match, max;
3fc6c082 9965
ee4e83ed 9966 ret = NULL;
b1503cda 9967 max = ARRAY_SIZE(ppc_defs);
ee4e83ed
JM		 9968 best = -1;
9969 pvr_rev = pvr & 0xFFFF;
9970 /* We want all specified bits to match */
9971 best_match = 32 - ctz32(pvr_rev);
068abdc8 9972 for (i = 0; i < max; i++) {
ee4e83ed
JM		 9973 /* We check that the 16 higher bits are the same to ensure the CPU
9974 * model will be the choosen one.
9975 */
9976 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9977 /* We want as much as possible of the low-level 16 bits
9978 * to be the same but we allow inexact matches.
9979 */
9980 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9981 /* We check '>=' instead of '>' because the PPC_defs table
9982 * is ordered by increasing revision.
4c1b1bfe 9983 * Then, we will match the higher revision compatible
ee4e83ed
JM		 9984 * with the requested PVR
9985 */
9986 if (match >= best_match) {
9987 best = i;
9988 best_match = match;
9989 }
3fc6c082
FB		 9990 }
9991 }
ee4e83ed
JM		 9992 if (best != -1)
9993 ret = &ppc_defs[best];
9994
9995 return ret;
3fc6c082
FB		 9996}
9997
ee4e83ed 9998#include <ctype.h>
3fc6c082 9999
c227f099 10000const ppc_def_t *cpu_ppc_find_by_name (const char *name)
ee4e83ed 10001{
c227f099 10002 const ppc_def_t *ret;
b55266b5 10003 const char *p;
ee4e83ed
JM		 10004 int i, max, len;
10005
10006 /* Check if the given name is a PVR */
10007 len = strlen(name);
10008 if (len == 10 && name[0] == '0' && name[1] == 'x') {
10009 p = name + 2;
10010 goto check_pvr;
10011 } else if (len == 8) {
10012 p = name;
10013 check_pvr:
10014 for (i = 0; i < 8; i++) {
cd390083 10015 if (!qemu_isxdigit(*p++))
ee4e83ed
JM		 10016 break;
10017 }
10018 if (i == 8)
10019 return ppc_find_by_pvr(strtoul(name, NULL, 16));
10020 }
10021 ret = NULL;
b1503cda 10022 max = ARRAY_SIZE(ppc_defs);
068abdc8 10023 for (i = 0; i < max; i++) {
ee4e83ed
JM		 10024 if (strcasecmp(name, ppc_defs[i].name) == 0) {
10025 ret = &ppc_defs[i];
10026 break;
3fc6c082
FB		 10027 }
10028 }
ee4e83ed
JM		 10029
10030 return ret;
3fc6c082
FB		 10031}
10032
9a78eead 10033void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf)
3fc6c082 10034{
068abdc8 10035 int i, max;
3fc6c082 10036
b1503cda 10037 max = ARRAY_SIZE(ppc_defs);
068abdc8 10038 for (i = 0; i < max; i++) {
a750fc0b
JM		 10039 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
10040 ppc_defs[i].name, ppc_defs[i].pvr);
3fc6c082
FB		 10041 }
10042}
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